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-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5.inc5
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch83
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch516
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch158
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch92
5 files changed, 384 insertions, 470 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5.inc b/meta-oe/recipes-devtools/gcc/gcc-4.5.inc
index d1802b5660..b23b3224b3 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.5.inc
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5.inc
@@ -14,7 +14,7 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
14 14
15 15
16PV = "4.5" 16PV = "4.5"
17PR = "r46" 17PR = "r47"
18 18
19# BINV should be incremented after updating to a revision 19# BINV should be incremented after updating to a revision
20# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made 20# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made
@@ -23,7 +23,7 @@ PR = "r46"
23# which will be next minor release and so on. 23# which will be next minor release and so on.
24 24
25BINV = "${PV}.4" 25BINV = "${PV}.4"
26SRCREV = "181733" 26SRCREV = "184907"
27BRANCH = "gcc-4_5-branch" 27BRANCH = "gcc-4_5-branch"
28PR_append = "+svnr${SRCPV}" 28PR_append = "+svnr${SRCPV}"
29 29
@@ -80,7 +80,6 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
80 file://linaro/gcc-4.5-linaro-r99344.patch \ 80 file://linaro/gcc-4.5-linaro-r99344.patch \
81 file://linaro/gcc-4.5-linaro-r99345.patch \ 81 file://linaro/gcc-4.5-linaro-r99345.patch \
82 file://linaro/gcc-4.5-linaro-r99346.patch \ 82 file://linaro/gcc-4.5-linaro-r99346.patch \
83 file://linaro/gcc-4.5-linaro-r99347.patch \
84 file://linaro/gcc-4.5-linaro-r99348.patch \ 83 file://linaro/gcc-4.5-linaro-r99348.patch \
85 file://linaro/gcc-4.5-linaro-r99349.patch \ 84 file://linaro/gcc-4.5-linaro-r99349.patch \
86 file://linaro/gcc-4.5-linaro-r99351.patch \ 85 file://linaro/gcc-4.5-linaro-r99351.patch \
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch
deleted file mode 100644
index 57b8605e55..0000000000
--- a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99347.patch
+++ /dev/null
@@ -1,83 +0,0 @@
1 Merge from Sourcery G++ 4.4:
2
3 2010-02-15 Julian Brown <julian@codesourcery.com>
4
5 Issue #7486
6
7 gcc/
8 * config/arm/arm.c (arm_libcall_uses_aapcs_base)
9 (arm_init_cumulative_args): Use correct ABI for double-precision
10 helper functions in hard-float mode if only single-precision
11 arithmetic is supported in hardware.
12
132010-07-26 Julian Brown <julian@codesourcery.com>
14
15 Backport from FSF mainline:
16
17 Julian Brown <julian@codesourcery.com>
18
19=== modified file 'gcc/config/arm/arm.c'
20--- old/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000
21+++ new/gcc/config/arm/arm.c 2010-08-13 10:43:42 +0000
22@@ -3453,6 +3453,28 @@
23 convert_optab_libfunc (sfix_optab, DImode, SFmode));
24 add_libcall (libcall_htab,
25 convert_optab_libfunc (ufix_optab, DImode, SFmode));
26+
27+ /* Values from double-precision helper functions are returned in core
28+ registers if the selected core only supports single-precision
29+ arithmetic, even if we are using the hard-float ABI. */
30+ if (TARGET_VFP)
31+ {
32+ add_libcall (libcall_htab, optab_libfunc (add_optab, DFmode));
33+ add_libcall (libcall_htab, optab_libfunc (sdiv_optab, DFmode));
34+ add_libcall (libcall_htab, optab_libfunc (smul_optab, DFmode));
35+ add_libcall (libcall_htab, optab_libfunc (neg_optab, DFmode));
36+ add_libcall (libcall_htab, optab_libfunc (sub_optab, DFmode));
37+ add_libcall (libcall_htab, optab_libfunc (eq_optab, DFmode));
38+ add_libcall (libcall_htab, optab_libfunc (lt_optab, DFmode));
39+ add_libcall (libcall_htab, optab_libfunc (le_optab, DFmode));
40+ add_libcall (libcall_htab, optab_libfunc (ge_optab, DFmode));
41+ add_libcall (libcall_htab, optab_libfunc (gt_optab, DFmode));
42+ add_libcall (libcall_htab, optab_libfunc (unord_optab, DFmode));
43+ add_libcall (libcall_htab,
44+ convert_optab_libfunc (sext_optab, DFmode, SFmode));
45+ add_libcall (libcall_htab,
46+ convert_optab_libfunc (trunc_optab, SFmode, DFmode));
47+ }
48 }
49
50 return libcall && htab_find (libcall_htab, libcall) != NULL;
51@@ -4406,6 +4428,31 @@
52 if (arm_libcall_uses_aapcs_base (libname))
53 pcum->pcs_variant = ARM_PCS_AAPCS;
54
55+ /* We must pass arguments to double-precision helper functions in core
56+ registers if we only have hardware support for single-precision
57+ arithmetic, even if we are using the hard-float ABI. */
58+ if (TARGET_VFP
59+ && (rtx_equal_p (libname, optab_libfunc (add_optab, DFmode))
60+ || rtx_equal_p (libname, optab_libfunc (sdiv_optab, DFmode))
61+ || rtx_equal_p (libname, optab_libfunc (smul_optab, DFmode))
62+ || rtx_equal_p (libname, optab_libfunc (neg_optab, DFmode))
63+ || rtx_equal_p (libname, optab_libfunc (sub_optab, DFmode))
64+ || rtx_equal_p (libname, optab_libfunc (eq_optab, DFmode))
65+ || rtx_equal_p (libname, optab_libfunc (lt_optab, DFmode))
66+ || rtx_equal_p (libname, optab_libfunc (le_optab, DFmode))
67+ || rtx_equal_p (libname, optab_libfunc (ge_optab, DFmode))
68+ || rtx_equal_p (libname, optab_libfunc (gt_optab, DFmode))
69+ || rtx_equal_p (libname, optab_libfunc (unord_optab, DFmode))
70+ || rtx_equal_p (libname, convert_optab_libfunc (sext_optab,
71+ DFmode, SFmode))
72+ || rtx_equal_p (libname, convert_optab_libfunc (trunc_optab,
73+ SFmode, DFmode))
74+ || rtx_equal_p (libname, convert_optab_libfunc (sfix_optab,
75+ SImode, DFmode))
76+ || rtx_equal_p (libname, convert_optab_libfunc (ufix_optab,
77+ SImode, DFmode))))
78+ pcum->pcs_variant = ARM_PCS_AAPCS;
79+
80 pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0;
81 pcum->aapcs_reg = NULL_RTX;
82 pcum->aapcs_partial = 0;
83
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch
index c66c11f82c..b7b6d88a04 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99380.patch
@@ -171,9 +171,11 @@
171 Backport from mainline: 171 Backport from mainline:
172 172
173=== modified file 'gcc/Makefile.in' 173=== modified file 'gcc/Makefile.in'
174--- old/gcc/Makefile.in 2010-08-10 13:31:21 +0000 174Index: gcc-4_5-branch/gcc/Makefile.in
175+++ new/gcc/Makefile.in 2010-09-01 13:29:58 +0000 175===================================================================
176@@ -3193,7 +3193,7 @@ 176--- gcc-4_5-branch.orig/gcc/Makefile.in 2012-03-06 12:11:29.000000000 -0800
177+++ gcc-4_5-branch/gcc/Makefile.in 2012-03-06 12:14:01.024439210 -0800
178@@ -3197,7 +3197,7 @@
177 ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ 179 ira-costs.o: ira-costs.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
178 hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \ 180 hard-reg-set.h $(RTL_H) $(EXPR_H) $(TM_P_H) $(FLAGS_H) $(BASIC_BLOCK_H) \
179 $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \ 181 $(REGS_H) addresses.h insn-config.h $(RECOG_H) $(TOPLEV_H) $(TARGET_H) \
@@ -182,10 +184,10 @@
182 ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ 184 ira-conflicts.o: ira-conflicts.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
183 $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \ 185 $(TARGET_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) \
184 insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \ 186 insn-config.h $(RECOG_H) $(BASIC_BLOCK_H) $(TOPLEV_H) $(TM_P_H) $(PARAMS_H) \
185 187Index: gcc-4_5-branch/gcc/basic-block.h
186=== modified file 'gcc/basic-block.h' 188===================================================================
187--- old/gcc/basic-block.h 2010-08-16 09:41:58 +0000 189--- gcc-4_5-branch.orig/gcc/basic-block.h 2012-03-06 12:11:33.000000000 -0800
188+++ new/gcc/basic-block.h 2010-09-01 13:29:58 +0000 190+++ gcc-4_5-branch/gcc/basic-block.h 2012-03-06 12:14:01.024439210 -0800
189@@ -894,6 +894,10 @@ 191@@ -894,6 +894,10 @@
190 192
191 /* In cfgcleanup.c. */ 193 /* In cfgcleanup.c. */
@@ -197,10 +199,10 @@
197 extern bool delete_unreachable_blocks (void); 199 extern bool delete_unreachable_blocks (void);
198 200
199 extern bool mark_dfs_back_edges (void); 201 extern bool mark_dfs_back_edges (void);
200 202Index: gcc-4_5-branch/gcc/cfgcleanup.c
201=== modified file 'gcc/cfgcleanup.c' 203===================================================================
202--- old/gcc/cfgcleanup.c 2010-05-17 16:26:22 +0000 204--- gcc-4_5-branch.orig/gcc/cfgcleanup.c 2012-03-06 11:53:32.000000000 -0800
203+++ new/gcc/cfgcleanup.c 2010-09-01 13:29:58 +0000 205+++ gcc-4_5-branch/gcc/cfgcleanup.c 2012-03-06 12:14:01.028439167 -0800
204@@ -68,7 +68,6 @@ 206@@ -68,7 +68,6 @@
205 static bool try_crossjump_to_edge (int, edge, edge); 207 static bool try_crossjump_to_edge (int, edge, edge);
206 static bool try_crossjump_bb (int, basic_block); 208 static bool try_crossjump_bb (int, basic_block);
@@ -209,16 +211,15 @@
209 static bool old_insns_match_p (int, rtx, rtx); 211 static bool old_insns_match_p (int, rtx, rtx);
210 212
211 static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block); 213 static void merge_blocks_move_predecessor_nojumps (basic_block, basic_block);
212@@ -972,13 +971,27 @@ 214@@ -977,13 +976,27 @@
213 be filled that clobbers a parameter expected by the subroutine. 215 be filled that clobbers a parameter expected by the subroutine.
214 216
215 ??? We take the simple route for now and assume that if they're 217 ??? We take the simple route for now and assume that if they're
216- equal, they were constructed identically. */ 218- equal, they were constructed identically. */
217- 219+ equal, they were constructed identically.
220
218- if (CALL_P (i1) 221- if (CALL_P (i1)
219- && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1), 222- && (!rtx_equal_p (CALL_INSN_FUNCTION_USAGE (i1),
220+ equal, they were constructed identically.
221+
222+ Also check for identical exception regions. */ 223+ Also check for identical exception regions. */
223+ 224+
224+ if (CALL_P (i1)) 225+ if (CALL_P (i1))
@@ -243,7 +244,7 @@
243 244
244 #ifdef STACK_REGS 245 #ifdef STACK_REGS
245 /* If cross_jump_death_matters is not 0, the insn's mode 246 /* If cross_jump_death_matters is not 0, the insn's mode
246@@ -1017,6 +1030,29 @@ 247@@ -1022,6 +1035,29 @@
247 return false; 248 return false;
248 } 249 }
249 250
@@ -273,7 +274,7 @@
273 /* Look through the insns at the end of BB1 and BB2 and find the longest 274 /* Look through the insns at the end of BB1 and BB2 and find the longest
274 sequence that are equivalent. Store the first insns for that sequence 275 sequence that are equivalent. Store the first insns for that sequence
275 in *F1 and *F2 and return the sequence length. 276 in *F1 and *F2 and return the sequence length.
276@@ -1024,9 +1060,8 @@ 277@@ -1029,9 +1065,8 @@
277 To simplify callers of this function, if the blocks match exactly, 278 To simplify callers of this function, if the blocks match exactly,
278 store the head of the blocks in *F1 and *F2. */ 279 store the head of the blocks in *F1 and *F2. */
279 280
@@ -285,7 +286,7 @@
285 { 286 {
286 rtx i1, i2, last1, last2, afterlast1, afterlast2; 287 rtx i1, i2, last1, last2, afterlast1, afterlast2;
287 int ninsns = 0; 288 int ninsns = 0;
288@@ -1066,7 +1101,7 @@ 289@@ -1071,7 +1106,7 @@
289 if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2)) 290 if (i1 == BB_HEAD (bb1) || i2 == BB_HEAD (bb2))
290 break; 291 break;
291 292
@@ -294,7 +295,7 @@
294 break; 295 break;
295 296
296 merge_memattrs (i1, i2); 297 merge_memattrs (i1, i2);
297@@ -1074,21 +1109,7 @@ 298@@ -1079,21 +1114,7 @@
298 /* Don't begin a cross-jump with a NOTE insn. */ 299 /* Don't begin a cross-jump with a NOTE insn. */
299 if (INSN_P (i1)) 300 if (INSN_P (i1))
300 { 301 {
@@ -317,7 +318,7 @@
317 318
318 afterlast1 = last1, afterlast2 = last2; 319 afterlast1 = last1, afterlast2 = last2;
319 last1 = i1, last2 = i2; 320 last1 = i1, last2 = i2;
320@@ -1130,6 +1151,97 @@ 321@@ -1135,6 +1156,97 @@
321 return ninsns; 322 return ninsns;
322 } 323 }
323 324
@@ -415,7 +416,7 @@
415 /* Return true iff outgoing edges of BB1 and BB2 match, together with 416 /* Return true iff outgoing edges of BB1 and BB2 match, together with
416 the branch instruction. This means that if we commonize the control 417 the branch instruction. This means that if we commonize the control
417 flow before end of the basic block, the semantic remains unchanged. 418 flow before end of the basic block, the semantic remains unchanged.
418@@ -1498,7 +1610,7 @@ 419@@ -1503,7 +1615,7 @@
419 return false; 420 return false;
420 421
421 /* ... and part the second. */ 422 /* ... and part the second. */
@@ -424,11 +425,11 @@
424 425
425 /* Don't proceed with the crossjump unless we found a sufficient number 426 /* Don't proceed with the crossjump unless we found a sufficient number
426 of matching instructions or the 'from' block was totally matched 427 of matching instructions or the 'from' block was totally matched
427 428Index: gcc-4_5-branch/gcc/cfgexpand.c
428=== modified file 'gcc/cfgexpand.c' 429===================================================================
429--- old/gcc/cfgexpand.c 2010-05-14 17:11:03 +0000 430--- gcc-4_5-branch.orig/gcc/cfgexpand.c 2012-03-06 11:53:32.000000000 -0800
430+++ new/gcc/cfgexpand.c 2010-09-01 13:29:58 +0000 431+++ gcc-4_5-branch/gcc/cfgexpand.c 2012-03-06 12:14:01.028439167 -0800
431@@ -3026,14 +3026,15 @@ 432@@ -3033,14 +3033,15 @@
432 if (SCALAR_INT_MODE_P (GET_MODE (op0)) 433 if (SCALAR_INT_MODE_P (GET_MODE (op0))
433 && SCALAR_INT_MODE_P (mode)) 434 && SCALAR_INT_MODE_P (mode))
434 { 435 {
@@ -448,11 +449,11 @@
448 return gen_rtx_MULT (mode, op0, op1); 449 return gen_rtx_MULT (mode, op0, op1);
449 } 450 }
450 return NULL; 451 return NULL;
451 452Index: gcc-4_5-branch/gcc/config/arm/arm.c
452=== modified file 'gcc/config/arm/arm.c' 453===================================================================
453--- old/gcc/config/arm/arm.c 2010-08-31 10:00:27 +0000 454--- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2012-03-06 12:11:35.000000000 -0800
454+++ new/gcc/config/arm/arm.c 2010-09-01 13:29:58 +0000 455+++ gcc-4_5-branch/gcc/config/arm/arm.c 2012-03-06 12:14:01.032439183 -0800
455@@ -8116,8 +8116,6 @@ 456@@ -8096,8 +8096,6 @@
456 static bool 457 static bool
457 xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) 458 xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
458 { 459 {
@@ -461,7 +462,7 @@
461 /* Some true dependencies can have a higher cost depending 462 /* Some true dependencies can have a higher cost depending
462 on precisely how certain input operands are used. */ 463 on precisely how certain input operands are used. */
463 if (REG_NOTE_KIND (link) == 0 464 if (REG_NOTE_KIND (link) == 0
464@@ -12166,6 +12164,60 @@ 465@@ -12146,6 +12144,60 @@
465 return result; 466 return result;
466 } 467 }
467 468
@@ -522,7 +523,7 @@
522 /* Gcc puts the pool in the wrong place for ARM, since we can only 523 /* Gcc puts the pool in the wrong place for ARM, since we can only
523 load addresses a limited distance around the pc. We do some 524 load addresses a limited distance around the pc. We do some
524 special munging to move the constant pool values to the correct 525 special munging to move the constant pool values to the correct
525@@ -12177,6 +12229,9 @@ 526@@ -12157,6 +12209,9 @@
526 HOST_WIDE_INT address = 0; 527 HOST_WIDE_INT address = 0;
527 Mfix * fix; 528 Mfix * fix;
528 529
@@ -532,10 +533,10 @@
532 minipool_fix_head = minipool_fix_tail = NULL; 533 minipool_fix_head = minipool_fix_tail = NULL;
533 534
534 /* The first insn must always be a note, or the code below won't 535 /* The first insn must always be a note, or the code below won't
535 536Index: gcc-4_5-branch/gcc/config/arm/arm.h
536=== modified file 'gcc/config/arm/arm.h' 537===================================================================
537--- old/gcc/config/arm/arm.h 2010-08-13 11:11:15 +0000 538--- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2012-03-06 12:11:33.000000000 -0800
538+++ new/gcc/config/arm/arm.h 2010-09-01 13:29:58 +0000 539+++ gcc-4_5-branch/gcc/config/arm/arm.h 2012-03-06 12:14:01.032439183 -0800
539@@ -1133,7 +1133,11 @@ 540@@ -1133,7 +1133,11 @@
540 } 541 }
541 542
@@ -549,10 +550,10 @@
549 550
550 /* Interrupt functions can only use registers that have already been 551 /* Interrupt functions can only use registers that have already been
551 saved by the prologue, even if they would normally be 552 saved by the prologue, even if they would normally be
552 553Index: gcc-4_5-branch/gcc/config/arm/arm.md
553=== modified file 'gcc/config/arm/arm.md' 554===================================================================
554--- old/gcc/config/arm/arm.md 2010-08-31 10:00:27 +0000 555--- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2012-03-06 12:11:35.000000000 -0800
555+++ new/gcc/config/arm/arm.md 2010-09-01 13:29:58 +0000 556+++ gcc-4_5-branch/gcc/config/arm/arm.md 2012-03-06 12:14:01.036439231 -0800
556@@ -4074,7 +4074,7 @@ 557@@ -4074,7 +4074,7 @@
557 558
558 (define_split 559 (define_split
@@ -562,10 +563,10 @@
562 "!TARGET_THUMB2 && !arm_arch6" 563 "!TARGET_THUMB2 && !arm_arch6"
563 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16))) 564 [(set (match_dup 0) (ashift:SI (match_dup 2) (const_int 16)))
564 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))] 565 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 16)))]
565 566Index: gcc-4_5-branch/gcc/config/arm/thumb2.md
566=== modified file 'gcc/config/arm/thumb2.md' 567===================================================================
567--- old/gcc/config/arm/thumb2.md 2010-08-31 10:00:27 +0000 568--- gcc-4_5-branch.orig/gcc/config/arm/thumb2.md 2012-03-06 12:11:35.000000000 -0800
568+++ new/gcc/config/arm/thumb2.md 2010-09-01 13:29:58 +0000 569+++ gcc-4_5-branch/gcc/config/arm/thumb2.md 2012-03-06 12:14:01.036439231 -0800
569@@ -1046,29 +1046,6 @@ 570@@ -1046,29 +1046,6 @@
570 }" 571 }"
571 ) 572 )
@@ -596,10 +597,10 @@
596 (define_insn "*thumb2_alusi3_short" 597 (define_insn "*thumb2_alusi3_short"
597 [(set (match_operand:SI 0 "s_register_operand" "=l") 598 [(set (match_operand:SI 0 "s_register_operand" "=l")
598 (match_operator:SI 3 "thumb_16bit_operator" 599 (match_operator:SI 3 "thumb_16bit_operator"
599 600Index: gcc-4_5-branch/gcc/config/avr/avr.h
600=== modified file 'gcc/config/avr/avr.h' 601===================================================================
601--- old/gcc/config/avr/avr.h 2010-01-11 23:12:14 +0000 602--- gcc-4_5-branch.orig/gcc/config/avr/avr.h 2012-03-06 11:53:21.000000000 -0800
602+++ new/gcc/config/avr/avr.h 2010-09-01 13:29:58 +0000 603+++ gcc-4_5-branch/gcc/config/avr/avr.h 2012-03-06 12:14:01.036439231 -0800
603@@ -232,7 +232,7 @@ 604@@ -232,7 +232,7 @@
604 32,33,34,35 \ 605 32,33,34,35 \
605 } 606 }
@@ -609,10 +610,10 @@
609 610
610 611
611 #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 612 #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
612 613Index: gcc-4_5-branch/gcc/config/i386/i386.h
613=== modified file 'gcc/config/i386/i386.h' 614===================================================================
614--- old/gcc/config/i386/i386.h 2010-04-27 19:14:19 +0000 615--- gcc-4_5-branch.orig/gcc/config/i386/i386.h 2012-03-06 11:53:19.000000000 -0800
615+++ new/gcc/config/i386/i386.h 2010-09-01 13:29:58 +0000 616+++ gcc-4_5-branch/gcc/config/i386/i386.h 2012-03-06 12:14:01.036439231 -0800
616@@ -955,7 +955,7 @@ 617@@ -955,7 +955,7 @@
617 registers listed in CALL_USED_REGISTERS, keeping the others 618 registers listed in CALL_USED_REGISTERS, keeping the others
618 available for storage of persistent values. 619 available for storage of persistent values.
@@ -636,10 +637,10 @@
636 637
637 638
638 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 639 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
639 640Index: gcc-4_5-branch/gcc/config/mips/mips.h
640=== modified file 'gcc/config/mips/mips.h' 641===================================================================
641--- old/gcc/config/mips/mips.h 2009-10-29 17:39:52 +0000 642--- gcc-4_5-branch.orig/gcc/config/mips/mips.h 2012-03-06 11:53:28.000000000 -0800
642+++ new/gcc/config/mips/mips.h 2010-09-01 13:29:58 +0000 643+++ gcc-4_5-branch/gcc/config/mips/mips.h 2012-03-06 12:14:01.040439261 -0800
643@@ -2059,12 +2059,12 @@ 644@@ -2059,12 +2059,12 @@
644 182,183,184,185,186,187 \ 645 182,183,184,185,186,187 \
645 } 646 }
@@ -655,10 +656,10 @@
655 656
656 /* True if VALUE is an unsigned 6-bit number. */ 657 /* True if VALUE is an unsigned 6-bit number. */
657 658
658 659Index: gcc-4_5-branch/gcc/config/picochip/picochip.h
659=== modified file 'gcc/config/picochip/picochip.h' 660===================================================================
660--- old/gcc/config/picochip/picochip.h 2009-11-04 11:06:36 +0000 661--- gcc-4_5-branch.orig/gcc/config/picochip/picochip.h 2012-03-06 11:53:26.000000000 -0800
661+++ new/gcc/config/picochip/picochip.h 2010-09-01 13:29:58 +0000 662+++ gcc-4_5-branch/gcc/config/picochip/picochip.h 2012-03-06 12:14:01.040439261 -0800
662@@ -261,7 +261,7 @@ 663@@ -261,7 +261,7 @@
663 /* We can dynamically change the REG_ALLOC_ORDER using the following hook. 664 /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
664 It would be desirable to change it for leaf functions so we can put 665 It would be desirable to change it for leaf functions so we can put
@@ -668,10 +669,10 @@
668 669
669 /* How Values Fit in Registers */ 670 /* How Values Fit in Registers */
670 671
671 672Index: gcc-4_5-branch/gcc/config/sparc/predicates.md
672=== modified file 'gcc/config/sparc/predicates.md' 673===================================================================
673--- old/gcc/config/sparc/predicates.md 2009-02-20 15:20:38 +0000 674--- gcc-4_5-branch.orig/gcc/config/sparc/predicates.md 2012-03-06 11:53:17.000000000 -0800
674+++ new/gcc/config/sparc/predicates.md 2010-09-01 13:29:58 +0000 675+++ gcc-4_5-branch/gcc/config/sparc/predicates.md 2012-03-06 12:14:01.040439261 -0800
675@@ -1,5 +1,5 @@ 676@@ -1,5 +1,5 @@
676 ;; Predicate definitions for SPARC. 677 ;; Predicate definitions for SPARC.
677-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc. 678-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
@@ -689,11 +690,11 @@
689- (and (match_code "mem") 690- (and (match_code "mem")
690- (and (match_operand 0 "memory_operand") 691- (and (match_operand 0 "memory_operand")
691- (match_test "REG_P (XEXP (op, 0))")))) 692- (match_test "REG_P (XEXP (op, 0))"))))
692 693Index: gcc-4_5-branch/gcc/config/sparc/sparc.h
693=== modified file 'gcc/config/sparc/sparc.h' 694===================================================================
694--- old/gcc/config/sparc/sparc.h 2010-04-02 18:54:46 +0000 695--- gcc-4_5-branch.orig/gcc/config/sparc/sparc.h 2012-03-06 11:53:17.000000000 -0800
695+++ new/gcc/config/sparc/sparc.h 2010-09-01 13:29:58 +0000 696+++ gcc-4_5-branch/gcc/config/sparc/sparc.h 2012-03-06 12:14:01.040439261 -0800
696@@ -1181,7 +1181,7 @@ 697@@ -1188,7 +1188,7 @@
697 96, 97, 98, 99, /* %fcc0-3 */ \ 698 96, 97, 98, 99, /* %fcc0-3 */ \
698 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 699 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
699 700
@@ -702,10 +703,10 @@
702 703
703 extern char sparc_leaf_regs[]; 704 extern char sparc_leaf_regs[];
704 #define LEAF_REGISTERS sparc_leaf_regs 705 #define LEAF_REGISTERS sparc_leaf_regs
705 706Index: gcc-4_5-branch/gcc/config/sparc/sync.md
706=== modified file 'gcc/config/sparc/sync.md' 707===================================================================
707--- old/gcc/config/sparc/sync.md 2009-02-20 15:20:38 +0000 708--- gcc-4_5-branch.orig/gcc/config/sparc/sync.md 2012-03-06 11:53:17.000000000 -0800
708+++ new/gcc/config/sparc/sync.md 2010-09-01 13:29:58 +0000 709+++ gcc-4_5-branch/gcc/config/sparc/sync.md 2012-03-06 12:14:01.040439261 -0800
709@@ -1,5 +1,5 @@ 710@@ -1,5 +1,5 @@
710 ;; GCC machine description for SPARC synchronization instructions. 711 ;; GCC machine description for SPARC synchronization instructions.
711-;; Copyright (C) 2005, 2007, 2009 712-;; Copyright (C) 2005, 2007, 2009
@@ -766,10 +767,10 @@
766 return "srlx\t%L3, 32, %H3"; 767 return "srlx\t%L3, 32, %H3";
767 } 768 }
768 [(set_attr "type" "multi") 769 [(set_attr "type" "multi")
769 770Index: gcc-4_5-branch/gcc/config/xtensa/xtensa.h
770=== modified file 'gcc/config/xtensa/xtensa.h' 771===================================================================
771--- old/gcc/config/xtensa/xtensa.h 2009-09-23 21:24:42 +0000 772--- gcc-4_5-branch.orig/gcc/config/xtensa/xtensa.h 2012-03-06 11:53:21.000000000 -0800
772+++ new/gcc/config/xtensa/xtensa.h 2010-09-01 13:29:58 +0000 773+++ gcc-4_5-branch/gcc/config/xtensa/xtensa.h 2012-03-06 12:14:01.040439261 -0800
773@@ -286,7 +286,7 @@ 774@@ -286,7 +286,7 @@
774 incoming argument in a2 is live throughout the function and 775 incoming argument in a2 is live throughout the function and
775 local-alloc decides to use a2, then the incoming argument must 776 local-alloc decides to use a2, then the incoming argument must
@@ -788,10 +789,10 @@
788 789
789 /* For Xtensa, the only point of this is to prevent GCC from otherwise 790 /* For Xtensa, the only point of this is to prevent GCC from otherwise
790 giving preference to call-used registers. To minimize window 791 giving preference to call-used registers. To minimize window
791 792Index: gcc-4_5-branch/gcc/doc/tm.texi
792=== modified file 'gcc/doc/tm.texi' 793===================================================================
793--- old/gcc/doc/tm.texi 2010-08-13 11:53:46 +0000 794--- gcc-4_5-branch.orig/gcc/doc/tm.texi 2012-03-06 12:11:33.000000000 -0800
794+++ new/gcc/doc/tm.texi 2010-09-01 13:29:58 +0000 795+++ gcc-4_5-branch/gcc/doc/tm.texi 2012-03-06 12:14:01.044439265 -0800
795@@ -2093,7 +2093,7 @@ 796@@ -2093,7 +2093,7 @@
796 the highest numbered allocable register first. 797 the highest numbered allocable register first.
797 @end defmac 798 @end defmac
@@ -817,11 +818,11 @@
817 @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno}) 818 @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno})
818 In some case register allocation order is not enough for the 819 In some case register allocation order is not enough for the
819 Integrated Register Allocator (@acronym{IRA}) to generate a good code. 820 Integrated Register Allocator (@acronym{IRA}) to generate a good code.
820 821Index: gcc-4_5-branch/gcc/expmed.c
821=== modified file 'gcc/expmed.c' 822===================================================================
822--- old/gcc/expmed.c 2010-03-03 22:10:17 +0000 823--- gcc-4_5-branch.orig/gcc/expmed.c 2012-03-06 11:53:32.000000000 -0800
823+++ new/gcc/expmed.c 2010-09-01 13:29:58 +0000 824+++ gcc-4_5-branch/gcc/expmed.c 2012-03-06 12:14:01.044439265 -0800
824@@ -3253,6 +3253,55 @@ 825@@ -3255,6 +3255,55 @@
825 gcc_assert (op0); 826 gcc_assert (op0);
826 return op0; 827 return op0;
827 } 828 }
@@ -877,11 +878,11 @@
877 878
878 /* Return the smallest n such that 2**n >= X. */ 879 /* Return the smallest n such that 2**n >= X. */
879 880
880 881Index: gcc-4_5-branch/gcc/expr.c
881=== modified file 'gcc/expr.c' 882===================================================================
882--- old/gcc/expr.c 2010-08-20 16:21:01 +0000 883--- gcc-4_5-branch.orig/gcc/expr.c 2012-03-06 12:11:34.000000000 -0800
883+++ new/gcc/expr.c 2010-09-01 13:29:58 +0000 884+++ gcc-4_5-branch/gcc/expr.c 2012-03-06 12:46:21.548533151 -0800
884@@ -7224,7 +7224,6 @@ 885@@ -7345,7 +7345,6 @@
885 optab this_optab; 886 optab this_optab;
886 rtx subtarget, original_target; 887 rtx subtarget, original_target;
887 int ignore; 888 int ignore;
@@ -889,7 +890,7 @@
889 bool reduce_bit_field; 890 bool reduce_bit_field;
890 gimple subexp0_def, subexp1_def; 891 gimple subexp0_def, subexp1_def;
891 tree top0, top1; 892 tree top0, top1;
892@@ -7679,13 +7678,7 @@ 893@@ -7800,13 +7799,7 @@
893 894
894 goto binop2; 895 goto binop2;
895 896
@@ -904,7 +905,7 @@
904 /* If first operand is constant, swap them. 905 /* If first operand is constant, swap them.
905 Thus the following special case checks need only 906 Thus the following special case checks need only
906 check the second operand. */ 907 check the second operand. */
907@@ -7696,96 +7689,35 @@ 908@@ -7817,96 +7810,35 @@
908 treeop1 = t1; 909 treeop1 = t1;
909 } 910 }
910 911
@@ -1015,7 +1016,7 @@
1015 enum machine_mode innermode = TYPE_MODE (op0type); 1016 enum machine_mode innermode = TYPE_MODE (op0type);
1016 bool zextend_p = TYPE_UNSIGNED (op0type); 1017 bool zextend_p = TYPE_UNSIGNED (op0type);
1017 optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab; 1018 optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
1018@@ -7795,24 +7727,22 @@ 1019@@ -7916,24 +7848,22 @@
1019 { 1020 {
1020 if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing) 1021 if (optab_handler (this_optab, mode)->insn_code != CODE_FOR_nothing)
1021 { 1022 {
@@ -1051,7 +1052,7 @@
1051 temp = expand_binop (mode, other_optab, op0, op1, target, 1052 temp = expand_binop (mode, other_optab, op0, op1, target,
1052 unsignedp, OPTAB_LIB_WIDEN); 1053 unsignedp, OPTAB_LIB_WIDEN);
1053 hipart = gen_highpart (innermode, temp); 1054 hipart = gen_highpart (innermode, temp);
1054@@ -7825,7 +7755,53 @@ 1055@@ -7946,7 +7876,53 @@
1055 } 1056 }
1056 } 1057 }
1057 } 1058 }
@@ -1106,7 +1107,7 @@
1106 return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp)); 1107 return REDUCE_BIT_FIELD (expand_mult (mode, op0, op1, target, unsignedp));
1107 1108
1108 case TRUNC_DIV_EXPR: 1109 case TRUNC_DIV_EXPR:
1109@@ -8311,6 +8287,8 @@ 1110@@ -8435,6 +8411,8 @@
1110 location_t loc = EXPR_LOCATION (exp); 1111 location_t loc = EXPR_LOCATION (exp);
1111 struct separate_ops ops; 1112 struct separate_ops ops;
1112 tree treeop0, treeop1, treeop2; 1113 tree treeop0, treeop1, treeop2;
@@ -1115,7 +1116,7 @@
1115 1116
1116 type = TREE_TYPE (exp); 1117 type = TREE_TYPE (exp);
1117 mode = TYPE_MODE (type); 1118 mode = TYPE_MODE (type);
1118@@ -8423,15 +8401,17 @@ 1119@@ -8547,15 +8525,17 @@
1119 base variable. This unnecessarily allocates a pseudo, see how we can 1120 base variable. This unnecessarily allocates a pseudo, see how we can
1120 reuse it, if partition base vars have it set already. */ 1121 reuse it, if partition base vars have it set already. */
1121 if (!currently_expanding_to_rtl) 1122 if (!currently_expanding_to_rtl)
@@ -1142,22 +1143,11 @@
1142 goto expand_decl_rtl; 1143 goto expand_decl_rtl;
1143 1144
1144 case PARM_DECL: 1145 case PARM_DECL:
1145@@ -8533,15 +8513,21 @@ 1146@@ -8669,7 +8649,15 @@
1146 /* If the mode of DECL_RTL does not match that of the decl, it
1147 must be a promoted value. We return a SUBREG of the wanted mode,
1148 but mark it so that we know that it was already extended. */
1149-
1150- if (REG_P (decl_rtl)
1151- && GET_MODE (decl_rtl) != DECL_MODE (exp))
1152+ if (REG_P (decl_rtl) && GET_MODE (decl_rtl) != DECL_MODE (exp))
1153 {
1154 enum machine_mode pmode;
1155 1147
1156- /* Get the signedness used for this variable. Ensure we get the 1148 /* Get the signedness used for this variable. Ensure we get the
1157- same mode we got when the variable was declared. */ 1149 same mode we got when the variable was declared. */
1158- pmode = promote_decl_mode (exp, &unsignedp); 1150- pmode = promote_decl_mode (exp, &unsignedp);
1159+ /* Get the signedness to be used for this variable. Ensure we get
1160+ the same mode we got when the variable was declared. */
1161+ if (code == SSA_NAME 1151+ if (code == SSA_NAME
1162+ && (g = SSA_NAME_DEF_STMT (ssa_name)) 1152+ && (g = SSA_NAME_DEF_STMT (ssa_name))
1163+ && gimple_code (g) == GIMPLE_CALL) 1153+ && gimple_code (g) == GIMPLE_CALL)
@@ -1170,11 +1160,11 @@
1170 gcc_assert (GET_MODE (decl_rtl) == pmode); 1160 gcc_assert (GET_MODE (decl_rtl) == pmode);
1171 1161
1172 temp = gen_lowpart_SUBREG (mode, decl_rtl); 1162 temp = gen_lowpart_SUBREG (mode, decl_rtl);
1173 1163Index: gcc-4_5-branch/gcc/fold-const.c
1174=== modified file 'gcc/fold-const.c' 1164===================================================================
1175--- old/gcc/fold-const.c 2010-04-06 09:36:57 +0000 1165--- gcc-4_5-branch.orig/gcc/fold-const.c 2012-03-06 11:53:32.000000000 -0800
1176+++ new/gcc/fold-const.c 2010-09-01 13:29:58 +0000 1166+++ gcc-4_5-branch/gcc/fold-const.c 2012-03-06 12:14:01.052439240 -0800
1177@@ -5741,6 +5741,76 @@ 1167@@ -5749,6 +5749,76 @@
1178 const_binop (BIT_XOR_EXPR, c, temp, 0)); 1168 const_binop (BIT_XOR_EXPR, c, temp, 0));
1179 } 1169 }
1180 1170
@@ -1251,7 +1241,7 @@
1251 /* Find ways of folding logical expressions of LHS and RHS: 1241 /* Find ways of folding logical expressions of LHS and RHS:
1252 Try to merge two comparisons to the same innermost item. 1242 Try to merge two comparisons to the same innermost item.
1253 Look for range tests like "ch >= '0' && ch <= '9'". 1243 Look for range tests like "ch >= '0' && ch <= '9'".
1254@@ -12539,6 +12609,22 @@ 1244@@ -12553,6 +12623,22 @@
1255 if (0 != (tem = fold_range_test (loc, code, type, op0, op1))) 1245 if (0 != (tem = fold_range_test (loc, code, type, op0, op1)))
1256 return tem; 1246 return tem;
1257 1247
@@ -1274,10 +1264,10 @@
1274 /* Check for the possibility of merging component references. If our 1264 /* Check for the possibility of merging component references. If our
1275 lhs is another similar operation, try to merge its rhs with our 1265 lhs is another similar operation, try to merge its rhs with our
1276 rhs. Then try to merge our lhs and rhs. */ 1266 rhs. Then try to merge our lhs and rhs. */
1277 1267Index: gcc-4_5-branch/gcc/ifcvt.c
1278=== modified file 'gcc/ifcvt.c' 1268===================================================================
1279--- old/gcc/ifcvt.c 2010-04-02 18:54:46 +0000 1269--- gcc-4_5-branch.orig/gcc/ifcvt.c 2012-03-06 11:53:32.000000000 -0800
1280+++ new/gcc/ifcvt.c 2010-09-01 13:29:58 +0000 1270+++ gcc-4_5-branch/gcc/ifcvt.c 2012-03-06 12:14:01.052439240 -0800
1281@@ -385,7 +385,11 @@ 1271@@ -385,7 +385,11 @@
1282 rtx false_expr; /* test for then block insns */ 1272 rtx false_expr; /* test for then block insns */
1283 rtx true_prob_val; /* probability of else block */ 1273 rtx true_prob_val; /* probability of else block */
@@ -1395,11 +1385,11 @@
1395 merge_if_block (ce_info); 1385 merge_if_block (ce_info);
1396 cond_exec_changed_p = TRUE; 1386 cond_exec_changed_p = TRUE;
1397 return TRUE; 1387 return TRUE;
1398 1388Index: gcc-4_5-branch/gcc/ira-color.c
1399=== modified file 'gcc/ira-color.c' 1389===================================================================
1400--- old/gcc/ira-color.c 2010-04-02 18:54:46 +0000 1390--- gcc-4_5-branch.orig/gcc/ira-color.c 2012-03-06 11:53:32.000000000 -0800
1401+++ new/gcc/ira-color.c 2010-09-01 13:29:58 +0000 1391+++ gcc-4_5-branch/gcc/ira-color.c 2012-03-06 12:14:01.056439222 -0800
1402@@ -441,14 +441,18 @@ 1392@@ -447,14 +447,18 @@
1403 { 1393 {
1404 HARD_REG_SET conflicting_regs; 1394 HARD_REG_SET conflicting_regs;
1405 int i, j, k, hard_regno, best_hard_regno, class_size; 1395 int i, j, k, hard_regno, best_hard_regno, class_size;
@@ -1420,7 +1410,7 @@
1420 #ifdef STACK_REGS 1410 #ifdef STACK_REGS
1421 bool no_stack_reg_p; 1411 bool no_stack_reg_p;
1422 #endif 1412 #endif
1423@@ -586,6 +590,7 @@ 1413@@ -592,6 +596,7 @@
1424 continue; 1414 continue;
1425 cost = costs[i]; 1415 cost = costs[i];
1426 full_cost = full_costs[i]; 1416 full_cost = full_costs[i];
@@ -1428,7 +1418,7 @@
1428 if (! allocated_hardreg_p[hard_regno] 1418 if (! allocated_hardreg_p[hard_regno]
1429 && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set)) 1419 && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set))
1430 /* We need to save/restore the hard register in 1420 /* We need to save/restore the hard register in
1431@@ -598,6 +603,7 @@ 1421@@ -604,6 +609,7 @@
1432 cost += add_cost; 1422 cost += add_cost;
1433 full_cost += add_cost; 1423 full_cost += add_cost;
1434 } 1424 }
@@ -1436,10 +1426,10 @@
1436 if (min_cost > cost) 1426 if (min_cost > cost)
1437 min_cost = cost; 1427 min_cost = cost;
1438 if (min_full_cost > full_cost) 1428 if (min_full_cost > full_cost)
1439 1429Index: gcc-4_5-branch/gcc/ira-costs.c
1440=== modified file 'gcc/ira-costs.c' 1430===================================================================
1441--- old/gcc/ira-costs.c 2010-08-13 11:40:17 +0000 1431--- gcc-4_5-branch.orig/gcc/ira-costs.c 2012-03-06 12:11:33.000000000 -0800
1442+++ new/gcc/ira-costs.c 2010-09-01 13:29:58 +0000 1432+++ gcc-4_5-branch/gcc/ira-costs.c 2012-03-06 12:14:01.056439222 -0800
1443@@ -33,6 +33,7 @@ 1433@@ -33,6 +33,7 @@
1444 #include "addresses.h" 1434 #include "addresses.h"
1445 #include "insn-config.h" 1435 #include "insn-config.h"
@@ -1525,10 +1515,10 @@
1525+ else 1515+ else
1526+ regno_equiv_gains[regno] += cost; 1516+ regno_equiv_gains[regno] += cost;
1527+} 1517+}
1528 1518Index: gcc-4_5-branch/gcc/ira.c
1529=== modified file 'gcc/ira.c' 1519===================================================================
1530--- old/gcc/ira.c 2010-08-12 13:51:16 +0000 1520--- gcc-4_5-branch.orig/gcc/ira.c 2012-03-06 12:11:32.000000000 -0800
1531+++ new/gcc/ira.c 2010-09-01 13:29:58 +0000 1521+++ gcc-4_5-branch/gcc/ira.c 2012-03-06 12:14:01.056439222 -0800
1532@@ -431,9 +431,6 @@ 1522@@ -431,9 +431,6 @@
1533 HARD_REG_SET processed_hard_reg_set; 1523 HARD_REG_SET processed_hard_reg_set;
1534 1524
@@ -1564,7 +1554,7 @@
1564 { 1554 {
1565 /* It can happen that a REG_EQUIV note contains a MEM 1555 /* It can happen that a REG_EQUIV note contains a MEM
1566 that is not a legitimate memory operand. As later 1556 that is not a legitimate memory operand. As later
1567@@ -3097,8 +3093,19 @@ 1557@@ -3096,8 +3092,19 @@
1568 if (dump_file) 1558 if (dump_file)
1569 print_insn_chains (dump_file); 1559 print_insn_chains (dump_file);
1570 } 1560 }
@@ -1585,7 +1575,7 @@
1585 1575
1586 /* All natural loops. */ 1576 /* All natural loops. */
1587 struct loops ira_loops; 1577 struct loops ira_loops;
1588@@ -3203,6 +3210,8 @@ 1578@@ -3202,6 +3209,8 @@
1589 record_loop_exits (); 1579 record_loop_exits ();
1590 current_loops = &ira_loops; 1580 current_loops = &ira_loops;
1591 1581
@@ -1594,7 +1584,7 @@
1594 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) 1584 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL)
1595 fprintf (ira_dump_file, "Building IRA IR\n"); 1585 fprintf (ira_dump_file, "Building IRA IR\n");
1596 loops_p = ira_build (optimize 1586 loops_p = ira_build (optimize
1597@@ -3263,13 +3272,8 @@ 1587@@ -3265,13 +3274,8 @@
1598 #endif 1588 #endif
1599 1589
1600 delete_trivially_dead_insns (get_insns (), max_reg_num ()); 1590 delete_trivially_dead_insns (get_insns (), max_reg_num ());
@@ -1609,19 +1599,19 @@
1609 1599
1610 if (max_regno != max_regno_before_ira) 1600 if (max_regno != max_regno_before_ira)
1611 { 1601 {
1612 1602Index: gcc-4_5-branch/gcc/ira.h
1613=== modified file 'gcc/ira.h' 1603===================================================================
1614--- old/gcc/ira.h 2009-09-02 17:54:25 +0000 1604--- gcc-4_5-branch.orig/gcc/ira.h 2012-03-06 11:53:32.000000000 -0800
1615+++ new/gcc/ira.h 2010-09-01 13:29:58 +0000 1605+++ gcc-4_5-branch/gcc/ira.h 2012-03-06 12:14:01.056439222 -0800
1616@@ -87,3 +87,4 @@ 1606@@ -87,3 +87,4 @@
1617 extern void ira_mark_new_stack_slot (rtx, int, unsigned int); 1607 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
1618 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); 1608 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
1619 1609
1620+extern void ira_adjust_equiv_reg_cost (unsigned, int); 1610+extern void ira_adjust_equiv_reg_cost (unsigned, int);
1621 1611Index: gcc-4_5-branch/gcc/optabs.h
1622=== modified file 'gcc/optabs.h' 1612===================================================================
1623--- old/gcc/optabs.h 2009-11-25 10:55:54 +0000 1613--- gcc-4_5-branch.orig/gcc/optabs.h 2012-03-06 11:53:32.000000000 -0800
1624+++ new/gcc/optabs.h 2010-09-01 13:29:58 +0000 1614+++ gcc-4_5-branch/gcc/optabs.h 2012-03-06 12:14:01.056439222 -0800
1625@@ -771,6 +771,9 @@ 1615@@ -771,6 +771,9 @@
1626 /* Generate code for float to integral conversion. */ 1616 /* Generate code for float to integral conversion. */
1627 extern bool expand_sfix_optab (rtx, rtx, convert_optab); 1617 extern bool expand_sfix_optab (rtx, rtx, convert_optab);
@@ -1632,10 +1622,10 @@
1632 /* Return tree if target supports vector operations for COND_EXPR. */ 1622 /* Return tree if target supports vector operations for COND_EXPR. */
1633 bool expand_vec_cond_expr_p (tree, enum machine_mode); 1623 bool expand_vec_cond_expr_p (tree, enum machine_mode);
1634 1624
1635 1625Index: gcc-4_5-branch/gcc/passes.c
1636=== modified file 'gcc/passes.c' 1626===================================================================
1637--- old/gcc/passes.c 2010-05-19 12:14:37 +0000 1627--- gcc-4_5-branch.orig/gcc/passes.c 2012-03-06 11:53:32.000000000 -0800
1638+++ new/gcc/passes.c 2010-09-01 13:29:58 +0000 1628+++ gcc-4_5-branch/gcc/passes.c 2012-03-06 12:14:01.056439222 -0800
1639@@ -944,6 +944,7 @@ 1629@@ -944,6 +944,7 @@
1640 NEXT_PASS (pass_forwprop); 1630 NEXT_PASS (pass_forwprop);
1641 NEXT_PASS (pass_phiopt); 1631 NEXT_PASS (pass_phiopt);
@@ -1644,10 +1634,10 @@
1644 NEXT_PASS (pass_tail_calls); 1634 NEXT_PASS (pass_tail_calls);
1645 NEXT_PASS (pass_rename_ssa_copies); 1635 NEXT_PASS (pass_rename_ssa_copies);
1646 NEXT_PASS (pass_uncprop); 1636 NEXT_PASS (pass_uncprop);
1647 1637Index: gcc-4_5-branch/gcc/reload.h
1648=== modified file 'gcc/reload.h' 1638===================================================================
1649--- old/gcc/reload.h 2010-04-02 18:54:46 +0000 1639--- gcc-4_5-branch.orig/gcc/reload.h 2012-03-06 11:53:32.000000000 -0800
1650+++ new/gcc/reload.h 2010-09-01 13:29:58 +0000 1640+++ gcc-4_5-branch/gcc/reload.h 2012-03-06 12:14:01.056439222 -0800
1651@@ -347,6 +347,10 @@ 1641@@ -347,6 +347,10 @@
1652 extern rtx eliminate_regs (rtx, enum machine_mode, rtx); 1642 extern rtx eliminate_regs (rtx, enum machine_mode, rtx);
1653 extern bool elimination_target_reg_p (rtx); 1643 extern bool elimination_target_reg_p (rtx);
@@ -1659,10 +1649,10 @@
1659 /* Deallocate the reload register used by reload number R. */ 1649 /* Deallocate the reload register used by reload number R. */
1660 extern void deallocate_reload_reg (int r); 1650 extern void deallocate_reload_reg (int r);
1661 1651
1662 1652Index: gcc-4_5-branch/gcc/reload1.c
1663=== modified file 'gcc/reload1.c' 1653===================================================================
1664--- old/gcc/reload1.c 2010-03-02 18:56:50 +0000 1654--- gcc-4_5-branch.orig/gcc/reload1.c 2012-03-06 11:53:32.000000000 -0800
1665+++ new/gcc/reload1.c 2010-09-01 13:29:58 +0000 1655+++ gcc-4_5-branch/gcc/reload1.c 2012-03-06 12:14:01.060439213 -0800
1666@@ -413,6 +413,7 @@ 1656@@ -413,6 +413,7 @@
1667 static void set_label_offsets (rtx, rtx, int); 1657 static void set_label_offsets (rtx, rtx, int);
1668 static void check_eliminable_occurrences (rtx); 1658 static void check_eliminable_occurrences (rtx);
@@ -1683,7 +1673,7 @@
1683 static void spill_hard_reg (unsigned int, int); 1673 static void spill_hard_reg (unsigned int, int);
1684 static int finish_spills (int); 1674 static int finish_spills (int);
1685 static void scan_paradoxical_subregs (rtx); 1675 static void scan_paradoxical_subregs (rtx);
1686@@ -698,6 +702,9 @@ 1676@@ -697,6 +701,9 @@
1687 1677
1688 /* Global variables used by reload and its subroutines. */ 1678 /* Global variables used by reload and its subroutines. */
1689 1679
@@ -1693,7 +1683,7 @@
1693 /* Set during calculate_needs if an insn needs register elimination. */ 1683 /* Set during calculate_needs if an insn needs register elimination. */
1694 static int something_needs_elimination; 1684 static int something_needs_elimination;
1695 /* Set during calculate_needs if an insn needs an operand changed. */ 1685 /* Set during calculate_needs if an insn needs an operand changed. */
1696@@ -776,22 +783,6 @@ 1686@@ -775,22 +782,6 @@
1697 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) 1687 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
1698 df_set_regs_ever_live (i, true); 1688 df_set_regs_ever_live (i, true);
1699 1689
@@ -1716,7 +1706,7 @@
1716 reg_old_renumber = XCNEWVEC (short, max_regno); 1706 reg_old_renumber = XCNEWVEC (short, max_regno);
1717 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); 1707 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
1718 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); 1708 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
1719@@ -799,115 +790,9 @@ 1709@@ -798,115 +789,9 @@
1720 1710
1721 CLEAR_HARD_REG_SET (bad_spill_regs_global); 1711 CLEAR_HARD_REG_SET (bad_spill_regs_global);
1722 1712
@@ -1833,13 +1823,11 @@
1833 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign 1823 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
1834 stack slots to the pseudos that lack hard regs or equivalents. 1824 stack slots to the pseudos that lack hard regs or equivalents.
1835 Do not touch virtual registers. */ 1825 Do not touch virtual registers. */
1836@@ -1411,31 +1296,11 @@ 1826@@ -1410,31 +1295,11 @@
1837 } 1827 }
1838 } 1828 }
1839 1829
1840+ free (temp_pseudo_reg_arr); 1830- /* Indicate that we no longer have known memory locations or constants. */
1841+
1842 /* Indicate that we no longer have known memory locations or constants. */
1843- if (reg_equiv_constant) 1831- if (reg_equiv_constant)
1844- free (reg_equiv_constant); 1832- free (reg_equiv_constant);
1845- if (reg_equiv_invariant) 1833- if (reg_equiv_invariant)
@@ -1849,8 +1837,8 @@
1849- VEC_free (rtx, gc, reg_equiv_memory_loc_vec); 1837- VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1850- reg_equiv_memory_loc = 0; 1838- reg_equiv_memory_loc = 0;
1851- 1839-
1852- free (temp_pseudo_reg_arr); 1840 free (temp_pseudo_reg_arr);
1853- 1841
1854- if (offsets_known_at) 1842- if (offsets_known_at)
1855- free (offsets_known_at); 1843- free (offsets_known_at);
1856- if (offsets_at) 1844- if (offsets_at)
@@ -1862,13 +1850,14 @@
1862- free (reg_equiv_alt_mem_list); 1850- free (reg_equiv_alt_mem_list);
1863- 1851-
1864- free (reg_equiv_mem); 1852- free (reg_equiv_mem);
1853+ /* Indicate that we no longer have known memory locations or constants. */
1865+ free_reg_equiv (); 1854+ free_reg_equiv ();
1866 reg_equiv_init = 0; 1855 reg_equiv_init = 0;
1867- free (reg_equiv_address); 1856- free (reg_equiv_address);
1868 free (reg_max_ref_width); 1857 free (reg_max_ref_width);
1869 free (reg_old_renumber); 1858 free (reg_old_renumber);
1870 free (pseudo_previous_regs); 1859 free (pseudo_previous_regs);
1871@@ -1728,6 +1593,100 @@ 1860@@ -1727,6 +1592,100 @@
1872 *pprev_reload = 0; 1861 *pprev_reload = 0;
1873 } 1862 }
1874 1863
@@ -1969,7 +1958,7 @@
1969 /* Comparison function for qsort to decide which of two reloads 1958 /* Comparison function for qsort to decide which of two reloads
1970 should be handled first. *P1 and *P2 are the reload numbers. */ 1959 should be handled first. *P1 and *P2 are the reload numbers. */
1971 1960
1972@@ -2514,6 +2473,36 @@ 1961@@ -2513,6 +2472,36 @@
1973 } 1962 }
1974 } 1963 }
1975 1964
@@ -2006,7 +1995,7 @@
2006 /* Scan X and replace any eliminable registers (such as fp) with a 1995 /* Scan X and replace any eliminable registers (such as fp) with a
2007 replacement (such as sp), plus an offset. 1996 replacement (such as sp), plus an offset.
2008 1997
2009@@ -2533,6 +2522,9 @@ 1998@@ -2532,6 +2521,9 @@
2010 This means, do not set ref_outside_mem even if the reference 1999 This means, do not set ref_outside_mem even if the reference
2011 is outside of MEMs. 2000 is outside of MEMs.
2012 2001
@@ -2016,7 +2005,7 @@
2016 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2005 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2017 replacements done assuming all offsets are at their initial values. If 2006 replacements done assuming all offsets are at their initial values. If
2018 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2007 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2019@@ -2541,7 +2533,7 @@ 2008@@ -2540,7 +2532,7 @@
2020 2009
2021 static rtx 2010 static rtx
2022 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn, 2011 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
@@ -2025,7 +2014,7 @@
2025 { 2014 {
2026 enum rtx_code code = GET_CODE (x); 2015 enum rtx_code code = GET_CODE (x);
2027 struct elim_table *ep; 2016 struct elim_table *ep;
2028@@ -2589,11 +2581,12 @@ 2017@@ -2588,11 +2580,12 @@
2029 { 2018 {
2030 if (may_use_invariant || (insn && DEBUG_INSN_P (insn))) 2019 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2031 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]), 2020 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
@@ -2040,7 +2029,7 @@
2040 } 2029 }
2041 return x; 2030 return x;
2042 2031
2043@@ -2654,8 +2647,10 @@ 2032@@ -2653,8 +2646,10 @@
2044 operand of a load-address insn. */ 2033 operand of a load-address insn. */
2045 2034
2046 { 2035 {
@@ -2053,7 +2042,7 @@
2053 2042
2054 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) 2043 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2055 { 2044 {
2056@@ -2729,9 +2724,11 @@ 2045@@ -2728,9 +2723,11 @@
2057 case GE: case GT: case GEU: case GTU: 2046 case GE: case GT: case GEU: case GTU:
2058 case LE: case LT: case LEU: case LTU: 2047 case LE: case LT: case LEU: case LTU:
2059 { 2048 {
@@ -2067,7 +2056,7 @@
2067 2056
2068 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2057 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2069 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 2058 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2070@@ -2742,7 +2739,8 @@ 2059@@ -2741,7 +2738,8 @@
2071 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 2060 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2072 if (XEXP (x, 0)) 2061 if (XEXP (x, 0))
2073 { 2062 {
@@ -2077,7 +2066,7 @@
2077 if (new_rtx != XEXP (x, 0)) 2066 if (new_rtx != XEXP (x, 0))
2078 { 2067 {
2079 /* If this is a REG_DEAD note, it is not valid anymore. 2068 /* If this is a REG_DEAD note, it is not valid anymore.
2080@@ -2750,7 +2748,8 @@ 2069@@ -2749,7 +2747,8 @@
2081 REG_DEAD note for the stack or frame pointer. */ 2070 REG_DEAD note for the stack or frame pointer. */
2082 if (REG_NOTE_KIND (x) == REG_DEAD) 2071 if (REG_NOTE_KIND (x) == REG_DEAD)
2083 return (XEXP (x, 1) 2072 return (XEXP (x, 1)
@@ -2087,7 +2076,7 @@
2087 : NULL_RTX); 2076 : NULL_RTX);
2088 2077
2089 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); 2078 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2090@@ -2765,7 +2764,8 @@ 2079@@ -2764,7 +2763,8 @@
2091 strictly needed, but it simplifies the code. */ 2080 strictly needed, but it simplifies the code. */
2092 if (XEXP (x, 1)) 2081 if (XEXP (x, 1))
2093 { 2082 {
@@ -2097,7 +2086,7 @@
2097 if (new_rtx != XEXP (x, 1)) 2086 if (new_rtx != XEXP (x, 1))
2098 return 2087 return
2099 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); 2088 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2100@@ -2791,7 +2791,7 @@ 2089@@ -2790,7 +2790,7 @@
2101 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) 2090 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2102 { 2091 {
2103 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, 2092 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
@@ -2106,7 +2095,7 @@
2106 2095
2107 if (new_rtx != XEXP (XEXP (x, 1), 1)) 2096 if (new_rtx != XEXP (XEXP (x, 1), 1))
2108 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), 2097 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2109@@ -2814,7 +2814,8 @@ 2098@@ -2813,7 +2813,8 @@
2110 case POPCOUNT: 2099 case POPCOUNT:
2111 case PARITY: 2100 case PARITY:
2112 case BSWAP: 2101 case BSWAP:
@@ -2116,7 +2105,7 @@
2116 if (new_rtx != XEXP (x, 0)) 2105 if (new_rtx != XEXP (x, 0))
2117 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); 2106 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2118 return x; 2107 return x;
2119@@ -2835,7 +2836,8 @@ 2108@@ -2834,7 +2835,8 @@
2120 new_rtx = SUBREG_REG (x); 2109 new_rtx = SUBREG_REG (x);
2121 } 2110 }
2122 else 2111 else
@@ -2126,7 +2115,7 @@
2126 2115
2127 if (new_rtx != SUBREG_REG (x)) 2116 if (new_rtx != SUBREG_REG (x))
2128 { 2117 {
2129@@ -2869,14 +2871,20 @@ 2118@@ -2868,14 +2870,20 @@
2130 /* Our only special processing is to pass the mode of the MEM to our 2119 /* Our only special processing is to pass the mode of the MEM to our
2131 recursive call and copy the flags. While we are here, handle this 2120 recursive call and copy the flags. While we are here, handle this
2132 case more efficiently. */ 2121 case more efficiently. */
@@ -2152,7 +2141,7 @@
2152 if (new_rtx != XEXP (x, 0)) 2141 if (new_rtx != XEXP (x, 0))
2153 return gen_rtx_USE (GET_MODE (x), new_rtx); 2142 return gen_rtx_USE (GET_MODE (x), new_rtx);
2154 return x; 2143 return x;
2155@@ -2900,7 +2908,8 @@ 2144@@ -2899,7 +2907,8 @@
2156 { 2145 {
2157 if (*fmt == 'e') 2146 if (*fmt == 'e')
2158 { 2147 {
@@ -2162,7 +2151,7 @@
2162 if (new_rtx != XEXP (x, i) && ! copied) 2151 if (new_rtx != XEXP (x, i) && ! copied)
2163 { 2152 {
2164 x = shallow_copy_rtx (x); 2153 x = shallow_copy_rtx (x);
2165@@ -2913,7 +2922,8 @@ 2154@@ -2912,7 +2921,8 @@
2166 int copied_vec = 0; 2155 int copied_vec = 0;
2167 for (j = 0; j < XVECLEN (x, i); j++) 2156 for (j = 0; j < XVECLEN (x, i); j++)
2168 { 2157 {
@@ -2172,7 +2161,7 @@
2172 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) 2161 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2173 { 2162 {
2174 rtvec new_v = gen_rtvec_v (XVECLEN (x, i), 2163 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2175@@ -2937,7 +2947,7 @@ 2164@@ -2936,7 +2946,7 @@
2176 rtx 2165 rtx
2177 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn) 2166 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2178 { 2167 {
@@ -2181,7 +2170,7 @@
2181 } 2170 }
2182 2171
2183 /* Scan rtx X for modifications of elimination target registers. Update 2172 /* Scan rtx X for modifications of elimination target registers. Update
2184@@ -3455,7 +3465,8 @@ 2173@@ -3454,7 +3464,8 @@
2185 /* Companion to the above plus substitution, we can allow 2174 /* Companion to the above plus substitution, we can allow
2186 invariants as the source of a plain move. */ 2175 invariants as the source of a plain move. */
2187 is_set_src = false; 2176 is_set_src = false;
@@ -2191,7 +2180,7 @@
2191 is_set_src = true; 2180 is_set_src = true;
2192 in_plus = false; 2181 in_plus = false;
2193 if (plus_src 2182 if (plus_src
2194@@ -3466,7 +3477,7 @@ 2183@@ -3465,7 +3476,7 @@
2195 substed_operand[i] 2184 substed_operand[i]
2196 = eliminate_regs_1 (recog_data.operand[i], VOIDmode, 2185 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
2197 replace ? insn : NULL_RTX, 2186 replace ? insn : NULL_RTX,
@@ -2200,7 +2189,7 @@
2200 if (substed_operand[i] != orig_operand[i]) 2189 if (substed_operand[i] != orig_operand[i])
2201 val = 1; 2190 val = 1;
2202 /* Terminate the search in check_eliminable_occurrences at 2191 /* Terminate the search in check_eliminable_occurrences at
2203@@ -3594,11 +3605,167 @@ 2192@@ -3593,11 +3604,167 @@
2204 the pre-passes. */ 2193 the pre-passes. */
2205 if (val && REG_NOTES (insn) != 0) 2194 if (val && REG_NOTES (insn) != 0)
2206 REG_NOTES (insn) 2195 REG_NOTES (insn)
@@ -2369,7 +2358,7 @@
2369 /* Loop through all elimination pairs. 2358 /* Loop through all elimination pairs.
2370 Recalculate the number not at initial offset. 2359 Recalculate the number not at initial offset.
2371 2360
2372@@ -3908,6 +4075,168 @@ 2361@@ -3907,6 +4074,168 @@
2373 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 2362 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
2374 } 2363 }
2375 } 2364 }
@@ -2547,10 +2536,10 @@
2547 return 1; 2536 return 1;
2548 return 0; 2537 return 0;
2549 } 2538 }
2550 2539Index: gcc-4_5-branch/gcc/system.h
2551=== modified file 'gcc/system.h' 2540===================================================================
2552--- old/gcc/system.h 2009-12-13 23:00:53 +0000 2541--- gcc-4_5-branch.orig/gcc/system.h 2012-03-06 11:53:32.000000000 -0800
2553+++ new/gcc/system.h 2010-09-01 13:29:58 +0000 2542+++ gcc-4_5-branch/gcc/system.h 2012-03-06 12:14:01.060439213 -0800
2554@@ -761,7 +761,8 @@ 2543@@ -761,7 +761,8 @@
2555 TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \ 2544 TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \
2556 SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \ 2545 SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \
@@ -2561,10 +2550,10 @@
2561 2550
2562 /* Hooks that are no longer used. */ 2551 /* Hooks that are no longer used. */
2563 #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \ 2552 #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \
2564 2553Index: gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c
2565=== added file 'gcc/testsuite/c-c++-common/uninit-17.c' 2554===================================================================
2566--- old/gcc/testsuite/c-c++-common/uninit-17.c 1970-01-01 00:00:00 +0000 2555--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2567+++ new/gcc/testsuite/c-c++-common/uninit-17.c 2010-09-01 13:29:58 +0000 2556+++ gcc-4_5-branch/gcc/testsuite/c-c++-common/uninit-17.c 2012-03-06 12:14:01.060439213 -0800
2568@@ -0,0 +1,25 @@ 2557@@ -0,0 +1,25 @@
2569+/* { dg-do compile } */ 2558+/* { dg-do compile } */
2570+/* { dg-options "-O2 -Wuninitialized" } */ 2559+/* { dg-options "-O2 -Wuninitialized" } */
@@ -2591,10 +2580,10 @@
2591+ bar(foo(a), ptr); 2580+ bar(foo(a), ptr);
2592+} 2581+}
2593+ 2582+
2594 2583Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c
2595=== added file 'gcc/testsuite/gcc.target/arm/eliminate.c' 2584===================================================================
2596--- old/gcc/testsuite/gcc.target/arm/eliminate.c 1970-01-01 00:00:00 +0000 2585--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2597+++ new/gcc/testsuite/gcc.target/arm/eliminate.c 2010-09-01 13:29:58 +0000 2586+++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/eliminate.c 2012-03-06 12:14:01.060439213 -0800
2598@@ -0,0 +1,19 @@ 2587@@ -0,0 +1,19 @@
2599+/* { dg-do compile } */ 2588+/* { dg-do compile } */
2600+/* { dg-options "-O2" } */ 2589+/* { dg-options "-O2" } */
@@ -2615,10 +2604,10 @@
2615+} 2604+}
2616+ 2605+
2617+/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */ 2606+/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */
2618 2607Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c
2619=== added file 'gcc/testsuite/gcc.target/arm/pr40900.c' 2608===================================================================
2620--- old/gcc/testsuite/gcc.target/arm/pr40900.c 1970-01-01 00:00:00 +0000 2609--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2621+++ new/gcc/testsuite/gcc.target/arm/pr40900.c 2010-09-01 13:29:58 +0000 2610+++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr40900.c 2012-03-06 12:14:01.060439213 -0800
2622@@ -0,0 +1,12 @@ 2611@@ -0,0 +1,12 @@
2623+/* { dg-do compile } */ 2612+/* { dg-do compile } */
2624+/* { dg-options "-O2 -fno-optimize-sibling-calls" } */ 2613+/* { dg-options "-O2 -fno-optimize-sibling-calls" } */
@@ -2632,10 +2621,10 @@
2632+/* { dg-final { scan-assembler-not "lsl" } } */ 2621+/* { dg-final { scan-assembler-not "lsl" } } */
2633+/* { dg-final { scan-assembler-not "asr" } } */ 2622+/* { dg-final { scan-assembler-not "asr" } } */
2634+/* { dg-final { scan-assembler-not "sxth" } } */ 2623+/* { dg-final { scan-assembler-not "sxth" } } */
2635 2624Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c
2636=== added file 'gcc/testsuite/gcc.target/arm/pr42496.c' 2625===================================================================
2637--- old/gcc/testsuite/gcc.target/arm/pr42496.c 1970-01-01 00:00:00 +0000 2626--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2638+++ new/gcc/testsuite/gcc.target/arm/pr42496.c 2010-09-01 13:29:58 +0000 2627+++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/pr42496.c 2012-03-06 12:14:01.060439213 -0800
2639@@ -0,0 +1,16 @@ 2628@@ -0,0 +1,16 @@
2640+/* { dg-options "-O2" } */ 2629+/* { dg-options "-O2" } */
2641+ 2630+
@@ -2653,10 +2642,10 @@
2653+ 2642+
2654+/* { dg-final { scan-assembler-not "strne" } } */ 2643+/* { dg-final { scan-assembler-not "strne" } } */
2655+/* { dg-final { scan-assembler-not "streq" } } */ 2644+/* { dg-final { scan-assembler-not "streq" } } */
2656 2645Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c
2657=== added file 'gcc/testsuite/gcc.target/arm/wmul-1.c' 2646===================================================================
2658--- old/gcc/testsuite/gcc.target/arm/wmul-1.c 1970-01-01 00:00:00 +0000 2647--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2659+++ new/gcc/testsuite/gcc.target/arm/wmul-1.c 2010-09-01 13:29:58 +0000 2648+++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-1.c 2012-03-06 12:14:01.060439213 -0800
2660@@ -0,0 +1,18 @@ 2649@@ -0,0 +1,18 @@
2661+/* { dg-do compile } */ 2650+/* { dg-do compile } */
2662+/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ 2651+/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */
@@ -2676,10 +2665,10 @@
2676+} 2665+}
2677+ 2666+
2678+/* { dg-final { scan-assembler-times "smulbb" 2 } } */ 2667+/* { dg-final { scan-assembler-times "smulbb" 2 } } */
2679 2668Index: gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c
2680=== added file 'gcc/testsuite/gcc.target/arm/wmul-2.c' 2669===================================================================
2681--- old/gcc/testsuite/gcc.target/arm/wmul-2.c 1970-01-01 00:00:00 +0000 2670--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2682+++ new/gcc/testsuite/gcc.target/arm/wmul-2.c 2010-09-01 13:29:58 +0000 2671+++ gcc-4_5-branch/gcc/testsuite/gcc.target/arm/wmul-2.c 2012-03-06 12:14:01.064439219 -0800
2683@@ -0,0 +1,12 @@ 2672@@ -0,0 +1,12 @@
2684+/* { dg-do compile } */ 2673+/* { dg-do compile } */
2685+/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */ 2674+/* { dg-options "-O2 -march=armv6t2 -fno-unroll-loops" } */
@@ -2693,10 +2682,10 @@
2693+} 2682+}
2694+ 2683+
2695+/* { dg-final { scan-assembler-times "smulbb" 1 } } */ 2684+/* { dg-final { scan-assembler-times "smulbb" 1 } } */
2696 2685Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c
2697=== added file 'gcc/testsuite/gcc.target/bfin/wmul-1.c' 2686===================================================================
2698--- old/gcc/testsuite/gcc.target/bfin/wmul-1.c 1970-01-01 00:00:00 +0000 2687--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2699+++ new/gcc/testsuite/gcc.target/bfin/wmul-1.c 2010-09-01 13:29:58 +0000 2688+++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-1.c 2012-03-06 12:14:01.064439219 -0800
2700@@ -0,0 +1,18 @@ 2689@@ -0,0 +1,18 @@
2701+/* { dg-do compile } */ 2690+/* { dg-do compile } */
2702+/* { dg-options "-O2" } */ 2691+/* { dg-options "-O2" } */
@@ -2716,10 +2705,10 @@
2716+} 2705+}
2717+ 2706+
2718+/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */ 2707+/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */
2719 2708Index: gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c
2720=== added file 'gcc/testsuite/gcc.target/bfin/wmul-2.c' 2709===================================================================
2721--- old/gcc/testsuite/gcc.target/bfin/wmul-2.c 1970-01-01 00:00:00 +0000 2710--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2722+++ new/gcc/testsuite/gcc.target/bfin/wmul-2.c 2010-09-01 13:29:58 +0000 2711+++ gcc-4_5-branch/gcc/testsuite/gcc.target/bfin/wmul-2.c 2012-03-06 12:14:01.064439219 -0800
2723@@ -0,0 +1,12 @@ 2712@@ -0,0 +1,12 @@
2724+/* { dg-do compile } */ 2713+/* { dg-do compile } */
2725+/* { dg-options "-O2" } */ 2714+/* { dg-options "-O2" } */
@@ -2733,10 +2722,10 @@
2733+} 2722+}
2734+ 2723+
2735+/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */ 2724+/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */
2736 2725Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c
2737=== added file 'gcc/testsuite/gcc.target/i386/pr41442.c' 2726===================================================================
2738--- old/gcc/testsuite/gcc.target/i386/pr41442.c 1970-01-01 00:00:00 +0000 2727--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2739+++ new/gcc/testsuite/gcc.target/i386/pr41442.c 2010-09-01 13:29:58 +0000 2728+++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/pr41442.c 2012-03-06 12:14:01.064439219 -0800
2740@@ -0,0 +1,18 @@ 2729@@ -0,0 +1,18 @@
2741+/* { dg-do compile } */ 2730+/* { dg-do compile } */
2742+/* { dg-options "-O2" } */ 2731+/* { dg-options "-O2" } */
@@ -2756,10 +2745,10 @@
2756+} 2745+}
2757+ 2746+
2758+/* { dg-final { scan-assembler-times "test|cmp" 2 } } */ 2747+/* { dg-final { scan-assembler-times "test|cmp" 2 } } */
2759 2748Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c
2760=== added file 'gcc/testsuite/gcc.target/i386/wmul-1.c' 2749===================================================================
2761--- old/gcc/testsuite/gcc.target/i386/wmul-1.c 1970-01-01 00:00:00 +0000 2750--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2762+++ new/gcc/testsuite/gcc.target/i386/wmul-1.c 2010-09-01 13:29:58 +0000 2751+++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-1.c 2012-03-06 12:14:01.064439219 -0800
2763@@ -0,0 +1,18 @@ 2752@@ -0,0 +1,18 @@
2764+/* { dg-do compile } */ 2753+/* { dg-do compile } */
2765+/* { dg-options "-O2" } */ 2754+/* { dg-options "-O2" } */
@@ -2779,10 +2768,10 @@
2779+} 2768+}
2780+ 2769+
2781+/* { dg-final { scan-assembler-times "imull" 2 } } */ 2770+/* { dg-final { scan-assembler-times "imull" 2 } } */
2782 2771Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c
2783=== added file 'gcc/testsuite/gcc.target/i386/wmul-2.c' 2772===================================================================
2784--- old/gcc/testsuite/gcc.target/i386/wmul-2.c 1970-01-01 00:00:00 +0000 2773--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2785+++ new/gcc/testsuite/gcc.target/i386/wmul-2.c 2010-09-01 13:29:58 +0000 2774+++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/wmul-2.c 2012-03-06 12:14:01.064439219 -0800
2786@@ -0,0 +1,12 @@ 2775@@ -0,0 +1,12 @@
2787+/* { dg-do compile } */ 2776+/* { dg-do compile } */
2788+/* { dg-options "-O2" } */ 2777+/* { dg-options "-O2" } */
@@ -2796,29 +2785,29 @@
2796+} 2785+}
2797+ 2786+
2798+/* { dg-final { scan-assembler-times "imull" 1 } } */ 2787+/* { dg-final { scan-assembler-times "imull" 1 } } */
2799 2788Index: gcc-4_5-branch/gcc/tree-cfg.c
2800=== modified file 'gcc/tree-cfg.c' 2789===================================================================
2801--- old/gcc/tree-cfg.c 2010-08-10 13:31:21 +0000 2790--- gcc-4_5-branch.orig/gcc/tree-cfg.c 2012-03-06 12:11:30.000000000 -0800
2802+++ new/gcc/tree-cfg.c 2010-09-01 13:29:58 +0000 2791+++ gcc-4_5-branch/gcc/tree-cfg.c 2012-03-06 12:14:01.064439219 -0800
2803@@ -3428,8 +3428,13 @@ 2792@@ -3429,8 +3429,13 @@
2804 connected to the operand types. */ 2793 connected to the operand types. */
2805 return verify_gimple_comparison (lhs_type, rhs1, rhs2); 2794 return verify_gimple_comparison (lhs_type, rhs1, rhs2);
2806 2795
2807+ case WIDEN_MULT_EXPR: 2796- case WIDEN_SUM_EXPR:
2797 case WIDEN_MULT_EXPR:
2808+ if (TREE_CODE (lhs_type) != INTEGER_TYPE) 2798+ if (TREE_CODE (lhs_type) != INTEGER_TYPE)
2809+ return true; 2799+ return true;
2810+ return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)) 2800+ return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type))
2811+ || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))); 2801+ || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)));
2812+ 2802+
2813 case WIDEN_SUM_EXPR: 2803+ case WIDEN_SUM_EXPR:
2814- case WIDEN_MULT_EXPR:
2815 case VEC_WIDEN_MULT_HI_EXPR: 2804 case VEC_WIDEN_MULT_HI_EXPR:
2816 case VEC_WIDEN_MULT_LO_EXPR: 2805 case VEC_WIDEN_MULT_LO_EXPR:
2817 case VEC_PACK_TRUNC_EXPR: 2806 case VEC_PACK_TRUNC_EXPR:
2818 2807Index: gcc-4_5-branch/gcc/tree-inline.c
2819=== modified file 'gcc/tree-inline.c' 2808===================================================================
2820--- old/gcc/tree-inline.c 2010-08-10 13:31:21 +0000 2809--- gcc-4_5-branch.orig/gcc/tree-inline.c 2012-03-06 12:11:30.000000000 -0800
2821+++ new/gcc/tree-inline.c 2010-09-01 13:29:58 +0000 2810+++ gcc-4_5-branch/gcc/tree-inline.c 2012-03-06 12:14:01.064439219 -0800
2822@@ -229,6 +229,7 @@ 2811@@ -229,6 +229,7 @@
2823 regions of the CFG, but this is expensive to test. */ 2812 regions of the CFG, but this is expensive to test. */
2824 if (id->entry_bb 2813 if (id->entry_bb
@@ -2827,10 +2816,10 @@
2827 && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL 2816 && TREE_CODE (SSA_NAME_VAR (name)) != PARM_DECL
2828 && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest 2817 && (id->entry_bb != EDGE_SUCC (ENTRY_BLOCK_PTR, 0)->dest
2829 || EDGE_COUNT (id->entry_bb->preds) != 1)) 2818 || EDGE_COUNT (id->entry_bb->preds) != 1))
2830 2819Index: gcc-4_5-branch/gcc/tree-pass.h
2831=== modified file 'gcc/tree-pass.h' 2820===================================================================
2832--- old/gcc/tree-pass.h 2010-04-02 18:54:46 +0000 2821--- gcc-4_5-branch.orig/gcc/tree-pass.h 2012-03-06 11:53:32.000000000 -0800
2833+++ new/gcc/tree-pass.h 2010-09-01 13:29:58 +0000 2822+++ gcc-4_5-branch/gcc/tree-pass.h 2012-03-06 12:14:01.068439233 -0800
2834@@ -407,6 +407,7 @@ 2823@@ -407,6 +407,7 @@
2835 extern struct gimple_opt_pass pass_cse_reciprocals; 2824 extern struct gimple_opt_pass pass_cse_reciprocals;
2836 extern struct gimple_opt_pass pass_cse_sincos; 2825 extern struct gimple_opt_pass pass_cse_sincos;
@@ -2839,11 +2828,11 @@
2839 extern struct gimple_opt_pass pass_warn_function_return; 2828 extern struct gimple_opt_pass pass_warn_function_return;
2840 extern struct gimple_opt_pass pass_warn_function_noreturn; 2829 extern struct gimple_opt_pass pass_warn_function_noreturn;
2841 extern struct gimple_opt_pass pass_cselim; 2830 extern struct gimple_opt_pass pass_cselim;
2842 2831Index: gcc-4_5-branch/gcc/tree-ssa-math-opts.c
2843=== modified file 'gcc/tree-ssa-math-opts.c' 2832===================================================================
2844--- old/gcc/tree-ssa-math-opts.c 2010-04-02 18:54:46 +0000 2833--- gcc-4_5-branch.orig/gcc/tree-ssa-math-opts.c 2012-03-06 11:53:32.000000000 -0800
2845+++ new/gcc/tree-ssa-math-opts.c 2010-09-01 13:29:58 +0000 2834+++ gcc-4_5-branch/gcc/tree-ssa-math-opts.c 2012-03-06 12:14:01.068439233 -0800
2846@@ -1260,3 +1260,137 @@ 2835@@ -1269,3 +1269,137 @@
2847 0 /* todo_flags_finish */ 2836 0 /* todo_flags_finish */
2848 } 2837 }
2849 }; 2838 };
@@ -2981,10 +2970,10 @@
2981+ 0 /* todo_flags_finish */ 2970+ 0 /* todo_flags_finish */
2982+ } 2971+ }
2983+}; 2972+};
2984 2973Index: gcc-4_5-branch/gcc/tree-ssa.c
2985=== modified file 'gcc/tree-ssa.c' 2974===================================================================
2986--- old/gcc/tree-ssa.c 2009-12-07 22:42:10 +0000 2975--- gcc-4_5-branch.orig/gcc/tree-ssa.c 2012-03-06 11:53:32.000000000 -0800
2987+++ new/gcc/tree-ssa.c 2010-09-01 13:29:58 +0000 2976+++ gcc-4_5-branch/gcc/tree-ssa.c 2012-03-06 12:14:01.068439233 -0800
2988@@ -1671,6 +1671,8 @@ 2977@@ -1671,6 +1671,8 @@
2989 { 2978 {
2990 TREE_NO_WARNING (var) = 1; 2979 TREE_NO_WARNING (var) = 1;
@@ -2994,4 +2983,3 @@
2994 if (xloc.file != floc.file 2983 if (xloc.file != floc.file
2995 || xloc.line < floc.line 2984 || xloc.line < floc.line
2996 || xloc.line > LOCATION_LINE (cfun->function_end_locus)) 2985 || xloc.line > LOCATION_LINE (cfun->function_end_locus))
2997
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch
index b6c6532661..ac3a1e224d 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99424.patch
@@ -66,8 +66,10 @@
66 * gcc.target/i386/volatile-bitfields-2.c: New. 66 * gcc.target/i386/volatile-bitfields-2.c: New.
67 67
68=== modified file 'gcc/calls.c' 68=== modified file 'gcc/calls.c'
69--- old/gcc/calls.c 2010-10-04 00:50:43 +0000 69Index: gcc-4_5-branch/gcc/calls.c
70+++ new/gcc/calls.c 2010-11-04 12:43:52 +0000 70===================================================================
71--- gcc-4_5-branch.orig/gcc/calls.c 2012-03-06 13:05:56.524590011 -0800
72+++ gcc-4_5-branch/gcc/calls.c 2012-03-06 13:36:10.276677792 -0800
71@@ -878,7 +878,7 @@ 73@@ -878,7 +878,7 @@
72 int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD); 74 int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD);
73 75
@@ -77,10 +79,10 @@
77 word_mode, word_mode); 79 word_mode, word_mode);
78 80
79 /* There is no need to restrict this code to loading items 81 /* There is no need to restrict this code to loading items
80 82Index: gcc-4_5-branch/gcc/common.opt
81=== modified file 'gcc/common.opt' 83===================================================================
82--- old/gcc/common.opt 2010-07-29 14:59:35 +0000 84--- gcc-4_5-branch.orig/gcc/common.opt 2012-03-06 13:05:48.400589618 -0800
83+++ new/gcc/common.opt 2010-11-04 12:43:52 +0000 85+++ gcc-4_5-branch/gcc/common.opt 2012-03-06 13:36:35.608679018 -0800
84@@ -613,6 +613,10 @@ 86@@ -613,6 +613,10 @@
85 Common Report Var(flag_loop_block) Optimization 87 Common Report Var(flag_loop_block) Optimization
86 Enable Loop Blocking transformation 88 Enable Loop Blocking transformation
@@ -92,10 +94,10 @@
92 fguess-branch-probability 94 fguess-branch-probability
93 Common Report Var(flag_guess_branch_prob) Optimization 95 Common Report Var(flag_guess_branch_prob) Optimization
94 Enable guessing of branch probabilities 96 Enable guessing of branch probabilities
95 97Index: gcc-4_5-branch/gcc/config/h8300/h8300.c
96=== modified file 'gcc/config/h8300/h8300.c' 98===================================================================
97--- old/gcc/config/h8300/h8300.c 2010-04-02 18:54:46 +0000 99--- gcc-4_5-branch.orig/gcc/config/h8300/h8300.c 2012-03-06 11:53:30.000000000 -0800
98+++ new/gcc/config/h8300/h8300.c 2010-11-04 12:43:52 +0000 100+++ gcc-4_5-branch/gcc/config/h8300/h8300.c 2012-03-06 13:36:35.528679014 -0800
99@@ -403,6 +403,10 @@ 101@@ -403,6 +403,10 @@
100 restore er6 though, so bump up the cost. */ 102 restore er6 though, so bump up the cost. */
101 h8300_move_ratio = 6; 103 h8300_move_ratio = 6;
@@ -107,10 +109,10 @@
107 } 109 }
108 110
109 /* Implement REG_CLASS_FROM_LETTER. 111 /* Implement REG_CLASS_FROM_LETTER.
110 112Index: gcc-4_5-branch/gcc/config/m32c/m32c.c
111=== modified file 'gcc/config/m32c/m32c.c' 113===================================================================
112--- old/gcc/config/m32c/m32c.c 2009-10-22 18:46:26 +0000 114--- gcc-4_5-branch.orig/gcc/config/m32c/m32c.c 2012-03-06 11:53:16.000000000 -0800
113+++ new/gcc/config/m32c/m32c.c 2010-11-04 12:43:52 +0000 115+++ gcc-4_5-branch/gcc/config/m32c/m32c.c 2012-03-06 13:36:35.488679012 -0800
114@@ -428,6 +428,10 @@ 116@@ -428,6 +428,10 @@
115 117
116 if (TARGET_A24) 118 if (TARGET_A24)
@@ -122,12 +124,12 @@
122 } 124 }
123 125
124 /* Defining data structures for per-function information */ 126 /* Defining data structures for per-function information */
125 127Index: gcc-4_5-branch/gcc/config/rx/rx.c
126=== modified file 'gcc/config/rx/rx.c' 128===================================================================
127--- old/gcc/config/rx/rx.c 2010-07-27 14:39:53 +0000 129--- gcc-4_5-branch.orig/gcc/config/rx/rx.c 2012-03-06 11:53:17.000000000 -0800
128+++ new/gcc/config/rx/rx.c 2010-11-04 12:43:52 +0000 130+++ gcc-4_5-branch/gcc/config/rx/rx.c 2012-03-06 13:36:35.508679013 -0800
129@@ -2187,6 +2187,14 @@ 131@@ -2417,6 +2417,14 @@
130 } 132 return ! TYPE_PACKED (record_type);
131 } 133 }
132 134
133+static void 135+static void
@@ -139,11 +141,11 @@
139+} 141+}
140+ 142+
141 143
142 static bool 144 /* Returns true if X a legitimate constant for an immediate
143 rx_allocate_stack_slots_for_args (void) 145 operand on the RX. X is already known to satisfy CONSTANT_P. */
144@@ -2759,6 +2767,9 @@ 146@@ -2794,6 +2802,9 @@
145 #undef TARGET_CC_MODES_COMPATIBLE 147 #undef TARGET_PROMOTE_FUNCTION_MODE
146 #define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible 148 #define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
147 149
148+#undef TARGET_OPTION_OVERRIDE 150+#undef TARGET_OPTION_OVERRIDE
149+#define TARGET_OPTION_OVERRIDE rx_option_override 151+#define TARGET_OPTION_OVERRIDE rx_option_override
@@ -151,10 +153,10 @@
151 struct gcc_target targetm = TARGET_INITIALIZER; 153 struct gcc_target targetm = TARGET_INITIALIZER;
152 154
153 /* #include "gt-rx.h" */ 155 /* #include "gt-rx.h" */
154 156Index: gcc-4_5-branch/gcc/config/sh/sh.c
155=== modified file 'gcc/config/sh/sh.c' 157===================================================================
156--- old/gcc/config/sh/sh.c 2010-05-05 21:12:17 +0000 158--- gcc-4_5-branch.orig/gcc/config/sh/sh.c 2012-03-06 11:53:20.000000000 -0800
157+++ new/gcc/config/sh/sh.c 2010-11-04 12:43:52 +0000 159+++ gcc-4_5-branch/gcc/config/sh/sh.c 2012-03-06 13:36:35.516679013 -0800
158@@ -950,6 +950,10 @@ 160@@ -950,6 +950,10 @@
159 161
160 if (sh_fixed_range_str) 162 if (sh_fixed_range_str)
@@ -166,10 +168,10 @@
166 } 168 }
167 169
168 /* Print the operand address in x to the stream. */ 170 /* Print the operand address in x to the stream. */
169 171Index: gcc-4_5-branch/gcc/doc/invoke.texi
170=== modified file 'gcc/doc/invoke.texi' 172===================================================================
171--- old/gcc/doc/invoke.texi 2010-10-04 00:50:43 +0000 173--- gcc-4_5-branch.orig/gcc/doc/invoke.texi 2012-03-06 13:05:56.988590034 -0800
172+++ new/gcc/doc/invoke.texi 2010-11-04 12:43:52 +0000 174+++ gcc-4_5-branch/gcc/doc/invoke.texi 2012-03-06 13:36:36.048679039 -0800
173@@ -922,7 +922,7 @@ 175@@ -922,7 +922,7 @@
174 -fargument-noalias-global -fargument-noalias-anything @gol 176 -fargument-noalias-global -fargument-noalias-anything @gol
175 -fleading-underscore -ftls-model=@var{model} @gol 177 -fleading-underscore -ftls-model=@var{model} @gol
@@ -213,10 +215,10 @@
213 @end table 215 @end table
214 216
215 @c man end 217 @c man end
216 218Index: gcc-4_5-branch/gcc/expmed.c
217=== modified file 'gcc/expmed.c' 219===================================================================
218--- old/gcc/expmed.c 2010-10-04 00:50:43 +0000 220--- gcc-4_5-branch.orig/gcc/expmed.c 2012-03-06 13:05:56.876590028 -0800
219+++ new/gcc/expmed.c 2010-11-04 12:43:52 +0000 221+++ gcc-4_5-branch/gcc/expmed.c 2012-03-06 13:36:35.104678993 -0800
220@@ -47,7 +47,7 @@ 222@@ -47,7 +47,7 @@
221 static rtx extract_fixed_bit_field (enum machine_mode, rtx, 223 static rtx extract_fixed_bit_field (enum machine_mode, rtx,
222 unsigned HOST_WIDE_INT, 224 unsigned HOST_WIDE_INT,
@@ -458,10 +460,10 @@
458 bitsdone += thissize; 460 bitsdone += thissize;
459 461
460 /* Shift this part into place for the result. */ 462 /* Shift this part into place for the result. */
461 463Index: gcc-4_5-branch/gcc/expr.c
462=== modified file 'gcc/expr.c' 464===================================================================
463--- old/gcc/expr.c 2010-10-04 00:50:43 +0000 465--- gcc-4_5-branch.orig/gcc/expr.c 2012-03-06 13:05:57.720590069 -0800
464+++ new/gcc/expr.c 2010-11-04 12:43:52 +0000 466+++ gcc-4_5-branch/gcc/expr.c 2012-03-06 13:40:14.504689612 -0800
465@@ -1749,7 +1749,7 @@ 467@@ -1749,7 +1749,7 @@
466 && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode)) 468 && (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode))
467 tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT, 469 tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
@@ -498,7 +500,16 @@
498 NULL_RTX, copy_mode, copy_mode)); 500 NULL_RTX, copy_mode, copy_mode));
499 } 501 }
500 502
501@@ -2970,7 +2970,7 @@ 503@@ -2291,7 +2291,7 @@
504 xbitpos for the destination store (right justified). */
505 store_bit_field (dst_word, bitsize, xbitpos % BITS_PER_WORD, word_mode,
506 extract_bit_field (src_word, bitsize,
507- bitpos % BITS_PER_WORD, 1,
508+ bitpos % BITS_PER_WORD, 1, false,
509 NULL_RTX, word_mode, word_mode));
510 }
511
512@@ -3075,7 +3075,7 @@
502 } 513 }
503 514
504 return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0, 515 return extract_bit_field (cplx, ibitsize, imag_p ? ibitsize : 0,
@@ -507,7 +518,7 @@
507 } 518 }
508 519
509 /* A subroutine of emit_move_insn_1. Yet another lowpart generator. 520 /* A subroutine of emit_move_insn_1. Yet another lowpart generator.
510@@ -4233,6 +4233,13 @@ 521@@ -4338,6 +4338,13 @@
511 522
512 to_rtx = expand_normal (tem); 523 to_rtx = expand_normal (tem);
513 524
@@ -517,11 +528,11 @@
517+ && GET_CODE (to_rtx) == MEM 528+ && GET_CODE (to_rtx) == MEM
518+ && flag_strict_volatile_bitfields > 0) 529+ && flag_strict_volatile_bitfields > 0)
519+ to_rtx = adjust_address (to_rtx, mode1, 0); 530+ to_rtx = adjust_address (to_rtx, mode1, 0);
520+ 531+
521 if (offset != 0) 532 if (offset != 0)
522 { 533 {
523 enum machine_mode address_mode; 534 enum machine_mode address_mode;
524@@ -5993,6 +6000,12 @@ 535@@ -6106,6 +6113,12 @@
525 mode = DECL_MODE (field); 536 mode = DECL_MODE (field);
526 else if (DECL_MODE (field) == BLKmode) 537 else if (DECL_MODE (field) == BLKmode)
527 blkmode_bitfield = true; 538 blkmode_bitfield = true;
@@ -534,7 +545,7 @@
534 545
535 *punsignedp = DECL_UNSIGNED (field); 546 *punsignedp = DECL_UNSIGNED (field);
536 } 547 }
537@@ -8848,6 +8861,7 @@ 548@@ -8978,6 +8991,7 @@
538 HOST_WIDE_INT bitsize, bitpos; 549 HOST_WIDE_INT bitsize, bitpos;
539 tree offset; 550 tree offset;
540 int volatilep = 0, must_force_mem; 551 int volatilep = 0, must_force_mem;
@@ -542,7 +553,7 @@
542 tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset, 553 tree tem = get_inner_reference (exp, &bitsize, &bitpos, &offset,
543 &mode1, &unsignedp, &volatilep, true); 554 &mode1, &unsignedp, &volatilep, true);
544 rtx orig_op0, memloc; 555 rtx orig_op0, memloc;
545@@ -8857,6 +8871,11 @@ 556@@ -8987,6 +9001,11 @@
546 infinitely recurse. */ 557 infinitely recurse. */
547 gcc_assert (tem != exp); 558 gcc_assert (tem != exp);
548 559
@@ -554,7 +565,7 @@
554 /* If TEM's type is a union of variable size, pass TARGET to the inner 565 /* If TEM's type is a union of variable size, pass TARGET to the inner
555 computation, since it will need a temporary and TARGET is known 566 computation, since it will need a temporary and TARGET is known
556 to have to do. This occurs in unchecked conversion in Ada. */ 567 to have to do. This occurs in unchecked conversion in Ada. */
557@@ -8873,6 +8892,14 @@ 568@@ -9003,6 +9022,14 @@
558 || modifier == EXPAND_STACK_PARM) 569 || modifier == EXPAND_STACK_PARM)
559 ? modifier : EXPAND_NORMAL); 570 ? modifier : EXPAND_NORMAL);
560 571
@@ -569,7 +580,7 @@
569 mode2 580 mode2
570 = CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0); 581 = CONSTANT_P (op0) ? TYPE_MODE (TREE_TYPE (tem)) : GET_MODE (op0);
571 582
572@@ -8998,6 +9025,9 @@ 583@@ -9128,6 +9155,9 @@
573 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT 584 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
574 && modifier != EXPAND_CONST_ADDRESS 585 && modifier != EXPAND_CONST_ADDRESS
575 && modifier != EXPAND_INITIALIZER) 586 && modifier != EXPAND_INITIALIZER)
@@ -579,7 +590,7 @@
579 /* If the field isn't aligned enough to fetch as a memref, 590 /* If the field isn't aligned enough to fetch as a memref,
580 fetch it as a bit field. */ 591 fetch it as a bit field. */
581 || (mode1 != BLKmode 592 || (mode1 != BLKmode
582@@ -9058,7 +9088,7 @@ 593@@ -9188,7 +9218,7 @@
583 if (MEM_P (op0) && REG_P (XEXP (op0, 0))) 594 if (MEM_P (op0) && REG_P (XEXP (op0, 0)))
584 mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0)); 595 mark_reg_pointer (XEXP (op0, 0), MEM_ALIGN (op0));
585 596
@@ -588,11 +599,11 @@
588 (modifier == EXPAND_STACK_PARM 599 (modifier == EXPAND_STACK_PARM
589 ? NULL_RTX : target), 600 ? NULL_RTX : target),
590 ext_mode, ext_mode); 601 ext_mode, ext_mode);
591 602Index: gcc-4_5-branch/gcc/expr.h
592=== modified file 'gcc/expr.h' 603===================================================================
593--- old/gcc/expr.h 2010-02-19 09:53:51 +0000 604--- gcc-4_5-branch.orig/gcc/expr.h 2012-03-06 11:53:32.000000000 -0800
594+++ new/gcc/expr.h 2010-11-04 12:43:52 +0000 605+++ gcc-4_5-branch/gcc/expr.h 2012-03-06 13:05:59.668590163 -0800
595@@ -802,7 +802,7 @@ 606@@ -804,7 +804,7 @@
596 extern void store_bit_field (rtx, unsigned HOST_WIDE_INT, 607 extern void store_bit_field (rtx, unsigned HOST_WIDE_INT,
597 unsigned HOST_WIDE_INT, enum machine_mode, rtx); 608 unsigned HOST_WIDE_INT, enum machine_mode, rtx);
598 extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT, 609 extern rtx extract_bit_field (rtx, unsigned HOST_WIDE_INT,
@@ -601,11 +612,11 @@
601 enum machine_mode, enum machine_mode); 612 enum machine_mode, enum machine_mode);
602 extern rtx extract_low_bits (enum machine_mode, enum machine_mode, rtx); 613 extern rtx extract_low_bits (enum machine_mode, enum machine_mode, rtx);
603 extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int); 614 extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int);
604 615Index: gcc-4_5-branch/gcc/fold-const.c
605=== modified file 'gcc/fold-const.c' 616===================================================================
606--- old/gcc/fold-const.c 2010-10-04 00:50:43 +0000 617--- gcc-4_5-branch.orig/gcc/fold-const.c 2012-03-06 13:05:56.880590028 -0800
607+++ new/gcc/fold-const.c 2010-11-04 12:43:52 +0000 618+++ gcc-4_5-branch/gcc/fold-const.c 2012-03-06 13:36:03.276677454 -0800
608@@ -4208,11 +4208,16 @@ 619@@ -4215,11 +4215,16 @@
609 620
610 /* See if we can find a mode to refer to this field. We should be able to, 621 /* See if we can find a mode to refer to this field. We should be able to,
611 but fail if we can't. */ 622 but fail if we can't. */
@@ -627,11 +638,11 @@
627 if (nmode == VOIDmode) 638 if (nmode == VOIDmode)
628 return 0; 639 return 0;
629 640
630 641Index: gcc-4_5-branch/gcc/stmt.c
631=== modified file 'gcc/stmt.c' 642===================================================================
632--- old/gcc/stmt.c 2010-08-13 11:53:46 +0000 643--- gcc-4_5-branch.orig/gcc/stmt.c 2012-03-06 13:05:54.568589917 -0800
633+++ new/gcc/stmt.c 2010-11-04 12:43:52 +0000 644+++ gcc-4_5-branch/gcc/stmt.c 2012-03-06 13:36:34.948678986 -0800
634@@ -1751,7 +1751,7 @@ 645@@ -1754,7 +1754,7 @@
635 xbitpos for the destination store (right justified). */ 646 xbitpos for the destination store (right justified). */
636 store_bit_field (dst, bitsize, xbitpos % BITS_PER_WORD, word_mode, 647 store_bit_field (dst, bitsize, xbitpos % BITS_PER_WORD, word_mode,
637 extract_bit_field (src, bitsize, 648 extract_bit_field (src, bitsize,
@@ -640,10 +651,10 @@
640 NULL_RTX, word_mode, word_mode)); 651 NULL_RTX, word_mode, word_mode));
641 } 652 }
642 653
643 654Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
644=== added file 'gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c' 655===================================================================
645--- old/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c 1970-01-01 00:00:00 +0000 656--- /dev/null 1970-01-01 00:00:00.000000000 +0000
646+++ new/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c 2010-11-04 12:43:52 +0000 657+++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c 2012-03-06 13:05:59.672590164 -0800
647@@ -0,0 +1,17 @@ 658@@ -0,0 +1,17 @@
648+/* { dg-do compile } */ 659+/* { dg-do compile } */
649+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */ 660+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
@@ -662,10 +673,10 @@
662+} 673+}
663+ 674+
664+/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */ 675+/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */
665 676Index: gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c
666=== added file 'gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c' 677===================================================================
667--- old/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c 1970-01-01 00:00:00 +0000 678--- /dev/null 1970-01-01 00:00:00.000000000 +0000
668+++ new/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c 2010-11-04 12:43:52 +0000 679+++ gcc-4_5-branch/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c 2012-03-06 13:05:59.672590164 -0800
669@@ -0,0 +1,17 @@ 680@@ -0,0 +1,17 @@
670+/* { dg-do compile } */ 681+/* { dg-do compile } */
671+/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */ 682+/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */
@@ -684,4 +695,3 @@
684+} 695+}
685+ 696+
686+/* { dg-final { scan-assembler "movl.*bits" } } */ 697+/* { dg-final { scan-assembler "movl.*bits" } } */
687
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
index ec0eebdf04..337b055805 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
@@ -99,7 +99,7 @@
99Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml 99Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
100=================================================================== 100===================================================================
101--- /dev/null 1970-01-01 00:00:00.000000000 +0000 101--- /dev/null 1970-01-01 00:00:00.000000000 +0000
102+++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml 2011-06-16 18:46:26.355282255 -0700 102+++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml 2012-03-06 12:51:19.980547615 -0800
103@@ -0,0 +1,333 @@ 103@@ -0,0 +1,333 @@
104+(* Auto-generate ARM ldm/stm patterns 104+(* Auto-generate ARM ldm/stm patterns
105+ Copyright (C) 2010 Free Software Foundation, Inc. 105+ Copyright (C) 2010 Free Software Foundation, Inc.
@@ -436,8 +436,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
436+ patterns (); 436+ patterns ();
437Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h 437Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
438=================================================================== 438===================================================================
439--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h 2011-06-16 18:46:18.000000000 -0700 439--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h 2012-03-06 12:47:54.000000000 -0800
440+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h 2011-06-16 18:46:26.355282255 -0700 440+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h 2012-03-06 12:51:19.980547615 -0800
441@@ -99,14 +99,11 @@ 441@@ -99,14 +99,11 @@
442 extern int label_mentioned_p (rtx); 442 extern int label_mentioned_p (rtx);
443 extern RTX_CODE minmax_code (rtx); 443 extern RTX_CODE minmax_code (rtx);
@@ -460,8 +460,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
460 extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, 460 extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
461Index: gcc-4_5-branch/gcc/config/arm/arm.c 461Index: gcc-4_5-branch/gcc/config/arm/arm.c
462=================================================================== 462===================================================================
463--- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2011-06-16 18:46:23.000000000 -0700 463--- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2012-03-06 12:47:56.000000000 -0800
464+++ gcc-4_5-branch/gcc/config/arm/arm.c 2011-06-16 18:46:26.365282255 -0700 464+++ gcc-4_5-branch/gcc/config/arm/arm.c 2012-03-06 12:51:19.988547639 -0800
465@@ -753,6 +753,12 @@ 465@@ -753,6 +753,12 @@
466 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" 466 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
467 }; 467 };
@@ -475,7 +475,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
475 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") 475 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
476 #define streq(string1, string2) (strcmp (string1, string2) == 0) 476 #define streq(string1, string2) (strcmp (string1, string2) == 0)
477 477
478@@ -9668,24 +9674,125 @@ 478@@ -9647,24 +9653,125 @@
479 return 0; 479 return 0;
480 } 480 }
481 481
@@ -612,7 +612,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
612 612
613 /* Loop over the operands and check that the memory references are 613 /* Loop over the operands and check that the memory references are
614 suitable (i.e. immediate offsets from the same base register). At 614 suitable (i.e. immediate offsets from the same base register). At
615@@ -9723,32 +9830,30 @@ 615@@ -9702,32 +9809,30 @@
616 if (i == 0) 616 if (i == 0)
617 { 617 {
618 base_reg = REGNO (reg); 618 base_reg = REGNO (reg);
@@ -659,7 +659,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
659 } 659 }
660 else 660 else
661 /* Not a suitable memory address. */ 661 /* Not a suitable memory address. */
662@@ -9757,167 +9862,90 @@ 662@@ -9736,167 +9841,90 @@
663 663
664 /* All the useful information has now been extracted from the 664 /* All the useful information has now been extracted from the
665 operands into unsorted_regs and unsorted_offsets; additionally, 665 operands into unsorted_regs and unsorted_offsets; additionally,
@@ -888,7 +888,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
888 888
889 /* Loop over the operands and check that the memory references are 889 /* Loop over the operands and check that the memory references are
890 suitable (i.e. immediate offsets from the same base register). At 890 suitable (i.e. immediate offsets from the same base register). At
891@@ -9952,32 +9980,32 @@ 891@@ -9931,32 +9959,32 @@
892 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 892 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
893 == CONST_INT))) 893 == CONST_INT)))
894 { 894 {
@@ -937,7 +937,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
937 } 937 }
938 else 938 else
939 /* Not a suitable memory address. */ 939 /* Not a suitable memory address. */
940@@ -9986,111 +10014,65 @@ 940@@ -9965,111 +9993,65 @@
941 941
942 /* All the useful information has now been extracted from the 942 /* All the useful information has now been extracted from the
943 operands into unsorted_regs and unsorted_offsets; additionally, 943 operands into unsorted_regs and unsorted_offsets; additionally,
@@ -1087,7 +1087,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1087 1087
1088 /* XScale has load-store double instructions, but they have stricter 1088 /* XScale has load-store double instructions, but they have stricter
1089 alignment requirements than load-store multiple, so we cannot 1089 alignment requirements than load-store multiple, so we cannot
1090@@ -10127,18 +10109,10 @@ 1090@@ -10106,18 +10088,10 @@
1091 start_sequence (); 1091 start_sequence ();
1092 1092
1093 for (i = 0; i < count; i++) 1093 for (i = 0; i < count; i++)
@@ -1109,7 +1109,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1109 1109
1110 seq = get_insns (); 1110 seq = get_insns ();
1111 end_sequence (); 1111 end_sequence ();
1112@@ -10147,41 +10121,40 @@ 1112@@ -10126,41 +10100,40 @@
1113 } 1113 }
1114 1114
1115 result = gen_rtx_PARALLEL (VOIDmode, 1115 result = gen_rtx_PARALLEL (VOIDmode,
@@ -1170,7 +1170,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1170 the pros/cons of ldm/stm usage for XScale. */ 1170 the pros/cons of ldm/stm usage for XScale. */
1171 if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size)) 1171 if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
1172 { 1172 {
1173@@ -10190,18 +10163,10 @@ 1173@@ -10169,18 +10142,10 @@
1174 start_sequence (); 1174 start_sequence ();
1175 1175
1176 for (i = 0; i < count; i++) 1176 for (i = 0; i < count; i++)
@@ -1192,7 +1192,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1192 1192
1193 seq = get_insns (); 1193 seq = get_insns ();
1194 end_sequence (); 1194 end_sequence ();
1195@@ -10210,29 +10175,319 @@ 1195@@ -10189,29 +10154,319 @@
1196 } 1196 }
1197 1197
1198 result = gen_rtx_PARALLEL (VOIDmode, 1198 result = gen_rtx_PARALLEL (VOIDmode,
@@ -1522,7 +1522,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1522 } 1522 }
1523 1523
1524 int 1524 int
1525@@ -10268,20 +10523,21 @@ 1525@@ -10247,20 +10502,21 @@
1526 for (i = 0; in_words_to_go >= 2; i+=4) 1526 for (i = 0; in_words_to_go >= 2; i+=4)
1527 { 1527 {
1528 if (in_words_to_go > 4) 1528 if (in_words_to_go > 4)
@@ -1554,8 +1554,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
1554 dstbase, &dstoffset)); 1554 dstbase, &dstoffset));
1555Index: gcc-4_5-branch/gcc/config/arm/arm.h 1555Index: gcc-4_5-branch/gcc/config/arm/arm.h
1556=================================================================== 1556===================================================================
1557--- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2011-06-16 18:46:20.000000000 -0700 1557--- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2012-03-06 12:47:55.000000000 -0800
1558+++ gcc-4_5-branch/gcc/config/arm/arm.h 2011-06-16 18:46:26.375282255 -0700 1558+++ gcc-4_5-branch/gcc/config/arm/arm.h 2012-03-06 12:51:19.988547639 -0800
1559@@ -1143,6 +1143,9 @@ 1559@@ -1143,6 +1143,9 @@
1560 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1560 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1561 || (MODE) == CImode || (MODE) == XImode) 1561 || (MODE) == CImode || (MODE) == XImode)
@@ -1577,8 +1577,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
1577 #endif /* ! GCC_ARM_H */ 1577 #endif /* ! GCC_ARM_H */
1578Index: gcc-4_5-branch/gcc/config/arm/arm.md 1578Index: gcc-4_5-branch/gcc/config/arm/arm.md
1579=================================================================== 1579===================================================================
1580--- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2011-06-16 18:46:23.000000000 -0700 1580--- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2012-03-06 12:47:56.000000000 -0800
1581+++ gcc-4_5-branch/gcc/config/arm/arm.md 2011-06-16 18:46:26.375282255 -0700 1581+++ gcc-4_5-branch/gcc/config/arm/arm.md 2012-03-06 12:51:19.992547622 -0800
1582@@ -6282,7 +6282,7 @@ 1582@@ -6282,7 +6282,7 @@
1583 1583
1584 ;; load- and store-multiple insns 1584 ;; load- and store-multiple insns
@@ -1969,7 +1969,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
1969Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md 1969Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
1970=================================================================== 1970===================================================================
1971--- /dev/null 1970-01-01 00:00:00.000000000 +0000 1971--- /dev/null 1970-01-01 00:00:00.000000000 +0000
1972+++ gcc-4_5-branch/gcc/config/arm/ldmstm.md 2011-06-16 18:46:26.375282255 -0700 1972+++ gcc-4_5-branch/gcc/config/arm/ldmstm.md 2012-03-06 12:51:19.992547622 -0800
1973@@ -0,0 +1,1191 @@ 1973@@ -0,0 +1,1191 @@
1974+/* ARM ldm/stm instruction patterns. This file was automatically generated 1974+/* ARM ldm/stm instruction patterns. This file was automatically generated
1975+ using arm-ldmstm.ml. Please do not edit manually. 1975+ using arm-ldmstm.ml. Please do not edit manually.
@@ -3164,8 +3164,8 @@ Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
3164+ 3164+
3165Index: gcc-4_5-branch/gcc/config/arm/predicates.md 3165Index: gcc-4_5-branch/gcc/config/arm/predicates.md
3166=================================================================== 3166===================================================================
3167--- gcc-4_5-branch.orig/gcc/config/arm/predicates.md 2011-06-16 18:46:18.000000000 -0700 3167--- gcc-4_5-branch.orig/gcc/config/arm/predicates.md 2012-03-06 12:47:54.000000000 -0800
3168+++ gcc-4_5-branch/gcc/config/arm/predicates.md 2011-06-16 18:46:26.375282255 -0700 3168+++ gcc-4_5-branch/gcc/config/arm/predicates.md 2012-03-06 12:51:19.992547622 -0800
3169@@ -211,6 +211,11 @@ 3169@@ -211,6 +211,11 @@
3170 (and (match_code "ior,xor,and") 3170 (and (match_code "ior,xor,and")
3171 (match_test "mode == GET_MODE (op)"))) 3171 (match_test "mode == GET_MODE (op)")))
@@ -3314,8 +3314,8 @@ Index: gcc-4_5-branch/gcc/config/arm/predicates.md
3314 return true; 3314 return true;
3315Index: gcc-4_5-branch/gcc/config/i386/i386.md 3315Index: gcc-4_5-branch/gcc/config/i386/i386.md
3316=================================================================== 3316===================================================================
3317--- gcc-4_5-branch.orig/gcc/config/i386/i386.md 2011-06-16 18:46:21.000000000 -0700 3317--- gcc-4_5-branch.orig/gcc/config/i386/i386.md 2012-03-06 12:47:55.000000000 -0800
3318+++ gcc-4_5-branch/gcc/config/i386/i386.md 2011-06-16 18:46:26.385282255 -0700 3318+++ gcc-4_5-branch/gcc/config/i386/i386.md 2012-03-06 12:51:19.996547605 -0800
3319@@ -4960,6 +4960,7 @@ 3319@@ -4960,6 +4960,7 @@
3320 (set (match_operand:SSEMODEI24 2 "register_operand" "") 3320 (set (match_operand:SSEMODEI24 2 "register_operand" "")
3321 (fix:SSEMODEI24 (match_dup 0)))] 3321 (fix:SSEMODEI24 (match_dup 0)))]
@@ -3324,7 +3324,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
3324 && peep2_reg_dead_p (2, operands[0])" 3324 && peep2_reg_dead_p (2, operands[0])"
3325 [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))] 3325 [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
3326 "") 3326 "")
3327@@ -20057,15 +20058,14 @@ 3327@@ -20089,15 +20090,14 @@
3328 ;; leal (%edx,%eax,4), %eax 3328 ;; leal (%edx,%eax,4), %eax
3329 3329
3330 (define_peephole2 3330 (define_peephole2
@@ -3345,7 +3345,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
3345 (clobber (reg:CC FLAGS_REG))])] 3345 (clobber (reg:CC FLAGS_REG))])]
3346 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3 3346 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
3347 /* Validate MODE for lea. */ 3347 /* Validate MODE for lea. */
3348@@ -20074,31 +20074,27 @@ 3348@@ -20106,31 +20106,27 @@
3349 || GET_MODE (operands[0]) == HImode)) 3349 || GET_MODE (operands[0]) == HImode))
3350 || GET_MODE (operands[0]) == SImode 3350 || GET_MODE (operands[0]) == SImode
3351 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)) 3351 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
@@ -3391,8 +3391,8 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
3391 3391
3392Index: gcc-4_5-branch/gcc/genoutput.c 3392Index: gcc-4_5-branch/gcc/genoutput.c
3393=================================================================== 3393===================================================================
3394--- gcc-4_5-branch.orig/gcc/genoutput.c 2011-06-16 17:59:04.000000000 -0700 3394--- gcc-4_5-branch.orig/gcc/genoutput.c 2012-03-06 11:53:32.000000000 -0800
3395+++ gcc-4_5-branch/gcc/genoutput.c 2011-06-16 18:46:26.385282255 -0700 3395+++ gcc-4_5-branch/gcc/genoutput.c 2012-03-06 12:51:20.000547582 -0800
3396@@ -266,6 +266,8 @@ 3396@@ -266,6 +266,8 @@
3397 3397
3398 printf (" %d,\n", d->strict_low); 3398 printf (" %d,\n", d->strict_low);
@@ -3404,8 +3404,8 @@ Index: gcc-4_5-branch/gcc/genoutput.c
3404 printf(" },\n"); 3404 printf(" },\n");
3405Index: gcc-4_5-branch/gcc/genrecog.c 3405Index: gcc-4_5-branch/gcc/genrecog.c
3406=================================================================== 3406===================================================================
3407--- gcc-4_5-branch.orig/gcc/genrecog.c 2011-06-16 17:59:04.000000000 -0700 3407--- gcc-4_5-branch.orig/gcc/genrecog.c 2012-03-06 11:53:32.000000000 -0800
3408+++ gcc-4_5-branch/gcc/genrecog.c 2011-06-16 18:46:26.395282255 -0700 3408+++ gcc-4_5-branch/gcc/genrecog.c 2012-03-06 12:51:20.000547582 -0800
3409@@ -1782,20 +1782,11 @@ 3409@@ -1782,20 +1782,11 @@
3410 int odepth = strlen (oldpos); 3410 int odepth = strlen (oldpos);
3411 int ndepth = strlen (newpos); 3411 int ndepth = strlen (newpos);
@@ -3429,8 +3429,8 @@ Index: gcc-4_5-branch/gcc/genrecog.c
3429 { 3429 {
3430Index: gcc-4_5-branch/gcc/recog.c 3430Index: gcc-4_5-branch/gcc/recog.c
3431=================================================================== 3431===================================================================
3432--- gcc-4_5-branch.orig/gcc/recog.c 2011-06-16 18:46:02.000000000 -0700 3432--- gcc-4_5-branch.orig/gcc/recog.c 2012-03-06 12:47:48.000000000 -0800
3433+++ gcc-4_5-branch/gcc/recog.c 2011-06-16 18:46:26.395282255 -0700 3433+++ gcc-4_5-branch/gcc/recog.c 2012-03-06 13:04:05.780584592 -0800
3434@@ -2082,6 +2082,7 @@ 3434@@ -2082,6 +2082,7 @@
3435 recog_data.operand_loc, 3435 recog_data.operand_loc,
3436 recog_data.constraints, 3436 recog_data.constraints,
@@ -3508,7 +3508,7 @@ Index: gcc-4_5-branch/gcc/recog.c
3508 3508
3509 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); 3509 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
3510 3510
3511@@ -2996,12 +3006,8 @@ 3511@@ -2997,12 +3007,8 @@
3512 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); 3512 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
3513 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); 3513 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
3514 3514
@@ -3523,17 +3523,17 @@ Index: gcc-4_5-branch/gcc/recog.c
3523 3523
3524 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3524 gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
3525 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); 3525 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3526@@ -3010,8 +3016,7 @@ 3526@@ -3016,8 +3022,7 @@
3527 { 3527 *def_rec; def_rec++)
3528 HARD_REG_SET this_live; 3528 SET_HARD_REG_BIT (live, DF_REF_REGNO (*def_rec));
3529 3529
3530- if (++from >= MAX_INSNS_PER_PEEP2 + 1) 3530- if (++from >= MAX_INSNS_PER_PEEP2 + 1)
3531- from = 0; 3531- from = 0;
3532+ from = peep2_buf_position (from + 1); 3532+ from = peep2_buf_position (from + 1);
3533 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3533 }
3534 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before); 3534
3535 IOR_HARD_REG_SET (live, this_live); 3535 cl = (class_str[0] == 'r' ? GENERAL_REGS
3536@@ -3104,19 +3109,234 @@ 3536@@ -3107,19 +3112,234 @@
3537 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); 3537 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3538 } 3538 }
3539 3539
@@ -3771,7 +3771,7 @@ Index: gcc-4_5-branch/gcc/recog.c
3771 df_analyze (); 3771 df_analyze ();
3772 3772
3773 /* Initialize the regsets we're going to use. */ 3773 /* Initialize the regsets we're going to use. */
3774@@ -3126,214 +3346,59 @@ 3774@@ -3129,214 +3349,59 @@
3775 3775
3776 FOR_EACH_BB_REVERSE (bb) 3776 FOR_EACH_BB_REVERSE (bb)
3777 { 3777 {
@@ -4028,7 +4028,7 @@ Index: gcc-4_5-branch/gcc/recog.c
4028 } 4028 }
4029 } 4029 }
4030 4030
4031@@ -3341,7 +3406,7 @@ 4031@@ -3344,7 +3409,7 @@
4032 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 4032 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
4033 BITMAP_FREE (peep2_insn_data[i].live_before); 4033 BITMAP_FREE (peep2_insn_data[i].live_before);
4034 BITMAP_FREE (live); 4034 BITMAP_FREE (live);
@@ -4039,8 +4039,8 @@ Index: gcc-4_5-branch/gcc/recog.c
4039 #endif /* HAVE_peephole2 */ 4039 #endif /* HAVE_peephole2 */
4040Index: gcc-4_5-branch/gcc/recog.h 4040Index: gcc-4_5-branch/gcc/recog.h
4041=================================================================== 4041===================================================================
4042--- gcc-4_5-branch.orig/gcc/recog.h 2011-06-16 17:59:04.000000000 -0700 4042--- gcc-4_5-branch.orig/gcc/recog.h 2012-03-06 11:53:32.000000000 -0800
4043+++ gcc-4_5-branch/gcc/recog.h 2011-06-16 18:46:26.405282255 -0700 4043+++ gcc-4_5-branch/gcc/recog.h 2012-03-06 12:51:20.000547582 -0800
4044@@ -194,6 +194,9 @@ 4044@@ -194,6 +194,9 @@
4045 /* Gives the constraint string for operand N. */ 4045 /* Gives the constraint string for operand N. */
4046 const char *constraints[MAX_RECOG_OPERANDS]; 4046 const char *constraints[MAX_RECOG_OPERANDS];
@@ -4062,8 +4062,8 @@ Index: gcc-4_5-branch/gcc/recog.h
4062 4062
4063Index: gcc-4_5-branch/gcc/reload.c 4063Index: gcc-4_5-branch/gcc/reload.c
4064=================================================================== 4064===================================================================
4065--- gcc-4_5-branch.orig/gcc/reload.c 2011-06-16 17:59:04.000000000 -0700 4065--- gcc-4_5-branch.orig/gcc/reload.c 2012-03-06 11:53:32.000000000 -0800
4066+++ gcc-4_5-branch/gcc/reload.c 2011-06-16 18:46:26.405282255 -0700 4066+++ gcc-4_5-branch/gcc/reload.c 2012-03-06 12:51:20.004547561 -0800
4067@@ -3631,7 +3631,7 @@ 4067@@ -3631,7 +3631,7 @@
4068 || modified[j] != RELOAD_WRITE) 4068 || modified[j] != RELOAD_WRITE)
4069 && j != i 4069 && j != i
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-02-13 08:55:23 +0000