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authorKhem Raj <raj.khem@gmail.com>2011-09-29 22:12:52 +0000
committerKoen Kooi <koen@dominion.thruhere.net>2011-10-04 13:48:57 +0200
commitb9b5306e551f26d76e9dc5fa6f10c2c095fe6e0f (patch)
tree3908112a2010485903e16f9f7fec5d0fec2a37fa /meta-oe/recipes-devtools/gcc/gcc-4.6/linaro
parent9f2e55480dc94e90ac09ca468cf2f0dacb54ae2d (diff)
downloadmeta-openembedded-b9b5306e551f26d76e9dc5fa6f10c2c095fe6e0f.tar.gz
gcc-4.6: Bring in latest linaro patches
Adjust existing patches for latest FSF gcc-4_6-branch Signed-off-by: Khem Raj <raj.khem@gmail.com> Acked-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Diffstat (limited to 'meta-oe/recipes-devtools/gcc/gcc-4.6/linaro')
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch49
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch3142
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch80
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch185
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch62
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch458
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch39
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch94
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch30
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch33
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch61
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106793.patch34
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch2648
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch1255
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch23
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch23
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch75
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch1270
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch948
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch201
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch38
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch47
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch92
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch767
-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch203
25 files changed, 10073 insertions, 1784 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
index 84f6f64989..f53b26a888 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106741.patch
@@ -17,8 +17,10 @@
17 for STORE_FLAG_VALUE==-1 case. 17 for STORE_FLAG_VALUE==-1 case.
18 18
19=== modified file 'gcc/combine.c' 19=== modified file 'gcc/combine.c'
20--- old/gcc/combine.c 2011-02-15 19:46:26 +0000 20Index: gcc-4_6-branch/gcc/combine.c
21+++ new/gcc/combine.c 2011-04-26 17:03:58 +0000 21===================================================================
22--- gcc-4_6-branch.orig/gcc/combine.c 2011-09-16 19:58:21.000000000 -0700
23+++ gcc-4_6-branch/gcc/combine.c 2011-09-16 20:05:36.626650681 -0700
22@@ -391,8 +391,8 @@ 24@@ -391,8 +391,8 @@
23 static void undo_all (void); 25 static void undo_all (void);
24 static void undo_commit (void); 26 static void undo_commit (void);
@@ -30,7 +32,7 @@
30 static rtx simplify_if_then_else (rtx); 32 static rtx simplify_if_then_else (rtx);
31 static rtx simplify_set (rtx); 33 static rtx simplify_set (rtx);
32 static rtx simplify_logical (rtx); 34 static rtx simplify_logical (rtx);
33@@ -3086,12 +3086,12 @@ 35@@ -3112,12 +3112,12 @@
34 if (i1) 36 if (i1)
35 { 37 {
36 subst_low_luid = DF_INSN_LUID (i1); 38 subst_low_luid = DF_INSN_LUID (i1);
@@ -45,7 +47,7 @@
45 } 47 }
46 } 48 }
47 49
48@@ -3103,7 +3103,7 @@ 50@@ -3129,7 +3129,7 @@
49 self-referential RTL when we will be substituting I1SRC for I1DEST 51 self-referential RTL when we will be substituting I1SRC for I1DEST
50 later. Likewise if I0 feeds into I2, either directly or indirectly 52 later. Likewise if I0 feeds into I2, either directly or indirectly
51 through I1, and I0DEST is in I0SRC. */ 53 through I1, and I0DEST is in I0SRC. */
@@ -54,7 +56,7 @@
54 (i1_feeds_i2_n && i1dest_in_i1src) 56 (i1_feeds_i2_n && i1dest_in_i1src)
55 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n)) 57 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
56 && i0dest_in_i0src)); 58 && i0dest_in_i0src));
57@@ -3142,7 +3142,7 @@ 59@@ -3168,7 +3168,7 @@
58 copy of I1SRC each time we substitute it, in order to avoid creating 60 copy of I1SRC each time we substitute it, in order to avoid creating
59 self-referential RTL when we will be substituting I0SRC for I0DEST 61 self-referential RTL when we will be substituting I0SRC for I0DEST
60 later. */ 62 later. */
@@ -63,7 +65,7 @@
63 i0_feeds_i1_n && i0dest_in_i0src); 65 i0_feeds_i1_n && i0dest_in_i0src);
64 substed_i1 = 1; 66 substed_i1 = 1;
65 67
66@@ -3172,7 +3172,7 @@ 68@@ -3198,7 +3198,7 @@
67 69
68 n_occurrences = 0; 70 n_occurrences = 0;
69 subst_low_luid = DF_INSN_LUID (i0); 71 subst_low_luid = DF_INSN_LUID (i0);
@@ -72,7 +74,7 @@
72 substed_i0 = 1; 74 substed_i0 = 1;
73 } 75 }
74 76
75@@ -3234,7 +3234,7 @@ 77@@ -3260,7 +3260,7 @@
76 { 78 {
77 rtx t = i1pat; 79 rtx t = i1pat;
78 if (i0_feeds_i1_n) 80 if (i0_feeds_i1_n)
@@ -81,7 +83,7 @@
81 83
82 XVECEXP (newpat, 0, --total_sets) = t; 84 XVECEXP (newpat, 0, --total_sets) = t;
83 } 85 }
84@@ -3242,10 +3242,10 @@ 86@@ -3268,10 +3268,10 @@
85 { 87 {
86 rtx t = i2pat; 88 rtx t = i2pat;
87 if (i1_feeds_i2_n) 89 if (i1_feeds_i2_n)
@@ -94,7 +96,7 @@
94 96
95 XVECEXP (newpat, 0, --total_sets) = t; 97 XVECEXP (newpat, 0, --total_sets) = t;
96 } 98 }
97@@ -4914,11 +4914,13 @@ 99@@ -4943,11 +4943,13 @@
98 100
99 IN_DEST is nonzero if we are processing the SET_DEST of a SET. 101 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
100 102
@@ -109,7 +111,7 @@
109 { 111 {
110 enum rtx_code code = GET_CODE (x); 112 enum rtx_code code = GET_CODE (x);
111 enum machine_mode op0_mode = VOIDmode; 113 enum machine_mode op0_mode = VOIDmode;
112@@ -4979,7 +4981,7 @@ 114@@ -5008,7 +5010,7 @@
113 && GET_CODE (XVECEXP (x, 0, 0)) == SET 115 && GET_CODE (XVECEXP (x, 0, 0)) == SET
114 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) 116 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
115 { 117 {
@@ -118,7 +120,7 @@
118 120
119 /* If this substitution failed, this whole thing fails. */ 121 /* If this substitution failed, this whole thing fails. */
120 if (GET_CODE (new_rtx) == CLOBBER 122 if (GET_CODE (new_rtx) == CLOBBER
121@@ -4996,7 +4998,7 @@ 123@@ -5025,7 +5027,7 @@
122 && GET_CODE (dest) != CC0 124 && GET_CODE (dest) != CC0
123 && GET_CODE (dest) != PC) 125 && GET_CODE (dest) != PC)
124 { 126 {
@@ -127,7 +129,7 @@
127 129
128 /* If this substitution failed, this whole thing fails. */ 130 /* If this substitution failed, this whole thing fails. */
129 if (GET_CODE (new_rtx) == CLOBBER 131 if (GET_CODE (new_rtx) == CLOBBER
130@@ -5042,8 +5044,8 @@ 132@@ -5071,8 +5073,8 @@
131 } 133 }
132 else 134 else
133 { 135 {
@@ -138,7 +140,7 @@
138 140
139 /* If this substitution failed, this whole thing 141 /* If this substitution failed, this whole thing
140 fails. */ 142 fails. */
141@@ -5120,7 +5122,9 @@ 143@@ -5149,7 +5151,9 @@
142 && (code == SUBREG || code == STRICT_LOW_PART 144 && (code == SUBREG || code == STRICT_LOW_PART
143 || code == ZERO_EXTRACT)) 145 || code == ZERO_EXTRACT))
144 || code == SET) 146 || code == SET)
@@ -149,7 +151,7 @@
149 151
150 /* If we found that we will have to reject this combination, 152 /* If we found that we will have to reject this combination,
151 indicate that by returning the CLOBBER ourselves, rather than 153 indicate that by returning the CLOBBER ourselves, rather than
152@@ -5177,7 +5181,7 @@ 154@@ -5206,7 +5210,7 @@
153 /* If X is sufficiently simple, don't bother trying to do anything 155 /* If X is sufficiently simple, don't bother trying to do anything
154 with it. */ 156 with it. */
155 if (code != CONST_INT && code != REG && code != CLOBBER) 157 if (code != CONST_INT && code != REG && code != CLOBBER)
@@ -158,7 +160,7 @@
158 160
159 if (GET_CODE (x) == code) 161 if (GET_CODE (x) == code)
160 break; 162 break;
161@@ -5197,10 +5201,12 @@ 163@@ -5226,10 +5230,12 @@
162 expression. 164 expression.
163 165
164 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero 166 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
@@ -173,7 +175,7 @@
173 { 175 {
174 enum rtx_code code = GET_CODE (x); 176 enum rtx_code code = GET_CODE (x);
175 enum machine_mode mode = GET_MODE (x); 177 enum machine_mode mode = GET_MODE (x);
176@@ -5255,8 +5261,8 @@ 178@@ -5284,8 +5290,8 @@
177 false arms to store-flag values. Be careful to use copy_rtx 179 false arms to store-flag values. Be careful to use copy_rtx
178 here since true_rtx or false_rtx might share RTL with x as a 180 here since true_rtx or false_rtx might share RTL with x as a
179 result of the if_then_else_cond call above. */ 181 result of the if_then_else_cond call above. */
@@ -184,16 +186,16 @@
184 186
185 /* If true_rtx and false_rtx are not general_operands, an if_then_else 187 /* If true_rtx and false_rtx are not general_operands, an if_then_else
186 is unlikely to be simpler. */ 188 is unlikely to be simpler. */
187@@ -5600,7 +5606,7 @@ 189@@ -5629,7 +5635,7 @@
188 { 190 {
189 /* Try to simplify the expression further. */ 191 /* Try to simplify the expression further. */
190 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); 192 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
191- temp = combine_simplify_rtx (tor, mode, in_dest); 193- temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
192+ temp = combine_simplify_rtx (tor, mode, in_dest, 0); 194+ temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
193 195
194 /* If we could, great. If not, do not go ahead with the IOR 196 /* If we could, great. If not, do not go ahead with the IOR
195 replacement, since PLUS appears in many special purpose 197 replacement, since PLUS appears in many special purpose
196@@ -5693,7 +5699,16 @@ 198@@ -5722,7 +5728,16 @@
197 ZERO_EXTRACT is indeed appropriate, it will be placed back by 199 ZERO_EXTRACT is indeed appropriate, it will be placed back by
198 the call to make_compound_operation in the SET case. */ 200 the call to make_compound_operation in the SET case. */
199 201
@@ -211,7 +213,7 @@
211 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 213 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
212 && op1 == const0_rtx 214 && op1 == const0_rtx
213 && mode == GET_MODE (op0) 215 && mode == GET_MODE (op0)
214@@ -5739,7 +5754,10 @@ 216@@ -5768,7 +5783,10 @@
215 217
216 /* If STORE_FLAG_VALUE is -1, we have cases similar to 218 /* If STORE_FLAG_VALUE is -1, we have cases similar to
217 those above. */ 219 those above. */
@@ -223,7 +225,7 @@
223 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT 225 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
224 && op1 == const0_rtx 226 && op1 == const0_rtx
225 && (num_sign_bit_copies (op0, mode) 227 && (num_sign_bit_copies (op0, mode)
226@@ -5937,11 +5955,11 @@ 228@@ -5966,11 +5984,11 @@
227 if (reg_mentioned_p (from, true_rtx)) 229 if (reg_mentioned_p (from, true_rtx))
228 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, 230 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
229 from, true_val), 231 from, true_val),
@@ -237,7 +239,7 @@
237 239
238 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); 240 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
239 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); 241 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
240@@ -6158,11 +6176,11 @@ 242@@ -6187,11 +6205,11 @@
241 { 243 {
242 temp = subst (simplify_gen_relational (true_code, m, VOIDmode, 244 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
243 cond_op0, cond_op1), 245 cond_op0, cond_op1),
@@ -251,4 +253,3 @@
251 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); 253 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
252 254
253 if (extend_op != UNKNOWN) 255 if (extend_op != UNKNOWN)
254
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
index d14f06c3ff..395c08cab7 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106742.patch
@@ -118,9 +118,11 @@
118 (neon_vld3<mode>, neon_vld4<mode>): Update accordingly. 118 (neon_vld3<mode>, neon_vld4<mode>): Update accordingly.
119 119
120=== modified file 'gcc/calls.c' 120=== modified file 'gcc/calls.c'
121--- old/gcc/calls.c 2011-03-03 21:56:58 +0000 121Index: gcc-4_6-branch/gcc/calls.c
122+++ new/gcc/calls.c 2011-05-03 15:17:25 +0000 122===================================================================
123@@ -684,7 +684,7 @@ 123--- gcc-4_6-branch.orig/gcc/calls.c 2011-06-24 08:33:49.000000000 -0700
124+++ gcc-4_6-branch/gcc/calls.c 2011-09-16 20:16:00.217564705 -0700
125@@ -686,7 +686,7 @@
124 /* If the value is a non-legitimate constant, force it into a 126 /* If the value is a non-legitimate constant, force it into a
125 pseudo now. TLS symbols sometimes need a call to resolve. */ 127 pseudo now. TLS symbols sometimes need a call to resolve. */
126 if (CONSTANT_P (args[i].value) 128 if (CONSTANT_P (args[i].value)
@@ -129,7 +131,7 @@
129 args[i].value = force_reg (args[i].mode, args[i].value); 131 args[i].value = force_reg (args[i].mode, args[i].value);
130 132
131 /* If we are to promote the function arg to a wider mode, 133 /* If we are to promote the function arg to a wider mode,
132@@ -3447,7 +3447,8 @@ 134@@ -3449,7 +3449,8 @@
133 135
134 /* Make sure it is a reasonable operand for a move or push insn. */ 136 /* Make sure it is a reasonable operand for a move or push insn. */
135 if (!REG_P (addr) && !MEM_P (addr) 137 if (!REG_P (addr) && !MEM_P (addr)
@@ -139,7 +141,7 @@
139 addr = force_operand (addr, NULL_RTX); 141 addr = force_operand (addr, NULL_RTX);
140 142
141 argvec[count].value = addr; 143 argvec[count].value = addr;
142@@ -3488,7 +3489,7 @@ 144@@ -3490,7 +3491,7 @@
143 145
144 /* Make sure it is a reasonable operand for a move or push insn. */ 146 /* Make sure it is a reasonable operand for a move or push insn. */
145 if (!REG_P (val) && !MEM_P (val) 147 if (!REG_P (val) && !MEM_P (val)
@@ -148,10 +150,10 @@
148 val = force_operand (val, NULL_RTX); 150 val = force_operand (val, NULL_RTX);
149 151
150 if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1)) 152 if (pass_by_reference (&args_so_far, mode, NULL_TREE, 1))
151 153Index: gcc-4_6-branch/gcc/config/arm/arm-protos.h
152=== modified file 'gcc/config/arm/arm-protos.h' 154===================================================================
153--- old/gcc/config/arm/arm-protos.h 2011-01-29 03:20:57 +0000 155--- gcc-4_6-branch.orig/gcc/config/arm/arm-protos.h 2011-06-24 08:33:37.000000000 -0700
154+++ new/gcc/config/arm/arm-protos.h 2011-05-03 15:17:25 +0000 156+++ gcc-4_6-branch/gcc/config/arm/arm-protos.h 2011-09-16 20:16:00.217564705 -0700
155@@ -81,7 +81,6 @@ 157@@ -81,7 +81,6 @@
156 extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx, 158 extern enum reg_class coproc_secondary_reload_class (enum machine_mode, rtx,
157 bool); 159 bool);
@@ -160,10 +162,10 @@
160 162
161 extern int cirrus_memory_offset (rtx); 163 extern int cirrus_memory_offset (rtx);
162 extern int arm_coproc_mem_operand (rtx, bool); 164 extern int arm_coproc_mem_operand (rtx, bool);
163 165Index: gcc-4_6-branch/gcc/config/arm/arm.c
164=== modified file 'gcc/config/arm/arm.c' 166===================================================================
165--- old/gcc/config/arm/arm.c 2011-04-28 11:46:58 +0000 167--- gcc-4_6-branch.orig/gcc/config/arm/arm.c 2011-09-16 20:14:34.000000000 -0700
166+++ new/gcc/config/arm/arm.c 2011-05-03 15:18:07 +0000 168+++ gcc-4_6-branch/gcc/config/arm/arm.c 2011-09-16 20:16:00.237564275 -0700
167@@ -143,6 +143,8 @@ 169@@ -143,6 +143,8 @@
168 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, 170 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
169 tree); 171 tree);
@@ -608,10 +610,12 @@
608 NEON_ARG_STOP); 610 NEON_ARG_STOP);
609 } 611 }
610 612
611@@ -22267,6 +22402,20 @@ 613@@ -22265,6 +22400,20 @@
612 return false; 614 return true;
613 }
614 615
616 return false;
617+}
618+
615+/* Implements target hook array_mode_supported_p. */ 619+/* Implements target hook array_mode_supported_p. */
616+ 620+
617+static bool 621+static bool
@@ -624,16 +628,14 @@
624+ return true; 628+ return true;
625+ 629+
626+ return false; 630+ return false;
627+} 631 }
628+ 632
629 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword 633 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword
630 registers when autovectorizing for Neon, at least until multiple vector 634Index: gcc-4_6-branch/gcc/config/arm/arm.h
631 widths are supported properly by the middle-end. */ 635===================================================================
632 636--- gcc-4_6-branch.orig/gcc/config/arm/arm.h 2011-09-16 20:14:33.000000000 -0700
633=== modified file 'gcc/config/arm/arm.h' 637+++ gcc-4_6-branch/gcc/config/arm/arm.h 2011-09-16 20:16:00.237564275 -0700
634--- old/gcc/config/arm/arm.h 2011-02-21 14:04:51 +0000 638@@ -1777,27 +1777,6 @@
635+++ new/gcc/config/arm/arm.h 2011-05-03 15:17:25 +0000
636@@ -1775,27 +1775,6 @@
637 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 639 #define TARGET_DEFAULT_WORD_RELOCATIONS 0
638 #endif 640 #endif
639 641
@@ -661,10 +663,10 @@
661 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 663 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
662 #define SUBTARGET_NAME_ENCODING_LENGTHS 664 #define SUBTARGET_NAME_ENCODING_LENGTHS
663 #endif 665 #endif
664 666Index: gcc-4_6-branch/gcc/config/arm/iterators.md
665=== modified file 'gcc/config/arm/iterators.md' 667===================================================================
666--- old/gcc/config/arm/iterators.md 2010-09-21 13:11:03 +0000 668--- gcc-4_6-branch.orig/gcc/config/arm/iterators.md 2011-06-24 08:33:37.000000000 -0700
667+++ new/gcc/config/arm/iterators.md 2011-05-03 15:14:56 +0000 669+++ gcc-4_6-branch/gcc/config/arm/iterators.md 2011-09-16 20:16:00.237564275 -0700
668@@ -194,24 +194,22 @@ 670@@ -194,24 +194,22 @@
669 671
670 ;; Mode of pair of elements for each vector mode, to define transfer 672 ;; Mode of pair of elements for each vector mode, to define transfer
@@ -698,10 +700,10 @@
698 (V2SI "V4SI") (V4SI "V4SI") 700 (V2SI "V4SI") (V4SI "V4SI")
699 (V2SF "V4SF") (V4SF "V4SF") 701 (V2SF "V4SF") (V4SF "V4SF")
700 (DI "OI") (V2DI "OI")]) 702 (DI "OI") (V2DI "OI")])
701 703Index: gcc-4_6-branch/gcc/config/arm/neon-testgen.ml
702=== modified file 'gcc/config/arm/neon-testgen.ml' 704===================================================================
703--- old/gcc/config/arm/neon-testgen.ml 2010-05-24 18:36:31 +0000 705--- gcc-4_6-branch.orig/gcc/config/arm/neon-testgen.ml 2011-06-24 08:33:37.000000000 -0700
704+++ new/gcc/config/arm/neon-testgen.ml 2011-05-03 15:14:56 +0000 706+++ gcc-4_6-branch/gcc/config/arm/neon-testgen.ml 2011-09-16 20:16:00.237564275 -0700
705@@ -177,7 +177,7 @@ 707@@ -177,7 +177,7 @@
706 let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in 708 let alt2 = commas (fun x -> x) (n_things n elt_regexp) "" in
707 "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}" 709 "\\\\\\{((" ^ alt1 ^ ")|(" ^ alt2 ^ "))\\\\\\}"
@@ -711,11 +713,11 @@
711 | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" 713 | Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
712 | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]" 714 | Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
713 | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]" 715 | All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
714 716Index: gcc-4_6-branch/gcc/config/arm/neon.md
715=== modified file 'gcc/config/arm/neon.md' 717===================================================================
716--- old/gcc/config/arm/neon.md 2011-01-03 20:52:22 +0000 718--- gcc-4_6-branch.orig/gcc/config/arm/neon.md 2011-07-19 21:50:44.000000000 -0700
717+++ new/gcc/config/arm/neon.md 2011-05-03 15:14:56 +0000 719+++ gcc-4_6-branch/gcc/config/arm/neon.md 2011-09-16 20:16:00.247564269 -0700
718@@ -4247,16 +4247,16 @@ 720@@ -4250,16 +4250,16 @@
719 721
720 (define_insn "neon_vld1<mode>" 722 (define_insn "neon_vld1<mode>"
721 [(set (match_operand:VDQX 0 "s_register_operand" "=w") 723 [(set (match_operand:VDQX 0 "s_register_operand" "=w")
@@ -735,7 +737,7 @@
735 (match_operand:VDX 2 "s_register_operand" "0") 737 (match_operand:VDX 2 "s_register_operand" "0")
736 (match_operand:SI 3 "immediate_operand" "i")] 738 (match_operand:SI 3 "immediate_operand" "i")]
737 UNSPEC_VLD1_LANE))] 739 UNSPEC_VLD1_LANE))]
738@@ -4267,9 +4267,9 @@ 740@@ -4270,9 +4270,9 @@
739 if (lane < 0 || lane >= max) 741 if (lane < 0 || lane >= max)
740 error ("lane out of range"); 742 error ("lane out of range");
741 if (max == 1) 743 if (max == 1)
@@ -747,7 +749,7 @@
747 } 749 }
748 [(set (attr "neon_type") 750 [(set (attr "neon_type")
749 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) 751 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
750@@ -4279,7 +4279,7 @@ 752@@ -4282,7 +4282,7 @@
751 753
752 (define_insn "neon_vld1_lane<mode>" 754 (define_insn "neon_vld1_lane<mode>"
753 [(set (match_operand:VQX 0 "s_register_operand" "=w") 755 [(set (match_operand:VQX 0 "s_register_operand" "=w")
@@ -756,7 +758,7 @@
756 (match_operand:VQX 2 "s_register_operand" "0") 758 (match_operand:VQX 2 "s_register_operand" "0")
757 (match_operand:SI 3 "immediate_operand" "i")] 759 (match_operand:SI 3 "immediate_operand" "i")]
758 UNSPEC_VLD1_LANE))] 760 UNSPEC_VLD1_LANE))]
759@@ -4298,9 +4298,9 @@ 761@@ -4301,9 +4301,9 @@
760 } 762 }
761 operands[0] = gen_rtx_REG (<V_HALF>mode, regno); 763 operands[0] = gen_rtx_REG (<V_HALF>mode, regno);
762 if (max == 2) 764 if (max == 2)
@@ -768,7 +770,7 @@
768 } 770 }
769 [(set (attr "neon_type") 771 [(set (attr "neon_type")
770 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2)) 772 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 2))
771@@ -4310,14 +4310,14 @@ 773@@ -4313,14 +4313,14 @@
772 774
773 (define_insn "neon_vld1_dup<mode>" 775 (define_insn "neon_vld1_dup<mode>"
774 [(set (match_operand:VDX 0 "s_register_operand" "=w") 776 [(set (match_operand:VDX 0 "s_register_operand" "=w")
@@ -786,7 +788,7 @@
786 } 788 }
787 [(set (attr "neon_type") 789 [(set (attr "neon_type")
788 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) 790 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
789@@ -4327,14 +4327,14 @@ 791@@ -4330,14 +4330,14 @@
790 792
791 (define_insn "neon_vld1_dup<mode>" 793 (define_insn "neon_vld1_dup<mode>"
792 [(set (match_operand:VQX 0 "s_register_operand" "=w") 794 [(set (match_operand:VQX 0 "s_register_operand" "=w")
@@ -804,7 +806,7 @@
804 } 806 }
805 [(set (attr "neon_type") 807 [(set (attr "neon_type")
806 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) 808 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
807@@ -4343,15 +4343,15 @@ 809@@ -4346,15 +4346,15 @@
808 ) 810 )
809 811
810 (define_insn "neon_vst1<mode>" 812 (define_insn "neon_vst1<mode>"
@@ -823,7 +825,7 @@
823 (vec_select:<V_elem> 825 (vec_select:<V_elem>
824 (match_operand:VDX 1 "s_register_operand" "w") 826 (match_operand:VDX 1 "s_register_operand" "w")
825 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] 827 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
826@@ -4362,9 +4362,9 @@ 828@@ -4365,9 +4365,9 @@
827 if (lane < 0 || lane >= max) 829 if (lane < 0 || lane >= max)
828 error ("lane out of range"); 830 error ("lane out of range");
829 if (max == 1) 831 if (max == 1)
@@ -835,7 +837,7 @@
835 } 837 }
836 [(set (attr "neon_type") 838 [(set (attr "neon_type")
837 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1)) 839 (if_then_else (eq (const_string "<V_mode_nunits>") (const_int 1))
838@@ -4372,7 +4372,7 @@ 840@@ -4375,7 +4375,7 @@
839 (const_string "neon_vst1_vst2_lane")))]) 841 (const_string "neon_vst1_vst2_lane")))])
840 842
841 (define_insn "neon_vst1_lane<mode>" 843 (define_insn "neon_vst1_lane<mode>"
@@ -844,7 +846,7 @@
844 (vec_select:<V_elem> 846 (vec_select:<V_elem>
845 (match_operand:VQX 1 "s_register_operand" "w") 847 (match_operand:VQX 1 "s_register_operand" "w")
846 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))] 848 (parallel [(match_operand:SI 2 "neon_lane_number" "i")])))]
847@@ -4391,24 +4391,24 @@ 849@@ -4394,24 +4394,24 @@
848 } 850 }
849 operands[1] = gen_rtx_REG (<V_HALF>mode, regno); 851 operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
850 if (max == 2) 852 if (max == 2)
@@ -874,7 +876,7 @@
874 } 876 }
875 [(set (attr "neon_type") 877 [(set (attr "neon_type")
876 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 878 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
877@@ -4418,16 +4418,16 @@ 879@@ -4421,16 +4421,16 @@
878 880
879 (define_insn "neon_vld2<mode>" 881 (define_insn "neon_vld2<mode>"
880 [(set (match_operand:OI 0 "s_register_operand" "=w") 882 [(set (match_operand:OI 0 "s_register_operand" "=w")
@@ -894,7 +896,7 @@
894 (match_operand:TI 2 "s_register_operand" "0") 896 (match_operand:TI 2 "s_register_operand" "0")
895 (match_operand:SI 3 "immediate_operand" "i") 897 (match_operand:SI 3 "immediate_operand" "i")
896 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 898 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
897@@ -4444,7 +4444,7 @@ 899@@ -4447,7 +4447,7 @@
898 ops[1] = gen_rtx_REG (DImode, regno + 2); 900 ops[1] = gen_rtx_REG (DImode, regno + 2);
899 ops[2] = operands[1]; 901 ops[2] = operands[1];
900 ops[3] = operands[3]; 902 ops[3] = operands[3];
@@ -903,7 +905,7 @@
903 return ""; 905 return "";
904 } 906 }
905 [(set_attr "neon_type" "neon_vld1_vld2_lane")] 907 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
906@@ -4452,7 +4452,7 @@ 908@@ -4455,7 +4455,7 @@
907 909
908 (define_insn "neon_vld2_lane<mode>" 910 (define_insn "neon_vld2_lane<mode>"
909 [(set (match_operand:OI 0 "s_register_operand" "=w") 911 [(set (match_operand:OI 0 "s_register_operand" "=w")
@@ -912,7 +914,7 @@
912 (match_operand:OI 2 "s_register_operand" "0") 914 (match_operand:OI 2 "s_register_operand" "0")
913 (match_operand:SI 3 "immediate_operand" "i") 915 (match_operand:SI 3 "immediate_operand" "i")
914 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 916 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
915@@ -4474,7 +4474,7 @@ 917@@ -4477,7 +4477,7 @@
916 ops[1] = gen_rtx_REG (DImode, regno + 4); 918 ops[1] = gen_rtx_REG (DImode, regno + 4);
917 ops[2] = operands[1]; 919 ops[2] = operands[1];
918 ops[3] = GEN_INT (lane); 920 ops[3] = GEN_INT (lane);
@@ -921,7 +923,7 @@
921 return ""; 923 return "";
922 } 924 }
923 [(set_attr "neon_type" "neon_vld1_vld2_lane")] 925 [(set_attr "neon_type" "neon_vld1_vld2_lane")]
924@@ -4482,15 +4482,15 @@ 926@@ -4485,15 +4485,15 @@
925 927
926 (define_insn "neon_vld2_dup<mode>" 928 (define_insn "neon_vld2_dup<mode>"
927 [(set (match_operand:TI 0 "s_register_operand" "=w") 929 [(set (match_operand:TI 0 "s_register_operand" "=w")
@@ -940,7 +942,7 @@
940 } 942 }
941 [(set (attr "neon_type") 943 [(set (attr "neon_type")
942 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) 944 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
943@@ -4499,16 +4499,16 @@ 945@@ -4502,16 +4502,16 @@
944 ) 946 )
945 947
946 (define_insn "neon_vst2<mode>" 948 (define_insn "neon_vst2<mode>"
@@ -960,7 +962,7 @@
960 } 962 }
961 [(set (attr "neon_type") 963 [(set (attr "neon_type")
962 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 964 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
963@@ -4517,17 +4517,17 @@ 965@@ -4520,17 +4520,17 @@
964 ) 966 )
965 967
966 (define_insn "neon_vst2<mode>" 968 (define_insn "neon_vst2<mode>"
@@ -981,7 +983,7 @@
981 (unspec:<V_two_elem> 983 (unspec:<V_two_elem>
982 [(match_operand:TI 1 "s_register_operand" "w") 984 [(match_operand:TI 1 "s_register_operand" "w")
983 (match_operand:SI 2 "immediate_operand" "i") 985 (match_operand:SI 2 "immediate_operand" "i")
984@@ -4545,14 +4545,14 @@ 986@@ -4548,14 +4548,14 @@
985 ops[1] = gen_rtx_REG (DImode, regno); 987 ops[1] = gen_rtx_REG (DImode, regno);
986 ops[2] = gen_rtx_REG (DImode, regno + 2); 988 ops[2] = gen_rtx_REG (DImode, regno + 2);
987 ops[3] = operands[2]; 989 ops[3] = operands[2];
@@ -998,7 +1000,7 @@
998 (unspec:<V_two_elem> 1000 (unspec:<V_two_elem>
999 [(match_operand:OI 1 "s_register_operand" "w") 1001 [(match_operand:OI 1 "s_register_operand" "w")
1000 (match_operand:SI 2 "immediate_operand" "i") 1002 (match_operand:SI 2 "immediate_operand" "i")
1001@@ -4575,7 +4575,7 @@ 1003@@ -4578,7 +4578,7 @@
1002 ops[1] = gen_rtx_REG (DImode, regno); 1004 ops[1] = gen_rtx_REG (DImode, regno);
1003 ops[2] = gen_rtx_REG (DImode, regno + 4); 1005 ops[2] = gen_rtx_REG (DImode, regno + 4);
1004 ops[3] = GEN_INT (lane); 1006 ops[3] = GEN_INT (lane);
@@ -1007,7 +1009,7 @@
1007 return ""; 1009 return "";
1008 } 1010 }
1009 [(set_attr "neon_type" "neon_vst1_vst2_lane")] 1011 [(set_attr "neon_type" "neon_vst1_vst2_lane")]
1010@@ -4583,15 +4583,15 @@ 1012@@ -4586,15 +4586,15 @@
1011 1013
1012 (define_insn "neon_vld3<mode>" 1014 (define_insn "neon_vld3<mode>"
1013 [(set (match_operand:EI 0 "s_register_operand" "=w") 1015 [(set (match_operand:EI 0 "s_register_operand" "=w")
@@ -1026,7 +1028,7 @@
1026 } 1028 }
1027 [(set (attr "neon_type") 1029 [(set (attr "neon_type")
1028 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 1030 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1029@@ -4600,27 +4600,25 @@ 1031@@ -4603,27 +4603,25 @@
1030 ) 1032 )
1031 1033
1032 (define_expand "neon_vld3<mode>" 1034 (define_expand "neon_vld3<mode>"
@@ -1064,7 +1066,7 @@
1064 "TARGET_NEON" 1066 "TARGET_NEON"
1065 { 1067 {
1066 int regno = REGNO (operands[0]); 1068 int regno = REGNO (operands[0]);
1067@@ -4628,8 +4626,8 @@ 1069@@ -4631,8 +4629,8 @@
1068 ops[0] = gen_rtx_REG (DImode, regno); 1070 ops[0] = gen_rtx_REG (DImode, regno);
1069 ops[1] = gen_rtx_REG (DImode, regno + 4); 1071 ops[1] = gen_rtx_REG (DImode, regno + 4);
1070 ops[2] = gen_rtx_REG (DImode, regno + 8); 1072 ops[2] = gen_rtx_REG (DImode, regno + 8);
@@ -1075,7 +1077,7 @@
1075 return ""; 1077 return "";
1076 } 1078 }
1077 [(set_attr "neon_type" "neon_vld3_vld4")] 1079 [(set_attr "neon_type" "neon_vld3_vld4")]
1078@@ -4637,13 +4635,10 @@ 1080@@ -4640,13 +4638,10 @@
1079 1081
1080 (define_insn "neon_vld3qb<mode>" 1082 (define_insn "neon_vld3qb<mode>"
1081 [(set (match_operand:CI 0 "s_register_operand" "=w") 1083 [(set (match_operand:CI 0 "s_register_operand" "=w")
@@ -1092,7 +1094,7 @@
1092 "TARGET_NEON" 1094 "TARGET_NEON"
1093 { 1095 {
1094 int regno = REGNO (operands[0]); 1096 int regno = REGNO (operands[0]);
1095@@ -4651,8 +4646,8 @@ 1097@@ -4654,8 +4649,8 @@
1096 ops[0] = gen_rtx_REG (DImode, regno + 2); 1098 ops[0] = gen_rtx_REG (DImode, regno + 2);
1097 ops[1] = gen_rtx_REG (DImode, regno + 6); 1099 ops[1] = gen_rtx_REG (DImode, regno + 6);
1098 ops[2] = gen_rtx_REG (DImode, regno + 10); 1100 ops[2] = gen_rtx_REG (DImode, regno + 10);
@@ -1103,7 +1105,7 @@
1103 return ""; 1105 return "";
1104 } 1106 }
1105 [(set_attr "neon_type" "neon_vld3_vld4")] 1107 [(set_attr "neon_type" "neon_vld3_vld4")]
1106@@ -4660,7 +4655,7 @@ 1108@@ -4663,7 +4658,7 @@
1107 1109
1108 (define_insn "neon_vld3_lane<mode>" 1110 (define_insn "neon_vld3_lane<mode>"
1109 [(set (match_operand:EI 0 "s_register_operand" "=w") 1111 [(set (match_operand:EI 0 "s_register_operand" "=w")
@@ -1112,7 +1114,7 @@
1112 (match_operand:EI 2 "s_register_operand" "0") 1114 (match_operand:EI 2 "s_register_operand" "0")
1113 (match_operand:SI 3 "immediate_operand" "i") 1115 (match_operand:SI 3 "immediate_operand" "i")
1114 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1116 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1115@@ -4678,7 +4673,7 @@ 1117@@ -4681,7 +4676,7 @@
1116 ops[2] = gen_rtx_REG (DImode, regno + 4); 1118 ops[2] = gen_rtx_REG (DImode, regno + 4);
1117 ops[3] = operands[1]; 1119 ops[3] = operands[1];
1118 ops[4] = operands[3]; 1120 ops[4] = operands[3];
@@ -1121,7 +1123,7 @@
1121 ops); 1123 ops);
1122 return ""; 1124 return "";
1123 } 1125 }
1124@@ -4687,7 +4682,7 @@ 1126@@ -4690,7 +4685,7 @@
1125 1127
1126 (define_insn "neon_vld3_lane<mode>" 1128 (define_insn "neon_vld3_lane<mode>"
1127 [(set (match_operand:CI 0 "s_register_operand" "=w") 1129 [(set (match_operand:CI 0 "s_register_operand" "=w")
@@ -1130,7 +1132,7 @@
1130 (match_operand:CI 2 "s_register_operand" "0") 1132 (match_operand:CI 2 "s_register_operand" "0")
1131 (match_operand:SI 3 "immediate_operand" "i") 1133 (match_operand:SI 3 "immediate_operand" "i")
1132 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1134 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1133@@ -4710,7 +4705,7 @@ 1135@@ -4713,7 +4708,7 @@
1134 ops[2] = gen_rtx_REG (DImode, regno + 8); 1136 ops[2] = gen_rtx_REG (DImode, regno + 8);
1135 ops[3] = operands[1]; 1137 ops[3] = operands[1];
1136 ops[4] = GEN_INT (lane); 1138 ops[4] = GEN_INT (lane);
@@ -1139,7 +1141,7 @@
1139 ops); 1141 ops);
1140 return ""; 1142 return "";
1141 } 1143 }
1142@@ -4719,7 +4714,7 @@ 1144@@ -4722,7 +4717,7 @@
1143 1145
1144 (define_insn "neon_vld3_dup<mode>" 1146 (define_insn "neon_vld3_dup<mode>"
1145 [(set (match_operand:EI 0 "s_register_operand" "=w") 1147 [(set (match_operand:EI 0 "s_register_operand" "=w")
@@ -1148,7 +1150,7 @@
1148 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1150 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1149 UNSPEC_VLD3_DUP))] 1151 UNSPEC_VLD3_DUP))]
1150 "TARGET_NEON" 1152 "TARGET_NEON"
1151@@ -4732,11 +4727,11 @@ 1153@@ -4735,11 +4730,11 @@
1152 ops[1] = gen_rtx_REG (DImode, regno + 2); 1154 ops[1] = gen_rtx_REG (DImode, regno + 2);
1153 ops[2] = gen_rtx_REG (DImode, regno + 4); 1155 ops[2] = gen_rtx_REG (DImode, regno + 4);
1154 ops[3] = operands[1]; 1156 ops[3] = operands[1];
@@ -1162,7 +1164,7 @@
1162 } 1164 }
1163 [(set (attr "neon_type") 1165 [(set (attr "neon_type")
1164 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) 1166 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1165@@ -4744,16 +4739,16 @@ 1167@@ -4747,16 +4742,16 @@
1166 (const_string "neon_vld1_1_2_regs")))]) 1168 (const_string "neon_vld1_1_2_regs")))])
1167 1169
1168 (define_insn "neon_vst3<mode>" 1170 (define_insn "neon_vst3<mode>"
@@ -1182,7 +1184,7 @@
1182 } 1184 }
1183 [(set (attr "neon_type") 1185 [(set (attr "neon_type")
1184 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 1186 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1185@@ -4761,62 +4756,60 @@ 1187@@ -4764,62 +4759,60 @@
1186 (const_string "neon_vst2_4_regs_vst3_vst4")))]) 1188 (const_string "neon_vst2_4_regs_vst3_vst4")))])
1187 1189
1188 (define_expand "neon_vst3<mode>" 1190 (define_expand "neon_vst3<mode>"
@@ -1264,7 +1266,7 @@
1264 (unspec:<V_three_elem> 1266 (unspec:<V_three_elem>
1265 [(match_operand:EI 1 "s_register_operand" "w") 1267 [(match_operand:EI 1 "s_register_operand" "w")
1266 (match_operand:SI 2 "immediate_operand" "i") 1268 (match_operand:SI 2 "immediate_operand" "i")
1267@@ -4835,7 +4828,7 @@ 1269@@ -4838,7 +4831,7 @@
1268 ops[2] = gen_rtx_REG (DImode, regno + 2); 1270 ops[2] = gen_rtx_REG (DImode, regno + 2);
1269 ops[3] = gen_rtx_REG (DImode, regno + 4); 1271 ops[3] = gen_rtx_REG (DImode, regno + 4);
1270 ops[4] = operands[2]; 1272 ops[4] = operands[2];
@@ -1273,7 +1275,7 @@
1273 ops); 1275 ops);
1274 return ""; 1276 return "";
1275 } 1277 }
1276@@ -4843,7 +4836,7 @@ 1278@@ -4846,7 +4839,7 @@
1277 ) 1279 )
1278 1280
1279 (define_insn "neon_vst3_lane<mode>" 1281 (define_insn "neon_vst3_lane<mode>"
@@ -1282,7 +1284,7 @@
1282 (unspec:<V_three_elem> 1284 (unspec:<V_three_elem>
1283 [(match_operand:CI 1 "s_register_operand" "w") 1285 [(match_operand:CI 1 "s_register_operand" "w")
1284 (match_operand:SI 2 "immediate_operand" "i") 1286 (match_operand:SI 2 "immediate_operand" "i")
1285@@ -4867,7 +4860,7 @@ 1287@@ -4870,7 +4863,7 @@
1286 ops[2] = gen_rtx_REG (DImode, regno + 4); 1288 ops[2] = gen_rtx_REG (DImode, regno + 4);
1287 ops[3] = gen_rtx_REG (DImode, regno + 8); 1289 ops[3] = gen_rtx_REG (DImode, regno + 8);
1288 ops[4] = GEN_INT (lane); 1290 ops[4] = GEN_INT (lane);
@@ -1291,7 +1293,7 @@
1291 ops); 1293 ops);
1292 return ""; 1294 return "";
1293 } 1295 }
1294@@ -4875,15 +4868,15 @@ 1296@@ -4878,15 +4871,15 @@
1295 1297
1296 (define_insn "neon_vld4<mode>" 1298 (define_insn "neon_vld4<mode>"
1297 [(set (match_operand:OI 0 "s_register_operand" "=w") 1299 [(set (match_operand:OI 0 "s_register_operand" "=w")
@@ -1310,7 +1312,7 @@
1310 } 1312 }
1311 [(set (attr "neon_type") 1313 [(set (attr "neon_type")
1312 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 1314 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1313@@ -4892,27 +4885,25 @@ 1315@@ -4895,27 +4888,25 @@
1314 ) 1316 )
1315 1317
1316 (define_expand "neon_vld4<mode>" 1318 (define_expand "neon_vld4<mode>"
@@ -1348,7 +1350,7 @@
1348 "TARGET_NEON" 1350 "TARGET_NEON"
1349 { 1351 {
1350 int regno = REGNO (operands[0]); 1352 int regno = REGNO (operands[0]);
1351@@ -4921,8 +4912,8 @@ 1353@@ -4924,8 +4915,8 @@
1352 ops[1] = gen_rtx_REG (DImode, regno + 4); 1354 ops[1] = gen_rtx_REG (DImode, regno + 4);
1353 ops[2] = gen_rtx_REG (DImode, regno + 8); 1355 ops[2] = gen_rtx_REG (DImode, regno + 8);
1354 ops[3] = gen_rtx_REG (DImode, regno + 12); 1356 ops[3] = gen_rtx_REG (DImode, regno + 12);
@@ -1359,7 +1361,7 @@
1359 return ""; 1361 return "";
1360 } 1362 }
1361 [(set_attr "neon_type" "neon_vld3_vld4")] 1363 [(set_attr "neon_type" "neon_vld3_vld4")]
1362@@ -4930,13 +4921,10 @@ 1364@@ -4933,13 +4924,10 @@
1363 1365
1364 (define_insn "neon_vld4qb<mode>" 1366 (define_insn "neon_vld4qb<mode>"
1365 [(set (match_operand:XI 0 "s_register_operand" "=w") 1367 [(set (match_operand:XI 0 "s_register_operand" "=w")
@@ -1376,7 +1378,7 @@
1376 "TARGET_NEON" 1378 "TARGET_NEON"
1377 { 1379 {
1378 int regno = REGNO (operands[0]); 1380 int regno = REGNO (operands[0]);
1379@@ -4945,8 +4933,8 @@ 1381@@ -4948,8 +4936,8 @@
1380 ops[1] = gen_rtx_REG (DImode, regno + 6); 1382 ops[1] = gen_rtx_REG (DImode, regno + 6);
1381 ops[2] = gen_rtx_REG (DImode, regno + 10); 1383 ops[2] = gen_rtx_REG (DImode, regno + 10);
1382 ops[3] = gen_rtx_REG (DImode, regno + 14); 1384 ops[3] = gen_rtx_REG (DImode, regno + 14);
@@ -1387,7 +1389,7 @@
1387 return ""; 1389 return "";
1388 } 1390 }
1389 [(set_attr "neon_type" "neon_vld3_vld4")] 1391 [(set_attr "neon_type" "neon_vld3_vld4")]
1390@@ -4954,7 +4942,7 @@ 1392@@ -4957,7 +4945,7 @@
1391 1393
1392 (define_insn "neon_vld4_lane<mode>" 1394 (define_insn "neon_vld4_lane<mode>"
1393 [(set (match_operand:OI 0 "s_register_operand" "=w") 1395 [(set (match_operand:OI 0 "s_register_operand" "=w")
@@ -1396,7 +1398,7 @@
1396 (match_operand:OI 2 "s_register_operand" "0") 1398 (match_operand:OI 2 "s_register_operand" "0")
1397 (match_operand:SI 3 "immediate_operand" "i") 1399 (match_operand:SI 3 "immediate_operand" "i")
1398 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1400 (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1399@@ -4973,7 +4961,7 @@ 1401@@ -4976,7 +4964,7 @@
1400 ops[3] = gen_rtx_REG (DImode, regno + 6); 1402 ops[3] = gen_rtx_REG (DImode, regno + 6);
1401 ops[4] = operands[1]; 1403 ops[4] = operands[1];
1402 ops[5] = operands[3]; 1404 ops[5] = operands[3];
@@ -1405,7 +1407,7 @@
1405 ops); 1407 ops);
1406 return ""; 1408 return "";
1407 } 1409 }
1408@@ -4982,7 +4970,7 @@ 1410@@ -4985,7 +4973,7 @@
1409 1411
1410 (define_insn "neon_vld4_lane<mode>" 1412 (define_insn "neon_vld4_lane<mode>"
1411 [(set (match_operand:XI 0 "s_register_operand" "=w") 1413 [(set (match_operand:XI 0 "s_register_operand" "=w")
@@ -1414,7 +1416,7 @@
1414 (match_operand:XI 2 "s_register_operand" "0") 1416 (match_operand:XI 2 "s_register_operand" "0")
1415 (match_operand:SI 3 "immediate_operand" "i") 1417 (match_operand:SI 3 "immediate_operand" "i")
1416 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1418 (unspec:VMQ [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1417@@ -5006,7 +4994,7 @@ 1419@@ -5009,7 +4997,7 @@
1418 ops[3] = gen_rtx_REG (DImode, regno + 12); 1420 ops[3] = gen_rtx_REG (DImode, regno + 12);
1419 ops[4] = operands[1]; 1421 ops[4] = operands[1];
1420 ops[5] = GEN_INT (lane); 1422 ops[5] = GEN_INT (lane);
@@ -1423,7 +1425,7 @@
1423 ops); 1425 ops);
1424 return ""; 1426 return "";
1425 } 1427 }
1426@@ -5015,7 +5003,7 @@ 1428@@ -5018,7 +5006,7 @@
1427 1429
1428 (define_insn "neon_vld4_dup<mode>" 1430 (define_insn "neon_vld4_dup<mode>"
1429 [(set (match_operand:OI 0 "s_register_operand" "=w") 1431 [(set (match_operand:OI 0 "s_register_operand" "=w")
@@ -1432,7 +1434,7 @@
1432 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] 1434 (unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
1433 UNSPEC_VLD4_DUP))] 1435 UNSPEC_VLD4_DUP))]
1434 "TARGET_NEON" 1436 "TARGET_NEON"
1435@@ -5029,12 +5017,12 @@ 1437@@ -5032,12 +5020,12 @@
1436 ops[2] = gen_rtx_REG (DImode, regno + 4); 1438 ops[2] = gen_rtx_REG (DImode, regno + 4);
1437 ops[3] = gen_rtx_REG (DImode, regno + 6); 1439 ops[3] = gen_rtx_REG (DImode, regno + 6);
1438 ops[4] = operands[1]; 1440 ops[4] = operands[1];
@@ -1447,7 +1449,7 @@
1447 } 1449 }
1448 [(set (attr "neon_type") 1450 [(set (attr "neon_type")
1449 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1")) 1451 (if_then_else (gt (const_string "<V_mode_nunits>") (const_string "1"))
1450@@ -5043,16 +5031,16 @@ 1452@@ -5046,16 +5034,16 @@
1451 ) 1453 )
1452 1454
1453 (define_insn "neon_vst4<mode>" 1455 (define_insn "neon_vst4<mode>"
@@ -1467,7 +1469,7 @@
1467 } 1469 }
1468 [(set (attr "neon_type") 1470 [(set (attr "neon_type")
1469 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64")) 1471 (if_then_else (eq (const_string "<V_sz_elem>") (const_string "64"))
1470@@ -5061,64 +5049,62 @@ 1472@@ -5064,64 +5052,62 @@
1471 ) 1473 )
1472 1474
1473 (define_expand "neon_vst4<mode>" 1475 (define_expand "neon_vst4<mode>"
@@ -1551,7 +1553,7 @@
1551 (unspec:<V_four_elem> 1553 (unspec:<V_four_elem>
1552 [(match_operand:OI 1 "s_register_operand" "w") 1554 [(match_operand:OI 1 "s_register_operand" "w")
1553 (match_operand:SI 2 "immediate_operand" "i") 1555 (match_operand:SI 2 "immediate_operand" "i")
1554@@ -5138,7 +5124,7 @@ 1556@@ -5141,7 +5127,7 @@
1555 ops[3] = gen_rtx_REG (DImode, regno + 4); 1557 ops[3] = gen_rtx_REG (DImode, regno + 4);
1556 ops[4] = gen_rtx_REG (DImode, regno + 6); 1558 ops[4] = gen_rtx_REG (DImode, regno + 6);
1557 ops[5] = operands[2]; 1559 ops[5] = operands[2];
@@ -1560,7 +1562,7 @@
1560 ops); 1562 ops);
1561 return ""; 1563 return "";
1562 } 1564 }
1563@@ -5146,7 +5132,7 @@ 1565@@ -5149,7 +5135,7 @@
1564 ) 1566 )
1565 1567
1566 (define_insn "neon_vst4_lane<mode>" 1568 (define_insn "neon_vst4_lane<mode>"
@@ -1569,7 +1571,7 @@
1569 (unspec:<V_four_elem> 1571 (unspec:<V_four_elem>
1570 [(match_operand:XI 1 "s_register_operand" "w") 1572 [(match_operand:XI 1 "s_register_operand" "w")
1571 (match_operand:SI 2 "immediate_operand" "i") 1573 (match_operand:SI 2 "immediate_operand" "i")
1572@@ -5171,7 +5157,7 @@ 1574@@ -5174,7 +5160,7 @@
1573 ops[3] = gen_rtx_REG (DImode, regno + 8); 1575 ops[3] = gen_rtx_REG (DImode, regno + 8);
1574 ops[4] = gen_rtx_REG (DImode, regno + 12); 1576 ops[4] = gen_rtx_REG (DImode, regno + 12);
1575 ops[5] = GEN_INT (lane); 1577 ops[5] = GEN_INT (lane);
@@ -1578,22 +1580,23 @@
1578 ops); 1580 ops);
1579 return ""; 1581 return "";
1580 } 1582 }
1581 1583Index: gcc-4_6-branch/gcc/config/arm/predicates.md
1582=== modified file 'gcc/config/arm/predicates.md' 1584===================================================================
1583--- old/gcc/config/arm/predicates.md 2011-04-07 10:52:12 +0000 1585--- gcc-4_6-branch.orig/gcc/config/arm/predicates.md 2011-09-16 19:58:21.000000000 -0700
1584+++ new/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000 1586+++ gcc-4_6-branch/gcc/config/arm/predicates.md 2011-09-16 20:19:03.967834108 -0700
1585@@ -683,3 +683,7 @@ 1587@@ -686,3 +686,8 @@
1586 } 1588
1587 return true; 1589 (define_special_predicate "add_operator"
1588 }) 1590 (match_code "plus"))
1589+ 1591+
1590+(define_special_predicate "neon_struct_operand" 1592+(define_special_predicate "neon_struct_operand"
1591+ (and (match_code "mem") 1593+ (and (match_code "mem")
1592+ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)"))) 1594+ (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
1593 1595+
1594=== modified file 'gcc/doc/tm.texi' 1596Index: gcc-4_6-branch/gcc/doc/tm.texi
1595--- old/gcc/doc/tm.texi 2011-01-22 19:35:10 +0000 1597===================================================================
1596+++ new/gcc/doc/tm.texi 2011-05-03 15:17:25 +0000 1598--- gcc-4_6-branch.orig/gcc/doc/tm.texi 2011-06-24 08:13:00.000000000 -0700
1599+++ gcc-4_6-branch/gcc/doc/tm.texi 2011-09-16 20:16:00.257564628 -0700
1597@@ -2533,7 +2533,7 @@ 1600@@ -2533,7 +2533,7 @@
1598 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when 1601 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1599 @var{x} is a floating-point constant. If the constant can't be loaded 1602 @var{x} is a floating-point constant. If the constant can't be loaded
@@ -1670,10 +1673,10 @@
1670 1673
1671 @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x}) 1674 @deftypefn {Target Hook} rtx TARGET_DELEGITIMIZE_ADDRESS (rtx @var{x})
1672 This hook is used to undo the possibly obfuscating effects of the 1675 This hook is used to undo the possibly obfuscating effects of the
1673 1676Index: gcc-4_6-branch/gcc/doc/tm.texi.in
1674=== modified file 'gcc/doc/tm.texi.in' 1677===================================================================
1675--- old/gcc/doc/tm.texi.in 2011-01-22 19:35:10 +0000 1678--- gcc-4_6-branch.orig/gcc/doc/tm.texi.in 2011-06-24 08:13:00.000000000 -0700
1676+++ new/gcc/doc/tm.texi.in 2011-05-03 15:17:25 +0000 1679+++ gcc-4_6-branch/gcc/doc/tm.texi.in 2011-09-16 20:16:00.257564628 -0700
1677@@ -2521,7 +2521,7 @@ 1680@@ -2521,7 +2521,7 @@
1678 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when 1681 register, so @code{TARGET_PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when
1679 @var{x} is a floating-point constant. If the constant can't be loaded 1682 @var{x} is a floating-point constant. If the constant can't be loaded
@@ -1724,10 +1727,10 @@
1724 1727
1725 @hook TARGET_DELEGITIMIZE_ADDRESS 1728 @hook TARGET_DELEGITIMIZE_ADDRESS
1726 This hook is used to undo the possibly obfuscating effects of the 1729 This hook is used to undo the possibly obfuscating effects of the
1727 1730Index: gcc-4_6-branch/gcc/expr.c
1728=== modified file 'gcc/expr.c' 1731===================================================================
1729--- old/gcc/expr.c 2011-04-05 16:18:11 +0000 1732--- gcc-4_6-branch.orig/gcc/expr.c 2011-09-16 20:14:32.000000000 -0700
1730+++ new/gcc/expr.c 2011-05-03 15:17:25 +0000 1733+++ gcc-4_6-branch/gcc/expr.c 2011-09-16 20:16:00.267564792 -0700
1731@@ -1497,7 +1497,7 @@ 1734@@ -1497,7 +1497,7 @@
1732 if (nregs == 0) 1735 if (nregs == 0)
1733 return; 1736 return;
@@ -1782,7 +1785,7 @@
1782 x = validize_mem (force_const_mem (mode, x)); 1785 x = validize_mem (force_const_mem (mode, x));
1783 1786
1784 /* If X is a hard register in a non-integer mode, copy it into a pseudo; 1787 /* If X is a hard register in a non-integer mode, copy it into a pseudo;
1785@@ -9066,7 +9066,7 @@ 1788@@ -9108,7 +9108,7 @@
1786 constant and we don't need a memory reference. */ 1789 constant and we don't need a memory reference. */
1787 if (CONSTANT_P (op0) 1790 if (CONSTANT_P (op0)
1788 && mode2 != BLKmode 1791 && mode2 != BLKmode
@@ -1791,10 +1794,10 @@
1791 && !must_force_mem) 1794 && !must_force_mem)
1792 op0 = force_reg (mode2, op0); 1795 op0 = force_reg (mode2, op0);
1793 1796
1794 1797Index: gcc-4_6-branch/gcc/hooks.c
1795=== modified file 'gcc/hooks.c' 1798===================================================================
1796--- old/gcc/hooks.c 2010-11-25 13:16:03 +0000 1799--- gcc-4_6-branch.orig/gcc/hooks.c 2011-06-24 08:33:48.000000000 -0700
1797+++ new/gcc/hooks.c 2011-05-03 15:16:01 +0000 1800+++ gcc-4_6-branch/gcc/hooks.c 2011-09-16 20:16:00.267564792 -0700
1798@@ -101,6 +101,15 @@ 1801@@ -101,6 +101,15 @@
1799 return true; 1802 return true;
1800 } 1803 }
@@ -1811,10 +1814,10 @@
1811 /* Generic hook that takes (FILE *, const char *) and does nothing. */ 1814 /* Generic hook that takes (FILE *, const char *) and does nothing. */
1812 void 1815 void
1813 hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED) 1816 hook_void_FILEptr_constcharptr (FILE *a ATTRIBUTE_UNUSED, const char *b ATTRIBUTE_UNUSED)
1814 1817Index: gcc-4_6-branch/gcc/hooks.h
1815=== modified file 'gcc/hooks.h' 1818===================================================================
1816--- old/gcc/hooks.h 2010-11-25 13:16:03 +0000 1819--- gcc-4_6-branch.orig/gcc/hooks.h 2011-06-24 08:33:48.000000000 -0700
1817+++ new/gcc/hooks.h 2011-05-03 15:16:01 +0000 1820+++ gcc-4_6-branch/gcc/hooks.h 2011-09-16 20:16:00.267564792 -0700
1818@@ -34,6 +34,8 @@ 1821@@ -34,6 +34,8 @@
1819 extern bool hook_bool_mode_true (enum machine_mode); 1822 extern bool hook_bool_mode_true (enum machine_mode);
1820 extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx); 1823 extern bool hook_bool_mode_const_rtx_false (enum machine_mode, const_rtx);
@@ -1824,10 +1827,10 @@
1824 extern bool hook_bool_tree_false (tree); 1827 extern bool hook_bool_tree_false (tree);
1825 extern bool hook_bool_const_tree_false (const_tree); 1828 extern bool hook_bool_const_tree_false (const_tree);
1826 extern bool hook_bool_tree_true (tree); 1829 extern bool hook_bool_tree_true (tree);
1827 1830Index: gcc-4_6-branch/gcc/recog.c
1828=== modified file 'gcc/recog.c' 1831===================================================================
1829--- old/gcc/recog.c 2010-11-30 16:36:19 +0000 1832--- gcc-4_6-branch.orig/gcc/recog.c 2011-06-24 08:33:49.000000000 -0700
1830+++ new/gcc/recog.c 2011-05-03 15:17:25 +0000 1833+++ gcc-4_6-branch/gcc/recog.c 2011-09-16 20:16:00.277564886 -0700
1831@@ -930,7 +930,9 @@ 1834@@ -930,7 +930,9 @@
1832 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode 1835 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1833 || mode == VOIDmode) 1836 || mode == VOIDmode)
@@ -1850,10 +1853,10 @@
1850 } 1853 }
1851 1854
1852 /* Returns 1 if OP is an operand that is a CONST_INT. */ 1855 /* Returns 1 if OP is an operand that is a CONST_INT. */
1853 1856Index: gcc-4_6-branch/gcc/reload.c
1854=== modified file 'gcc/reload.c' 1857===================================================================
1855--- old/gcc/reload.c 2011-02-02 16:52:21 +0000 1858--- gcc-4_6-branch.orig/gcc/reload.c 2011-06-24 08:33:49.000000000 -0700
1856+++ new/gcc/reload.c 2011-05-03 15:17:25 +0000 1859+++ gcc-4_6-branch/gcc/reload.c 2011-09-16 20:16:00.277564886 -0700
1857@@ -4721,7 +4721,8 @@ 1860@@ -4721,7 +4721,8 @@
1858 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno], 1861 simplify_gen_subreg (GET_MODE (x), reg_equiv_constant[regno],
1859 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); 1862 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
@@ -1882,10 +1885,10 @@
1882 || targetm.preferred_reload_class (XEXP (x, 1), rclass) 1885 || targetm.preferred_reload_class (XEXP (x, 1), rclass)
1883 == NO_REGS)) 1886 == NO_REGS))
1884 { 1887 {
1885 1888Index: gcc-4_6-branch/gcc/reload1.c
1886=== modified file 'gcc/reload1.c' 1889===================================================================
1887--- old/gcc/reload1.c 2011-01-23 21:11:24 +0000 1890--- gcc-4_6-branch.orig/gcc/reload1.c 2011-06-24 08:33:49.000000000 -0700
1888+++ new/gcc/reload1.c 2011-05-03 15:17:25 +0000 1891+++ gcc-4_6-branch/gcc/reload1.c 2011-09-16 20:16:00.277564886 -0700
1889@@ -4155,6 +4155,9 @@ 1892@@ -4155,6 +4155,9 @@
1890 } 1893 }
1891 else if (function_invariant_p (x)) 1894 else if (function_invariant_p (x))
@@ -1911,10 +1914,10 @@
1911 if (! reg_equiv_memory_loc[i]) 1914 if (! reg_equiv_memory_loc[i])
1912 reg_equiv_init[i] = NULL_RTX; 1915 reg_equiv_init[i] = NULL_RTX;
1913 } 1916 }
1914 1917Index: gcc-4_6-branch/gcc/stor-layout.c
1915=== modified file 'gcc/stor-layout.c' 1918===================================================================
1916--- old/gcc/stor-layout.c 2011-03-10 22:37:22 +0000 1919--- gcc-4_6-branch.orig/gcc/stor-layout.c 2011-06-24 08:33:49.000000000 -0700
1917+++ new/gcc/stor-layout.c 2011-05-03 15:16:01 +0000 1920+++ gcc-4_6-branch/gcc/stor-layout.c 2011-09-16 20:16:00.287564867 -0700
1918@@ -546,6 +546,34 @@ 1921@@ -546,6 +546,34 @@
1919 return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT)); 1922 return MIN (BIGGEST_ALIGNMENT, MAX (1, mode_base_align[mode]*BITS_PER_UNIT));
1920 } 1923 }
@@ -1967,10 +1970,10 @@
1967 if (TYPE_MODE (type) != BLKmode 1970 if (TYPE_MODE (type) != BLKmode
1968 && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT 1971 && STRICT_ALIGNMENT && TYPE_ALIGN (type) < BIGGEST_ALIGNMENT
1969 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type))) 1972 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (TYPE_MODE (type)))
1970 1973Index: gcc-4_6-branch/gcc/target.def
1971=== modified file 'gcc/target.def' 1974===================================================================
1972--- old/gcc/target.def 2011-01-22 19:35:10 +0000 1975--- gcc-4_6-branch.orig/gcc/target.def 2011-06-24 08:33:48.000000000 -0700
1973+++ new/gcc/target.def 2011-05-03 15:17:25 +0000 1976+++ gcc-4_6-branch/gcc/target.def 2011-09-16 20:16:00.287564867 -0700
1974@@ -1344,6 +1344,13 @@ 1977@@ -1344,6 +1344,13 @@
1975 unsigned, (unsigned nunroll, struct loop *loop), 1978 unsigned, (unsigned nunroll, struct loop *loop),
1976 NULL) 1979 NULL)
@@ -2024,10 +2027,10 @@
2024 /* Compute cost of moving data from a register of class FROM to one of 2027 /* Compute cost of moving data from a register of class FROM to one of
2025 TO, using MODE. */ 2028 TO, using MODE. */
2026 DEFHOOK 2029 DEFHOOK
2027 2030Index: gcc-4_6-branch/gcc/targhooks.c
2028=== modified file 'gcc/targhooks.c' 2031===================================================================
2029--- old/gcc/targhooks.c 2011-01-14 15:02:20 +0000 2032--- gcc-4_6-branch.orig/gcc/targhooks.c 2011-06-24 08:33:48.000000000 -0700
2030+++ new/gcc/targhooks.c 2011-05-03 15:17:25 +0000 2033+++ gcc-4_6-branch/gcc/targhooks.c 2011-09-16 20:16:00.287564867 -0700
2031@@ -1519,4 +1519,15 @@ 2034@@ -1519,4 +1519,15 @@
2032 { OPT_LEVELS_NONE, 0, NULL, 0 } 2035 { OPT_LEVELS_NONE, 0, NULL, 0 }
2033 }; 2036 };
@@ -2044,19 +2047,19 @@
2044+} 2047+}
2045+ 2048+
2046 #include "gt-targhooks.h" 2049 #include "gt-targhooks.h"
2047 2050Index: gcc-4_6-branch/gcc/targhooks.h
2048=== modified file 'gcc/targhooks.h' 2051===================================================================
2049--- old/gcc/targhooks.h 2011-01-14 15:02:20 +0000 2052--- gcc-4_6-branch.orig/gcc/targhooks.h 2011-06-24 08:33:48.000000000 -0700
2050+++ new/gcc/targhooks.h 2011-05-03 15:17:25 +0000 2053+++ gcc-4_6-branch/gcc/targhooks.h 2011-09-16 20:16:00.287564867 -0700
2051@@ -183,3 +183,4 @@ 2054@@ -183,3 +183,4 @@
2052 2055
2053 extern void *default_get_pch_validity (size_t *); 2056 extern void *default_get_pch_validity (size_t *);
2054 extern const char *default_pch_valid_p (const void *, size_t); 2057 extern const char *default_pch_valid_p (const void *, size_t);
2055+extern bool default_legitimate_constant_p (enum machine_mode, rtx); 2058+extern bool default_legitimate_constant_p (enum machine_mode, rtx);
2056 2059Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
2057=== added file 'gcc/testsuite/gcc.target/arm/neon-vld3-1.c' 2060===================================================================
2058--- old/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 1970-01-01 00:00:00 +0000 2061--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2059+++ new/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-05-03 15:14:56 +0000 2062+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vld3-1.c 2011-09-16 20:16:00.287564867 -0700
2060@@ -0,0 +1,27 @@ 2063@@ -0,0 +1,27 @@
2061+/* { dg-do run } */ 2064+/* { dg-do run } */
2062+/* { dg-require-effective-target arm_neon_hw } */ 2065+/* { dg-require-effective-target arm_neon_hw } */
@@ -2085,10 +2088,10 @@
2085+ foo (buffer); 2088+ foo (buffer);
2086+ return buffer[0] != 3; 2089+ return buffer[0] != 3;
2087+} 2090+}
2088 2091Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
2089=== added file 'gcc/testsuite/gcc.target/arm/neon-vst3-1.c' 2092===================================================================
2090--- old/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 1970-01-01 00:00:00 +0000 2093--- /dev/null 1970-01-01 00:00:00.000000000 +0000
2091+++ new/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-05-03 15:14:56 +0000 2094+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon-vst3-1.c 2011-09-16 20:16:00.287564867 -0700
2092@@ -0,0 +1,25 @@ 2095@@ -0,0 +1,25 @@
2093+/* { dg-do run } */ 2096+/* { dg-do run } */
2094+/* { dg-require-effective-target arm_neon_hw } */ 2097+/* { dg-require-effective-target arm_neon_hw } */
@@ -2115,10 +2118,10 @@
2115+ foo (buffer); 2118+ foo (buffer);
2116+ return buffer[35] != 1; 2119+ return buffer[35] != 1;
2117+} 2120+}
2118 2121Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
2119=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c' 2122===================================================================
2120--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2010-05-24 18:36:31 +0000 2123--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-06-24 08:13:40.000000000 -0700
2121+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-05-03 15:14:56 +0000 2124+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c 2011-09-16 20:16:00.297564810 -0700
2122@@ -15,5 +15,5 @@ 2125@@ -15,5 +15,5 @@
2123 out_float32x4_t = vld1q_dup_f32 (0); 2126 out_float32x4_t = vld1q_dup_f32 (0);
2124 } 2127 }
@@ -2126,10 +2129,10 @@
2126-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2129-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2127+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2130+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2128 /* { dg-final { cleanup-saved-temps } } */ 2131 /* { dg-final { cleanup-saved-temps } } */
2129 2132Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
2130=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c' 2133===================================================================
2131--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2010-05-24 18:36:31 +0000 2134--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-06-24 08:13:40.000000000 -0700
2132+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-05-03 15:14:56 +0000 2135+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c 2011-09-16 20:16:00.297564810 -0700
2133@@ -15,5 +15,5 @@ 2136@@ -15,5 +15,5 @@
2134 out_poly16x8_t = vld1q_dup_p16 (0); 2137 out_poly16x8_t = vld1q_dup_p16 (0);
2135 } 2138 }
@@ -2137,10 +2140,10 @@
2137-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2140-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2138+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2141+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2139 /* { dg-final { cleanup-saved-temps } } */ 2142 /* { dg-final { cleanup-saved-temps } } */
2140 2143Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
2141=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c' 2144===================================================================
2142--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2010-05-24 18:36:31 +0000 2145--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-06-24 08:13:40.000000000 -0700
2143+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-05-03 15:14:56 +0000 2146+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c 2011-09-16 20:16:00.297564810 -0700
2144@@ -15,5 +15,5 @@ 2147@@ -15,5 +15,5 @@
2145 out_poly8x16_t = vld1q_dup_p8 (0); 2148 out_poly8x16_t = vld1q_dup_p8 (0);
2146 } 2149 }
@@ -2148,10 +2151,10 @@
2148-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2151-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2149+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2152+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2150 /* { dg-final { cleanup-saved-temps } } */ 2153 /* { dg-final { cleanup-saved-temps } } */
2151 2154Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
2152=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c' 2155===================================================================
2153--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2010-05-24 18:36:31 +0000 2156--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-06-24 08:13:40.000000000 -0700
2154+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-05-03 15:14:56 +0000 2157+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c 2011-09-16 20:16:00.297564810 -0700
2155@@ -15,5 +15,5 @@ 2158@@ -15,5 +15,5 @@
2156 out_int16x8_t = vld1q_dup_s16 (0); 2159 out_int16x8_t = vld1q_dup_s16 (0);
2157 } 2160 }
@@ -2159,10 +2162,10 @@
2159-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2162-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2160+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2163+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2161 /* { dg-final { cleanup-saved-temps } } */ 2164 /* { dg-final { cleanup-saved-temps } } */
2162 2165Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
2163=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c' 2166===================================================================
2164--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2010-05-24 18:36:31 +0000 2167--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-06-24 08:13:40.000000000 -0700
2165+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-05-03 15:14:56 +0000 2168+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c 2011-09-16 20:16:00.297564810 -0700
2166@@ -15,5 +15,5 @@ 2169@@ -15,5 +15,5 @@
2167 out_int32x4_t = vld1q_dup_s32 (0); 2170 out_int32x4_t = vld1q_dup_s32 (0);
2168 } 2171 }
@@ -2170,10 +2173,10 @@
2170-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2173-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2171+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2174+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2172 /* { dg-final { cleanup-saved-temps } } */ 2175 /* { dg-final { cleanup-saved-temps } } */
2173 2176Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
2174=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c' 2177===================================================================
2175--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2010-05-24 18:36:31 +0000 2178--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-06-24 08:13:40.000000000 -0700
2176+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-05-03 15:14:56 +0000 2179+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c 2011-09-16 20:16:00.347564808 -0700
2177@@ -15,5 +15,5 @@ 2180@@ -15,5 +15,5 @@
2178 out_int64x2_t = vld1q_dup_s64 (0); 2181 out_int64x2_t = vld1q_dup_s64 (0);
2179 } 2182 }
@@ -2181,10 +2184,10 @@
2181-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2184-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2182+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2185+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2183 /* { dg-final { cleanup-saved-temps } } */ 2186 /* { dg-final { cleanup-saved-temps } } */
2184 2187Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
2185=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c' 2188===================================================================
2186--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2010-05-24 18:36:31 +0000 2189--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-06-24 08:13:40.000000000 -0700
2187+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-05-03 15:14:56 +0000 2190+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c 2011-09-16 20:16:00.347564808 -0700
2188@@ -15,5 +15,5 @@ 2191@@ -15,5 +15,5 @@
2189 out_int8x16_t = vld1q_dup_s8 (0); 2192 out_int8x16_t = vld1q_dup_s8 (0);
2190 } 2193 }
@@ -2192,10 +2195,10 @@
2192-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2195-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2193+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2196+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2194 /* { dg-final { cleanup-saved-temps } } */ 2197 /* { dg-final { cleanup-saved-temps } } */
2195 2198Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
2196=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c' 2199===================================================================
2197--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2010-05-24 18:36:31 +0000 2200--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-06-24 08:13:40.000000000 -0700
2198+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-05-03 15:14:56 +0000 2201+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c 2011-09-16 20:16:00.347564808 -0700
2199@@ -15,5 +15,5 @@ 2202@@ -15,5 +15,5 @@
2200 out_uint16x8_t = vld1q_dup_u16 (0); 2203 out_uint16x8_t = vld1q_dup_u16 (0);
2201 } 2204 }
@@ -2203,10 +2206,10 @@
2203-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2206-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2204+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2207+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2205 /* { dg-final { cleanup-saved-temps } } */ 2208 /* { dg-final { cleanup-saved-temps } } */
2206 2209Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
2207=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c' 2210===================================================================
2208--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2010-05-24 18:36:31 +0000 2211--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-06-24 08:13:40.000000000 -0700
2209+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-05-03 15:14:56 +0000 2212+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c 2011-09-16 20:16:00.347564808 -0700
2210@@ -15,5 +15,5 @@ 2213@@ -15,5 +15,5 @@
2211 out_uint32x4_t = vld1q_dup_u32 (0); 2214 out_uint32x4_t = vld1q_dup_u32 (0);
2212 } 2215 }
@@ -2214,10 +2217,10 @@
2214-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2217-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2215+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2218+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2216 /* { dg-final { cleanup-saved-temps } } */ 2219 /* { dg-final { cleanup-saved-temps } } */
2217 2220Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
2218=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c' 2221===================================================================
2219--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2010-05-24 18:36:31 +0000 2222--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-06-24 08:13:40.000000000 -0700
2220+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-05-03 15:14:56 +0000 2223+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c 2011-09-16 20:16:00.347564808 -0700
2221@@ -15,5 +15,5 @@ 2224@@ -15,5 +15,5 @@
2222 out_uint64x2_t = vld1q_dup_u64 (0); 2225 out_uint64x2_t = vld1q_dup_u64 (0);
2223 } 2226 }
@@ -2225,10 +2228,10 @@
2225-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2228-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2226+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2229+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2227 /* { dg-final { cleanup-saved-temps } } */ 2230 /* { dg-final { cleanup-saved-temps } } */
2228 2231Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
2229=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c' 2232===================================================================
2230--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2010-05-24 18:36:31 +0000 2233--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-06-24 08:13:40.000000000 -0700
2231+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-05-03 15:14:56 +0000 2234+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c 2011-09-16 20:16:00.347564808 -0700
2232@@ -15,5 +15,5 @@ 2235@@ -15,5 +15,5 @@
2233 out_uint8x16_t = vld1q_dup_u8 (0); 2236 out_uint8x16_t = vld1q_dup_u8 (0);
2234 } 2237 }
@@ -2236,10 +2239,10 @@
2236-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2239-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2237+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2240+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2238 /* { dg-final { cleanup-saved-temps } } */ 2241 /* { dg-final { cleanup-saved-temps } } */
2239 2242Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
2240=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c' 2243===================================================================
2241--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2010-05-24 18:36:31 +0000 2244--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2242+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-05-03 15:14:56 +0000 2245+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c 2011-09-16 20:16:00.347564808 -0700
2243@@ -16,5 +16,5 @@ 2246@@ -16,5 +16,5 @@
2244 out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1); 2247 out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
2245 } 2248 }
@@ -2247,10 +2250,10 @@
2247-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2250-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2248+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2251+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2249 /* { dg-final { cleanup-saved-temps } } */ 2252 /* { dg-final { cleanup-saved-temps } } */
2250 2253Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
2251=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c' 2254===================================================================
2252--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2010-05-24 18:36:31 +0000 2255--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2253+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-05-03 15:14:56 +0000 2256+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c 2011-09-16 20:16:00.347564808 -0700
2254@@ -16,5 +16,5 @@ 2257@@ -16,5 +16,5 @@
2255 out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1); 2258 out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
2256 } 2259 }
@@ -2258,10 +2261,10 @@
2258-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2261-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2259+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2262+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2260 /* { dg-final { cleanup-saved-temps } } */ 2263 /* { dg-final { cleanup-saved-temps } } */
2261 2264Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
2262=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c' 2265===================================================================
2263--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2010-05-24 18:36:31 +0000 2266--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
2264+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-05-03 15:14:56 +0000 2267+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c 2011-09-16 20:16:00.347564808 -0700
2265@@ -16,5 +16,5 @@ 2268@@ -16,5 +16,5 @@
2266 out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1); 2269 out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
2267 } 2270 }
@@ -2269,10 +2272,10 @@
2269-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2272-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2270+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2273+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2271 /* { dg-final { cleanup-saved-temps } } */ 2274 /* { dg-final { cleanup-saved-temps } } */
2272 2275Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
2273=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c' 2276===================================================================
2274--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2010-05-24 18:36:31 +0000 2277--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2275+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-05-03 15:14:56 +0000 2278+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c 2011-09-16 20:16:00.347564808 -0700
2276@@ -16,5 +16,5 @@ 2279@@ -16,5 +16,5 @@
2277 out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1); 2280 out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
2278 } 2281 }
@@ -2280,10 +2283,10 @@
2280-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2283-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2281+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2284+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2282 /* { dg-final { cleanup-saved-temps } } */ 2285 /* { dg-final { cleanup-saved-temps } } */
2283 2286Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
2284=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c' 2287===================================================================
2285--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2010-05-24 18:36:31 +0000 2288--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2286+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-05-03 15:14:56 +0000 2289+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c 2011-09-16 20:16:00.347564808 -0700
2287@@ -16,5 +16,5 @@ 2290@@ -16,5 +16,5 @@
2288 out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1); 2291 out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
2289 } 2292 }
@@ -2291,10 +2294,10 @@
2291-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2294-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2292+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2295+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2293 /* { dg-final { cleanup-saved-temps } } */ 2296 /* { dg-final { cleanup-saved-temps } } */
2294 2297Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
2295=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c' 2298===================================================================
2296--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2010-05-24 18:36:31 +0000 2299--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
2297+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-05-03 15:14:56 +0000 2300+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c 2011-09-16 20:16:00.347564808 -0700
2298@@ -16,5 +16,5 @@ 2301@@ -16,5 +16,5 @@
2299 out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1); 2302 out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
2300 } 2303 }
@@ -2302,10 +2305,10 @@
2302-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2305-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2303+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2306+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2304 /* { dg-final { cleanup-saved-temps } } */ 2307 /* { dg-final { cleanup-saved-temps } } */
2305 2308Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
2306=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c' 2309===================================================================
2307--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2010-05-24 18:36:31 +0000 2310--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
2308+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-05-03 15:14:56 +0000 2311+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c 2011-09-16 20:16:00.347564808 -0700
2309@@ -16,5 +16,5 @@ 2312@@ -16,5 +16,5 @@
2310 out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1); 2313 out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
2311 } 2314 }
@@ -2313,10 +2316,10 @@
2313-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2316-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2314+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2317+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2315 /* { dg-final { cleanup-saved-temps } } */ 2318 /* { dg-final { cleanup-saved-temps } } */
2316 2319Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
2317=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c' 2320===================================================================
2318--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2010-05-24 18:36:31 +0000 2321--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2319+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-05-03 15:14:56 +0000 2322+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c 2011-09-16 20:16:00.347564808 -0700
2320@@ -16,5 +16,5 @@ 2323@@ -16,5 +16,5 @@
2321 out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1); 2324 out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
2322 } 2325 }
@@ -2324,10 +2327,10 @@
2324-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2327-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2325+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2328+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2326 /* { dg-final { cleanup-saved-temps } } */ 2329 /* { dg-final { cleanup-saved-temps } } */
2327 2330Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
2328=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c' 2331===================================================================
2329--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2010-05-24 18:36:31 +0000 2332--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2330+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-05-03 15:14:56 +0000 2333+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c 2011-09-16 20:16:00.347564808 -0700
2331@@ -16,5 +16,5 @@ 2334@@ -16,5 +16,5 @@
2332 out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1); 2335 out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
2333 } 2336 }
@@ -2335,10 +2338,10 @@
2335-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2338-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2336+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2339+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2337 /* { dg-final { cleanup-saved-temps } } */ 2340 /* { dg-final { cleanup-saved-temps } } */
2338 2341Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
2339=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c' 2342===================================================================
2340--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2010-05-24 18:36:31 +0000 2343--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
2341+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-05-03 15:14:56 +0000 2344+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c 2011-09-16 20:16:00.347564808 -0700
2342@@ -16,5 +16,5 @@ 2345@@ -16,5 +16,5 @@
2343 out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1); 2346 out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
2344 } 2347 }
@@ -2346,10 +2349,10 @@
2346-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2349-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2347+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2350+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2348 /* { dg-final { cleanup-saved-temps } } */ 2351 /* { dg-final { cleanup-saved-temps } } */
2349 2352Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
2350=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c' 2353===================================================================
2351--- old/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2010-05-24 18:36:31 +0000 2354--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
2352+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-05-03 15:14:56 +0000 2355+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c 2011-09-16 20:16:00.347564808 -0700
2353@@ -16,5 +16,5 @@ 2356@@ -16,5 +16,5 @@
2354 out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1); 2357 out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
2355 } 2358 }
@@ -2357,10 +2360,10 @@
2357-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2360-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2358+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2361+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2359 /* { dg-final { cleanup-saved-temps } } */ 2362 /* { dg-final { cleanup-saved-temps } } */
2360 2363Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
2361=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c' 2364===================================================================
2362--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2010-05-24 18:36:31 +0000 2365--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-06-24 08:13:40.000000000 -0700
2363+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-05-03 15:14:56 +0000 2366+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c 2011-09-16 20:16:00.357564842 -0700
2364@@ -15,5 +15,5 @@ 2367@@ -15,5 +15,5 @@
2365 out_float32x4_t = vld1q_f32 (0); 2368 out_float32x4_t = vld1q_f32 (0);
2366 } 2369 }
@@ -2368,10 +2371,10 @@
2368-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2371-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2369+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2372+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2370 /* { dg-final { cleanup-saved-temps } } */ 2373 /* { dg-final { cleanup-saved-temps } } */
2371 2374Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
2372=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c' 2375===================================================================
2373--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2010-05-24 18:36:31 +0000 2376--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-06-24 08:13:40.000000000 -0700
2374+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-05-03 15:14:56 +0000 2377+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c 2011-09-16 20:16:00.357564842 -0700
2375@@ -15,5 +15,5 @@ 2378@@ -15,5 +15,5 @@
2376 out_poly16x8_t = vld1q_p16 (0); 2379 out_poly16x8_t = vld1q_p16 (0);
2377 } 2380 }
@@ -2379,10 +2382,10 @@
2379-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2382-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2380+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2383+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2381 /* { dg-final { cleanup-saved-temps } } */ 2384 /* { dg-final { cleanup-saved-temps } } */
2382 2385Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
2383=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c' 2386===================================================================
2384--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2010-05-24 18:36:31 +0000 2387--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-06-24 08:13:40.000000000 -0700
2385+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-05-03 15:14:56 +0000 2388+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c 2011-09-16 20:16:00.357564842 -0700
2386@@ -15,5 +15,5 @@ 2389@@ -15,5 +15,5 @@
2387 out_poly8x16_t = vld1q_p8 (0); 2390 out_poly8x16_t = vld1q_p8 (0);
2388 } 2391 }
@@ -2390,10 +2393,10 @@
2390-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2393-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2391+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2394+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2392 /* { dg-final { cleanup-saved-temps } } */ 2395 /* { dg-final { cleanup-saved-temps } } */
2393 2396Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
2394=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c' 2397===================================================================
2395--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2010-05-24 18:36:31 +0000 2398--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-06-24 08:13:40.000000000 -0700
2396+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-05-03 15:14:56 +0000 2399+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c 2011-09-16 20:16:00.357564842 -0700
2397@@ -15,5 +15,5 @@ 2400@@ -15,5 +15,5 @@
2398 out_int16x8_t = vld1q_s16 (0); 2401 out_int16x8_t = vld1q_s16 (0);
2399 } 2402 }
@@ -2401,10 +2404,10 @@
2401-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2404-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2402+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2405+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2403 /* { dg-final { cleanup-saved-temps } } */ 2406 /* { dg-final { cleanup-saved-temps } } */
2404 2407Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
2405=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c' 2408===================================================================
2406--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2010-05-24 18:36:31 +0000 2409--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-06-24 08:13:40.000000000 -0700
2407+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-05-03 15:14:56 +0000 2410+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c 2011-09-16 20:16:00.357564842 -0700
2408@@ -15,5 +15,5 @@ 2411@@ -15,5 +15,5 @@
2409 out_int32x4_t = vld1q_s32 (0); 2412 out_int32x4_t = vld1q_s32 (0);
2410 } 2413 }
@@ -2412,10 +2415,10 @@
2412-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2415-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2413+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2416+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2414 /* { dg-final { cleanup-saved-temps } } */ 2417 /* { dg-final { cleanup-saved-temps } } */
2415 2418Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
2416=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c' 2419===================================================================
2417--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2010-05-24 18:36:31 +0000 2420--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-06-24 08:13:40.000000000 -0700
2418+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-05-03 15:14:56 +0000 2421+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c 2011-09-16 20:16:00.357564842 -0700
2419@@ -15,5 +15,5 @@ 2422@@ -15,5 +15,5 @@
2420 out_int64x2_t = vld1q_s64 (0); 2423 out_int64x2_t = vld1q_s64 (0);
2421 } 2424 }
@@ -2423,10 +2426,10 @@
2423-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2426-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2424+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2427+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2425 /* { dg-final { cleanup-saved-temps } } */ 2428 /* { dg-final { cleanup-saved-temps } } */
2426 2429Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
2427=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c' 2430===================================================================
2428--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2010-05-24 18:36:31 +0000 2431--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-06-24 08:13:40.000000000 -0700
2429+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-05-03 15:14:56 +0000 2432+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c 2011-09-16 20:16:00.357564842 -0700
2430@@ -15,5 +15,5 @@ 2433@@ -15,5 +15,5 @@
2431 out_int8x16_t = vld1q_s8 (0); 2434 out_int8x16_t = vld1q_s8 (0);
2432 } 2435 }
@@ -2434,10 +2437,10 @@
2434-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2437-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2435+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2438+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2436 /* { dg-final { cleanup-saved-temps } } */ 2439 /* { dg-final { cleanup-saved-temps } } */
2437 2440Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
2438=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c' 2441===================================================================
2439--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2010-05-24 18:36:31 +0000 2442--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-06-24 08:13:40.000000000 -0700
2440+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-05-03 15:14:56 +0000 2443+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c 2011-09-16 20:16:00.357564842 -0700
2441@@ -15,5 +15,5 @@ 2444@@ -15,5 +15,5 @@
2442 out_uint16x8_t = vld1q_u16 (0); 2445 out_uint16x8_t = vld1q_u16 (0);
2443 } 2446 }
@@ -2445,10 +2448,10 @@
2445-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2448-/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2446+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2449+/* { dg-final { scan-assembler "vld1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2447 /* { dg-final { cleanup-saved-temps } } */ 2450 /* { dg-final { cleanup-saved-temps } } */
2448 2451Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
2449=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c' 2452===================================================================
2450--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2010-05-24 18:36:31 +0000 2453--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-06-24 08:13:40.000000000 -0700
2451+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-05-03 15:14:56 +0000 2454+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c 2011-09-16 20:16:00.357564842 -0700
2452@@ -15,5 +15,5 @@ 2455@@ -15,5 +15,5 @@
2453 out_uint32x4_t = vld1q_u32 (0); 2456 out_uint32x4_t = vld1q_u32 (0);
2454 } 2457 }
@@ -2456,10 +2459,10 @@
2456-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2459-/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2457+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2460+/* { dg-final { scan-assembler "vld1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2458 /* { dg-final { cleanup-saved-temps } } */ 2461 /* { dg-final { cleanup-saved-temps } } */
2459 2462Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
2460=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c' 2463===================================================================
2461--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2010-05-24 18:36:31 +0000 2464--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-06-24 08:13:40.000000000 -0700
2462+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-05-03 15:14:56 +0000 2465+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c 2011-09-16 20:16:00.357564842 -0700
2463@@ -15,5 +15,5 @@ 2466@@ -15,5 +15,5 @@
2464 out_uint64x2_t = vld1q_u64 (0); 2467 out_uint64x2_t = vld1q_u64 (0);
2465 } 2468 }
@@ -2467,10 +2470,10 @@
2467-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2470-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2468+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2471+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2469 /* { dg-final { cleanup-saved-temps } } */ 2472 /* { dg-final { cleanup-saved-temps } } */
2470 2473Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
2471=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c' 2474===================================================================
2472--- old/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2010-05-24 18:36:31 +0000 2475--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-06-24 08:13:40.000000000 -0700
2473+++ new/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-05-03 15:14:56 +0000 2476+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c 2011-09-16 20:16:00.357564842 -0700
2474@@ -15,5 +15,5 @@ 2477@@ -15,5 +15,5 @@
2475 out_uint8x16_t = vld1q_u8 (0); 2478 out_uint8x16_t = vld1q_u8 (0);
2476 } 2479 }
@@ -2478,10 +2481,10 @@
2478-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2481-/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2479+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2482+/* { dg-final { scan-assembler "vld1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2480 /* { dg-final { cleanup-saved-temps } } */ 2483 /* { dg-final { cleanup-saved-temps } } */
2481 2484Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
2482=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c' 2485===================================================================
2483--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2010-05-24 18:36:31 +0000 2486--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-06-24 08:13:40.000000000 -0700
2484+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-05-03 15:14:56 +0000 2487+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c 2011-09-16 20:16:00.357564842 -0700
2485@@ -15,5 +15,5 @@ 2488@@ -15,5 +15,5 @@
2486 out_float32x2_t = vld1_dup_f32 (0); 2489 out_float32x2_t = vld1_dup_f32 (0);
2487 } 2490 }
@@ -2489,10 +2492,10 @@
2489-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2492-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2490+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2493+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2491 /* { dg-final { cleanup-saved-temps } } */ 2494 /* { dg-final { cleanup-saved-temps } } */
2492 2495Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
2493=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c' 2496===================================================================
2494--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2010-05-24 18:36:31 +0000 2497--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-06-24 08:13:40.000000000 -0700
2495+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-05-03 15:14:56 +0000 2498+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c 2011-09-16 20:16:00.357564842 -0700
2496@@ -15,5 +15,5 @@ 2499@@ -15,5 +15,5 @@
2497 out_poly16x4_t = vld1_dup_p16 (0); 2500 out_poly16x4_t = vld1_dup_p16 (0);
2498 } 2501 }
@@ -2500,10 +2503,10 @@
2500-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2503-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2501+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2504+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2502 /* { dg-final { cleanup-saved-temps } } */ 2505 /* { dg-final { cleanup-saved-temps } } */
2503 2506Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
2504=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c' 2507===================================================================
2505--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2010-05-24 18:36:31 +0000 2508--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-06-24 08:13:40.000000000 -0700
2506+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-05-03 15:14:56 +0000 2509+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c 2011-09-16 20:16:00.357564842 -0700
2507@@ -15,5 +15,5 @@ 2510@@ -15,5 +15,5 @@
2508 out_poly8x8_t = vld1_dup_p8 (0); 2511 out_poly8x8_t = vld1_dup_p8 (0);
2509 } 2512 }
@@ -2511,10 +2514,10 @@
2511-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2514-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2512+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2515+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2513 /* { dg-final { cleanup-saved-temps } } */ 2516 /* { dg-final { cleanup-saved-temps } } */
2514 2517Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
2515=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c' 2518===================================================================
2516--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2010-05-24 18:36:31 +0000 2519--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-06-24 08:13:40.000000000 -0700
2517+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-05-03 15:14:56 +0000 2520+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c 2011-09-16 20:16:00.357564842 -0700
2518@@ -15,5 +15,5 @@ 2521@@ -15,5 +15,5 @@
2519 out_int16x4_t = vld1_dup_s16 (0); 2522 out_int16x4_t = vld1_dup_s16 (0);
2520 } 2523 }
@@ -2522,10 +2525,10 @@
2522-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2525-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2523+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2526+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2524 /* { dg-final { cleanup-saved-temps } } */ 2527 /* { dg-final { cleanup-saved-temps } } */
2525 2528Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
2526=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c' 2529===================================================================
2527--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2010-05-24 18:36:31 +0000 2530--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-06-24 08:13:40.000000000 -0700
2528+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-05-03 15:14:56 +0000 2531+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c 2011-09-16 20:16:00.357564842 -0700
2529@@ -15,5 +15,5 @@ 2532@@ -15,5 +15,5 @@
2530 out_int32x2_t = vld1_dup_s32 (0); 2533 out_int32x2_t = vld1_dup_s32 (0);
2531 } 2534 }
@@ -2533,10 +2536,10 @@
2533-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2536-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2534+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2537+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2535 /* { dg-final { cleanup-saved-temps } } */ 2538 /* { dg-final { cleanup-saved-temps } } */
2536 2539Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
2537=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c' 2540===================================================================
2538--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2010-05-24 18:36:31 +0000 2541--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-06-24 08:13:40.000000000 -0700
2539+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-05-03 15:14:56 +0000 2542+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c 2011-09-16 20:16:00.357564842 -0700
2540@@ -15,5 +15,5 @@ 2543@@ -15,5 +15,5 @@
2541 out_int64x1_t = vld1_dup_s64 (0); 2544 out_int64x1_t = vld1_dup_s64 (0);
2542 } 2545 }
@@ -2544,10 +2547,10 @@
2544-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2547-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2545+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2548+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2546 /* { dg-final { cleanup-saved-temps } } */ 2549 /* { dg-final { cleanup-saved-temps } } */
2547 2550Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
2548=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c' 2551===================================================================
2549--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2010-05-24 18:36:31 +0000 2552--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-06-24 08:13:40.000000000 -0700
2550+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-05-03 15:14:56 +0000 2553+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c 2011-09-16 20:16:00.357564842 -0700
2551@@ -15,5 +15,5 @@ 2554@@ -15,5 +15,5 @@
2552 out_int8x8_t = vld1_dup_s8 (0); 2555 out_int8x8_t = vld1_dup_s8 (0);
2553 } 2556 }
@@ -2555,10 +2558,10 @@
2555-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2558-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2556+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2559+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2557 /* { dg-final { cleanup-saved-temps } } */ 2560 /* { dg-final { cleanup-saved-temps } } */
2558 2561Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
2559=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c' 2562===================================================================
2560--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2010-05-24 18:36:31 +0000 2563--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-06-24 08:13:40.000000000 -0700
2561+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-05-03 15:14:56 +0000 2564+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c 2011-09-16 20:16:00.357564842 -0700
2562@@ -15,5 +15,5 @@ 2565@@ -15,5 +15,5 @@
2563 out_uint16x4_t = vld1_dup_u16 (0); 2566 out_uint16x4_t = vld1_dup_u16 (0);
2564 } 2567 }
@@ -2566,10 +2569,10 @@
2566-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2569-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2567+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2570+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2568 /* { dg-final { cleanup-saved-temps } } */ 2571 /* { dg-final { cleanup-saved-temps } } */
2569 2572Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
2570=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c' 2573===================================================================
2571--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2010-05-24 18:36:31 +0000 2574--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-06-24 08:13:40.000000000 -0700
2572+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-05-03 15:14:56 +0000 2575+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c 2011-09-16 20:16:00.357564842 -0700
2573@@ -15,5 +15,5 @@ 2576@@ -15,5 +15,5 @@
2574 out_uint32x2_t = vld1_dup_u32 (0); 2577 out_uint32x2_t = vld1_dup_u32 (0);
2575 } 2578 }
@@ -2577,10 +2580,10 @@
2577-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2580-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2578+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2581+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2579 /* { dg-final { cleanup-saved-temps } } */ 2582 /* { dg-final { cleanup-saved-temps } } */
2580 2583Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
2581=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c' 2584===================================================================
2582--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2010-05-24 18:36:31 +0000 2585--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-06-24 08:13:40.000000000 -0700
2583+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-05-03 15:14:56 +0000 2586+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c 2011-09-16 20:16:00.367564848 -0700
2584@@ -15,5 +15,5 @@ 2587@@ -15,5 +15,5 @@
2585 out_uint64x1_t = vld1_dup_u64 (0); 2588 out_uint64x1_t = vld1_dup_u64 (0);
2586 } 2589 }
@@ -2588,10 +2591,10 @@
2588-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2591-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2589+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2592+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2590 /* { dg-final { cleanup-saved-temps } } */ 2593 /* { dg-final { cleanup-saved-temps } } */
2591 2594Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
2592=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c' 2595===================================================================
2593--- old/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2010-05-24 18:36:31 +0000 2596--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-06-24 08:13:40.000000000 -0700
2594+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-05-03 15:14:56 +0000 2597+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c 2011-09-16 20:16:00.367564848 -0700
2595@@ -15,5 +15,5 @@ 2598@@ -15,5 +15,5 @@
2596 out_uint8x8_t = vld1_dup_u8 (0); 2599 out_uint8x8_t = vld1_dup_u8 (0);
2597 } 2600 }
@@ -2599,10 +2602,10 @@
2599-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2602-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2600+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2603+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2601 /* { dg-final { cleanup-saved-temps } } */ 2604 /* { dg-final { cleanup-saved-temps } } */
2602 2605Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
2603=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c' 2606===================================================================
2604--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2010-05-24 18:36:31 +0000 2607--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2605+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-05-03 15:14:56 +0000 2608+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c 2011-09-16 20:16:00.367564848 -0700
2606@@ -16,5 +16,5 @@ 2609@@ -16,5 +16,5 @@
2607 out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1); 2610 out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
2608 } 2611 }
@@ -2610,10 +2613,10 @@
2610-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2613-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2611+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2614+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2612 /* { dg-final { cleanup-saved-temps } } */ 2615 /* { dg-final { cleanup-saved-temps } } */
2613 2616Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
2614=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c' 2617===================================================================
2615--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2010-05-24 18:36:31 +0000 2618--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2616+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-05-03 15:14:56 +0000 2619+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c 2011-09-16 20:16:00.367564848 -0700
2617@@ -16,5 +16,5 @@ 2620@@ -16,5 +16,5 @@
2618 out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1); 2621 out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
2619 } 2622 }
@@ -2621,10 +2624,10 @@
2621-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2624-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2622+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2625+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2623 /* { dg-final { cleanup-saved-temps } } */ 2626 /* { dg-final { cleanup-saved-temps } } */
2624 2627Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
2625=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c' 2628===================================================================
2626--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2010-05-24 18:36:31 +0000 2629--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
2627+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-05-03 15:14:56 +0000 2630+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c 2011-09-16 20:16:00.367564848 -0700
2628@@ -16,5 +16,5 @@ 2631@@ -16,5 +16,5 @@
2629 out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1); 2632 out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
2630 } 2633 }
@@ -2632,10 +2635,10 @@
2632-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2635-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2633+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2636+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2634 /* { dg-final { cleanup-saved-temps } } */ 2637 /* { dg-final { cleanup-saved-temps } } */
2635 2638Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
2636=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c' 2639===================================================================
2637--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2010-05-24 18:36:31 +0000 2640--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2638+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-05-03 15:14:56 +0000 2641+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c 2011-09-16 20:16:00.367564848 -0700
2639@@ -16,5 +16,5 @@ 2642@@ -16,5 +16,5 @@
2640 out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1); 2643 out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
2641 } 2644 }
@@ -2643,10 +2646,10 @@
2643-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2646-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2644+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2647+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2645 /* { dg-final { cleanup-saved-temps } } */ 2648 /* { dg-final { cleanup-saved-temps } } */
2646 2649Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
2647=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c' 2650===================================================================
2648--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2010-05-24 18:36:31 +0000 2651--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2649+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-05-03 15:14:56 +0000 2652+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c 2011-09-16 20:16:00.367564848 -0700
2650@@ -16,5 +16,5 @@ 2653@@ -16,5 +16,5 @@
2651 out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1); 2654 out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
2652 } 2655 }
@@ -2654,10 +2657,10 @@
2654-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2657-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2655+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2658+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2656 /* { dg-final { cleanup-saved-temps } } */ 2659 /* { dg-final { cleanup-saved-temps } } */
2657 2660Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
2658=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c' 2661===================================================================
2659--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2010-05-24 18:36:31 +0000 2662--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
2660+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-05-03 15:14:56 +0000 2663+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c 2011-09-16 20:16:00.367564848 -0700
2661@@ -16,5 +16,5 @@ 2664@@ -16,5 +16,5 @@
2662 out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0); 2665 out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
2663 } 2666 }
@@ -2665,10 +2668,10 @@
2665-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2668-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2666+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2669+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2667 /* { dg-final { cleanup-saved-temps } } */ 2670 /* { dg-final { cleanup-saved-temps } } */
2668 2671Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
2669=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c' 2672===================================================================
2670--- old/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2010-05-24 18:36:31 +0000 2673--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
2671+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-05-03 15:14:56 +0000 2674+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c 2011-09-16 20:16:00.367564848 -0700
2672@@ -16,5 +16,5 @@ 2675@@ -16,5 +16,5 @@
2673 out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1); 2676 out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
2674 } 2677 }
@@ -2676,10 +2679,10 @@
2676-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2679-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2677+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2680+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2678 /* { dg-final { cleanup-saved-temps } } */ 2681 /* { dg-final { cleanup-saved-temps } } */
2679 2682Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
2680=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c' 2683===================================================================
2681--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2010-05-24 18:36:31 +0000 2684--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2682+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-05-03 15:14:56 +0000 2685+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c 2011-09-16 20:16:00.367564848 -0700
2683@@ -16,5 +16,5 @@ 2686@@ -16,5 +16,5 @@
2684 out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1); 2687 out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
2685 } 2688 }
@@ -2687,10 +2690,10 @@
2687-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2690-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2688+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2691+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2689 /* { dg-final { cleanup-saved-temps } } */ 2692 /* { dg-final { cleanup-saved-temps } } */
2690 2693Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
2691=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c' 2694===================================================================
2692--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2010-05-24 18:36:31 +0000 2695--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2693+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-05-03 15:14:56 +0000 2696+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c 2011-09-16 20:16:00.367564848 -0700
2694@@ -16,5 +16,5 @@ 2697@@ -16,5 +16,5 @@
2695 out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1); 2698 out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
2696 } 2699 }
@@ -2698,10 +2701,10 @@
2698-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2701-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2699+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2702+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2700 /* { dg-final { cleanup-saved-temps } } */ 2703 /* { dg-final { cleanup-saved-temps } } */
2701 2704Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
2702=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c' 2705===================================================================
2703--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2010-05-24 18:36:31 +0000 2706--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
2704+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-05-03 15:14:56 +0000 2707+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c 2011-09-16 20:16:00.367564848 -0700
2705@@ -16,5 +16,5 @@ 2708@@ -16,5 +16,5 @@
2706 out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0); 2709 out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
2707 } 2710 }
@@ -2709,10 +2712,10 @@
2709-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2712-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2710+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2713+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2711 /* { dg-final { cleanup-saved-temps } } */ 2714 /* { dg-final { cleanup-saved-temps } } */
2712 2715Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
2713=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c' 2716===================================================================
2714--- old/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2010-05-24 18:36:31 +0000 2717--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
2715+++ new/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-05-03 15:14:56 +0000 2718+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c 2011-09-16 20:16:00.367564848 -0700
2716@@ -16,5 +16,5 @@ 2719@@ -16,5 +16,5 @@
2717 out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1); 2720 out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
2718 } 2721 }
@@ -2720,10 +2723,10 @@
2720-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2723-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2721+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2724+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2722 /* { dg-final { cleanup-saved-temps } } */ 2725 /* { dg-final { cleanup-saved-temps } } */
2723 2726Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
2724=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1f32.c' 2727===================================================================
2725--- old/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2010-05-24 18:36:31 +0000 2728--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-06-24 08:13:40.000000000 -0700
2726+++ new/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-05-03 15:14:56 +0000 2729+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1f32.c 2011-09-16 20:16:00.367564848 -0700
2727@@ -15,5 +15,5 @@ 2730@@ -15,5 +15,5 @@
2728 out_float32x2_t = vld1_f32 (0); 2731 out_float32x2_t = vld1_f32 (0);
2729 } 2732 }
@@ -2731,10 +2734,10 @@
2731-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2734-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2732+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2735+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2733 /* { dg-final { cleanup-saved-temps } } */ 2736 /* { dg-final { cleanup-saved-temps } } */
2734 2737Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
2735=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p16.c' 2738===================================================================
2736--- old/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2010-05-24 18:36:31 +0000 2739--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-06-24 08:13:40.000000000 -0700
2737+++ new/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-05-03 15:14:56 +0000 2740+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p16.c 2011-09-16 20:16:00.377564842 -0700
2738@@ -15,5 +15,5 @@ 2741@@ -15,5 +15,5 @@
2739 out_poly16x4_t = vld1_p16 (0); 2742 out_poly16x4_t = vld1_p16 (0);
2740 } 2743 }
@@ -2742,10 +2745,10 @@
2742-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2745-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2743+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2746+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2744 /* { dg-final { cleanup-saved-temps } } */ 2747 /* { dg-final { cleanup-saved-temps } } */
2745 2748Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
2746=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1p8.c' 2749===================================================================
2747--- old/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2010-05-24 18:36:31 +0000 2750--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-06-24 08:13:40.000000000 -0700
2748+++ new/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-05-03 15:14:56 +0000 2751+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1p8.c 2011-09-16 20:16:00.377564842 -0700
2749@@ -15,5 +15,5 @@ 2752@@ -15,5 +15,5 @@
2750 out_poly8x8_t = vld1_p8 (0); 2753 out_poly8x8_t = vld1_p8 (0);
2751 } 2754 }
@@ -2753,10 +2756,10 @@
2753-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2756-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2754+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2757+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2755 /* { dg-final { cleanup-saved-temps } } */ 2758 /* { dg-final { cleanup-saved-temps } } */
2756 2759Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
2757=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s16.c' 2760===================================================================
2758--- old/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2010-05-24 18:36:31 +0000 2761--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-06-24 08:13:40.000000000 -0700
2759+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-05-03 15:14:56 +0000 2762+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s16.c 2011-09-16 20:16:00.377564842 -0700
2760@@ -15,5 +15,5 @@ 2763@@ -15,5 +15,5 @@
2761 out_int16x4_t = vld1_s16 (0); 2764 out_int16x4_t = vld1_s16 (0);
2762 } 2765 }
@@ -2764,10 +2767,10 @@
2764-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2767-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2765+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2768+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2766 /* { dg-final { cleanup-saved-temps } } */ 2769 /* { dg-final { cleanup-saved-temps } } */
2767 2770Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
2768=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s32.c' 2771===================================================================
2769--- old/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2010-05-24 18:36:31 +0000 2772--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-06-24 08:13:40.000000000 -0700
2770+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-05-03 15:14:56 +0000 2773+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s32.c 2011-09-16 20:16:00.377564842 -0700
2771@@ -15,5 +15,5 @@ 2774@@ -15,5 +15,5 @@
2772 out_int32x2_t = vld1_s32 (0); 2775 out_int32x2_t = vld1_s32 (0);
2773 } 2776 }
@@ -2775,10 +2778,10 @@
2775-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2778-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2776+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2779+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2777 /* { dg-final { cleanup-saved-temps } } */ 2780 /* { dg-final { cleanup-saved-temps } } */
2778 2781Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
2779=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s64.c' 2782===================================================================
2780--- old/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2010-05-24 18:36:31 +0000 2783--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-06-24 08:13:40.000000000 -0700
2781+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-05-03 15:14:56 +0000 2784+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s64.c 2011-09-16 20:16:00.377564842 -0700
2782@@ -15,5 +15,5 @@ 2785@@ -15,5 +15,5 @@
2783 out_int64x1_t = vld1_s64 (0); 2786 out_int64x1_t = vld1_s64 (0);
2784 } 2787 }
@@ -2786,10 +2789,10 @@
2786-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2789-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2787+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2790+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2788 /* { dg-final { cleanup-saved-temps } } */ 2791 /* { dg-final { cleanup-saved-temps } } */
2789 2792Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
2790=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1s8.c' 2793===================================================================
2791--- old/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2010-05-24 18:36:31 +0000 2794--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-06-24 08:13:40.000000000 -0700
2792+++ new/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-05-03 15:14:56 +0000 2795+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1s8.c 2011-09-16 20:16:00.377564842 -0700
2793@@ -15,5 +15,5 @@ 2796@@ -15,5 +15,5 @@
2794 out_int8x8_t = vld1_s8 (0); 2797 out_int8x8_t = vld1_s8 (0);
2795 } 2798 }
@@ -2797,10 +2800,10 @@
2797-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2800-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2798+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2801+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2799 /* { dg-final { cleanup-saved-temps } } */ 2802 /* { dg-final { cleanup-saved-temps } } */
2800 2803Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
2801=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u16.c' 2804===================================================================
2802--- old/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2010-05-24 18:36:31 +0000 2805--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-06-24 08:13:40.000000000 -0700
2803+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-05-03 15:14:56 +0000 2806+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u16.c 2011-09-16 20:16:00.377564842 -0700
2804@@ -15,5 +15,5 @@ 2807@@ -15,5 +15,5 @@
2805 out_uint16x4_t = vld1_u16 (0); 2808 out_uint16x4_t = vld1_u16 (0);
2806 } 2809 }
@@ -2808,10 +2811,10 @@
2808-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2811-/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2809+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2812+/* { dg-final { scan-assembler "vld1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2810 /* { dg-final { cleanup-saved-temps } } */ 2813 /* { dg-final { cleanup-saved-temps } } */
2811 2814Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
2812=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u32.c' 2815===================================================================
2813--- old/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2010-05-24 18:36:31 +0000 2816--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-06-24 08:13:40.000000000 -0700
2814+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-05-03 15:14:56 +0000 2817+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u32.c 2011-09-16 20:16:00.377564842 -0700
2815@@ -15,5 +15,5 @@ 2818@@ -15,5 +15,5 @@
2816 out_uint32x2_t = vld1_u32 (0); 2819 out_uint32x2_t = vld1_u32 (0);
2817 } 2820 }
@@ -2819,10 +2822,10 @@
2819-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2822-/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2820+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2823+/* { dg-final { scan-assembler "vld1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2821 /* { dg-final { cleanup-saved-temps } } */ 2824 /* { dg-final { cleanup-saved-temps } } */
2822 2825Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
2823=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u64.c' 2826===================================================================
2824--- old/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2010-05-24 18:36:31 +0000 2827--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-06-24 08:13:40.000000000 -0700
2825+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-05-03 15:14:56 +0000 2828+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u64.c 2011-09-16 20:16:00.377564842 -0700
2826@@ -15,5 +15,5 @@ 2829@@ -15,5 +15,5 @@
2827 out_uint64x1_t = vld1_u64 (0); 2830 out_uint64x1_t = vld1_u64 (0);
2828 } 2831 }
@@ -2830,10 +2833,10 @@
2830-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2833-/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2831+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2834+/* { dg-final { scan-assembler "vld1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2832 /* { dg-final { cleanup-saved-temps } } */ 2835 /* { dg-final { cleanup-saved-temps } } */
2833 2836Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
2834=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld1u8.c' 2837===================================================================
2835--- old/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2010-05-24 18:36:31 +0000 2838--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-06-24 08:13:40.000000000 -0700
2836+++ new/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-05-03 15:14:56 +0000 2839+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld1u8.c 2011-09-16 20:16:00.387564830 -0700
2837@@ -15,5 +15,5 @@ 2840@@ -15,5 +15,5 @@
2838 out_uint8x8_t = vld1_u8 (0); 2841 out_uint8x8_t = vld1_u8 (0);
2839 } 2842 }
@@ -2841,10 +2844,10 @@
2841-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2844-/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2842+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2845+/* { dg-final { scan-assembler "vld1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2843 /* { dg-final { cleanup-saved-temps } } */ 2846 /* { dg-final { cleanup-saved-temps } } */
2844 2847Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
2845=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c' 2848===================================================================
2846--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2010-05-24 18:36:31 +0000 2849--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
2847+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-05-03 15:14:56 +0000 2850+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c 2011-09-16 20:16:00.387564830 -0700
2848@@ -16,5 +16,5 @@ 2851@@ -16,5 +16,5 @@
2849 out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1); 2852 out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
2850 } 2853 }
@@ -2852,10 +2855,10 @@
2852-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2855-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2853+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2856+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2854 /* { dg-final { cleanup-saved-temps } } */ 2857 /* { dg-final { cleanup-saved-temps } } */
2855 2858Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
2856=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c' 2859===================================================================
2857--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2010-05-24 18:36:31 +0000 2860--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
2858+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-05-03 15:14:56 +0000 2861+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c 2011-09-16 20:16:00.387564830 -0700
2859@@ -16,5 +16,5 @@ 2862@@ -16,5 +16,5 @@
2860 out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1); 2863 out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
2861 } 2864 }
@@ -2863,10 +2866,10 @@
2863-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2866-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2864+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2867+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2865 /* { dg-final { cleanup-saved-temps } } */ 2868 /* { dg-final { cleanup-saved-temps } } */
2866 2869Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
2867=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c' 2870===================================================================
2868--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2010-05-24 18:36:31 +0000 2871--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
2869+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-05-03 15:14:56 +0000 2872+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c 2011-09-16 20:16:00.387564830 -0700
2870@@ -16,5 +16,5 @@ 2873@@ -16,5 +16,5 @@
2871 out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1); 2874 out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
2872 } 2875 }
@@ -2874,10 +2877,10 @@
2874-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2877-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2875+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2878+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2876 /* { dg-final { cleanup-saved-temps } } */ 2879 /* { dg-final { cleanup-saved-temps } } */
2877 2880Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
2878=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c' 2881===================================================================
2879--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2010-05-24 18:36:31 +0000 2882--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
2880+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-05-03 15:14:56 +0000 2883+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c 2011-09-16 20:16:00.387564830 -0700
2881@@ -16,5 +16,5 @@ 2884@@ -16,5 +16,5 @@
2882 out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1); 2885 out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
2883 } 2886 }
@@ -2885,10 +2888,10 @@
2885-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2888-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2886+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2889+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2887 /* { dg-final { cleanup-saved-temps } } */ 2890 /* { dg-final { cleanup-saved-temps } } */
2888 2891Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
2889=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c' 2892===================================================================
2890--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2010-05-24 18:36:31 +0000 2893--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
2891+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-05-03 15:14:56 +0000 2894+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c 2011-09-16 20:16:00.397564843 -0700
2892@@ -16,5 +16,5 @@ 2895@@ -16,5 +16,5 @@
2893 out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1); 2896 out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
2894 } 2897 }
@@ -2896,10 +2899,10 @@
2896-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2899-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2897+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2900+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2898 /* { dg-final { cleanup-saved-temps } } */ 2901 /* { dg-final { cleanup-saved-temps } } */
2899 2902Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
2900=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c' 2903===================================================================
2901--- old/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2010-05-24 18:36:31 +0000 2904--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
2902+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-05-03 15:14:56 +0000 2905+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c 2011-09-16 20:16:00.397564843 -0700
2903@@ -16,5 +16,5 @@ 2906@@ -16,5 +16,5 @@
2904 out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1); 2907 out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
2905 } 2908 }
@@ -2907,10 +2910,10 @@
2907-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2910-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2908+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2911+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2909 /* { dg-final { cleanup-saved-temps } } */ 2912 /* { dg-final { cleanup-saved-temps } } */
2910 2913Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
2911=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c' 2914===================================================================
2912--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2010-05-24 18:36:31 +0000 2915--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-06-24 08:13:40.000000000 -0700
2913+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-05-03 15:14:56 +0000 2916+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c 2011-09-16 20:16:00.397564843 -0700
2914@@ -15,6 +15,6 @@ 2917@@ -15,6 +15,6 @@
2915 out_float32x4x2_t = vld2q_f32 (0); 2918 out_float32x4x2_t = vld2q_f32 (0);
2916 } 2919 }
@@ -2920,10 +2923,10 @@
2920+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2923+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2921+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2924+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2922 /* { dg-final { cleanup-saved-temps } } */ 2925 /* { dg-final { cleanup-saved-temps } } */
2923 2926Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
2924=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c' 2927===================================================================
2925--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2010-05-24 18:36:31 +0000 2928--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-06-24 08:13:40.000000000 -0700
2926+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-05-03 15:14:56 +0000 2929+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c 2011-09-16 20:16:00.397564843 -0700
2927@@ -15,6 +15,6 @@ 2930@@ -15,6 +15,6 @@
2928 out_poly16x8x2_t = vld2q_p16 (0); 2931 out_poly16x8x2_t = vld2q_p16 (0);
2929 } 2932 }
@@ -2933,10 +2936,10 @@
2933+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2936+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2934+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2937+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2935 /* { dg-final { cleanup-saved-temps } } */ 2938 /* { dg-final { cleanup-saved-temps } } */
2936 2939Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
2937=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c' 2940===================================================================
2938--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2010-05-24 18:36:31 +0000 2941--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-06-24 08:13:40.000000000 -0700
2939+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-05-03 15:14:56 +0000 2942+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c 2011-09-16 20:16:00.397564843 -0700
2940@@ -15,6 +15,6 @@ 2943@@ -15,6 +15,6 @@
2941 out_poly8x16x2_t = vld2q_p8 (0); 2944 out_poly8x16x2_t = vld2q_p8 (0);
2942 } 2945 }
@@ -2946,10 +2949,10 @@
2946+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2949+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2947+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2950+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2948 /* { dg-final { cleanup-saved-temps } } */ 2951 /* { dg-final { cleanup-saved-temps } } */
2949 2952Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
2950=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c' 2953===================================================================
2951--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2010-05-24 18:36:31 +0000 2954--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-06-24 08:13:40.000000000 -0700
2952+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-05-03 15:14:56 +0000 2955+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c 2011-09-16 20:16:00.397564843 -0700
2953@@ -15,6 +15,6 @@ 2956@@ -15,6 +15,6 @@
2954 out_int16x8x2_t = vld2q_s16 (0); 2957 out_int16x8x2_t = vld2q_s16 (0);
2955 } 2958 }
@@ -2959,10 +2962,10 @@
2959+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2962+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2960+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2963+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2961 /* { dg-final { cleanup-saved-temps } } */ 2964 /* { dg-final { cleanup-saved-temps } } */
2962 2965Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
2963=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c' 2966===================================================================
2964--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2010-05-24 18:36:31 +0000 2967--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-06-24 08:13:40.000000000 -0700
2965+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-05-03 15:14:56 +0000 2968+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c 2011-09-16 20:16:00.397564843 -0700
2966@@ -15,6 +15,6 @@ 2969@@ -15,6 +15,6 @@
2967 out_int32x4x2_t = vld2q_s32 (0); 2970 out_int32x4x2_t = vld2q_s32 (0);
2968 } 2971 }
@@ -2972,10 +2975,10 @@
2972+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2975+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2973+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2976+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2974 /* { dg-final { cleanup-saved-temps } } */ 2977 /* { dg-final { cleanup-saved-temps } } */
2975 2978Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
2976=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c' 2979===================================================================
2977--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2010-05-24 18:36:31 +0000 2980--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-06-24 08:13:40.000000000 -0700
2978+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-05-03 15:14:56 +0000 2981+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c 2011-09-16 20:16:00.397564843 -0700
2979@@ -15,6 +15,6 @@ 2982@@ -15,6 +15,6 @@
2980 out_int8x16x2_t = vld2q_s8 (0); 2983 out_int8x16x2_t = vld2q_s8 (0);
2981 } 2984 }
@@ -2985,10 +2988,10 @@
2985+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2988+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2986+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 2989+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2987 /* { dg-final { cleanup-saved-temps } } */ 2990 /* { dg-final { cleanup-saved-temps } } */
2988 2991Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
2989=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c' 2992===================================================================
2990--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2010-05-24 18:36:31 +0000 2993--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-06-24 08:13:40.000000000 -0700
2991+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-05-03 15:14:56 +0000 2994+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c 2011-09-16 20:16:00.397564843 -0700
2992@@ -15,6 +15,6 @@ 2995@@ -15,6 +15,6 @@
2993 out_uint16x8x2_t = vld2q_u16 (0); 2996 out_uint16x8x2_t = vld2q_u16 (0);
2994 } 2997 }
@@ -2998,10 +3001,10 @@
2998+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3001+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
2999+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3002+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3000 /* { dg-final { cleanup-saved-temps } } */ 3003 /* { dg-final { cleanup-saved-temps } } */
3001 3004Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
3002=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c' 3005===================================================================
3003--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2010-05-24 18:36:31 +0000 3006--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-06-24 08:13:40.000000000 -0700
3004+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-05-03 15:14:56 +0000 3007+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c 2011-09-16 20:16:00.407564879 -0700
3005@@ -15,6 +15,6 @@ 3008@@ -15,6 +15,6 @@
3006 out_uint32x4x2_t = vld2q_u32 (0); 3009 out_uint32x4x2_t = vld2q_u32 (0);
3007 } 3010 }
@@ -3011,10 +3014,10 @@
3011+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3014+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3012+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3015+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3013 /* { dg-final { cleanup-saved-temps } } */ 3016 /* { dg-final { cleanup-saved-temps } } */
3014 3017Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
3015=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c' 3018===================================================================
3016--- old/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2010-05-24 18:36:31 +0000 3019--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-06-24 08:13:40.000000000 -0700
3017+++ new/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-05-03 15:14:56 +0000 3020+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c 2011-09-16 20:16:00.407564879 -0700
3018@@ -15,6 +15,6 @@ 3021@@ -15,6 +15,6 @@
3019 out_uint8x16x2_t = vld2q_u8 (0); 3022 out_uint8x16x2_t = vld2q_u8 (0);
3020 } 3023 }
@@ -3024,10 +3027,10 @@
3024+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3027+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3025+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3028+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3026 /* { dg-final { cleanup-saved-temps } } */ 3029 /* { dg-final { cleanup-saved-temps } } */
3027 3030Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
3028=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c' 3031===================================================================
3029--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2010-05-24 18:36:31 +0000 3032--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-06-24 08:13:40.000000000 -0700
3030+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-05-03 15:14:56 +0000 3033+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c 2011-09-16 20:16:00.407564879 -0700
3031@@ -15,5 +15,5 @@ 3034@@ -15,5 +15,5 @@
3032 out_float32x2x2_t = vld2_dup_f32 (0); 3035 out_float32x2x2_t = vld2_dup_f32 (0);
3033 } 3036 }
@@ -3035,10 +3038,10 @@
3035-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3038-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3036+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3039+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3037 /* { dg-final { cleanup-saved-temps } } */ 3040 /* { dg-final { cleanup-saved-temps } } */
3038 3041Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
3039=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c' 3042===================================================================
3040--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2010-05-24 18:36:31 +0000 3043--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-06-24 08:13:40.000000000 -0700
3041+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-05-03 15:14:56 +0000 3044+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c 2011-09-16 20:16:00.407564879 -0700
3042@@ -15,5 +15,5 @@ 3045@@ -15,5 +15,5 @@
3043 out_poly16x4x2_t = vld2_dup_p16 (0); 3046 out_poly16x4x2_t = vld2_dup_p16 (0);
3044 } 3047 }
@@ -3046,10 +3049,10 @@
3046-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3049-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3047+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3050+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3048 /* { dg-final { cleanup-saved-temps } } */ 3051 /* { dg-final { cleanup-saved-temps } } */
3049 3052Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
3050=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c' 3053===================================================================
3051--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2010-05-24 18:36:31 +0000 3054--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-06-24 08:13:40.000000000 -0700
3052+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-05-03 15:14:56 +0000 3055+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c 2011-09-16 20:16:00.407564879 -0700
3053@@ -15,5 +15,5 @@ 3056@@ -15,5 +15,5 @@
3054 out_poly8x8x2_t = vld2_dup_p8 (0); 3057 out_poly8x8x2_t = vld2_dup_p8 (0);
3055 } 3058 }
@@ -3057,10 +3060,10 @@
3057-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3060-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3058+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3061+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3059 /* { dg-final { cleanup-saved-temps } } */ 3062 /* { dg-final { cleanup-saved-temps } } */
3060 3063Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
3061=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c' 3064===================================================================
3062--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2010-05-24 18:36:31 +0000 3065--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-06-24 08:13:40.000000000 -0700
3063+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-05-03 15:14:56 +0000 3066+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c 2011-09-16 20:16:00.407564879 -0700
3064@@ -15,5 +15,5 @@ 3067@@ -15,5 +15,5 @@
3065 out_int16x4x2_t = vld2_dup_s16 (0); 3068 out_int16x4x2_t = vld2_dup_s16 (0);
3066 } 3069 }
@@ -3068,10 +3071,10 @@
3068-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3071-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3069+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3072+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3070 /* { dg-final { cleanup-saved-temps } } */ 3073 /* { dg-final { cleanup-saved-temps } } */
3071 3074Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
3072=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c' 3075===================================================================
3073--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2010-05-24 18:36:31 +0000 3076--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-06-24 08:13:40.000000000 -0700
3074+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-05-03 15:14:56 +0000 3077+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c 2011-09-16 20:16:00.407564879 -0700
3075@@ -15,5 +15,5 @@ 3078@@ -15,5 +15,5 @@
3076 out_int32x2x2_t = vld2_dup_s32 (0); 3079 out_int32x2x2_t = vld2_dup_s32 (0);
3077 } 3080 }
@@ -3079,10 +3082,10 @@
3079-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3082-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3080+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3083+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3081 /* { dg-final { cleanup-saved-temps } } */ 3084 /* { dg-final { cleanup-saved-temps } } */
3082 3085Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
3083=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c' 3086===================================================================
3084--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2010-05-24 18:36:31 +0000 3087--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-06-24 08:13:40.000000000 -0700
3085+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-05-03 15:14:56 +0000 3088+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c 2011-09-16 20:16:00.407564879 -0700
3086@@ -15,5 +15,5 @@ 3089@@ -15,5 +15,5 @@
3087 out_int64x1x2_t = vld2_dup_s64 (0); 3090 out_int64x1x2_t = vld2_dup_s64 (0);
3088 } 3091 }
@@ -3090,10 +3093,10 @@
3090-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3093-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3091+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3094+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3092 /* { dg-final { cleanup-saved-temps } } */ 3095 /* { dg-final { cleanup-saved-temps } } */
3093 3096Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
3094=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c' 3097===================================================================
3095--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2010-05-24 18:36:31 +0000 3098--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-06-24 08:13:40.000000000 -0700
3096+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-05-03 15:14:56 +0000 3099+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c 2011-09-16 20:16:00.417564906 -0700
3097@@ -15,5 +15,5 @@ 3100@@ -15,5 +15,5 @@
3098 out_int8x8x2_t = vld2_dup_s8 (0); 3101 out_int8x8x2_t = vld2_dup_s8 (0);
3099 } 3102 }
@@ -3101,10 +3104,10 @@
3101-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3104-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3102+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3105+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3103 /* { dg-final { cleanup-saved-temps } } */ 3106 /* { dg-final { cleanup-saved-temps } } */
3104 3107Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
3105=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c' 3108===================================================================
3106--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2010-05-24 18:36:31 +0000 3109--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-06-24 08:13:40.000000000 -0700
3107+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-05-03 15:14:56 +0000 3110+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c 2011-09-16 20:16:00.417564906 -0700
3108@@ -15,5 +15,5 @@ 3111@@ -15,5 +15,5 @@
3109 out_uint16x4x2_t = vld2_dup_u16 (0); 3112 out_uint16x4x2_t = vld2_dup_u16 (0);
3110 } 3113 }
@@ -3112,10 +3115,10 @@
3112-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3115-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3113+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3116+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3114 /* { dg-final { cleanup-saved-temps } } */ 3117 /* { dg-final { cleanup-saved-temps } } */
3115 3118Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
3116=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c' 3119===================================================================
3117--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2010-05-24 18:36:31 +0000 3120--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-06-24 08:13:40.000000000 -0700
3118+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-05-03 15:14:56 +0000 3121+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c 2011-09-16 20:16:00.417564906 -0700
3119@@ -15,5 +15,5 @@ 3122@@ -15,5 +15,5 @@
3120 out_uint32x2x2_t = vld2_dup_u32 (0); 3123 out_uint32x2x2_t = vld2_dup_u32 (0);
3121 } 3124 }
@@ -3123,10 +3126,10 @@
3123-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3126-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3124+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3127+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3125 /* { dg-final { cleanup-saved-temps } } */ 3128 /* { dg-final { cleanup-saved-temps } } */
3126 3129Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
3127=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c' 3130===================================================================
3128--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2010-05-24 18:36:31 +0000 3131--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-06-24 08:13:40.000000000 -0700
3129+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-05-03 15:14:56 +0000 3132+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c 2011-09-16 20:16:00.417564906 -0700
3130@@ -15,5 +15,5 @@ 3133@@ -15,5 +15,5 @@
3131 out_uint64x1x2_t = vld2_dup_u64 (0); 3134 out_uint64x1x2_t = vld2_dup_u64 (0);
3132 } 3135 }
@@ -3134,10 +3137,10 @@
3134-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3137-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3135+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3138+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3136 /* { dg-final { cleanup-saved-temps } } */ 3139 /* { dg-final { cleanup-saved-temps } } */
3137 3140Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
3138=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c' 3141===================================================================
3139--- old/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2010-05-24 18:36:31 +0000 3142--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-06-24 08:13:40.000000000 -0700
3140+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-05-03 15:14:56 +0000 3143+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c 2011-09-16 20:16:00.417564906 -0700
3141@@ -15,5 +15,5 @@ 3144@@ -15,5 +15,5 @@
3142 out_uint8x8x2_t = vld2_dup_u8 (0); 3145 out_uint8x8x2_t = vld2_dup_u8 (0);
3143 } 3146 }
@@ -3145,10 +3148,10 @@
3145-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3148-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3146+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3149+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3147 /* { dg-final { cleanup-saved-temps } } */ 3150 /* { dg-final { cleanup-saved-temps } } */
3148 3151Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
3149=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c' 3152===================================================================
3150--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2010-05-24 18:36:31 +0000 3153--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3151+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-05-03 15:14:56 +0000 3154+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c 2011-09-16 20:16:00.417564906 -0700
3152@@ -16,5 +16,5 @@ 3155@@ -16,5 +16,5 @@
3153 out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1); 3156 out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
3154 } 3157 }
@@ -3156,10 +3159,10 @@
3156-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3159-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3157+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3160+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3158 /* { dg-final { cleanup-saved-temps } } */ 3161 /* { dg-final { cleanup-saved-temps } } */
3159 3162Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
3160=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c' 3163===================================================================
3161--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2010-05-24 18:36:31 +0000 3164--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3162+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-05-03 15:14:56 +0000 3165+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c 2011-09-16 20:16:00.417564906 -0700
3163@@ -16,5 +16,5 @@ 3166@@ -16,5 +16,5 @@
3164 out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1); 3167 out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
3165 } 3168 }
@@ -3167,10 +3170,10 @@
3167-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3170-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3168+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3171+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3169 /* { dg-final { cleanup-saved-temps } } */ 3172 /* { dg-final { cleanup-saved-temps } } */
3170 3173Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
3171=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c' 3174===================================================================
3172--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2010-05-24 18:36:31 +0000 3175--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
3173+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-05-03 15:14:56 +0000 3176+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c 2011-09-16 20:16:00.417564906 -0700
3174@@ -16,5 +16,5 @@ 3177@@ -16,5 +16,5 @@
3175 out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1); 3178 out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
3176 } 3179 }
@@ -3178,10 +3181,10 @@
3178-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3181-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3179+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3182+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3180 /* { dg-final { cleanup-saved-temps } } */ 3183 /* { dg-final { cleanup-saved-temps } } */
3181 3184Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
3182=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c' 3185===================================================================
3183--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2010-05-24 18:36:31 +0000 3186--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3184+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-05-03 15:14:56 +0000 3187+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c 2011-09-16 20:16:00.417564906 -0700
3185@@ -16,5 +16,5 @@ 3188@@ -16,5 +16,5 @@
3186 out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1); 3189 out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
3187 } 3190 }
@@ -3189,10 +3192,10 @@
3189-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3192-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3190+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3193+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3191 /* { dg-final { cleanup-saved-temps } } */ 3194 /* { dg-final { cleanup-saved-temps } } */
3192 3195Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
3193=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c' 3196===================================================================
3194--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2010-05-24 18:36:31 +0000 3197--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3195+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-05-03 15:14:56 +0000 3198+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c 2011-09-16 20:16:00.417564906 -0700
3196@@ -16,5 +16,5 @@ 3199@@ -16,5 +16,5 @@
3197 out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1); 3200 out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
3198 } 3201 }
@@ -3200,10 +3203,10 @@
3200-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3203-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3201+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3204+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3202 /* { dg-final { cleanup-saved-temps } } */ 3205 /* { dg-final { cleanup-saved-temps } } */
3203 3206Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
3204=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c' 3207===================================================================
3205--- old/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2010-05-24 18:36:31 +0000 3208--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
3206+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-05-03 15:14:56 +0000 3209+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c 2011-09-16 20:16:00.417564906 -0700
3207@@ -16,5 +16,5 @@ 3210@@ -16,5 +16,5 @@
3208 out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1); 3211 out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
3209 } 3212 }
@@ -3211,10 +3214,10 @@
3211-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3214-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3212+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3215+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3213 /* { dg-final { cleanup-saved-temps } } */ 3216 /* { dg-final { cleanup-saved-temps } } */
3214 3217Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
3215=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c' 3218===================================================================
3216--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2010-05-24 18:36:31 +0000 3219--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3217+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-05-03 15:14:56 +0000 3220+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c 2011-09-16 20:16:00.417564906 -0700
3218@@ -16,5 +16,5 @@ 3221@@ -16,5 +16,5 @@
3219 out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1); 3222 out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
3220 } 3223 }
@@ -3222,10 +3225,10 @@
3222-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3225-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3223+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3226+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3224 /* { dg-final { cleanup-saved-temps } } */ 3227 /* { dg-final { cleanup-saved-temps } } */
3225 3228Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
3226=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c' 3229===================================================================
3227--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2010-05-24 18:36:31 +0000 3230--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3228+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-05-03 15:14:56 +0000 3231+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c 2011-09-16 20:16:00.417564906 -0700
3229@@ -16,5 +16,5 @@ 3232@@ -16,5 +16,5 @@
3230 out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1); 3233 out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
3231 } 3234 }
@@ -3233,10 +3236,10 @@
3233-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3236-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3234+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3237+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3235 /* { dg-final { cleanup-saved-temps } } */ 3238 /* { dg-final { cleanup-saved-temps } } */
3236 3239Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
3237=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c' 3240===================================================================
3238--- old/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2010-05-24 18:36:31 +0000 3241--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
3239+++ new/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-05-03 15:14:56 +0000 3242+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c 2011-09-16 20:16:00.417564906 -0700
3240@@ -16,5 +16,5 @@ 3243@@ -16,5 +16,5 @@
3241 out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1); 3244 out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
3242 } 3245 }
@@ -3244,10 +3247,10 @@
3244-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3247-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3245+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3248+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3246 /* { dg-final { cleanup-saved-temps } } */ 3249 /* { dg-final { cleanup-saved-temps } } */
3247 3250Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
3248=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2f32.c' 3251===================================================================
3249--- old/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2010-05-24 18:36:31 +0000 3252--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-06-24 08:13:40.000000000 -0700
3250+++ new/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-05-03 15:14:56 +0000 3253+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2f32.c 2011-09-16 20:16:00.427564921 -0700
3251@@ -15,5 +15,5 @@ 3254@@ -15,5 +15,5 @@
3252 out_float32x2x2_t = vld2_f32 (0); 3255 out_float32x2x2_t = vld2_f32 (0);
3253 } 3256 }
@@ -3255,10 +3258,10 @@
3255-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3258-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3256+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3259+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3257 /* { dg-final { cleanup-saved-temps } } */ 3260 /* { dg-final { cleanup-saved-temps } } */
3258 3261Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
3259=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p16.c' 3262===================================================================
3260--- old/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2010-05-24 18:36:31 +0000 3263--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-06-24 08:13:40.000000000 -0700
3261+++ new/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-05-03 15:14:56 +0000 3264+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p16.c 2011-09-16 20:16:00.427564921 -0700
3262@@ -15,5 +15,5 @@ 3265@@ -15,5 +15,5 @@
3263 out_poly16x4x2_t = vld2_p16 (0); 3266 out_poly16x4x2_t = vld2_p16 (0);
3264 } 3267 }
@@ -3266,10 +3269,10 @@
3266-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3269-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3267+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3270+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3268 /* { dg-final { cleanup-saved-temps } } */ 3271 /* { dg-final { cleanup-saved-temps } } */
3269 3272Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
3270=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2p8.c' 3273===================================================================
3271--- old/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2010-05-24 18:36:31 +0000 3274--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-06-24 08:13:40.000000000 -0700
3272+++ new/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-05-03 15:14:56 +0000 3275+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2p8.c 2011-09-16 20:16:00.427564921 -0700
3273@@ -15,5 +15,5 @@ 3276@@ -15,5 +15,5 @@
3274 out_poly8x8x2_t = vld2_p8 (0); 3277 out_poly8x8x2_t = vld2_p8 (0);
3275 } 3278 }
@@ -3277,10 +3280,10 @@
3277-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3280-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3278+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3281+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3279 /* { dg-final { cleanup-saved-temps } } */ 3282 /* { dg-final { cleanup-saved-temps } } */
3280 3283Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
3281=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s16.c' 3284===================================================================
3282--- old/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2010-05-24 18:36:31 +0000 3285--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-06-24 08:13:40.000000000 -0700
3283+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-05-03 15:14:56 +0000 3286+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s16.c 2011-09-16 20:16:00.427564921 -0700
3284@@ -15,5 +15,5 @@ 3287@@ -15,5 +15,5 @@
3285 out_int16x4x2_t = vld2_s16 (0); 3288 out_int16x4x2_t = vld2_s16 (0);
3286 } 3289 }
@@ -3288,10 +3291,10 @@
3288-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3291-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3289+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3292+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3290 /* { dg-final { cleanup-saved-temps } } */ 3293 /* { dg-final { cleanup-saved-temps } } */
3291 3294Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
3292=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s32.c' 3295===================================================================
3293--- old/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2010-05-24 18:36:31 +0000 3296--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-06-24 08:13:40.000000000 -0700
3294+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-05-03 15:14:56 +0000 3297+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s32.c 2011-09-16 20:16:00.427564921 -0700
3295@@ -15,5 +15,5 @@ 3298@@ -15,5 +15,5 @@
3296 out_int32x2x2_t = vld2_s32 (0); 3299 out_int32x2x2_t = vld2_s32 (0);
3297 } 3300 }
@@ -3299,10 +3302,10 @@
3299-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3302-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3300+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3303+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3301 /* { dg-final { cleanup-saved-temps } } */ 3304 /* { dg-final { cleanup-saved-temps } } */
3302 3305Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
3303=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s64.c' 3306===================================================================
3304--- old/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2010-05-24 18:36:31 +0000 3307--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-06-24 08:13:40.000000000 -0700
3305+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-05-03 15:14:56 +0000 3308+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s64.c 2011-09-16 20:16:00.427564921 -0700
3306@@ -15,5 +15,5 @@ 3309@@ -15,5 +15,5 @@
3307 out_int64x1x2_t = vld2_s64 (0); 3310 out_int64x1x2_t = vld2_s64 (0);
3308 } 3311 }
@@ -3310,10 +3313,10 @@
3310-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3313-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3311+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3314+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3312 /* { dg-final { cleanup-saved-temps } } */ 3315 /* { dg-final { cleanup-saved-temps } } */
3313 3316Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
3314=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2s8.c' 3317===================================================================
3315--- old/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2010-05-24 18:36:31 +0000 3318--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-06-24 08:13:40.000000000 -0700
3316+++ new/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-05-03 15:14:56 +0000 3319+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2s8.c 2011-09-16 20:16:00.437564924 -0700
3317@@ -15,5 +15,5 @@ 3320@@ -15,5 +15,5 @@
3318 out_int8x8x2_t = vld2_s8 (0); 3321 out_int8x8x2_t = vld2_s8 (0);
3319 } 3322 }
@@ -3321,10 +3324,10 @@
3321-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3324-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3322+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3325+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3323 /* { dg-final { cleanup-saved-temps } } */ 3326 /* { dg-final { cleanup-saved-temps } } */
3324 3327Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
3325=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u16.c' 3328===================================================================
3326--- old/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2010-05-24 18:36:31 +0000 3329--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-06-24 08:13:40.000000000 -0700
3327+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-05-03 15:14:56 +0000 3330+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u16.c 2011-09-16 20:16:00.437564924 -0700
3328@@ -15,5 +15,5 @@ 3331@@ -15,5 +15,5 @@
3329 out_uint16x4x2_t = vld2_u16 (0); 3332 out_uint16x4x2_t = vld2_u16 (0);
3330 } 3333 }
@@ -3332,10 +3335,10 @@
3332-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3335-/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3333+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3336+/* { dg-final { scan-assembler "vld2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3334 /* { dg-final { cleanup-saved-temps } } */ 3337 /* { dg-final { cleanup-saved-temps } } */
3335 3338Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
3336=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u32.c' 3339===================================================================
3337--- old/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2010-05-24 18:36:31 +0000 3340--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-06-24 08:13:40.000000000 -0700
3338+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-05-03 15:14:56 +0000 3341+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u32.c 2011-09-16 20:16:00.437564924 -0700
3339@@ -15,5 +15,5 @@ 3342@@ -15,5 +15,5 @@
3340 out_uint32x2x2_t = vld2_u32 (0); 3343 out_uint32x2x2_t = vld2_u32 (0);
3341 } 3344 }
@@ -3343,10 +3346,10 @@
3343-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3346-/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3344+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3347+/* { dg-final { scan-assembler "vld2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3345 /* { dg-final { cleanup-saved-temps } } */ 3348 /* { dg-final { cleanup-saved-temps } } */
3346 3349Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
3347=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u64.c' 3350===================================================================
3348--- old/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2010-05-24 18:36:31 +0000 3351--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-06-24 08:13:40.000000000 -0700
3349+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-05-03 15:14:56 +0000 3352+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u64.c 2011-09-16 20:16:00.437564924 -0700
3350@@ -15,5 +15,5 @@ 3353@@ -15,5 +15,5 @@
3351 out_uint64x1x2_t = vld2_u64 (0); 3354 out_uint64x1x2_t = vld2_u64 (0);
3352 } 3355 }
@@ -3354,10 +3357,10 @@
3354-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3357-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3355+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3358+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3356 /* { dg-final { cleanup-saved-temps } } */ 3359 /* { dg-final { cleanup-saved-temps } } */
3357 3360Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
3358=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld2u8.c' 3361===================================================================
3359--- old/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2010-05-24 18:36:31 +0000 3362--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-06-24 08:13:40.000000000 -0700
3360+++ new/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-05-03 15:14:56 +0000 3363+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld2u8.c 2011-09-16 20:16:00.437564924 -0700
3361@@ -15,5 +15,5 @@ 3364@@ -15,5 +15,5 @@
3362 out_uint8x8x2_t = vld2_u8 (0); 3365 out_uint8x8x2_t = vld2_u8 (0);
3363 } 3366 }
@@ -3365,10 +3368,10 @@
3365-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3368-/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3366+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3369+/* { dg-final { scan-assembler "vld2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3367 /* { dg-final { cleanup-saved-temps } } */ 3370 /* { dg-final { cleanup-saved-temps } } */
3368 3371Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
3369=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c' 3372===================================================================
3370--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2010-05-24 18:36:31 +0000 3373--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3371+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-05-03 15:14:56 +0000 3374+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c 2011-09-16 20:16:00.437564924 -0700
3372@@ -16,5 +16,5 @@ 3375@@ -16,5 +16,5 @@
3373 out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1); 3376 out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
3374 } 3377 }
@@ -3376,10 +3379,10 @@
3376-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3379-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3377+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3380+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3378 /* { dg-final { cleanup-saved-temps } } */ 3381 /* { dg-final { cleanup-saved-temps } } */
3379 3382Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
3380=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c' 3383===================================================================
3381--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2010-05-24 18:36:31 +0000 3384--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3382+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-05-03 15:14:56 +0000 3385+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c 2011-09-16 20:16:00.437564924 -0700
3383@@ -16,5 +16,5 @@ 3386@@ -16,5 +16,5 @@
3384 out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1); 3387 out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
3385 } 3388 }
@@ -3387,10 +3390,10 @@
3387-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3390-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3388+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3391+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3389 /* { dg-final { cleanup-saved-temps } } */ 3392 /* { dg-final { cleanup-saved-temps } } */
3390 3393Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
3391=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c' 3394===================================================================
3392--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2010-05-24 18:36:31 +0000 3395--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3393+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-05-03 15:14:56 +0000 3396+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c 2011-09-16 20:16:00.447564932 -0700
3394@@ -16,5 +16,5 @@ 3397@@ -16,5 +16,5 @@
3395 out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1); 3398 out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
3396 } 3399 }
@@ -3398,10 +3401,10 @@
3398-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3401-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3399+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3402+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3400 /* { dg-final { cleanup-saved-temps } } */ 3403 /* { dg-final { cleanup-saved-temps } } */
3401 3404Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
3402=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c' 3405===================================================================
3403--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2010-05-24 18:36:31 +0000 3406--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3404+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-05-03 15:14:56 +0000 3407+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c 2011-09-16 20:16:00.447564932 -0700
3405@@ -16,5 +16,5 @@ 3408@@ -16,5 +16,5 @@
3406 out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1); 3409 out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
3407 } 3410 }
@@ -3409,10 +3412,10 @@
3409-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3412-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3410+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3413+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3411 /* { dg-final { cleanup-saved-temps } } */ 3414 /* { dg-final { cleanup-saved-temps } } */
3412 3415Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
3413=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c' 3416===================================================================
3414--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2010-05-24 18:36:31 +0000 3417--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3415+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-05-03 15:14:56 +0000 3418+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c 2011-09-16 20:16:00.447564932 -0700
3416@@ -16,5 +16,5 @@ 3419@@ -16,5 +16,5 @@
3417 out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1); 3420 out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
3418 } 3421 }
@@ -3420,10 +3423,10 @@
3420-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3423-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3421+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3424+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3422 /* { dg-final { cleanup-saved-temps } } */ 3425 /* { dg-final { cleanup-saved-temps } } */
3423 3426Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
3424=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c' 3427===================================================================
3425--- old/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2010-05-24 18:36:31 +0000 3428--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3426+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-05-03 15:14:56 +0000 3429+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c 2011-09-16 20:16:00.447564932 -0700
3427@@ -16,5 +16,5 @@ 3430@@ -16,5 +16,5 @@
3428 out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1); 3431 out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
3429 } 3432 }
@@ -3431,10 +3434,10 @@
3431-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3434-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3432+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3435+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3433 /* { dg-final { cleanup-saved-temps } } */ 3436 /* { dg-final { cleanup-saved-temps } } */
3434 3437Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
3435=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c' 3438===================================================================
3436--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2010-05-24 18:36:31 +0000 3439--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-06-24 08:13:40.000000000 -0700
3437+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-05-03 15:14:56 +0000 3440+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c 2011-09-16 20:16:00.447564932 -0700
3438@@ -15,6 +15,6 @@ 3441@@ -15,6 +15,6 @@
3439 out_float32x4x3_t = vld3q_f32 (0); 3442 out_float32x4x3_t = vld3q_f32 (0);
3440 } 3443 }
@@ -3444,10 +3447,10 @@
3444+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3447+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3445+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3448+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3446 /* { dg-final { cleanup-saved-temps } } */ 3449 /* { dg-final { cleanup-saved-temps } } */
3447 3450Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
3448=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c' 3451===================================================================
3449--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2010-05-24 18:36:31 +0000 3452--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-06-24 08:13:40.000000000 -0700
3450+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-05-03 15:14:56 +0000 3453+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c 2011-09-16 20:16:00.447564932 -0700
3451@@ -15,6 +15,6 @@ 3454@@ -15,6 +15,6 @@
3452 out_poly16x8x3_t = vld3q_p16 (0); 3455 out_poly16x8x3_t = vld3q_p16 (0);
3453 } 3456 }
@@ -3457,10 +3460,10 @@
3457+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3460+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3458+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3461+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3459 /* { dg-final { cleanup-saved-temps } } */ 3462 /* { dg-final { cleanup-saved-temps } } */
3460 3463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
3461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c' 3464===================================================================
3462--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2010-05-24 18:36:31 +0000 3465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-06-24 08:13:40.000000000 -0700
3463+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-05-03 15:14:56 +0000 3466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c 2011-09-16 20:16:00.447564932 -0700
3464@@ -15,6 +15,6 @@ 3467@@ -15,6 +15,6 @@
3465 out_poly8x16x3_t = vld3q_p8 (0); 3468 out_poly8x16x3_t = vld3q_p8 (0);
3466 } 3469 }
@@ -3470,10 +3473,10 @@
3470+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3473+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3471+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3474+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3472 /* { dg-final { cleanup-saved-temps } } */ 3475 /* { dg-final { cleanup-saved-temps } } */
3473 3476Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
3474=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c' 3477===================================================================
3475--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2010-05-24 18:36:31 +0000 3478--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-06-24 08:13:40.000000000 -0700
3476+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-05-03 15:14:56 +0000 3479+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c 2011-09-16 20:16:00.447564932 -0700
3477@@ -15,6 +15,6 @@ 3480@@ -15,6 +15,6 @@
3478 out_int16x8x3_t = vld3q_s16 (0); 3481 out_int16x8x3_t = vld3q_s16 (0);
3479 } 3482 }
@@ -3483,10 +3486,10 @@
3483+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3486+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3484+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3487+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3485 /* { dg-final { cleanup-saved-temps } } */ 3488 /* { dg-final { cleanup-saved-temps } } */
3486 3489Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
3487=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c' 3490===================================================================
3488--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2010-05-24 18:36:31 +0000 3491--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-06-24 08:13:40.000000000 -0700
3489+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-05-03 15:14:56 +0000 3492+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c 2011-09-16 20:16:00.447564932 -0700
3490@@ -15,6 +15,6 @@ 3493@@ -15,6 +15,6 @@
3491 out_int32x4x3_t = vld3q_s32 (0); 3494 out_int32x4x3_t = vld3q_s32 (0);
3492 } 3495 }
@@ -3496,10 +3499,10 @@
3496+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3499+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3497+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3500+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3498 /* { dg-final { cleanup-saved-temps } } */ 3501 /* { dg-final { cleanup-saved-temps } } */
3499 3502Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
3500=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c' 3503===================================================================
3501--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2010-05-24 18:36:31 +0000 3504--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-06-24 08:13:40.000000000 -0700
3502+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-05-03 15:14:56 +0000 3505+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c 2011-09-16 20:16:00.447564932 -0700
3503@@ -15,6 +15,6 @@ 3506@@ -15,6 +15,6 @@
3504 out_int8x16x3_t = vld3q_s8 (0); 3507 out_int8x16x3_t = vld3q_s8 (0);
3505 } 3508 }
@@ -3509,10 +3512,10 @@
3509+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3512+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3510+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3513+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3511 /* { dg-final { cleanup-saved-temps } } */ 3514 /* { dg-final { cleanup-saved-temps } } */
3512 3515Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
3513=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c' 3516===================================================================
3514--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2010-05-24 18:36:31 +0000 3517--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-06-24 08:13:40.000000000 -0700
3515+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-05-03 15:14:56 +0000 3518+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c 2011-09-16 20:16:00.447564932 -0700
3516@@ -15,6 +15,6 @@ 3519@@ -15,6 +15,6 @@
3517 out_uint16x8x3_t = vld3q_u16 (0); 3520 out_uint16x8x3_t = vld3q_u16 (0);
3518 } 3521 }
@@ -3522,10 +3525,10 @@
3522+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3525+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3523+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3526+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3524 /* { dg-final { cleanup-saved-temps } } */ 3527 /* { dg-final { cleanup-saved-temps } } */
3525 3528Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
3526=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c' 3529===================================================================
3527--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2010-05-24 18:36:31 +0000 3530--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-06-24 08:13:40.000000000 -0700
3528+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-05-03 15:14:56 +0000 3531+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c 2011-09-16 20:16:00.447564932 -0700
3529@@ -15,6 +15,6 @@ 3532@@ -15,6 +15,6 @@
3530 out_uint32x4x3_t = vld3q_u32 (0); 3533 out_uint32x4x3_t = vld3q_u32 (0);
3531 } 3534 }
@@ -3535,10 +3538,10 @@
3535+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3538+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3536+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3539+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3537 /* { dg-final { cleanup-saved-temps } } */ 3540 /* { dg-final { cleanup-saved-temps } } */
3538 3541Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
3539=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c' 3542===================================================================
3540--- old/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2010-05-24 18:36:31 +0000 3543--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-06-24 08:13:40.000000000 -0700
3541+++ new/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-05-03 15:14:56 +0000 3544+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c 2011-09-16 20:16:00.457564944 -0700
3542@@ -15,6 +15,6 @@ 3545@@ -15,6 +15,6 @@
3543 out_uint8x16x3_t = vld3q_u8 (0); 3546 out_uint8x16x3_t = vld3q_u8 (0);
3544 } 3547 }
@@ -3548,10 +3551,10 @@
3548+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3551+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3549+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3552+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3550 /* { dg-final { cleanup-saved-temps } } */ 3553 /* { dg-final { cleanup-saved-temps } } */
3551 3554Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
3552=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c' 3555===================================================================
3553--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2010-05-24 18:36:31 +0000 3556--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-06-24 08:13:40.000000000 -0700
3554+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-05-03 15:14:56 +0000 3557+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c 2011-09-16 20:16:00.457564944 -0700
3555@@ -15,5 +15,5 @@ 3558@@ -15,5 +15,5 @@
3556 out_float32x2x3_t = vld3_dup_f32 (0); 3559 out_float32x2x3_t = vld3_dup_f32 (0);
3557 } 3560 }
@@ -3559,10 +3562,10 @@
3559-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3562-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3560+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3563+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3561 /* { dg-final { cleanup-saved-temps } } */ 3564 /* { dg-final { cleanup-saved-temps } } */
3562 3565Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
3563=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c' 3566===================================================================
3564--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2010-05-24 18:36:31 +0000 3567--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-06-24 08:13:40.000000000 -0700
3565+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-05-03 15:14:56 +0000 3568+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c 2011-09-16 20:16:00.457564944 -0700
3566@@ -15,5 +15,5 @@ 3569@@ -15,5 +15,5 @@
3567 out_poly16x4x3_t = vld3_dup_p16 (0); 3570 out_poly16x4x3_t = vld3_dup_p16 (0);
3568 } 3571 }
@@ -3570,10 +3573,10 @@
3570-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3573-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3571+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3574+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3572 /* { dg-final { cleanup-saved-temps } } */ 3575 /* { dg-final { cleanup-saved-temps } } */
3573 3576Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
3574=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c' 3577===================================================================
3575--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2010-05-24 18:36:31 +0000 3578--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-06-24 08:13:40.000000000 -0700
3576+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-05-03 15:14:56 +0000 3579+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c 2011-09-16 20:16:00.457564944 -0700
3577@@ -15,5 +15,5 @@ 3580@@ -15,5 +15,5 @@
3578 out_poly8x8x3_t = vld3_dup_p8 (0); 3581 out_poly8x8x3_t = vld3_dup_p8 (0);
3579 } 3582 }
@@ -3581,10 +3584,10 @@
3581-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3584-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3582+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3585+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3583 /* { dg-final { cleanup-saved-temps } } */ 3586 /* { dg-final { cleanup-saved-temps } } */
3584 3587Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
3585=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c' 3588===================================================================
3586--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2010-05-24 18:36:31 +0000 3589--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-06-24 08:13:40.000000000 -0700
3587+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-05-03 15:14:56 +0000 3590+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c 2011-09-16 20:16:00.457564944 -0700
3588@@ -15,5 +15,5 @@ 3591@@ -15,5 +15,5 @@
3589 out_int16x4x3_t = vld3_dup_s16 (0); 3592 out_int16x4x3_t = vld3_dup_s16 (0);
3590 } 3593 }
@@ -3592,10 +3595,10 @@
3592-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3595-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3593+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3596+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3594 /* { dg-final { cleanup-saved-temps } } */ 3597 /* { dg-final { cleanup-saved-temps } } */
3595 3598Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
3596=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c' 3599===================================================================
3597--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2010-05-24 18:36:31 +0000 3600--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-06-24 08:13:40.000000000 -0700
3598+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-05-03 15:14:56 +0000 3601+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c 2011-09-16 20:16:00.457564944 -0700
3599@@ -15,5 +15,5 @@ 3602@@ -15,5 +15,5 @@
3600 out_int32x2x3_t = vld3_dup_s32 (0); 3603 out_int32x2x3_t = vld3_dup_s32 (0);
3601 } 3604 }
@@ -3603,10 +3606,10 @@
3603-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3606-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3604+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3607+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3605 /* { dg-final { cleanup-saved-temps } } */ 3608 /* { dg-final { cleanup-saved-temps } } */
3606 3609Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
3607=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c' 3610===================================================================
3608--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2010-05-24 18:36:31 +0000 3611--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-06-24 08:13:40.000000000 -0700
3609+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-05-03 15:14:56 +0000 3612+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c 2011-09-16 20:16:00.457564944 -0700
3610@@ -15,5 +15,5 @@ 3613@@ -15,5 +15,5 @@
3611 out_int64x1x3_t = vld3_dup_s64 (0); 3614 out_int64x1x3_t = vld3_dup_s64 (0);
3612 } 3615 }
@@ -3614,10 +3617,10 @@
3614-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3617-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3615+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3618+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3616 /* { dg-final { cleanup-saved-temps } } */ 3619 /* { dg-final { cleanup-saved-temps } } */
3617 3620Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
3618=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c' 3621===================================================================
3619--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2010-05-24 18:36:31 +0000 3622--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-06-24 08:13:40.000000000 -0700
3620+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-05-03 15:14:56 +0000 3623+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c 2011-09-16 20:16:00.457564944 -0700
3621@@ -15,5 +15,5 @@ 3624@@ -15,5 +15,5 @@
3622 out_int8x8x3_t = vld3_dup_s8 (0); 3625 out_int8x8x3_t = vld3_dup_s8 (0);
3623 } 3626 }
@@ -3625,10 +3628,10 @@
3625-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3628-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3626+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3629+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3627 /* { dg-final { cleanup-saved-temps } } */ 3630 /* { dg-final { cleanup-saved-temps } } */
3628 3631Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
3629=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c' 3632===================================================================
3630--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2010-05-24 18:36:31 +0000 3633--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-06-24 08:13:40.000000000 -0700
3631+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-05-03 15:14:56 +0000 3634+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c 2011-09-16 20:16:00.457564944 -0700
3632@@ -15,5 +15,5 @@ 3635@@ -15,5 +15,5 @@
3633 out_uint16x4x3_t = vld3_dup_u16 (0); 3636 out_uint16x4x3_t = vld3_dup_u16 (0);
3634 } 3637 }
@@ -3636,10 +3639,10 @@
3636-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3639-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3637+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3640+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3638 /* { dg-final { cleanup-saved-temps } } */ 3641 /* { dg-final { cleanup-saved-temps } } */
3639 3642Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
3640=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c' 3643===================================================================
3641--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2010-05-24 18:36:31 +0000 3644--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-06-24 08:13:40.000000000 -0700
3642+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-05-03 15:14:56 +0000 3645+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c 2011-09-16 20:16:00.457564944 -0700
3643@@ -15,5 +15,5 @@ 3646@@ -15,5 +15,5 @@
3644 out_uint32x2x3_t = vld3_dup_u32 (0); 3647 out_uint32x2x3_t = vld3_dup_u32 (0);
3645 } 3648 }
@@ -3647,10 +3650,10 @@
3647-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3650-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3648+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3651+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3649 /* { dg-final { cleanup-saved-temps } } */ 3652 /* { dg-final { cleanup-saved-temps } } */
3650 3653Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
3651=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c' 3654===================================================================
3652--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2010-05-24 18:36:31 +0000 3655--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-06-24 08:13:40.000000000 -0700
3653+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-05-03 15:14:56 +0000 3656+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c 2011-09-16 20:16:00.457564944 -0700
3654@@ -15,5 +15,5 @@ 3657@@ -15,5 +15,5 @@
3655 out_uint64x1x3_t = vld3_dup_u64 (0); 3658 out_uint64x1x3_t = vld3_dup_u64 (0);
3656 } 3659 }
@@ -3658,10 +3661,10 @@
3658-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3661-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3659+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3662+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3660 /* { dg-final { cleanup-saved-temps } } */ 3663 /* { dg-final { cleanup-saved-temps } } */
3661 3664Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
3662=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c' 3665===================================================================
3663--- old/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2010-05-24 18:36:31 +0000 3666--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-06-24 08:13:40.000000000 -0700
3664+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-05-03 15:14:56 +0000 3667+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c 2011-09-16 20:16:00.457564944 -0700
3665@@ -15,5 +15,5 @@ 3668@@ -15,5 +15,5 @@
3666 out_uint8x8x3_t = vld3_dup_u8 (0); 3669 out_uint8x8x3_t = vld3_dup_u8 (0);
3667 } 3670 }
@@ -3669,10 +3672,10 @@
3669-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3672-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3670+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3673+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3671 /* { dg-final { cleanup-saved-temps } } */ 3674 /* { dg-final { cleanup-saved-temps } } */
3672 3675Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
3673=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c' 3676===================================================================
3674--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2010-05-24 18:36:31 +0000 3677--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3675+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-05-03 15:14:56 +0000 3678+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c 2011-09-16 20:16:00.457564944 -0700
3676@@ -16,5 +16,5 @@ 3679@@ -16,5 +16,5 @@
3677 out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1); 3680 out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
3678 } 3681 }
@@ -3680,10 +3683,10 @@
3680-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3683-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3681+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3684+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3682 /* { dg-final { cleanup-saved-temps } } */ 3685 /* { dg-final { cleanup-saved-temps } } */
3683 3686Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
3684=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c' 3687===================================================================
3685--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2010-05-24 18:36:31 +0000 3688--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3686+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-05-03 15:14:56 +0000 3689+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c 2011-09-16 20:16:00.457564944 -0700
3687@@ -16,5 +16,5 @@ 3690@@ -16,5 +16,5 @@
3688 out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1); 3691 out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
3689 } 3692 }
@@ -3691,10 +3694,10 @@
3691-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3694-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3692+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3695+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3693 /* { dg-final { cleanup-saved-temps } } */ 3696 /* { dg-final { cleanup-saved-temps } } */
3694 3697Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
3695=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c' 3698===================================================================
3696--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2010-05-24 18:36:31 +0000 3699--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
3697+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-05-03 15:14:56 +0000 3700+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c 2011-09-16 20:16:00.457564944 -0700
3698@@ -16,5 +16,5 @@ 3701@@ -16,5 +16,5 @@
3699 out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1); 3702 out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
3700 } 3703 }
@@ -3702,10 +3705,10 @@
3702-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3705-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3703+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3706+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3704 /* { dg-final { cleanup-saved-temps } } */ 3707 /* { dg-final { cleanup-saved-temps } } */
3705 3708Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
3706=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c' 3709===================================================================
3707--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2010-05-24 18:36:31 +0000 3710--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3708+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-05-03 15:14:56 +0000 3711+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c 2011-09-16 20:16:00.457564944 -0700
3709@@ -16,5 +16,5 @@ 3712@@ -16,5 +16,5 @@
3710 out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1); 3713 out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
3711 } 3714 }
@@ -3713,10 +3716,10 @@
3713-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3716-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3714+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3717+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3715 /* { dg-final { cleanup-saved-temps } } */ 3718 /* { dg-final { cleanup-saved-temps } } */
3716 3719Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
3717=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c' 3720===================================================================
3718--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2010-05-24 18:36:31 +0000 3721--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3719+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-05-03 15:14:56 +0000 3722+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c 2011-09-16 20:16:00.457564944 -0700
3720@@ -16,5 +16,5 @@ 3723@@ -16,5 +16,5 @@
3721 out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1); 3724 out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
3722 } 3725 }
@@ -3724,10 +3727,10 @@
3724-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3727-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3725+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3728+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3726 /* { dg-final { cleanup-saved-temps } } */ 3729 /* { dg-final { cleanup-saved-temps } } */
3727 3730Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
3728=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c' 3731===================================================================
3729--- old/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2010-05-24 18:36:31 +0000 3732--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
3730+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-05-03 15:14:56 +0000 3733+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c 2011-09-16 20:16:00.457564944 -0700
3731@@ -16,5 +16,5 @@ 3734@@ -16,5 +16,5 @@
3732 out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1); 3735 out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
3733 } 3736 }
@@ -3735,10 +3738,10 @@
3735-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3738-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3736+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3739+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3737 /* { dg-final { cleanup-saved-temps } } */ 3740 /* { dg-final { cleanup-saved-temps } } */
3738 3741Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
3739=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c' 3742===================================================================
3740--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2010-05-24 18:36:31 +0000 3743--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3741+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-05-03 15:14:56 +0000 3744+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c 2011-09-16 20:16:00.457564944 -0700
3742@@ -16,5 +16,5 @@ 3745@@ -16,5 +16,5 @@
3743 out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1); 3746 out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
3744 } 3747 }
@@ -3746,10 +3749,10 @@
3746-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3749-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3747+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3750+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3748 /* { dg-final { cleanup-saved-temps } } */ 3751 /* { dg-final { cleanup-saved-temps } } */
3749 3752Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
3750=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c' 3753===================================================================
3751--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2010-05-24 18:36:31 +0000 3754--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3752+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-05-03 15:14:56 +0000 3755+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c 2011-09-16 20:16:00.457564944 -0700
3753@@ -16,5 +16,5 @@ 3756@@ -16,5 +16,5 @@
3754 out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1); 3757 out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
3755 } 3758 }
@@ -3757,10 +3760,10 @@
3757-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3760-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3758+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3761+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3759 /* { dg-final { cleanup-saved-temps } } */ 3762 /* { dg-final { cleanup-saved-temps } } */
3760 3763Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
3761=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c' 3764===================================================================
3762--- old/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2010-05-24 18:36:31 +0000 3765--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
3763+++ new/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-05-03 15:14:56 +0000 3766+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c 2011-09-16 20:16:00.457564944 -0700
3764@@ -16,5 +16,5 @@ 3767@@ -16,5 +16,5 @@
3765 out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1); 3768 out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
3766 } 3769 }
@@ -3768,10 +3771,10 @@
3768-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3771-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3769+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3772+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3770 /* { dg-final { cleanup-saved-temps } } */ 3773 /* { dg-final { cleanup-saved-temps } } */
3771 3774Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
3772=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3f32.c' 3775===================================================================
3773--- old/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2010-05-24 18:36:31 +0000 3776--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-06-24 08:13:40.000000000 -0700
3774+++ new/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-05-03 15:14:56 +0000 3777+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3f32.c 2011-09-16 20:16:00.457564944 -0700
3775@@ -15,5 +15,5 @@ 3778@@ -15,5 +15,5 @@
3776 out_float32x2x3_t = vld3_f32 (0); 3779 out_float32x2x3_t = vld3_f32 (0);
3777 } 3780 }
@@ -3779,10 +3782,10 @@
3779-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3782-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3780+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3783+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3781 /* { dg-final { cleanup-saved-temps } } */ 3784 /* { dg-final { cleanup-saved-temps } } */
3782 3785Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
3783=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p16.c' 3786===================================================================
3784--- old/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2010-05-24 18:36:31 +0000 3787--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-06-24 08:13:40.000000000 -0700
3785+++ new/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-05-03 15:14:56 +0000 3788+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p16.c 2011-09-16 20:16:00.457564944 -0700
3786@@ -15,5 +15,5 @@ 3789@@ -15,5 +15,5 @@
3787 out_poly16x4x3_t = vld3_p16 (0); 3790 out_poly16x4x3_t = vld3_p16 (0);
3788 } 3791 }
@@ -3790,10 +3793,10 @@
3790-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3793-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3791+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3794+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3792 /* { dg-final { cleanup-saved-temps } } */ 3795 /* { dg-final { cleanup-saved-temps } } */
3793 3796Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
3794=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3p8.c' 3797===================================================================
3795--- old/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2010-05-24 18:36:31 +0000 3798--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-06-24 08:13:40.000000000 -0700
3796+++ new/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-05-03 15:14:56 +0000 3799+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3p8.c 2011-09-16 20:16:00.457564944 -0700
3797@@ -15,5 +15,5 @@ 3800@@ -15,5 +15,5 @@
3798 out_poly8x8x3_t = vld3_p8 (0); 3801 out_poly8x8x3_t = vld3_p8 (0);
3799 } 3802 }
@@ -3801,10 +3804,10 @@
3801-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3804-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3802+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3805+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3803 /* { dg-final { cleanup-saved-temps } } */ 3806 /* { dg-final { cleanup-saved-temps } } */
3804 3807Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
3805=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s16.c' 3808===================================================================
3806--- old/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2010-05-24 18:36:31 +0000 3809--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-06-24 08:13:40.000000000 -0700
3807+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-05-03 15:14:56 +0000 3810+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s16.c 2011-09-16 20:16:00.457564944 -0700
3808@@ -15,5 +15,5 @@ 3811@@ -15,5 +15,5 @@
3809 out_int16x4x3_t = vld3_s16 (0); 3812 out_int16x4x3_t = vld3_s16 (0);
3810 } 3813 }
@@ -3812,10 +3815,10 @@
3812-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3815-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3813+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3816+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3814 /* { dg-final { cleanup-saved-temps } } */ 3817 /* { dg-final { cleanup-saved-temps } } */
3815 3818Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
3816=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s32.c' 3819===================================================================
3817--- old/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2010-05-24 18:36:31 +0000 3820--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-06-24 08:13:40.000000000 -0700
3818+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-05-03 15:14:56 +0000 3821+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s32.c 2011-09-16 20:16:00.457564944 -0700
3819@@ -15,5 +15,5 @@ 3822@@ -15,5 +15,5 @@
3820 out_int32x2x3_t = vld3_s32 (0); 3823 out_int32x2x3_t = vld3_s32 (0);
3821 } 3824 }
@@ -3823,10 +3826,10 @@
3823-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3826-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3824+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3827+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3825 /* { dg-final { cleanup-saved-temps } } */ 3828 /* { dg-final { cleanup-saved-temps } } */
3826 3829Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
3827=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s64.c' 3830===================================================================
3828--- old/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2010-05-24 18:36:31 +0000 3831--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-06-24 08:13:40.000000000 -0700
3829+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-05-03 15:14:56 +0000 3832+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s64.c 2011-09-16 20:16:00.457564944 -0700
3830@@ -15,5 +15,5 @@ 3833@@ -15,5 +15,5 @@
3831 out_int64x1x3_t = vld3_s64 (0); 3834 out_int64x1x3_t = vld3_s64 (0);
3832 } 3835 }
@@ -3834,10 +3837,10 @@
3834-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3837-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3835+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3838+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3836 /* { dg-final { cleanup-saved-temps } } */ 3839 /* { dg-final { cleanup-saved-temps } } */
3837 3840Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
3838=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3s8.c' 3841===================================================================
3839--- old/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2010-05-24 18:36:31 +0000 3842--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-06-24 08:13:40.000000000 -0700
3840+++ new/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-05-03 15:14:56 +0000 3843+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3s8.c 2011-09-16 20:16:00.467564964 -0700
3841@@ -15,5 +15,5 @@ 3844@@ -15,5 +15,5 @@
3842 out_int8x8x3_t = vld3_s8 (0); 3845 out_int8x8x3_t = vld3_s8 (0);
3843 } 3846 }
@@ -3845,10 +3848,10 @@
3845-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3848-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3846+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3849+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3847 /* { dg-final { cleanup-saved-temps } } */ 3850 /* { dg-final { cleanup-saved-temps } } */
3848 3851Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
3849=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u16.c' 3852===================================================================
3850--- old/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2010-05-24 18:36:31 +0000 3853--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-06-24 08:13:40.000000000 -0700
3851+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-05-03 15:14:56 +0000 3854+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u16.c 2011-09-16 20:16:00.467564964 -0700
3852@@ -15,5 +15,5 @@ 3855@@ -15,5 +15,5 @@
3853 out_uint16x4x3_t = vld3_u16 (0); 3856 out_uint16x4x3_t = vld3_u16 (0);
3854 } 3857 }
@@ -3856,10 +3859,10 @@
3856-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3859-/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3857+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3860+/* { dg-final { scan-assembler "vld3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3858 /* { dg-final { cleanup-saved-temps } } */ 3861 /* { dg-final { cleanup-saved-temps } } */
3859 3862Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
3860=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u32.c' 3863===================================================================
3861--- old/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2010-05-24 18:36:31 +0000 3864--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-06-24 08:13:40.000000000 -0700
3862+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-05-03 15:14:56 +0000 3865+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u32.c 2011-09-16 20:16:00.467564964 -0700
3863@@ -15,5 +15,5 @@ 3866@@ -15,5 +15,5 @@
3864 out_uint32x2x3_t = vld3_u32 (0); 3867 out_uint32x2x3_t = vld3_u32 (0);
3865 } 3868 }
@@ -3867,10 +3870,10 @@
3867-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3870-/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3868+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3871+/* { dg-final { scan-assembler "vld3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3869 /* { dg-final { cleanup-saved-temps } } */ 3872 /* { dg-final { cleanup-saved-temps } } */
3870 3873Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
3871=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u64.c' 3874===================================================================
3872--- old/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2010-05-24 18:36:31 +0000 3875--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-06-24 08:13:40.000000000 -0700
3873+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-05-03 15:14:56 +0000 3876+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u64.c 2011-09-16 20:16:00.467564964 -0700
3874@@ -15,5 +15,5 @@ 3877@@ -15,5 +15,5 @@
3875 out_uint64x1x3_t = vld3_u64 (0); 3878 out_uint64x1x3_t = vld3_u64 (0);
3876 } 3879 }
@@ -3878,10 +3881,10 @@
3878-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3881-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3879+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3882+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3880 /* { dg-final { cleanup-saved-temps } } */ 3883 /* { dg-final { cleanup-saved-temps } } */
3881 3884Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
3882=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld3u8.c' 3885===================================================================
3883--- old/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2010-05-24 18:36:31 +0000 3886--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-06-24 08:13:40.000000000 -0700
3884+++ new/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-05-03 15:14:56 +0000 3887+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld3u8.c 2011-09-16 20:16:00.467564964 -0700
3885@@ -15,5 +15,5 @@ 3888@@ -15,5 +15,5 @@
3886 out_uint8x8x3_t = vld3_u8 (0); 3889 out_uint8x8x3_t = vld3_u8 (0);
3887 } 3890 }
@@ -3889,10 +3892,10 @@
3889-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3892-/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3890+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3893+/* { dg-final { scan-assembler "vld3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3891 /* { dg-final { cleanup-saved-temps } } */ 3894 /* { dg-final { cleanup-saved-temps } } */
3892 3895Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
3893=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c' 3896===================================================================
3894--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2010-05-24 18:36:31 +0000 3897--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
3895+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-05-03 15:14:56 +0000 3898+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c 2011-09-16 20:16:00.467564964 -0700
3896@@ -16,5 +16,5 @@ 3899@@ -16,5 +16,5 @@
3897 out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1); 3900 out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
3898 } 3901 }
@@ -3900,10 +3903,10 @@
3900-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3903-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3901+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3904+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3902 /* { dg-final { cleanup-saved-temps } } */ 3905 /* { dg-final { cleanup-saved-temps } } */
3903 3906Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
3904=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c' 3907===================================================================
3905--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2010-05-24 18:36:31 +0000 3908--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
3906+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-05-03 15:14:56 +0000 3909+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c 2011-09-16 20:16:00.467564964 -0700
3907@@ -16,5 +16,5 @@ 3910@@ -16,5 +16,5 @@
3908 out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1); 3911 out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
3909 } 3912 }
@@ -3911,10 +3914,10 @@
3911-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3914-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3912+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3915+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3913 /* { dg-final { cleanup-saved-temps } } */ 3916 /* { dg-final { cleanup-saved-temps } } */
3914 3917Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
3915=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c' 3918===================================================================
3916--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2010-05-24 18:36:31 +0000 3919--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
3917+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-05-03 15:14:56 +0000 3920+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c 2011-09-16 20:16:00.467564964 -0700
3918@@ -16,5 +16,5 @@ 3921@@ -16,5 +16,5 @@
3919 out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1); 3922 out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
3920 } 3923 }
@@ -3922,10 +3925,10 @@
3922-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3925-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3923+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3926+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3924 /* { dg-final { cleanup-saved-temps } } */ 3927 /* { dg-final { cleanup-saved-temps } } */
3925 3928Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
3926=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c' 3929===================================================================
3927--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2010-05-24 18:36:31 +0000 3930--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
3928+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-05-03 15:14:56 +0000 3931+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c 2011-09-16 20:16:00.467564964 -0700
3929@@ -16,5 +16,5 @@ 3932@@ -16,5 +16,5 @@
3930 out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1); 3933 out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
3931 } 3934 }
@@ -3933,10 +3936,10 @@
3933-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3936-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3934+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3937+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3935 /* { dg-final { cleanup-saved-temps } } */ 3938 /* { dg-final { cleanup-saved-temps } } */
3936 3939Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
3937=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c' 3940===================================================================
3938--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2010-05-24 18:36:31 +0000 3941--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
3939+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-05-03 15:14:56 +0000 3942+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c 2011-09-16 20:16:00.467564964 -0700
3940@@ -16,5 +16,5 @@ 3943@@ -16,5 +16,5 @@
3941 out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1); 3944 out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
3942 } 3945 }
@@ -3944,10 +3947,10 @@
3944-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3947-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3945+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3948+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3946 /* { dg-final { cleanup-saved-temps } } */ 3949 /* { dg-final { cleanup-saved-temps } } */
3947 3950Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
3948=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c' 3951===================================================================
3949--- old/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2010-05-24 18:36:31 +0000 3952--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
3950+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-05-03 15:14:56 +0000 3953+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c 2011-09-16 20:16:00.467564964 -0700
3951@@ -16,5 +16,5 @@ 3954@@ -16,5 +16,5 @@
3952 out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1); 3955 out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
3953 } 3956 }
@@ -3955,10 +3958,10 @@
3955-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3958-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3956+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3959+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3957 /* { dg-final { cleanup-saved-temps } } */ 3960 /* { dg-final { cleanup-saved-temps } } */
3958 3961Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
3959=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c' 3962===================================================================
3960--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2010-05-24 18:36:31 +0000 3963--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-06-24 08:13:40.000000000 -0700
3961+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-05-03 15:14:56 +0000 3964+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c 2011-09-16 20:16:00.467564964 -0700
3962@@ -15,6 +15,6 @@ 3965@@ -15,6 +15,6 @@
3963 out_float32x4x4_t = vld4q_f32 (0); 3966 out_float32x4x4_t = vld4q_f32 (0);
3964 } 3967 }
@@ -3968,10 +3971,10 @@
3968+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3971+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3969+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3972+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3970 /* { dg-final { cleanup-saved-temps } } */ 3973 /* { dg-final { cleanup-saved-temps } } */
3971 3974Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
3972=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c' 3975===================================================================
3973--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2010-05-24 18:36:31 +0000 3976--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-06-24 08:13:40.000000000 -0700
3974+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-05-03 15:14:56 +0000 3977+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c 2011-09-16 20:16:00.467564964 -0700
3975@@ -15,6 +15,6 @@ 3978@@ -15,6 +15,6 @@
3976 out_poly16x8x4_t = vld4q_p16 (0); 3979 out_poly16x8x4_t = vld4q_p16 (0);
3977 } 3980 }
@@ -3981,10 +3984,10 @@
3981+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3984+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3982+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3985+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3983 /* { dg-final { cleanup-saved-temps } } */ 3986 /* { dg-final { cleanup-saved-temps } } */
3984 3987Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
3985=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c' 3988===================================================================
3986--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2010-05-24 18:36:31 +0000 3989--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-06-24 08:13:40.000000000 -0700
3987+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-05-03 15:14:56 +0000 3990+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c 2011-09-16 20:16:00.467564964 -0700
3988@@ -15,6 +15,6 @@ 3991@@ -15,6 +15,6 @@
3989 out_poly8x16x4_t = vld4q_p8 (0); 3992 out_poly8x16x4_t = vld4q_p8 (0);
3990 } 3993 }
@@ -3994,10 +3997,10 @@
3994+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3997+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3995+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 3998+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
3996 /* { dg-final { cleanup-saved-temps } } */ 3999 /* { dg-final { cleanup-saved-temps } } */
3997 4000Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
3998=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c' 4001===================================================================
3999--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2010-05-24 18:36:31 +0000 4002--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-06-24 08:13:40.000000000 -0700
4000+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-05-03 15:14:56 +0000 4003+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c 2011-09-16 20:16:00.477564991 -0700
4001@@ -15,6 +15,6 @@ 4004@@ -15,6 +15,6 @@
4002 out_int16x8x4_t = vld4q_s16 (0); 4005 out_int16x8x4_t = vld4q_s16 (0);
4003 } 4006 }
@@ -4007,10 +4010,10 @@
4007+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4010+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4008+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4011+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4009 /* { dg-final { cleanup-saved-temps } } */ 4012 /* { dg-final { cleanup-saved-temps } } */
4010 4013Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
4011=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c' 4014===================================================================
4012--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2010-05-24 18:36:31 +0000 4015--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-06-24 08:13:40.000000000 -0700
4013+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-05-03 15:14:56 +0000 4016+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c 2011-09-16 20:16:00.477564991 -0700
4014@@ -15,6 +15,6 @@ 4017@@ -15,6 +15,6 @@
4015 out_int32x4x4_t = vld4q_s32 (0); 4018 out_int32x4x4_t = vld4q_s32 (0);
4016 } 4019 }
@@ -4020,10 +4023,10 @@
4020+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4023+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4021+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4024+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4022 /* { dg-final { cleanup-saved-temps } } */ 4025 /* { dg-final { cleanup-saved-temps } } */
4023 4026Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
4024=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c' 4027===================================================================
4025--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2010-05-24 18:36:31 +0000 4028--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-06-24 08:13:40.000000000 -0700
4026+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-05-03 15:14:56 +0000 4029+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c 2011-09-16 20:16:00.477564991 -0700
4027@@ -15,6 +15,6 @@ 4030@@ -15,6 +15,6 @@
4028 out_int8x16x4_t = vld4q_s8 (0); 4031 out_int8x16x4_t = vld4q_s8 (0);
4029 } 4032 }
@@ -4033,10 +4036,10 @@
4033+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4036+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4034+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4037+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4035 /* { dg-final { cleanup-saved-temps } } */ 4038 /* { dg-final { cleanup-saved-temps } } */
4036 4039Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
4037=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c' 4040===================================================================
4038--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2010-05-24 18:36:31 +0000 4041--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-06-24 08:13:40.000000000 -0700
4039+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-05-03 15:14:56 +0000 4042+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c 2011-09-16 20:16:00.477564991 -0700
4040@@ -15,6 +15,6 @@ 4043@@ -15,6 +15,6 @@
4041 out_uint16x8x4_t = vld4q_u16 (0); 4044 out_uint16x8x4_t = vld4q_u16 (0);
4042 } 4045 }
@@ -4046,10 +4049,10 @@
4046+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4049+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4047+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4050+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4048 /* { dg-final { cleanup-saved-temps } } */ 4051 /* { dg-final { cleanup-saved-temps } } */
4049 4052Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
4050=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c' 4053===================================================================
4051--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2010-05-24 18:36:31 +0000 4054--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-06-24 08:13:40.000000000 -0700
4052+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-05-03 15:14:56 +0000 4055+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c 2011-09-16 20:16:00.477564991 -0700
4053@@ -15,6 +15,6 @@ 4056@@ -15,6 +15,6 @@
4054 out_uint32x4x4_t = vld4q_u32 (0); 4057 out_uint32x4x4_t = vld4q_u32 (0);
4055 } 4058 }
@@ -4059,10 +4062,10 @@
4059+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4062+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4060+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4063+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4061 /* { dg-final { cleanup-saved-temps } } */ 4064 /* { dg-final { cleanup-saved-temps } } */
4062 4065Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
4063=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c' 4066===================================================================
4064--- old/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2010-05-24 18:36:31 +0000 4067--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-06-24 08:13:40.000000000 -0700
4065+++ new/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-05-03 15:14:56 +0000 4068+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c 2011-09-16 20:16:00.477564991 -0700
4066@@ -15,6 +15,6 @@ 4069@@ -15,6 +15,6 @@
4067 out_uint8x16x4_t = vld4q_u8 (0); 4070 out_uint8x16x4_t = vld4q_u8 (0);
4068 } 4071 }
@@ -4072,10 +4075,10 @@
4072+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4075+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4073+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4076+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4074 /* { dg-final { cleanup-saved-temps } } */ 4077 /* { dg-final { cleanup-saved-temps } } */
4075 4078Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
4076=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c' 4079===================================================================
4077--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2010-05-24 18:36:31 +0000 4080--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-06-24 08:13:40.000000000 -0700
4078+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-05-03 15:14:56 +0000 4081+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c 2011-09-16 20:16:00.477564991 -0700
4079@@ -15,5 +15,5 @@ 4082@@ -15,5 +15,5 @@
4080 out_float32x2x4_t = vld4_dup_f32 (0); 4083 out_float32x2x4_t = vld4_dup_f32 (0);
4081 } 4084 }
@@ -4083,10 +4086,10 @@
4083-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4086-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4084+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4087+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4085 /* { dg-final { cleanup-saved-temps } } */ 4088 /* { dg-final { cleanup-saved-temps } } */
4086 4089Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
4087=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c' 4090===================================================================
4088--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2010-05-24 18:36:31 +0000 4091--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-06-24 08:13:40.000000000 -0700
4089+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-05-03 15:14:56 +0000 4092+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c 2011-09-16 20:16:00.477564991 -0700
4090@@ -15,5 +15,5 @@ 4093@@ -15,5 +15,5 @@
4091 out_poly16x4x4_t = vld4_dup_p16 (0); 4094 out_poly16x4x4_t = vld4_dup_p16 (0);
4092 } 4095 }
@@ -4094,10 +4097,10 @@
4094-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4097-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4095+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4098+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4096 /* { dg-final { cleanup-saved-temps } } */ 4099 /* { dg-final { cleanup-saved-temps } } */
4097 4100Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
4098=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c' 4101===================================================================
4099--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2010-05-24 18:36:31 +0000 4102--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-06-24 08:13:40.000000000 -0700
4100+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-05-03 15:14:56 +0000 4103+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c 2011-09-16 20:16:00.477564991 -0700
4101@@ -15,5 +15,5 @@ 4104@@ -15,5 +15,5 @@
4102 out_poly8x8x4_t = vld4_dup_p8 (0); 4105 out_poly8x8x4_t = vld4_dup_p8 (0);
4103 } 4106 }
@@ -4105,10 +4108,10 @@
4105-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4108-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4106+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4109+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4107 /* { dg-final { cleanup-saved-temps } } */ 4110 /* { dg-final { cleanup-saved-temps } } */
4108 4111Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
4109=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c' 4112===================================================================
4110--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2010-05-24 18:36:31 +0000 4113--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-06-24 08:13:40.000000000 -0700
4111+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-05-03 15:14:56 +0000 4114+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c 2011-09-16 20:16:00.477564991 -0700
4112@@ -15,5 +15,5 @@ 4115@@ -15,5 +15,5 @@
4113 out_int16x4x4_t = vld4_dup_s16 (0); 4116 out_int16x4x4_t = vld4_dup_s16 (0);
4114 } 4117 }
@@ -4116,10 +4119,10 @@
4116-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4119-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4117+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4120+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4118 /* { dg-final { cleanup-saved-temps } } */ 4121 /* { dg-final { cleanup-saved-temps } } */
4119 4122Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
4120=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c' 4123===================================================================
4121--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2010-05-24 18:36:31 +0000 4124--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-06-24 08:13:40.000000000 -0700
4122+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-05-03 15:14:56 +0000 4125+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c 2011-09-16 20:16:00.477564991 -0700
4123@@ -15,5 +15,5 @@ 4126@@ -15,5 +15,5 @@
4124 out_int32x2x4_t = vld4_dup_s32 (0); 4127 out_int32x2x4_t = vld4_dup_s32 (0);
4125 } 4128 }
@@ -4127,10 +4130,10 @@
4127-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4130-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4128+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4131+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4129 /* { dg-final { cleanup-saved-temps } } */ 4132 /* { dg-final { cleanup-saved-temps } } */
4130 4133Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
4131=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c' 4134===================================================================
4132--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2010-05-24 18:36:31 +0000 4135--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-06-24 08:13:40.000000000 -0700
4133+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-05-03 15:14:56 +0000 4136+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c 2011-09-16 20:16:00.487565006 -0700
4134@@ -15,5 +15,5 @@ 4137@@ -15,5 +15,5 @@
4135 out_int64x1x4_t = vld4_dup_s64 (0); 4138 out_int64x1x4_t = vld4_dup_s64 (0);
4136 } 4139 }
@@ -4138,10 +4141,10 @@
4138-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4141-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4139+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4142+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4140 /* { dg-final { cleanup-saved-temps } } */ 4143 /* { dg-final { cleanup-saved-temps } } */
4141 4144Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
4142=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c' 4145===================================================================
4143--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2010-05-24 18:36:31 +0000 4146--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-06-24 08:13:40.000000000 -0700
4144+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-05-03 15:14:56 +0000 4147+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c 2011-09-16 20:16:00.487565006 -0700
4145@@ -15,5 +15,5 @@ 4148@@ -15,5 +15,5 @@
4146 out_int8x8x4_t = vld4_dup_s8 (0); 4149 out_int8x8x4_t = vld4_dup_s8 (0);
4147 } 4150 }
@@ -4149,10 +4152,10 @@
4149-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4152-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4150+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4153+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4151 /* { dg-final { cleanup-saved-temps } } */ 4154 /* { dg-final { cleanup-saved-temps } } */
4152 4155Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
4153=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c' 4156===================================================================
4154--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2010-05-24 18:36:31 +0000 4157--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-06-24 08:13:40.000000000 -0700
4155+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-05-03 15:14:56 +0000 4158+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c 2011-09-16 20:16:00.487565006 -0700
4156@@ -15,5 +15,5 @@ 4159@@ -15,5 +15,5 @@
4157 out_uint16x4x4_t = vld4_dup_u16 (0); 4160 out_uint16x4x4_t = vld4_dup_u16 (0);
4158 } 4161 }
@@ -4160,10 +4163,10 @@
4160-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4163-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4161+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4164+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4162 /* { dg-final { cleanup-saved-temps } } */ 4165 /* { dg-final { cleanup-saved-temps } } */
4163 4166Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
4164=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c' 4167===================================================================
4165--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2010-05-24 18:36:31 +0000 4168--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-06-24 08:13:40.000000000 -0700
4166+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-05-03 15:14:56 +0000 4169+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c 2011-09-16 20:16:00.487565006 -0700
4167@@ -15,5 +15,5 @@ 4170@@ -15,5 +15,5 @@
4168 out_uint32x2x4_t = vld4_dup_u32 (0); 4171 out_uint32x2x4_t = vld4_dup_u32 (0);
4169 } 4172 }
@@ -4171,10 +4174,10 @@
4171-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4174-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4172+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4175+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4173 /* { dg-final { cleanup-saved-temps } } */ 4176 /* { dg-final { cleanup-saved-temps } } */
4174 4177Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
4175=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c' 4178===================================================================
4176--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2010-05-24 18:36:31 +0000 4179--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-06-24 08:13:40.000000000 -0700
4177+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-05-03 15:14:56 +0000 4180+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c 2011-09-16 20:16:00.487565006 -0700
4178@@ -15,5 +15,5 @@ 4181@@ -15,5 +15,5 @@
4179 out_uint64x1x4_t = vld4_dup_u64 (0); 4182 out_uint64x1x4_t = vld4_dup_u64 (0);
4180 } 4183 }
@@ -4182,10 +4185,10 @@
4182-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4185-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4183+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4186+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4184 /* { dg-final { cleanup-saved-temps } } */ 4187 /* { dg-final { cleanup-saved-temps } } */
4185 4188Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
4186=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c' 4189===================================================================
4187--- old/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2010-05-24 18:36:31 +0000 4190--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-06-24 08:13:40.000000000 -0700
4188+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-05-03 15:14:56 +0000 4191+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c 2011-09-16 20:16:00.487565006 -0700
4189@@ -15,5 +15,5 @@ 4192@@ -15,5 +15,5 @@
4190 out_uint8x8x4_t = vld4_dup_u8 (0); 4193 out_uint8x8x4_t = vld4_dup_u8 (0);
4191 } 4194 }
@@ -4193,10 +4196,10 @@
4193-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4196-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4194+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4197+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4195 /* { dg-final { cleanup-saved-temps } } */ 4198 /* { dg-final { cleanup-saved-temps } } */
4196 4199Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
4197=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c' 4200===================================================================
4198--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2010-05-24 18:36:31 +0000 4201--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4199+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-05-03 15:14:56 +0000 4202+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c 2011-09-16 20:16:00.487565006 -0700
4200@@ -16,5 +16,5 @@ 4203@@ -16,5 +16,5 @@
4201 out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1); 4204 out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
4202 } 4205 }
@@ -4204,10 +4207,10 @@
4204-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4207-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4205+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4208+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4206 /* { dg-final { cleanup-saved-temps } } */ 4209 /* { dg-final { cleanup-saved-temps } } */
4207 4210Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
4208=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c' 4211===================================================================
4209--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2010-05-24 18:36:31 +0000 4212--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4210+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-05-03 15:14:56 +0000 4213+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c 2011-09-16 20:16:00.487565006 -0700
4211@@ -16,5 +16,5 @@ 4214@@ -16,5 +16,5 @@
4212 out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1); 4215 out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
4213 } 4216 }
@@ -4215,10 +4218,10 @@
4215-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4218-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4216+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4219+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4217 /* { dg-final { cleanup-saved-temps } } */ 4220 /* { dg-final { cleanup-saved-temps } } */
4218 4221Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
4219=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c' 4222===================================================================
4220--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2010-05-24 18:36:31 +0000 4223--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4221+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-05-03 15:14:56 +0000 4224+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c 2011-09-16 20:16:00.487565006 -0700
4222@@ -16,5 +16,5 @@ 4225@@ -16,5 +16,5 @@
4223 out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1); 4226 out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
4224 } 4227 }
@@ -4226,10 +4229,10 @@
4226-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4229-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4227+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4230+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4228 /* { dg-final { cleanup-saved-temps } } */ 4231 /* { dg-final { cleanup-saved-temps } } */
4229 4232Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
4230=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c' 4233===================================================================
4231--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2010-05-24 18:36:31 +0000 4234--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4232+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-05-03 15:14:56 +0000 4235+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c 2011-09-16 20:16:00.497565009 -0700
4233@@ -16,5 +16,5 @@ 4236@@ -16,5 +16,5 @@
4234 out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1); 4237 out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
4235 } 4238 }
@@ -4237,10 +4240,10 @@
4237-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4240-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4238+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4241+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4239 /* { dg-final { cleanup-saved-temps } } */ 4242 /* { dg-final { cleanup-saved-temps } } */
4240 4243Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
4241=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c' 4244===================================================================
4242--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2010-05-24 18:36:31 +0000 4245--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4243+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-05-03 15:14:56 +0000 4246+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c 2011-09-16 20:16:00.497565009 -0700
4244@@ -16,5 +16,5 @@ 4247@@ -16,5 +16,5 @@
4245 out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1); 4248 out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
4246 } 4249 }
@@ -4248,10 +4251,10 @@
4248-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4251-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4249+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4252+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4250 /* { dg-final { cleanup-saved-temps } } */ 4253 /* { dg-final { cleanup-saved-temps } } */
4251 4254Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
4252=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c' 4255===================================================================
4253--- old/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2010-05-24 18:36:31 +0000 4256--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4254+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-05-03 15:14:56 +0000 4257+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c 2011-09-16 20:16:00.497565009 -0700
4255@@ -16,5 +16,5 @@ 4258@@ -16,5 +16,5 @@
4256 out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1); 4259 out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
4257 } 4260 }
@@ -4259,10 +4262,10 @@
4259-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4262-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4260+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4263+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4261 /* { dg-final { cleanup-saved-temps } } */ 4264 /* { dg-final { cleanup-saved-temps } } */
4262 4265Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
4263=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c' 4266===================================================================
4264--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2010-05-24 18:36:31 +0000 4267--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4265+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-05-03 15:14:56 +0000 4268+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c 2011-09-16 20:16:00.497565009 -0700
4266@@ -16,5 +16,5 @@ 4269@@ -16,5 +16,5 @@
4267 out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1); 4270 out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
4268 } 4271 }
@@ -4270,10 +4273,10 @@
4270-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4273-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4271+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4274+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4272 /* { dg-final { cleanup-saved-temps } } */ 4275 /* { dg-final { cleanup-saved-temps } } */
4273 4276Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
4274=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c' 4277===================================================================
4275--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2010-05-24 18:36:31 +0000 4278--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4276+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-05-03 15:14:56 +0000 4279+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c 2011-09-16 20:16:00.497565009 -0700
4277@@ -16,5 +16,5 @@ 4280@@ -16,5 +16,5 @@
4278 out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1); 4281 out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
4279 } 4282 }
@@ -4281,10 +4284,10 @@
4281-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4284-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4282+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4285+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4283 /* { dg-final { cleanup-saved-temps } } */ 4286 /* { dg-final { cleanup-saved-temps } } */
4284 4287Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
4285=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c' 4288===================================================================
4286--- old/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2010-05-24 18:36:31 +0000 4289--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4287+++ new/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-05-03 15:14:56 +0000 4290+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c 2011-09-16 20:16:00.497565009 -0700
4288@@ -16,5 +16,5 @@ 4291@@ -16,5 +16,5 @@
4289 out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1); 4292 out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
4290 } 4293 }
@@ -4292,10 +4295,10 @@
4292-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4295-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4293+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4296+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4294 /* { dg-final { cleanup-saved-temps } } */ 4297 /* { dg-final { cleanup-saved-temps } } */
4295 4298Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
4296=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4f32.c' 4299===================================================================
4297--- old/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2010-05-24 18:36:31 +0000 4300--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-06-24 08:13:40.000000000 -0700
4298+++ new/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-05-03 15:14:56 +0000 4301+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4f32.c 2011-09-16 20:16:00.497565009 -0700
4299@@ -15,5 +15,5 @@ 4302@@ -15,5 +15,5 @@
4300 out_float32x2x4_t = vld4_f32 (0); 4303 out_float32x2x4_t = vld4_f32 (0);
4301 } 4304 }
@@ -4303,10 +4306,10 @@
4303-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4306-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4304+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4307+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4305 /* { dg-final { cleanup-saved-temps } } */ 4308 /* { dg-final { cleanup-saved-temps } } */
4306 4309Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
4307=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p16.c' 4310===================================================================
4308--- old/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2010-05-24 18:36:31 +0000 4311--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-06-24 08:13:40.000000000 -0700
4309+++ new/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-05-03 15:14:56 +0000 4312+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p16.c 2011-09-16 20:16:00.497565009 -0700
4310@@ -15,5 +15,5 @@ 4313@@ -15,5 +15,5 @@
4311 out_poly16x4x4_t = vld4_p16 (0); 4314 out_poly16x4x4_t = vld4_p16 (0);
4312 } 4315 }
@@ -4314,10 +4317,10 @@
4314-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4317-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4315+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4318+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4316 /* { dg-final { cleanup-saved-temps } } */ 4319 /* { dg-final { cleanup-saved-temps } } */
4317 4320Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
4318=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4p8.c' 4321===================================================================
4319--- old/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2010-05-24 18:36:31 +0000 4322--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-06-24 08:13:40.000000000 -0700
4320+++ new/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-05-03 15:14:56 +0000 4323+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4p8.c 2011-09-16 20:16:00.497565009 -0700
4321@@ -15,5 +15,5 @@ 4324@@ -15,5 +15,5 @@
4322 out_poly8x8x4_t = vld4_p8 (0); 4325 out_poly8x8x4_t = vld4_p8 (0);
4323 } 4326 }
@@ -4325,10 +4328,10 @@
4325-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4328-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4326+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4329+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4327 /* { dg-final { cleanup-saved-temps } } */ 4330 /* { dg-final { cleanup-saved-temps } } */
4328 4331Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
4329=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s16.c' 4332===================================================================
4330--- old/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2010-05-24 18:36:31 +0000 4333--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-06-24 08:13:40.000000000 -0700
4331+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-05-03 15:14:56 +0000 4334+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s16.c 2011-09-16 20:16:00.497565009 -0700
4332@@ -15,5 +15,5 @@ 4335@@ -15,5 +15,5 @@
4333 out_int16x4x4_t = vld4_s16 (0); 4336 out_int16x4x4_t = vld4_s16 (0);
4334 } 4337 }
@@ -4336,10 +4339,10 @@
4336-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4339-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4337+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4340+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4338 /* { dg-final { cleanup-saved-temps } } */ 4341 /* { dg-final { cleanup-saved-temps } } */
4339 4342Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
4340=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s32.c' 4343===================================================================
4341--- old/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2010-05-24 18:36:31 +0000 4344--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-06-24 08:13:40.000000000 -0700
4342+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-05-03 15:14:56 +0000 4345+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s32.c 2011-09-16 20:16:00.497565009 -0700
4343@@ -15,5 +15,5 @@ 4346@@ -15,5 +15,5 @@
4344 out_int32x2x4_t = vld4_s32 (0); 4347 out_int32x2x4_t = vld4_s32 (0);
4345 } 4348 }
@@ -4347,10 +4350,10 @@
4347-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4350-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4348+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4351+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4349 /* { dg-final { cleanup-saved-temps } } */ 4352 /* { dg-final { cleanup-saved-temps } } */
4350 4353Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
4351=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s64.c' 4354===================================================================
4352--- old/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2010-05-24 18:36:31 +0000 4355--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-06-24 08:13:40.000000000 -0700
4353+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-05-03 15:14:56 +0000 4356+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s64.c 2011-09-16 20:16:00.497565009 -0700
4354@@ -15,5 +15,5 @@ 4357@@ -15,5 +15,5 @@
4355 out_int64x1x4_t = vld4_s64 (0); 4358 out_int64x1x4_t = vld4_s64 (0);
4356 } 4359 }
@@ -4358,10 +4361,10 @@
4358-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4361-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4359+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4362+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4360 /* { dg-final { cleanup-saved-temps } } */ 4363 /* { dg-final { cleanup-saved-temps } } */
4361 4364Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
4362=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4s8.c' 4365===================================================================
4363--- old/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2010-05-24 18:36:31 +0000 4366--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-06-24 08:13:40.000000000 -0700
4364+++ new/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-05-03 15:14:56 +0000 4367+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4s8.c 2011-09-16 20:16:00.497565009 -0700
4365@@ -15,5 +15,5 @@ 4368@@ -15,5 +15,5 @@
4366 out_int8x8x4_t = vld4_s8 (0); 4369 out_int8x8x4_t = vld4_s8 (0);
4367 } 4370 }
@@ -4369,10 +4372,10 @@
4369-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4372-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4370+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4373+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4371 /* { dg-final { cleanup-saved-temps } } */ 4374 /* { dg-final { cleanup-saved-temps } } */
4372 4375Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
4373=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u16.c' 4376===================================================================
4374--- old/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2010-05-24 18:36:31 +0000 4377--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-06-24 08:13:40.000000000 -0700
4375+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-05-03 15:14:56 +0000 4378+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u16.c 2011-09-16 20:16:00.497565009 -0700
4376@@ -15,5 +15,5 @@ 4379@@ -15,5 +15,5 @@
4377 out_uint16x4x4_t = vld4_u16 (0); 4380 out_uint16x4x4_t = vld4_u16 (0);
4378 } 4381 }
@@ -4380,10 +4383,10 @@
4380-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4383-/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4381+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4384+/* { dg-final { scan-assembler "vld4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4382 /* { dg-final { cleanup-saved-temps } } */ 4385 /* { dg-final { cleanup-saved-temps } } */
4383 4386Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
4384=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u32.c' 4387===================================================================
4385--- old/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2010-05-24 18:36:31 +0000 4388--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-06-24 08:13:40.000000000 -0700
4386+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-05-03 15:14:56 +0000 4389+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u32.c 2011-09-16 20:16:00.507565013 -0700
4387@@ -15,5 +15,5 @@ 4390@@ -15,5 +15,5 @@
4388 out_uint32x2x4_t = vld4_u32 (0); 4391 out_uint32x2x4_t = vld4_u32 (0);
4389 } 4392 }
@@ -4391,10 +4394,10 @@
4391-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4394-/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4392+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4395+/* { dg-final { scan-assembler "vld4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4393 /* { dg-final { cleanup-saved-temps } } */ 4396 /* { dg-final { cleanup-saved-temps } } */
4394 4397Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
4395=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u64.c' 4398===================================================================
4396--- old/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2010-05-24 18:36:31 +0000 4399--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-06-24 08:13:40.000000000 -0700
4397+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-05-03 15:14:56 +0000 4400+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u64.c 2011-09-16 20:16:00.507565013 -0700
4398@@ -15,5 +15,5 @@ 4401@@ -15,5 +15,5 @@
4399 out_uint64x1x4_t = vld4_u64 (0); 4402 out_uint64x1x4_t = vld4_u64 (0);
4400 } 4403 }
@@ -4402,10 +4405,10 @@
4402-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4405-/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4403+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4406+/* { dg-final { scan-assembler "vld1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4404 /* { dg-final { cleanup-saved-temps } } */ 4407 /* { dg-final { cleanup-saved-temps } } */
4405 4408Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
4406=== modified file 'gcc/testsuite/gcc.target/arm/neon/vld4u8.c' 4409===================================================================
4407--- old/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2010-05-24 18:36:31 +0000 4410--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-06-24 08:13:40.000000000 -0700
4408+++ new/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-05-03 15:14:56 +0000 4411+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vld4u8.c 2011-09-16 20:16:00.507565013 -0700
4409@@ -15,5 +15,5 @@ 4412@@ -15,5 +15,5 @@
4410 out_uint8x8x4_t = vld4_u8 (0); 4413 out_uint8x8x4_t = vld4_u8 (0);
4411 } 4414 }
@@ -4413,10 +4416,10 @@
4413-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4416-/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4414+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4417+/* { dg-final { scan-assembler "vld4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4415 /* { dg-final { cleanup-saved-temps } } */ 4418 /* { dg-final { cleanup-saved-temps } } */
4416 4419Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
4417=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c' 4420===================================================================
4418--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2010-05-24 18:36:31 +0000 4421--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4419+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-05-03 15:14:56 +0000 4422+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c 2011-09-16 20:16:00.507565013 -0700
4420@@ -16,5 +16,5 @@ 4423@@ -16,5 +16,5 @@
4421 vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1); 4424 vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
4422 } 4425 }
@@ -4424,10 +4427,10 @@
4424-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4427-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4425+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4428+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4426 /* { dg-final { cleanup-saved-temps } } */ 4429 /* { dg-final { cleanup-saved-temps } } */
4427 4430Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
4428=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c' 4431===================================================================
4429--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2010-05-24 18:36:31 +0000 4432--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4430+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-05-03 15:14:56 +0000 4433+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c 2011-09-16 20:16:00.507565013 -0700
4431@@ -16,5 +16,5 @@ 4434@@ -16,5 +16,5 @@
4432 vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1); 4435 vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
4433 } 4436 }
@@ -4435,10 +4438,10 @@
4435-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4438-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4436+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4439+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4437 /* { dg-final { cleanup-saved-temps } } */ 4440 /* { dg-final { cleanup-saved-temps } } */
4438 4441Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
4439=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c' 4442===================================================================
4440--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2010-05-24 18:36:31 +0000 4443--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4441+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-05-03 15:14:56 +0000 4444+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c 2011-09-16 20:16:00.507565013 -0700
4442@@ -16,5 +16,5 @@ 4445@@ -16,5 +16,5 @@
4443 vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1); 4446 vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
4444 } 4447 }
@@ -4446,10 +4449,10 @@
4446-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4449-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4447+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4450+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4448 /* { dg-final { cleanup-saved-temps } } */ 4451 /* { dg-final { cleanup-saved-temps } } */
4449 4452Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
4450=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c' 4453===================================================================
4451--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2010-05-24 18:36:31 +0000 4454--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4452+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-05-03 15:14:56 +0000 4455+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c 2011-09-16 20:16:00.507565013 -0700
4453@@ -16,5 +16,5 @@ 4456@@ -16,5 +16,5 @@
4454 vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1); 4457 vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
4455 } 4458 }
@@ -4457,10 +4460,10 @@
4457-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4460-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4458+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4461+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4459 /* { dg-final { cleanup-saved-temps } } */ 4462 /* { dg-final { cleanup-saved-temps } } */
4460 4463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
4461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c' 4464===================================================================
4462--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2010-05-24 18:36:31 +0000 4465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4463+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-05-03 15:14:56 +0000 4466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c 2011-09-16 20:16:00.507565013 -0700
4464@@ -16,5 +16,5 @@ 4467@@ -16,5 +16,5 @@
4465 vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1); 4468 vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
4466 } 4469 }
@@ -4468,10 +4471,10 @@
4468-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4471-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4469+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4472+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4470 /* { dg-final { cleanup-saved-temps } } */ 4473 /* { dg-final { cleanup-saved-temps } } */
4471 4474Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
4472=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c' 4475===================================================================
4473--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2010-05-24 18:36:31 +0000 4476--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-06-24 08:13:40.000000000 -0700
4474+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-05-03 15:14:56 +0000 4477+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c 2011-09-16 20:16:00.507565013 -0700
4475@@ -16,5 +16,5 @@ 4478@@ -16,5 +16,5 @@
4476 vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1); 4479 vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
4477 } 4480 }
@@ -4479,10 +4482,10 @@
4479-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4482-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4480+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4483+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4481 /* { dg-final { cleanup-saved-temps } } */ 4484 /* { dg-final { cleanup-saved-temps } } */
4482 4485Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
4483=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c' 4486===================================================================
4484--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2010-05-24 18:36:31 +0000 4487--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4485+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-05-03 15:14:56 +0000 4488+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c 2011-09-16 20:16:00.507565013 -0700
4486@@ -16,5 +16,5 @@ 4489@@ -16,5 +16,5 @@
4487 vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1); 4490 vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
4488 } 4491 }
@@ -4490,10 +4493,10 @@
4490-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4493-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4491+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4494+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4492 /* { dg-final { cleanup-saved-temps } } */ 4495 /* { dg-final { cleanup-saved-temps } } */
4493 4496Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
4494=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c' 4497===================================================================
4495--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2010-05-24 18:36:31 +0000 4498--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4496+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-05-03 15:14:56 +0000 4499+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c 2011-09-16 20:16:00.507565013 -0700
4497@@ -16,5 +16,5 @@ 4500@@ -16,5 +16,5 @@
4498 vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1); 4501 vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
4499 } 4502 }
@@ -4501,10 +4504,10 @@
4501-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4504-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4502+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4505+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4503 /* { dg-final { cleanup-saved-temps } } */ 4506 /* { dg-final { cleanup-saved-temps } } */
4504 4507Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
4505=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c' 4508===================================================================
4506--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2010-05-24 18:36:31 +0000 4509--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4507+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-05-03 15:14:56 +0000 4510+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c 2011-09-16 20:16:00.507565013 -0700
4508@@ -16,5 +16,5 @@ 4511@@ -16,5 +16,5 @@
4509 vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1); 4512 vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
4510 } 4513 }
@@ -4512,10 +4515,10 @@
4512-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4515-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4513+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4516+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4514 /* { dg-final { cleanup-saved-temps } } */ 4517 /* { dg-final { cleanup-saved-temps } } */
4515 4518Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
4516=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c' 4519===================================================================
4517--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2010-05-24 18:36:31 +0000 4520--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-06-24 08:13:40.000000000 -0700
4518+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-05-03 15:14:56 +0000 4521+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c 2011-09-16 20:16:00.507565013 -0700
4519@@ -16,5 +16,5 @@ 4522@@ -16,5 +16,5 @@
4520 vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1); 4523 vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
4521 } 4524 }
@@ -4523,10 +4526,10 @@
4523-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4526-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4524+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4527+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4525 /* { dg-final { cleanup-saved-temps } } */ 4528 /* { dg-final { cleanup-saved-temps } } */
4526 4529Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
4527=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c' 4530===================================================================
4528--- old/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2010-05-24 18:36:31 +0000 4531--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4529+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-05-03 15:14:56 +0000 4532+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c 2011-09-16 20:16:00.507565013 -0700
4530@@ -16,5 +16,5 @@ 4533@@ -16,5 +16,5 @@
4531 vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1); 4534 vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
4532 } 4535 }
@@ -4534,10 +4537,10 @@
4534-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4537-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4535+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4538+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4536 /* { dg-final { cleanup-saved-temps } } */ 4539 /* { dg-final { cleanup-saved-temps } } */
4537 4540Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
4538=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c' 4541===================================================================
4539--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2010-05-24 18:36:31 +0000 4542--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-06-24 08:13:40.000000000 -0700
4540+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-05-03 15:14:56 +0000 4543+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c 2011-09-16 20:16:00.507565013 -0700
4541@@ -16,5 +16,5 @@ 4544@@ -16,5 +16,5 @@
4542 vst1q_f32 (arg0_float32_t, arg1_float32x4_t); 4545 vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
4543 } 4546 }
@@ -4545,10 +4548,10 @@
4545-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4548-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4546+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4549+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4547 /* { dg-final { cleanup-saved-temps } } */ 4550 /* { dg-final { cleanup-saved-temps } } */
4548 4551Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
4549=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c' 4552===================================================================
4550--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2010-05-24 18:36:31 +0000 4553--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-06-24 08:13:40.000000000 -0700
4551+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-05-03 15:14:56 +0000 4554+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c 2011-09-16 20:16:00.507565013 -0700
4552@@ -16,5 +16,5 @@ 4555@@ -16,5 +16,5 @@
4553 vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t); 4556 vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
4554 } 4557 }
@@ -4556,10 +4559,10 @@
4556-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4559-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4557+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4560+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4558 /* { dg-final { cleanup-saved-temps } } */ 4561 /* { dg-final { cleanup-saved-temps } } */
4559 4562Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
4560=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c' 4563===================================================================
4561--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2010-05-24 18:36:31 +0000 4564--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-06-24 08:13:40.000000000 -0700
4562+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-05-03 15:14:56 +0000 4565+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c 2011-09-16 20:16:00.507565013 -0700
4563@@ -16,5 +16,5 @@ 4566@@ -16,5 +16,5 @@
4564 vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t); 4567 vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
4565 } 4568 }
@@ -4567,10 +4570,10 @@
4567-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4570-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4568+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4571+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4569 /* { dg-final { cleanup-saved-temps } } */ 4572 /* { dg-final { cleanup-saved-temps } } */
4570 4573Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
4571=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c' 4574===================================================================
4572--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2010-05-24 18:36:31 +0000 4575--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-06-24 08:13:40.000000000 -0700
4573+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-05-03 15:14:56 +0000 4576+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c 2011-09-16 20:16:00.507565013 -0700
4574@@ -16,5 +16,5 @@ 4577@@ -16,5 +16,5 @@
4575 vst1q_s16 (arg0_int16_t, arg1_int16x8_t); 4578 vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
4576 } 4579 }
@@ -4578,10 +4581,10 @@
4578-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4581-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4579+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4582+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4580 /* { dg-final { cleanup-saved-temps } } */ 4583 /* { dg-final { cleanup-saved-temps } } */
4581 4584Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
4582=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c' 4585===================================================================
4583--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2010-05-24 18:36:31 +0000 4586--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-06-24 08:13:40.000000000 -0700
4584+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-05-03 15:14:56 +0000 4587+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c 2011-09-16 20:16:00.517565031 -0700
4585@@ -16,5 +16,5 @@ 4588@@ -16,5 +16,5 @@
4586 vst1q_s32 (arg0_int32_t, arg1_int32x4_t); 4589 vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
4587 } 4590 }
@@ -4589,10 +4592,10 @@
4589-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4592-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4590+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4593+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4591 /* { dg-final { cleanup-saved-temps } } */ 4594 /* { dg-final { cleanup-saved-temps } } */
4592 4595Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
4593=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c' 4596===================================================================
4594--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2010-05-24 18:36:31 +0000 4597--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-06-24 08:13:40.000000000 -0700
4595+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-05-03 15:14:56 +0000 4598+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c 2011-09-16 20:16:00.517565031 -0700
4596@@ -16,5 +16,5 @@ 4599@@ -16,5 +16,5 @@
4597 vst1q_s64 (arg0_int64_t, arg1_int64x2_t); 4600 vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
4598 } 4601 }
@@ -4600,10 +4603,10 @@
4600-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4603-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4601+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4604+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4602 /* { dg-final { cleanup-saved-temps } } */ 4605 /* { dg-final { cleanup-saved-temps } } */
4603 4606Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
4604=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c' 4607===================================================================
4605--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2010-05-24 18:36:31 +0000 4608--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-06-24 08:13:40.000000000 -0700
4606+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-05-03 15:14:56 +0000 4609+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c 2011-09-16 20:16:00.517565031 -0700
4607@@ -16,5 +16,5 @@ 4610@@ -16,5 +16,5 @@
4608 vst1q_s8 (arg0_int8_t, arg1_int8x16_t); 4611 vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
4609 } 4612 }
@@ -4611,10 +4614,10 @@
4611-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4614-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4612+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4615+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4613 /* { dg-final { cleanup-saved-temps } } */ 4616 /* { dg-final { cleanup-saved-temps } } */
4614 4617Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
4615=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c' 4618===================================================================
4616--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2010-05-24 18:36:31 +0000 4619--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-06-24 08:13:40.000000000 -0700
4617+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-05-03 15:14:56 +0000 4620+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c 2011-09-16 20:16:00.517565031 -0700
4618@@ -16,5 +16,5 @@ 4621@@ -16,5 +16,5 @@
4619 vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t); 4622 vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
4620 } 4623 }
@@ -4622,10 +4625,10 @@
4622-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4625-/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4623+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4626+/* { dg-final { scan-assembler "vst1\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4624 /* { dg-final { cleanup-saved-temps } } */ 4627 /* { dg-final { cleanup-saved-temps } } */
4625 4628Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
4626=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c' 4629===================================================================
4627--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2010-05-24 18:36:31 +0000 4630--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-06-24 08:13:40.000000000 -0700
4628+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-05-03 15:14:56 +0000 4631+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c 2011-09-16 20:16:00.517565031 -0700
4629@@ -16,5 +16,5 @@ 4632@@ -16,5 +16,5 @@
4630 vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t); 4633 vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
4631 } 4634 }
@@ -4633,10 +4636,10 @@
4633-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4636-/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4634+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4637+/* { dg-final { scan-assembler "vst1\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4635 /* { dg-final { cleanup-saved-temps } } */ 4638 /* { dg-final { cleanup-saved-temps } } */
4636 4639Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
4637=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c' 4640===================================================================
4638--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2010-05-24 18:36:31 +0000 4641--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-06-24 08:13:40.000000000 -0700
4639+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-05-03 15:14:56 +0000 4642+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c 2011-09-16 20:16:00.517565031 -0700
4640@@ -16,5 +16,5 @@ 4643@@ -16,5 +16,5 @@
4641 vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t); 4644 vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
4642 } 4645 }
@@ -4644,10 +4647,10 @@
4644-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4647-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4645+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4648+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4646 /* { dg-final { cleanup-saved-temps } } */ 4649 /* { dg-final { cleanup-saved-temps } } */
4647 4650Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
4648=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c' 4651===================================================================
4649--- old/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2010-05-24 18:36:31 +0000 4652--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-06-24 08:13:40.000000000 -0700
4650+++ new/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-05-03 15:14:56 +0000 4653+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c 2011-09-16 20:16:00.517565031 -0700
4651@@ -16,5 +16,5 @@ 4654@@ -16,5 +16,5 @@
4652 vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t); 4655 vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
4653 } 4656 }
@@ -4655,10 +4658,10 @@
4655-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4658-/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4656+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4659+/* { dg-final { scan-assembler "vst1\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4657 /* { dg-final { cleanup-saved-temps } } */ 4660 /* { dg-final { cleanup-saved-temps } } */
4658 4661Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
4659=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c' 4662===================================================================
4660--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2010-05-24 18:36:31 +0000 4663--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4661+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-05-03 15:14:56 +0000 4664+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c 2011-09-16 20:16:00.517565031 -0700
4662@@ -16,5 +16,5 @@ 4665@@ -16,5 +16,5 @@
4663 vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1); 4666 vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
4664 } 4667 }
@@ -4666,10 +4669,10 @@
4666-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4669-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4667+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4670+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4668 /* { dg-final { cleanup-saved-temps } } */ 4671 /* { dg-final { cleanup-saved-temps } } */
4669 4672Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
4670=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c' 4673===================================================================
4671--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2010-05-24 18:36:31 +0000 4674--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4672+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-05-03 15:14:56 +0000 4675+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c 2011-09-16 20:16:00.517565031 -0700
4673@@ -16,5 +16,5 @@ 4676@@ -16,5 +16,5 @@
4674 vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1); 4677 vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
4675 } 4678 }
@@ -4677,10 +4680,10 @@
4677-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4680-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4678+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4681+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4679 /* { dg-final { cleanup-saved-temps } } */ 4682 /* { dg-final { cleanup-saved-temps } } */
4680 4683Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
4681=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c' 4684===================================================================
4682--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2010-05-24 18:36:31 +0000 4685--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-06-24 08:13:40.000000000 -0700
4683+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-05-03 15:14:56 +0000 4686+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c 2011-09-16 20:16:00.517565031 -0700
4684@@ -16,5 +16,5 @@ 4687@@ -16,5 +16,5 @@
4685 vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1); 4688 vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
4686 } 4689 }
@@ -4688,10 +4691,10 @@
4688-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4691-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4689+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4692+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4690 /* { dg-final { cleanup-saved-temps } } */ 4693 /* { dg-final { cleanup-saved-temps } } */
4691 4694Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
4692=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c' 4695===================================================================
4693--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2010-05-24 18:36:31 +0000 4696--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4694+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-05-03 15:14:56 +0000 4697+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c 2011-09-16 20:16:00.517565031 -0700
4695@@ -16,5 +16,5 @@ 4698@@ -16,5 +16,5 @@
4696 vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1); 4699 vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
4697 } 4700 }
@@ -4699,10 +4702,10 @@
4699-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4702-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4700+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4703+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4701 /* { dg-final { cleanup-saved-temps } } */ 4704 /* { dg-final { cleanup-saved-temps } } */
4702 4705Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
4703=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c' 4706===================================================================
4704--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2010-05-24 18:36:31 +0000 4707--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4705+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-05-03 15:14:56 +0000 4708+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c 2011-09-16 20:16:00.517565031 -0700
4706@@ -16,5 +16,5 @@ 4709@@ -16,5 +16,5 @@
4707 vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1); 4710 vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
4708 } 4711 }
@@ -4710,10 +4713,10 @@
4710-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4713-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4711+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4714+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4712 /* { dg-final { cleanup-saved-temps } } */ 4715 /* { dg-final { cleanup-saved-temps } } */
4713 4716Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
4714=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c' 4717===================================================================
4715--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2010-05-24 18:36:31 +0000 4718--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-06-24 08:13:40.000000000 -0700
4716+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-05-03 15:14:56 +0000 4719+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c 2011-09-16 20:16:00.517565031 -0700
4717@@ -16,5 +16,5 @@ 4720@@ -16,5 +16,5 @@
4718 vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0); 4721 vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
4719 } 4722 }
@@ -4721,10 +4724,10 @@
4721-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4724-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4722+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4725+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4723 /* { dg-final { cleanup-saved-temps } } */ 4726 /* { dg-final { cleanup-saved-temps } } */
4724 4727Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
4725=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c' 4728===================================================================
4726--- old/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2010-05-24 18:36:31 +0000 4729--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-06-24 08:13:40.000000000 -0700
4727+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-05-03 15:14:56 +0000 4730+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c 2011-09-16 20:16:00.517565031 -0700
4728@@ -16,5 +16,5 @@ 4731@@ -16,5 +16,5 @@
4729 vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1); 4732 vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
4730 } 4733 }
@@ -4732,10 +4735,10 @@
4732-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4735-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4733+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4736+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4734 /* { dg-final { cleanup-saved-temps } } */ 4737 /* { dg-final { cleanup-saved-temps } } */
4735 4738Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
4736=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c' 4739===================================================================
4737--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2010-05-24 18:36:31 +0000 4740--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4738+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-05-03 15:14:56 +0000 4741+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c 2011-09-16 20:16:00.517565031 -0700
4739@@ -16,5 +16,5 @@ 4742@@ -16,5 +16,5 @@
4740 vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1); 4743 vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
4741 } 4744 }
@@ -4743,10 +4746,10 @@
4743-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4746-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4744+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4747+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4745 /* { dg-final { cleanup-saved-temps } } */ 4748 /* { dg-final { cleanup-saved-temps } } */
4746 4749Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
4747=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c' 4750===================================================================
4748--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2010-05-24 18:36:31 +0000 4751--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4749+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-05-03 15:14:56 +0000 4752+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c 2011-09-16 20:16:00.517565031 -0700
4750@@ -16,5 +16,5 @@ 4753@@ -16,5 +16,5 @@
4751 vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1); 4754 vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
4752 } 4755 }
@@ -4754,10 +4757,10 @@
4754-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4757-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4755+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4758+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4756 /* { dg-final { cleanup-saved-temps } } */ 4759 /* { dg-final { cleanup-saved-temps } } */
4757 4760Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
4758=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c' 4761===================================================================
4759--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2010-05-24 18:36:31 +0000 4762--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-06-24 08:13:40.000000000 -0700
4760+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-05-03 15:14:56 +0000 4763+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c 2011-09-16 20:16:00.517565031 -0700
4761@@ -16,5 +16,5 @@ 4764@@ -16,5 +16,5 @@
4762 vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0); 4765 vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
4763 } 4766 }
@@ -4765,10 +4768,10 @@
4765-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4768-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4766+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4769+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4767 /* { dg-final { cleanup-saved-temps } } */ 4770 /* { dg-final { cleanup-saved-temps } } */
4768 4771Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
4769=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c' 4772===================================================================
4770--- old/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2010-05-24 18:36:31 +0000 4773--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-06-24 08:13:40.000000000 -0700
4771+++ new/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-05-03 15:14:56 +0000 4774+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c 2011-09-16 20:16:00.517565031 -0700
4772@@ -16,5 +16,5 @@ 4775@@ -16,5 +16,5 @@
4773 vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1); 4776 vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
4774 } 4777 }
@@ -4776,10 +4779,10 @@
4776-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4779-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4777+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4780+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4778 /* { dg-final { cleanup-saved-temps } } */ 4781 /* { dg-final { cleanup-saved-temps } } */
4779 4782Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
4780=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1f32.c' 4783===================================================================
4781--- old/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2010-05-24 18:36:31 +0000 4784--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-06-24 08:13:40.000000000 -0700
4782+++ new/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-05-03 15:14:56 +0000 4785+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1f32.c 2011-09-16 20:16:00.517565031 -0700
4783@@ -16,5 +16,5 @@ 4786@@ -16,5 +16,5 @@
4784 vst1_f32 (arg0_float32_t, arg1_float32x2_t); 4787 vst1_f32 (arg0_float32_t, arg1_float32x2_t);
4785 } 4788 }
@@ -4787,10 +4790,10 @@
4787-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4790-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4788+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4791+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4789 /* { dg-final { cleanup-saved-temps } } */ 4792 /* { dg-final { cleanup-saved-temps } } */
4790 4793Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
4791=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p16.c' 4794===================================================================
4792--- old/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2010-05-24 18:36:31 +0000 4795--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-06-24 08:13:40.000000000 -0700
4793+++ new/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-05-03 15:14:56 +0000 4796+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p16.c 2011-09-16 20:16:00.517565031 -0700
4794@@ -16,5 +16,5 @@ 4797@@ -16,5 +16,5 @@
4795 vst1_p16 (arg0_poly16_t, arg1_poly16x4_t); 4798 vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
4796 } 4799 }
@@ -4798,10 +4801,10 @@
4798-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4801-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4799+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4802+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4800 /* { dg-final { cleanup-saved-temps } } */ 4803 /* { dg-final { cleanup-saved-temps } } */
4801 4804Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
4802=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1p8.c' 4805===================================================================
4803--- old/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2010-05-24 18:36:31 +0000 4806--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-06-24 08:13:40.000000000 -0700
4804+++ new/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-05-03 15:14:56 +0000 4807+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1p8.c 2011-09-16 20:16:00.517565031 -0700
4805@@ -16,5 +16,5 @@ 4808@@ -16,5 +16,5 @@
4806 vst1_p8 (arg0_poly8_t, arg1_poly8x8_t); 4809 vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
4807 } 4810 }
@@ -4809,10 +4812,10 @@
4809-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4812-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4810+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4813+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4811 /* { dg-final { cleanup-saved-temps } } */ 4814 /* { dg-final { cleanup-saved-temps } } */
4812 4815Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
4813=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s16.c' 4816===================================================================
4814--- old/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2010-05-24 18:36:31 +0000 4817--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-06-24 08:13:40.000000000 -0700
4815+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-05-03 15:14:56 +0000 4818+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s16.c 2011-09-16 20:16:00.527565060 -0700
4816@@ -16,5 +16,5 @@ 4819@@ -16,5 +16,5 @@
4817 vst1_s16 (arg0_int16_t, arg1_int16x4_t); 4820 vst1_s16 (arg0_int16_t, arg1_int16x4_t);
4818 } 4821 }
@@ -4820,10 +4823,10 @@
4820-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4823-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4821+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4824+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4822 /* { dg-final { cleanup-saved-temps } } */ 4825 /* { dg-final { cleanup-saved-temps } } */
4823 4826Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
4824=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s32.c' 4827===================================================================
4825--- old/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2010-05-24 18:36:31 +0000 4828--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-06-24 08:13:40.000000000 -0700
4826+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-05-03 15:14:56 +0000 4829+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s32.c 2011-09-16 20:16:00.527565060 -0700
4827@@ -16,5 +16,5 @@ 4830@@ -16,5 +16,5 @@
4828 vst1_s32 (arg0_int32_t, arg1_int32x2_t); 4831 vst1_s32 (arg0_int32_t, arg1_int32x2_t);
4829 } 4832 }
@@ -4831,10 +4834,10 @@
4831-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4834-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4832+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4835+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4833 /* { dg-final { cleanup-saved-temps } } */ 4836 /* { dg-final { cleanup-saved-temps } } */
4834 4837Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
4835=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s64.c' 4838===================================================================
4836--- old/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2010-05-24 18:36:31 +0000 4839--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-06-24 08:13:40.000000000 -0700
4837+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-05-03 15:14:56 +0000 4840+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s64.c 2011-09-16 20:16:00.527565060 -0700
4838@@ -16,5 +16,5 @@ 4841@@ -16,5 +16,5 @@
4839 vst1_s64 (arg0_int64_t, arg1_int64x1_t); 4842 vst1_s64 (arg0_int64_t, arg1_int64x1_t);
4840 } 4843 }
@@ -4842,10 +4845,10 @@
4842-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4845-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4843+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4846+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4844 /* { dg-final { cleanup-saved-temps } } */ 4847 /* { dg-final { cleanup-saved-temps } } */
4845 4848Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
4846=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1s8.c' 4849===================================================================
4847--- old/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2010-05-24 18:36:31 +0000 4850--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-06-24 08:13:40.000000000 -0700
4848+++ new/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-05-03 15:14:56 +0000 4851+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1s8.c 2011-09-16 20:16:00.527565060 -0700
4849@@ -16,5 +16,5 @@ 4852@@ -16,5 +16,5 @@
4850 vst1_s8 (arg0_int8_t, arg1_int8x8_t); 4853 vst1_s8 (arg0_int8_t, arg1_int8x8_t);
4851 } 4854 }
@@ -4853,10 +4856,10 @@
4853-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4856-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4854+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4857+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4855 /* { dg-final { cleanup-saved-temps } } */ 4858 /* { dg-final { cleanup-saved-temps } } */
4856 4859Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
4857=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u16.c' 4860===================================================================
4858--- old/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2010-05-24 18:36:31 +0000 4861--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-06-24 08:13:40.000000000 -0700
4859+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-05-03 15:14:56 +0000 4862+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u16.c 2011-09-16 20:16:00.527565060 -0700
4860@@ -16,5 +16,5 @@ 4863@@ -16,5 +16,5 @@
4861 vst1_u16 (arg0_uint16_t, arg1_uint16x4_t); 4864 vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
4862 } 4865 }
@@ -4864,10 +4867,10 @@
4864-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4867-/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4865+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4868+/* { dg-final { scan-assembler "vst1\.16\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4866 /* { dg-final { cleanup-saved-temps } } */ 4869 /* { dg-final { cleanup-saved-temps } } */
4867 4870Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
4868=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u32.c' 4871===================================================================
4869--- old/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2010-05-24 18:36:31 +0000 4872--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-06-24 08:13:40.000000000 -0700
4870+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-05-03 15:14:56 +0000 4873+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u32.c 2011-09-16 20:16:00.527565060 -0700
4871@@ -16,5 +16,5 @@ 4874@@ -16,5 +16,5 @@
4872 vst1_u32 (arg0_uint32_t, arg1_uint32x2_t); 4875 vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
4873 } 4876 }
@@ -4875,10 +4878,10 @@
4875-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4878-/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4876+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4879+/* { dg-final { scan-assembler "vst1\.32\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4877 /* { dg-final { cleanup-saved-temps } } */ 4880 /* { dg-final { cleanup-saved-temps } } */
4878 4881Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
4879=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u64.c' 4882===================================================================
4880--- old/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2010-05-24 18:36:31 +0000 4883--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-06-24 08:13:40.000000000 -0700
4881+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-05-03 15:14:56 +0000 4884+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u64.c 2011-09-16 20:16:00.527565060 -0700
4882@@ -16,5 +16,5 @@ 4885@@ -16,5 +16,5 @@
4883 vst1_u64 (arg0_uint64_t, arg1_uint64x1_t); 4886 vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
4884 } 4887 }
@@ -4886,10 +4889,10 @@
4886-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4889-/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4887+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4890+/* { dg-final { scan-assembler "vst1\.64\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4888 /* { dg-final { cleanup-saved-temps } } */ 4891 /* { dg-final { cleanup-saved-temps } } */
4889 4892Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
4890=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst1u8.c' 4893===================================================================
4891--- old/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2010-05-24 18:36:31 +0000 4894--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-06-24 08:13:40.000000000 -0700
4892+++ new/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-05-03 15:14:56 +0000 4895+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst1u8.c 2011-09-16 20:16:00.527565060 -0700
4893@@ -16,5 +16,5 @@ 4896@@ -16,5 +16,5 @@
4894 vst1_u8 (arg0_uint8_t, arg1_uint8x8_t); 4897 vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
4895 } 4898 }
@@ -4897,10 +4900,10 @@
4897-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4900-/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4898+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4901+/* { dg-final { scan-assembler "vst1\.8\[ \]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4899 /* { dg-final { cleanup-saved-temps } } */ 4902 /* { dg-final { cleanup-saved-temps } } */
4900 4903Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
4901=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c' 4904===================================================================
4902--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2010-05-24 18:36:31 +0000 4905--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
4903+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-05-03 15:14:56 +0000 4906+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c 2011-09-16 20:16:00.527565060 -0700
4904@@ -16,5 +16,5 @@ 4907@@ -16,5 +16,5 @@
4905 vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1); 4908 vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
4906 } 4909 }
@@ -4908,10 +4911,10 @@
4908-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4911-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4909+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4912+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4910 /* { dg-final { cleanup-saved-temps } } */ 4913 /* { dg-final { cleanup-saved-temps } } */
4911 4914Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
4912=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c' 4915===================================================================
4913--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2010-05-24 18:36:31 +0000 4916--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
4914+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-05-03 15:14:56 +0000 4917+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c 2011-09-16 20:16:00.527565060 -0700
4915@@ -16,5 +16,5 @@ 4918@@ -16,5 +16,5 @@
4916 vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1); 4919 vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
4917 } 4920 }
@@ -4919,10 +4922,10 @@
4919-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4922-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4920+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4923+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4921 /* { dg-final { cleanup-saved-temps } } */ 4924 /* { dg-final { cleanup-saved-temps } } */
4922 4925Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
4923=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c' 4926===================================================================
4924--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2010-05-24 18:36:31 +0000 4927--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
4925+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-05-03 15:14:56 +0000 4928+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c 2011-09-16 20:16:00.527565060 -0700
4926@@ -16,5 +16,5 @@ 4929@@ -16,5 +16,5 @@
4927 vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1); 4930 vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
4928 } 4931 }
@@ -4930,10 +4933,10 @@
4930-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4933-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4931+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4934+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4932 /* { dg-final { cleanup-saved-temps } } */ 4935 /* { dg-final { cleanup-saved-temps } } */
4933 4936Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
4934=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c' 4937===================================================================
4935--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2010-05-24 18:36:31 +0000 4938--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
4936+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-05-03 15:14:56 +0000 4939+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c 2011-09-16 20:16:00.527565060 -0700
4937@@ -16,5 +16,5 @@ 4940@@ -16,5 +16,5 @@
4938 vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1); 4941 vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
4939 } 4942 }
@@ -4941,10 +4944,10 @@
4941-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4944-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4942+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4945+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4943 /* { dg-final { cleanup-saved-temps } } */ 4946 /* { dg-final { cleanup-saved-temps } } */
4944 4947Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
4945=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c' 4948===================================================================
4946--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2010-05-24 18:36:31 +0000 4949--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
4947+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-05-03 15:14:56 +0000 4950+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c 2011-09-16 20:16:00.527565060 -0700
4948@@ -16,5 +16,5 @@ 4951@@ -16,5 +16,5 @@
4949 vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1); 4952 vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
4950 } 4953 }
@@ -4952,10 +4955,10 @@
4952-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4955-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4953+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4956+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4954 /* { dg-final { cleanup-saved-temps } } */ 4957 /* { dg-final { cleanup-saved-temps } } */
4955 4958Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
4956=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c' 4959===================================================================
4957--- old/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2010-05-24 18:36:31 +0000 4960--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
4958+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-05-03 15:14:56 +0000 4961+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c 2011-09-16 20:16:00.527565060 -0700
4959@@ -16,5 +16,5 @@ 4962@@ -16,5 +16,5 @@
4960 vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1); 4963 vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
4961 } 4964 }
@@ -4963,10 +4966,10 @@
4963-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4966-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4964+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4967+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4965 /* { dg-final { cleanup-saved-temps } } */ 4968 /* { dg-final { cleanup-saved-temps } } */
4966 4969Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
4967=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c' 4970===================================================================
4968--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2010-05-24 18:36:31 +0000 4971--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-06-24 08:13:40.000000000 -0700
4969+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-05-03 15:14:56 +0000 4972+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c 2011-09-16 20:16:00.527565060 -0700
4970@@ -16,6 +16,6 @@ 4973@@ -16,6 +16,6 @@
4971 vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t); 4974 vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
4972 } 4975 }
@@ -4976,10 +4979,10 @@
4976+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4979+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4977+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4980+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4978 /* { dg-final { cleanup-saved-temps } } */ 4981 /* { dg-final { cleanup-saved-temps } } */
4979 4982Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
4980=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c' 4983===================================================================
4981--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2010-05-24 18:36:31 +0000 4984--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-06-24 08:13:40.000000000 -0700
4982+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-05-03 15:14:56 +0000 4985+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c 2011-09-16 20:16:00.527565060 -0700
4983@@ -16,6 +16,6 @@ 4986@@ -16,6 +16,6 @@
4984 vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t); 4987 vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
4985 } 4988 }
@@ -4989,10 +4992,10 @@
4989+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4992+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4990+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 4993+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
4991 /* { dg-final { cleanup-saved-temps } } */ 4994 /* { dg-final { cleanup-saved-temps } } */
4992 4995Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
4993=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c' 4996===================================================================
4994--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2010-05-24 18:36:31 +0000 4997--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-06-24 08:13:40.000000000 -0700
4995+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-05-03 15:14:56 +0000 4998+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c 2011-09-16 20:16:00.527565060 -0700
4996@@ -16,6 +16,6 @@ 4999@@ -16,6 +16,6 @@
4997 vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t); 5000 vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
4998 } 5001 }
@@ -5002,10 +5005,10 @@
5002+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5005+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5003+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5006+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5004 /* { dg-final { cleanup-saved-temps } } */ 5007 /* { dg-final { cleanup-saved-temps } } */
5005 5008Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
5006=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c' 5009===================================================================
5007--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2010-05-24 18:36:31 +0000 5010--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-06-24 08:13:40.000000000 -0700
5008+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-05-03 15:14:56 +0000 5011+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c 2011-09-16 20:16:00.527565060 -0700
5009@@ -16,6 +16,6 @@ 5012@@ -16,6 +16,6 @@
5010 vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t); 5013 vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
5011 } 5014 }
@@ -5015,10 +5018,10 @@
5015+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5018+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5016+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5019+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5017 /* { dg-final { cleanup-saved-temps } } */ 5020 /* { dg-final { cleanup-saved-temps } } */
5018 5021Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
5019=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c' 5022===================================================================
5020--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2010-05-24 18:36:31 +0000 5023--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-06-24 08:13:40.000000000 -0700
5021+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-05-03 15:14:56 +0000 5024+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c 2011-09-16 20:16:00.527565060 -0700
5022@@ -16,6 +16,6 @@ 5025@@ -16,6 +16,6 @@
5023 vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t); 5026 vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
5024 } 5027 }
@@ -5028,10 +5031,10 @@
5028+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5031+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5029+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5032+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5030 /* { dg-final { cleanup-saved-temps } } */ 5033 /* { dg-final { cleanup-saved-temps } } */
5031 5034Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
5032=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c' 5035===================================================================
5033--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2010-05-24 18:36:31 +0000 5036--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-06-24 08:13:40.000000000 -0700
5034+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-05-03 15:14:56 +0000 5037+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c 2011-09-16 20:16:00.527565060 -0700
5035@@ -16,6 +16,6 @@ 5038@@ -16,6 +16,6 @@
5036 vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t); 5039 vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
5037 } 5040 }
@@ -5041,10 +5044,10 @@
5041+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5044+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5042+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5045+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5043 /* { dg-final { cleanup-saved-temps } } */ 5046 /* { dg-final { cleanup-saved-temps } } */
5044 5047Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
5045=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c' 5048===================================================================
5046--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2010-05-24 18:36:31 +0000 5049--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-06-24 08:13:40.000000000 -0700
5047+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-05-03 15:14:56 +0000 5050+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c 2011-09-16 20:16:00.527565060 -0700
5048@@ -16,6 +16,6 @@ 5051@@ -16,6 +16,6 @@
5049 vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t); 5052 vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
5050 } 5053 }
@@ -5054,10 +5057,10 @@
5054+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5057+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5055+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5058+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5056 /* { dg-final { cleanup-saved-temps } } */ 5059 /* { dg-final { cleanup-saved-temps } } */
5057 5060Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
5058=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c' 5061===================================================================
5059--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2010-05-24 18:36:31 +0000 5062--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-06-24 08:13:40.000000000 -0700
5060+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-05-03 15:14:56 +0000 5063+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c 2011-09-16 20:16:00.527565060 -0700
5061@@ -16,6 +16,6 @@ 5064@@ -16,6 +16,6 @@
5062 vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t); 5065 vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
5063 } 5066 }
@@ -5067,10 +5070,10 @@
5067+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5070+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5068+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5071+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5069 /* { dg-final { cleanup-saved-temps } } */ 5072 /* { dg-final { cleanup-saved-temps } } */
5070 5073Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
5071=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c' 5074===================================================================
5072--- old/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2010-05-24 18:36:31 +0000 5075--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-06-24 08:13:40.000000000 -0700
5073+++ new/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-05-03 15:14:56 +0000 5076+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c 2011-09-16 20:16:00.537565077 -0700
5074@@ -16,6 +16,6 @@ 5077@@ -16,6 +16,6 @@
5075 vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t); 5078 vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
5076 } 5079 }
@@ -5080,10 +5083,10 @@
5080+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5083+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5081+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5084+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5082 /* { dg-final { cleanup-saved-temps } } */ 5085 /* { dg-final { cleanup-saved-temps } } */
5083 5086Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
5084=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c' 5087===================================================================
5085--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2010-05-24 18:36:31 +0000 5088--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5086+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-05-03 15:14:56 +0000 5089+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c 2011-09-16 20:16:00.537565077 -0700
5087@@ -16,5 +16,5 @@ 5090@@ -16,5 +16,5 @@
5088 vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1); 5091 vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
5089 } 5092 }
@@ -5091,10 +5094,10 @@
5091-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5094-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5092+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5095+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5093 /* { dg-final { cleanup-saved-temps } } */ 5096 /* { dg-final { cleanup-saved-temps } } */
5094 5097Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
5095=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c' 5098===================================================================
5096--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2010-05-24 18:36:31 +0000 5099--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5097+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-05-03 15:14:56 +0000 5100+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c 2011-09-16 20:16:00.537565077 -0700
5098@@ -16,5 +16,5 @@ 5101@@ -16,5 +16,5 @@
5099 vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1); 5102 vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
5100 } 5103 }
@@ -5102,10 +5105,10 @@
5102-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5105-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5103+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5106+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5104 /* { dg-final { cleanup-saved-temps } } */ 5107 /* { dg-final { cleanup-saved-temps } } */
5105 5108Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
5106=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c' 5109===================================================================
5107--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2010-05-24 18:36:31 +0000 5110--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5108+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-05-03 15:14:56 +0000 5111+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c 2011-09-16 20:16:00.537565077 -0700
5109@@ -16,5 +16,5 @@ 5112@@ -16,5 +16,5 @@
5110 vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1); 5113 vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
5111 } 5114 }
@@ -5113,10 +5116,10 @@
5113-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5116-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5114+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5117+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5115 /* { dg-final { cleanup-saved-temps } } */ 5118 /* { dg-final { cleanup-saved-temps } } */
5116 5119Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
5117=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c' 5120===================================================================
5118--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2010-05-24 18:36:31 +0000 5121--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5119+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-05-03 15:14:56 +0000 5122+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c 2011-09-16 20:16:00.537565077 -0700
5120@@ -16,5 +16,5 @@ 5123@@ -16,5 +16,5 @@
5121 vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1); 5124 vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
5122 } 5125 }
@@ -5124,10 +5127,10 @@
5124-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5127-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5125+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5128+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5126 /* { dg-final { cleanup-saved-temps } } */ 5129 /* { dg-final { cleanup-saved-temps } } */
5127 5130Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
5128=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c' 5131===================================================================
5129--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2010-05-24 18:36:31 +0000 5132--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5130+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-05-03 15:14:56 +0000 5133+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c 2011-09-16 20:16:00.537565077 -0700
5131@@ -16,5 +16,5 @@ 5134@@ -16,5 +16,5 @@
5132 vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1); 5135 vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
5133 } 5136 }
@@ -5135,10 +5138,10 @@
5135-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5138-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5136+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5139+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5137 /* { dg-final { cleanup-saved-temps } } */ 5140 /* { dg-final { cleanup-saved-temps } } */
5138 5141Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
5139=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c' 5142===================================================================
5140--- old/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2010-05-24 18:36:31 +0000 5143--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5141+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-05-03 15:14:56 +0000 5144+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c 2011-09-16 20:16:00.537565077 -0700
5142@@ -16,5 +16,5 @@ 5145@@ -16,5 +16,5 @@
5143 vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1); 5146 vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
5144 } 5147 }
@@ -5146,10 +5149,10 @@
5146-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5149-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5147+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5150+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5148 /* { dg-final { cleanup-saved-temps } } */ 5151 /* { dg-final { cleanup-saved-temps } } */
5149 5152Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
5150=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c' 5153===================================================================
5151--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2010-05-24 18:36:31 +0000 5154--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5152+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-05-03 15:14:56 +0000 5155+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c 2011-09-16 20:16:00.537565077 -0700
5153@@ -16,5 +16,5 @@ 5156@@ -16,5 +16,5 @@
5154 vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1); 5157 vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
5155 } 5158 }
@@ -5157,10 +5160,10 @@
5157-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5160-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5158+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5161+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5159 /* { dg-final { cleanup-saved-temps } } */ 5162 /* { dg-final { cleanup-saved-temps } } */
5160 5163Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
5161=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c' 5164===================================================================
5162--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2010-05-24 18:36:31 +0000 5165--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5163+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-05-03 15:14:56 +0000 5166+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c 2011-09-16 20:16:00.537565077 -0700
5164@@ -16,5 +16,5 @@ 5167@@ -16,5 +16,5 @@
5165 vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1); 5168 vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
5166 } 5169 }
@@ -5168,10 +5171,10 @@
5168-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5171-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5169+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5172+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5170 /* { dg-final { cleanup-saved-temps } } */ 5173 /* { dg-final { cleanup-saved-temps } } */
5171 5174Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
5172=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c' 5175===================================================================
5173--- old/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2010-05-24 18:36:31 +0000 5176--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5174+++ new/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-05-03 15:14:56 +0000 5177+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c 2011-09-16 20:16:00.537565077 -0700
5175@@ -16,5 +16,5 @@ 5178@@ -16,5 +16,5 @@
5176 vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1); 5179 vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
5177 } 5180 }
@@ -5179,10 +5182,10 @@
5179-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5182-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5180+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5183+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5181 /* { dg-final { cleanup-saved-temps } } */ 5184 /* { dg-final { cleanup-saved-temps } } */
5182 5185Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
5183=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2f32.c' 5186===================================================================
5184--- old/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2010-05-24 18:36:31 +0000 5187--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-06-24 08:13:40.000000000 -0700
5185+++ new/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-05-03 15:14:56 +0000 5188+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2f32.c 2011-09-16 20:16:00.537565077 -0700
5186@@ -16,5 +16,5 @@ 5189@@ -16,5 +16,5 @@
5187 vst2_f32 (arg0_float32_t, arg1_float32x2x2_t); 5190 vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
5188 } 5191 }
@@ -5190,10 +5193,10 @@
5190-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5193-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5191+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5194+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5192 /* { dg-final { cleanup-saved-temps } } */ 5195 /* { dg-final { cleanup-saved-temps } } */
5193 5196Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
5194=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p16.c' 5197===================================================================
5195--- old/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2010-05-24 18:36:31 +0000 5198--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-06-24 08:13:40.000000000 -0700
5196+++ new/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-05-03 15:14:56 +0000 5199+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p16.c 2011-09-16 20:16:00.537565077 -0700
5197@@ -16,5 +16,5 @@ 5200@@ -16,5 +16,5 @@
5198 vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t); 5201 vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
5199 } 5202 }
@@ -5201,10 +5204,10 @@
5201-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5204-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5202+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5205+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5203 /* { dg-final { cleanup-saved-temps } } */ 5206 /* { dg-final { cleanup-saved-temps } } */
5204 5207Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
5205=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2p8.c' 5208===================================================================
5206--- old/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2010-05-24 18:36:31 +0000 5209--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-06-24 08:13:40.000000000 -0700
5207+++ new/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-05-03 15:14:56 +0000 5210+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2p8.c 2011-09-16 20:16:00.547565082 -0700
5208@@ -16,5 +16,5 @@ 5211@@ -16,5 +16,5 @@
5209 vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t); 5212 vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
5210 } 5213 }
@@ -5212,10 +5215,10 @@
5212-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5215-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5213+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5216+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5214 /* { dg-final { cleanup-saved-temps } } */ 5217 /* { dg-final { cleanup-saved-temps } } */
5215 5218Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
5216=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s16.c' 5219===================================================================
5217--- old/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2010-05-24 18:36:31 +0000 5220--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-06-24 08:13:40.000000000 -0700
5218+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-05-03 15:14:56 +0000 5221+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s16.c 2011-09-16 20:16:00.547565082 -0700
5219@@ -16,5 +16,5 @@ 5222@@ -16,5 +16,5 @@
5220 vst2_s16 (arg0_int16_t, arg1_int16x4x2_t); 5223 vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
5221 } 5224 }
@@ -5223,10 +5226,10 @@
5223-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5226-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5224+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5227+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5225 /* { dg-final { cleanup-saved-temps } } */ 5228 /* { dg-final { cleanup-saved-temps } } */
5226 5229Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
5227=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s32.c' 5230===================================================================
5228--- old/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2010-05-24 18:36:31 +0000 5231--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-06-24 08:13:40.000000000 -0700
5229+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-05-03 15:14:56 +0000 5232+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s32.c 2011-09-16 20:16:00.547565082 -0700
5230@@ -16,5 +16,5 @@ 5233@@ -16,5 +16,5 @@
5231 vst2_s32 (arg0_int32_t, arg1_int32x2x2_t); 5234 vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
5232 } 5235 }
@@ -5234,10 +5237,10 @@
5234-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5237-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5235+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5238+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5236 /* { dg-final { cleanup-saved-temps } } */ 5239 /* { dg-final { cleanup-saved-temps } } */
5237 5240Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
5238=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s64.c' 5241===================================================================
5239--- old/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2010-05-24 18:36:31 +0000 5242--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-06-24 08:13:40.000000000 -0700
5240+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-05-03 15:14:56 +0000 5243+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s64.c 2011-09-16 20:16:00.547565082 -0700
5241@@ -16,5 +16,5 @@ 5244@@ -16,5 +16,5 @@
5242 vst2_s64 (arg0_int64_t, arg1_int64x1x2_t); 5245 vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
5243 } 5246 }
@@ -5245,10 +5248,10 @@
5245-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5248-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5246+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5249+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5247 /* { dg-final { cleanup-saved-temps } } */ 5250 /* { dg-final { cleanup-saved-temps } } */
5248 5251Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
5249=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2s8.c' 5252===================================================================
5250--- old/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2010-05-24 18:36:31 +0000 5253--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-06-24 08:13:40.000000000 -0700
5251+++ new/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-05-03 15:14:56 +0000 5254+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2s8.c 2011-09-16 20:16:00.547565082 -0700
5252@@ -16,5 +16,5 @@ 5255@@ -16,5 +16,5 @@
5253 vst2_s8 (arg0_int8_t, arg1_int8x8x2_t); 5256 vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
5254 } 5257 }
@@ -5256,10 +5259,10 @@
5256-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5259-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5257+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5260+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5258 /* { dg-final { cleanup-saved-temps } } */ 5261 /* { dg-final { cleanup-saved-temps } } */
5259 5262Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
5260=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u16.c' 5263===================================================================
5261--- old/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2010-05-24 18:36:31 +0000 5264--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-06-24 08:13:40.000000000 -0700
5262+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-05-03 15:14:56 +0000 5265+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u16.c 2011-09-16 20:16:00.547565082 -0700
5263@@ -16,5 +16,5 @@ 5266@@ -16,5 +16,5 @@
5264 vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t); 5267 vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
5265 } 5268 }
@@ -5267,10 +5270,10 @@
5267-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5270-/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5268+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5271+/* { dg-final { scan-assembler "vst2\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5269 /* { dg-final { cleanup-saved-temps } } */ 5272 /* { dg-final { cleanup-saved-temps } } */
5270 5273Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
5271=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u32.c' 5274===================================================================
5272--- old/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2010-05-24 18:36:31 +0000 5275--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-06-24 08:13:40.000000000 -0700
5273+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-05-03 15:14:56 +0000 5276+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u32.c 2011-09-16 20:16:00.547565082 -0700
5274@@ -16,5 +16,5 @@ 5277@@ -16,5 +16,5 @@
5275 vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t); 5278 vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
5276 } 5279 }
@@ -5278,10 +5281,10 @@
5278-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5281-/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5279+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5282+/* { dg-final { scan-assembler "vst2\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5280 /* { dg-final { cleanup-saved-temps } } */ 5283 /* { dg-final { cleanup-saved-temps } } */
5281 5284Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
5282=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u64.c' 5285===================================================================
5283--- old/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2010-05-24 18:36:31 +0000 5286--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-06-24 08:13:40.000000000 -0700
5284+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-05-03 15:14:56 +0000 5287+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u64.c 2011-09-16 20:16:00.557565092 -0700
5285@@ -16,5 +16,5 @@ 5288@@ -16,5 +16,5 @@
5286 vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t); 5289 vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
5287 } 5290 }
@@ -5289,10 +5292,10 @@
5289-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5292-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5290+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5293+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5291 /* { dg-final { cleanup-saved-temps } } */ 5294 /* { dg-final { cleanup-saved-temps } } */
5292 5295Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
5293=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst2u8.c' 5296===================================================================
5294--- old/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2010-05-24 18:36:31 +0000 5297--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-06-24 08:13:40.000000000 -0700
5295+++ new/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-05-03 15:14:56 +0000 5298+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst2u8.c 2011-09-16 20:16:00.557565092 -0700
5296@@ -16,5 +16,5 @@ 5299@@ -16,5 +16,5 @@
5297 vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t); 5300 vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
5298 } 5301 }
@@ -5300,10 +5303,10 @@
5300-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5303-/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5301+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5304+/* { dg-final { scan-assembler "vst2\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5302 /* { dg-final { cleanup-saved-temps } } */ 5305 /* { dg-final { cleanup-saved-temps } } */
5303 5306Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
5304=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c' 5307===================================================================
5305--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2010-05-24 18:36:31 +0000 5308--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5306+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-05-03 15:14:56 +0000 5309+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c 2011-09-16 20:16:00.557565092 -0700
5307@@ -16,5 +16,5 @@ 5310@@ -16,5 +16,5 @@
5308 vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1); 5311 vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
5309 } 5312 }
@@ -5311,10 +5314,10 @@
5311-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5314-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5312+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5315+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5313 /* { dg-final { cleanup-saved-temps } } */ 5316 /* { dg-final { cleanup-saved-temps } } */
5314 5317Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
5315=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c' 5318===================================================================
5316--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2010-05-24 18:36:31 +0000 5319--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5317+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-05-03 15:14:56 +0000 5320+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c 2011-09-16 20:16:00.557565092 -0700
5318@@ -16,5 +16,5 @@ 5321@@ -16,5 +16,5 @@
5319 vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1); 5322 vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
5320 } 5323 }
@@ -5322,10 +5325,10 @@
5322-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5325-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5323+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5326+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5324 /* { dg-final { cleanup-saved-temps } } */ 5327 /* { dg-final { cleanup-saved-temps } } */
5325 5328Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
5326=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c' 5329===================================================================
5327--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2010-05-24 18:36:31 +0000 5330--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5328+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-05-03 15:14:56 +0000 5331+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c 2011-09-16 20:16:00.557565092 -0700
5329@@ -16,5 +16,5 @@ 5332@@ -16,5 +16,5 @@
5330 vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1); 5333 vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
5331 } 5334 }
@@ -5333,10 +5336,10 @@
5333-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5336-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5334+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5337+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5335 /* { dg-final { cleanup-saved-temps } } */ 5338 /* { dg-final { cleanup-saved-temps } } */
5336 5339Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
5337=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c' 5340===================================================================
5338--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2010-05-24 18:36:31 +0000 5341--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5339+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-05-03 15:14:56 +0000 5342+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c 2011-09-16 20:16:00.557565092 -0700
5340@@ -16,5 +16,5 @@ 5343@@ -16,5 +16,5 @@
5341 vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1); 5344 vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
5342 } 5345 }
@@ -5344,10 +5347,10 @@
5344-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5347-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5345+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5348+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5346 /* { dg-final { cleanup-saved-temps } } */ 5349 /* { dg-final { cleanup-saved-temps } } */
5347 5350Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
5348=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c' 5351===================================================================
5349--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2010-05-24 18:36:31 +0000 5352--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5350+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-05-03 15:14:56 +0000 5353+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c 2011-09-16 20:16:00.557565092 -0700
5351@@ -16,5 +16,5 @@ 5354@@ -16,5 +16,5 @@
5352 vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1); 5355 vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
5353 } 5356 }
@@ -5355,10 +5358,10 @@
5355-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5358-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5356+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5359+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5357 /* { dg-final { cleanup-saved-temps } } */ 5360 /* { dg-final { cleanup-saved-temps } } */
5358 5361Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
5359=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c' 5362===================================================================
5360--- old/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2010-05-24 18:36:31 +0000 5363--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5361+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-05-03 15:14:56 +0000 5364+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c 2011-09-16 20:16:00.557565092 -0700
5362@@ -16,5 +16,5 @@ 5365@@ -16,5 +16,5 @@
5363 vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1); 5366 vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
5364 } 5367 }
@@ -5366,10 +5369,10 @@
5366-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5369-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5367+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5370+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5368 /* { dg-final { cleanup-saved-temps } } */ 5371 /* { dg-final { cleanup-saved-temps } } */
5369 5372Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
5370=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c' 5373===================================================================
5371--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2010-05-24 18:36:31 +0000 5374--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-06-24 08:13:40.000000000 -0700
5372+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-05-03 15:14:56 +0000 5375+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c 2011-09-16 20:16:00.557565092 -0700
5373@@ -16,6 +16,6 @@ 5376@@ -16,6 +16,6 @@
5374 vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t); 5377 vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
5375 } 5378 }
@@ -5379,10 +5382,10 @@
5379+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5382+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5380+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5383+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5381 /* { dg-final { cleanup-saved-temps } } */ 5384 /* { dg-final { cleanup-saved-temps } } */
5382 5385Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
5383=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c' 5386===================================================================
5384--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2010-05-24 18:36:31 +0000 5387--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-06-24 08:13:40.000000000 -0700
5385+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-05-03 15:14:56 +0000 5388+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c 2011-09-16 20:16:00.567565108 -0700
5386@@ -16,6 +16,6 @@ 5389@@ -16,6 +16,6 @@
5387 vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t); 5390 vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
5388 } 5391 }
@@ -5392,10 +5395,10 @@
5392+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5395+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5393+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5396+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5394 /* { dg-final { cleanup-saved-temps } } */ 5397 /* { dg-final { cleanup-saved-temps } } */
5395 5398Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
5396=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c' 5399===================================================================
5397--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2010-05-24 18:36:31 +0000 5400--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-06-24 08:13:40.000000000 -0700
5398+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-05-03 15:14:56 +0000 5401+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c 2011-09-16 20:16:00.567565108 -0700
5399@@ -16,6 +16,6 @@ 5402@@ -16,6 +16,6 @@
5400 vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t); 5403 vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
5401 } 5404 }
@@ -5405,10 +5408,10 @@
5405+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5408+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5406+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5409+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5407 /* { dg-final { cleanup-saved-temps } } */ 5410 /* { dg-final { cleanup-saved-temps } } */
5408 5411Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
5409=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c' 5412===================================================================
5410--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2010-05-24 18:36:31 +0000 5413--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-06-24 08:13:40.000000000 -0700
5411+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-05-03 15:14:56 +0000 5414+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c 2011-09-16 20:16:00.567565108 -0700
5412@@ -16,6 +16,6 @@ 5415@@ -16,6 +16,6 @@
5413 vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t); 5416 vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
5414 } 5417 }
@@ -5418,10 +5421,10 @@
5418+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5421+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5419+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5422+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5420 /* { dg-final { cleanup-saved-temps } } */ 5423 /* { dg-final { cleanup-saved-temps } } */
5421 5424Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
5422=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c' 5425===================================================================
5423--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2010-05-24 18:36:31 +0000 5426--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-06-24 08:13:40.000000000 -0700
5424+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-05-03 15:14:56 +0000 5427+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c 2011-09-16 20:16:00.567565108 -0700
5425@@ -16,6 +16,6 @@ 5428@@ -16,6 +16,6 @@
5426 vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t); 5429 vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
5427 } 5430 }
@@ -5431,10 +5434,10 @@
5431+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5434+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5432+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5435+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5433 /* { dg-final { cleanup-saved-temps } } */ 5436 /* { dg-final { cleanup-saved-temps } } */
5434 5437Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
5435=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c' 5438===================================================================
5436--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2010-05-24 18:36:31 +0000 5439--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-06-24 08:13:40.000000000 -0700
5437+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-05-03 15:14:56 +0000 5440+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c 2011-09-16 20:16:00.567565108 -0700
5438@@ -16,6 +16,6 @@ 5441@@ -16,6 +16,6 @@
5439 vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t); 5442 vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
5440 } 5443 }
@@ -5444,10 +5447,10 @@
5444+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5447+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5445+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5448+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5446 /* { dg-final { cleanup-saved-temps } } */ 5449 /* { dg-final { cleanup-saved-temps } } */
5447 5450Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
5448=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c' 5451===================================================================
5449--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2010-05-24 18:36:31 +0000 5452--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-06-24 08:13:40.000000000 -0700
5450+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-05-03 15:14:56 +0000 5453+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c 2011-09-16 20:16:00.567565108 -0700
5451@@ -16,6 +16,6 @@ 5454@@ -16,6 +16,6 @@
5452 vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t); 5455 vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
5453 } 5456 }
@@ -5457,10 +5460,10 @@
5457+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5460+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5458+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5461+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5459 /* { dg-final { cleanup-saved-temps } } */ 5462 /* { dg-final { cleanup-saved-temps } } */
5460 5463Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
5461=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c' 5464===================================================================
5462--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2010-05-24 18:36:31 +0000 5465--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-06-24 08:13:40.000000000 -0700
5463+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-05-03 15:14:56 +0000 5466+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c 2011-09-16 20:16:00.567565108 -0700
5464@@ -16,6 +16,6 @@ 5467@@ -16,6 +16,6 @@
5465 vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t); 5468 vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
5466 } 5469 }
@@ -5470,10 +5473,10 @@
5470+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5473+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5471+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5474+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5472 /* { dg-final { cleanup-saved-temps } } */ 5475 /* { dg-final { cleanup-saved-temps } } */
5473 5476Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
5474=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c' 5477===================================================================
5475--- old/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2010-05-24 18:36:31 +0000 5478--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-06-24 08:13:40.000000000 -0700
5476+++ new/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-05-03 15:14:56 +0000 5479+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c 2011-09-16 20:16:00.567565108 -0700
5477@@ -16,6 +16,6 @@ 5480@@ -16,6 +16,6 @@
5478 vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t); 5481 vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
5479 } 5482 }
@@ -5483,10 +5486,10 @@
5483+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5486+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5484+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5487+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5485 /* { dg-final { cleanup-saved-temps } } */ 5488 /* { dg-final { cleanup-saved-temps } } */
5486 5489Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
5487=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c' 5490===================================================================
5488--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2010-05-24 18:36:31 +0000 5491--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5489+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-05-03 15:14:56 +0000 5492+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c 2011-09-16 20:16:00.567565108 -0700
5490@@ -16,5 +16,5 @@ 5493@@ -16,5 +16,5 @@
5491 vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1); 5494 vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
5492 } 5495 }
@@ -5494,10 +5497,10 @@
5494-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5497-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5495+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5498+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5496 /* { dg-final { cleanup-saved-temps } } */ 5499 /* { dg-final { cleanup-saved-temps } } */
5497 5500Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
5498=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c' 5501===================================================================
5499--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2010-05-24 18:36:31 +0000 5502--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5500+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-05-03 15:14:56 +0000 5503+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c 2011-09-16 20:16:00.577565135 -0700
5501@@ -16,5 +16,5 @@ 5504@@ -16,5 +16,5 @@
5502 vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1); 5505 vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
5503 } 5506 }
@@ -5505,10 +5508,10 @@
5505-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5508-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5506+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5509+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5507 /* { dg-final { cleanup-saved-temps } } */ 5510 /* { dg-final { cleanup-saved-temps } } */
5508 5511Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
5509=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c' 5512===================================================================
5510--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2010-05-24 18:36:31 +0000 5513--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5511+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-05-03 15:14:56 +0000 5514+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c 2011-09-16 20:16:00.577565135 -0700
5512@@ -16,5 +16,5 @@ 5515@@ -16,5 +16,5 @@
5513 vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1); 5516 vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
5514 } 5517 }
@@ -5516,10 +5519,10 @@
5516-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5519-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5517+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5520+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5518 /* { dg-final { cleanup-saved-temps } } */ 5521 /* { dg-final { cleanup-saved-temps } } */
5519 5522Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
5520=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c' 5523===================================================================
5521--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2010-05-24 18:36:31 +0000 5524--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5522+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-05-03 15:14:56 +0000 5525+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c 2011-09-16 20:16:00.577565135 -0700
5523@@ -16,5 +16,5 @@ 5526@@ -16,5 +16,5 @@
5524 vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1); 5527 vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
5525 } 5528 }
@@ -5527,10 +5530,10 @@
5527-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5530-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5528+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5531+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5529 /* { dg-final { cleanup-saved-temps } } */ 5532 /* { dg-final { cleanup-saved-temps } } */
5530 5533Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
5531=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c' 5534===================================================================
5532--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2010-05-24 18:36:31 +0000 5535--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5533+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-05-03 15:14:56 +0000 5536+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c 2011-09-16 20:16:00.577565135 -0700
5534@@ -16,5 +16,5 @@ 5537@@ -16,5 +16,5 @@
5535 vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1); 5538 vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
5536 } 5539 }
@@ -5538,10 +5541,10 @@
5538-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5541-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5539+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5542+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5540 /* { dg-final { cleanup-saved-temps } } */ 5543 /* { dg-final { cleanup-saved-temps } } */
5541 5544Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
5542=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c' 5545===================================================================
5543--- old/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2010-05-24 18:36:31 +0000 5546--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5544+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-05-03 15:14:56 +0000 5547+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c 2011-09-16 20:16:00.577565135 -0700
5545@@ -16,5 +16,5 @@ 5548@@ -16,5 +16,5 @@
5546 vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1); 5549 vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
5547 } 5550 }
@@ -5549,10 +5552,10 @@
5549-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5552-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5550+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5553+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5551 /* { dg-final { cleanup-saved-temps } } */ 5554 /* { dg-final { cleanup-saved-temps } } */
5552 5555Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
5553=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c' 5556===================================================================
5554--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2010-05-24 18:36:31 +0000 5557--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5555+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-05-03 15:14:56 +0000 5558+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c 2011-09-16 20:16:00.577565135 -0700
5556@@ -16,5 +16,5 @@ 5559@@ -16,5 +16,5 @@
5557 vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1); 5560 vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
5558 } 5561 }
@@ -5560,10 +5563,10 @@
5560-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5563-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5561+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5564+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5562 /* { dg-final { cleanup-saved-temps } } */ 5565 /* { dg-final { cleanup-saved-temps } } */
5563 5566Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
5564=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c' 5567===================================================================
5565--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2010-05-24 18:36:31 +0000 5568--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5566+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-05-03 15:14:56 +0000 5569+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c 2011-09-16 20:16:00.577565135 -0700
5567@@ -16,5 +16,5 @@ 5570@@ -16,5 +16,5 @@
5568 vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1); 5571 vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
5569 } 5572 }
@@ -5571,10 +5574,10 @@
5571-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5574-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5572+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5575+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5573 /* { dg-final { cleanup-saved-temps } } */ 5576 /* { dg-final { cleanup-saved-temps } } */
5574 5577Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
5575=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c' 5578===================================================================
5576--- old/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2010-05-24 18:36:31 +0000 5579--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5577+++ new/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-05-03 15:14:56 +0000 5580+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c 2011-09-16 20:16:00.587565144 -0700
5578@@ -16,5 +16,5 @@ 5581@@ -16,5 +16,5 @@
5579 vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1); 5582 vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
5580 } 5583 }
@@ -5582,10 +5585,10 @@
5582-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5585-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5583+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5586+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5584 /* { dg-final { cleanup-saved-temps } } */ 5587 /* { dg-final { cleanup-saved-temps } } */
5585 5588Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
5586=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3f32.c' 5589===================================================================
5587--- old/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2010-05-24 18:36:31 +0000 5590--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-06-24 08:13:40.000000000 -0700
5588+++ new/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-05-03 15:14:56 +0000 5591+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3f32.c 2011-09-16 20:16:00.587565144 -0700
5589@@ -16,5 +16,5 @@ 5592@@ -16,5 +16,5 @@
5590 vst3_f32 (arg0_float32_t, arg1_float32x2x3_t); 5593 vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
5591 } 5594 }
@@ -5593,10 +5596,10 @@
5593-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5596-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5594+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5597+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5595 /* { dg-final { cleanup-saved-temps } } */ 5598 /* { dg-final { cleanup-saved-temps } } */
5596 5599Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
5597=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p16.c' 5600===================================================================
5598--- old/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2010-05-24 18:36:31 +0000 5601--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-06-24 08:13:40.000000000 -0700
5599+++ new/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-05-03 15:14:56 +0000 5602+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p16.c 2011-09-16 20:16:00.587565144 -0700
5600@@ -16,5 +16,5 @@ 5603@@ -16,5 +16,5 @@
5601 vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t); 5604 vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
5602 } 5605 }
@@ -5604,10 +5607,10 @@
5604-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5607-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5605+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5608+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5606 /* { dg-final { cleanup-saved-temps } } */ 5609 /* { dg-final { cleanup-saved-temps } } */
5607 5610Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
5608=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3p8.c' 5611===================================================================
5609--- old/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2010-05-24 18:36:31 +0000 5612--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-06-24 08:13:40.000000000 -0700
5610+++ new/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-05-03 15:14:56 +0000 5613+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3p8.c 2011-09-16 20:16:00.587565144 -0700
5611@@ -16,5 +16,5 @@ 5614@@ -16,5 +16,5 @@
5612 vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t); 5615 vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
5613 } 5616 }
@@ -5615,10 +5618,10 @@
5615-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5618-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5616+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5619+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5617 /* { dg-final { cleanup-saved-temps } } */ 5620 /* { dg-final { cleanup-saved-temps } } */
5618 5621Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
5619=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s16.c' 5622===================================================================
5620--- old/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2010-05-24 18:36:31 +0000 5623--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-06-24 08:13:40.000000000 -0700
5621+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-05-03 15:14:56 +0000 5624+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s16.c 2011-09-16 20:16:00.587565144 -0700
5622@@ -16,5 +16,5 @@ 5625@@ -16,5 +16,5 @@
5623 vst3_s16 (arg0_int16_t, arg1_int16x4x3_t); 5626 vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
5624 } 5627 }
@@ -5626,10 +5629,10 @@
5626-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5629-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5627+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5630+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5628 /* { dg-final { cleanup-saved-temps } } */ 5631 /* { dg-final { cleanup-saved-temps } } */
5629 5632Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
5630=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s32.c' 5633===================================================================
5631--- old/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2010-05-24 18:36:31 +0000 5634--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-06-24 08:13:40.000000000 -0700
5632+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-05-03 15:14:56 +0000 5635+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s32.c 2011-09-16 20:16:00.587565144 -0700
5633@@ -16,5 +16,5 @@ 5636@@ -16,5 +16,5 @@
5634 vst3_s32 (arg0_int32_t, arg1_int32x2x3_t); 5637 vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
5635 } 5638 }
@@ -5637,10 +5640,10 @@
5637-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5640-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5638+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5641+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5639 /* { dg-final { cleanup-saved-temps } } */ 5642 /* { dg-final { cleanup-saved-temps } } */
5640 5643Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
5641=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s64.c' 5644===================================================================
5642--- old/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2010-05-24 18:36:31 +0000 5645--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-06-24 08:13:40.000000000 -0700
5643+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-05-03 15:14:56 +0000 5646+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s64.c 2011-09-16 20:16:00.587565144 -0700
5644@@ -16,5 +16,5 @@ 5647@@ -16,5 +16,5 @@
5645 vst3_s64 (arg0_int64_t, arg1_int64x1x3_t); 5648 vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
5646 } 5649 }
@@ -5648,10 +5651,10 @@
5648-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5651-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5649+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5652+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5650 /* { dg-final { cleanup-saved-temps } } */ 5653 /* { dg-final { cleanup-saved-temps } } */
5651 5654Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
5652=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3s8.c' 5655===================================================================
5653--- old/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2010-05-24 18:36:31 +0000 5656--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-06-24 08:13:40.000000000 -0700
5654+++ new/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-05-03 15:14:56 +0000 5657+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3s8.c 2011-09-16 20:16:00.587565144 -0700
5655@@ -16,5 +16,5 @@ 5658@@ -16,5 +16,5 @@
5656 vst3_s8 (arg0_int8_t, arg1_int8x8x3_t); 5659 vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
5657 } 5660 }
@@ -5659,10 +5662,10 @@
5659-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5662-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5660+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5663+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5661 /* { dg-final { cleanup-saved-temps } } */ 5664 /* { dg-final { cleanup-saved-temps } } */
5662 5665Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
5663=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u16.c' 5666===================================================================
5664--- old/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2010-05-24 18:36:31 +0000 5667--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-06-24 08:13:40.000000000 -0700
5665+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-05-03 15:14:56 +0000 5668+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u16.c 2011-09-16 20:16:00.587565144 -0700
5666@@ -16,5 +16,5 @@ 5669@@ -16,5 +16,5 @@
5667 vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t); 5670 vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
5668 } 5671 }
@@ -5670,10 +5673,10 @@
5670-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5673-/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5671+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5674+/* { dg-final { scan-assembler "vst3\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5672 /* { dg-final { cleanup-saved-temps } } */ 5675 /* { dg-final { cleanup-saved-temps } } */
5673 5676Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
5674=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u32.c' 5677===================================================================
5675--- old/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2010-05-24 18:36:31 +0000 5678--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-06-24 08:13:40.000000000 -0700
5676+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-05-03 15:14:56 +0000 5679+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u32.c 2011-09-16 20:16:00.587565144 -0700
5677@@ -16,5 +16,5 @@ 5680@@ -16,5 +16,5 @@
5678 vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t); 5681 vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
5679 } 5682 }
@@ -5681,10 +5684,10 @@
5681-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5684-/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5682+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5685+/* { dg-final { scan-assembler "vst3\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5683 /* { dg-final { cleanup-saved-temps } } */ 5686 /* { dg-final { cleanup-saved-temps } } */
5684 5687Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
5685=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u64.c' 5688===================================================================
5686--- old/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2010-05-24 18:36:31 +0000 5689--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-06-24 08:13:40.000000000 -0700
5687+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-05-03 15:14:56 +0000 5690+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u64.c 2011-09-16 20:16:00.587565144 -0700
5688@@ -16,5 +16,5 @@ 5691@@ -16,5 +16,5 @@
5689 vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t); 5692 vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
5690 } 5693 }
@@ -5692,10 +5695,10 @@
5692-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5695-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5693+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5696+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5694 /* { dg-final { cleanup-saved-temps } } */ 5697 /* { dg-final { cleanup-saved-temps } } */
5695 5698Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
5696=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst3u8.c' 5699===================================================================
5697--- old/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2010-05-24 18:36:31 +0000 5700--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-06-24 08:13:40.000000000 -0700
5698+++ new/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-05-03 15:14:56 +0000 5701+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst3u8.c 2011-09-16 20:16:00.587565144 -0700
5699@@ -16,5 +16,5 @@ 5702@@ -16,5 +16,5 @@
5700 vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t); 5703 vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
5701 } 5704 }
@@ -5703,10 +5706,10 @@
5703-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5706-/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5704+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5707+/* { dg-final { scan-assembler "vst3\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5705 /* { dg-final { cleanup-saved-temps } } */ 5708 /* { dg-final { cleanup-saved-temps } } */
5706 5709Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
5707=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c' 5710===================================================================
5708--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2010-05-24 18:36:31 +0000 5711--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5709+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-05-03 15:14:56 +0000 5712+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c 2011-09-16 20:16:00.597565156 -0700
5710@@ -16,5 +16,5 @@ 5713@@ -16,5 +16,5 @@
5711 vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1); 5714 vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
5712 } 5715 }
@@ -5714,10 +5717,10 @@
5714-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5717-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5715+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5718+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5716 /* { dg-final { cleanup-saved-temps } } */ 5719 /* { dg-final { cleanup-saved-temps } } */
5717 5720Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
5718=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c' 5721===================================================================
5719--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2010-05-24 18:36:31 +0000 5722--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5720+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-05-03 15:14:56 +0000 5723+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c 2011-09-16 20:16:00.597565156 -0700
5721@@ -16,5 +16,5 @@ 5724@@ -16,5 +16,5 @@
5722 vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1); 5725 vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
5723 } 5726 }
@@ -5725,10 +5728,10 @@
5725-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5728-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5726+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5729+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5727 /* { dg-final { cleanup-saved-temps } } */ 5730 /* { dg-final { cleanup-saved-temps } } */
5728 5731Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
5729=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c' 5732===================================================================
5730--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2010-05-24 18:36:31 +0000 5733--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5731+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-05-03 15:14:56 +0000 5734+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c 2011-09-16 20:16:00.597565156 -0700
5732@@ -16,5 +16,5 @@ 5735@@ -16,5 +16,5 @@
5733 vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1); 5736 vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
5734 } 5737 }
@@ -5736,10 +5739,10 @@
5736-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5739-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5737+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5740+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5738 /* { dg-final { cleanup-saved-temps } } */ 5741 /* { dg-final { cleanup-saved-temps } } */
5739 5742Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
5740=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c' 5743===================================================================
5741--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2010-05-24 18:36:31 +0000 5744--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5742+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-05-03 15:14:56 +0000 5745+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c 2011-09-16 20:16:00.597565156 -0700
5743@@ -16,5 +16,5 @@ 5746@@ -16,5 +16,5 @@
5744 vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1); 5747 vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
5745 } 5748 }
@@ -5747,10 +5750,10 @@
5747-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5750-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5748+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5751+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5749 /* { dg-final { cleanup-saved-temps } } */ 5752 /* { dg-final { cleanup-saved-temps } } */
5750 5753Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
5751=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c' 5754===================================================================
5752--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2010-05-24 18:36:31 +0000 5755--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5753+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-05-03 15:14:56 +0000 5756+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c 2011-09-16 20:16:00.597565156 -0700
5754@@ -16,5 +16,5 @@ 5757@@ -16,5 +16,5 @@
5755 vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1); 5758 vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
5756 } 5759 }
@@ -5758,10 +5761,10 @@
5758-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5761-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5759+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5762+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5760 /* { dg-final { cleanup-saved-temps } } */ 5763 /* { dg-final { cleanup-saved-temps } } */
5761 5764Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
5762=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c' 5765===================================================================
5763--- old/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2010-05-24 18:36:31 +0000 5766--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5764+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-05-03 15:14:56 +0000 5767+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c 2011-09-16 20:16:00.597565156 -0700
5765@@ -16,5 +16,5 @@ 5768@@ -16,5 +16,5 @@
5766 vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1); 5769 vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
5767 } 5770 }
@@ -5769,10 +5772,10 @@
5769-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5772-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5770+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5773+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5771 /* { dg-final { cleanup-saved-temps } } */ 5774 /* { dg-final { cleanup-saved-temps } } */
5772 5775Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
5773=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c' 5776===================================================================
5774--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2010-05-24 18:36:31 +0000 5777--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-06-24 08:13:40.000000000 -0700
5775+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-05-03 15:14:56 +0000 5778+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c 2011-09-16 20:16:00.597565156 -0700
5776@@ -16,6 +16,6 @@ 5779@@ -16,6 +16,6 @@
5777 vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t); 5780 vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
5778 } 5781 }
@@ -5782,10 +5785,10 @@
5782+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5785+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5783+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5786+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5784 /* { dg-final { cleanup-saved-temps } } */ 5787 /* { dg-final { cleanup-saved-temps } } */
5785 5788Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
5786=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c' 5789===================================================================
5787--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2010-05-24 18:36:31 +0000 5790--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-06-24 08:13:40.000000000 -0700
5788+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-05-03 15:14:56 +0000 5791+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c 2011-09-16 20:16:00.597565156 -0700
5789@@ -16,6 +16,6 @@ 5792@@ -16,6 +16,6 @@
5790 vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t); 5793 vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
5791 } 5794 }
@@ -5795,10 +5798,10 @@
5795+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5798+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5796+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5799+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5797 /* { dg-final { cleanup-saved-temps } } */ 5800 /* { dg-final { cleanup-saved-temps } } */
5798 5801Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
5799=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c' 5802===================================================================
5800--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2010-05-24 18:36:31 +0000 5803--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-06-24 08:13:40.000000000 -0700
5801+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-05-03 15:14:56 +0000 5804+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c 2011-09-16 20:16:00.597565156 -0700
5802@@ -16,6 +16,6 @@ 5805@@ -16,6 +16,6 @@
5803 vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t); 5806 vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
5804 } 5807 }
@@ -5808,10 +5811,10 @@
5808+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5811+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5809+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5812+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5810 /* { dg-final { cleanup-saved-temps } } */ 5813 /* { dg-final { cleanup-saved-temps } } */
5811 5814Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
5812=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c' 5815===================================================================
5813--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2010-05-24 18:36:31 +0000 5816--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-06-24 08:13:40.000000000 -0700
5814+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-05-03 15:14:56 +0000 5817+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c 2011-09-16 20:16:00.597565156 -0700
5815@@ -16,6 +16,6 @@ 5818@@ -16,6 +16,6 @@
5816 vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t); 5819 vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
5817 } 5820 }
@@ -5821,10 +5824,10 @@
5821+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5824+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5822+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5825+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5823 /* { dg-final { cleanup-saved-temps } } */ 5826 /* { dg-final { cleanup-saved-temps } } */
5824 5827Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
5825=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c' 5828===================================================================
5826--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2010-05-24 18:36:31 +0000 5829--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-06-24 08:13:40.000000000 -0700
5827+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-05-03 15:14:56 +0000 5830+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c 2011-09-16 20:16:00.597565156 -0700
5828@@ -16,6 +16,6 @@ 5831@@ -16,6 +16,6 @@
5829 vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t); 5832 vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
5830 } 5833 }
@@ -5834,10 +5837,10 @@
5834+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5837+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5835+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5838+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5836 /* { dg-final { cleanup-saved-temps } } */ 5839 /* { dg-final { cleanup-saved-temps } } */
5837 5840Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
5838=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c' 5841===================================================================
5839--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2010-05-24 18:36:31 +0000 5842--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-06-24 08:13:40.000000000 -0700
5840+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-05-03 15:14:56 +0000 5843+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c 2011-09-16 20:16:00.607565171 -0700
5841@@ -16,6 +16,6 @@ 5844@@ -16,6 +16,6 @@
5842 vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t); 5845 vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
5843 } 5846 }
@@ -5847,10 +5850,10 @@
5847+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5850+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5848+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5851+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5849 /* { dg-final { cleanup-saved-temps } } */ 5852 /* { dg-final { cleanup-saved-temps } } */
5850 5853Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
5851=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c' 5854===================================================================
5852--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2010-05-24 18:36:31 +0000 5855--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-06-24 08:13:40.000000000 -0700
5853+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-05-03 15:14:56 +0000 5856+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c 2011-09-16 20:16:00.607565171 -0700
5854@@ -16,6 +16,6 @@ 5857@@ -16,6 +16,6 @@
5855 vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t); 5858 vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
5856 } 5859 }
@@ -5860,10 +5863,10 @@
5860+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5863+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5861+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5864+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5862 /* { dg-final { cleanup-saved-temps } } */ 5865 /* { dg-final { cleanup-saved-temps } } */
5863 5866Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
5864=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c' 5867===================================================================
5865--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2010-05-24 18:36:31 +0000 5868--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-06-24 08:13:40.000000000 -0700
5866+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-05-03 15:14:56 +0000 5869+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c 2011-09-16 20:16:00.607565171 -0700
5867@@ -16,6 +16,6 @@ 5870@@ -16,6 +16,6 @@
5868 vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t); 5871 vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
5869 } 5872 }
@@ -5873,10 +5876,10 @@
5873+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5876+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5874+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5877+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5875 /* { dg-final { cleanup-saved-temps } } */ 5878 /* { dg-final { cleanup-saved-temps } } */
5876 5879Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
5877=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c' 5880===================================================================
5878--- old/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2010-05-24 18:36:31 +0000 5881--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-06-24 08:13:40.000000000 -0700
5879+++ new/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-05-03 15:14:56 +0000 5882+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c 2011-09-16 20:16:00.607565171 -0700
5880@@ -16,6 +16,6 @@ 5883@@ -16,6 +16,6 @@
5881 vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t); 5884 vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
5882 } 5885 }
@@ -5886,10 +5889,10 @@
5886+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5889+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5887+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5890+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5888 /* { dg-final { cleanup-saved-temps } } */ 5891 /* { dg-final { cleanup-saved-temps } } */
5889 5892Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
5890=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c' 5893===================================================================
5891--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2010-05-24 18:36:31 +0000 5894--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-06-24 08:13:40.000000000 -0700
5892+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-05-03 15:14:56 +0000 5895+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c 2011-09-16 20:16:00.607565171 -0700
5893@@ -16,5 +16,5 @@ 5896@@ -16,5 +16,5 @@
5894 vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1); 5897 vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
5895 } 5898 }
@@ -5897,10 +5900,10 @@
5897-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5900-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5898+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5901+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5899 /* { dg-final { cleanup-saved-temps } } */ 5902 /* { dg-final { cleanup-saved-temps } } */
5900 5903Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
5901=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c' 5904===================================================================
5902--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2010-05-24 18:36:31 +0000 5905--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-06-24 08:13:40.000000000 -0700
5903+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-05-03 15:14:56 +0000 5906+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c 2011-09-16 20:16:00.607565171 -0700
5904@@ -16,5 +16,5 @@ 5907@@ -16,5 +16,5 @@
5905 vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1); 5908 vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
5906 } 5909 }
@@ -5908,10 +5911,10 @@
5908-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5911-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5909+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5912+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5910 /* { dg-final { cleanup-saved-temps } } */ 5913 /* { dg-final { cleanup-saved-temps } } */
5911 5914Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
5912=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c' 5915===================================================================
5913--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2010-05-24 18:36:31 +0000 5916--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-06-24 08:13:40.000000000 -0700
5914+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-05-03 15:14:56 +0000 5917+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c 2011-09-16 20:16:00.607565171 -0700
5915@@ -16,5 +16,5 @@ 5918@@ -16,5 +16,5 @@
5916 vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1); 5919 vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
5917 } 5920 }
@@ -5919,10 +5922,10 @@
5919-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5922-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5920+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5923+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5921 /* { dg-final { cleanup-saved-temps } } */ 5924 /* { dg-final { cleanup-saved-temps } } */
5922 5925Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
5923=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c' 5926===================================================================
5924--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2010-05-24 18:36:31 +0000 5927--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-06-24 08:13:40.000000000 -0700
5925+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-05-03 15:14:56 +0000 5928+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c 2011-09-16 20:16:00.607565171 -0700
5926@@ -16,5 +16,5 @@ 5929@@ -16,5 +16,5 @@
5927 vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1); 5930 vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
5928 } 5931 }
@@ -5930,10 +5933,10 @@
5930-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5933-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5931+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5934+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5932 /* { dg-final { cleanup-saved-temps } } */ 5935 /* { dg-final { cleanup-saved-temps } } */
5933 5936Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
5934=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c' 5937===================================================================
5935--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2010-05-24 18:36:31 +0000 5938--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-06-24 08:13:40.000000000 -0700
5936+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-05-03 15:14:56 +0000 5939+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c 2011-09-16 20:16:00.607565171 -0700
5937@@ -16,5 +16,5 @@ 5940@@ -16,5 +16,5 @@
5938 vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1); 5941 vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
5939 } 5942 }
@@ -5941,10 +5944,10 @@
5941-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5944-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5942+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5945+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5943 /* { dg-final { cleanup-saved-temps } } */ 5946 /* { dg-final { cleanup-saved-temps } } */
5944 5947Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
5945=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c' 5948===================================================================
5946--- old/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2010-05-24 18:36:31 +0000 5949--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-06-24 08:13:40.000000000 -0700
5947+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-05-03 15:14:56 +0000 5950+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c 2011-09-16 20:16:00.607565171 -0700
5948@@ -16,5 +16,5 @@ 5951@@ -16,5 +16,5 @@
5949 vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1); 5952 vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
5950 } 5953 }
@@ -5952,10 +5955,10 @@
5952-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5955-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5953+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5956+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5954 /* { dg-final { cleanup-saved-temps } } */ 5957 /* { dg-final { cleanup-saved-temps } } */
5955 5958Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
5956=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c' 5959===================================================================
5957--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2010-05-24 18:36:31 +0000 5960--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-06-24 08:13:40.000000000 -0700
5958+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-05-03 15:14:56 +0000 5961+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c 2011-09-16 20:16:00.607565171 -0700
5959@@ -16,5 +16,5 @@ 5962@@ -16,5 +16,5 @@
5960 vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1); 5963 vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
5961 } 5964 }
@@ -5963,10 +5966,10 @@
5963-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5966-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5964+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5967+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5965 /* { dg-final { cleanup-saved-temps } } */ 5968 /* { dg-final { cleanup-saved-temps } } */
5966 5969Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
5967=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c' 5970===================================================================
5968--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2010-05-24 18:36:31 +0000 5971--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-06-24 08:13:40.000000000 -0700
5969+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-05-03 15:14:56 +0000 5972+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c 2011-09-16 20:16:00.607565171 -0700
5970@@ -16,5 +16,5 @@ 5973@@ -16,5 +16,5 @@
5971 vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1); 5974 vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
5972 } 5975 }
@@ -5974,10 +5977,10 @@
5974-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5977-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5975+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5978+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5976 /* { dg-final { cleanup-saved-temps } } */ 5979 /* { dg-final { cleanup-saved-temps } } */
5977 5980Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
5978=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c' 5981===================================================================
5979--- old/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2010-05-24 18:36:31 +0000 5982--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-06-24 08:13:40.000000000 -0700
5980+++ new/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-05-03 15:14:56 +0000 5983+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c 2011-09-16 20:16:00.607565171 -0700
5981@@ -16,5 +16,5 @@ 5984@@ -16,5 +16,5 @@
5982 vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1); 5985 vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
5983 } 5986 }
@@ -5985,10 +5988,10 @@
5985-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5988-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5986+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5989+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5987 /* { dg-final { cleanup-saved-temps } } */ 5990 /* { dg-final { cleanup-saved-temps } } */
5988 5991Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
5989=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4f32.c' 5992===================================================================
5990--- old/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2010-05-24 18:36:31 +0000 5993--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-06-24 08:13:40.000000000 -0700
5991+++ new/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-05-03 15:14:56 +0000 5994+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4f32.c 2011-09-16 20:16:00.607565171 -0700
5992@@ -16,5 +16,5 @@ 5995@@ -16,5 +16,5 @@
5993 vst4_f32 (arg0_float32_t, arg1_float32x2x4_t); 5996 vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
5994 } 5997 }
@@ -5996,10 +5999,10 @@
5996-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 5999-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5997+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6000+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
5998 /* { dg-final { cleanup-saved-temps } } */ 6001 /* { dg-final { cleanup-saved-temps } } */
5999 6002Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
6000=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p16.c' 6003===================================================================
6001--- old/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2010-05-24 18:36:31 +0000 6004--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-06-24 08:13:40.000000000 -0700
6002+++ new/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-05-03 15:14:56 +0000 6005+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p16.c 2011-09-16 20:16:00.607565171 -0700
6003@@ -16,5 +16,5 @@ 6006@@ -16,5 +16,5 @@
6004 vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t); 6007 vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
6005 } 6008 }
@@ -6007,10 +6010,10 @@
6007-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6010-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6008+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6011+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6009 /* { dg-final { cleanup-saved-temps } } */ 6012 /* { dg-final { cleanup-saved-temps } } */
6010 6013Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
6011=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4p8.c' 6014===================================================================
6012--- old/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2010-05-24 18:36:31 +0000 6015--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-06-24 08:13:40.000000000 -0700
6013+++ new/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-05-03 15:14:56 +0000 6016+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4p8.c 2011-09-16 20:16:00.607565171 -0700
6014@@ -16,5 +16,5 @@ 6017@@ -16,5 +16,5 @@
6015 vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t); 6018 vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
6016 } 6019 }
@@ -6018,10 +6021,10 @@
6018-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6021-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6019+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6022+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6020 /* { dg-final { cleanup-saved-temps } } */ 6023 /* { dg-final { cleanup-saved-temps } } */
6021 6024Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
6022=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s16.c' 6025===================================================================
6023--- old/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2010-05-24 18:36:31 +0000 6026--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-06-24 08:13:40.000000000 -0700
6024+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-05-03 15:14:56 +0000 6027+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s16.c 2011-09-16 20:16:00.607565171 -0700
6025@@ -16,5 +16,5 @@ 6028@@ -16,5 +16,5 @@
6026 vst4_s16 (arg0_int16_t, arg1_int16x4x4_t); 6029 vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
6027 } 6030 }
@@ -6029,10 +6032,10 @@
6029-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6032-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6030+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6033+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6031 /* { dg-final { cleanup-saved-temps } } */ 6034 /* { dg-final { cleanup-saved-temps } } */
6032 6035Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
6033=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s32.c' 6036===================================================================
6034--- old/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2010-05-24 18:36:31 +0000 6037--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-06-24 08:13:40.000000000 -0700
6035+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-05-03 15:14:56 +0000 6038+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s32.c 2011-09-16 20:16:00.607565171 -0700
6036@@ -16,5 +16,5 @@ 6039@@ -16,5 +16,5 @@
6037 vst4_s32 (arg0_int32_t, arg1_int32x2x4_t); 6040 vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
6038 } 6041 }
@@ -6040,10 +6043,10 @@
6040-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6043-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6041+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6044+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6042 /* { dg-final { cleanup-saved-temps } } */ 6045 /* { dg-final { cleanup-saved-temps } } */
6043 6046Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
6044=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s64.c' 6047===================================================================
6045--- old/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2010-05-24 18:36:31 +0000 6048--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-06-24 08:13:40.000000000 -0700
6046+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-05-03 15:14:56 +0000 6049+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s64.c 2011-09-16 20:16:00.607565171 -0700
6047@@ -16,5 +16,5 @@ 6050@@ -16,5 +16,5 @@
6048 vst4_s64 (arg0_int64_t, arg1_int64x1x4_t); 6051 vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
6049 } 6052 }
@@ -6051,10 +6054,10 @@
6051-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6054-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6052+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6055+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6053 /* { dg-final { cleanup-saved-temps } } */ 6056 /* { dg-final { cleanup-saved-temps } } */
6054 6057Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
6055=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4s8.c' 6058===================================================================
6056--- old/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2010-05-24 18:36:31 +0000 6059--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-06-24 08:13:40.000000000 -0700
6057+++ new/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-05-03 15:14:56 +0000 6060+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4s8.c 2011-09-16 20:16:00.607565171 -0700
6058@@ -16,5 +16,5 @@ 6061@@ -16,5 +16,5 @@
6059 vst4_s8 (arg0_int8_t, arg1_int8x8x4_t); 6062 vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
6060 } 6063 }
@@ -6062,10 +6065,10 @@
6062-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6065-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6063+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6066+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6064 /* { dg-final { cleanup-saved-temps } } */ 6067 /* { dg-final { cleanup-saved-temps } } */
6065 6068Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
6066=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u16.c' 6069===================================================================
6067--- old/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2010-05-24 18:36:31 +0000 6070--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-06-24 08:13:40.000000000 -0700
6068+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-05-03 15:14:56 +0000 6071+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u16.c 2011-09-16 20:16:00.607565171 -0700
6069@@ -16,5 +16,5 @@ 6072@@ -16,5 +16,5 @@
6070 vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t); 6073 vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
6071 } 6074 }
@@ -6073,10 +6076,10 @@
6073-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6076-/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6074+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6077+/* { dg-final { scan-assembler "vst4\.16\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6075 /* { dg-final { cleanup-saved-temps } } */ 6078 /* { dg-final { cleanup-saved-temps } } */
6076 6079Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
6077=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u32.c' 6080===================================================================
6078--- old/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2010-05-24 18:36:31 +0000 6081--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-06-24 08:13:40.000000000 -0700
6079+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-05-03 15:14:56 +0000 6082+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u32.c 2011-09-16 20:16:00.607565171 -0700
6080@@ -16,5 +16,5 @@ 6083@@ -16,5 +16,5 @@
6081 vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t); 6084 vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
6082 } 6085 }
@@ -6084,10 +6087,10 @@
6084-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6087-/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6085+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6088+/* { dg-final { scan-assembler "vst4\.32\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6086 /* { dg-final { cleanup-saved-temps } } */ 6089 /* { dg-final { cleanup-saved-temps } } */
6087 6090Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
6088=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u64.c' 6091===================================================================
6089--- old/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2010-05-24 18:36:31 +0000 6092--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-06-24 08:13:40.000000000 -0700
6090+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-05-03 15:14:56 +0000 6093+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u64.c 2011-09-16 20:16:00.607565171 -0700
6091@@ -16,5 +16,5 @@ 6094@@ -16,5 +16,5 @@
6092 vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t); 6095 vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
6093 } 6096 }
@@ -6095,10 +6098,10 @@
6095-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6098-/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6096+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6099+/* { dg-final { scan-assembler "vst1\.64\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6097 /* { dg-final { cleanup-saved-temps } } */ 6100 /* { dg-final { cleanup-saved-temps } } */
6098 6101Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
6099=== modified file 'gcc/testsuite/gcc.target/arm/neon/vst4u8.c' 6102===================================================================
6100--- old/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2010-05-24 18:36:31 +0000 6103--- gcc-4_6-branch.orig/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-06-24 08:13:40.000000000 -0700
6101+++ new/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-05-03 15:14:56 +0000 6104+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/neon/vst4u8.c 2011-09-16 20:16:00.607565171 -0700
6102@@ -16,5 +16,5 @@ 6105@@ -16,5 +16,5 @@
6103 vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t); 6106 vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
6104 } 6107 }
@@ -6106,10 +6109,10 @@
6106-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6109-/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6107+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ 6110+/* { dg-final { scan-assembler "vst4\.8\[ \]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
6108 /* { dg-final { cleanup-saved-temps } } */ 6111 /* { dg-final { cleanup-saved-temps } } */
6109 6112Index: gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c
6110=== added file 'gcc/testsuite/gcc.target/arm/pr46329.c' 6113===================================================================
6111--- old/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000 6114--- /dev/null 1970-01-01 00:00:00.000000000 +0000
6112+++ new/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 15:18:07 +0000 6115+++ gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr46329.c 2011-09-16 20:16:00.617565191 -0700
6113@@ -0,0 +1,9 @@ 6116@@ -0,0 +1,9 @@
6114+/* { dg-options "-O2" } */ 6117+/* { dg-options "-O2" } */
6115+/* { dg-add-options arm_neon } */ 6118+/* { dg-add-options arm_neon } */
@@ -6120,4 +6123,3 @@
6120+{ 6123+{
6121+ x <<= x; 6124+ x <<= x;
6122+} 6125+}
6123
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
index 8d2ce21762..4abfa02a77 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106763.patch
@@ -1,87 +1,16 @@
12011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 12011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2 2
3 Backport from mainline. 3 Backport from mainline.
4 LP 791327
5 gcc/
6 2011-06-09 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 PR target/49335
9 * config/arm/predicates.md (add_operator): New.
10 * config/arm/arm.md ("*arith_shiftsi"): Fix for SP reg usage
11 in Thumb2.
12
132011-06-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
14
15 Backport from mainline.
16 gcc/ 4 gcc/
17 2011-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 5 2011-06-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
18 6
19 PR target/49385 7 PR target/49385
20 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast 8 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast
21 one of the operands is a register. 9 one of the operands is a register.
22 10Index: gcc-4_6-branch/gcc/config/arm/thumb2.md
23=== modified file 'gcc/config/arm/arm.md' 11===================================================================
24--- old/gcc/config/arm/arm.md 2011-06-27 22:14:07 +0000 12--- gcc-4_6-branch.orig/gcc/config/arm/thumb2.md 2011-09-16 20:22:40.000000000 -0700
25+++ new/gcc/config/arm/arm.md 2011-06-28 12:02:27 +0000 13+++ gcc-4_6-branch/gcc/config/arm/thumb2.md 2011-09-16 20:28:47.648690433 -0700
26@@ -8584,18 +8584,22 @@
27 ;; Patterns to allow combination of arithmetic, cond code and shifts
28
29 (define_insn "*arith_shiftsi"
30- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
31+ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
32 (match_operator:SI 1 "shiftable_operator"
33 [(match_operator:SI 3 "shift_operator"
34- [(match_operand:SI 4 "s_register_operand" "r,r")
35- (match_operand:SI 5 "shift_amount_operand" "M,r")])
36- (match_operand:SI 2 "s_register_operand" "rk,rk")]))]
37+ [(match_operand:SI 4 "s_register_operand" "r,r,r,r")
38+ (match_operand:SI 5 "shift_amount_operand" "M,M,M,r")])
39+ (match_operand:SI 2 "s_register_operand" "rk,rk,r,rk")]))]
40 "TARGET_32BIT"
41 "%i1%?\\t%0, %2, %4%S3"
42 [(set_attr "predicable" "yes")
43 (set_attr "shift" "4")
44- (set_attr "arch" "32,a")
45- ;; We have to make sure to disable the second alternative if
46+ (set_attr "arch" "a,t2,t2,a")
47+ ;; Thumb2 doesn't allow the stack pointer to be used for
48+ ;; operand1 for all operations other than add and sub. In this case
49+ ;; the minus operation is a candidate for an rsub and hence needs
50+ ;; to be disabled.
51+ ;; We have to make sure to disable the fourth alternative if
52 ;; the shift_operator is MULT, since otherwise the insn will
53 ;; also match a multiply_accumulate pattern and validate_change
54 ;; will allow a replacement of the constant with a register
55@@ -8603,9 +8607,13 @@
56 (set_attr_alternative "insn_enabled"
57 [(const_string "yes")
58 (if_then_else
59+ (match_operand:SI 1 "add_operator" "")
60+ (const_string "yes") (const_string "no"))
61+ (const_string "yes")
62+ (if_then_else
63 (match_operand:SI 3 "mult_operator" "")
64 (const_string "no") (const_string "yes"))])
65- (set_attr "type" "alu_shift,alu_shift_reg")])
66+ (set_attr "type" "alu_shift,alu_shift,alu_shift,alu_shift_reg")])
67
68 (define_split
69 [(set (match_operand:SI 0 "s_register_operand" "")
70
71=== modified file 'gcc/config/arm/predicates.md'
72--- old/gcc/config/arm/predicates.md 2011-05-03 15:14:56 +0000
73+++ new/gcc/config/arm/predicates.md 2011-06-22 15:50:23 +0000
74@@ -687,3 +687,6 @@
75 (define_special_predicate "neon_struct_operand"
76 (and (match_code "mem")
77 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
78+
79+(define_special_predicate "add_operator"
80+ (match_code "plus"))
81
82=== modified file 'gcc/config/arm/thumb2.md'
83--- old/gcc/config/arm/thumb2.md 2011-06-14 14:37:30 +0000
84+++ new/gcc/config/arm/thumb2.md 2011-06-20 12:18:27 +0000
85@@ -207,7 +207,9 @@ 14@@ -207,7 +207,9 @@
86 (define_insn "*thumb2_movhi_insn" 15 (define_insn "*thumb2_movhi_insn"
87 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") 16 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
@@ -93,4 +22,3 @@
93 "@ 22 "@
94 mov%?\\t%0, %1\\t%@ movhi 23 mov%?\\t%0, %1\\t%@ movhi
95 movw%?\\t%0, %L1\\t%@ movhi 24 movw%?\\t%0, %L1\\t%@ movhi
96
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
index 37e3036b22..ff34514ff7 100644
--- a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106769.patch
@@ -50,8 +50,10 @@
50 * gcc.dg/vect/vect-widen-mult-half.c: New test. 50 * gcc.dg/vect/vect-widen-mult-half.c: New test.
51 51
52=== added file 'gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c' 52=== added file 'gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c'
53--- old/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c 1970-01-01 00:00:00 +0000 53Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c
54+++ new/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c 2011-07-06 12:04:10 +0000 54===================================================================
55--- /dev/null 1970-01-01 00:00:00.000000000 +0000
56+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/slp-widen-mult-half.c 2011-09-16 20:32:57.279056697 -0700
55@@ -0,0 +1,52 @@ 57@@ -0,0 +1,52 @@
56+/* { dg-require-effective-target vect_int } */ 58+/* { dg-require-effective-target vect_int } */
57+ 59+
@@ -105,10 +107,10 @@
105+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */ 107+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
106+/* { dg-final { cleanup-tree-dump "vect" } } */ 108+/* { dg-final { cleanup-tree-dump "vect" } } */
107+ 109+
108 110Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c
109=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c' 111===================================================================
110--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c 1970-01-01 00:00:00 +0000 112--- /dev/null 1970-01-01 00:00:00.000000000 +0000
111+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c 2011-07-06 12:04:10 +0000 113+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half-u8.c 2011-09-16 20:32:57.279056697 -0700
112@@ -0,0 +1,59 @@ 114@@ -0,0 +1,59 @@
113+/* { dg-require-effective-target vect_int } */ 115+/* { dg-require-effective-target vect_int } */
114+ 116+
@@ -169,10 +171,10 @@
169+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */ 171+/* { dg-final { scan-tree-dump-times "pattern recognized" 2 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
170+/* { dg-final { cleanup-tree-dump "vect" } } */ 172+/* { dg-final { cleanup-tree-dump "vect" } } */
171+ 173+
172 174Index: gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c
173=== added file 'gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c' 175===================================================================
174--- old/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c 1970-01-01 00:00:00 +0000 176--- /dev/null 1970-01-01 00:00:00.000000000 +0000
175+++ new/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c 2011-07-06 12:04:10 +0000 177+++ gcc-4_6-branch/gcc/testsuite/gcc.dg/vect/vect-widen-mult-half.c 2011-09-16 20:32:57.279056697 -0700
176@@ -0,0 +1,49 @@ 178@@ -0,0 +1,49 @@
177+/* { dg-require-effective-target vect_int } */ 179+/* { dg-require-effective-target vect_int } */
178+ 180+
@@ -223,10 +225,10 @@
223+/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */ 225+/* { dg-final { scan-tree-dump-times "pattern recognized" 1 "vect" { target vect_widen_mult_hi_to_si_pattern } } } */
224+/* { dg-final { cleanup-tree-dump "vect" } } */ 226+/* { dg-final { cleanup-tree-dump "vect" } } */
225+ 227+
226 228Index: gcc-4_6-branch/gcc/tree-vect-loop.c
227=== modified file 'gcc/tree-vect-loop.c' 229===================================================================
228--- old/gcc/tree-vect-loop.c 2011-07-04 11:13:51 +0000 230--- gcc-4_6-branch.orig/gcc/tree-vect-loop.c 2011-09-16 20:31:52.000000000 -0700
229+++ new/gcc/tree-vect-loop.c 2011-07-11 11:02:55 +0000 231+++ gcc-4_6-branch/gcc/tree-vect-loop.c 2011-09-16 20:32:57.289056641 -0700
230@@ -181,6 +181,8 @@ 232@@ -181,6 +181,8 @@
231 stmt_vec_info stmt_info; 233 stmt_vec_info stmt_info;
232 int i; 234 int i;
@@ -246,7 +248,6 @@
246- tree vf_vectype; 248- tree vf_vectype;
247- gimple stmt = gsi_stmt (si), pattern_stmt; 249- gimple stmt = gsi_stmt (si), pattern_stmt;
248- stmt_info = vinfo_for_stmt (stmt); 250- stmt_info = vinfo_for_stmt (stmt);
249-
250+ tree vf_vectype; 251+ tree vf_vectype;
251+ 252+
252+ if (analyze_pattern_stmt) 253+ if (analyze_pattern_stmt)
@@ -256,7 +257,7 @@
256+ } 257+ }
257+ else 258+ else
258+ stmt = gsi_stmt (si); 259+ stmt = gsi_stmt (si);
259+ 260
260+ stmt_info = vinfo_for_stmt (stmt); 261+ stmt_info = vinfo_for_stmt (stmt);
261+ 262+
262 if (vect_print_dump_info (REPORT_DETAILS)) 263 if (vect_print_dump_info (REPORT_DETAILS))
@@ -376,10 +377,10 @@
376 } /* stmts in BB */ 377 } /* stmts in BB */
377 } /* BBs in loop */ 378 } /* BBs in loop */
378 379
379 380Index: gcc-4_6-branch/gcc/tree-vect-patterns.c
380=== modified file 'gcc/tree-vect-patterns.c' 381===================================================================
381--- old/gcc/tree-vect-patterns.c 2011-06-22 12:10:44 +0000 382--- gcc-4_6-branch.orig/gcc/tree-vect-patterns.c 2011-09-16 20:31:52.000000000 -0700
382+++ new/gcc/tree-vect-patterns.c 2011-07-06 12:04:10 +0000 383+++ gcc-4_6-branch/gcc/tree-vect-patterns.c 2011-09-16 20:32:57.289056641 -0700
383@@ -39,10 +39,13 @@ 384@@ -39,10 +39,13 @@
384 #include "diagnostic-core.h" 385 #include "diagnostic-core.h"
385 386
@@ -552,21 +553,6 @@
552 S5 prod_T = a_T * CONST; 553 S5 prod_T = a_T * CONST;
553 554
554- Input: 555- Input:
555-
556- * LAST_STMT: A stmt from which the pattern search begins. In the example,
557- when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
558- detected.
559-
560- Output:
561-
562- * TYPE_IN: The type of the input arguments to the pattern.
563-
564- * TYPE_OUT: The type of the output of this pattern.
565-
566- * Return value: A new stmt that will be used to replace the sequence of
567- stmts that constitute the pattern. In this case it will be:
568- WIDEN_MULT <a_t, b_t>
569- */
570+ A special case of multiplication by constants is when 'TYPE' is 4 times 556+ A special case of multiplication by constants is when 'TYPE' is 4 times
571+ bigger than 'type', but CONST fits an intermediate type 2 times smaller 557+ bigger than 'type', but CONST fits an intermediate type 2 times smaller
572+ than 'TYPE'. In that case we create an additional pattern stmt for S3 558+ than 'TYPE'. In that case we create an additional pattern stmt for S3
@@ -584,20 +570,30 @@
584+ '--> prod_T' = a_it w* CONST; 570+ '--> prod_T' = a_it w* CONST;
585+ 571+
586+ Input/Output: 572+ Input/Output:
587+ 573
574- * LAST_STMT: A stmt from which the pattern search begins. In the example,
575- when this function is called with S5, the pattern {S3,S4,S5,(S6)} is
576- detected.
588+ * STMTS: Contains a stmt from which the pattern search begins. In the 577+ * STMTS: Contains a stmt from which the pattern search begins. In the
589+ example, when this function is called with S5, the pattern {S3,S4,S5,(S6)} 578+ example, when this function is called with S5, the pattern {S3,S4,S5,(S6)}
590+ is detected. In case of unsigned widen-mult, the original stmt (S5) is 579+ is detected. In case of unsigned widen-mult, the original stmt (S5) is
591+ replaced with S6 in STMTS. In case of multiplication by a constant 580+ replaced with S6 in STMTS. In case of multiplication by a constant
592+ of an intermediate type (the last case above), STMTS also contains S3 581+ of an intermediate type (the last case above), STMTS also contains S3
593+ (inserted before S5). 582+ (inserted before S5).
594+ 583
584- Output:
595+ Output: 585+ Output:
596+ 586
587- * TYPE_IN: The type of the input arguments to the pattern.
597+ * TYPE_IN: The type of the input arguments to the pattern. 588+ * TYPE_IN: The type of the input arguments to the pattern.
598+ 589
590- * TYPE_OUT: The type of the output of this pattern.
599+ * TYPE_OUT: The type of the output of this pattern. 591+ * TYPE_OUT: The type of the output of this pattern.
600+ 592
593- * Return value: A new stmt that will be used to replace the sequence of
594- stmts that constitute the pattern. In this case it will be:
595- WIDEN_MULT <a_t, b_t>
596- */
601+ * Return value: A new stmt that will be used to replace the sequence of 597+ * Return value: A new stmt that will be used to replace the sequence of
602+ stmts that constitute the pattern. In this case it will be: 598+ stmts that constitute the pattern. In this case it will be:
603+ WIDEN_MULT <a_t, b_t> 599+ WIDEN_MULT <a_t, b_t>
@@ -932,10 +928,10 @@
932 928
933 if (vect_print_dump_info (REPORT_DETAILS)) 929 if (vect_print_dump_info (REPORT_DETAILS))
934 fprintf (vect_dump, "=== vect_pattern_recog ==="); 930 fprintf (vect_dump, "=== vect_pattern_recog ===");
935 931Index: gcc-4_6-branch/gcc/tree-vect-slp.c
936=== modified file 'gcc/tree-vect-slp.c' 932===================================================================
937--- old/gcc/tree-vect-slp.c 2011-06-19 10:59:13 +0000 933--- gcc-4_6-branch.orig/gcc/tree-vect-slp.c 2011-09-16 20:31:52.000000000 -0700
938+++ new/gcc/tree-vect-slp.c 2011-07-06 12:04:10 +0000 934+++ gcc-4_6-branch/gcc/tree-vect-slp.c 2011-09-16 20:32:57.289056641 -0700
939@@ -152,7 +152,9 @@ 935@@ -152,7 +152,9 @@
940 if (loop && def_stmt && gimple_bb (def_stmt) 936 if (loop && def_stmt && gimple_bb (def_stmt)
941 && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt)) 937 && flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
@@ -947,10 +943,10 @@
947 { 943 {
948 if (!*first_stmt_dt0) 944 if (!*first_stmt_dt0)
949 *pattern0 = true; 945 *pattern0 = true;
950 946Index: gcc-4_6-branch/gcc/tree-vect-stmts.c
951=== modified file 'gcc/tree-vect-stmts.c' 947===================================================================
952--- old/gcc/tree-vect-stmts.c 2011-06-22 06:21:13 +0000 948--- gcc-4_6-branch.orig/gcc/tree-vect-stmts.c 2011-09-16 20:31:52.000000000 -0700
953+++ new/gcc/tree-vect-stmts.c 2011-07-06 12:04:10 +0000 949+++ gcc-4_6-branch/gcc/tree-vect-stmts.c 2011-09-16 20:32:57.289056641 -0700
954@@ -126,33 +126,72 @@ 950@@ -126,33 +126,72 @@
955 951
956 static void 952 static void
@@ -974,21 +970,6 @@
974 if (STMT_VINFO_IN_PATTERN_P (stmt_info)) 970 if (STMT_VINFO_IN_PATTERN_P (stmt_info))
975 { 971 {
976- gimple pattern_stmt; 972- gimple pattern_stmt;
977-
978- /* This is the last stmt in a sequence that was detected as a
979- pattern that can potentially be vectorized. Don't mark the stmt
980- as relevant/live because it's not going to be vectorized.
981- Instead mark the pattern-stmt that replaces it. */
982-
983- pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
984-
985- if (vect_print_dump_info (REPORT_DETAILS))
986- fprintf (vect_dump, "last stmt in pattern. don't mark relevant/live.");
987- stmt_info = vinfo_for_stmt (pattern_stmt);
988- gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
989- save_relevant = STMT_VINFO_RELEVANT (stmt_info);
990- save_live_p = STMT_VINFO_LIVE_P (stmt_info);
991- stmt = pattern_stmt;
992+ bool found = false; 973+ bool found = false;
993+ if (!used_in_pattern) 974+ if (!used_in_pattern)
994+ { 975+ {
@@ -1026,7 +1007,21 @@
1026+ pattern that can potentially be vectorized. Don't mark the stmt 1007+ pattern that can potentially be vectorized. Don't mark the stmt
1027+ as relevant/live because it's not going to be vectorized. 1008+ as relevant/live because it's not going to be vectorized.
1028+ Instead mark the pattern-stmt that replaces it. */ 1009+ Instead mark the pattern-stmt that replaces it. */
1029+ 1010
1011- /* This is the last stmt in a sequence that was detected as a
1012- pattern that can potentially be vectorized. Don't mark the stmt
1013- as relevant/live because it's not going to be vectorized.
1014- Instead mark the pattern-stmt that replaces it. */
1015-
1016- pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1017-
1018- if (vect_print_dump_info (REPORT_DETAILS))
1019- fprintf (vect_dump, "last stmt in pattern. don't mark relevant/live.");
1020- stmt_info = vinfo_for_stmt (pattern_stmt);
1021- gcc_assert (STMT_VINFO_RELATED_STMT (stmt_info) == stmt);
1022- save_relevant = STMT_VINFO_RELEVANT (stmt_info);
1023- save_live_p = STMT_VINFO_LIVE_P (stmt_info);
1024- stmt = pattern_stmt;
1030+ pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info); 1025+ pattern_stmt = STMT_VINFO_RELATED_STMT (stmt_info);
1031+ 1026+
1032+ if (vect_print_dump_info (REPORT_DETAILS)) 1027+ if (vect_print_dump_info (REPORT_DETAILS))
@@ -1119,9 +1114,6 @@
1119- VEC_free (gimple, heap, worklist); 1114- VEC_free (gimple, heap, worklist);
1120- return false; 1115- return false;
1121- } 1116- }
1122- }
1123- else
1124- return false;
1125+ break; 1117+ break;
1126+ 1118+
1127+ case GIMPLE_BINARY_RHS: 1119+ case GIMPLE_BINARY_RHS:
@@ -1154,7 +1146,9 @@
1154+ 1146+
1155+ default: 1147+ default:
1156+ return false; 1148+ return false;
1157+ } 1149 }
1150- else
1151- return false;
1158 } 1152 }
1159 else if (is_gimple_call (stmt)) 1153 else if (is_gimple_call (stmt))
1160 { 1154 {
@@ -1173,7 +1167,7 @@
1173 gcc_assert (vec_stmt); 1167 gcc_assert (vec_stmt);
1174 if (gimple_code (vec_stmt) == GIMPLE_PHI) 1168 if (gimple_code (vec_stmt) == GIMPLE_PHI)
1175 vec_oprnd = PHI_RESULT (vec_stmt); 1169 vec_oprnd = PHI_RESULT (vec_stmt);
1176@@ -4886,6 +4946,7 @@ 1170@@ -4894,6 +4954,7 @@
1177 enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info); 1171 enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
1178 bool ok; 1172 bool ok;
1179 tree scalar_type, vectype; 1173 tree scalar_type, vectype;
@@ -1181,14 +1175,13 @@
1181 1175
1182 if (vect_print_dump_info (REPORT_DETAILS)) 1176 if (vect_print_dump_info (REPORT_DETAILS))
1183 { 1177 {
1184@@ -4907,16 +4968,22 @@ 1178@@ -4915,16 +4976,22 @@
1185 - any LABEL_EXPRs in the loop 1179 - any LABEL_EXPRs in the loop
1186 - computations that are used only for array indexing or loop control. 1180 - computations that are used only for array indexing or loop control.
1187 In basic blocks we only analyze statements that are a part of some SLP 1181 In basic blocks we only analyze statements that are a part of some SLP
1188- instance, therefore, all the statements are relevant. */ 1182- instance, therefore, all the statements are relevant. */
1189-
1190+ instance, therefore, all the statements are relevant. 1183+ instance, therefore, all the statements are relevant.
1191+ 1184
1192+ Pattern statement need to be analyzed instead of the original statement 1185+ Pattern statement need to be analyzed instead of the original statement
1193+ if the original statement is not relevant. Otherwise, we analyze both 1186+ if the original statement is not relevant. Otherwise, we analyze both
1194+ statements. */ 1187+ statements. */
@@ -1207,7 +1200,7 @@
1207 stmt = pattern_stmt; 1200 stmt = pattern_stmt;
1208 stmt_info = vinfo_for_stmt (pattern_stmt); 1201 stmt_info = vinfo_for_stmt (pattern_stmt);
1209 if (vect_print_dump_info (REPORT_DETAILS)) 1202 if (vect_print_dump_info (REPORT_DETAILS))
1210@@ -4933,6 +5000,21 @@ 1203@@ -4941,6 +5008,21 @@
1211 return true; 1204 return true;
1212 } 1205 }
1213 } 1206 }
@@ -1229,42 +1222,7 @@
1229 1222
1230 switch (STMT_VINFO_DEF_TYPE (stmt_info)) 1223 switch (STMT_VINFO_DEF_TYPE (stmt_info))
1231 { 1224 {
1232@@ -5066,7 +5148,6 @@ 1225@@ -5605,8 +5687,12 @@
1233 bool is_store = false;
1234 gimple vec_stmt = NULL;
1235 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
1236- gimple orig_stmt_in_pattern, orig_scalar_stmt = stmt;
1237 bool done;
1238
1239 switch (STMT_VINFO_TYPE (stmt_info))
1240@@ -5205,25 +5286,7 @@
1241 }
1242
1243 if (vec_stmt)
1244- {
1245- STMT_VINFO_VEC_STMT (stmt_info) = vec_stmt;
1246- orig_stmt_in_pattern = STMT_VINFO_RELATED_STMT (stmt_info);
1247- if (orig_stmt_in_pattern)
1248- {
1249- stmt_vec_info stmt_vinfo = vinfo_for_stmt (orig_stmt_in_pattern);
1250- /* STMT was inserted by the vectorizer to replace a computation idiom.
1251- ORIG_STMT_IN_PATTERN is a stmt in the original sequence that
1252- computed this idiom. We need to record a pointer to VEC_STMT in
1253- the stmt_info of ORIG_STMT_IN_PATTERN. See more details in the
1254- documentation of vect_pattern_recog. */
1255- if (STMT_VINFO_IN_PATTERN_P (stmt_vinfo))
1256- {
1257- gcc_assert (STMT_VINFO_RELATED_STMT (stmt_vinfo)
1258- == orig_scalar_stmt);
1259- STMT_VINFO_VEC_STMT (stmt_vinfo) = vec_stmt;
1260- }
1261- }
1262- }
1263+ STMT_VINFO_VEC_STMT (stmt_info) = vec_stmt;
1264
1265 return is_store;
1266 }
1267@@ -5601,8 +5664,12 @@
1268 || *dt == vect_nested_cycle) 1226 || *dt == vect_nested_cycle)
1269 { 1227 {
1270 stmt_vec_info stmt_info = vinfo_for_stmt (*def_stmt); 1228 stmt_vec_info stmt_info = vinfo_for_stmt (*def_stmt);
@@ -1278,10 +1236,10 @@
1278 *vectype = STMT_VINFO_VECTYPE (stmt_info); 1236 *vectype = STMT_VINFO_VECTYPE (stmt_info);
1279 gcc_assert (*vectype != NULL_TREE); 1237 gcc_assert (*vectype != NULL_TREE);
1280 } 1238 }
1281 1239Index: gcc-4_6-branch/gcc/tree-vectorizer.h
1282=== modified file 'gcc/tree-vectorizer.h' 1240===================================================================
1283--- old/gcc/tree-vectorizer.h 2011-07-04 11:13:51 +0000 1241--- gcc-4_6-branch.orig/gcc/tree-vectorizer.h 2011-09-16 20:31:52.000000000 -0700
1284+++ new/gcc/tree-vectorizer.h 2011-07-11 11:02:55 +0000 1242+++ gcc-4_6-branch/gcc/tree-vectorizer.h 2011-09-16 20:32:57.299056515 -0700
1285@@ -890,7 +890,7 @@ 1243@@ -890,7 +890,7 @@
1286 /* Pattern recognition functions. 1244 /* Pattern recognition functions.
1287 Additional pattern recognition functions can (and will) be added 1245 Additional pattern recognition functions can (and will) be added
@@ -1291,4 +1249,3 @@
1291 #define NUM_PATTERNS 4 1249 #define NUM_PATTERNS 4
1292 void vect_pattern_recog (loop_vec_info); 1250 void vect_pattern_recog (loop_vec_info);
1293 1251
1294
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
new file mode 100644
index 0000000000..61e3916375
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106783.patch
@@ -0,0 +1,62 @@
12011-07-31 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r176970:
5
6 * modulo-sched.c: Change comment.
7 (reset_sched_times): Fix print message.
8 (print_partial_schedule): Add print info.
9
10=== modified file 'gcc/modulo-sched.c'
11--- old/gcc/modulo-sched.c 2011-07-04 12:01:34 +0000
12+++ new/gcc/modulo-sched.c 2011-07-31 10:58:46 +0000
13@@ -84,13 +84,14 @@
14 II cycles (i.e. use register copies to prevent a def from overwriting
15 itself before reaching the use).
16
17- SMS works with countable loops whose loop count can be easily
18- adjusted. This is because we peel a constant number of iterations
19- into a prologue and epilogue for which we want to avoid emitting
20- the control part, and a kernel which is to iterate that constant
21- number of iterations less than the original loop. So the control
22- part should be a set of insns clearly identified and having its
23- own iv, not otherwise used in the loop (at-least for now), which
24+ SMS works with countable loops (1) whose control part can be easily
25+ decoupled from the rest of the loop and (2) whose loop count can
26+ be easily adjusted. This is because we peel a constant number of
27+ iterations into a prologue and epilogue for which we want to avoid
28+ emitting the control part, and a kernel which is to iterate that
29+ constant number of iterations less than the original loop. So the
30+ control part should be a set of insns clearly identified and having
31+ its own iv, not otherwise used in the loop (at-least for now), which
32 initializes a register before the loop to the number of iterations.
33 Currently SMS relies on the do-loop pattern to recognize such loops,
34 where (1) the control part comprises of all insns defining and/or
35@@ -598,8 +599,8 @@
36 /* Print the scheduling times after the rotation. */
37 fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
38 "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
39- INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
40- normalized_time);
41+ INSN_UID (crr_insn->node->insn), normalized_time,
42+ new_min_cycle);
43 if (JUMP_P (crr_insn->node->insn))
44 fprintf (dump_file, " (branch)");
45 fprintf (dump_file, "\n");
46@@ -2550,8 +2551,13 @@
47 fprintf (dump, "\n[ROW %d ]: ", i);
48 while (ps_i)
49 {
50- fprintf (dump, "%d, ",
51- INSN_UID (ps_i->node->insn));
52+ if (JUMP_P (ps_i->node->insn))
53+ fprintf (dump, "%d (branch), ",
54+ INSN_UID (ps_i->node->insn));
55+ else
56+ fprintf (dump, "%d, ",
57+ INSN_UID (ps_i->node->insn));
58+
59 ps_i = ps_i->next_in_row;
60 }
61 }
62
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
new file mode 100644
index 0000000000..b82fe76d41
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106784.patch
@@ -0,0 +1,458 @@
12011-08-09 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r177235.
5 * modulo-sched.c (calculate_stage_count,
6 calculate_must_precede_follow, get_sched_window,
7 try_scheduling_node_in_cycle, remove_node_from_ps):
8 Add declaration.
9 (update_node_sched_params, set_must_precede_follow, optimize_sc):
10 New functions.
11 (reset_sched_times): Call update_node_sched_params.
12 (sms_schedule): Call optimize_sc.
13 (get_sched_window): Change function arguments.
14 (sms_schedule_by_order): Update call to get_sched_window.
15 Call set_must_precede_follow.
16 (calculate_stage_count): Add function argument.
17
18=== modified file 'gcc/modulo-sched.c'
19--- old/gcc/modulo-sched.c 2011-07-31 10:58:46 +0000
20+++ new/gcc/modulo-sched.c 2011-08-09 04:51:48 +0000
21@@ -203,7 +203,16 @@
22 rtx, rtx);
23 static void duplicate_insns_of_cycles (partial_schedule_ptr,
24 int, int, int, rtx);
25-static int calculate_stage_count (partial_schedule_ptr ps);
26+static int calculate_stage_count (partial_schedule_ptr, int);
27+static void calculate_must_precede_follow (ddg_node_ptr, int, int,
28+ int, int, sbitmap, sbitmap, sbitmap);
29+static int get_sched_window (partial_schedule_ptr, ddg_node_ptr,
30+ sbitmap, int, int *, int *, int *);
31+static bool try_scheduling_node_in_cycle (partial_schedule_ptr, ddg_node_ptr,
32+ int, int, sbitmap, int *, sbitmap,
33+ sbitmap);
34+static bool remove_node_from_ps (partial_schedule_ptr, ps_insn_ptr);
35+
36 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
37 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
38 #define SCHED_FIRST_REG_MOVE(x) \
39@@ -577,6 +586,36 @@
40 }
41 }
42
43+/* Update the sched_params (time, row and stage) for node U using the II,
44+ the CYCLE of U and MIN_CYCLE.
45+ We're not simply taking the following
46+ SCHED_STAGE (u) = CALC_STAGE_COUNT (SCHED_TIME (u), min_cycle, ii);
47+ because the stages may not be aligned on cycle 0. */
48+static void
49+update_node_sched_params (ddg_node_ptr u, int ii, int cycle, int min_cycle)
50+{
51+ int sc_until_cycle_zero;
52+ int stage;
53+
54+ SCHED_TIME (u) = cycle;
55+ SCHED_ROW (u) = SMODULO (cycle, ii);
56+
57+ /* The calculation of stage count is done adding the number
58+ of stages before cycle zero and after cycle zero. */
59+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, min_cycle, ii);
60+
61+ if (SCHED_TIME (u) < 0)
62+ {
63+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
64+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
65+ }
66+ else
67+ {
68+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
69+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
70+ }
71+}
72+
73 /* Bump the SCHED_TIMEs of all nodes by AMOUNT. Set the values of
74 SCHED_ROW and SCHED_STAGE. */
75 static void
76@@ -592,7 +631,6 @@
77 ddg_node_ptr u = crr_insn->node;
78 int normalized_time = SCHED_TIME (u) - amount;
79 int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
80- int sc_until_cycle_zero, stage;
81
82 if (dump_file)
83 {
84@@ -608,23 +646,9 @@
85
86 gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
87 gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
88- SCHED_TIME (u) = normalized_time;
89- SCHED_ROW (u) = SMODULO (normalized_time, ii);
90-
91- /* The calculation of stage count is done adding the number
92- of stages before cycle zero and after cycle zero. */
93- sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
94-
95- if (SCHED_TIME (u) < 0)
96- {
97- stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
98- SCHED_STAGE (u) = sc_until_cycle_zero - stage;
99- }
100- else
101- {
102- stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
103- SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
104- }
105+
106+ crr_insn->cycle = normalized_time;
107+ update_node_sched_params (u, ii, normalized_time, new_min_cycle);
108 }
109 }
110
111@@ -661,6 +685,206 @@
112 PREV_INSN (last));
113 }
114
115+/* Set bitmaps TMP_FOLLOW and TMP_PRECEDE to MUST_FOLLOW and MUST_PRECEDE
116+ respectively only if cycle C falls on the border of the scheduling
117+ window boundaries marked by START and END cycles. STEP is the
118+ direction of the window. */
119+static inline void
120+set_must_precede_follow (sbitmap *tmp_follow, sbitmap must_follow,
121+ sbitmap *tmp_precede, sbitmap must_precede, int c,
122+ int start, int end, int step)
123+{
124+ *tmp_precede = NULL;
125+ *tmp_follow = NULL;
126+
127+ if (c == start)
128+ {
129+ if (step == 1)
130+ *tmp_precede = must_precede;
131+ else /* step == -1. */
132+ *tmp_follow = must_follow;
133+ }
134+ if (c == end - step)
135+ {
136+ if (step == 1)
137+ *tmp_follow = must_follow;
138+ else /* step == -1. */
139+ *tmp_precede = must_precede;
140+ }
141+
142+}
143+
144+/* Return True if the branch can be moved to row ii-1 while
145+ normalizing the partial schedule PS to start from cycle zero and thus
146+ optimize the SC. Otherwise return False. */
147+static bool
148+optimize_sc (partial_schedule_ptr ps, ddg_ptr g)
149+{
150+ int amount = PS_MIN_CYCLE (ps);
151+ sbitmap sched_nodes = sbitmap_alloc (g->num_nodes);
152+ int start, end, step;
153+ int ii = ps->ii;
154+ bool ok = false;
155+ int stage_count, stage_count_curr;
156+
157+ /* Compare the SC after normalization and SC after bringing the branch
158+ to row ii-1. If they are equal just bail out. */
159+ stage_count = calculate_stage_count (ps, amount);
160+ stage_count_curr =
161+ calculate_stage_count (ps, SCHED_TIME (g->closing_branch) - (ii - 1));
162+
163+ if (stage_count == stage_count_curr)
164+ {
165+ if (dump_file)
166+ fprintf (dump_file, "SMS SC already optimized.\n");
167+
168+ ok = false;
169+ goto clear;
170+ }
171+
172+ if (dump_file)
173+ {
174+ fprintf (dump_file, "SMS Trying to optimize branch location\n");
175+ fprintf (dump_file, "SMS partial schedule before trial:\n");
176+ print_partial_schedule (ps, dump_file);
177+ }
178+
179+ /* First, normalize the partial scheduling. */
180+ reset_sched_times (ps, amount);
181+ rotate_partial_schedule (ps, amount);
182+ if (dump_file)
183+ {
184+ fprintf (dump_file,
185+ "SMS partial schedule after normalization (ii, %d, SC %d):\n",
186+ ii, stage_count);
187+ print_partial_schedule (ps, dump_file);
188+ }
189+
190+ if (SMODULO (SCHED_TIME (g->closing_branch), ii) == ii - 1)
191+ {
192+ ok = true;
193+ goto clear;
194+ }
195+
196+ sbitmap_ones (sched_nodes);
197+
198+ /* Calculate the new placement of the branch. It should be in row
199+ ii-1 and fall into it's scheduling window. */
200+ if (get_sched_window (ps, g->closing_branch, sched_nodes, ii, &start,
201+ &step, &end) == 0)
202+ {
203+ bool success;
204+ ps_insn_ptr next_ps_i;
205+ int branch_cycle = SCHED_TIME (g->closing_branch);
206+ int row = SMODULO (branch_cycle, ps->ii);
207+ int num_splits = 0;
208+ sbitmap must_precede, must_follow, tmp_precede, tmp_follow;
209+ int c;
210+
211+ if (dump_file)
212+ fprintf (dump_file, "\nTrying to schedule node %d "
213+ "INSN = %d in (%d .. %d) step %d\n",
214+ g->closing_branch->cuid,
215+ (INSN_UID (g->closing_branch->insn)), start, end, step);
216+
217+ gcc_assert ((step > 0 && start < end) || (step < 0 && start > end));
218+ if (step == 1)
219+ {
220+ c = start + ii - SMODULO (start, ii) - 1;
221+ gcc_assert (c >= start);
222+ if (c >= end)
223+ {
224+ ok = false;
225+ if (dump_file)
226+ fprintf (dump_file,
227+ "SMS failed to schedule branch at cycle: %d\n", c);
228+ goto clear;
229+ }
230+ }
231+ else
232+ {
233+ c = start - SMODULO (start, ii) - 1;
234+ gcc_assert (c <= start);
235+
236+ if (c <= end)
237+ {
238+ if (dump_file)
239+ fprintf (dump_file,
240+ "SMS failed to schedule branch at cycle: %d\n", c);
241+ ok = false;
242+ goto clear;
243+ }
244+ }
245+
246+ must_precede = sbitmap_alloc (g->num_nodes);
247+ must_follow = sbitmap_alloc (g->num_nodes);
248+
249+ /* Try to schedule the branch is it's new cycle. */
250+ calculate_must_precede_follow (g->closing_branch, start, end,
251+ step, ii, sched_nodes,
252+ must_precede, must_follow);
253+
254+ set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
255+ must_precede, c, start, end, step);
256+
257+ /* Find the element in the partial schedule related to the closing
258+ branch so we can remove it from it's current cycle. */
259+ for (next_ps_i = ps->rows[row];
260+ next_ps_i; next_ps_i = next_ps_i->next_in_row)
261+ if (next_ps_i->node->cuid == g->closing_branch->cuid)
262+ break;
263+
264+ gcc_assert (next_ps_i);
265+ gcc_assert (remove_node_from_ps (ps, next_ps_i));
266+ success =
267+ try_scheduling_node_in_cycle (ps, g->closing_branch,
268+ g->closing_branch->cuid, c,
269+ sched_nodes, &num_splits,
270+ tmp_precede, tmp_follow);
271+ gcc_assert (num_splits == 0);
272+ if (!success)
273+ {
274+ if (dump_file)
275+ fprintf (dump_file,
276+ "SMS failed to schedule branch at cycle: %d, "
277+ "bringing it back to cycle %d\n", c, branch_cycle);
278+
279+ /* The branch was failed to be placed in row ii - 1.
280+ Put it back in it's original place in the partial
281+ schedualing. */
282+ set_must_precede_follow (&tmp_follow, must_follow, &tmp_precede,
283+ must_precede, branch_cycle, start, end,
284+ step);
285+ success =
286+ try_scheduling_node_in_cycle (ps, g->closing_branch,
287+ g->closing_branch->cuid,
288+ branch_cycle, sched_nodes,
289+ &num_splits, tmp_precede,
290+ tmp_follow);
291+ gcc_assert (success && (num_splits == 0));
292+ ok = false;
293+ }
294+ else
295+ {
296+ /* The branch is placed in row ii - 1. */
297+ if (dump_file)
298+ fprintf (dump_file,
299+ "SMS success in moving branch to cycle %d\n", c);
300+
301+ update_node_sched_params (g->closing_branch, ii, c,
302+ PS_MIN_CYCLE (ps));
303+ ok = true;
304+ }
305+
306+ free (must_precede);
307+ free (must_follow);
308+ }
309+
310+clear:
311+ free (sched_nodes);
312+ return ok;
313+}
314+
315 static void
316 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
317 int to_stage, int for_prolog, rtx count_reg)
318@@ -1116,6 +1340,7 @@
319 int mii, rec_mii;
320 unsigned stage_count = 0;
321 HOST_WIDEST_INT loop_count = 0;
322+ bool opt_sc_p = false;
323
324 if (! (g = g_arr[loop->num]))
325 continue;
326@@ -1197,14 +1422,32 @@
327 set_node_sched_params (g);
328
329 ps = sms_schedule_by_order (g, mii, maxii, node_order);
330-
331- if (ps)
332- {
333- stage_count = calculate_stage_count (ps);
334- gcc_assert(stage_count >= 1);
335- PS_STAGE_COUNT(ps) = stage_count;
336- }
337-
338+
339+ if (ps)
340+ {
341+ /* Try to achieve optimized SC by normalizing the partial
342+ schedule (having the cycles start from cycle zero).
343+ The branch location must be placed in row ii-1 in the
344+ final scheduling. If failed, shift all instructions to
345+ position the branch in row ii-1. */
346+ opt_sc_p = optimize_sc (ps, g);
347+ if (opt_sc_p)
348+ stage_count = calculate_stage_count (ps, 0);
349+ else
350+ {
351+ /* Bring the branch to cycle ii-1. */
352+ int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
353+
354+ if (dump_file)
355+ fprintf (dump_file, "SMS schedule branch at cycle ii-1\n");
356+
357+ stage_count = calculate_stage_count (ps, amount);
358+ }
359+
360+ gcc_assert (stage_count >= 1);
361+ PS_STAGE_COUNT (ps) = stage_count;
362+ }
363+
364 /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
365 1 means that there is no interleaving between iterations thus
366 we let the scheduling passes do the job in this case. */
367@@ -1225,12 +1468,16 @@
368 else
369 {
370 struct undo_replace_buff_elem *reg_move_replaces;
371- int amount = SCHED_TIME (g->closing_branch) + 1;
372+
373+ if (!opt_sc_p)
374+ {
375+ /* Rotate the partial schedule to have the branch in row ii-1. */
376+ int amount = SCHED_TIME (g->closing_branch) - (ps->ii - 1);
377+
378+ reset_sched_times (ps, amount);
379+ rotate_partial_schedule (ps, amount);
380+ }
381
382- /* Set the stage boundaries. The closing_branch was scheduled
383- and should appear in the last (ii-1) row. */
384- reset_sched_times (ps, amount);
385- rotate_partial_schedule (ps, amount);
386 set_columns_for_ps (ps);
387
388 canon_loop (loop);
389@@ -1382,13 +1629,11 @@
390 scheduling window is empty and zero otherwise. */
391
392 static int
393-get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
394+get_sched_window (partial_schedule_ptr ps, ddg_node_ptr u_node,
395 sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
396 {
397 int start, step, end;
398 ddg_edge_ptr e;
399- int u = nodes_order [i];
400- ddg_node_ptr u_node = &ps->g->nodes[u];
401 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
402 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
403 sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
404@@ -1800,7 +2045,7 @@
405
406 /* Try to get non-empty scheduling window. */
407 success = 0;
408- if (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start,
409+ if (get_sched_window (ps, u_node, sched_nodes, ii, &start,
410 &step, &end) == 0)
411 {
412 if (dump_file)
413@@ -1817,24 +2062,11 @@
414
415 for (c = start; c != end; c += step)
416 {
417- sbitmap tmp_precede = NULL;
418- sbitmap tmp_follow = NULL;
419-
420- if (c == start)
421- {
422- if (step == 1)
423- tmp_precede = must_precede;
424- else /* step == -1. */
425- tmp_follow = must_follow;
426- }
427- if (c == end - step)
428- {
429- if (step == 1)
430- tmp_follow = must_follow;
431- else /* step == -1. */
432- tmp_precede = must_precede;
433- }
434-
435+ sbitmap tmp_precede, tmp_follow;
436+
437+ set_must_precede_follow (&tmp_follow, must_follow,
438+ &tmp_precede, must_precede,
439+ c, start, end, step);
440 success =
441 try_scheduling_node_in_cycle (ps, u_node, u, c,
442 sched_nodes,
443@@ -2899,12 +3131,10 @@
444 }
445
446 /* Calculate the stage count of the partial schedule PS. The calculation
447- takes into account the rotation to bring the closing branch to row
448- ii-1. */
449+ takes into account the rotation amount passed in ROTATION_AMOUNT. */
450 int
451-calculate_stage_count (partial_schedule_ptr ps)
452+calculate_stage_count (partial_schedule_ptr ps, int rotation_amount)
453 {
454- int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
455 int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
456 int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
457 int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
458
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
new file mode 100644
index 0000000000..608dd18336
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106785.patch
@@ -0,0 +1,39 @@
1 2011-08-09 Revital Eres <revital.eres@linaro.org>
2
3 gcc/
4 Backport from trunk -r176972:
5
6 * ddg.c (create_ddg_dep_from_intra_loop_link): Remove
7 the creation of anti-dep edge from a branch.
8 (add_cross_iteration_register_deps):
9 Create anti-dep edge from a branch.
10
11=== modified file 'gcc/ddg.c'
12--- old/gcc/ddg.c 2011-07-04 11:00:06 +0000
13+++ new/gcc/ddg.c 2011-07-31 11:29:10 +0000
14@@ -197,11 +197,6 @@
15 }
16 }
17
18- /* If a true dep edge enters the branch create an anti edge in the
19- opposite direction to prevent the creation of reg-moves. */
20- if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
21- create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
22-
23 latency = dep_cost (link);
24 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
25 add_edge_to_ddg (g, e);
26@@ -306,8 +301,11 @@
27
28 gcc_assert (first_def_node);
29
30+ /* Always create the edge if the use node is a branch in
31+ order to prevent the creation of reg-moves. */
32 if (DF_REF_ID (last_def) != DF_REF_ID (first_def)
33- || !flag_modulo_sched_allow_regmoves)
34+ || !flag_modulo_sched_allow_regmoves
35+ || JUMP_P (use_node->insn))
36 create_ddg_dep_no_link (g, use_node, first_def_node, ANTI_DEP,
37 REG_DEP, 1);
38
39
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
new file mode 100644
index 0000000000..55b7cc1078
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106786.patch
@@ -0,0 +1,94 @@
12011-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-07-28 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 * config/arm/vfp.md ("*movdf_vfp"): Handle the VFP constraints
9 before the core constraints. Adjust attributes.
10 (*thumb2_movdf_vfp"): Likewise.
11
12=== modified file 'gcc/config/arm/vfp.md'
13--- old/gcc/config/arm/vfp.md 2011-01-20 22:03:29 +0000
14+++ new/gcc/config/arm/vfp.md 2011-07-27 12:59:19 +0000
15@@ -401,8 +401,8 @@
16 ;; DFmode moves
17
18 (define_insn "*movdf_vfp"
19- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
20- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
21+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r, m,w,r")
22+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w ,mF,r,w,r"))]
23 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
24 && ( register_operand (operands[0], DFmode)
25 || register_operand (operands[1], DFmode))"
26@@ -418,9 +418,9 @@
27 gcc_assert (TARGET_VFP_DOUBLE);
28 return \"fconstd%?\\t%P0, #%G1\";
29 case 3: case 4:
30+ return output_move_vfp (operands);
31+ case 5: case 6:
32 return output_move_double (operands);
33- case 5: case 6:
34- return output_move_vfp (operands);
35 case 7:
36 if (TARGET_VFP_SINGLE)
37 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
38@@ -435,7 +435,7 @@
39 "
40 [(set_attr "type"
41 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
42- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
43+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
44 (eq_attr "alternative" "7")
45 (if_then_else
46 (eq (symbol_ref "TARGET_VFP_SINGLE")
47@@ -449,8 +449,8 @@
48 )
49
50 (define_insn "*thumb2_movdf_vfp"
51- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
52- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
53+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w ,Uv,r ,m,w,r")
54+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,UvF,w, mF,r, w,r"))]
55 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
56 "*
57 {
58@@ -463,10 +463,10 @@
59 case 2:
60 gcc_assert (TARGET_VFP_DOUBLE);
61 return \"fconstd%?\\t%P0, #%G1\";
62- case 3: case 4: case 8:
63+ case 3: case 4:
64+ return output_move_vfp (operands);
65+ case 5: case 6: case 8:
66 return output_move_double (operands);
67- case 5: case 6:
68- return output_move_vfp (operands);
69 case 7:
70 if (TARGET_VFP_SINGLE)
71 return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
72@@ -478,8 +478,8 @@
73 }
74 "
75 [(set_attr "type"
76- "r_2_f,f_2_r,fconstd,load2,store2,f_loadd,f_stored,ffarithd,*")
77- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
78+ "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
79+ (set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
80 (eq_attr "alternative" "7")
81 (if_then_else
82 (eq (symbol_ref "TARGET_VFP_SINGLE")
83@@ -487,8 +487,8 @@
84 (const_int 8)
85 (const_int 4))]
86 (const_int 4)))
87- (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
88- (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
89+ (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
90+ (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
91 )
92
93
94
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
new file mode 100644
index 0000000000..bdb48ad1e6
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106787.patch
@@ -0,0 +1,30 @@
12011-08-15 Michael Hope <michael.hope@linaro.org>
2
3 Backport from mainline r177357
4
5 gcc/testsuite/
6 2011-08-04 Ian Bolton <ian.bolton@arm.com>
7
8 * gcc.target/arm/vfp-1.c: no large negative offsets on Thumb2.
9
10=== modified file 'gcc/testsuite/gcc.target/arm/vfp-1.c'
11--- old/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-01-01 08:52:03 +0000
12+++ new/gcc/testsuite/gcc.target/arm/vfp-1.c 2011-08-09 23:22:51 +0000
13@@ -127,13 +127,13 @@
14
15 void test_ldst (float f[], double d[]) {
16 /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
17- /* { dg-final { scan-assembler "flds.+ \\\[r0, #-1020\\\]" } } */
18+ /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
19 /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
20- /* { dg-final { scan-assembler "fsts.+ \\\[r0, #0\\\]\n" } } */
21+ /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */
22 f[256] = f[255] + f[-255];
23
24 /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
25- /* { dg-final { scan-assembler "fldd.+ \\\[r1, #-1016\\\]" } } */
26+ /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
27 /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
28 d[32] = d[127] + d[-127];
29 }
30
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
new file mode 100644
index 0000000000..a384ce7a18
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106789.patch
@@ -0,0 +1,33 @@
12011-08-15 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 * config/rs6000/rs6000.c (paired_expand_vector_init): Don't create
5 CONST_VECTORs with symbolic elements.
6 (rs6000_expand_vector_init): Likewise.
7
8=== modified file 'gcc/config/rs6000/rs6000.c'
9--- old/gcc/config/rs6000/rs6000.c 2011-07-27 18:17:15 +0000
10+++ new/gcc/config/rs6000/rs6000.c 2011-08-16 08:59:36 +0000
11@@ -5134,7 +5134,9 @@
12 for (i = 0; i < n_elts; ++i)
13 {
14 x = XVECEXP (vals, 0, i);
15- if (!CONSTANT_P (x))
16+ if (!(CONST_INT_P (x)
17+ || GET_CODE (x) == CONST_DOUBLE
18+ || GET_CODE (x) == CONST_FIXED))
19 ++n_var;
20 }
21 if (n_var == 0)
22@@ -5286,7 +5288,9 @@
23 for (i = 0; i < n_elts; ++i)
24 {
25 x = XVECEXP (vals, 0, i);
26- if (!CONSTANT_P (x))
27+ if (!(CONST_INT_P (x)
28+ || GET_CODE (x) == CONST_DOUBLE
29+ || GET_CODE (x) == CONST_FIXED))
30 ++n_var, one_var = i;
31 else if (x != CONST0_RTX (inner_mode))
32 all_const_zero = false;
33
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
new file mode 100644
index 0000000000..12c578c2b4
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106792.patch
@@ -0,0 +1,61 @@
12011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-08-12 Richard Sandiford <rdsandiford@googlemail.com>
7
8 * config/arm/arm.c (get_label_padding): New function.
9 (create_fix_barrier, arm_reorg): Use it.
10
11=== modified file 'gcc/config/arm/arm.c'
12--- old/gcc/config/arm/arm.c 2011-07-04 14:03:49 +0000
13+++ new/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
14@@ -11769,6 +11769,19 @@
15 return 0;
16 }
17
18+/* Return the maximum amount of padding that will be inserted before
19+ label LABEL. */
20+
21+static HOST_WIDE_INT
22+get_label_padding (rtx label)
23+{
24+ HOST_WIDE_INT align, min_insn_size;
25+
26+ align = 1 << label_to_alignment (label);
27+ min_insn_size = TARGET_THUMB ? 2 : 4;
28+ return align > min_insn_size ? align - min_insn_size : 0;
29+}
30+
31 /* Move a minipool fix MP from its current location to before MAX_MP.
32 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
33 constraints may need updating. */
34@@ -12315,8 +12328,12 @@
35 within range. */
36 gcc_assert (GET_CODE (from) != BARRIER);
37
38- /* Count the length of this insn. */
39- count += get_attr_length (from);
40+ /* Count the length of this insn. This must stay in sync with the
41+ code that pushes minipool fixes. */
42+ if (LABEL_P (from))
43+ count += get_label_padding (from);
44+ else
45+ count += get_attr_length (from);
46
47 /* If there is a jump table, add its length. */
48 tmp = is_jump_table (from);
49@@ -12736,6 +12753,11 @@
50 insn = table;
51 }
52 }
53+ else if (LABEL_P (insn))
54+ /* Add the worst-case padding due to alignment. We don't add
55+ the _current_ padding because the minipool insertions
56+ themselves might change it. */
57+ address += get_label_padding (insn);
58 }
59
60 fix = minipool_fix_head;
61
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106793.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106793.patch
new file mode 100644
index 0000000000..04dabaf604
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106793.patch
@@ -0,0 +1,34 @@
12011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-08-18 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * config/arm/arm.c (arm_rtx_costs_1): Don't modify the costs of SET.
9 (arm_size_rtx_costs): Likewise.
10
11=== modified file 'gcc/config/arm/arm.c'
12--- old/gcc/config/arm/arm.c 2011-08-12 08:08:31 +0000
13+++ new/gcc/config/arm/arm.c 2011-08-18 13:53:37 +0000
14@@ -7464,6 +7464,9 @@
15 *total = COSTS_N_INSNS (4);
16 return true;
17
18+ case SET:
19+ return false;
20+
21 default:
22 *total = COSTS_N_INSNS (4);
23 return false;
24@@ -7811,6 +7814,9 @@
25 *total = COSTS_N_INSNS (1) + 1;
26 return true;
27
28+ case SET:
29+ return false;
30+
31 default:
32 if (mode != VOIDmode)
33 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
34
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
new file mode 100644
index 0000000000..29663c64a0
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106794.patch
@@ -0,0 +1,2648 @@
12011-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4 * config/arm/arm.c (arm_init_neon_builtins): Use
5 n_operands instead of n_generator_args.
6
72011-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
8
9 Backport from mainline
10 2011-04-18 Jie Zhang <jie@codesourcery.com>
11 Richard Earnshaw <rearnsha@arm.com>
12
13 * arm.c (neon_builtin_type_bits): Remove.
14 (typedef enum neon_builtin_mode): New.
15 (T_MAX): Don't define.
16 (typedef enum neon_builtin_datum): Remove bits, codes[],
17 num_vars and base_fcode. Add mode, code and fcode.
18 (VAR1, VAR2, VAR3, VAR4, VAR5, VAR6, VAR7, VAR8, VAR9
19 VAR10): Change accordingly.
20 (neon_builtin_data[]): Change accordingly
21 (arm_init_neon_builtins): Change accordingly.
22 (neon_builtin_compare): Remove.
23 (locate_neon_builtin_icode): Remove.
24 (arm_expand_neon_builtin): Change accordingly.
25
26 * arm.h (enum arm_builtins): Move to ...
27 * arm.c (enum arm_builtins): ... here; and rearrange builtin code.
28
29 * arm.c (arm_builtin_decl): Declare.
30 (TARGET_BUILTIN_DECL): Define.
31 (enum arm_builtins): Correct ARM_BUILTIN_MAX.
32 (arm_builtin_decls[]): New.
33 (arm_init_neon_builtins): Store builtin declarations in
34 arm_builtin_decls[].
35 (arm_init_tls_builtins): Likewise.
36 (arm_init_iwmmxt_builtins): Likewise. Refactor initialization code.
37 (arm_builtin_decl): New.
38
39=== modified file 'gcc/config/arm/arm.c'
40--- old/gcc/config/arm/arm.c 2011-08-18 13:53:37 +0000
41+++ new/gcc/config/arm/arm.c 2011-08-24 17:35:16 +0000
42@@ -162,6 +162,7 @@
43 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
44 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
45 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
46+static tree arm_builtin_decl (unsigned, bool);
47 static void emit_constant_insn (rtx cond, rtx pattern);
48 static rtx emit_set_insn (rtx, rtx);
49 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
50@@ -415,6 +416,8 @@
51 #define TARGET_INIT_BUILTINS arm_init_builtins
52 #undef TARGET_EXPAND_BUILTIN
53 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
54+#undef TARGET_BUILTIN_DECL
55+#define TARGET_BUILTIN_DECL arm_builtin_decl
56
57 #undef TARGET_INIT_LIBFUNCS
58 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
59@@ -18147,505 +18150,31 @@
60 return value;
61 }
62
63-#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
64- do \
65- { \
66- if ((MASK) & insn_flags) \
67- add_builtin_function ((NAME), (TYPE), (CODE), \
68- BUILT_IN_MD, NULL, NULL_TREE); \
69- } \
70- while (0)
71-
72-struct builtin_description
73-{
74- const unsigned int mask;
75- const enum insn_code icode;
76- const char * const name;
77- const enum arm_builtins code;
78- const enum rtx_code comparison;
79- const unsigned int flag;
80-};
81-
82-static const struct builtin_description bdesc_2arg[] =
83-{
84-#define IWMMXT_BUILTIN(code, string, builtin) \
85- { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
86- ARM_BUILTIN_##builtin, UNKNOWN, 0 },
87-
88- IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
89- IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
90- IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
91- IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
92- IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
93- IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
94- IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
95- IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
96- IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
97- IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
98- IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
99- IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
100- IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
101- IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
102- IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
103- IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
104- IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
105- IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
106- IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
107- IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
108- IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
109- IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
110- IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
111- IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
112- IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
113- IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
114- IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
115- IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
116- IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
117- IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
118- IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
119- IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
120- IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
121- IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
122- IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
123- IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
124- IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
125- IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
126- IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
127- IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
128- IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
129- IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
130- IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
131- IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
132- IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
133- IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
134- IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
135- IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
136- IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
137- IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
138- IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
139- IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
140- IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
141- IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
142- IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
143- IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
144- IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
145- IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
146-
147-#define IWMMXT_BUILTIN2(code, builtin) \
148- { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
149-
150- IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
151- IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
152- IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
153- IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
154- IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
155- IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
156- IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
157- IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
158- IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
159- IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
160- IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
161- IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
162- IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
163- IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
164- IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
165- IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
166- IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
167- IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
168- IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
169- IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
170- IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
171- IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
172- IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
173- IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
174- IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
175- IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
176- IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
177- IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
178- IWMMXT_BUILTIN2 (rordi3_di, WRORD)
179- IWMMXT_BUILTIN2 (rordi3, WRORDI)
180- IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
181- IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
182-};
183-
184-static const struct builtin_description bdesc_1arg[] =
185-{
186- IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
187- IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
188- IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
189- IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
190- IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
191- IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
192- IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
193- IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
194- IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
195- IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
196- IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
197- IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
198- IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
199- IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
200- IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
201- IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
202- IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
203- IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
204-};
205-
206-/* Set up all the iWMMXt builtins. This is
207- not called if TARGET_IWMMXT is zero. */
208-
209-static void
210-arm_init_iwmmxt_builtins (void)
211-{
212- const struct builtin_description * d;
213- size_t i;
214- tree endlink = void_list_node;
215-
216- tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
217- tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
218- tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
219-
220- tree int_ftype_int
221- = build_function_type (integer_type_node,
222- tree_cons (NULL_TREE, integer_type_node, endlink));
223- tree v8qi_ftype_v8qi_v8qi_int
224- = build_function_type (V8QI_type_node,
225- tree_cons (NULL_TREE, V8QI_type_node,
226- tree_cons (NULL_TREE, V8QI_type_node,
227- tree_cons (NULL_TREE,
228- integer_type_node,
229- endlink))));
230- tree v4hi_ftype_v4hi_int
231- = build_function_type (V4HI_type_node,
232- tree_cons (NULL_TREE, V4HI_type_node,
233- tree_cons (NULL_TREE, integer_type_node,
234- endlink)));
235- tree v2si_ftype_v2si_int
236- = build_function_type (V2SI_type_node,
237- tree_cons (NULL_TREE, V2SI_type_node,
238- tree_cons (NULL_TREE, integer_type_node,
239- endlink)));
240- tree v2si_ftype_di_di
241- = build_function_type (V2SI_type_node,
242- tree_cons (NULL_TREE, long_long_integer_type_node,
243- tree_cons (NULL_TREE, long_long_integer_type_node,
244- endlink)));
245- tree di_ftype_di_int
246- = build_function_type (long_long_integer_type_node,
247- tree_cons (NULL_TREE, long_long_integer_type_node,
248- tree_cons (NULL_TREE, integer_type_node,
249- endlink)));
250- tree di_ftype_di_int_int
251- = build_function_type (long_long_integer_type_node,
252- tree_cons (NULL_TREE, long_long_integer_type_node,
253- tree_cons (NULL_TREE, integer_type_node,
254- tree_cons (NULL_TREE,
255- integer_type_node,
256- endlink))));
257- tree int_ftype_v8qi
258- = build_function_type (integer_type_node,
259- tree_cons (NULL_TREE, V8QI_type_node,
260- endlink));
261- tree int_ftype_v4hi
262- = build_function_type (integer_type_node,
263- tree_cons (NULL_TREE, V4HI_type_node,
264- endlink));
265- tree int_ftype_v2si
266- = build_function_type (integer_type_node,
267- tree_cons (NULL_TREE, V2SI_type_node,
268- endlink));
269- tree int_ftype_v8qi_int
270- = build_function_type (integer_type_node,
271- tree_cons (NULL_TREE, V8QI_type_node,
272- tree_cons (NULL_TREE, integer_type_node,
273- endlink)));
274- tree int_ftype_v4hi_int
275- = build_function_type (integer_type_node,
276- tree_cons (NULL_TREE, V4HI_type_node,
277- tree_cons (NULL_TREE, integer_type_node,
278- endlink)));
279- tree int_ftype_v2si_int
280- = build_function_type (integer_type_node,
281- tree_cons (NULL_TREE, V2SI_type_node,
282- tree_cons (NULL_TREE, integer_type_node,
283- endlink)));
284- tree v8qi_ftype_v8qi_int_int
285- = build_function_type (V8QI_type_node,
286- tree_cons (NULL_TREE, V8QI_type_node,
287- tree_cons (NULL_TREE, integer_type_node,
288- tree_cons (NULL_TREE,
289- integer_type_node,
290- endlink))));
291- tree v4hi_ftype_v4hi_int_int
292- = build_function_type (V4HI_type_node,
293- tree_cons (NULL_TREE, V4HI_type_node,
294- tree_cons (NULL_TREE, integer_type_node,
295- tree_cons (NULL_TREE,
296- integer_type_node,
297- endlink))));
298- tree v2si_ftype_v2si_int_int
299- = build_function_type (V2SI_type_node,
300- tree_cons (NULL_TREE, V2SI_type_node,
301- tree_cons (NULL_TREE, integer_type_node,
302- tree_cons (NULL_TREE,
303- integer_type_node,
304- endlink))));
305- /* Miscellaneous. */
306- tree v8qi_ftype_v4hi_v4hi
307- = build_function_type (V8QI_type_node,
308- tree_cons (NULL_TREE, V4HI_type_node,
309- tree_cons (NULL_TREE, V4HI_type_node,
310- endlink)));
311- tree v4hi_ftype_v2si_v2si
312- = build_function_type (V4HI_type_node,
313- tree_cons (NULL_TREE, V2SI_type_node,
314- tree_cons (NULL_TREE, V2SI_type_node,
315- endlink)));
316- tree v2si_ftype_v4hi_v4hi
317- = build_function_type (V2SI_type_node,
318- tree_cons (NULL_TREE, V4HI_type_node,
319- tree_cons (NULL_TREE, V4HI_type_node,
320- endlink)));
321- tree v2si_ftype_v8qi_v8qi
322- = build_function_type (V2SI_type_node,
323- tree_cons (NULL_TREE, V8QI_type_node,
324- tree_cons (NULL_TREE, V8QI_type_node,
325- endlink)));
326- tree v4hi_ftype_v4hi_di
327- = build_function_type (V4HI_type_node,
328- tree_cons (NULL_TREE, V4HI_type_node,
329- tree_cons (NULL_TREE,
330- long_long_integer_type_node,
331- endlink)));
332- tree v2si_ftype_v2si_di
333- = build_function_type (V2SI_type_node,
334- tree_cons (NULL_TREE, V2SI_type_node,
335- tree_cons (NULL_TREE,
336- long_long_integer_type_node,
337- endlink)));
338- tree void_ftype_int_int
339- = build_function_type (void_type_node,
340- tree_cons (NULL_TREE, integer_type_node,
341- tree_cons (NULL_TREE, integer_type_node,
342- endlink)));
343- tree di_ftype_void
344- = build_function_type (long_long_unsigned_type_node, endlink);
345- tree di_ftype_v8qi
346- = build_function_type (long_long_integer_type_node,
347- tree_cons (NULL_TREE, V8QI_type_node,
348- endlink));
349- tree di_ftype_v4hi
350- = build_function_type (long_long_integer_type_node,
351- tree_cons (NULL_TREE, V4HI_type_node,
352- endlink));
353- tree di_ftype_v2si
354- = build_function_type (long_long_integer_type_node,
355- tree_cons (NULL_TREE, V2SI_type_node,
356- endlink));
357- tree v2si_ftype_v4hi
358- = build_function_type (V2SI_type_node,
359- tree_cons (NULL_TREE, V4HI_type_node,
360- endlink));
361- tree v4hi_ftype_v8qi
362- = build_function_type (V4HI_type_node,
363- tree_cons (NULL_TREE, V8QI_type_node,
364- endlink));
365-
366- tree di_ftype_di_v4hi_v4hi
367- = build_function_type (long_long_unsigned_type_node,
368- tree_cons (NULL_TREE,
369- long_long_unsigned_type_node,
370- tree_cons (NULL_TREE, V4HI_type_node,
371- tree_cons (NULL_TREE,
372- V4HI_type_node,
373- endlink))));
374-
375- tree di_ftype_v4hi_v4hi
376- = build_function_type (long_long_unsigned_type_node,
377- tree_cons (NULL_TREE, V4HI_type_node,
378- tree_cons (NULL_TREE, V4HI_type_node,
379- endlink)));
380-
381- /* Normal vector binops. */
382- tree v8qi_ftype_v8qi_v8qi
383- = build_function_type (V8QI_type_node,
384- tree_cons (NULL_TREE, V8QI_type_node,
385- tree_cons (NULL_TREE, V8QI_type_node,
386- endlink)));
387- tree v4hi_ftype_v4hi_v4hi
388- = build_function_type (V4HI_type_node,
389- tree_cons (NULL_TREE, V4HI_type_node,
390- tree_cons (NULL_TREE, V4HI_type_node,
391- endlink)));
392- tree v2si_ftype_v2si_v2si
393- = build_function_type (V2SI_type_node,
394- tree_cons (NULL_TREE, V2SI_type_node,
395- tree_cons (NULL_TREE, V2SI_type_node,
396- endlink)));
397- tree di_ftype_di_di
398- = build_function_type (long_long_unsigned_type_node,
399- tree_cons (NULL_TREE, long_long_unsigned_type_node,
400- tree_cons (NULL_TREE,
401- long_long_unsigned_type_node,
402- endlink)));
403-
404- /* Add all builtins that are more or less simple operations on two
405- operands. */
406- for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
407- {
408- /* Use one of the operands; the target can have a different mode for
409- mask-generating compares. */
410- enum machine_mode mode;
411- tree type;
412-
413- if (d->name == 0)
414- continue;
415-
416- mode = insn_data[d->icode].operand[1].mode;
417-
418- switch (mode)
419- {
420- case V8QImode:
421- type = v8qi_ftype_v8qi_v8qi;
422- break;
423- case V4HImode:
424- type = v4hi_ftype_v4hi_v4hi;
425- break;
426- case V2SImode:
427- type = v2si_ftype_v2si_v2si;
428- break;
429- case DImode:
430- type = di_ftype_di_di;
431- break;
432-
433- default:
434- gcc_unreachable ();
435- }
436-
437- def_mbuiltin (d->mask, d->name, type, d->code);
438- }
439-
440- /* Add the remaining MMX insns with somewhat more complicated types. */
441- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
442- def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
443- def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
444-
445- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
446- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
447- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
448- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
449- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
450- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
451-
452- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
453- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
454- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
455- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
456- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
457- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
458-
459- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
460- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
461- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
462- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
463- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
464- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
465-
466- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
467- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
468- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
469- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
470- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
471- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
472-
473- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
474-
475- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
476- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
477- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
478- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
479-
480- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
481- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
482- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
483- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
484- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
485- def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
486- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
487- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
488- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
489-
490- def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
491- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
492- def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
493-
494- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
495- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
496- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
497-
498- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
499- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
500- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
501- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
502- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
503- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
504-
505- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
506- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
507- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
508- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
509- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
510- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
511- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
512- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
513- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
514- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
515- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
516- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
517-
518- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
519- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
520- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
521- def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
522-
523- def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
524- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
525- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
526- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
527- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
528- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
529- def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
530-}
531-
532-static void
533-arm_init_tls_builtins (void)
534-{
535- tree ftype, decl;
536-
537- ftype = build_function_type (ptr_type_node, void_list_node);
538- decl = add_builtin_function ("__builtin_thread_pointer", ftype,
539- ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
540- NULL, NULL_TREE);
541- TREE_NOTHROW (decl) = 1;
542- TREE_READONLY (decl) = 1;
543-}
544-
545-enum neon_builtin_type_bits {
546- T_V8QI = 0x0001,
547- T_V4HI = 0x0002,
548- T_V2SI = 0x0004,
549- T_V2SF = 0x0008,
550- T_DI = 0x0010,
551- T_DREG = 0x001F,
552- T_V16QI = 0x0020,
553- T_V8HI = 0x0040,
554- T_V4SI = 0x0080,
555- T_V4SF = 0x0100,
556- T_V2DI = 0x0200,
557- T_TI = 0x0400,
558- T_QREG = 0x07E0,
559- T_EI = 0x0800,
560- T_OI = 0x1000
561-};
562+typedef enum {
563+ T_V8QI,
564+ T_V4HI,
565+ T_V2SI,
566+ T_V2SF,
567+ T_DI,
568+ T_V16QI,
569+ T_V8HI,
570+ T_V4SI,
571+ T_V4SF,
572+ T_V2DI,
573+ T_TI,
574+ T_EI,
575+ T_OI,
576+ T_MAX /* Size of enum. Keep last. */
577+} neon_builtin_type_mode;
578+
579+#define TYPE_MODE_BIT(X) (1 << (X))
580+
581+#define TB_DREG (TYPE_MODE_BIT (T_V8QI) | TYPE_MODE_BIT (T_V4HI) \
582+ | TYPE_MODE_BIT (T_V2SI) | TYPE_MODE_BIT (T_V2SF) \
583+ | TYPE_MODE_BIT (T_DI))
584+#define TB_QREG (TYPE_MODE_BIT (T_V16QI) | TYPE_MODE_BIT (T_V8HI) \
585+ | TYPE_MODE_BIT (T_V4SI) | TYPE_MODE_BIT (T_V4SF) \
586+ | TYPE_MODE_BIT (T_V2DI) | TYPE_MODE_BIT (T_TI))
587
588 #define v8qi_UP T_V8QI
589 #define v4hi_UP T_V4HI
590@@ -18663,8 +18192,6 @@
591
592 #define UP(X) X##_UP
593
594-#define T_MAX 13
595-
596 typedef enum {
597 NEON_BINOP,
598 NEON_TERNOP,
599@@ -18708,49 +18235,42 @@
600 typedef struct {
601 const char *name;
602 const neon_itype itype;
603- const int bits;
604- const enum insn_code codes[T_MAX];
605- const unsigned int num_vars;
606- unsigned int base_fcode;
607+ const neon_builtin_type_mode mode;
608+ const enum insn_code code;
609+ unsigned int fcode;
610 } neon_builtin_datum;
611
612 #define CF(N,X) CODE_FOR_neon_##N##X
613
614 #define VAR1(T, N, A) \
615- #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
616+ {#N, NEON_##T, UP (A), CF (N, A), 0}
617 #define VAR2(T, N, A, B) \
618- #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
619+ VAR1 (T, N, A), \
620+ {#N, NEON_##T, UP (B), CF (N, B), 0}
621 #define VAR3(T, N, A, B, C) \
622- #N, NEON_##T, UP (A) | UP (B) | UP (C), \
623- { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
624+ VAR2 (T, N, A, B), \
625+ {#N, NEON_##T, UP (C), CF (N, C), 0}
626 #define VAR4(T, N, A, B, C, D) \
627- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
628- { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
629+ VAR3 (T, N, A, B, C), \
630+ {#N, NEON_##T, UP (D), CF (N, D), 0}
631 #define VAR5(T, N, A, B, C, D, E) \
632- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
633- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
634+ VAR4 (T, N, A, B, C, D), \
635+ {#N, NEON_##T, UP (E), CF (N, E), 0}
636 #define VAR6(T, N, A, B, C, D, E, F) \
637- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
638- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
639+ VAR5 (T, N, A, B, C, D, E), \
640+ {#N, NEON_##T, UP (F), CF (N, F), 0}
641 #define VAR7(T, N, A, B, C, D, E, F, G) \
642- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
643- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
644- CF (N, G) }, 7, 0
645+ VAR6 (T, N, A, B, C, D, E, F), \
646+ {#N, NEON_##T, UP (G), CF (N, G), 0}
647 #define VAR8(T, N, A, B, C, D, E, F, G, H) \
648- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
649- | UP (H), \
650- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
651- CF (N, G), CF (N, H) }, 8, 0
652+ VAR7 (T, N, A, B, C, D, E, F, G), \
653+ {#N, NEON_##T, UP (H), CF (N, H), 0}
654 #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
655- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
656- | UP (H) | UP (I), \
657- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
658- CF (N, G), CF (N, H), CF (N, I) }, 9, 0
659+ VAR8 (T, N, A, B, C, D, E, F, G, H), \
660+ {#N, NEON_##T, UP (I), CF (N, I), 0}
661 #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
662- #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
663- | UP (H) | UP (I) | UP (J), \
664- { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
665- CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
666+ VAR9 (T, N, A, B, C, D, E, F, G, H, I), \
667+ {#N, NEON_##T, UP (J), CF (N, J), 0}
668
669 /* The mode entries in the following table correspond to the "key" type of the
670 instruction variant, i.e. equivalent to that which would be specified after
671@@ -18758,192 +18278,190 @@
672 (Signed/unsigned/polynomial types are not differentiated between though, and
673 are all mapped onto the same mode for a given element size.) The modes
674 listed per instruction should be the same as those defined for that
675- instruction's pattern in neon.md.
676- WARNING: Variants should be listed in the same increasing order as
677- neon_builtin_type_bits. */
678+ instruction's pattern in neon.md. */
679
680 static neon_builtin_datum neon_builtin_data[] =
681 {
682- { VAR10 (BINOP, vadd,
683- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
684- { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) },
685- { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) },
686- { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
687- { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
688- { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) },
689- { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
690- { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
691- { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) },
692- { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
693- { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) },
694- { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) },
695- { VAR2 (TERNOP, vqdmlal, v4hi, v2si) },
696- { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) },
697- { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) },
698- { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) },
699- { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) },
700- { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) },
701- { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) },
702- { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) },
703- { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) },
704- { VAR2 (BINOP, vqdmull, v4hi, v2si) },
705- { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
706- { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
707- { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
708- { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) },
709- { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) },
710- { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) },
711- { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
712- { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
713- { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
714- { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) },
715- { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
716- { VAR10 (BINOP, vsub,
717- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
718- { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) },
719- { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) },
720- { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
721- { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
722- { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) },
723- { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
724- { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
725- { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
726- { VAR2 (BINOP, vcage, v2sf, v4sf) },
727- { VAR2 (BINOP, vcagt, v2sf, v4sf) },
728- { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
729- { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
730- { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) },
731- { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
732- { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) },
733- { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
734- { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
735- { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) },
736- { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
737- { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
738- { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) },
739- { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) },
740- { VAR2 (BINOP, vrecps, v2sf, v4sf) },
741- { VAR2 (BINOP, vrsqrts, v2sf, v4sf) },
742- { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
743- { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
744- { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
745- { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
746- { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
747- { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
748- { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
749- { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
750- { VAR2 (UNOP, vcnt, v8qi, v16qi) },
751- { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) },
752- { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) },
753- { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
754+ VAR10 (BINOP, vadd,
755+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
756+ VAR3 (BINOP, vaddl, v8qi, v4hi, v2si),
757+ VAR3 (BINOP, vaddw, v8qi, v4hi, v2si),
758+ VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
759+ VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
760+ VAR3 (BINOP, vaddhn, v8hi, v4si, v2di),
761+ VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
762+ VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
763+ VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si),
764+ VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
765+ VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si),
766+ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si),
767+ VAR2 (TERNOP, vqdmlal, v4hi, v2si),
768+ VAR2 (TERNOP, vqdmlsl, v4hi, v2si),
769+ VAR3 (BINOP, vmull, v8qi, v4hi, v2si),
770+ VAR2 (SCALARMULL, vmull_n, v4hi, v2si),
771+ VAR2 (LANEMULL, vmull_lane, v4hi, v2si),
772+ VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si),
773+ VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si),
774+ VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si),
775+ VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si),
776+ VAR2 (BINOP, vqdmull, v4hi, v2si),
777+ VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
778+ VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
779+ VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
780+ VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di),
781+ VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di),
782+ VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di),
783+ VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
784+ VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
785+ VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
786+ VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si),
787+ VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
788+ VAR10 (BINOP, vsub,
789+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
790+ VAR3 (BINOP, vsubl, v8qi, v4hi, v2si),
791+ VAR3 (BINOP, vsubw, v8qi, v4hi, v2si),
792+ VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
793+ VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
794+ VAR3 (BINOP, vsubhn, v8hi, v4si, v2di),
795+ VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
796+ VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
797+ VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
798+ VAR2 (BINOP, vcage, v2sf, v4sf),
799+ VAR2 (BINOP, vcagt, v2sf, v4sf),
800+ VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
801+ VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
802+ VAR3 (BINOP, vabdl, v8qi, v4hi, v2si),
803+ VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
804+ VAR3 (TERNOP, vabal, v8qi, v4hi, v2si),
805+ VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
806+ VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
807+ VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf),
808+ VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
809+ VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
810+ VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf),
811+ VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf),
812+ VAR2 (BINOP, vrecps, v2sf, v4sf),
813+ VAR2 (BINOP, vrsqrts, v2sf, v4sf),
814+ VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
815+ VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di),
816+ VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
817+ VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
818+ VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
819+ VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
820+ VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
821+ VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
822+ VAR2 (UNOP, vcnt, v8qi, v16qi),
823+ VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf),
824+ VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf),
825+ VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si),
826 /* FIXME: vget_lane supports more variants than this! */
827- { VAR10 (GETLANE, vget_lane,
828- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
829- { VAR10 (SETLANE, vset_lane,
830- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
831- { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) },
832- { VAR10 (DUP, vdup_n,
833- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
834- { VAR10 (DUPLANE, vdup_lane,
835- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
836- { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) },
837- { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) },
838- { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) },
839- { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) },
840- { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) },
841- { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) },
842- { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) },
843- { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
844- { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
845- { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) },
846- { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) },
847- { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
848- { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) },
849- { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) },
850- { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
851- { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
852- { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) },
853- { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) },
854- { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
855- { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) },
856- { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) },
857- { VAR10 (BINOP, vext,
858- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
859- { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
860- { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) },
861- { VAR2 (UNOP, vrev16, v8qi, v16qi) },
862- { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) },
863- { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) },
864- { VAR10 (SELECT, vbsl,
865- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
866- { VAR1 (VTBL, vtbl1, v8qi) },
867- { VAR1 (VTBL, vtbl2, v8qi) },
868- { VAR1 (VTBL, vtbl3, v8qi) },
869- { VAR1 (VTBL, vtbl4, v8qi) },
870- { VAR1 (VTBX, vtbx1, v8qi) },
871- { VAR1 (VTBX, vtbx2, v8qi) },
872- { VAR1 (VTBX, vtbx3, v8qi) },
873- { VAR1 (VTBX, vtbx4, v8qi) },
874- { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
875- { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
876- { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
877- { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) },
878- { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) },
879- { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) },
880- { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) },
881- { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) },
882- { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) },
883- { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) },
884- { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) },
885- { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) },
886- { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) },
887- { VAR10 (LOAD1, vld1,
888- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
889- { VAR10 (LOAD1LANE, vld1_lane,
890- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
891- { VAR10 (LOAD1, vld1_dup,
892- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
893- { VAR10 (STORE1, vst1,
894- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
895- { VAR10 (STORE1LANE, vst1_lane,
896- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
897- { VAR9 (LOADSTRUCT,
898- vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
899- { VAR7 (LOADSTRUCTLANE, vld2_lane,
900- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
901- { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) },
902- { VAR9 (STORESTRUCT, vst2,
903- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
904- { VAR7 (STORESTRUCTLANE, vst2_lane,
905- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
906- { VAR9 (LOADSTRUCT,
907- vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
908- { VAR7 (LOADSTRUCTLANE, vld3_lane,
909- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
910- { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) },
911- { VAR9 (STORESTRUCT, vst3,
912- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
913- { VAR7 (STORESTRUCTLANE, vst3_lane,
914- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
915- { VAR9 (LOADSTRUCT, vld4,
916- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
917- { VAR7 (LOADSTRUCTLANE, vld4_lane,
918- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
919- { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) },
920- { VAR9 (STORESTRUCT, vst4,
921- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
922- { VAR7 (STORESTRUCTLANE, vst4_lane,
923- v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
924- { VAR10 (LOGICBINOP, vand,
925- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
926- { VAR10 (LOGICBINOP, vorr,
927- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
928- { VAR10 (BINOP, veor,
929- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
930- { VAR10 (LOGICBINOP, vbic,
931- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
932- { VAR10 (LOGICBINOP, vorn,
933- v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }
934+ VAR10 (GETLANE, vget_lane,
935+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
936+ VAR10 (SETLANE, vset_lane,
937+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
938+ VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di),
939+ VAR10 (DUP, vdup_n,
940+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
941+ VAR10 (DUPLANE, vdup_lane,
942+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
943+ VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di),
944+ VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di),
945+ VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di),
946+ VAR3 (UNOP, vmovn, v8hi, v4si, v2di),
947+ VAR3 (UNOP, vqmovn, v8hi, v4si, v2di),
948+ VAR3 (UNOP, vqmovun, v8hi, v4si, v2di),
949+ VAR3 (UNOP, vmovl, v8qi, v4hi, v2si),
950+ VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
951+ VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
952+ VAR2 (LANEMAC, vmlal_lane, v4hi, v2si),
953+ VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si),
954+ VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
955+ VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si),
956+ VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si),
957+ VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
958+ VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
959+ VAR2 (SCALARMAC, vmlal_n, v4hi, v2si),
960+ VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si),
961+ VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
962+ VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si),
963+ VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si),
964+ VAR10 (BINOP, vext,
965+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
966+ VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
967+ VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi),
968+ VAR2 (UNOP, vrev16, v8qi, v16qi),
969+ VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf),
970+ VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf),
971+ VAR10 (SELECT, vbsl,
972+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
973+ VAR1 (VTBL, vtbl1, v8qi),
974+ VAR1 (VTBL, vtbl2, v8qi),
975+ VAR1 (VTBL, vtbl3, v8qi),
976+ VAR1 (VTBL, vtbl4, v8qi),
977+ VAR1 (VTBX, vtbx1, v8qi),
978+ VAR1 (VTBX, vtbx2, v8qi),
979+ VAR1 (VTBX, vtbx3, v8qi),
980+ VAR1 (VTBX, vtbx4, v8qi),
981+ VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
982+ VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
983+ VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf),
984+ VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di),
985+ VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di),
986+ VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di),
987+ VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di),
988+ VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di),
989+ VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di),
990+ VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di),
991+ VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di),
992+ VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di),
993+ VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di),
994+ VAR10 (LOAD1, vld1,
995+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
996+ VAR10 (LOAD1LANE, vld1_lane,
997+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
998+ VAR10 (LOAD1, vld1_dup,
999+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1000+ VAR10 (STORE1, vst1,
1001+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1002+ VAR10 (STORE1LANE, vst1_lane,
1003+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1004+ VAR9 (LOADSTRUCT,
1005+ vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1006+ VAR7 (LOADSTRUCTLANE, vld2_lane,
1007+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1008+ VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di),
1009+ VAR9 (STORESTRUCT, vst2,
1010+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1011+ VAR7 (STORESTRUCTLANE, vst2_lane,
1012+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1013+ VAR9 (LOADSTRUCT,
1014+ vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1015+ VAR7 (LOADSTRUCTLANE, vld3_lane,
1016+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1017+ VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di),
1018+ VAR9 (STORESTRUCT, vst3,
1019+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1020+ VAR7 (STORESTRUCTLANE, vst3_lane,
1021+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1022+ VAR9 (LOADSTRUCT, vld4,
1023+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1024+ VAR7 (LOADSTRUCTLANE, vld4_lane,
1025+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1026+ VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di),
1027+ VAR9 (STORESTRUCT, vst4,
1028+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf),
1029+ VAR7 (STORESTRUCTLANE, vst4_lane,
1030+ v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf),
1031+ VAR10 (LOGICBINOP, vand,
1032+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1033+ VAR10 (LOGICBINOP, vorr,
1034+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1035+ VAR10 (BINOP, veor,
1036+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1037+ VAR10 (LOGICBINOP, vbic,
1038+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di),
1039+ VAR10 (LOGICBINOP, vorn,
1040+ v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
1041 };
1042
1043 #undef CF
1044@@ -18958,10 +18476,185 @@
1045 #undef VAR9
1046 #undef VAR10
1047
1048+/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
1049+ symbolic names defined here (which would require too much duplication).
1050+ FIXME? */
1051+enum arm_builtins
1052+{
1053+ ARM_BUILTIN_GETWCX,
1054+ ARM_BUILTIN_SETWCX,
1055+
1056+ ARM_BUILTIN_WZERO,
1057+
1058+ ARM_BUILTIN_WAVG2BR,
1059+ ARM_BUILTIN_WAVG2HR,
1060+ ARM_BUILTIN_WAVG2B,
1061+ ARM_BUILTIN_WAVG2H,
1062+
1063+ ARM_BUILTIN_WACCB,
1064+ ARM_BUILTIN_WACCH,
1065+ ARM_BUILTIN_WACCW,
1066+
1067+ ARM_BUILTIN_WMACS,
1068+ ARM_BUILTIN_WMACSZ,
1069+ ARM_BUILTIN_WMACU,
1070+ ARM_BUILTIN_WMACUZ,
1071+
1072+ ARM_BUILTIN_WSADB,
1073+ ARM_BUILTIN_WSADBZ,
1074+ ARM_BUILTIN_WSADH,
1075+ ARM_BUILTIN_WSADHZ,
1076+
1077+ ARM_BUILTIN_WALIGN,
1078+
1079+ ARM_BUILTIN_TMIA,
1080+ ARM_BUILTIN_TMIAPH,
1081+ ARM_BUILTIN_TMIABB,
1082+ ARM_BUILTIN_TMIABT,
1083+ ARM_BUILTIN_TMIATB,
1084+ ARM_BUILTIN_TMIATT,
1085+
1086+ ARM_BUILTIN_TMOVMSKB,
1087+ ARM_BUILTIN_TMOVMSKH,
1088+ ARM_BUILTIN_TMOVMSKW,
1089+
1090+ ARM_BUILTIN_TBCSTB,
1091+ ARM_BUILTIN_TBCSTH,
1092+ ARM_BUILTIN_TBCSTW,
1093+
1094+ ARM_BUILTIN_WMADDS,
1095+ ARM_BUILTIN_WMADDU,
1096+
1097+ ARM_BUILTIN_WPACKHSS,
1098+ ARM_BUILTIN_WPACKWSS,
1099+ ARM_BUILTIN_WPACKDSS,
1100+ ARM_BUILTIN_WPACKHUS,
1101+ ARM_BUILTIN_WPACKWUS,
1102+ ARM_BUILTIN_WPACKDUS,
1103+
1104+ ARM_BUILTIN_WADDB,
1105+ ARM_BUILTIN_WADDH,
1106+ ARM_BUILTIN_WADDW,
1107+ ARM_BUILTIN_WADDSSB,
1108+ ARM_BUILTIN_WADDSSH,
1109+ ARM_BUILTIN_WADDSSW,
1110+ ARM_BUILTIN_WADDUSB,
1111+ ARM_BUILTIN_WADDUSH,
1112+ ARM_BUILTIN_WADDUSW,
1113+ ARM_BUILTIN_WSUBB,
1114+ ARM_BUILTIN_WSUBH,
1115+ ARM_BUILTIN_WSUBW,
1116+ ARM_BUILTIN_WSUBSSB,
1117+ ARM_BUILTIN_WSUBSSH,
1118+ ARM_BUILTIN_WSUBSSW,
1119+ ARM_BUILTIN_WSUBUSB,
1120+ ARM_BUILTIN_WSUBUSH,
1121+ ARM_BUILTIN_WSUBUSW,
1122+
1123+ ARM_BUILTIN_WAND,
1124+ ARM_BUILTIN_WANDN,
1125+ ARM_BUILTIN_WOR,
1126+ ARM_BUILTIN_WXOR,
1127+
1128+ ARM_BUILTIN_WCMPEQB,
1129+ ARM_BUILTIN_WCMPEQH,
1130+ ARM_BUILTIN_WCMPEQW,
1131+ ARM_BUILTIN_WCMPGTUB,
1132+ ARM_BUILTIN_WCMPGTUH,
1133+ ARM_BUILTIN_WCMPGTUW,
1134+ ARM_BUILTIN_WCMPGTSB,
1135+ ARM_BUILTIN_WCMPGTSH,
1136+ ARM_BUILTIN_WCMPGTSW,
1137+
1138+ ARM_BUILTIN_TEXTRMSB,
1139+ ARM_BUILTIN_TEXTRMSH,
1140+ ARM_BUILTIN_TEXTRMSW,
1141+ ARM_BUILTIN_TEXTRMUB,
1142+ ARM_BUILTIN_TEXTRMUH,
1143+ ARM_BUILTIN_TEXTRMUW,
1144+ ARM_BUILTIN_TINSRB,
1145+ ARM_BUILTIN_TINSRH,
1146+ ARM_BUILTIN_TINSRW,
1147+
1148+ ARM_BUILTIN_WMAXSW,
1149+ ARM_BUILTIN_WMAXSH,
1150+ ARM_BUILTIN_WMAXSB,
1151+ ARM_BUILTIN_WMAXUW,
1152+ ARM_BUILTIN_WMAXUH,
1153+ ARM_BUILTIN_WMAXUB,
1154+ ARM_BUILTIN_WMINSW,
1155+ ARM_BUILTIN_WMINSH,
1156+ ARM_BUILTIN_WMINSB,
1157+ ARM_BUILTIN_WMINUW,
1158+ ARM_BUILTIN_WMINUH,
1159+ ARM_BUILTIN_WMINUB,
1160+
1161+ ARM_BUILTIN_WMULUM,
1162+ ARM_BUILTIN_WMULSM,
1163+ ARM_BUILTIN_WMULUL,
1164+
1165+ ARM_BUILTIN_PSADBH,
1166+ ARM_BUILTIN_WSHUFH,
1167+
1168+ ARM_BUILTIN_WSLLH,
1169+ ARM_BUILTIN_WSLLW,
1170+ ARM_BUILTIN_WSLLD,
1171+ ARM_BUILTIN_WSRAH,
1172+ ARM_BUILTIN_WSRAW,
1173+ ARM_BUILTIN_WSRAD,
1174+ ARM_BUILTIN_WSRLH,
1175+ ARM_BUILTIN_WSRLW,
1176+ ARM_BUILTIN_WSRLD,
1177+ ARM_BUILTIN_WRORH,
1178+ ARM_BUILTIN_WRORW,
1179+ ARM_BUILTIN_WRORD,
1180+ ARM_BUILTIN_WSLLHI,
1181+ ARM_BUILTIN_WSLLWI,
1182+ ARM_BUILTIN_WSLLDI,
1183+ ARM_BUILTIN_WSRAHI,
1184+ ARM_BUILTIN_WSRAWI,
1185+ ARM_BUILTIN_WSRADI,
1186+ ARM_BUILTIN_WSRLHI,
1187+ ARM_BUILTIN_WSRLWI,
1188+ ARM_BUILTIN_WSRLDI,
1189+ ARM_BUILTIN_WRORHI,
1190+ ARM_BUILTIN_WRORWI,
1191+ ARM_BUILTIN_WRORDI,
1192+
1193+ ARM_BUILTIN_WUNPCKIHB,
1194+ ARM_BUILTIN_WUNPCKIHH,
1195+ ARM_BUILTIN_WUNPCKIHW,
1196+ ARM_BUILTIN_WUNPCKILB,
1197+ ARM_BUILTIN_WUNPCKILH,
1198+ ARM_BUILTIN_WUNPCKILW,
1199+
1200+ ARM_BUILTIN_WUNPCKEHSB,
1201+ ARM_BUILTIN_WUNPCKEHSH,
1202+ ARM_BUILTIN_WUNPCKEHSW,
1203+ ARM_BUILTIN_WUNPCKEHUB,
1204+ ARM_BUILTIN_WUNPCKEHUH,
1205+ ARM_BUILTIN_WUNPCKEHUW,
1206+ ARM_BUILTIN_WUNPCKELSB,
1207+ ARM_BUILTIN_WUNPCKELSH,
1208+ ARM_BUILTIN_WUNPCKELSW,
1209+ ARM_BUILTIN_WUNPCKELUB,
1210+ ARM_BUILTIN_WUNPCKELUH,
1211+ ARM_BUILTIN_WUNPCKELUW,
1212+
1213+ ARM_BUILTIN_THREAD_POINTER,
1214+
1215+ ARM_BUILTIN_NEON_BASE,
1216+
1217+ ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE + ARRAY_SIZE (neon_builtin_data)
1218+};
1219+
1220+static GTY(()) tree arm_builtin_decls[ARM_BUILTIN_MAX];
1221+
1222 static void
1223 arm_init_neon_builtins (void)
1224 {
1225- unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
1226+ unsigned int i, fcode;
1227+ tree decl;
1228
1229 tree neon_intQI_type_node;
1230 tree neon_intHI_type_node;
1231@@ -19209,250 +18902,740 @@
1232 }
1233 }
1234
1235- for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++)
1236+ for (i = 0, fcode = ARM_BUILTIN_NEON_BASE;
1237+ i < ARRAY_SIZE (neon_builtin_data);
1238+ i++, fcode++)
1239 {
1240 neon_builtin_datum *d = &neon_builtin_data[i];
1241- unsigned int j, codeidx = 0;
1242-
1243- d->base_fcode = fcode;
1244-
1245- for (j = 0; j < T_MAX; j++)
1246- {
1247- const char* const modenames[] = {
1248- "v8qi", "v4hi", "v2si", "v2sf", "di",
1249- "v16qi", "v8hi", "v4si", "v4sf", "v2di"
1250- };
1251- char namebuf[60];
1252- tree ftype = NULL;
1253- enum insn_code icode;
1254- int is_load = 0, is_store = 0;
1255-
1256- if ((d->bits & (1 << j)) == 0)
1257- continue;
1258-
1259- icode = d->codes[codeidx++];
1260-
1261- switch (d->itype)
1262- {
1263- case NEON_LOAD1:
1264- case NEON_LOAD1LANE:
1265- case NEON_LOADSTRUCT:
1266- case NEON_LOADSTRUCTLANE:
1267- is_load = 1;
1268- /* Fall through. */
1269- case NEON_STORE1:
1270- case NEON_STORE1LANE:
1271- case NEON_STORESTRUCT:
1272- case NEON_STORESTRUCTLANE:
1273- if (!is_load)
1274- is_store = 1;
1275- /* Fall through. */
1276- case NEON_UNOP:
1277- case NEON_BINOP:
1278- case NEON_LOGICBINOP:
1279- case NEON_SHIFTINSERT:
1280- case NEON_TERNOP:
1281- case NEON_GETLANE:
1282- case NEON_SETLANE:
1283- case NEON_CREATE:
1284- case NEON_DUP:
1285- case NEON_DUPLANE:
1286- case NEON_SHIFTIMM:
1287- case NEON_SHIFTACC:
1288- case NEON_COMBINE:
1289- case NEON_SPLIT:
1290- case NEON_CONVERT:
1291- case NEON_FIXCONV:
1292- case NEON_LANEMUL:
1293- case NEON_LANEMULL:
1294- case NEON_LANEMULH:
1295- case NEON_LANEMAC:
1296- case NEON_SCALARMUL:
1297- case NEON_SCALARMULL:
1298- case NEON_SCALARMULH:
1299- case NEON_SCALARMAC:
1300- case NEON_SELECT:
1301- case NEON_VTBL:
1302- case NEON_VTBX:
1303- {
1304- int k;
1305- tree return_type = void_type_node, args = void_list_node;
1306-
1307- /* Build a function type directly from the insn_data for this
1308- builtin. The build_function_type() function takes care of
1309- removing duplicates for us. */
1310- for (k = insn_data[icode].n_operands - 1; k >= 0; k--)
1311- {
1312- tree eltype;
1313-
1314- if (is_load && k == 1)
1315- {
1316- /* Neon load patterns always have the memory operand
1317- in the operand 1 position. */
1318- gcc_assert (insn_data[icode].operand[k].predicate
1319- == neon_struct_operand);
1320-
1321- switch (1 << j)
1322- {
1323- case T_V8QI:
1324- case T_V16QI:
1325- eltype = const_intQI_pointer_node;
1326- break;
1327-
1328- case T_V4HI:
1329- case T_V8HI:
1330- eltype = const_intHI_pointer_node;
1331- break;
1332-
1333- case T_V2SI:
1334- case T_V4SI:
1335- eltype = const_intSI_pointer_node;
1336- break;
1337-
1338- case T_V2SF:
1339- case T_V4SF:
1340- eltype = const_float_pointer_node;
1341- break;
1342-
1343- case T_DI:
1344- case T_V2DI:
1345- eltype = const_intDI_pointer_node;
1346- break;
1347-
1348- default: gcc_unreachable ();
1349- }
1350- }
1351- else if (is_store && k == 0)
1352- {
1353- /* Similarly, Neon store patterns use operand 0 as
1354- the memory location to store to. */
1355- gcc_assert (insn_data[icode].operand[k].predicate
1356- == neon_struct_operand);
1357-
1358- switch (1 << j)
1359- {
1360- case T_V8QI:
1361- case T_V16QI:
1362- eltype = intQI_pointer_node;
1363- break;
1364-
1365- case T_V4HI:
1366- case T_V8HI:
1367- eltype = intHI_pointer_node;
1368- break;
1369-
1370- case T_V2SI:
1371- case T_V4SI:
1372- eltype = intSI_pointer_node;
1373- break;
1374-
1375- case T_V2SF:
1376- case T_V4SF:
1377- eltype = float_pointer_node;
1378- break;
1379-
1380- case T_DI:
1381- case T_V2DI:
1382- eltype = intDI_pointer_node;
1383- break;
1384-
1385- default: gcc_unreachable ();
1386- }
1387- }
1388- else
1389- {
1390- switch (insn_data[icode].operand[k].mode)
1391- {
1392- case VOIDmode: eltype = void_type_node; break;
1393- /* Scalars. */
1394- case QImode: eltype = neon_intQI_type_node; break;
1395- case HImode: eltype = neon_intHI_type_node; break;
1396- case SImode: eltype = neon_intSI_type_node; break;
1397- case SFmode: eltype = neon_float_type_node; break;
1398- case DImode: eltype = neon_intDI_type_node; break;
1399- case TImode: eltype = intTI_type_node; break;
1400- case EImode: eltype = intEI_type_node; break;
1401- case OImode: eltype = intOI_type_node; break;
1402- case CImode: eltype = intCI_type_node; break;
1403- case XImode: eltype = intXI_type_node; break;
1404- /* 64-bit vectors. */
1405- case V8QImode: eltype = V8QI_type_node; break;
1406- case V4HImode: eltype = V4HI_type_node; break;
1407- case V2SImode: eltype = V2SI_type_node; break;
1408- case V2SFmode: eltype = V2SF_type_node; break;
1409- /* 128-bit vectors. */
1410- case V16QImode: eltype = V16QI_type_node; break;
1411- case V8HImode: eltype = V8HI_type_node; break;
1412- case V4SImode: eltype = V4SI_type_node; break;
1413- case V4SFmode: eltype = V4SF_type_node; break;
1414- case V2DImode: eltype = V2DI_type_node; break;
1415- default: gcc_unreachable ();
1416- }
1417- }
1418-
1419- if (k == 0 && !is_store)
1420- return_type = eltype;
1421- else
1422- args = tree_cons (NULL_TREE, eltype, args);
1423- }
1424-
1425- ftype = build_function_type (return_type, args);
1426- }
1427- break;
1428-
1429- case NEON_RESULTPAIR:
1430- {
1431- switch (insn_data[icode].operand[1].mode)
1432- {
1433- case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
1434- case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
1435- case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
1436- case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
1437- case DImode: ftype = void_ftype_pdi_di_di; break;
1438- case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
1439- case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
1440- case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
1441- case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
1442- case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
1443- default: gcc_unreachable ();
1444- }
1445- }
1446- break;
1447-
1448- case NEON_REINTERP:
1449- {
1450- /* We iterate over 5 doubleword types, then 5 quadword
1451- types. */
1452- int rhs = j % 5;
1453- switch (insn_data[icode].operand[0].mode)
1454- {
1455- case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
1456- case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
1457- case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
1458- case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
1459- case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
1460- case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
1461- case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
1462- case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
1463- case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
1464- case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
1465- default: gcc_unreachable ();
1466- }
1467- }
1468- break;
1469-
1470- default:
1471- gcc_unreachable ();
1472- }
1473-
1474- gcc_assert (ftype != NULL);
1475-
1476- sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]);
1477-
1478- add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL,
1479- NULL_TREE);
1480- }
1481- }
1482+
1483+ const char* const modenames[] = {
1484+ "v8qi", "v4hi", "v2si", "v2sf", "di",
1485+ "v16qi", "v8hi", "v4si", "v4sf", "v2di",
1486+ "ti", "ei", "oi"
1487+ };
1488+ char namebuf[60];
1489+ tree ftype = NULL;
1490+ int is_load = 0, is_store = 0;
1491+
1492+ gcc_assert (ARRAY_SIZE (modenames) == T_MAX);
1493+
1494+ d->fcode = fcode;
1495+
1496+ switch (d->itype)
1497+ {
1498+ case NEON_LOAD1:
1499+ case NEON_LOAD1LANE:
1500+ case NEON_LOADSTRUCT:
1501+ case NEON_LOADSTRUCTLANE:
1502+ is_load = 1;
1503+ /* Fall through. */
1504+ case NEON_STORE1:
1505+ case NEON_STORE1LANE:
1506+ case NEON_STORESTRUCT:
1507+ case NEON_STORESTRUCTLANE:
1508+ if (!is_load)
1509+ is_store = 1;
1510+ /* Fall through. */
1511+ case NEON_UNOP:
1512+ case NEON_BINOP:
1513+ case NEON_LOGICBINOP:
1514+ case NEON_SHIFTINSERT:
1515+ case NEON_TERNOP:
1516+ case NEON_GETLANE:
1517+ case NEON_SETLANE:
1518+ case NEON_CREATE:
1519+ case NEON_DUP:
1520+ case NEON_DUPLANE:
1521+ case NEON_SHIFTIMM:
1522+ case NEON_SHIFTACC:
1523+ case NEON_COMBINE:
1524+ case NEON_SPLIT:
1525+ case NEON_CONVERT:
1526+ case NEON_FIXCONV:
1527+ case NEON_LANEMUL:
1528+ case NEON_LANEMULL:
1529+ case NEON_LANEMULH:
1530+ case NEON_LANEMAC:
1531+ case NEON_SCALARMUL:
1532+ case NEON_SCALARMULL:
1533+ case NEON_SCALARMULH:
1534+ case NEON_SCALARMAC:
1535+ case NEON_SELECT:
1536+ case NEON_VTBL:
1537+ case NEON_VTBX:
1538+ {
1539+ int k;
1540+ tree return_type = void_type_node, args = void_list_node;
1541+
1542+ /* Build a function type directly from the insn_data for
1543+ this builtin. The build_function_type() function takes
1544+ care of removing duplicates for us. */
1545+ for (k = insn_data[d->code].n_operands - 1; k >= 0; k--)
1546+ {
1547+ tree eltype;
1548+
1549+ if (is_load && k == 1)
1550+ {
1551+ /* Neon load patterns always have the memory
1552+ operand in the operand 1 position. */
1553+ gcc_assert (insn_data[d->code].operand[k].predicate
1554+ == neon_struct_operand);
1555+
1556+ switch (d->mode)
1557+ {
1558+ case T_V8QI:
1559+ case T_V16QI:
1560+ eltype = const_intQI_pointer_node;
1561+ break;
1562+
1563+ case T_V4HI:
1564+ case T_V8HI:
1565+ eltype = const_intHI_pointer_node;
1566+ break;
1567+
1568+ case T_V2SI:
1569+ case T_V4SI:
1570+ eltype = const_intSI_pointer_node;
1571+ break;
1572+
1573+ case T_V2SF:
1574+ case T_V4SF:
1575+ eltype = const_float_pointer_node;
1576+ break;
1577+
1578+ case T_DI:
1579+ case T_V2DI:
1580+ eltype = const_intDI_pointer_node;
1581+ break;
1582+
1583+ default: gcc_unreachable ();
1584+ }
1585+ }
1586+ else if (is_store && k == 0)
1587+ {
1588+ /* Similarly, Neon store patterns use operand 0 as
1589+ the memory location to store to. */
1590+ gcc_assert (insn_data[d->code].operand[k].predicate
1591+ == neon_struct_operand);
1592+
1593+ switch (d->mode)
1594+ {
1595+ case T_V8QI:
1596+ case T_V16QI:
1597+ eltype = intQI_pointer_node;
1598+ break;
1599+
1600+ case T_V4HI:
1601+ case T_V8HI:
1602+ eltype = intHI_pointer_node;
1603+ break;
1604+
1605+ case T_V2SI:
1606+ case T_V4SI:
1607+ eltype = intSI_pointer_node;
1608+ break;
1609+
1610+ case T_V2SF:
1611+ case T_V4SF:
1612+ eltype = float_pointer_node;
1613+ break;
1614+
1615+ case T_DI:
1616+ case T_V2DI:
1617+ eltype = intDI_pointer_node;
1618+ break;
1619+
1620+ default: gcc_unreachable ();
1621+ }
1622+ }
1623+ else
1624+ {
1625+ switch (insn_data[d->code].operand[k].mode)
1626+ {
1627+ case VOIDmode: eltype = void_type_node; break;
1628+ /* Scalars. */
1629+ case QImode: eltype = neon_intQI_type_node; break;
1630+ case HImode: eltype = neon_intHI_type_node; break;
1631+ case SImode: eltype = neon_intSI_type_node; break;
1632+ case SFmode: eltype = neon_float_type_node; break;
1633+ case DImode: eltype = neon_intDI_type_node; break;
1634+ case TImode: eltype = intTI_type_node; break;
1635+ case EImode: eltype = intEI_type_node; break;
1636+ case OImode: eltype = intOI_type_node; break;
1637+ case CImode: eltype = intCI_type_node; break;
1638+ case XImode: eltype = intXI_type_node; break;
1639+ /* 64-bit vectors. */
1640+ case V8QImode: eltype = V8QI_type_node; break;
1641+ case V4HImode: eltype = V4HI_type_node; break;
1642+ case V2SImode: eltype = V2SI_type_node; break;
1643+ case V2SFmode: eltype = V2SF_type_node; break;
1644+ /* 128-bit vectors. */
1645+ case V16QImode: eltype = V16QI_type_node; break;
1646+ case V8HImode: eltype = V8HI_type_node; break;
1647+ case V4SImode: eltype = V4SI_type_node; break;
1648+ case V4SFmode: eltype = V4SF_type_node; break;
1649+ case V2DImode: eltype = V2DI_type_node; break;
1650+ default: gcc_unreachable ();
1651+ }
1652+ }
1653+
1654+ if (k == 0 && !is_store)
1655+ return_type = eltype;
1656+ else
1657+ args = tree_cons (NULL_TREE, eltype, args);
1658+ }
1659+
1660+ ftype = build_function_type (return_type, args);
1661+ }
1662+ break;
1663+
1664+ case NEON_RESULTPAIR:
1665+ {
1666+ switch (insn_data[d->code].operand[1].mode)
1667+ {
1668+ case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
1669+ case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
1670+ case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
1671+ case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
1672+ case DImode: ftype = void_ftype_pdi_di_di; break;
1673+ case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
1674+ case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
1675+ case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
1676+ case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
1677+ case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
1678+ default: gcc_unreachable ();
1679+ }
1680+ }
1681+ break;
1682+
1683+ case NEON_REINTERP:
1684+ {
1685+ /* We iterate over 5 doubleword types, then 5 quadword
1686+ types. */
1687+ int rhs = d->mode % 5;
1688+ switch (insn_data[d->code].operand[0].mode)
1689+ {
1690+ case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
1691+ case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
1692+ case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
1693+ case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
1694+ case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
1695+ case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
1696+ case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
1697+ case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
1698+ case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
1699+ case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
1700+ default: gcc_unreachable ();
1701+ }
1702+ }
1703+ break;
1704+
1705+ default:
1706+ gcc_unreachable ();
1707+ }
1708+
1709+ gcc_assert (ftype != NULL);
1710+
1711+ sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[d->mode]);
1712+
1713+ decl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL,
1714+ NULL_TREE);
1715+ arm_builtin_decls[fcode] = decl;
1716+ }
1717+}
1718+
1719+#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
1720+ do \
1721+ { \
1722+ if ((MASK) & insn_flags) \
1723+ { \
1724+ tree bdecl; \
1725+ bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
1726+ BUILT_IN_MD, NULL, NULL_TREE); \
1727+ arm_builtin_decls[CODE] = bdecl; \
1728+ } \
1729+ } \
1730+ while (0)
1731+
1732+struct builtin_description
1733+{
1734+ const unsigned int mask;
1735+ const enum insn_code icode;
1736+ const char * const name;
1737+ const enum arm_builtins code;
1738+ const enum rtx_code comparison;
1739+ const unsigned int flag;
1740+};
1741+
1742+static const struct builtin_description bdesc_2arg[] =
1743+{
1744+#define IWMMXT_BUILTIN(code, string, builtin) \
1745+ { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
1746+ ARM_BUILTIN_##builtin, UNKNOWN, 0 },
1747+
1748+ IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
1749+ IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
1750+ IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
1751+ IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
1752+ IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
1753+ IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
1754+ IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
1755+ IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
1756+ IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
1757+ IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
1758+ IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
1759+ IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
1760+ IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
1761+ IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
1762+ IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
1763+ IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
1764+ IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
1765+ IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
1766+ IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
1767+ IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
1768+ IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
1769+ IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
1770+ IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
1771+ IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
1772+ IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
1773+ IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
1774+ IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
1775+ IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
1776+ IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
1777+ IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
1778+ IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
1779+ IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
1780+ IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
1781+ IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
1782+ IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
1783+ IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
1784+ IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
1785+ IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
1786+ IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
1787+ IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
1788+ IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
1789+ IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
1790+ IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
1791+ IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
1792+ IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
1793+ IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
1794+ IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
1795+ IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
1796+ IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
1797+ IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
1798+ IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
1799+ IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
1800+ IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
1801+ IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
1802+ IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
1803+ IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
1804+ IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
1805+ IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
1806+
1807+#define IWMMXT_BUILTIN2(code, builtin) \
1808+ { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 },
1809+
1810+ IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
1811+ IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
1812+ IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
1813+ IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
1814+ IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
1815+ IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
1816+ IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
1817+ IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
1818+ IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
1819+ IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
1820+ IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
1821+ IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
1822+ IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
1823+ IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
1824+ IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
1825+ IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
1826+ IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
1827+ IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
1828+ IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
1829+ IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
1830+ IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
1831+ IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
1832+ IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
1833+ IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
1834+ IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
1835+ IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
1836+ IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
1837+ IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
1838+ IWMMXT_BUILTIN2 (rordi3_di, WRORD)
1839+ IWMMXT_BUILTIN2 (rordi3, WRORDI)
1840+ IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
1841+ IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
1842+};
1843+
1844+static const struct builtin_description bdesc_1arg[] =
1845+{
1846+ IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
1847+ IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
1848+ IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
1849+ IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
1850+ IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
1851+ IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
1852+ IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
1853+ IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
1854+ IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
1855+ IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
1856+ IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
1857+ IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
1858+ IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
1859+ IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
1860+ IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
1861+ IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
1862+ IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
1863+ IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
1864+};
1865+
1866+/* Set up all the iWMMXt builtins. This is not called if
1867+ TARGET_IWMMXT is zero. */
1868+
1869+static void
1870+arm_init_iwmmxt_builtins (void)
1871+{
1872+ const struct builtin_description * d;
1873+ size_t i;
1874+ tree endlink = void_list_node;
1875+
1876+ tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
1877+ tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
1878+ tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
1879+
1880+ tree int_ftype_int
1881+ = build_function_type (integer_type_node,
1882+ tree_cons (NULL_TREE, integer_type_node, endlink));
1883+ tree v8qi_ftype_v8qi_v8qi_int
1884+ = build_function_type (V8QI_type_node,
1885+ tree_cons (NULL_TREE, V8QI_type_node,
1886+ tree_cons (NULL_TREE, V8QI_type_node,
1887+ tree_cons (NULL_TREE,
1888+ integer_type_node,
1889+ endlink))));
1890+ tree v4hi_ftype_v4hi_int
1891+ = build_function_type (V4HI_type_node,
1892+ tree_cons (NULL_TREE, V4HI_type_node,
1893+ tree_cons (NULL_TREE, integer_type_node,
1894+ endlink)));
1895+ tree v2si_ftype_v2si_int
1896+ = build_function_type (V2SI_type_node,
1897+ tree_cons (NULL_TREE, V2SI_type_node,
1898+ tree_cons (NULL_TREE, integer_type_node,
1899+ endlink)));
1900+ tree v2si_ftype_di_di
1901+ = build_function_type (V2SI_type_node,
1902+ tree_cons (NULL_TREE, long_long_integer_type_node,
1903+ tree_cons (NULL_TREE,
1904+ long_long_integer_type_node,
1905+ endlink)));
1906+ tree di_ftype_di_int
1907+ = build_function_type (long_long_integer_type_node,
1908+ tree_cons (NULL_TREE, long_long_integer_type_node,
1909+ tree_cons (NULL_TREE, integer_type_node,
1910+ endlink)));
1911+ tree di_ftype_di_int_int
1912+ = build_function_type (long_long_integer_type_node,
1913+ tree_cons (NULL_TREE, long_long_integer_type_node,
1914+ tree_cons (NULL_TREE, integer_type_node,
1915+ tree_cons (NULL_TREE,
1916+ integer_type_node,
1917+ endlink))));
1918+ tree int_ftype_v8qi
1919+ = build_function_type (integer_type_node,
1920+ tree_cons (NULL_TREE, V8QI_type_node,
1921+ endlink));
1922+ tree int_ftype_v4hi
1923+ = build_function_type (integer_type_node,
1924+ tree_cons (NULL_TREE, V4HI_type_node,
1925+ endlink));
1926+ tree int_ftype_v2si
1927+ = build_function_type (integer_type_node,
1928+ tree_cons (NULL_TREE, V2SI_type_node,
1929+ endlink));
1930+ tree int_ftype_v8qi_int
1931+ = build_function_type (integer_type_node,
1932+ tree_cons (NULL_TREE, V8QI_type_node,
1933+ tree_cons (NULL_TREE, integer_type_node,
1934+ endlink)));
1935+ tree int_ftype_v4hi_int
1936+ = build_function_type (integer_type_node,
1937+ tree_cons (NULL_TREE, V4HI_type_node,
1938+ tree_cons (NULL_TREE, integer_type_node,
1939+ endlink)));
1940+ tree int_ftype_v2si_int
1941+ = build_function_type (integer_type_node,
1942+ tree_cons (NULL_TREE, V2SI_type_node,
1943+ tree_cons (NULL_TREE, integer_type_node,
1944+ endlink)));
1945+ tree v8qi_ftype_v8qi_int_int
1946+ = build_function_type (V8QI_type_node,
1947+ tree_cons (NULL_TREE, V8QI_type_node,
1948+ tree_cons (NULL_TREE, integer_type_node,
1949+ tree_cons (NULL_TREE,
1950+ integer_type_node,
1951+ endlink))));
1952+ tree v4hi_ftype_v4hi_int_int
1953+ = build_function_type (V4HI_type_node,
1954+ tree_cons (NULL_TREE, V4HI_type_node,
1955+ tree_cons (NULL_TREE, integer_type_node,
1956+ tree_cons (NULL_TREE,
1957+ integer_type_node,
1958+ endlink))));
1959+ tree v2si_ftype_v2si_int_int
1960+ = build_function_type (V2SI_type_node,
1961+ tree_cons (NULL_TREE, V2SI_type_node,
1962+ tree_cons (NULL_TREE, integer_type_node,
1963+ tree_cons (NULL_TREE,
1964+ integer_type_node,
1965+ endlink))));
1966+ /* Miscellaneous. */
1967+ tree v8qi_ftype_v4hi_v4hi
1968+ = build_function_type (V8QI_type_node,
1969+ tree_cons (NULL_TREE, V4HI_type_node,
1970+ tree_cons (NULL_TREE, V4HI_type_node,
1971+ endlink)));
1972+ tree v4hi_ftype_v2si_v2si
1973+ = build_function_type (V4HI_type_node,
1974+ tree_cons (NULL_TREE, V2SI_type_node,
1975+ tree_cons (NULL_TREE, V2SI_type_node,
1976+ endlink)));
1977+ tree v2si_ftype_v4hi_v4hi
1978+ = build_function_type (V2SI_type_node,
1979+ tree_cons (NULL_TREE, V4HI_type_node,
1980+ tree_cons (NULL_TREE, V4HI_type_node,
1981+ endlink)));
1982+ tree v2si_ftype_v8qi_v8qi
1983+ = build_function_type (V2SI_type_node,
1984+ tree_cons (NULL_TREE, V8QI_type_node,
1985+ tree_cons (NULL_TREE, V8QI_type_node,
1986+ endlink)));
1987+ tree v4hi_ftype_v4hi_di
1988+ = build_function_type (V4HI_type_node,
1989+ tree_cons (NULL_TREE, V4HI_type_node,
1990+ tree_cons (NULL_TREE,
1991+ long_long_integer_type_node,
1992+ endlink)));
1993+ tree v2si_ftype_v2si_di
1994+ = build_function_type (V2SI_type_node,
1995+ tree_cons (NULL_TREE, V2SI_type_node,
1996+ tree_cons (NULL_TREE,
1997+ long_long_integer_type_node,
1998+ endlink)));
1999+ tree void_ftype_int_int
2000+ = build_function_type (void_type_node,
2001+ tree_cons (NULL_TREE, integer_type_node,
2002+ tree_cons (NULL_TREE, integer_type_node,
2003+ endlink)));
2004+ tree di_ftype_void
2005+ = build_function_type (long_long_unsigned_type_node, endlink);
2006+ tree di_ftype_v8qi
2007+ = build_function_type (long_long_integer_type_node,
2008+ tree_cons (NULL_TREE, V8QI_type_node,
2009+ endlink));
2010+ tree di_ftype_v4hi
2011+ = build_function_type (long_long_integer_type_node,
2012+ tree_cons (NULL_TREE, V4HI_type_node,
2013+ endlink));
2014+ tree di_ftype_v2si
2015+ = build_function_type (long_long_integer_type_node,
2016+ tree_cons (NULL_TREE, V2SI_type_node,
2017+ endlink));
2018+ tree v2si_ftype_v4hi
2019+ = build_function_type (V2SI_type_node,
2020+ tree_cons (NULL_TREE, V4HI_type_node,
2021+ endlink));
2022+ tree v4hi_ftype_v8qi
2023+ = build_function_type (V4HI_type_node,
2024+ tree_cons (NULL_TREE, V8QI_type_node,
2025+ endlink));
2026+
2027+ tree di_ftype_di_v4hi_v4hi
2028+ = build_function_type (long_long_unsigned_type_node,
2029+ tree_cons (NULL_TREE,
2030+ long_long_unsigned_type_node,
2031+ tree_cons (NULL_TREE, V4HI_type_node,
2032+ tree_cons (NULL_TREE,
2033+ V4HI_type_node,
2034+ endlink))));
2035+
2036+ tree di_ftype_v4hi_v4hi
2037+ = build_function_type (long_long_unsigned_type_node,
2038+ tree_cons (NULL_TREE, V4HI_type_node,
2039+ tree_cons (NULL_TREE, V4HI_type_node,
2040+ endlink)));
2041+
2042+ /* Normal vector binops. */
2043+ tree v8qi_ftype_v8qi_v8qi
2044+ = build_function_type (V8QI_type_node,
2045+ tree_cons (NULL_TREE, V8QI_type_node,
2046+ tree_cons (NULL_TREE, V8QI_type_node,
2047+ endlink)));
2048+ tree v4hi_ftype_v4hi_v4hi
2049+ = build_function_type (V4HI_type_node,
2050+ tree_cons (NULL_TREE, V4HI_type_node,
2051+ tree_cons (NULL_TREE, V4HI_type_node,
2052+ endlink)));
2053+ tree v2si_ftype_v2si_v2si
2054+ = build_function_type (V2SI_type_node,
2055+ tree_cons (NULL_TREE, V2SI_type_node,
2056+ tree_cons (NULL_TREE, V2SI_type_node,
2057+ endlink)));
2058+ tree di_ftype_di_di
2059+ = build_function_type (long_long_unsigned_type_node,
2060+ tree_cons (NULL_TREE, long_long_unsigned_type_node,
2061+ tree_cons (NULL_TREE,
2062+ long_long_unsigned_type_node,
2063+ endlink)));
2064+
2065+ /* Add all builtins that are more or less simple operations on two
2066+ operands. */
2067+ for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
2068+ {
2069+ /* Use one of the operands; the target can have a different mode for
2070+ mask-generating compares. */
2071+ enum machine_mode mode;
2072+ tree type;
2073+
2074+ if (d->name == 0)
2075+ continue;
2076+
2077+ mode = insn_data[d->icode].operand[1].mode;
2078+
2079+ switch (mode)
2080+ {
2081+ case V8QImode:
2082+ type = v8qi_ftype_v8qi_v8qi;
2083+ break;
2084+ case V4HImode:
2085+ type = v4hi_ftype_v4hi_v4hi;
2086+ break;
2087+ case V2SImode:
2088+ type = v2si_ftype_v2si_v2si;
2089+ break;
2090+ case DImode:
2091+ type = di_ftype_di_di;
2092+ break;
2093+
2094+ default:
2095+ gcc_unreachable ();
2096+ }
2097+
2098+ def_mbuiltin (d->mask, d->name, type, d->code);
2099+ }
2100+
2101+ /* Add the remaining MMX insns with somewhat more complicated types. */
2102+#define iwmmx_mbuiltin(NAME, TYPE, CODE) \
2103+ def_mbuiltin (FL_IWMMXT, "__builtin_arm_" NAME, (TYPE), \
2104+ ARM_BUILTIN_ ## CODE)
2105+
2106+ iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
2107+ iwmmx_mbuiltin ("setwcx", void_ftype_int_int, SETWCX);
2108+ iwmmx_mbuiltin ("getwcx", int_ftype_int, GETWCX);
2109+
2110+ iwmmx_mbuiltin ("wsllh", v4hi_ftype_v4hi_di, WSLLH);
2111+ iwmmx_mbuiltin ("wsllw", v2si_ftype_v2si_di, WSLLW);
2112+ iwmmx_mbuiltin ("wslld", di_ftype_di_di, WSLLD);
2113+ iwmmx_mbuiltin ("wsllhi", v4hi_ftype_v4hi_int, WSLLHI);
2114+ iwmmx_mbuiltin ("wsllwi", v2si_ftype_v2si_int, WSLLWI);
2115+ iwmmx_mbuiltin ("wslldi", di_ftype_di_int, WSLLDI);
2116+
2117+ iwmmx_mbuiltin ("wsrlh", v4hi_ftype_v4hi_di, WSRLH);
2118+ iwmmx_mbuiltin ("wsrlw", v2si_ftype_v2si_di, WSRLW);
2119+ iwmmx_mbuiltin ("wsrld", di_ftype_di_di, WSRLD);
2120+ iwmmx_mbuiltin ("wsrlhi", v4hi_ftype_v4hi_int, WSRLHI);
2121+ iwmmx_mbuiltin ("wsrlwi", v2si_ftype_v2si_int, WSRLWI);
2122+ iwmmx_mbuiltin ("wsrldi", di_ftype_di_int, WSRLDI);
2123+
2124+ iwmmx_mbuiltin ("wsrah", v4hi_ftype_v4hi_di, WSRAH);
2125+ iwmmx_mbuiltin ("wsraw", v2si_ftype_v2si_di, WSRAW);
2126+ iwmmx_mbuiltin ("wsrad", di_ftype_di_di, WSRAD);
2127+ iwmmx_mbuiltin ("wsrahi", v4hi_ftype_v4hi_int, WSRAHI);
2128+ iwmmx_mbuiltin ("wsrawi", v2si_ftype_v2si_int, WSRAWI);
2129+ iwmmx_mbuiltin ("wsradi", di_ftype_di_int, WSRADI);
2130+
2131+ iwmmx_mbuiltin ("wrorh", v4hi_ftype_v4hi_di, WRORH);
2132+ iwmmx_mbuiltin ("wrorw", v2si_ftype_v2si_di, WRORW);
2133+ iwmmx_mbuiltin ("wrord", di_ftype_di_di, WRORD);
2134+ iwmmx_mbuiltin ("wrorhi", v4hi_ftype_v4hi_int, WRORHI);
2135+ iwmmx_mbuiltin ("wrorwi", v2si_ftype_v2si_int, WRORWI);
2136+ iwmmx_mbuiltin ("wrordi", di_ftype_di_int, WRORDI);
2137+
2138+ iwmmx_mbuiltin ("wshufh", v4hi_ftype_v4hi_int, WSHUFH);
2139+
2140+ iwmmx_mbuiltin ("wsadb", v2si_ftype_v8qi_v8qi, WSADB);
2141+ iwmmx_mbuiltin ("wsadh", v2si_ftype_v4hi_v4hi, WSADH);
2142+ iwmmx_mbuiltin ("wsadbz", v2si_ftype_v8qi_v8qi, WSADBZ);
2143+ iwmmx_mbuiltin ("wsadhz", v2si_ftype_v4hi_v4hi, WSADHZ);
2144+
2145+ iwmmx_mbuiltin ("textrmsb", int_ftype_v8qi_int, TEXTRMSB);
2146+ iwmmx_mbuiltin ("textrmsh", int_ftype_v4hi_int, TEXTRMSH);
2147+ iwmmx_mbuiltin ("textrmsw", int_ftype_v2si_int, TEXTRMSW);
2148+ iwmmx_mbuiltin ("textrmub", int_ftype_v8qi_int, TEXTRMUB);
2149+ iwmmx_mbuiltin ("textrmuh", int_ftype_v4hi_int, TEXTRMUH);
2150+ iwmmx_mbuiltin ("textrmuw", int_ftype_v2si_int, TEXTRMUW);
2151+ iwmmx_mbuiltin ("tinsrb", v8qi_ftype_v8qi_int_int, TINSRB);
2152+ iwmmx_mbuiltin ("tinsrh", v4hi_ftype_v4hi_int_int, TINSRH);
2153+ iwmmx_mbuiltin ("tinsrw", v2si_ftype_v2si_int_int, TINSRW);
2154+
2155+ iwmmx_mbuiltin ("waccb", di_ftype_v8qi, WACCB);
2156+ iwmmx_mbuiltin ("wacch", di_ftype_v4hi, WACCH);
2157+ iwmmx_mbuiltin ("waccw", di_ftype_v2si, WACCW);
2158+
2159+ iwmmx_mbuiltin ("tmovmskb", int_ftype_v8qi, TMOVMSKB);
2160+ iwmmx_mbuiltin ("tmovmskh", int_ftype_v4hi, TMOVMSKH);
2161+ iwmmx_mbuiltin ("tmovmskw", int_ftype_v2si, TMOVMSKW);
2162+
2163+ iwmmx_mbuiltin ("wpackhss", v8qi_ftype_v4hi_v4hi, WPACKHSS);
2164+ iwmmx_mbuiltin ("wpackhus", v8qi_ftype_v4hi_v4hi, WPACKHUS);
2165+ iwmmx_mbuiltin ("wpackwus", v4hi_ftype_v2si_v2si, WPACKWUS);
2166+ iwmmx_mbuiltin ("wpackwss", v4hi_ftype_v2si_v2si, WPACKWSS);
2167+ iwmmx_mbuiltin ("wpackdus", v2si_ftype_di_di, WPACKDUS);
2168+ iwmmx_mbuiltin ("wpackdss", v2si_ftype_di_di, WPACKDSS);
2169+
2170+ iwmmx_mbuiltin ("wunpckehub", v4hi_ftype_v8qi, WUNPCKEHUB);
2171+ iwmmx_mbuiltin ("wunpckehuh", v2si_ftype_v4hi, WUNPCKEHUH);
2172+ iwmmx_mbuiltin ("wunpckehuw", di_ftype_v2si, WUNPCKEHUW);
2173+ iwmmx_mbuiltin ("wunpckehsb", v4hi_ftype_v8qi, WUNPCKEHSB);
2174+ iwmmx_mbuiltin ("wunpckehsh", v2si_ftype_v4hi, WUNPCKEHSH);
2175+ iwmmx_mbuiltin ("wunpckehsw", di_ftype_v2si, WUNPCKEHSW);
2176+ iwmmx_mbuiltin ("wunpckelub", v4hi_ftype_v8qi, WUNPCKELUB);
2177+ iwmmx_mbuiltin ("wunpckeluh", v2si_ftype_v4hi, WUNPCKELUH);
2178+ iwmmx_mbuiltin ("wunpckeluw", di_ftype_v2si, WUNPCKELUW);
2179+ iwmmx_mbuiltin ("wunpckelsb", v4hi_ftype_v8qi, WUNPCKELSB);
2180+ iwmmx_mbuiltin ("wunpckelsh", v2si_ftype_v4hi, WUNPCKELSH);
2181+ iwmmx_mbuiltin ("wunpckelsw", di_ftype_v2si, WUNPCKELSW);
2182+
2183+ iwmmx_mbuiltin ("wmacs", di_ftype_di_v4hi_v4hi, WMACS);
2184+ iwmmx_mbuiltin ("wmacsz", di_ftype_v4hi_v4hi, WMACSZ);
2185+ iwmmx_mbuiltin ("wmacu", di_ftype_di_v4hi_v4hi, WMACU);
2186+ iwmmx_mbuiltin ("wmacuz", di_ftype_v4hi_v4hi, WMACUZ);
2187+
2188+ iwmmx_mbuiltin ("walign", v8qi_ftype_v8qi_v8qi_int, WALIGN);
2189+ iwmmx_mbuiltin ("tmia", di_ftype_di_int_int, TMIA);
2190+ iwmmx_mbuiltin ("tmiaph", di_ftype_di_int_int, TMIAPH);
2191+ iwmmx_mbuiltin ("tmiabb", di_ftype_di_int_int, TMIABB);
2192+ iwmmx_mbuiltin ("tmiabt", di_ftype_di_int_int, TMIABT);
2193+ iwmmx_mbuiltin ("tmiatb", di_ftype_di_int_int, TMIATB);
2194+ iwmmx_mbuiltin ("tmiatt", di_ftype_di_int_int, TMIATT);
2195+
2196+#undef iwmmx_mbuiltin
2197+}
2198+
2199+static void
2200+arm_init_tls_builtins (void)
2201+{
2202+ tree ftype, decl;
2203+
2204+ ftype = build_function_type (ptr_type_node, void_list_node);
2205+ decl = add_builtin_function ("__builtin_thread_pointer", ftype,
2206+ ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
2207+ NULL, NULL_TREE);
2208+ TREE_NOTHROW (decl) = 1;
2209+ TREE_READONLY (decl) = 1;
2210+ arm_builtin_decls[ARM_BUILTIN_THREAD_POINTER] = decl;
2211 }
2212
2213 static void
2214@@ -19479,6 +19662,17 @@
2215 arm_init_fp16_builtins ();
2216 }
2217
2218+/* Return the ARM builtin for CODE. */
2219+
2220+static tree
2221+arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
2222+{
2223+ if (code >= ARM_BUILTIN_MAX)
2224+ return error_mark_node;
2225+
2226+ return arm_builtin_decls[code];
2227+}
2228+
2229 /* Implement TARGET_INVALID_PARAMETER_TYPE. */
2230
2231 static const char *
2232@@ -19630,58 +19824,6 @@
2233 return target;
2234 }
2235
2236-static int
2237-neon_builtin_compare (const void *a, const void *b)
2238-{
2239- const neon_builtin_datum *const key = (const neon_builtin_datum *) a;
2240- const neon_builtin_datum *const memb = (const neon_builtin_datum *) b;
2241- unsigned int soughtcode = key->base_fcode;
2242-
2243- if (soughtcode >= memb->base_fcode
2244- && soughtcode < memb->base_fcode + memb->num_vars)
2245- return 0;
2246- else if (soughtcode < memb->base_fcode)
2247- return -1;
2248- else
2249- return 1;
2250-}
2251-
2252-static enum insn_code
2253-locate_neon_builtin_icode (int fcode, neon_itype *itype,
2254- enum neon_builtin_type_bits *type_bit)
2255-{
2256- neon_builtin_datum key
2257- = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 };
2258- neon_builtin_datum *found;
2259- int idx, type, ntypes;
2260-
2261- key.base_fcode = fcode;
2262- found = (neon_builtin_datum *)
2263- bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data),
2264- sizeof (neon_builtin_data[0]), neon_builtin_compare);
2265- gcc_assert (found);
2266- idx = fcode - (int) found->base_fcode;
2267- gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars);
2268-
2269- if (itype)
2270- *itype = found->itype;
2271-
2272- if (type_bit)
2273- {
2274- ntypes = 0;
2275- for (type = 0; type < T_MAX; type++)
2276- if (found->bits & (1 << type))
2277- {
2278- if (ntypes == idx)
2279- break;
2280- ntypes++;
2281- }
2282- gcc_assert (type < T_MAX);
2283- *type_bit = (enum neon_builtin_type_bits) (1 << type);
2284- }
2285- return found->codes[idx];
2286-}
2287-
2288 typedef enum {
2289 NEON_ARG_COPY_TO_REG,
2290 NEON_ARG_CONSTANT,
2291@@ -19695,14 +19837,14 @@
2292 and return an expression for the accessed memory.
2293
2294 The intrinsic function operates on a block of registers that has
2295- mode REG_MODE. This block contains vectors of type TYPE_BIT.
2296+ mode REG_MODE. This block contains vectors of type TYPE_MODE.
2297 The function references the memory at EXP in mode MEM_MODE;
2298 this mode may be BLKmode if no more suitable mode is available. */
2299
2300 static tree
2301 neon_dereference_pointer (tree exp, enum machine_mode mem_mode,
2302 enum machine_mode reg_mode,
2303- enum neon_builtin_type_bits type_bit)
2304+ neon_builtin_type_mode type_mode)
2305 {
2306 HOST_WIDE_INT reg_size, vector_size, nvectors, nelems;
2307 tree elem_type, upper_bound, array_type;
2308@@ -19711,8 +19853,8 @@
2309 reg_size = GET_MODE_SIZE (reg_mode);
2310
2311 /* Work out the size of each vector in bytes. */
2312- gcc_assert (type_bit & (T_DREG | T_QREG));
2313- vector_size = (type_bit & T_QREG ? 16 : 8);
2314+ gcc_assert (TYPE_MODE_BIT (type_mode) & (TB_DREG | TB_QREG));
2315+ vector_size = (TYPE_MODE_BIT (type_mode) & TB_QREG ? 16 : 8);
2316
2317 /* Work out how many vectors there are. */
2318 gcc_assert (reg_size % vector_size == 0);
2319@@ -19743,7 +19885,7 @@
2320 /* Expand a Neon builtin. */
2321 static rtx
2322 arm_expand_neon_args (rtx target, int icode, int have_retval,
2323- enum neon_builtin_type_bits type_bit,
2324+ neon_builtin_type_mode type_mode,
2325 tree exp, ...)
2326 {
2327 va_list ap;
2328@@ -19779,7 +19921,7 @@
2329 {
2330 other_mode = insn_data[icode].operand[1 - opno].mode;
2331 arg[argc] = neon_dereference_pointer (arg[argc], mode[argc],
2332- other_mode, type_bit);
2333+ other_mode, type_mode);
2334 }
2335 op[argc] = expand_normal (arg[argc]);
2336
2337@@ -19889,16 +20031,17 @@
2338 static rtx
2339 arm_expand_neon_builtin (int fcode, tree exp, rtx target)
2340 {
2341- neon_itype itype;
2342- enum neon_builtin_type_bits type_bit;
2343- enum insn_code icode = locate_neon_builtin_icode (fcode, &itype, &type_bit);
2344+ neon_builtin_datum *d = &neon_builtin_data[fcode - ARM_BUILTIN_NEON_BASE];
2345+ neon_itype itype = d->itype;
2346+ enum insn_code icode = d->code;
2347+ neon_builtin_type_mode type_mode = d->mode;
2348
2349 switch (itype)
2350 {
2351 case NEON_UNOP:
2352 case NEON_CONVERT:
2353 case NEON_DUPLANE:
2354- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2355+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2356 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
2357
2358 case NEON_BINOP:
2359@@ -19908,89 +20051,89 @@
2360 case NEON_SCALARMULH:
2361 case NEON_SHIFTINSERT:
2362 case NEON_LOGICBINOP:
2363- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2364+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2365 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2366 NEON_ARG_STOP);
2367
2368 case NEON_TERNOP:
2369- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2370+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2371 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2372 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2373
2374 case NEON_GETLANE:
2375 case NEON_FIXCONV:
2376 case NEON_SHIFTIMM:
2377- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2378+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2379 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
2380 NEON_ARG_STOP);
2381
2382 case NEON_CREATE:
2383- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2384+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2385 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2386
2387 case NEON_DUP:
2388 case NEON_SPLIT:
2389 case NEON_REINTERP:
2390- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2391+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2392 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2393
2394 case NEON_COMBINE:
2395 case NEON_VTBL:
2396- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2397+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2398 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2399
2400 case NEON_RESULTPAIR:
2401- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2402+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2403 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2404 NEON_ARG_STOP);
2405
2406 case NEON_LANEMUL:
2407 case NEON_LANEMULL:
2408 case NEON_LANEMULH:
2409- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2410+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2411 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2412 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2413
2414 case NEON_LANEMAC:
2415- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2416+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2417 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2418 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
2419
2420 case NEON_SHIFTACC:
2421- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2422+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2423 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2424 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2425
2426 case NEON_SCALARMAC:
2427- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2428+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2429 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2430 NEON_ARG_CONSTANT, NEON_ARG_STOP);
2431
2432 case NEON_SELECT:
2433 case NEON_VTBX:
2434- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2435+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2436 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
2437 NEON_ARG_STOP);
2438
2439 case NEON_LOAD1:
2440 case NEON_LOADSTRUCT:
2441- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2442+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2443 NEON_ARG_MEMORY, NEON_ARG_STOP);
2444
2445 case NEON_LOAD1LANE:
2446 case NEON_LOADSTRUCTLANE:
2447- return arm_expand_neon_args (target, icode, 1, type_bit, exp,
2448+ return arm_expand_neon_args (target, icode, 1, type_mode, exp,
2449 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2450 NEON_ARG_STOP);
2451
2452 case NEON_STORE1:
2453 case NEON_STORESTRUCT:
2454- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2455+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2456 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
2457
2458 case NEON_STORE1LANE:
2459 case NEON_STORESTRUCTLANE:
2460- return arm_expand_neon_args (target, icode, 0, type_bit, exp,
2461+ return arm_expand_neon_args (target, icode, 0, type_mode, exp,
2462 NEON_ARG_MEMORY, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
2463 NEON_ARG_STOP);
2464 }
2465
2466=== modified file 'gcc/config/arm/arm.h'
2467--- old/gcc/config/arm/arm.h 2011-08-13 08:32:32 +0000
2468+++ new/gcc/config/arm/arm.h 2011-08-24 17:35:16 +0000
2469@@ -2269,178 +2269,6 @@
2470 : arm_gen_return_addr_mask ())
2471
2472
2473-/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2474- symbolic names defined here (which would require too much duplication).
2475- FIXME? */
2476-enum arm_builtins
2477-{
2478- ARM_BUILTIN_GETWCX,
2479- ARM_BUILTIN_SETWCX,
2480-
2481- ARM_BUILTIN_WZERO,
2482-
2483- ARM_BUILTIN_WAVG2BR,
2484- ARM_BUILTIN_WAVG2HR,
2485- ARM_BUILTIN_WAVG2B,
2486- ARM_BUILTIN_WAVG2H,
2487-
2488- ARM_BUILTIN_WACCB,
2489- ARM_BUILTIN_WACCH,
2490- ARM_BUILTIN_WACCW,
2491-
2492- ARM_BUILTIN_WMACS,
2493- ARM_BUILTIN_WMACSZ,
2494- ARM_BUILTIN_WMACU,
2495- ARM_BUILTIN_WMACUZ,
2496-
2497- ARM_BUILTIN_WSADB,
2498- ARM_BUILTIN_WSADBZ,
2499- ARM_BUILTIN_WSADH,
2500- ARM_BUILTIN_WSADHZ,
2501-
2502- ARM_BUILTIN_WALIGN,
2503-
2504- ARM_BUILTIN_TMIA,
2505- ARM_BUILTIN_TMIAPH,
2506- ARM_BUILTIN_TMIABB,
2507- ARM_BUILTIN_TMIABT,
2508- ARM_BUILTIN_TMIATB,
2509- ARM_BUILTIN_TMIATT,
2510-
2511- ARM_BUILTIN_TMOVMSKB,
2512- ARM_BUILTIN_TMOVMSKH,
2513- ARM_BUILTIN_TMOVMSKW,
2514-
2515- ARM_BUILTIN_TBCSTB,
2516- ARM_BUILTIN_TBCSTH,
2517- ARM_BUILTIN_TBCSTW,
2518-
2519- ARM_BUILTIN_WMADDS,
2520- ARM_BUILTIN_WMADDU,
2521-
2522- ARM_BUILTIN_WPACKHSS,
2523- ARM_BUILTIN_WPACKWSS,
2524- ARM_BUILTIN_WPACKDSS,
2525- ARM_BUILTIN_WPACKHUS,
2526- ARM_BUILTIN_WPACKWUS,
2527- ARM_BUILTIN_WPACKDUS,
2528-
2529- ARM_BUILTIN_WADDB,
2530- ARM_BUILTIN_WADDH,
2531- ARM_BUILTIN_WADDW,
2532- ARM_BUILTIN_WADDSSB,
2533- ARM_BUILTIN_WADDSSH,
2534- ARM_BUILTIN_WADDSSW,
2535- ARM_BUILTIN_WADDUSB,
2536- ARM_BUILTIN_WADDUSH,
2537- ARM_BUILTIN_WADDUSW,
2538- ARM_BUILTIN_WSUBB,
2539- ARM_BUILTIN_WSUBH,
2540- ARM_BUILTIN_WSUBW,
2541- ARM_BUILTIN_WSUBSSB,
2542- ARM_BUILTIN_WSUBSSH,
2543- ARM_BUILTIN_WSUBSSW,
2544- ARM_BUILTIN_WSUBUSB,
2545- ARM_BUILTIN_WSUBUSH,
2546- ARM_BUILTIN_WSUBUSW,
2547-
2548- ARM_BUILTIN_WAND,
2549- ARM_BUILTIN_WANDN,
2550- ARM_BUILTIN_WOR,
2551- ARM_BUILTIN_WXOR,
2552-
2553- ARM_BUILTIN_WCMPEQB,
2554- ARM_BUILTIN_WCMPEQH,
2555- ARM_BUILTIN_WCMPEQW,
2556- ARM_BUILTIN_WCMPGTUB,
2557- ARM_BUILTIN_WCMPGTUH,
2558- ARM_BUILTIN_WCMPGTUW,
2559- ARM_BUILTIN_WCMPGTSB,
2560- ARM_BUILTIN_WCMPGTSH,
2561- ARM_BUILTIN_WCMPGTSW,
2562-
2563- ARM_BUILTIN_TEXTRMSB,
2564- ARM_BUILTIN_TEXTRMSH,
2565- ARM_BUILTIN_TEXTRMSW,
2566- ARM_BUILTIN_TEXTRMUB,
2567- ARM_BUILTIN_TEXTRMUH,
2568- ARM_BUILTIN_TEXTRMUW,
2569- ARM_BUILTIN_TINSRB,
2570- ARM_BUILTIN_TINSRH,
2571- ARM_BUILTIN_TINSRW,
2572-
2573- ARM_BUILTIN_WMAXSW,
2574- ARM_BUILTIN_WMAXSH,
2575- ARM_BUILTIN_WMAXSB,
2576- ARM_BUILTIN_WMAXUW,
2577- ARM_BUILTIN_WMAXUH,
2578- ARM_BUILTIN_WMAXUB,
2579- ARM_BUILTIN_WMINSW,
2580- ARM_BUILTIN_WMINSH,
2581- ARM_BUILTIN_WMINSB,
2582- ARM_BUILTIN_WMINUW,
2583- ARM_BUILTIN_WMINUH,
2584- ARM_BUILTIN_WMINUB,
2585-
2586- ARM_BUILTIN_WMULUM,
2587- ARM_BUILTIN_WMULSM,
2588- ARM_BUILTIN_WMULUL,
2589-
2590- ARM_BUILTIN_PSADBH,
2591- ARM_BUILTIN_WSHUFH,
2592-
2593- ARM_BUILTIN_WSLLH,
2594- ARM_BUILTIN_WSLLW,
2595- ARM_BUILTIN_WSLLD,
2596- ARM_BUILTIN_WSRAH,
2597- ARM_BUILTIN_WSRAW,
2598- ARM_BUILTIN_WSRAD,
2599- ARM_BUILTIN_WSRLH,
2600- ARM_BUILTIN_WSRLW,
2601- ARM_BUILTIN_WSRLD,
2602- ARM_BUILTIN_WRORH,
2603- ARM_BUILTIN_WRORW,
2604- ARM_BUILTIN_WRORD,
2605- ARM_BUILTIN_WSLLHI,
2606- ARM_BUILTIN_WSLLWI,
2607- ARM_BUILTIN_WSLLDI,
2608- ARM_BUILTIN_WSRAHI,
2609- ARM_BUILTIN_WSRAWI,
2610- ARM_BUILTIN_WSRADI,
2611- ARM_BUILTIN_WSRLHI,
2612- ARM_BUILTIN_WSRLWI,
2613- ARM_BUILTIN_WSRLDI,
2614- ARM_BUILTIN_WRORHI,
2615- ARM_BUILTIN_WRORWI,
2616- ARM_BUILTIN_WRORDI,
2617-
2618- ARM_BUILTIN_WUNPCKIHB,
2619- ARM_BUILTIN_WUNPCKIHH,
2620- ARM_BUILTIN_WUNPCKIHW,
2621- ARM_BUILTIN_WUNPCKILB,
2622- ARM_BUILTIN_WUNPCKILH,
2623- ARM_BUILTIN_WUNPCKILW,
2624-
2625- ARM_BUILTIN_WUNPCKEHSB,
2626- ARM_BUILTIN_WUNPCKEHSH,
2627- ARM_BUILTIN_WUNPCKEHSW,
2628- ARM_BUILTIN_WUNPCKEHUB,
2629- ARM_BUILTIN_WUNPCKEHUH,
2630- ARM_BUILTIN_WUNPCKEHUW,
2631- ARM_BUILTIN_WUNPCKELSB,
2632- ARM_BUILTIN_WUNPCKELSH,
2633- ARM_BUILTIN_WUNPCKELSW,
2634- ARM_BUILTIN_WUNPCKELUB,
2635- ARM_BUILTIN_WUNPCKELUH,
2636- ARM_BUILTIN_WUNPCKELUW,
2637-
2638- ARM_BUILTIN_THREAD_POINTER,
2639-
2640- ARM_BUILTIN_NEON_BASE,
2641-
2642- ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
2643-};
2644-
2645 /* Do not emit .note.GNU-stack by default. */
2646 #ifndef NEED_INDICATE_EXEC_STACK
2647 #define NEED_INDICATE_EXEC_STACK 0
2648
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
new file mode 100644
index 0000000000..1a940975f3
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106796.patch
@@ -0,0 +1,1255 @@
12011-08-25 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * tree-ssa-math-opts.c (is_widening_mult_rhs_p): Handle constants
9 beyond conversions.
10 (convert_mult_to_widen): Convert constant inputs to the right type.
11 (convert_plusminus_to_widen): Don't automatically reject inputs that
12 are not an SSA_NAME.
13 Convert constant inputs to the right type.
14
15 gcc/testsuite/
16 * gcc.target/arm/wmul-11.c: New file.
17 * gcc.target/arm/wmul-12.c: New file.
18 * gcc.target/arm/wmul-13.c: New file.
19
20 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
21
22 gcc/
23 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Convert add_rhs
24 to the correct type.
25
26 gcc/testsuite/
27 * gcc.target/arm/wmul-10.c: New file.
28
29 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
30
31 gcc/
32 * tree-ssa-math-opts.c (convert_mult_to_widen): Better handle
33 unsigned inputs of different modes.
34 (convert_plusminus_to_widen): Likewise.
35
36 gcc/testsuite/
37 * gcc.target/arm/wmul-9.c: New file.
38 * gcc.target/arm/wmul-bitfield-2.c: New file.
39
40 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
41
42 gcc/
43 * tree-ssa-math-opts.c (is_widening_mult_rhs_p): Add new argument
44 'type'.
45 Use 'type' from caller, not inferred from 'rhs'.
46 Don't reject non-conversion statements. Do return lhs in this case.
47 (is_widening_mult_p): Add new argument 'type'.
48 Use 'type' from caller, not inferred from 'stmt'.
49 Pass type to is_widening_mult_rhs_p.
50 (convert_mult_to_widen): Pass type to is_widening_mult_p.
51 (convert_plusminus_to_widen): Likewise.
52
53 gcc/testsuite/
54 * gcc.target/arm/wmul-8.c: New file.
55
56 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
57
58 gcc/
59 * tree-ssa-math-opts.c (is_widening_mult_p): Remove FIXME.
60 Ensure the the larger type is the first operand.
61
62 gcc/testsuite/
63 * gcc.target/arm/wmul-7.c: New file.
64
65 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
66
67 gcc/
68 * tree-ssa-math-opts.c (convert_mult_to_widen): Convert
69 unsupported unsigned multiplies to signed.
70 (convert_plusminus_to_widen): Likewise.
71
72 gcc/testsuite/
73 * gcc.target/arm/wmul-6.c: New file.
74
75 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
76
77 gcc/
78 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Permit a single
79 conversion statement separating multiply-and-accumulate.
80
81 gcc/testsuite/
82 * gcc.target/arm/wmul-5.c: New file.
83 * gcc.target/arm/no-wmla-1.c: New file.
84
85 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
86
87 gcc/
88 * config/arm/arm.md (maddhidi4): Remove '*' from name.
89 * expr.c (expand_expr_real_2): Use find_widening_optab_handler.
90 * optabs.c (find_widening_optab_handler_and_mode): New function.
91 (expand_widen_pattern_expr): Use find_widening_optab_handler.
92 (expand_binop_directly): Likewise.
93 (expand_binop): Likewise.
94 * optabs.h (find_widening_optab_handler): New macro define.
95 (find_widening_optab_handler_and_mode): New prototype.
96 * tree-cfg.c (verify_gimple_assign_binary): Adjust WIDEN_MULT_EXPR
97 type precision rules.
98 (verify_gimple_assign_ternary): Likewise for WIDEN_MULT_PLUS_EXPR.
99 * tree-ssa-math-opts.c (build_and_insert_cast): New function.
100 (is_widening_mult_rhs_p): Allow widening by more than one mode.
101 Explicitly disallow mis-matched input types.
102 (convert_mult_to_widen): Use find_widening_optab_handler, and cast
103 input types to fit the new handler.
104 (convert_plusminus_to_widen): Likewise.
105
106 gcc/testsuite/
107 * gcc.target/arm/wmul-bitfield-1.c: New file.
108
109 2011-08-19 Andrew Stubbs <ams@codesourcery.com>
110
111 gcc/
112 * expr.c (expand_expr_real_2): Use widening_optab_handler.
113 * genopinit.c (optabs): Use set_widening_optab_handler for $N.
114 (gen_insn): $N now means $a must be wider than $b, not consecutive.
115 * optabs.c (widened_mode): New function.
116 (expand_widen_pattern_expr): Use widening_optab_handler.
117 (expand_binop_directly): Likewise.
118 (expand_binop): Likewise.
119 * optabs.h (widening_optab_handlers): New struct.
120 (optab_d): New member, 'widening'.
121 (widening_optab_handler): New function.
122 (set_widening_optab_handler): New function.
123 * tree-ssa-math-opts.c (convert_mult_to_widen): Use
124 widening_optab_handler.
125 (convert_plusminus_to_widen): Likewise.
126
127=== modified file 'gcc/config/arm/arm.md'
128--- old/gcc/config/arm/arm.md 2011-08-13 08:32:32 +0000
129+++ new/gcc/config/arm/arm.md 2011-08-25 11:42:09 +0000
130@@ -1839,7 +1839,7 @@
131 (set_attr "predicable" "yes")]
132 )
133
134-(define_insn "*maddhidi4"
135+(define_insn "maddhidi4"
136 [(set (match_operand:DI 0 "s_register_operand" "=r")
137 (plus:DI
138 (mult:DI (sign_extend:DI
139
140=== modified file 'gcc/expr.c'
141--- old/gcc/expr.c 2011-08-13 08:32:32 +0000
142+++ new/gcc/expr.c 2011-08-25 11:42:09 +0000
143@@ -7688,18 +7688,16 @@
144 {
145 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (treeop0));
146 this_optab = usmul_widen_optab;
147- if (mode == GET_MODE_2XWIDER_MODE (innermode))
148+ if (find_widening_optab_handler (this_optab, mode, innermode, 0)
149+ != CODE_FOR_nothing)
150 {
151- if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
152- {
153- if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
154- expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
155- EXPAND_NORMAL);
156- else
157- expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
158- EXPAND_NORMAL);
159- goto binop3;
160- }
161+ if (TYPE_UNSIGNED (TREE_TYPE (treeop0)))
162+ expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
163+ EXPAND_NORMAL);
164+ else
165+ expand_operands (treeop0, treeop1, NULL_RTX, &op1, &op0,
166+ EXPAND_NORMAL);
167+ goto binop3;
168 }
169 }
170 /* Check for a multiplication with matching signedness. */
171@@ -7714,10 +7712,10 @@
172 optab other_optab = zextend_p ? smul_widen_optab : umul_widen_optab;
173 this_optab = zextend_p ? umul_widen_optab : smul_widen_optab;
174
175- if (mode == GET_MODE_2XWIDER_MODE (innermode)
176- && TREE_CODE (treeop0) != INTEGER_CST)
177+ if (TREE_CODE (treeop0) != INTEGER_CST)
178 {
179- if (optab_handler (this_optab, mode) != CODE_FOR_nothing)
180+ if (find_widening_optab_handler (this_optab, mode, innermode, 0)
181+ != CODE_FOR_nothing)
182 {
183 expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1,
184 EXPAND_NORMAL);
185@@ -7725,7 +7723,8 @@
186 unsignedp, this_optab);
187 return REDUCE_BIT_FIELD (temp);
188 }
189- if (optab_handler (other_optab, mode) != CODE_FOR_nothing
190+ if (find_widening_optab_handler (other_optab, mode, innermode, 0)
191+ != CODE_FOR_nothing
192 && innermode == word_mode)
193 {
194 rtx htem, hipart;
195
196=== modified file 'gcc/genopinit.c'
197--- old/gcc/genopinit.c 2011-05-05 15:43:06 +0000
198+++ new/gcc/genopinit.c 2011-07-15 13:06:31 +0000
199@@ -46,10 +46,12 @@
200 used. $A and $B are replaced with the full name of the mode; $a and $b
201 are replaced with the short form of the name, as above.
202
203- If $N is present in the pattern, it means the two modes must be consecutive
204- widths in the same mode class (e.g, QImode and HImode). $I means that
205- only full integer modes should be considered for the next mode, and $F
206- means that only float modes should be considered.
207+ If $N is present in the pattern, it means the two modes must be in
208+ the same mode class, and $b must be greater than $a (e.g, QImode
209+ and HImode).
210+
211+ $I means that only full integer modes should be considered for the
212+ next mode, and $F means that only float modes should be considered.
213 $P means that both full and partial integer modes should be considered.
214 $Q means that only fixed-point modes should be considered.
215
216@@ -99,17 +101,17 @@
217 "set_optab_handler (smulv_optab, $A, CODE_FOR_$(mulv$I$a3$))",
218 "set_optab_handler (umul_highpart_optab, $A, CODE_FOR_$(umul$a3_highpart$))",
219 "set_optab_handler (smul_highpart_optab, $A, CODE_FOR_$(smul$a3_highpart$))",
220- "set_optab_handler (smul_widen_optab, $B, CODE_FOR_$(mul$a$b3$)$N)",
221- "set_optab_handler (umul_widen_optab, $B, CODE_FOR_$(umul$a$b3$)$N)",
222- "set_optab_handler (usmul_widen_optab, $B, CODE_FOR_$(usmul$a$b3$)$N)",
223- "set_optab_handler (smadd_widen_optab, $B, CODE_FOR_$(madd$a$b4$)$N)",
224- "set_optab_handler (umadd_widen_optab, $B, CODE_FOR_$(umadd$a$b4$)$N)",
225- "set_optab_handler (ssmadd_widen_optab, $B, CODE_FOR_$(ssmadd$a$b4$)$N)",
226- "set_optab_handler (usmadd_widen_optab, $B, CODE_FOR_$(usmadd$a$b4$)$N)",
227- "set_optab_handler (smsub_widen_optab, $B, CODE_FOR_$(msub$a$b4$)$N)",
228- "set_optab_handler (umsub_widen_optab, $B, CODE_FOR_$(umsub$a$b4$)$N)",
229- "set_optab_handler (ssmsub_widen_optab, $B, CODE_FOR_$(ssmsub$a$b4$)$N)",
230- "set_optab_handler (usmsub_widen_optab, $B, CODE_FOR_$(usmsub$a$b4$)$N)",
231+ "set_widening_optab_handler (smul_widen_optab, $B, $A, CODE_FOR_$(mul$a$b3$)$N)",
232+ "set_widening_optab_handler (umul_widen_optab, $B, $A, CODE_FOR_$(umul$a$b3$)$N)",
233+ "set_widening_optab_handler (usmul_widen_optab, $B, $A, CODE_FOR_$(usmul$a$b3$)$N)",
234+ "set_widening_optab_handler (smadd_widen_optab, $B, $A, CODE_FOR_$(madd$a$b4$)$N)",
235+ "set_widening_optab_handler (umadd_widen_optab, $B, $A, CODE_FOR_$(umadd$a$b4$)$N)",
236+ "set_widening_optab_handler (ssmadd_widen_optab, $B, $A, CODE_FOR_$(ssmadd$a$b4$)$N)",
237+ "set_widening_optab_handler (usmadd_widen_optab, $B, $A, CODE_FOR_$(usmadd$a$b4$)$N)",
238+ "set_widening_optab_handler (smsub_widen_optab, $B, $A, CODE_FOR_$(msub$a$b4$)$N)",
239+ "set_widening_optab_handler (umsub_widen_optab, $B, $A, CODE_FOR_$(umsub$a$b4$)$N)",
240+ "set_widening_optab_handler (ssmsub_widen_optab, $B, $A, CODE_FOR_$(ssmsub$a$b4$)$N)",
241+ "set_widening_optab_handler (usmsub_widen_optab, $B, $A, CODE_FOR_$(usmsub$a$b4$)$N)",
242 "set_optab_handler (sdiv_optab, $A, CODE_FOR_$(div$a3$))",
243 "set_optab_handler (ssdiv_optab, $A, CODE_FOR_$(ssdiv$Q$a3$))",
244 "set_optab_handler (sdivv_optab, $A, CODE_FOR_$(div$V$I$a3$))",
245@@ -304,7 +306,7 @@
246 {
247 int force_float = 0, force_int = 0, force_partial_int = 0;
248 int force_fixed = 0;
249- int force_consec = 0;
250+ int force_wider = 0;
251 int matches = 1;
252
253 for (pp = optabs[pindex]; pp[0] != '$' || pp[1] != '('; pp++)
254@@ -322,7 +324,7 @@
255 switch (*++pp)
256 {
257 case 'N':
258- force_consec = 1;
259+ force_wider = 1;
260 break;
261 case 'I':
262 force_int = 1;
263@@ -391,7 +393,10 @@
264 || mode_class[i] == MODE_VECTOR_FRACT
265 || mode_class[i] == MODE_VECTOR_UFRACT
266 || mode_class[i] == MODE_VECTOR_ACCUM
267- || mode_class[i] == MODE_VECTOR_UACCUM))
268+ || mode_class[i] == MODE_VECTOR_UACCUM)
269+ && (! force_wider
270+ || *pp == 'a'
271+ || m1 < i))
272 break;
273 }
274
275@@ -411,8 +416,7 @@
276 }
277
278 if (matches && pp[0] == '$' && pp[1] == ')'
279- && *np == 0
280- && (! force_consec || (int) GET_MODE_WIDER_MODE(m1) == m2))
281+ && *np == 0)
282 break;
283 }
284
285
286=== modified file 'gcc/optabs.c'
287--- old/gcc/optabs.c 2011-07-04 14:03:49 +0000
288+++ new/gcc/optabs.c 2011-08-11 15:46:01 +0000
289@@ -225,6 +225,61 @@
290 return 1;
291 }
292
293+/* Given two input operands, OP0 and OP1, determine what the correct from_mode
294+ for a widening operation would be. In most cases this would be OP0, but if
295+ that's a constant it'll be VOIDmode, which isn't useful. */
296+
297+static enum machine_mode
298+widened_mode (enum machine_mode to_mode, rtx op0, rtx op1)
299+{
300+ enum machine_mode m0 = GET_MODE (op0);
301+ enum machine_mode m1 = GET_MODE (op1);
302+ enum machine_mode result;
303+
304+ if (m0 == VOIDmode && m1 == VOIDmode)
305+ return to_mode;
306+ else if (m0 == VOIDmode || GET_MODE_SIZE (m0) < GET_MODE_SIZE (m1))
307+ result = m1;
308+ else
309+ result = m0;
310+
311+ if (GET_MODE_SIZE (result) > GET_MODE_SIZE (to_mode))
312+ return to_mode;
313+
314+ return result;
315+}
316+
317+/* Find a widening optab even if it doesn't widen as much as we want.
318+ E.g. if from_mode is HImode, and to_mode is DImode, and there is no
319+ direct HI->SI insn, then return SI->DI, if that exists.
320+ If PERMIT_NON_WIDENING is non-zero then this can be used with
321+ non-widening optabs also. */
322+
323+enum insn_code
324+find_widening_optab_handler_and_mode (optab op, enum machine_mode to_mode,
325+ enum machine_mode from_mode,
326+ int permit_non_widening,
327+ enum machine_mode *found_mode)
328+{
329+ for (; (permit_non_widening || from_mode != to_mode)
330+ && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode)
331+ && from_mode != VOIDmode;
332+ from_mode = GET_MODE_WIDER_MODE (from_mode))
333+ {
334+ enum insn_code handler = widening_optab_handler (op, to_mode,
335+ from_mode);
336+
337+ if (handler != CODE_FOR_nothing)
338+ {
339+ if (found_mode)
340+ *found_mode = from_mode;
341+ return handler;
342+ }
343+ }
344+
345+ return CODE_FOR_nothing;
346+}
347+
348 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
349 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
350 not actually do a sign-extend or zero-extend, but can leave the
351@@ -517,8 +572,9 @@
352 optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default);
353 if (ops->code == WIDEN_MULT_PLUS_EXPR
354 || ops->code == WIDEN_MULT_MINUS_EXPR)
355- icode = (int) optab_handler (widen_pattern_optab,
356- TYPE_MODE (TREE_TYPE (ops->op2)));
357+ icode = (int) find_widening_optab_handler (widen_pattern_optab,
358+ TYPE_MODE (TREE_TYPE (ops->op2)),
359+ tmode0, 0);
360 else
361 icode = (int) optab_handler (widen_pattern_optab, tmode0);
362 gcc_assert (icode != CODE_FOR_nothing);
363@@ -1389,7 +1445,9 @@
364 rtx target, int unsignedp, enum optab_methods methods,
365 rtx last)
366 {
367- int icode = (int) optab_handler (binoptab, mode);
368+ enum machine_mode from_mode = widened_mode (mode, op0, op1);
369+ int icode = (int) find_widening_optab_handler (binoptab, mode,
370+ from_mode, 1);
371 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
372 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
373 enum machine_mode tmp_mode;
374@@ -1546,7 +1604,9 @@
375 /* If we can do it with a three-operand insn, do so. */
376
377 if (methods != OPTAB_MUST_WIDEN
378- && optab_handler (binoptab, mode) != CODE_FOR_nothing)
379+ && find_widening_optab_handler (binoptab, mode,
380+ widened_mode (mode, op0, op1), 1)
381+ != CODE_FOR_nothing)
382 {
383 temp = expand_binop_directly (mode, binoptab, op0, op1, target,
384 unsignedp, methods, last);
385@@ -1586,8 +1646,9 @@
386
387 if (binoptab == smul_optab
388 && GET_MODE_WIDER_MODE (mode) != VOIDmode
389- && (optab_handler ((unsignedp ? umul_widen_optab : smul_widen_optab),
390- GET_MODE_WIDER_MODE (mode))
391+ && (widening_optab_handler ((unsignedp ? umul_widen_optab
392+ : smul_widen_optab),
393+ GET_MODE_WIDER_MODE (mode), mode)
394 != CODE_FOR_nothing))
395 {
396 temp = expand_binop (GET_MODE_WIDER_MODE (mode),
397@@ -1618,9 +1679,11 @@
398 if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
399 || (binoptab == smul_optab
400 && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode
401- && (optab_handler ((unsignedp ? umul_widen_optab
402- : smul_widen_optab),
403- GET_MODE_WIDER_MODE (wider_mode))
404+ && (find_widening_optab_handler ((unsignedp
405+ ? umul_widen_optab
406+ : smul_widen_optab),
407+ GET_MODE_WIDER_MODE (wider_mode),
408+ mode, 0)
409 != CODE_FOR_nothing)))
410 {
411 rtx xop0 = op0, xop1 = op1;
412@@ -2043,8 +2106,8 @@
413 && optab_handler (add_optab, word_mode) != CODE_FOR_nothing)
414 {
415 rtx product = NULL_RTX;
416-
417- if (optab_handler (umul_widen_optab, mode) != CODE_FOR_nothing)
418+ if (widening_optab_handler (umul_widen_optab, mode, word_mode)
419+ != CODE_FOR_nothing)
420 {
421 product = expand_doubleword_mult (mode, op0, op1, target,
422 true, methods);
423@@ -2053,7 +2116,8 @@
424 }
425
426 if (product == NULL_RTX
427- && optab_handler (smul_widen_optab, mode) != CODE_FOR_nothing)
428+ && widening_optab_handler (smul_widen_optab, mode, word_mode)
429+ != CODE_FOR_nothing)
430 {
431 product = expand_doubleword_mult (mode, op0, op1, target,
432 false, methods);
433@@ -2144,7 +2208,8 @@
434 wider_mode != VOIDmode;
435 wider_mode = GET_MODE_WIDER_MODE (wider_mode))
436 {
437- if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing
438+ if (find_widening_optab_handler (binoptab, wider_mode, mode, 1)
439+ != CODE_FOR_nothing
440 || (methods == OPTAB_LIB
441 && optab_libfunc (binoptab, wider_mode)))
442 {
443
444=== modified file 'gcc/optabs.h'
445--- old/gcc/optabs.h 2011-05-05 15:43:06 +0000
446+++ new/gcc/optabs.h 2011-07-27 14:12:45 +0000
447@@ -42,6 +42,11 @@
448 int insn_code;
449 };
450
451+struct widening_optab_handlers
452+{
453+ struct optab_handlers handlers[NUM_MACHINE_MODES][NUM_MACHINE_MODES];
454+};
455+
456 struct optab_d
457 {
458 enum rtx_code code;
459@@ -50,6 +55,7 @@
460 void (*libcall_gen)(struct optab_d *, const char *name, char suffix,
461 enum machine_mode);
462 struct optab_handlers handlers[NUM_MACHINE_MODES];
463+ struct widening_optab_handlers *widening;
464 };
465 typedef struct optab_d * optab;
466
467@@ -799,6 +805,15 @@
468 extern void emit_unop_insn (int, rtx, rtx, enum rtx_code);
469 extern bool maybe_emit_unop_insn (int, rtx, rtx, enum rtx_code);
470
471+/* Find a widening optab even if it doesn't widen as much as we want. */
472+#define find_widening_optab_handler(A,B,C,D) \
473+ find_widening_optab_handler_and_mode (A, B, C, D, NULL)
474+extern enum insn_code find_widening_optab_handler_and_mode (optab,
475+ enum machine_mode,
476+ enum machine_mode,
477+ int,
478+ enum machine_mode *);
479+
480 /* An extra flag to control optab_for_tree_code's behavior. This is needed to
481 distinguish between machines with a vector shift that takes a scalar for the
482 shift amount vs. machines that take a vector for the shift amount. */
483@@ -874,6 +889,23 @@
484 + (int) CODE_FOR_nothing);
485 }
486
487+/* Like optab_handler, but for widening_operations that have a TO_MODE and
488+ a FROM_MODE. */
489+
490+static inline enum insn_code
491+widening_optab_handler (optab op, enum machine_mode to_mode,
492+ enum machine_mode from_mode)
493+{
494+ if (to_mode == from_mode || from_mode == VOIDmode)
495+ return optab_handler (op, to_mode);
496+
497+ if (op->widening)
498+ return (enum insn_code) (op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
499+ + (int) CODE_FOR_nothing);
500+
501+ return CODE_FOR_nothing;
502+}
503+
504 /* Record that insn CODE should be used to implement mode MODE of OP. */
505
506 static inline void
507@@ -882,6 +914,26 @@
508 op->handlers[(int) mode].insn_code = (int) code - (int) CODE_FOR_nothing;
509 }
510
511+/* Like set_optab_handler, but for widening operations that have a TO_MODE
512+ and a FROM_MODE. */
513+
514+static inline void
515+set_widening_optab_handler (optab op, enum machine_mode to_mode,
516+ enum machine_mode from_mode, enum insn_code code)
517+{
518+ if (to_mode == from_mode)
519+ set_optab_handler (op, to_mode, code);
520+ else
521+ {
522+ if (op->widening == NULL)
523+ op->widening = (struct widening_optab_handlers *)
524+ xcalloc (1, sizeof (struct widening_optab_handlers));
525+
526+ op->widening->handlers[(int) to_mode][(int) from_mode].insn_code
527+ = (int) code - (int) CODE_FOR_nothing;
528+ }
529+}
530+
531 /* Return the insn used to perform conversion OP from mode FROM_MODE
532 to mode TO_MODE; return CODE_FOR_nothing if the target does not have
533 such an insn. */
534
535=== added file 'gcc/testsuite/gcc.target/arm/no-wmla-1.c'
536--- old/gcc/testsuite/gcc.target/arm/no-wmla-1.c 1970-01-01 00:00:00 +0000
537+++ new/gcc/testsuite/gcc.target/arm/no-wmla-1.c 2011-07-15 13:52:38 +0000
538@@ -0,0 +1,11 @@
539+/* { dg-do compile } */
540+/* { dg-options "-O2 -march=armv7-a" } */
541+
542+int
543+foo (int a, short b, short c)
544+{
545+ int bc = b * c;
546+ return a + (short)bc;
547+}
548+
549+/* { dg-final { scan-assembler "mul" } } */
550
551=== added file 'gcc/testsuite/gcc.target/arm/wmul-10.c'
552--- old/gcc/testsuite/gcc.target/arm/wmul-10.c 1970-01-01 00:00:00 +0000
553+++ new/gcc/testsuite/gcc.target/arm/wmul-10.c 2011-07-18 12:56:20 +0000
554@@ -0,0 +1,10 @@
555+/* { dg-do compile } */
556+/* { dg-options "-O2 -march=armv7-a" } */
557+
558+unsigned long long
559+foo (unsigned short a, unsigned short *b, unsigned short *c)
560+{
561+ return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c;
562+}
563+
564+/* { dg-final { scan-assembler "umlal" } } */
565
566=== added file 'gcc/testsuite/gcc.target/arm/wmul-11.c'
567--- old/gcc/testsuite/gcc.target/arm/wmul-11.c 1970-01-01 00:00:00 +0000
568+++ new/gcc/testsuite/gcc.target/arm/wmul-11.c 2011-07-22 15:46:42 +0000
569@@ -0,0 +1,10 @@
570+/* { dg-do compile } */
571+/* { dg-options "-O2 -march=armv7-a" } */
572+
573+long long
574+foo (int *b)
575+{
576+ return 10 * (long long)*b;
577+}
578+
579+/* { dg-final { scan-assembler "smull" } } */
580
581=== added file 'gcc/testsuite/gcc.target/arm/wmul-12.c'
582--- old/gcc/testsuite/gcc.target/arm/wmul-12.c 1970-01-01 00:00:00 +0000
583+++ new/gcc/testsuite/gcc.target/arm/wmul-12.c 2011-07-22 15:46:42 +0000
584@@ -0,0 +1,11 @@
585+/* { dg-do compile } */
586+/* { dg-options "-O2 -march=armv7-a" } */
587+
588+long long
589+foo (int *b, int *c)
590+{
591+ int tmp = *b * *c;
592+ return 10 + (long long)tmp;
593+}
594+
595+/* { dg-final { scan-assembler "smlal" } } */
596
597=== added file 'gcc/testsuite/gcc.target/arm/wmul-13.c'
598--- old/gcc/testsuite/gcc.target/arm/wmul-13.c 1970-01-01 00:00:00 +0000
599+++ new/gcc/testsuite/gcc.target/arm/wmul-13.c 2011-07-22 15:46:42 +0000
600@@ -0,0 +1,10 @@
601+/* { dg-do compile } */
602+/* { dg-options "-O2 -march=armv7-a" } */
603+
604+long long
605+foo (int *a, int *b)
606+{
607+ return *a + (long long)*b * 10;
608+}
609+
610+/* { dg-final { scan-assembler "smlal" } } */
611
612=== added file 'gcc/testsuite/gcc.target/arm/wmul-5.c'
613--- old/gcc/testsuite/gcc.target/arm/wmul-5.c 1970-01-01 00:00:00 +0000
614+++ new/gcc/testsuite/gcc.target/arm/wmul-5.c 2011-07-15 13:52:38 +0000
615@@ -0,0 +1,10 @@
616+/* { dg-do compile } */
617+/* { dg-options "-O2 -march=armv7-a" } */
618+
619+long long
620+foo (long long a, char *b, char *c)
621+{
622+ return a + *b * *c;
623+}
624+
625+/* { dg-final { scan-assembler "umlal" } } */
626
627=== added file 'gcc/testsuite/gcc.target/arm/wmul-6.c'
628--- old/gcc/testsuite/gcc.target/arm/wmul-6.c 1970-01-01 00:00:00 +0000
629+++ new/gcc/testsuite/gcc.target/arm/wmul-6.c 2011-07-15 13:59:11 +0000
630@@ -0,0 +1,10 @@
631+/* { dg-do compile } */
632+/* { dg-options "-O2 -march=armv7-a" } */
633+
634+long long
635+foo (long long a, unsigned char *b, signed char *c)
636+{
637+ return a + (long long)*b * (long long)*c;
638+}
639+
640+/* { dg-final { scan-assembler "smlal" } } */
641
642=== added file 'gcc/testsuite/gcc.target/arm/wmul-7.c'
643--- old/gcc/testsuite/gcc.target/arm/wmul-7.c 1970-01-01 00:00:00 +0000
644+++ new/gcc/testsuite/gcc.target/arm/wmul-7.c 2011-07-15 14:11:23 +0000
645@@ -0,0 +1,10 @@
646+/* { dg-do compile } */
647+/* { dg-options "-O2 -march=armv7-a" } */
648+
649+unsigned long long
650+foo (unsigned long long a, unsigned char *b, unsigned short *c)
651+{
652+ return a + *b * *c;
653+}
654+
655+/* { dg-final { scan-assembler "umlal" } } */
656
657=== added file 'gcc/testsuite/gcc.target/arm/wmul-8.c'
658--- old/gcc/testsuite/gcc.target/arm/wmul-8.c 1970-01-01 00:00:00 +0000
659+++ new/gcc/testsuite/gcc.target/arm/wmul-8.c 2011-07-15 14:16:54 +0000
660@@ -0,0 +1,10 @@
661+/* { dg-do compile } */
662+/* { dg-options "-O2 -march=armv7-a" } */
663+
664+long long
665+foo (long long a, int *b, int *c)
666+{
667+ return a + *b * *c;
668+}
669+
670+/* { dg-final { scan-assembler "smlal" } } */
671
672=== added file 'gcc/testsuite/gcc.target/arm/wmul-9.c'
673--- old/gcc/testsuite/gcc.target/arm/wmul-9.c 1970-01-01 00:00:00 +0000
674+++ new/gcc/testsuite/gcc.target/arm/wmul-9.c 2011-07-15 14:22:39 +0000
675@@ -0,0 +1,10 @@
676+/* { dg-do compile } */
677+/* { dg-options "-O2 -march=armv7-a" } */
678+
679+long long
680+foo (long long a, short *b, char *c)
681+{
682+ return a + *b * *c;
683+}
684+
685+/* { dg-final { scan-assembler "smlalbb" } } */
686
687=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c'
688--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c 1970-01-01 00:00:00 +0000
689+++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c 2011-07-15 13:44:50 +0000
690@@ -0,0 +1,17 @@
691+/* { dg-do compile } */
692+/* { dg-options "-O2 -march=armv7-a" } */
693+
694+struct bf
695+{
696+ int a : 3;
697+ int b : 15;
698+ int c : 3;
699+};
700+
701+long long
702+foo (long long a, struct bf b, struct bf c)
703+{
704+ return a + b.b * c.b;
705+}
706+
707+/* { dg-final { scan-assembler "smlalbb" } } */
708
709=== added file 'gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c'
710--- old/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c 1970-01-01 00:00:00 +0000
711+++ new/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c 2011-07-15 14:22:39 +0000
712@@ -0,0 +1,17 @@
713+/* { dg-do compile } */
714+/* { dg-options "-O2 -march=armv7-a" } */
715+
716+struct bf
717+{
718+ int a : 3;
719+ unsigned int b : 15;
720+ int c : 3;
721+};
722+
723+long long
724+foo (long long a, struct bf b, struct bf c)
725+{
726+ return a + b.b * c.c;
727+}
728+
729+/* { dg-final { scan-assembler "smlalbb" } } */
730
731=== modified file 'gcc/tree-cfg.c'
732--- old/gcc/tree-cfg.c 2011-07-01 09:19:21 +0000
733+++ new/gcc/tree-cfg.c 2011-07-15 13:44:50 +0000
734@@ -3574,7 +3574,7 @@
735 case WIDEN_MULT_EXPR:
736 if (TREE_CODE (lhs_type) != INTEGER_TYPE)
737 return true;
738- return ((2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type))
739+ return ((2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type))
740 || (TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type)));
741
742 case WIDEN_SUM_EXPR:
743@@ -3667,7 +3667,7 @@
744 && !FIXED_POINT_TYPE_P (rhs1_type))
745 || !useless_type_conversion_p (rhs1_type, rhs2_type)
746 || !useless_type_conversion_p (lhs_type, rhs3_type)
747- || 2 * TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (lhs_type)
748+ || 2 * TYPE_PRECISION (rhs1_type) > TYPE_PRECISION (lhs_type)
749 || TYPE_PRECISION (rhs1_type) != TYPE_PRECISION (rhs2_type))
750 {
751 error ("type mismatch in widening multiply-accumulate expression");
752
753=== modified file 'gcc/tree-ssa-math-opts.c'
754--- old/gcc/tree-ssa-math-opts.c 2011-03-11 16:36:16 +0000
755+++ new/gcc/tree-ssa-math-opts.c 2011-08-09 10:26:48 +0000
756@@ -1266,39 +1266,67 @@
757 }
758 };
759
760-/* Return true if RHS is a suitable operand for a widening multiplication.
761+/* Build a gimple assignment to cast VAL to TARGET. Insert the statement
762+ prior to GSI's current position, and return the fresh SSA name. */
763+
764+static tree
765+build_and_insert_cast (gimple_stmt_iterator *gsi, location_t loc,
766+ tree target, tree val)
767+{
768+ tree result = make_ssa_name (target, NULL);
769+ gimple stmt = gimple_build_assign_with_ops (CONVERT_EXPR, result, val, NULL);
770+ gimple_set_location (stmt, loc);
771+ gsi_insert_before (gsi, stmt, GSI_SAME_STMT);
772+ return result;
773+}
774+
775+/* Return true if RHS is a suitable operand for a widening multiplication,
776+ assuming a target type of TYPE.
777 There are two cases:
778
779- - RHS makes some value twice as wide. Store that value in *NEW_RHS_OUT
780- if so, and store its type in *TYPE_OUT.
781+ - RHS makes some value at least twice as wide. Store that value
782+ in *NEW_RHS_OUT if so, and store its type in *TYPE_OUT.
783
784 - RHS is an integer constant. Store that value in *NEW_RHS_OUT if so,
785 but leave *TYPE_OUT untouched. */
786
787 static bool
788-is_widening_mult_rhs_p (tree rhs, tree *type_out, tree *new_rhs_out)
789+is_widening_mult_rhs_p (tree type, tree rhs, tree *type_out,
790+ tree *new_rhs_out)
791 {
792 gimple stmt;
793- tree type, type1, rhs1;
794+ tree type1, rhs1;
795 enum tree_code rhs_code;
796
797 if (TREE_CODE (rhs) == SSA_NAME)
798 {
799- type = TREE_TYPE (rhs);
800 stmt = SSA_NAME_DEF_STMT (rhs);
801- if (!is_gimple_assign (stmt))
802- return false;
803-
804- rhs_code = gimple_assign_rhs_code (stmt);
805- if (TREE_CODE (type) == INTEGER_TYPE
806- ? !CONVERT_EXPR_CODE_P (rhs_code)
807- : rhs_code != FIXED_CONVERT_EXPR)
808- return false;
809-
810- rhs1 = gimple_assign_rhs1 (stmt);
811+ if (is_gimple_assign (stmt))
812+ {
813+ rhs_code = gimple_assign_rhs_code (stmt);
814+ if (TREE_CODE (type) == INTEGER_TYPE
815+ ? !CONVERT_EXPR_CODE_P (rhs_code)
816+ : rhs_code != FIXED_CONVERT_EXPR)
817+ rhs1 = rhs;
818+ else
819+ {
820+ rhs1 = gimple_assign_rhs1 (stmt);
821+
822+ if (TREE_CODE (rhs1) == INTEGER_CST)
823+ {
824+ *new_rhs_out = rhs1;
825+ *type_out = NULL;
826+ return true;
827+ }
828+ }
829+ }
830+ else
831+ rhs1 = rhs;
832+
833 type1 = TREE_TYPE (rhs1);
834+
835 if (TREE_CODE (type1) != TREE_CODE (type)
836- || TYPE_PRECISION (type1) * 2 != TYPE_PRECISION (type))
837+ || TYPE_PRECISION (type1) * 2 > TYPE_PRECISION (type))
838 return false;
839
840 *new_rhs_out = rhs1;
841@@ -1316,28 +1344,27 @@
842 return false;
843 }
844
845-/* Return true if STMT performs a widening multiplication. If so,
846- store the unwidened types of the operands in *TYPE1_OUT and *TYPE2_OUT
847- respectively. Also fill *RHS1_OUT and *RHS2_OUT such that converting
848- those operands to types *TYPE1_OUT and *TYPE2_OUT would give the
849- operands of the multiplication. */
850+/* Return true if STMT performs a widening multiplication, assuming the
851+ output type is TYPE. If so, store the unwidened types of the operands
852+ in *TYPE1_OUT and *TYPE2_OUT respectively. Also fill *RHS1_OUT and
853+ *RHS2_OUT such that converting those operands to types *TYPE1_OUT
854+ and *TYPE2_OUT would give the operands of the multiplication. */
855
856 static bool
857-is_widening_mult_p (gimple stmt,
858+is_widening_mult_p (tree type, gimple stmt,
859 tree *type1_out, tree *rhs1_out,
860 tree *type2_out, tree *rhs2_out)
861 {
862- tree type;
863-
864- type = TREE_TYPE (gimple_assign_lhs (stmt));
865 if (TREE_CODE (type) != INTEGER_TYPE
866 && TREE_CODE (type) != FIXED_POINT_TYPE)
867 return false;
868
869- if (!is_widening_mult_rhs_p (gimple_assign_rhs1 (stmt), type1_out, rhs1_out))
870+ if (!is_widening_mult_rhs_p (type, gimple_assign_rhs1 (stmt), type1_out,
871+ rhs1_out))
872 return false;
873
874- if (!is_widening_mult_rhs_p (gimple_assign_rhs2 (stmt), type2_out, rhs2_out))
875+ if (!is_widening_mult_rhs_p (type, gimple_assign_rhs2 (stmt), type2_out,
876+ rhs2_out))
877 return false;
878
879 if (*type1_out == NULL)
880@@ -1354,6 +1381,18 @@
881 *type2_out = *type1_out;
882 }
883
884+ /* Ensure that the larger of the two operands comes first. */
885+ if (TYPE_PRECISION (*type1_out) < TYPE_PRECISION (*type2_out))
886+ {
887+ tree tmp;
888+ tmp = *type1_out;
889+ *type1_out = *type2_out;
890+ *type2_out = tmp;
891+ tmp = *rhs1_out;
892+ *rhs1_out = *rhs2_out;
893+ *rhs2_out = tmp;
894+ }
895+
896 return true;
897 }
898
899@@ -1362,31 +1401,100 @@
900 value is true iff we converted the statement. */
901
902 static bool
903-convert_mult_to_widen (gimple stmt)
904+convert_mult_to_widen (gimple stmt, gimple_stmt_iterator *gsi)
905 {
906- tree lhs, rhs1, rhs2, type, type1, type2;
907+ tree lhs, rhs1, rhs2, type, type1, type2, tmp = NULL;
908 enum insn_code handler;
909+ enum machine_mode to_mode, from_mode, actual_mode;
910+ optab op;
911+ int actual_precision;
912+ location_t loc = gimple_location (stmt);
913+ bool from_unsigned1, from_unsigned2;
914
915 lhs = gimple_assign_lhs (stmt);
916 type = TREE_TYPE (lhs);
917 if (TREE_CODE (type) != INTEGER_TYPE)
918 return false;
919
920- if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
921+ if (!is_widening_mult_p (type, stmt, &type1, &rhs1, &type2, &rhs2))
922 return false;
923
924- if (TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2))
925- handler = optab_handler (umul_widen_optab, TYPE_MODE (type));
926- else if (!TYPE_UNSIGNED (type1) && !TYPE_UNSIGNED (type2))
927- handler = optab_handler (smul_widen_optab, TYPE_MODE (type));
928+ to_mode = TYPE_MODE (type);
929+ from_mode = TYPE_MODE (type1);
930+ from_unsigned1 = TYPE_UNSIGNED (type1);
931+ from_unsigned2 = TYPE_UNSIGNED (type2);
932+
933+ if (from_unsigned1 && from_unsigned2)
934+ op = umul_widen_optab;
935+ else if (!from_unsigned1 && !from_unsigned2)
936+ op = smul_widen_optab;
937 else
938- handler = optab_handler (usmul_widen_optab, TYPE_MODE (type));
939+ op = usmul_widen_optab;
940+
941+ handler = find_widening_optab_handler_and_mode (op, to_mode, from_mode,
942+ 0, &actual_mode);
943
944 if (handler == CODE_FOR_nothing)
945- return false;
946-
947- gimple_assign_set_rhs1 (stmt, fold_convert (type1, rhs1));
948- gimple_assign_set_rhs2 (stmt, fold_convert (type2, rhs2));
949+ {
950+ if (op != smul_widen_optab)
951+ {
952+ /* We can use a signed multiply with unsigned types as long as
953+ there is a wider mode to use, or it is the smaller of the two
954+ types that is unsigned. Note that type1 >= type2, always. */
955+ if ((TYPE_UNSIGNED (type1)
956+ && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
957+ || (TYPE_UNSIGNED (type2)
958+ && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
959+ {
960+ from_mode = GET_MODE_WIDER_MODE (from_mode);
961+ if (GET_MODE_SIZE (to_mode) <= GET_MODE_SIZE (from_mode))
962+ return false;
963+ }
964+
965+ op = smul_widen_optab;
966+ handler = find_widening_optab_handler_and_mode (op, to_mode,
967+ from_mode, 0,
968+ &actual_mode);
969+
970+ if (handler == CODE_FOR_nothing)
971+ return false;
972+
973+ from_unsigned1 = from_unsigned2 = false;
974+ }
975+ else
976+ return false;
977+ }
978+
979+ /* Ensure that the inputs to the handler are in the correct precison
980+ for the opcode. This will be the full mode size. */
981+ actual_precision = GET_MODE_PRECISION (actual_mode);
982+ if (actual_precision != TYPE_PRECISION (type1)
983+ || from_unsigned1 != TYPE_UNSIGNED (type1))
984+ {
985+ tmp = create_tmp_var (build_nonstandard_integer_type
986+ (actual_precision, from_unsigned1),
987+ NULL);
988+ rhs1 = build_and_insert_cast (gsi, loc, tmp, rhs1);
989+ }
990+ if (actual_precision != TYPE_PRECISION (type2)
991+ || from_unsigned2 != TYPE_UNSIGNED (type2))
992+ {
993+ /* Reuse the same type info, if possible. */
994+ if (!tmp || from_unsigned1 != from_unsigned2)
995+ tmp = create_tmp_var (build_nonstandard_integer_type
996+ (actual_precision, from_unsigned2),
997+ NULL);
998+ rhs2 = build_and_insert_cast (gsi, loc, tmp, rhs2);
999+ }
1000+
1001+ /* Handle constants. */
1002+ if (TREE_CODE (rhs1) == INTEGER_CST)
1003+ rhs1 = fold_convert (type1, rhs1);
1004+ if (TREE_CODE (rhs2) == INTEGER_CST)
1005+ rhs2 = fold_convert (type2, rhs2);
1006+
1007+ gimple_assign_set_rhs1 (stmt, rhs1);
1008+ gimple_assign_set_rhs2 (stmt, rhs2);
1009 gimple_assign_set_rhs_code (stmt, WIDEN_MULT_EXPR);
1010 update_stmt (stmt);
1011 return true;
1012@@ -1403,11 +1511,17 @@
1013 enum tree_code code)
1014 {
1015 gimple rhs1_stmt = NULL, rhs2_stmt = NULL;
1016- tree type, type1, type2;
1017+ gimple conv1_stmt = NULL, conv2_stmt = NULL, conv_stmt;
1018+ tree type, type1, type2, optype, tmp = NULL;
1019 tree lhs, rhs1, rhs2, mult_rhs1, mult_rhs2, add_rhs;
1020 enum tree_code rhs1_code = ERROR_MARK, rhs2_code = ERROR_MARK;
1021 optab this_optab;
1022 enum tree_code wmult_code;
1023+ enum insn_code handler;
1024+ enum machine_mode to_mode, from_mode, actual_mode;
1025+ location_t loc = gimple_location (stmt);
1026+ int actual_precision;
1027+ bool from_unsigned1, from_unsigned2;
1028
1029 lhs = gimple_assign_lhs (stmt);
1030 type = TREE_TYPE (lhs);
1031@@ -1429,8 +1543,6 @@
1032 if (is_gimple_assign (rhs1_stmt))
1033 rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
1034 }
1035- else
1036- return false;
1037
1038 if (TREE_CODE (rhs2) == SSA_NAME)
1039 {
1040@@ -1438,57 +1550,160 @@
1041 if (is_gimple_assign (rhs2_stmt))
1042 rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
1043 }
1044- else
1045- return false;
1046-
1047- if (code == PLUS_EXPR && rhs1_code == MULT_EXPR)
1048- {
1049- if (!is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
1050- &type2, &mult_rhs2))
1051- return false;
1052- add_rhs = rhs2;
1053- }
1054- else if (rhs2_code == MULT_EXPR)
1055- {
1056- if (!is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
1057- &type2, &mult_rhs2))
1058- return false;
1059- add_rhs = rhs1;
1060- }
1061- else if (code == PLUS_EXPR && rhs1_code == WIDEN_MULT_EXPR)
1062- {
1063- mult_rhs1 = gimple_assign_rhs1 (rhs1_stmt);
1064- mult_rhs2 = gimple_assign_rhs2 (rhs1_stmt);
1065- type1 = TREE_TYPE (mult_rhs1);
1066- type2 = TREE_TYPE (mult_rhs2);
1067- add_rhs = rhs2;
1068- }
1069- else if (rhs2_code == WIDEN_MULT_EXPR)
1070- {
1071- mult_rhs1 = gimple_assign_rhs1 (rhs2_stmt);
1072- mult_rhs2 = gimple_assign_rhs2 (rhs2_stmt);
1073- type1 = TREE_TYPE (mult_rhs1);
1074- type2 = TREE_TYPE (mult_rhs2);
1075- add_rhs = rhs1;
1076- }
1077- else
1078- return false;
1079-
1080- if (TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2))
1081- return false;
1082+
1083+ /* Allow for one conversion statement between the multiply
1084+ and addition/subtraction statement. If there are more than
1085+ one conversions then we assume they would invalidate this
1086+ transformation. If that's not the case then they should have
1087+ been folded before now. */
1088+ if (CONVERT_EXPR_CODE_P (rhs1_code))
1089+ {
1090+ conv1_stmt = rhs1_stmt;
1091+ rhs1 = gimple_assign_rhs1 (rhs1_stmt);
1092+ if (TREE_CODE (rhs1) == SSA_NAME)
1093+ {
1094+ rhs1_stmt = SSA_NAME_DEF_STMT (rhs1);
1095+ if (is_gimple_assign (rhs1_stmt))
1096+ rhs1_code = gimple_assign_rhs_code (rhs1_stmt);
1097+ }
1098+ else
1099+ return false;
1100+ }
1101+ if (CONVERT_EXPR_CODE_P (rhs2_code))
1102+ {
1103+ conv2_stmt = rhs2_stmt;
1104+ rhs2 = gimple_assign_rhs1 (rhs2_stmt);
1105+ if (TREE_CODE (rhs2) == SSA_NAME)
1106+ {
1107+ rhs2_stmt = SSA_NAME_DEF_STMT (rhs2);
1108+ if (is_gimple_assign (rhs2_stmt))
1109+ rhs2_code = gimple_assign_rhs_code (rhs2_stmt);
1110+ }
1111+ else
1112+ return false;
1113+ }
1114+
1115+ /* If code is WIDEN_MULT_EXPR then it would seem unnecessary to call
1116+ is_widening_mult_p, but we still need the rhs returns.
1117+
1118+ It might also appear that it would be sufficient to use the existing
1119+ operands of the widening multiply, but that would limit the choice of
1120+ multiply-and-accumulate instructions. */
1121+ if (code == PLUS_EXPR
1122+ && (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
1123+ {
1124+ if (!is_widening_mult_p (type, rhs1_stmt, &type1, &mult_rhs1,
1125+ &type2, &mult_rhs2))
1126+ return false;
1127+ add_rhs = rhs2;
1128+ conv_stmt = conv1_stmt;
1129+ }
1130+ else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
1131+ {
1132+ if (!is_widening_mult_p (type, rhs2_stmt, &type1, &mult_rhs1,
1133+ &type2, &mult_rhs2))
1134+ return false;
1135+ add_rhs = rhs1;
1136+ conv_stmt = conv2_stmt;
1137+ }
1138+ else
1139+ return false;
1140+
1141+ to_mode = TYPE_MODE (type);
1142+ from_mode = TYPE_MODE (type1);
1143+ from_unsigned1 = TYPE_UNSIGNED (type1);
1144+ from_unsigned2 = TYPE_UNSIGNED (type2);
1145+
1146+ /* There's no such thing as a mixed sign madd yet, so use a wider mode. */
1147+ if (from_unsigned1 != from_unsigned2)
1148+ {
1149+ /* We can use a signed multiply with unsigned types as long as
1150+ there is a wider mode to use, or it is the smaller of the two
1151+ types that is unsigned. Note that type1 >= type2, always. */
1152+ if ((from_unsigned1
1153+ && TYPE_PRECISION (type1) == GET_MODE_PRECISION (from_mode))
1154+ || (from_unsigned2
1155+ && TYPE_PRECISION (type2) == GET_MODE_PRECISION (from_mode)))
1156+ {
1157+ from_mode = GET_MODE_WIDER_MODE (from_mode);
1158+ if (GET_MODE_SIZE (from_mode) >= GET_MODE_SIZE (to_mode))
1159+ return false;
1160+ }
1161+
1162+ from_unsigned1 = from_unsigned2 = false;
1163+ }
1164+
1165+ /* If there was a conversion between the multiply and addition
1166+ then we need to make sure it fits a multiply-and-accumulate.
1167+ The should be a single mode change which does not change the
1168+ value. */
1169+ if (conv_stmt)
1170+ {
1171+ /* We use the original, unmodified data types for this. */
1172+ tree from_type = TREE_TYPE (gimple_assign_rhs1 (conv_stmt));
1173+ tree to_type = TREE_TYPE (gimple_assign_lhs (conv_stmt));
1174+ int data_size = TYPE_PRECISION (type1) + TYPE_PRECISION (type2);
1175+ bool is_unsigned = TYPE_UNSIGNED (type1) && TYPE_UNSIGNED (type2);
1176+
1177+ if (TYPE_PRECISION (from_type) > TYPE_PRECISION (to_type))
1178+ {
1179+ /* Conversion is a truncate. */
1180+ if (TYPE_PRECISION (to_type) < data_size)
1181+ return false;
1182+ }
1183+ else if (TYPE_PRECISION (from_type) < TYPE_PRECISION (to_type))
1184+ {
1185+ /* Conversion is an extend. Check it's the right sort. */
1186+ if (TYPE_UNSIGNED (from_type) != is_unsigned
1187+ && !(is_unsigned && TYPE_PRECISION (from_type) > data_size))
1188+ return false;
1189+ }
1190+ /* else convert is a no-op for our purposes. */
1191+ }
1192
1193 /* Verify that the machine can perform a widening multiply
1194 accumulate in this mode/signedness combination, otherwise
1195 this transformation is likely to pessimize code. */
1196- this_optab = optab_for_tree_code (wmult_code, type1, optab_default);
1197- if (optab_handler (this_optab, TYPE_MODE (type)) == CODE_FOR_nothing)
1198+ optype = build_nonstandard_integer_type (from_mode, from_unsigned1);
1199+ this_optab = optab_for_tree_code (wmult_code, optype, optab_default);
1200+ handler = find_widening_optab_handler_and_mode (this_optab, to_mode,
1201+ from_mode, 0, &actual_mode);
1202+
1203+ if (handler == CODE_FOR_nothing)
1204 return false;
1205
1206- /* ??? May need some type verification here? */
1207-
1208- gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code,
1209- fold_convert (type1, mult_rhs1),
1210- fold_convert (type2, mult_rhs2),
1211+ /* Ensure that the inputs to the handler are in the correct precison
1212+ for the opcode. This will be the full mode size. */
1213+ actual_precision = GET_MODE_PRECISION (actual_mode);
1214+ if (actual_precision != TYPE_PRECISION (type1)
1215+ || from_unsigned1 != TYPE_UNSIGNED (type1))
1216+ {
1217+ tmp = create_tmp_var (build_nonstandard_integer_type
1218+ (actual_precision, from_unsigned1),
1219+ NULL);
1220+ mult_rhs1 = build_and_insert_cast (gsi, loc, tmp, mult_rhs1);
1221+ }
1222+ if (actual_precision != TYPE_PRECISION (type2)
1223+ || from_unsigned2 != TYPE_UNSIGNED (type2))
1224+ {
1225+ if (!tmp || from_unsigned1 != from_unsigned2)
1226+ tmp = create_tmp_var (build_nonstandard_integer_type
1227+ (actual_precision, from_unsigned2),
1228+ NULL);
1229+ mult_rhs2 = build_and_insert_cast (gsi, loc, tmp, mult_rhs2);
1230+ }
1231+
1232+ if (!useless_type_conversion_p (type, TREE_TYPE (add_rhs)))
1233+ add_rhs = build_and_insert_cast (gsi, loc, create_tmp_var (type, NULL),
1234+ add_rhs);
1235+
1236+ /* Handle constants. */
1237+ if (TREE_CODE (mult_rhs1) == INTEGER_CST)
1238+ rhs1 = fold_convert (type1, mult_rhs1);
1239+ if (TREE_CODE (mult_rhs2) == INTEGER_CST)
1240+ rhs2 = fold_convert (type2, mult_rhs2);
1241+
1242+ gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
1243 add_rhs);
1244 update_stmt (gsi_stmt (*gsi));
1245 return true;
1246@@ -1696,7 +1911,7 @@
1247 switch (code)
1248 {
1249 case MULT_EXPR:
1250- if (!convert_mult_to_widen (stmt)
1251+ if (!convert_mult_to_widen (stmt, &gsi)
1252 && convert_mult_to_fma (stmt,
1253 gimple_assign_rhs1 (stmt),
1254 gimple_assign_rhs2 (stmt)))
1255
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
new file mode 100644
index 0000000000..8230beb91e
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106797.patch
@@ -0,0 +1,23 @@
12011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-08-26 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * df-problems.c (df_note_bb_compute): Pass uses rather than defs
9 to df_set_dead_notes_for_mw.
10
11=== modified file 'gcc/df-problems.c'
12--- old/gcc/df-problems.c 2011-07-07 19:10:01 +0000
13+++ new/gcc/df-problems.c 2011-08-26 14:32:47 +0000
14@@ -3375,7 +3375,7 @@
15 while (*mws_rec)
16 {
17 struct df_mw_hardreg *mws = *mws_rec;
18- if ((DF_MWS_REG_DEF_P (mws))
19+ if (DF_MWS_REG_USE_P (mws)
20 && !df_ignore_stack_reg (mws->start_regno))
21 {
22 bool really_add_notes = debug_insn != 0;
23
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
new file mode 100644
index 0000000000..aa067b7113
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106798.patch
@@ -0,0 +1,23 @@
12011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/
4
5 2011-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
6
7 PR target/48328
8 * config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance
9 for tbh instructions.
10
11=== modified file 'gcc/config/arm/arm.h'
12--- old/gcc/config/arm/arm.h 2011-08-24 17:35:16 +0000
13+++ new/gcc/config/arm/arm.h 2011-09-05 14:32:11 +0000
14@@ -1961,7 +1961,7 @@
15 : min >= -4096 && max < 4096 \
16 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
17 : SImode) \
18- : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
19+ : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
20 : (max >= 0x200) ? HImode \
21 : QImode))
22
23
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
new file mode 100644
index 0000000000..c440db91e1
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106799.patch
@@ -0,0 +1,75 @@
1 2011-09-05 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from mainline.
4 2011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
5
6 * config/arm/cortex-a9.md ("cortex_a9_mult_long"): New.
7 ("cortex_a9_multiply_long"): New and use above. Handle all
8 long multiply cases.
9 ("cortex_a9_multiply"): Handle smmul and smmulr.
10 ("cortex_a9_mac"): Handle smmla.
11
12=== modified file 'gcc/config/arm/cortex-a9.md'
13--- old/gcc/config/arm/cortex-a9.md 2011-01-18 15:28:08 +0000
14+++ new/gcc/config/arm/cortex-a9.md 2011-08-26 08:52:15 +0000
15@@ -68,7 +68,8 @@
16 "cortex_a9_mac_m1*2, cortex_a9_mac_m2, cortex_a9_p0_wb")
17 (define_reservation "cortex_a9_mac"
18 "cortex_a9_multcycle1*2 ,cortex_a9_mac_m2, cortex_a9_p0_wb")
19-
20+(define_reservation "cortex_a9_mult_long"
21+ "cortex_a9_mac_m1*3, cortex_a9_mac_m2, cortex_a9_p0_wb")
22
23 ;; Issue at the same time along the load store pipeline and
24 ;; the VFP / Neon pipeline is not possible.
25@@ -139,29 +140,35 @@
26 (eq_attr "insn" "smlaxy"))
27 "cortex_a9_mac16")
28
29-
30 (define_insn_reservation "cortex_a9_multiply" 4
31 (and (eq_attr "tune" "cortexa9")
32- (eq_attr "insn" "mul"))
33+ (eq_attr "insn" "mul,smmul,smmulr"))
34 "cortex_a9_mult")
35
36 (define_insn_reservation "cortex_a9_mac" 4
37 (and (eq_attr "tune" "cortexa9")
38- (eq_attr "insn" "mla"))
39+ (eq_attr "insn" "mla,smmla"))
40 "cortex_a9_mac")
41
42+(define_insn_reservation "cortex_a9_multiply_long" 5
43+ (and (eq_attr "tune" "cortexa9")
44+ (eq_attr "insn" "smull,umull,smulls,umulls,smlal,smlals,umlal,umlals"))
45+ "cortex_a9_mult_long")
46+
47 ;; An instruction with a result in E2 can be forwarded
48 ;; to E2 or E1 or M1 or the load store unit in the next cycle.
49
50 (define_bypass 1 "cortex_a9_dp"
51 "cortex_a9_dp_shift, cortex_a9_multiply,
52 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
53- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
54+ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
55+ cortex_a9_multiply_long")
56
57 (define_bypass 2 "cortex_a9_dp_shift"
58 "cortex_a9_dp_shift, cortex_a9_multiply,
59 cortex_a9_load1_2, cortex_a9_dp, cortex_a9_store1_2,
60- cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4")
61+ cortex_a9_mult16, cortex_a9_mac16, cortex_a9_mac, cortex_a9_store3_4, cortex_a9_load3_4,
62+ cortex_a9_multiply_long")
63
64 ;; An instruction in the load store pipeline can provide
65 ;; read access to a DP instruction in the P0 default pipeline
66@@ -212,7 +219,7 @@
67
68 (define_bypass 1
69 "cortex_a9_fps"
70- "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply")
71+ "cortex_a9_fadd, cortex_a9_fps, cortex_a9_fcmp, cortex_a9_dp, cortex_a9_dp_shift, cortex_a9_multiply, cortex_a9_multiply_long")
72
73 ;; Scheduling on the FP_ADD pipeline.
74 (define_reservation "ca9fp_add" "ca9_issue_vfp_neon + ca9fp_add1, ca9fp_add2, ca9fp_add3, ca9fp_add4")
75
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
new file mode 100644
index 0000000000..dfdeec7245
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106800.patch
@@ -0,0 +1,1270 @@
12011-09-07 Ira Rosen <ira.rosen@linaro.org>
2
3 Backport from mainline:
4
5 2011-08-04 Ira Rosen <ira.rosen@linaro.org>
6
7 gcc/
8 * tree-vectorizer.h (struct _stmt_vec_info): Add new field for
9 pattern def statement, and its access macro.
10 (NUM_PATTERNS): Set to 5.
11 * tree-vect-loop.c (vect_determine_vectorization_factor): Handle
12 pattern def statement.
13 (vect_transform_loop): Likewise.
14 * tree-vect-patterns.c (vect_vect_recog_func_ptrs): Add new
15 function vect_recog_over_widening_pattern ().
16 (vect_operation_fits_smaller_type): New function.
17 (vect_recog_over_widening_pattern, vect_mark_pattern_stmts):
18 Likewise.
19 (vect_pattern_recog_1): Move the code that marks pattern
20 statements to vect_mark_pattern_stmts (), and call it. Update
21 documentation.
22 * tree-vect-stmts.c (vect_supportable_shift): New function.
23 (vect_analyze_stmt): Handle pattern def statement.
24 (new_stmt_vec_info): Initialize pattern def statement.
25
26 gcc/testsuite/
27 * gcc.dg/vect/vect-over-widen-1.c: New test.
28 * gcc.dg/vect/vect-over-widen-2.c: New test.
29 * gcc.dg/vect/vect-over-widen-3.c: New test.
30 * gcc.dg/vect/vect-over-widen-4.c: New test.
31
32
33 2011-08-09 Ira Rosen <ira.rosen@linaro.org>
34
35 gcc/
36 PR tree-optimization/50014
37 * tree-vect-loop.c (vectorizable_reduction): Get def type before
38 calling vect_get_vec_def_for_stmt_copy ().
39
40 gcc/testsuite/
41 PR tree-optimization/50014
42 * gcc.dg/vect/pr50014.c: New test.
43
44
45 2011-08-11 Ira Rosen <ira.rosen@linaro.org>
46
47 gcc/
48 PR tree-optimization/50039
49 * tree-vect-patterns.c (vect_operation_fits_smaller_type): Check
50 that DEF_STMT has a stmt_vec_info.
51
52 gcc/testsuite/
53 PR tree-optimization/50039
54 * gcc.dg/vect/vect.exp: Run no-tree-fre-* tests with -fno-tree-fre.
55 * gcc.dg/vect/no-tree-fre-pr50039.c: New test.
56
57
58 2011-09-04 Jakub Jelinek <jakub@redhat.com>
59 Ira Rosen <ira.rosen@linaro.org>
60
61 gcc/
62 PR tree-optimization/50208
63 * tree-vect-patterns.c (vect_handle_widen_mult_by_const): Add an
64 argument. Check that def_stmt is inside the loop.
65 (vect_recog_widen_mult_pattern): Update calls to
66 vect_handle_widen_mult_by_cons.
67 (vect_operation_fits_smaller_type): Check that def_stmt is
68 inside the loop.
69
70 gcc/testsuite/
71 PR tree-optimization/50208
72 * gcc.dg/vect/no-fre-pre-pr50208.c: New test.
73 * gcc.dg/vect/vect.exp: Run no-fre-pre-*.c tests with
74 -fno-tree-fre -fno-tree-pre.
75
76=== added file 'gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c'
77--- old/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c 1970-01-01 00:00:00 +0000
78+++ new/gcc/testsuite/gcc.dg/vect/no-fre-pre-pr50208.c 2011-09-05 06:23:37 +0000
79@@ -0,0 +1,17 @@
80+/* { dg-do compile } */
81+
82+char c;
83+int a, b;
84+
85+void foo (int j)
86+{
87+ int i;
88+ while (--j)
89+ {
90+ b = 3;
91+ for (i = 0; i < 2; ++i)
92+ a = b ^ c;
93+ }
94+}
95+
96+/* { dg-final { cleanup-tree-dump "vect" } } */
97
98=== added file 'gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c'
99--- old/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c 1970-01-01 00:00:00 +0000
100+++ new/gcc/testsuite/gcc.dg/vect/no-tree-fre-pr50039.c 2011-09-05 06:23:37 +0000
101@@ -0,0 +1,15 @@
102+/* { dg-do compile } */
103+
104+extern unsigned char g_5;
105+extern int g_31, g_76;
106+int main(void) {
107+ int i, j;
108+ for (j=0; j < 2; ++j) {
109+ g_31 = -3;
110+ for (i=0; i < 2; ++i)
111+ g_76 = (g_31 ? g_31+1 : 0) ^ g_5;
112+ }
113+}
114+
115+/* { dg-final { cleanup-tree-dump "vect" } } */
116+
117
118=== added file 'gcc/testsuite/gcc.dg/vect/pr50014.c'
119--- old/gcc/testsuite/gcc.dg/vect/pr50014.c 1970-01-01 00:00:00 +0000
120+++ new/gcc/testsuite/gcc.dg/vect/pr50014.c 2011-09-05 06:23:37 +0000
121@@ -0,0 +1,16 @@
122+/* { dg-do compile } */
123+/* { dg-require-effective-target vect_int } */
124+
125+int f(unsigned char *s, int n)
126+{
127+ int sum = 0;
128+ int i;
129+
130+ for (i = 0; i < n; i++)
131+ sum += 256 * s[i];
132+
133+ return sum;
134+}
135+
136+/* { dg-final { cleanup-tree-dump "vect" } } */
137+
138
139=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c'
140--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 1970-01-01 00:00:00 +0000
141+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-1.c 2011-09-05 06:23:37 +0000
142@@ -0,0 +1,64 @@
143+/* { dg-require-effective-target vect_int } */
144+/* { dg-require-effective-target vect_shift } */
145+
146+#include <stdlib.h>
147+#include <stdarg.h>
148+#include "tree-vect.h"
149+
150+#define N 64
151+
152+/* Modified rgb to rgb conversion from FFmpeg. */
153+__attribute__ ((noinline)) void
154+foo (unsigned char *src, unsigned char *dst)
155+{
156+ unsigned char *s = src;
157+ unsigned short *d = (unsigned short *)dst;
158+ int i;
159+
160+ for (i = 0; i < N/4; i++)
161+ {
162+ const int b = *s++;
163+ const int g = *s++;
164+ const int r = *s++;
165+ const int a = *s++;
166+ *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
167+ d++;
168+ }
169+
170+ s = src;
171+ d = (unsigned short *)dst;
172+ for (i = 0; i < N/4; i++)
173+ {
174+ const int b = *s++;
175+ const int g = *s++;
176+ const int r = *s++;
177+ const int a = *s++;
178+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
179+ abort ();
180+ d++;
181+ }
182+}
183+
184+int main (void)
185+{
186+ int i;
187+ unsigned char in[N], out[N];
188+
189+ check_vect ();
190+
191+ for (i = 0; i < N; i++)
192+ {
193+ in[i] = i;
194+ out[i] = 255;
195+ __asm__ volatile ("");
196+ }
197+
198+ foo (in, out);
199+
200+ return 0;
201+}
202+
203+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
204+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
205+/* { dg-final { cleanup-tree-dump "vect" } } */
206+
207
208=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c'
209--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c 1970-01-01 00:00:00 +0000
210+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-2.c 2011-09-05 06:23:37 +0000
211@@ -0,0 +1,65 @@
212+/* { dg-require-effective-target vect_int } */
213+/* { dg-require-effective-target vect_shift } */
214+
215+#include <stdlib.h>
216+#include <stdarg.h>
217+#include "tree-vect.h"
218+
219+#define N 64
220+
221+/* Modified rgb to rgb conversion from FFmpeg. */
222+__attribute__ ((noinline)) void
223+foo (unsigned char *src, unsigned char *dst)
224+{
225+ unsigned char *s = src;
226+ int *d = (int *)dst;
227+ int i;
228+
229+ for (i = 0; i < N/4; i++)
230+ {
231+ const int b = *s++;
232+ const int g = *s++;
233+ const int r = *s++;
234+ const int a = *s++;
235+ *d = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
236+ d++;
237+ }
238+
239+ s = src;
240+ d = (int *)dst;
241+ for (i = 0; i < N/4; i++)
242+ {
243+ const int b = *s++;
244+ const int g = *s++;
245+ const int r = *s++;
246+ const int a = *s++;
247+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
248+ abort ();
249+ d++;
250+ }
251+}
252+
253+int main (void)
254+{
255+ int i;
256+ unsigned char in[N], out[N];
257+
258+ check_vect ();
259+
260+ for (i = 0; i < N; i++)
261+ {
262+ in[i] = i;
263+ out[i] = 255;
264+ __asm__ volatile ("");
265+ }
266+
267+ foo (in, out);
268+
269+ return 0;
270+}
271+
272+/* Final value stays in int, so no over-widening is detected at the moment. */
273+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 0 "vect" } } */
274+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
275+/* { dg-final { cleanup-tree-dump "vect" } } */
276+
277
278=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c'
279--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c 1970-01-01 00:00:00 +0000
280+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-3.c 2011-09-05 06:23:37 +0000
281@@ -0,0 +1,64 @@
282+/* { dg-require-effective-target vect_int } */
283+/* { dg-require-effective-target vect_shift } */
284+
285+#include <stdlib.h>
286+#include <stdarg.h>
287+#include "tree-vect.h"
288+
289+#define N 64
290+
291+/* Modified rgb to rgb conversion from FFmpeg. */
292+__attribute__ ((noinline)) void
293+foo (unsigned char *src, unsigned char *dst)
294+{
295+ unsigned char *s = src;
296+ unsigned short *d = (unsigned short *)dst;
297+ int i;
298+
299+ for (i = 0; i < N/4; i++)
300+ {
301+ const int b = *s++;
302+ const int g = *s++;
303+ const int r = *s++;
304+ const int a = *s++;
305+ *d = ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9));
306+ d++;
307+ }
308+
309+ s = src;
310+ d = (unsigned short *)dst;
311+ for (i = 0; i < N/4; i++)
312+ {
313+ const int b = *s++;
314+ const int g = *s++;
315+ const int r = *s++;
316+ const int a = *s++;
317+ if (*d != ((b>>3) | ((g&0xFFC)<<3) | ((r+0xF8)>>8) | (a<<9)))
318+ abort ();
319+ d++;
320+ }
321+}
322+
323+int main (void)
324+{
325+ int i;
326+ unsigned char in[N], out[N];
327+
328+ check_vect ();
329+
330+ for (i = 0; i < N; i++)
331+ {
332+ in[i] = i;
333+ out[i] = 255;
334+ __asm__ volatile ("");
335+ }
336+
337+ foo (in, out);
338+
339+ return 0;
340+}
341+
342+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 1 "vect" } } */
343+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
344+/* { dg-final { cleanup-tree-dump "vect" } } */
345+
346
347=== added file 'gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c'
348--- old/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 1970-01-01 00:00:00 +0000
349+++ new/gcc/testsuite/gcc.dg/vect/vect-over-widen-4.c 2011-09-05 06:23:37 +0000
350@@ -0,0 +1,68 @@
351+/* { dg-require-effective-target vect_int } */
352+/* { dg-require-effective-target vect_shift } */
353+
354+#include <stdlib.h>
355+#include <stdarg.h>
356+#include "tree-vect.h"
357+
358+#define N 64
359+
360+/* Modified rgb to rgb conversion from FFmpeg. */
361+__attribute__ ((noinline)) int
362+foo (unsigned char *src, unsigned char *dst)
363+{
364+ unsigned char *s = src;
365+ unsigned short *d = (unsigned short *)dst, res;
366+ int i, result = 0;
367+
368+ for (i = 0; i < N/4; i++)
369+ {
370+ const int b = *s++;
371+ const int g = *s++;
372+ const int r = *s++;
373+ const int a = *s++;
374+ res = ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5));
375+ *d = res;
376+ result += res;
377+ d++;
378+ }
379+
380+ s = src;
381+ d = (unsigned short *)dst;
382+ for (i = 0; i < N/4; i++)
383+ {
384+ const int b = *s++;
385+ const int g = *s++;
386+ const int r = *s++;
387+ const int a = *s++;
388+ if (*d != ((b>>3) | ((g&0xFC)<<3) | ((r&0xF8)<<8) | (a>>5)))
389+ abort ();
390+ d++;
391+ }
392+
393+ return result;
394+}
395+
396+int main (void)
397+{
398+ int i;
399+ unsigned char in[N], out[N];
400+
401+ check_vect ();
402+
403+ for (i = 0; i < N; i++)
404+ {
405+ in[i] = i;
406+ out[i] = 255;
407+ __asm__ volatile ("");
408+ }
409+
410+ foo (in, out);
411+
412+ return 0;
413+}
414+
415+/* { dg-final { scan-tree-dump-times "vect_recog_over_widening_pattern: detected" 4 "vect" } } */
416+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
417+/* { dg-final { cleanup-tree-dump "vect" } } */
418+
419
420=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
421--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2011-05-05 15:43:31 +0000
422+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2011-09-05 06:23:37 +0000
423@@ -245,6 +245,18 @@
424 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-reassoc-bb-slp-*.\[cS\]]] \
425 "" $VECT_SLP_CFLAGS
426
427+# -fno-tree-fre
428+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
429+lappend DEFAULT_VECTCFLAGS "-fno-tree-fre"
430+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-tree-fre-*.\[cS\]]] \
431+ "" $DEFAULT_VECTCFLAGS
432+
433+# -fno-tree-fre -fno-tree-pre
434+set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
435+lappend DEFAULT_VECTCFLAGS "-fno-tree-fre" "-fno-tree-pre"
436+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/no-fre-pre*.\[cS\]]] \
437+ "" $DEFAULT_VECTCFLAGS
438+
439 # Clean up.
440 set dg-do-what-default ${save-dg-do-what-default}
441
442
443=== modified file 'gcc/tree-vect-loop.c'
444--- old/gcc/tree-vect-loop.c 2011-07-11 11:02:55 +0000
445+++ new/gcc/tree-vect-loop.c 2011-09-05 06:23:37 +0000
446@@ -181,8 +181,8 @@
447 stmt_vec_info stmt_info;
448 int i;
449 HOST_WIDE_INT dummy;
450- gimple stmt, pattern_stmt = NULL;
451- bool analyze_pattern_stmt = false;
452+ gimple stmt, pattern_stmt = NULL, pattern_def_stmt = NULL;
453+ bool analyze_pattern_stmt = false, pattern_def = false;
454
455 if (vect_print_dump_info (REPORT_DETAILS))
456 fprintf (vect_dump, "=== vect_determine_vectorization_factor ===");
457@@ -297,6 +297,29 @@
458 || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
459 analyze_pattern_stmt = true;
460
461+ /* If a pattern statement has a def stmt, analyze it too. */
462+ if (is_pattern_stmt_p (stmt_info)
463+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
464+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
465+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
466+ {
467+ if (pattern_def)
468+ pattern_def = false;
469+ else
470+ {
471+ if (vect_print_dump_info (REPORT_DETAILS))
472+ {
473+ fprintf (vect_dump, "==> examining pattern def stmt: ");
474+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
475+ TDF_SLIM);
476+ }
477+
478+ pattern_def = true;
479+ stmt = pattern_def_stmt;
480+ stmt_info = vinfo_for_stmt (stmt);
481+ }
482+ }
483+
484 if (gimple_get_lhs (stmt) == NULL_TREE)
485 {
486 if (vect_print_dump_info (REPORT_UNVECTORIZED_LOCATIONS))
487@@ -401,7 +424,7 @@
488 || (nunits > vectorization_factor))
489 vectorization_factor = nunits;
490
491- if (!analyze_pattern_stmt)
492+ if (!analyze_pattern_stmt && !pattern_def)
493 gsi_next (&si);
494 }
495 }
496@@ -3985,7 +4008,7 @@
497 VEC (tree, heap) *vec_oprnds0 = NULL, *vec_oprnds1 = NULL, *vect_defs = NULL;
498 VEC (gimple, heap) *phis = NULL;
499 int vec_num;
500- tree def0, def1, tem;
501+ tree def0, def1, tem, op0, op1 = NULL_TREE;
502
503 if (nested_in_vect_loop_p (loop, stmt))
504 {
505@@ -4418,8 +4441,6 @@
506 /* Handle uses. */
507 if (j == 0)
508 {
509- tree op0, op1 = NULL_TREE;
510-
511 op0 = ops[!reduc_index];
512 if (op_type == ternary_op)
513 {
514@@ -4449,11 +4470,19 @@
515 {
516 if (!slp_node)
517 {
518- enum vect_def_type dt = vect_unknown_def_type; /* Dummy */
519- loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt, loop_vec_def0);
520+ enum vect_def_type dt;
521+ gimple dummy_stmt;
522+ tree dummy;
523+
524+ vect_is_simple_use (ops[!reduc_index], loop_vinfo, NULL,
525+ &dummy_stmt, &dummy, &dt);
526+ loop_vec_def0 = vect_get_vec_def_for_stmt_copy (dt,
527+ loop_vec_def0);
528 VEC_replace (tree, vec_oprnds0, 0, loop_vec_def0);
529 if (op_type == ternary_op)
530 {
531+ vect_is_simple_use (op1, loop_vinfo, NULL, &dummy_stmt,
532+ &dummy, &dt);
533 loop_vec_def1 = vect_get_vec_def_for_stmt_copy (dt,
534 loop_vec_def1);
535 VEC_replace (tree, vec_oprnds1, 0, loop_vec_def1);
536@@ -4758,8 +4787,8 @@
537 tree cond_expr = NULL_TREE;
538 gimple_seq cond_expr_stmt_list = NULL;
539 bool do_peeling_for_loop_bound;
540- gimple stmt, pattern_stmt;
541- bool transform_pattern_stmt = false;
542+ gimple stmt, pattern_stmt, pattern_def_stmt;
543+ bool transform_pattern_stmt = false, pattern_def = false;
544
545 if (vect_print_dump_info (REPORT_DETAILS))
546 fprintf (vect_dump, "=== vec_transform_loop ===");
547@@ -4903,6 +4932,30 @@
548 || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_stmt))))
549 transform_pattern_stmt = true;
550
551+ /* If pattern statement has a def stmt, vectorize it too. */
552+ if (is_pattern_stmt_p (stmt_info)
553+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
554+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
555+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
556+ {
557+ if (pattern_def)
558+ pattern_def = false;
559+ else
560+ {
561+ if (vect_print_dump_info (REPORT_DETAILS))
562+ {
563+ fprintf (vect_dump, "==> vectorizing pattern def"
564+ " stmt: ");
565+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0,
566+ TDF_SLIM);
567+ }
568+
569+ pattern_def = true;
570+ stmt = pattern_def_stmt;
571+ stmt_info = vinfo_for_stmt (stmt);
572+ }
573+ }
574+
575 gcc_assert (STMT_VINFO_VECTYPE (stmt_info));
576 nunits = (unsigned int) TYPE_VECTOR_SUBPARTS (
577 STMT_VINFO_VECTYPE (stmt_info));
578@@ -4930,7 +4983,7 @@
579 /* Hybrid SLP stmts must be vectorized in addition to SLP. */
580 if (!vinfo_for_stmt (stmt) || PURE_SLP_STMT (stmt_info))
581 {
582- if (!transform_pattern_stmt)
583+ if (!transform_pattern_stmt && !pattern_def)
584 gsi_next (&si);
585 continue;
586 }
587@@ -4962,7 +5015,7 @@
588 }
589 }
590
591- if (!transform_pattern_stmt)
592+ if (!transform_pattern_stmt && !pattern_def)
593 gsi_next (&si);
594 } /* stmts in BB */
595 } /* BBs in loop */
596
597=== modified file 'gcc/tree-vect-patterns.c'
598--- old/gcc/tree-vect-patterns.c 2011-07-06 12:04:10 +0000
599+++ new/gcc/tree-vect-patterns.c 2011-09-05 06:23:37 +0000
600@@ -46,11 +46,14 @@
601 static gimple vect_recog_dot_prod_pattern (VEC (gimple, heap) **, tree *,
602 tree *);
603 static gimple vect_recog_pow_pattern (VEC (gimple, heap) **, tree *, tree *);
604+static gimple vect_recog_over_widening_pattern (VEC (gimple, heap) **, tree *,
605+ tree *);
606 static vect_recog_func_ptr vect_vect_recog_func_ptrs[NUM_PATTERNS] = {
607 vect_recog_widen_mult_pattern,
608 vect_recog_widen_sum_pattern,
609 vect_recog_dot_prod_pattern,
610- vect_recog_pow_pattern};
611+ vect_recog_pow_pattern,
612+ vect_recog_over_widening_pattern};
613
614
615 /* Function widened_name_p
616@@ -339,12 +342,14 @@
617 replace a_T = (TYPE) a_t; with a_it - (interm_type) a_t; */
618
619 static bool
620-vect_handle_widen_mult_by_const (tree const_oprnd, tree *oprnd,
621+vect_handle_widen_mult_by_const (gimple stmt, tree const_oprnd, tree *oprnd,
622 VEC (gimple, heap) **stmts, tree type,
623 tree *half_type, gimple def_stmt)
624 {
625 tree new_type, new_oprnd, tmp;
626 gimple new_stmt;
627+ loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
628+ struct loop *loop = LOOP_VINFO_LOOP (loop_info);
629
630 if (int_fits_type_p (const_oprnd, *half_type))
631 {
632@@ -354,6 +359,8 @@
633 }
634
635 if (TYPE_PRECISION (type) < (TYPE_PRECISION (*half_type) * 4)
636+ || !gimple_bb (def_stmt)
637+ || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
638 || !vinfo_for_stmt (def_stmt))
639 return false;
640
641@@ -522,7 +529,8 @@
642 {
643 if (TREE_CODE (oprnd0) == INTEGER_CST
644 && TREE_CODE (half_type1) == INTEGER_TYPE
645- && vect_handle_widen_mult_by_const (oprnd0, &oprnd1, stmts, type,
646+ && vect_handle_widen_mult_by_const (last_stmt, oprnd0, &oprnd1,
647+ stmts, type,
648 &half_type1, def_stmt1))
649 half_type0 = half_type1;
650 else
651@@ -532,7 +540,8 @@
652 {
653 if (TREE_CODE (oprnd1) == INTEGER_CST
654 && TREE_CODE (half_type0) == INTEGER_TYPE
655- && vect_handle_widen_mult_by_const (oprnd1, &oprnd0, stmts, type,
656+ && vect_handle_widen_mult_by_const (last_stmt, oprnd1, &oprnd0,
657+ stmts, type,
658 &half_type0, def_stmt0))
659 half_type1 = half_type0;
660 else
661@@ -826,6 +835,424 @@
662 }
663
664
665+/* Return TRUE if the operation in STMT can be performed on a smaller type.
666+
667+ Input:
668+ STMT - a statement to check.
669+ DEF - we support operations with two operands, one of which is constant.
670+ The other operand can be defined by a demotion operation, or by a
671+ previous statement in a sequence of over-promoted operations. In the
672+ later case DEF is used to replace that operand. (It is defined by a
673+ pattern statement we created for the previous statement in the
674+ sequence).
675+
676+ Input/output:
677+ NEW_TYPE - Output: a smaller type that we are trying to use. Input: if not
678+ NULL, it's the type of DEF.
679+ STMTS - additional pattern statements. If a pattern statement (type
680+ conversion) is created in this function, its original statement is
681+ added to STMTS.
682+
683+ Output:
684+ OP0, OP1 - if the operation fits a smaller type, OP0 and OP1 are the new
685+ operands to use in the new pattern statement for STMT (will be created
686+ in vect_recog_over_widening_pattern ()).
687+ NEW_DEF_STMT - in case DEF has to be promoted, we create two pattern
688+ statements for STMT: the first one is a type promotion and the second
689+ one is the operation itself. We return the type promotion statement
690+ in NEW_DEF_STMT and further store it in STMT_VINFO_PATTERN_DEF_STMT of
691+ the second pattern statement. */
692+
693+static bool
694+vect_operation_fits_smaller_type (gimple stmt, tree def, tree *new_type,
695+ tree *op0, tree *op1, gimple *new_def_stmt,
696+ VEC (gimple, heap) **stmts)
697+{
698+ enum tree_code code;
699+ tree const_oprnd, oprnd;
700+ tree interm_type = NULL_TREE, half_type, tmp, new_oprnd, type;
701+ gimple def_stmt, new_stmt;
702+ bool first = false;
703+ loop_vec_info loop_info = STMT_VINFO_LOOP_VINFO (vinfo_for_stmt (stmt));
704+ struct loop *loop = LOOP_VINFO_LOOP (loop_info);
705+
706+ *new_def_stmt = NULL;
707+
708+ if (!is_gimple_assign (stmt))
709+ return false;
710+
711+ code = gimple_assign_rhs_code (stmt);
712+ if (code != LSHIFT_EXPR && code != RSHIFT_EXPR
713+ && code != BIT_IOR_EXPR && code != BIT_XOR_EXPR && code != BIT_AND_EXPR)
714+ return false;
715+
716+ oprnd = gimple_assign_rhs1 (stmt);
717+ const_oprnd = gimple_assign_rhs2 (stmt);
718+ type = gimple_expr_type (stmt);
719+
720+ if (TREE_CODE (oprnd) != SSA_NAME
721+ || TREE_CODE (const_oprnd) != INTEGER_CST)
722+ return false;
723+
724+ /* If we are in the middle of a sequence, we use DEF from a previous
725+ statement. Otherwise, OPRND has to be a result of type promotion. */
726+ if (*new_type)
727+ {
728+ half_type = *new_type;
729+ oprnd = def;
730+ }
731+ else
732+ {
733+ first = true;
734+ if (!widened_name_p (oprnd, stmt, &half_type, &def_stmt, false)
735+ || !gimple_bb (def_stmt)
736+ || !flow_bb_inside_loop_p (loop, gimple_bb (def_stmt))
737+ || !vinfo_for_stmt (def_stmt))
738+ return false;
739+ }
740+
741+ /* Can we perform the operation on a smaller type? */
742+ switch (code)
743+ {
744+ case BIT_IOR_EXPR:
745+ case BIT_XOR_EXPR:
746+ case BIT_AND_EXPR:
747+ if (!int_fits_type_p (const_oprnd, half_type))
748+ {
749+ /* HALF_TYPE is not enough. Try a bigger type if possible. */
750+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
751+ return false;
752+
753+ interm_type = build_nonstandard_integer_type (
754+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
755+ if (!int_fits_type_p (const_oprnd, interm_type))
756+ return false;
757+ }
758+
759+ break;
760+
761+ case LSHIFT_EXPR:
762+ /* Try intermediate type - HALF_TYPE is not enough for sure. */
763+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
764+ return false;
765+
766+ /* Check that HALF_TYPE size + shift amount <= INTERM_TYPE size.
767+ (e.g., if the original value was char, the shift amount is at most 8
768+ if we want to use short). */
769+ if (compare_tree_int (const_oprnd, TYPE_PRECISION (half_type)) == 1)
770+ return false;
771+
772+ interm_type = build_nonstandard_integer_type (
773+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
774+
775+ if (!vect_supportable_shift (code, interm_type))
776+ return false;
777+
778+ break;
779+
780+ case RSHIFT_EXPR:
781+ if (vect_supportable_shift (code, half_type))
782+ break;
783+
784+ /* Try intermediate type - HALF_TYPE is not supported. */
785+ if (TYPE_PRECISION (type) < (TYPE_PRECISION (half_type) * 4))
786+ return false;
787+
788+ interm_type = build_nonstandard_integer_type (
789+ TYPE_PRECISION (half_type) * 2, TYPE_UNSIGNED (type));
790+
791+ if (!vect_supportable_shift (code, interm_type))
792+ return false;
793+
794+ break;
795+
796+ default:
797+ gcc_unreachable ();
798+ }
799+
800+ /* There are four possible cases:
801+ 1. OPRND is defined by a type promotion (in that case FIRST is TRUE, it's
802+ the first statement in the sequence)
803+ a. The original, HALF_TYPE, is not enough - we replace the promotion
804+ from HALF_TYPE to TYPE with a promotion to INTERM_TYPE.
805+ b. HALF_TYPE is sufficient, OPRND is set as the RHS of the original
806+ promotion.
807+ 2. OPRND is defined by a pattern statement we created.
808+ a. Its type is not sufficient for the operation, we create a new stmt:
809+ a type conversion for OPRND from HALF_TYPE to INTERM_TYPE. We store
810+ this statement in NEW_DEF_STMT, and it is later put in
811+ STMT_VINFO_PATTERN_DEF_STMT of the pattern statement for STMT.
812+ b. OPRND is good to use in the new statement. */
813+ if (first)
814+ {
815+ if (interm_type)
816+ {
817+ /* Replace the original type conversion HALF_TYPE->TYPE with
818+ HALF_TYPE->INTERM_TYPE. */
819+ if (STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)))
820+ {
821+ new_stmt = STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt));
822+ /* Check if the already created pattern stmt is what we need. */
823+ if (!is_gimple_assign (new_stmt)
824+ || gimple_assign_rhs_code (new_stmt) != NOP_EXPR
825+ || TREE_TYPE (gimple_assign_lhs (new_stmt)) != interm_type)
826+ return false;
827+
828+ oprnd = gimple_assign_lhs (new_stmt);
829+ }
830+ else
831+ {
832+ /* Create NEW_OPRND = (INTERM_TYPE) OPRND. */
833+ oprnd = gimple_assign_rhs1 (def_stmt);
834+ tmp = create_tmp_reg (interm_type, NULL);
835+ add_referenced_var (tmp);
836+ new_oprnd = make_ssa_name (tmp, NULL);
837+ new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
838+ oprnd, NULL_TREE);
839+ SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
840+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (def_stmt)) = new_stmt;
841+ VEC_safe_push (gimple, heap, *stmts, def_stmt);
842+ oprnd = new_oprnd;
843+ }
844+ }
845+ else
846+ {
847+ /* Retrieve the operand before the type promotion. */
848+ oprnd = gimple_assign_rhs1 (def_stmt);
849+ }
850+ }
851+ else
852+ {
853+ if (interm_type)
854+ {
855+ /* Create a type conversion HALF_TYPE->INTERM_TYPE. */
856+ tmp = create_tmp_reg (interm_type, NULL);
857+ add_referenced_var (tmp);
858+ new_oprnd = make_ssa_name (tmp, NULL);
859+ new_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
860+ oprnd, NULL_TREE);
861+ SSA_NAME_DEF_STMT (new_oprnd) = new_stmt;
862+ oprnd = new_oprnd;
863+ *new_def_stmt = new_stmt;
864+ }
865+
866+ /* Otherwise, OPRND is already set. */
867+ }
868+
869+ if (interm_type)
870+ *new_type = interm_type;
871+ else
872+ *new_type = half_type;
873+
874+ *op0 = oprnd;
875+ *op1 = fold_convert (*new_type, const_oprnd);
876+
877+ return true;
878+}
879+
880+
881+/* Try to find a statement or a sequence of statements that can be performed
882+ on a smaller type:
883+
884+ type x_t;
885+ TYPE x_T, res0_T, res1_T;
886+ loop:
887+ S1 x_t = *p;
888+ S2 x_T = (TYPE) x_t;
889+ S3 res0_T = op (x_T, C0);
890+ S4 res1_T = op (res0_T, C1);
891+ S5 ... = () res1_T; - type demotion
892+
893+ where type 'TYPE' is at least double the size of type 'type', C0 and C1 are
894+ constants.
895+ Check if S3 and S4 can be done on a smaller type than 'TYPE', it can either
896+ be 'type' or some intermediate type. For now, we expect S5 to be a type
897+ demotion operation. We also check that S3 and S4 have only one use.
898+.
899+
900+*/
901+static gimple
902+vect_recog_over_widening_pattern (VEC (gimple, heap) **stmts,
903+ tree *type_in, tree *type_out)
904+{
905+ gimple stmt = VEC_pop (gimple, *stmts);
906+ gimple pattern_stmt = NULL, new_def_stmt, prev_stmt = NULL, use_stmt = NULL;
907+ tree op0, op1, vectype = NULL_TREE, lhs, use_lhs, use_type;
908+ imm_use_iterator imm_iter;
909+ use_operand_p use_p;
910+ int nuses = 0;
911+ tree var = NULL_TREE, new_type = NULL_TREE, tmp, new_oprnd;
912+ bool first;
913+ struct loop *loop = (gimple_bb (stmt))->loop_father;
914+
915+ first = true;
916+ while (1)
917+ {
918+ if (!vinfo_for_stmt (stmt)
919+ || STMT_VINFO_IN_PATTERN_P (vinfo_for_stmt (stmt)))
920+ return NULL;
921+
922+ new_def_stmt = NULL;
923+ if (!vect_operation_fits_smaller_type (stmt, var, &new_type,
924+ &op0, &op1, &new_def_stmt,
925+ stmts))
926+ {
927+ if (first)
928+ return NULL;
929+ else
930+ break;
931+ }
932+
933+ /* STMT can be performed on a smaller type. Check its uses. */
934+ lhs = gimple_assign_lhs (stmt);
935+ nuses = 0;
936+ FOR_EACH_IMM_USE_FAST (use_p, imm_iter, lhs)
937+ {
938+ if (is_gimple_debug (USE_STMT (use_p)))
939+ continue;
940+ use_stmt = USE_STMT (use_p);
941+ nuses++;
942+ }
943+
944+ if (nuses != 1 || !is_gimple_assign (use_stmt)
945+ || !gimple_bb (use_stmt)
946+ || !flow_bb_inside_loop_p (loop, gimple_bb (use_stmt)))
947+ return NULL;
948+
949+ /* Create pattern statement for STMT. */
950+ vectype = get_vectype_for_scalar_type (new_type);
951+ if (!vectype)
952+ return NULL;
953+
954+ /* We want to collect all the statements for which we create pattern
955+ statetments, except for the case when the last statement in the
956+ sequence doesn't have a corresponding pattern statement. In such
957+ case we associate the last pattern statement with the last statement
958+ in the sequence. Therefore, we only add an original statetement to
959+ the list if we know that it is not the last. */
960+ if (prev_stmt)
961+ VEC_safe_push (gimple, heap, *stmts, prev_stmt);
962+
963+ var = vect_recog_temp_ssa_var (new_type, NULL);
964+ pattern_stmt = gimple_build_assign_with_ops (
965+ gimple_assign_rhs_code (stmt), var, op0, op1);
966+ SSA_NAME_DEF_STMT (var) = pattern_stmt;
967+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (stmt)) = pattern_stmt;
968+ STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (stmt)) = new_def_stmt;
969+
970+ if (vect_print_dump_info (REPORT_DETAILS))
971+ {
972+ fprintf (vect_dump, "created pattern stmt: ");
973+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
974+ }
975+
976+ prev_stmt = stmt;
977+ stmt = use_stmt;
978+
979+ first = false;
980+ }
981+
982+ /* We got a sequence. We expect it to end with a type demotion operation.
983+ Otherwise, we quit (for now). There are three possible cases: the
984+ conversion is to NEW_TYPE (we don't do anything), the conversion is to
985+ a type bigger than NEW_TYPE and/or the signedness of USE_TYPE and
986+ NEW_TYPE differs (we create a new conversion statement). */
987+ if (CONVERT_EXPR_CODE_P (gimple_assign_rhs_code (use_stmt)))
988+ {
989+ use_lhs = gimple_assign_lhs (use_stmt);
990+ use_type = TREE_TYPE (use_lhs);
991+ /* Support only type promotion or signedess change. */
992+ if (!INTEGRAL_TYPE_P (use_type)
993+ || TYPE_PRECISION (new_type) > TYPE_PRECISION (use_type))
994+ return NULL;
995+
996+ if (TYPE_UNSIGNED (new_type) != TYPE_UNSIGNED (use_type)
997+ || TYPE_PRECISION (new_type) != TYPE_PRECISION (use_type))
998+ {
999+ /* Create NEW_TYPE->USE_TYPE conversion. */
1000+ tmp = create_tmp_reg (use_type, NULL);
1001+ add_referenced_var (tmp);
1002+ new_oprnd = make_ssa_name (tmp, NULL);
1003+ pattern_stmt = gimple_build_assign_with_ops (NOP_EXPR, new_oprnd,
1004+ var, NULL_TREE);
1005+ SSA_NAME_DEF_STMT (new_oprnd) = pattern_stmt;
1006+ STMT_VINFO_RELATED_STMT (vinfo_for_stmt (use_stmt)) = pattern_stmt;
1007+
1008+ *type_in = get_vectype_for_scalar_type (new_type);
1009+ *type_out = get_vectype_for_scalar_type (use_type);
1010+
1011+ /* We created a pattern statement for the last statement in the
1012+ sequence, so we don't need to associate it with the pattern
1013+ statement created for PREV_STMT. Therefore, we add PREV_STMT
1014+ to the list in order to mark it later in vect_pattern_recog_1. */
1015+ if (prev_stmt)
1016+ VEC_safe_push (gimple, heap, *stmts, prev_stmt);
1017+ }
1018+ else
1019+ {
1020+ if (prev_stmt)
1021+ STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (use_stmt))
1022+ = STMT_VINFO_PATTERN_DEF_STMT (vinfo_for_stmt (prev_stmt));
1023+
1024+ *type_in = vectype;
1025+ *type_out = NULL_TREE;
1026+ }
1027+
1028+ VEC_safe_push (gimple, heap, *stmts, use_stmt);
1029+ }
1030+ else
1031+ /* TODO: support general case, create a conversion to the correct type. */
1032+ return NULL;
1033+
1034+ /* Pattern detected. */
1035+ if (vect_print_dump_info (REPORT_DETAILS))
1036+ {
1037+ fprintf (vect_dump, "vect_recog_over_widening_pattern: detected: ");
1038+ print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
1039+ }
1040+
1041+ return pattern_stmt;
1042+}
1043+
1044+
1045+/* Mark statements that are involved in a pattern. */
1046+
1047+static inline void
1048+vect_mark_pattern_stmts (gimple orig_stmt, gimple pattern_stmt,
1049+ tree pattern_vectype)
1050+{
1051+ stmt_vec_info pattern_stmt_info, def_stmt_info;
1052+ stmt_vec_info orig_stmt_info = vinfo_for_stmt (orig_stmt);
1053+ loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (orig_stmt_info);
1054+ gimple def_stmt;
1055+
1056+ set_vinfo_for_stmt (pattern_stmt,
1057+ new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1058+ gimple_set_bb (pattern_stmt, gimple_bb (orig_stmt));
1059+ pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1060+
1061+ STMT_VINFO_RELATED_STMT (pattern_stmt_info) = orig_stmt;
1062+ STMT_VINFO_DEF_TYPE (pattern_stmt_info)
1063+ = STMT_VINFO_DEF_TYPE (orig_stmt_info);
1064+ STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
1065+ STMT_VINFO_IN_PATTERN_P (orig_stmt_info) = true;
1066+ STMT_VINFO_RELATED_STMT (orig_stmt_info) = pattern_stmt;
1067+ STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info)
1068+ = STMT_VINFO_PATTERN_DEF_STMT (orig_stmt_info);
1069+ if (STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info))
1070+ {
1071+ def_stmt = STMT_VINFO_PATTERN_DEF_STMT (pattern_stmt_info);
1072+ set_vinfo_for_stmt (def_stmt,
1073+ new_stmt_vec_info (def_stmt, loop_vinfo, NULL));
1074+ gimple_set_bb (def_stmt, gimple_bb (orig_stmt));
1075+ def_stmt_info = vinfo_for_stmt (def_stmt);
1076+ STMT_VINFO_RELATED_STMT (def_stmt_info) = orig_stmt;
1077+ STMT_VINFO_DEF_TYPE (def_stmt_info)
1078+ = STMT_VINFO_DEF_TYPE (orig_stmt_info);
1079+ STMT_VINFO_VECTYPE (def_stmt_info) = pattern_vectype;
1080+ }
1081+}
1082+
1083 /* Function vect_pattern_recog_1
1084
1085 Input:
1086@@ -855,7 +1282,6 @@
1087 {
1088 gimple stmt = gsi_stmt (si), pattern_stmt;
1089 stmt_vec_info stmt_info;
1090- stmt_vec_info pattern_stmt_info;
1091 loop_vec_info loop_vinfo;
1092 tree pattern_vectype;
1093 tree type_in, type_out;
1094@@ -923,16 +1349,7 @@
1095 }
1096
1097 /* Mark the stmts that are involved in the pattern. */
1098- set_vinfo_for_stmt (pattern_stmt,
1099- new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1100- gimple_set_bb (pattern_stmt, gimple_bb (stmt));
1101- pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1102-
1103- STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
1104- STMT_VINFO_DEF_TYPE (pattern_stmt_info) = STMT_VINFO_DEF_TYPE (stmt_info);
1105- STMT_VINFO_VECTYPE (pattern_stmt_info) = pattern_vectype;
1106- STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
1107- STMT_VINFO_RELATED_STMT (stmt_info) = pattern_stmt;
1108+ vect_mark_pattern_stmts (stmt, pattern_stmt, pattern_vectype);
1109
1110 /* Patterns cannot be vectorized using SLP, because they change the order of
1111 computation. */
1112@@ -940,9 +1357,9 @@
1113 if (next == stmt)
1114 VEC_ordered_remove (gimple, LOOP_VINFO_REDUCTIONS (loop_vinfo), i);
1115
1116- /* In case of widen-mult by a constant, it is possible that an additional
1117- pattern stmt is created and inserted in STMTS_TO_REPLACE. We create a
1118- stmt_info for it, and mark the relevant statements. */
1119+ /* It is possible that additional pattern stmts are created and inserted in
1120+ STMTS_TO_REPLACE. We create a stmt_info for each of them, and mark the
1121+ relevant statements. */
1122 for (i = 0; VEC_iterate (gimple, stmts_to_replace, i, stmt)
1123 && (unsigned) i < (VEC_length (gimple, stmts_to_replace) - 1);
1124 i++)
1125@@ -955,16 +1372,7 @@
1126 print_gimple_stmt (vect_dump, pattern_stmt, 0, TDF_SLIM);
1127 }
1128
1129- set_vinfo_for_stmt (pattern_stmt,
1130- new_stmt_vec_info (pattern_stmt, loop_vinfo, NULL));
1131- gimple_set_bb (pattern_stmt, gimple_bb (stmt));
1132- pattern_stmt_info = vinfo_for_stmt (pattern_stmt);
1133-
1134- STMT_VINFO_RELATED_STMT (pattern_stmt_info) = stmt;
1135- STMT_VINFO_DEF_TYPE (pattern_stmt_info)
1136- = STMT_VINFO_DEF_TYPE (stmt_info);
1137- STMT_VINFO_VECTYPE (pattern_stmt_info) = STMT_VINFO_VECTYPE (stmt_info);
1138- STMT_VINFO_IN_PATTERN_P (stmt_info) = true;
1139+ vect_mark_pattern_stmts (stmt, pattern_stmt, NULL_TREE);
1140 }
1141
1142 VEC_free (gimple, heap, stmts_to_replace);
1143
1144=== modified file 'gcc/tree-vect-stmts.c'
1145--- old/gcc/tree-vect-stmts.c 2011-07-06 12:04:10 +0000
1146+++ new/gcc/tree-vect-stmts.c 2011-09-05 06:23:37 +0000
1147@@ -2246,6 +2246,42 @@
1148 }
1149
1150
1151+/* Return TRUE if CODE (a shift operation) is supported for SCALAR_TYPE
1152+ either as shift by a scalar or by a vector. */
1153+
1154+bool
1155+vect_supportable_shift (enum tree_code code, tree scalar_type)
1156+{
1157+
1158+ enum machine_mode vec_mode;
1159+ optab optab;
1160+ int icode;
1161+ tree vectype;
1162+
1163+ vectype = get_vectype_for_scalar_type (scalar_type);
1164+ if (!vectype)
1165+ return false;
1166+
1167+ optab = optab_for_tree_code (code, vectype, optab_scalar);
1168+ if (!optab
1169+ || optab_handler (optab, TYPE_MODE (vectype)) == CODE_FOR_nothing)
1170+ {
1171+ optab = optab_for_tree_code (code, vectype, optab_vector);
1172+ if (!optab
1173+ || (optab_handler (optab, TYPE_MODE (vectype))
1174+ == CODE_FOR_nothing))
1175+ return false;
1176+ }
1177+
1178+ vec_mode = TYPE_MODE (vectype);
1179+ icode = (int) optab_handler (optab, vec_mode);
1180+ if (icode == CODE_FOR_nothing)
1181+ return false;
1182+
1183+ return true;
1184+}
1185+
1186+
1187 /* Function vectorizable_shift.
1188
1189 Check if STMT performs a shift operation that can be vectorized.
1190@@ -4946,7 +4982,7 @@
1191 enum vect_relevant relevance = STMT_VINFO_RELEVANT (stmt_info);
1192 bool ok;
1193 tree scalar_type, vectype;
1194- gimple pattern_stmt;
1195+ gimple pattern_stmt, pattern_def_stmt;
1196
1197 if (vect_print_dump_info (REPORT_DETAILS))
1198 {
1199@@ -5016,6 +5052,23 @@
1200 return false;
1201 }
1202
1203+ if (is_pattern_stmt_p (stmt_info)
1204+ && (pattern_def_stmt = STMT_VINFO_PATTERN_DEF_STMT (stmt_info))
1205+ && (STMT_VINFO_RELEVANT_P (vinfo_for_stmt (pattern_def_stmt))
1206+ || STMT_VINFO_LIVE_P (vinfo_for_stmt (pattern_def_stmt))))
1207+ {
1208+ /* Analyze def stmt of STMT if it's a pattern stmt. */
1209+ if (vect_print_dump_info (REPORT_DETAILS))
1210+ {
1211+ fprintf (vect_dump, "==> examining pattern def statement: ");
1212+ print_gimple_stmt (vect_dump, pattern_def_stmt, 0, TDF_SLIM);
1213+ }
1214+
1215+ if (!vect_analyze_stmt (pattern_def_stmt, need_to_vectorize, node))
1216+ return false;
1217+ }
1218+
1219+
1220 switch (STMT_VINFO_DEF_TYPE (stmt_info))
1221 {
1222 case vect_internal_def:
1223@@ -5336,6 +5389,7 @@
1224 STMT_VINFO_VECTORIZABLE (res) = true;
1225 STMT_VINFO_IN_PATTERN_P (res) = false;
1226 STMT_VINFO_RELATED_STMT (res) = NULL;
1227+ STMT_VINFO_PATTERN_DEF_STMT (res) = NULL;
1228 STMT_VINFO_DATA_REF (res) = NULL;
1229
1230 STMT_VINFO_DR_BASE_ADDRESS (res) = NULL;
1231
1232=== modified file 'gcc/tree-vectorizer.h'
1233--- old/gcc/tree-vectorizer.h 2011-07-11 11:02:55 +0000
1234+++ new/gcc/tree-vectorizer.h 2011-09-05 06:23:37 +0000
1235@@ -464,6 +464,9 @@
1236 pattern). */
1237 gimple related_stmt;
1238
1239+ /* Used to keep a def stmt of a pattern stmt if such exists. */
1240+ gimple pattern_def_stmt;
1241+
1242 /* List of datarefs that are known to have the same alignment as the dataref
1243 of this stmt. */
1244 VEC(dr_p,heap) *same_align_refs;
1245@@ -531,6 +534,7 @@
1246
1247 #define STMT_VINFO_IN_PATTERN_P(S) (S)->in_pattern_p
1248 #define STMT_VINFO_RELATED_STMT(S) (S)->related_stmt
1249+#define STMT_VINFO_PATTERN_DEF_STMT(S) (S)->pattern_def_stmt
1250 #define STMT_VINFO_SAME_ALIGN_REFS(S) (S)->same_align_refs
1251 #define STMT_VINFO_DEF_TYPE(S) (S)->def_type
1252 #define STMT_VINFO_DR_GROUP_FIRST_DR(S) (S)->first_dr
1253@@ -814,6 +818,7 @@
1254 extern void vect_get_load_cost (struct data_reference *, int, bool,
1255 unsigned int *, unsigned int *);
1256 extern void vect_get_store_cost (struct data_reference *, int, unsigned int *);
1257+extern bool vect_supportable_shift (enum tree_code, tree);
1258
1259 /* In tree-vect-data-refs.c. */
1260 extern bool vect_can_force_dr_alignment_p (const_tree, unsigned int);
1261@@ -891,7 +896,7 @@
1262 Additional pattern recognition functions can (and will) be added
1263 in the future. */
1264 typedef gimple (* vect_recog_func_ptr) (VEC (gimple, heap) **, tree *, tree *);
1265-#define NUM_PATTERNS 4
1266+#define NUM_PATTERNS 5
1267 void vect_pattern_recog (loop_vec_info);
1268
1269 /* In tree-vectorizer.c. */
1270
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
new file mode 100644
index 0000000000..ade96fdd11
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106802.patch
@@ -0,0 +1,948 @@
12011-09-12 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-08-30 Andrew Stubbs <ams@codesourcery.com>
6
7 gcc/
8 * config/arm/arm.c (optimal_immediate_sequence_1): Make b1, b2,
9 b3 and b4 unsigned.
10
11 2011-08-30 Andrew Stubbs <ams@codesourcery.com>
12
13 gcc/
14 * config/arm/arm.c (arm_gen_constant): Set can_negate correctly
15 when code is SET.
16
17 2011-08-26 Andrew Stubbs <ams@codesourcery.com>
18
19 gcc/
20 * config/arm/arm.c (struct four_ints): New type.
21 (count_insns_for_constant): Delete function.
22 (find_best_start): Delete function.
23 (optimal_immediate_sequence): New function.
24 (optimal_immediate_sequence_1): New function.
25 (arm_gen_constant): Move constant splitting code to
26 optimal_immediate_sequence.
27 Rewrite constant negation/invertion code.
28
29 gcc/testsuite/
30 * gcc.target/arm/thumb2-replicated-constant1.c: New file.
31 * gcc.target/arm/thumb2-replicated-constant2.c: New file.
32 * gcc.target/arm/thumb2-replicated-constant3.c: New file.
33 * gcc.target/arm/thumb2-replicated-constant4.c: New file.
34
35 2011-08-26 Andrew Stubbs <ams@codesourcery.com>
36
37 gcc/
38 * config/arm/arm-protos.h (const_ok_for_op): Add prototype.
39 * config/arm/arm.c (const_ok_for_op): Add support for addw/subw.
40 Remove prototype. Remove static function type.
41 * config/arm/arm.md (*arm_addsi3): Add addw/subw support.
42 Add arch attribute.
43 * config/arm/constraints.md (Pj, PJ): New constraints.
44
45 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
46
47 gcc/
48 * config/arm/arm.c (arm_gen_constant): Move mowv support ....
49 (const_ok_for_op): ... to here.
50
51 2011-04-20 Andrew Stubbs <ams@codesourcery.com>
52
53 gcc/
54 * config/arm/arm.c (arm_gen_constant): Remove redundant can_invert.
55
56
57=== modified file 'gcc/config/arm/arm-protos.h'
58--- old/gcc/config/arm/arm-protos.h 2011-07-04 14:03:49 +0000
59+++ new/gcc/config/arm/arm-protos.h 2011-08-25 13:26:58 +0000
60@@ -46,6 +46,7 @@
61 extern bool arm_small_register_classes_for_mode_p (enum machine_mode);
62 extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode);
63 extern int const_ok_for_arm (HOST_WIDE_INT);
64+extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
65 extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int);
67 extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
68
69=== modified file 'gcc/config/arm/arm.c'
70--- old/gcc/config/arm/arm.c 2011-08-24 17:35:16 +0000
71+++ new/gcc/config/arm/arm.c 2011-09-06 12:57:56 +0000
72@@ -63,6 +63,11 @@
73
74 void (*arm_lang_output_object_attributes_hook)(void);
75
76+struct four_ints
77+{
78+ int i[4];
79+};
80+
81 /* Forward function declarations. */
82 static bool arm_needs_doubleword_align (enum machine_mode, const_tree);
83 static int arm_compute_static_chain_stack_bytes (void);
84@@ -81,7 +86,6 @@
85 static bool arm_legitimate_address_p (enum machine_mode, rtx, bool);
86 static int thumb_far_jump_used_p (void);
87 static bool thumb_force_lr_save (void);
88-static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
89 static rtx emit_sfm (int, int);
90 static unsigned arm_size_return_regs (void);
91 static bool arm_assemble_integer (rtx, unsigned int, int);
92@@ -129,7 +133,13 @@
93 static int arm_comp_type_attributes (const_tree, const_tree);
94 static void arm_set_default_type_attributes (tree);
95 static int arm_adjust_cost (rtx, rtx, rtx, int);
96-static int count_insns_for_constant (HOST_WIDE_INT, int);
97+static int optimal_immediate_sequence (enum rtx_code code,
98+ unsigned HOST_WIDE_INT val,
99+ struct four_ints *return_sequence);
100+static int optimal_immediate_sequence_1 (enum rtx_code code,
101+ unsigned HOST_WIDE_INT val,
102+ struct four_ints *return_sequence,
103+ int i);
104 static int arm_get_strip_length (int);
105 static bool arm_function_ok_for_sibcall (tree, tree);
106 static enum machine_mode arm_promote_function_mode (const_tree,
107@@ -2525,7 +2535,7 @@
108 }
109
110 /* Return true if I is a valid constant for the operation CODE. */
111-static int
112+int
113 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
114 {
115 if (const_ok_for_arm (i))
116@@ -2533,7 +2543,21 @@
117
118 switch (code)
119 {
120+ case SET:
121+ /* See if we can use movw. */
122+ if (arm_arch_thumb2 && (i & 0xffff0000) == 0)
123+ return 1;
124+ else
125+ return 0;
126+
127 case PLUS:
128+ /* See if we can use addw or subw. */
129+ if (TARGET_THUMB2
130+ && ((i & 0xfffff000) == 0
131+ || ((-i) & 0xfffff000) == 0))
132+ return 1;
133+ /* else fall through. */
134+
135 case COMPARE:
136 case EQ:
137 case NE:
138@@ -2649,68 +2673,41 @@
139 1);
140 }
141
142-/* Return the number of instructions required to synthesize the given
143- constant, if we start emitting them from bit-position I. */
144-static int
145-count_insns_for_constant (HOST_WIDE_INT remainder, int i)
146-{
147- HOST_WIDE_INT temp1;
148- int step_size = TARGET_ARM ? 2 : 1;
149- int num_insns = 0;
150-
151- gcc_assert (TARGET_ARM || i == 0);
152-
153- do
154- {
155- int end;
156-
157- if (i <= 0)
158- i += 32;
159- if (remainder & (((1 << step_size) - 1) << (i - step_size)))
160- {
161- end = i - 8;
162- if (end < 0)
163- end += 32;
164- temp1 = remainder & ((0x0ff << end)
165- | ((i < end) ? (0xff >> (32 - end)) : 0));
166- remainder &= ~temp1;
167- num_insns++;
168- i -= 8 - step_size;
169- }
170- i -= step_size;
171- } while (remainder);
172- return num_insns;
173-}
174-
175-static int
176-find_best_start (unsigned HOST_WIDE_INT remainder)
177+/* Return a sequence of integers, in RETURN_SEQUENCE that fit into
178+ ARM/THUMB2 immediates, and add up to VAL.
179+ Thr function return value gives the number of insns required. */
180+static int
181+optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
182+ struct four_ints *return_sequence)
183 {
184 int best_consecutive_zeros = 0;
185 int i;
186 int best_start = 0;
187+ int insns1, insns2;
188+ struct four_ints tmp_sequence;
189
190 /* If we aren't targetting ARM, the best place to start is always at
191- the bottom. */
192- if (! TARGET_ARM)
193- return 0;
194-
195- for (i = 0; i < 32; i += 2)
196+ the bottom, otherwise look more closely. */
197+ if (TARGET_ARM)
198 {
199- int consecutive_zeros = 0;
200-
201- if (!(remainder & (3 << i)))
202+ for (i = 0; i < 32; i += 2)
203 {
204- while ((i < 32) && !(remainder & (3 << i)))
205- {
206- consecutive_zeros += 2;
207- i += 2;
208- }
209- if (consecutive_zeros > best_consecutive_zeros)
210- {
211- best_consecutive_zeros = consecutive_zeros;
212- best_start = i - consecutive_zeros;
213- }
214- i -= 2;
215+ int consecutive_zeros = 0;
216+
217+ if (!(val & (3 << i)))
218+ {
219+ while ((i < 32) && !(val & (3 << i)))
220+ {
221+ consecutive_zeros += 2;
222+ i += 2;
223+ }
224+ if (consecutive_zeros > best_consecutive_zeros)
225+ {
226+ best_consecutive_zeros = consecutive_zeros;
227+ best_start = i - consecutive_zeros;
228+ }
229+ i -= 2;
230+ }
231 }
232 }
233
234@@ -2737,13 +2734,161 @@
235 the constant starting from `best_start', and also starting from
236 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
237 yield a shorter sequence, we may as well use zero. */
238+ insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
239 if (best_start != 0
240- && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
241- && (count_insns_for_constant (remainder, 0) <=
242- count_insns_for_constant (remainder, best_start)))
243- best_start = 0;
244-
245- return best_start;
246+ && ((((unsigned HOST_WIDE_INT) 1) << best_start) < val))
247+ {
248+ insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
249+ if (insns2 <= insns1)
250+ {
251+ *return_sequence = tmp_sequence;
252+ insns1 = insns2;
253+ }
254+ }
255+
256+ return insns1;
257+}
258+
259+/* As for optimal_immediate_sequence, but starting at bit-position I. */
260+static int
261+optimal_immediate_sequence_1 (enum rtx_code code, unsigned HOST_WIDE_INT val,
262+ struct four_ints *return_sequence, int i)
263+{
264+ int remainder = val & 0xffffffff;
265+ int insns = 0;
266+
267+ /* Try and find a way of doing the job in either two or three
268+ instructions.
269+
270+ In ARM mode we can use 8-bit constants, rotated to any 2-bit aligned
271+ location. We start at position I. This may be the MSB, or
272+ optimial_immediate_sequence may have positioned it at the largest block
273+ of zeros that are aligned on a 2-bit boundary. We then fill up the temps,
274+ wrapping around to the top of the word when we drop off the bottom.
275+ In the worst case this code should produce no more than four insns.
276+
277+ In Thumb2 mode, we can use 32/16-bit replicated constants, and 8-bit
278+ constants, shifted to any arbitrary location. We should always start
279+ at the MSB. */
280+ do
281+ {
282+ int end;
283+ unsigned int b1, b2, b3, b4;
284+ unsigned HOST_WIDE_INT result;
285+ int loc;
286+
287+ gcc_assert (insns < 4);
288+
289+ if (i <= 0)
290+ i += 32;
291+
292+ /* First, find the next normal 12/8-bit shifted/rotated immediate. */
293+ if (remainder & ((TARGET_ARM ? (3 << (i - 2)) : (1 << (i - 1)))))
294+ {
295+ loc = i;
296+ if (i <= 12 && TARGET_THUMB2 && code == PLUS)
297+ /* We can use addw/subw for the last 12 bits. */
298+ result = remainder;
299+ else
300+ {
301+ /* Use an 8-bit shifted/rotated immediate. */
302+ end = i - 8;
303+ if (end < 0)
304+ end += 32;
305+ result = remainder & ((0x0ff << end)
306+ | ((i < end) ? (0xff >> (32 - end))
307+ : 0));
308+ i -= 8;
309+ }
310+ }
311+ else
312+ {
313+ /* Arm allows rotates by a multiple of two. Thumb-2 allows
314+ arbitrary shifts. */
315+ i -= TARGET_ARM ? 2 : 1;
316+ continue;
317+ }
318+
319+ /* Next, see if we can do a better job with a thumb2 replicated
320+ constant.
321+
322+ We do it this way around to catch the cases like 0x01F001E0 where
323+ two 8-bit immediates would work, but a replicated constant would
324+ make it worse.
325+
326+ TODO: 16-bit constants that don't clear all the bits, but still win.
327+ TODO: Arithmetic splitting for set/add/sub, rather than bitwise. */
328+ if (TARGET_THUMB2)
329+ {
330+ b1 = (remainder & 0xff000000) >> 24;
331+ b2 = (remainder & 0x00ff0000) >> 16;
332+ b3 = (remainder & 0x0000ff00) >> 8;
333+ b4 = remainder & 0xff;
334+
335+ if (loc > 24)
336+ {
337+ /* The 8-bit immediate already found clears b1 (and maybe b2),
338+ but must leave b3 and b4 alone. */
339+
340+ /* First try to find a 32-bit replicated constant that clears
341+ almost everything. We can assume that we can't do it in one,
342+ or else we wouldn't be here. */
343+ unsigned int tmp = b1 & b2 & b3 & b4;
344+ unsigned int tmp2 = tmp + (tmp << 8) + (tmp << 16)
345+ + (tmp << 24);
346+ unsigned int matching_bytes = (tmp == b1) + (tmp == b2)
347+ + (tmp == b3) + (tmp == b4);
348+ if (tmp
349+ && (matching_bytes >= 3
350+ || (matching_bytes == 2
351+ && const_ok_for_op (remainder & ~tmp2, code))))
352+ {
353+ /* At least 3 of the bytes match, and the fourth has at
354+ least as many bits set, or two of the bytes match
355+ and it will only require one more insn to finish. */
356+ result = tmp2;
357+ i = tmp != b1 ? 32
358+ : tmp != b2 ? 24
359+ : tmp != b3 ? 16
360+ : 8;
361+ }
362+
363+ /* Second, try to find a 16-bit replicated constant that can
364+ leave three of the bytes clear. If b2 or b4 is already
365+ zero, then we can. If the 8-bit from above would not
366+ clear b2 anyway, then we still win. */
367+ else if (b1 == b3 && (!b2 || !b4
368+ || (remainder & 0x00ff0000 & ~result)))
369+ {
370+ result = remainder & 0xff00ff00;
371+ i = 24;
372+ }
373+ }
374+ else if (loc > 16)
375+ {
376+ /* The 8-bit immediate already found clears b2 (and maybe b3)
377+ and we don't get here unless b1 is alredy clear, but it will
378+ leave b4 unchanged. */
379+
380+ /* If we can clear b2 and b4 at once, then we win, since the
381+ 8-bits couldn't possibly reach that far. */
382+ if (b2 == b4)
383+ {
384+ result = remainder & 0x00ff00ff;
385+ i = 16;
386+ }
387+ }
388+ }
389+
390+ return_sequence->i[insns++] = result;
391+ remainder &= ~result;
392+
393+ if (code == SET || code == MINUS)
394+ code = PLUS;
395+ }
396+ while (remainder);
397+
398+ return insns;
399 }
400
401 /* Emit an instruction with the indicated PATTERN. If COND is
402@@ -2760,7 +2905,6 @@
403
404 /* As above, but extra parameter GENERATE which, if clear, suppresses
405 RTL generation. */
406-/* ??? This needs more work for thumb2. */
407
408 static int
409 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
410@@ -2772,15 +2916,15 @@
411 int final_invert = 0;
412 int can_negate_initial = 0;
413 int i;
414- int num_bits_set = 0;
415 int set_sign_bit_copies = 0;
416 int clear_sign_bit_copies = 0;
417 int clear_zero_bit_copies = 0;
418 int set_zero_bit_copies = 0;
419- int insns = 0;
420+ int insns = 0, neg_insns, inv_insns;
421 unsigned HOST_WIDE_INT temp1, temp2;
422 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
423- int step_size = TARGET_ARM ? 2 : 1;
424+ struct four_ints *immediates;
425+ struct four_ints pos_immediates, neg_immediates, inv_immediates;
426
427 /* Find out which operations are safe for a given CODE. Also do a quick
428 check for degenerate cases; these can occur when DImode operations
429@@ -2789,7 +2933,6 @@
430 {
431 case SET:
432 can_invert = 1;
433- can_negate = 1;
434 break;
435
436 case PLUS:
437@@ -2817,9 +2960,6 @@
438 gen_rtx_SET (VOIDmode, target, source));
439 return 1;
440 }
441-
442- if (TARGET_THUMB2)
443- can_invert = 1;
444 break;
445
446 case AND:
447@@ -2861,6 +3001,7 @@
448 gen_rtx_NOT (mode, source)));
449 return 1;
450 }
451+ final_invert = 1;
452 break;
453
454 case MINUS:
455@@ -2883,7 +3024,6 @@
456 source)));
457 return 1;
458 }
459- can_negate = 1;
460
461 break;
462
463@@ -2892,9 +3032,7 @@
464 }
465
466 /* If we can do it in one insn get out quickly. */
467- if (const_ok_for_arm (val)
468- || (can_negate_initial && const_ok_for_arm (-val))
469- || (can_invert && const_ok_for_arm (~val)))
470+ if (const_ok_for_op (val, code))
471 {
472 if (generate)
473 emit_constant_insn (cond,
474@@ -2947,15 +3085,6 @@
475 switch (code)
476 {
477 case SET:
478- /* See if we can use movw. */
479- if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
480- {
481- if (generate)
482- emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
483- GEN_INT (val)));
484- return 1;
485- }
486-
487 /* See if we can do this by sign_extending a constant that is known
488 to be negative. This is a good, way of doing it, since the shift
489 may well merge into a subsequent insn. */
490@@ -3306,121 +3435,97 @@
491 break;
492 }
493
494- for (i = 0; i < 32; i++)
495- if (remainder & (1 << i))
496- num_bits_set++;
497-
498- if ((code == AND)
499- || (code != IOR && can_invert && num_bits_set > 16))
500- remainder ^= 0xffffffff;
501- else if (code == PLUS && num_bits_set > 16)
502- remainder = (-remainder) & 0xffffffff;
503-
504- /* For XOR, if more than half the bits are set and there's a sequence
505- of more than 8 consecutive ones in the pattern then we can XOR by the
506- inverted constant and then invert the final result; this may save an
507- instruction and might also lead to the final mvn being merged with
508- some other operation. */
509- else if (code == XOR && num_bits_set > 16
510- && (count_insns_for_constant (remainder ^ 0xffffffff,
511- find_best_start
512- (remainder ^ 0xffffffff))
513- < count_insns_for_constant (remainder,
514- find_best_start (remainder))))
515- {
516- remainder ^= 0xffffffff;
517- final_invert = 1;
518+ /* Calculate what the instruction sequences would be if we generated it
519+ normally, negated, or inverted. */
520+ if (code == AND)
521+ /* AND cannot be split into multiple insns, so invert and use BIC. */
522+ insns = 99;
523+ else
524+ insns = optimal_immediate_sequence (code, remainder, &pos_immediates);
525+
526+ if (can_negate)
527+ neg_insns = optimal_immediate_sequence (code, (-remainder) & 0xffffffff,
528+ &neg_immediates);
529+ else
530+ neg_insns = 99;
531+
532+ if (can_invert || final_invert)
533+ inv_insns = optimal_immediate_sequence (code, remainder ^ 0xffffffff,
534+ &inv_immediates);
535+ else
536+ inv_insns = 99;
537+
538+ immediates = &pos_immediates;
539+
540+ /* Is the negated immediate sequence more efficient? */
541+ if (neg_insns < insns && neg_insns <= inv_insns)
542+ {
543+ insns = neg_insns;
544+ immediates = &neg_immediates;
545+ }
546+ else
547+ can_negate = 0;
548+
549+ /* Is the inverted immediate sequence more efficient?
550+ We must allow for an extra NOT instruction for XOR operations, although
551+ there is some chance that the final 'mvn' will get optimized later. */
552+ if ((inv_insns + 1) < insns || (!final_invert && inv_insns < insns))
553+ {
554+ insns = inv_insns;
555+ immediates = &inv_immediates;
556 }
557 else
558 {
559 can_invert = 0;
560- can_negate = 0;
561+ final_invert = 0;
562 }
563
564- /* Now try and find a way of doing the job in either two or three
565- instructions.
566- We start by looking for the largest block of zeros that are aligned on
567- a 2-bit boundary, we then fill up the temps, wrapping around to the
568- top of the word when we drop off the bottom.
569- In the worst case this code should produce no more than four insns.
570- Thumb-2 constants are shifted, not rotated, so the MSB is always the
571- best place to start. */
572-
573- /* ??? Use thumb2 replicated constants when the high and low halfwords are
574- the same. */
575- {
576- /* Now start emitting the insns. */
577- i = find_best_start (remainder);
578- do
579- {
580- int end;
581-
582- if (i <= 0)
583- i += 32;
584- if (remainder & (3 << (i - 2)))
585- {
586- end = i - 8;
587- if (end < 0)
588- end += 32;
589- temp1 = remainder & ((0x0ff << end)
590- | ((i < end) ? (0xff >> (32 - end)) : 0));
591- remainder &= ~temp1;
592-
593- if (generate)
594- {
595- rtx new_src, temp1_rtx;
596-
597- if (code == SET || code == MINUS)
598- {
599- new_src = (subtargets ? gen_reg_rtx (mode) : target);
600- if (can_invert && code != MINUS)
601- temp1 = ~temp1;
602- }
603- else
604- {
605- if ((final_invert || remainder) && subtargets)
606- new_src = gen_reg_rtx (mode);
607- else
608- new_src = target;
609- if (can_invert)
610- temp1 = ~temp1;
611- else if (can_negate)
612- temp1 = -temp1;
613- }
614-
615- temp1 = trunc_int_for_mode (temp1, mode);
616- temp1_rtx = GEN_INT (temp1);
617-
618- if (code == SET)
619- ;
620- else if (code == MINUS)
621- temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
622- else
623- temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
624-
625- emit_constant_insn (cond,
626- gen_rtx_SET (VOIDmode, new_src,
627- temp1_rtx));
628- source = new_src;
629- }
630-
631- if (code == SET)
632- {
633- can_invert = 0;
634- code = PLUS;
635- }
636- else if (code == MINUS)
637+ /* Now output the chosen sequence as instructions. */
638+ if (generate)
639+ {
640+ for (i = 0; i < insns; i++)
641+ {
642+ rtx new_src, temp1_rtx;
643+
644+ temp1 = immediates->i[i];
645+
646+ if (code == SET || code == MINUS)
647+ new_src = (subtargets ? gen_reg_rtx (mode) : target);
648+ else if ((final_invert || i < (insns - 1)) && subtargets)
649+ new_src = gen_reg_rtx (mode);
650+ else
651+ new_src = target;
652+
653+ if (can_invert)
654+ temp1 = ~temp1;
655+ else if (can_negate)
656+ temp1 = -temp1;
657+
658+ temp1 = trunc_int_for_mode (temp1, mode);
659+ temp1_rtx = GEN_INT (temp1);
660+
661+ if (code == SET)
662+ ;
663+ else if (code == MINUS)
664+ temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
665+ else
666+ temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
667+
668+ emit_constant_insn (cond,
669+ gen_rtx_SET (VOIDmode, new_src,
670+ temp1_rtx));
671+ source = new_src;
672+
673+ if (code == SET)
674+ {
675+ can_negate = can_invert;
676+ can_invert = 0;
677 code = PLUS;
678-
679- insns++;
680- i -= 8 - step_size;
681- }
682- /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
683- shifts. */
684- i -= step_size;
685- }
686- while (remainder);
687- }
688+ }
689+ else if (code == MINUS)
690+ code = PLUS;
691+ }
692+ }
693
694 if (final_invert)
695 {
696
697=== modified file 'gcc/config/arm/arm.md'
698--- old/gcc/config/arm/arm.md 2011-08-25 11:42:09 +0000
699+++ new/gcc/config/arm/arm.md 2011-08-25 13:26:58 +0000
700@@ -701,21 +701,24 @@
701 ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
702 ;; put the duplicated register first, and not try the commutative version.
703 (define_insn_and_split "*arm_addsi3"
704- [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k,r")
705- (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk")
706- (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))]
707+ [(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k, r, k,r, k, r")
708+ (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, rk,k,rk,k, rk")
709+ (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, L,PJ,PJ,?n")))]
710 "TARGET_32BIT"
711 "@
712 add%?\\t%0, %1, %2
713 add%?\\t%0, %1, %2
714 add%?\\t%0, %2, %1
715- sub%?\\t%0, %1, #%n2
716- sub%?\\t%0, %1, #%n2
717+ addw%?\\t%0, %1, %2
718+ addw%?\\t%0, %1, %2
719+ sub%?\\t%0, %1, #%n2
720+ sub%?\\t%0, %1, #%n2
721+ subw%?\\t%0, %1, #%n2
722+ subw%?\\t%0, %1, #%n2
723 #"
724 "TARGET_32BIT
725 && GET_CODE (operands[2]) == CONST_INT
726- && !(const_ok_for_arm (INTVAL (operands[2]))
727- || const_ok_for_arm (-INTVAL (operands[2])))
728+ && !const_ok_for_op (INTVAL (operands[2]), PLUS)
729 && (reload_completed || !arm_eliminable_register (operands[1]))"
730 [(clobber (const_int 0))]
731 "
732@@ -724,8 +727,9 @@
733 operands[1], 0);
734 DONE;
735 "
736- [(set_attr "length" "4,4,4,4,4,16")
737- (set_attr "predicable" "yes")]
738+ [(set_attr "length" "4,4,4,4,4,4,4,4,4,16")
739+ (set_attr "predicable" "yes")
740+ (set_attr "arch" "*,*,*,t2,t2,*,*,t2,t2,*")]
741 )
742
743 (define_insn_and_split "*thumb1_addsi3"
744
745=== modified file 'gcc/config/arm/constraints.md'
746--- old/gcc/config/arm/constraints.md 2011-01-03 20:52:22 +0000
747+++ new/gcc/config/arm/constraints.md 2011-08-25 13:26:58 +0000
748@@ -31,7 +31,7 @@
749 ;; The following multi-letter normal constraints have been used:
750 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
751 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
752-;; in Thumb-2 state: Ps, Pt, Pu, Pv, Pw, Px
753+;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
754
755 ;; The following memory constraints have been used:
756 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
757@@ -74,6 +74,18 @@
758 (and (match_code "const_int")
759 (match_test "(ival & 0xffff0000) == 0")))))
760
761+(define_constraint "Pj"
762+ "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
763+ (and (match_code "const_int")
764+ (and (match_test "TARGET_THUMB2")
765+ (match_test "(ival & 0xfffff000) == 0"))))
766+
767+(define_constraint "PJ"
768+ "@internal A constant that satisfies the Pj constrant if negated."
769+ (and (match_code "const_int")
770+ (and (match_test "TARGET_THUMB2")
771+ (match_test "((-ival) & 0xfffff000) == 0"))))
772+
773 (define_register_constraint "k" "STACK_REG"
774 "@internal The stack register.")
775
776
777=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c'
778--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 1970-01-01 00:00:00 +0000
779+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c 2011-08-25 13:31:00 +0000
780@@ -0,0 +1,27 @@
781+/* Ensure simple replicated constant immediates work. */
782+/* { dg-options "-mthumb -O2" } */
783+/* { dg-require-effective-target arm_thumb2_ok } */
784+
785+int
786+foo1 (int a)
787+{
788+ return a + 0xfefefefe;
789+}
790+
791+/* { dg-final { scan-assembler "add.*#-16843010" } } */
792+
793+int
794+foo2 (int a)
795+{
796+ return a - 0xab00ab00;
797+}
798+
799+/* { dg-final { scan-assembler "sub.*#-1426019584" } } */
800+
801+int
802+foo3 (int a)
803+{
804+ return a & 0x00cd00cd;
805+}
806+
807+/* { dg-final { scan-assembler "and.*#13435085" } } */
808
809=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c'
810--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 1970-01-01 00:00:00 +0000
811+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c 2011-08-25 13:31:00 +0000
812@@ -0,0 +1,75 @@
813+/* Ensure split constants can use replicated patterns. */
814+/* { dg-options "-mthumb -O2" } */
815+/* { dg-require-effective-target arm_thumb2_ok } */
816+
817+int
818+foo1 (int a)
819+{
820+ return a + 0xfe00fe01;
821+}
822+
823+/* { dg-final { scan-assembler "add.*#-33489408" } } */
824+/* { dg-final { scan-assembler "add.*#1" } } */
825+
826+int
827+foo2 (int a)
828+{
829+ return a + 0xdd01dd00;
830+}
831+
832+/* { dg-final { scan-assembler "add.*#-587145984" } } */
833+/* { dg-final { scan-assembler "add.*#65536" } } */
834+
835+int
836+foo3 (int a)
837+{
838+ return a + 0x00443344;
839+}
840+
841+/* { dg-final { scan-assembler "add.*#4456516" } } */
842+/* { dg-final { scan-assembler "add.*#13056" } } */
843+
844+int
845+foo4 (int a)
846+{
847+ return a + 0x77330033;
848+}
849+
850+/* { dg-final { scan-assembler "add.*#1996488704" } } */
851+/* { dg-final { scan-assembler "add.*#3342387" } } */
852+
853+int
854+foo5 (int a)
855+{
856+ return a + 0x11221122;
857+}
858+
859+/* { dg-final { scan-assembler "add.*#285217024" } } */
860+/* { dg-final { scan-assembler "add.*#2228258" } } */
861+
862+int
863+foo6 (int a)
864+{
865+ return a + 0x66666677;
866+}
867+
868+/* { dg-final { scan-assembler "add.*#1717986918" } } */
869+/* { dg-final { scan-assembler "add.*#17" } } */
870+
871+int
872+foo7 (int a)
873+{
874+ return a + 0x99888888;
875+}
876+
877+/* { dg-final { scan-assembler "add.*#-2004318072" } } */
878+/* { dg-final { scan-assembler "add.*#285212672" } } */
879+
880+int
881+foo8 (int a)
882+{
883+ return a + 0xdddddfff;
884+}
885+
886+/* { dg-final { scan-assembler "add.*#-572662307" } } */
887+/* { dg-final { scan-assembler "addw.*#546" } } */
888
889=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c'
890--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 1970-01-01 00:00:00 +0000
891+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c 2011-08-25 13:31:00 +0000
892@@ -0,0 +1,28 @@
893+/* Ensure negated/inverted replicated constant immediates work. */
894+/* { dg-options "-mthumb -O2" } */
895+/* { dg-require-effective-target arm_thumb2_ok } */
896+
897+int
898+foo1 (int a)
899+{
900+ return a | 0xffffff00;
901+}
902+
903+/* { dg-final { scan-assembler "orn.*#255" } } */
904+
905+int
906+foo2 (int a)
907+{
908+ return a & 0xffeeffee;
909+}
910+
911+/* { dg-final { scan-assembler "bic.*#1114129" } } */
912+
913+int
914+foo3 (int a)
915+{
916+ return a & 0xaaaaaa00;
917+}
918+
919+/* { dg-final { scan-assembler "and.*#-1431655766" } } */
920+/* { dg-final { scan-assembler "bic.*#170" } } */
921
922=== added file 'gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c'
923--- old/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 1970-01-01 00:00:00 +0000
924+++ new/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c 2011-08-25 13:31:00 +0000
925@@ -0,0 +1,22 @@
926+/* Ensure replicated constants don't make things worse. */
927+/* { dg-options "-mthumb -O2" } */
928+/* { dg-require-effective-target arm_thumb2_ok } */
929+
930+int
931+foo1 (int a)
932+{
933+ /* It might be tempting to use 0x01000100, but it wouldn't help. */
934+ return a + 0x01f001e0;
935+}
936+
937+/* { dg-final { scan-assembler "add.*#32505856" } } */
938+/* { dg-final { scan-assembler "add.*#480" } } */
939+
940+int
941+foo2 (int a)
942+{
943+ return a + 0x0f100e10;
944+}
945+
946+/* { dg-final { scan-assembler "add.*#252706816" } } */
947+/* { dg-final { scan-assembler "add.*#3600" } } */
948
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
new file mode 100644
index 0000000000..5b36959b6b
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106803.patch
@@ -0,0 +1,201 @@
12011-09-12 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 PR target/49030
5 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
6 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
7 reusing the old code from get_arm_condition_code. Return ARM_NV
8 for invalid comparison codes.
9 (get_arm_condition_code): Redefine in terms of
10 maybe_get_arm_condition_code.
11 * config/arm/predicates.md (arm_comparison_operator): Use
12 maybe_get_arm_condition_code.
13
14 gcc/testsuite/
15 PR target/49030
16 * gcc.dg/torture/pr49030.c: New test.
17
18=== modified file 'gcc/config/arm/arm-protos.h'
19--- old/gcc/config/arm/arm-protos.h 2011-08-25 13:26:58 +0000
20+++ new/gcc/config/arm/arm-protos.h 2011-09-12 11:03:11 +0000
21@@ -179,6 +179,7 @@
22 #endif
23 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
24 #ifdef RTX_CODE
25+extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
26 extern void thumb1_final_prescan_insn (rtx);
27 extern void thumb2_final_prescan_insn (rtx);
28 extern const char *thumb_load_double_from_address (rtx *);
29
30=== modified file 'gcc/config/arm/arm.c'
31--- old/gcc/config/arm/arm.c 2011-09-06 12:57:56 +0000
32+++ new/gcc/config/arm/arm.c 2011-09-12 11:03:11 +0000
33@@ -17494,10 +17494,10 @@
34 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
35
36 /* Returns the index of the ARM condition code string in
37- `arm_condition_codes'. COMPARISON should be an rtx like
38- `(eq (...) (...))'. */
39-static enum arm_cond_code
40-get_arm_condition_code (rtx comparison)
41+ `arm_condition_codes', or ARM_NV if the comparison is invalid.
42+ COMPARISON should be an rtx like `(eq (...) (...))'. */
43+enum arm_cond_code
44+maybe_get_arm_condition_code (rtx comparison)
45 {
46 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
47 enum arm_cond_code code;
48@@ -17521,11 +17521,11 @@
49 case CC_DLTUmode: code = ARM_CC;
50
51 dominance:
52- gcc_assert (comp_code == EQ || comp_code == NE);
53-
54 if (comp_code == EQ)
55 return ARM_INVERSE_CONDITION_CODE (code);
56- return code;
57+ if (comp_code == NE)
58+ return code;
59+ return ARM_NV;
60
61 case CC_NOOVmode:
62 switch (comp_code)
63@@ -17534,7 +17534,7 @@
64 case EQ: return ARM_EQ;
65 case GE: return ARM_PL;
66 case LT: return ARM_MI;
67- default: gcc_unreachable ();
68+ default: return ARM_NV;
69 }
70
71 case CC_Zmode:
72@@ -17542,7 +17542,7 @@
73 {
74 case NE: return ARM_NE;
75 case EQ: return ARM_EQ;
76- default: gcc_unreachable ();
77+ default: return ARM_NV;
78 }
79
80 case CC_Nmode:
81@@ -17550,7 +17550,7 @@
82 {
83 case NE: return ARM_MI;
84 case EQ: return ARM_PL;
85- default: gcc_unreachable ();
86+ default: return ARM_NV;
87 }
88
89 case CCFPEmode:
90@@ -17575,7 +17575,7 @@
91 /* UNEQ and LTGT do not have a representation. */
92 case UNEQ: /* Fall through. */
93 case LTGT: /* Fall through. */
94- default: gcc_unreachable ();
95+ default: return ARM_NV;
96 }
97
98 case CC_SWPmode:
99@@ -17591,7 +17591,7 @@
100 case GTU: return ARM_CC;
101 case LEU: return ARM_CS;
102 case LTU: return ARM_HI;
103- default: gcc_unreachable ();
104+ default: return ARM_NV;
105 }
106
107 case CC_Cmode:
108@@ -17599,7 +17599,7 @@
109 {
110 case LTU: return ARM_CS;
111 case GEU: return ARM_CC;
112- default: gcc_unreachable ();
113+ default: return ARM_NV;
114 }
115
116 case CC_CZmode:
117@@ -17611,7 +17611,7 @@
118 case GTU: return ARM_HI;
119 case LEU: return ARM_LS;
120 case LTU: return ARM_CC;
121- default: gcc_unreachable ();
122+ default: return ARM_NV;
123 }
124
125 case CC_NCVmode:
126@@ -17621,7 +17621,7 @@
127 case LT: return ARM_LT;
128 case GEU: return ARM_CS;
129 case LTU: return ARM_CC;
130- default: gcc_unreachable ();
131+ default: return ARM_NV;
132 }
133
134 case CCmode:
135@@ -17637,13 +17637,22 @@
136 case GTU: return ARM_HI;
137 case LEU: return ARM_LS;
138 case LTU: return ARM_CC;
139- default: gcc_unreachable ();
140+ default: return ARM_NV;
141 }
142
143 default: gcc_unreachable ();
144 }
145 }
146
147+/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
148+static enum arm_cond_code
149+get_arm_condition_code (rtx comparison)
150+{
151+ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
152+ gcc_assert (code != ARM_NV);
153+ return code;
154+}
155+
156 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
157 instructions. */
158 void
159
160=== modified file 'gcc/config/arm/predicates.md'
161--- old/gcc/config/arm/predicates.md 2011-08-13 08:40:36 +0000
162+++ new/gcc/config/arm/predicates.md 2011-09-05 09:40:19 +0000
163@@ -242,10 +242,9 @@
164 ;; True for integer comparisons and, if FP is active, for comparisons
165 ;; other than LTGT or UNEQ.
166 (define_special_predicate "arm_comparison_operator"
167- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
168- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
169- && (TARGET_FPA || TARGET_VFP)")
170- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
171+ (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
172+ unordered,ordered,unlt,unle,unge,ungt")
173+ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
174
175 (define_special_predicate "lt_ge_comparison_operator"
176 (match_code "lt,ge"))
177
178=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
179--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
180+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-09-05 09:40:19 +0000
181@@ -0,0 +1,19 @@
182+void
183+sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
184+ unsigned long dst_skip)
185+{
186+ long long y;
187+ while (nsamples--)
188+ {
189+ y = (long long) (*src * 8388608.0f) << 8;
190+ if (y > 2147483647) {
191+ *(int *) dst = 2147483647;
192+ } else if (y < -2147483647 - 1) {
193+ *(int *) dst = -2147483647 - 1;
194+ } else {
195+ *(int *) dst = (int) y;
196+ }
197+ dst += dst_skip;
198+ src++;
199+ }
200+}
201
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
new file mode 100644
index 0000000000..09d0767914
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106804.patch
@@ -0,0 +1,38 @@
12011-09-01 Andrew Stubbs <ams@codesourcery.com>
2
3 gcc/
4 * config/arm/predicates.md (shift_amount_operand): Ensure shift
5 amount is positive.
6
7 gcc/testsuite/
8 * gcc.dg/pr50193-1.c: New file.
9
10=== modified file 'gcc/config/arm/predicates.md'
11--- old/gcc/config/arm/predicates.md 2011-09-05 09:40:19 +0000
12+++ new/gcc/config/arm/predicates.md 2011-09-12 11:24:34 +0000
13@@ -132,7 +132,8 @@
14 (define_predicate "shift_amount_operand"
15 (ior (and (match_test "TARGET_ARM")
16 (match_operand 0 "s_register_operand"))
17- (match_operand 0 "const_int_operand")))
18+ (and (match_operand 0 "const_int_operand")
19+ (match_test "INTVAL (op) > 0"))))
20
21 (define_predicate "arm_add_operand"
22 (ior (match_operand 0 "arm_rhs_operand")
23
24=== added file 'gcc/testsuite/gcc.dg/pr50193-1.c'
25--- old/gcc/testsuite/gcc.dg/pr50193-1.c 1970-01-01 00:00:00 +0000
26+++ new/gcc/testsuite/gcc.dg/pr50193-1.c 2011-09-01 12:22:14 +0000
27@@ -0,0 +1,10 @@
28+/* PR 50193: ARM: ICE on a | (b << negative-constant) */
29+/* Ensure that the compiler doesn't ICE. */
30+
31+/* { dg-options "-O2" } */
32+
33+int
34+foo(int a, int b)
35+{
36+ return a | (b << -3); /* { dg-warning "left shift count is negative" } */
37+}
38
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
new file mode 100644
index 0000000000..5dec32fa71
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106805.patch
@@ -0,0 +1,47 @@
12011-09-12 Andrew Stubbs <ams@codesourcery.com>
2
3 Backport from FSF mainline:
4
5 2011-09-08 Andrew Stubbs <ams@codesourcery.com>
6
7 PR tree-optimization/50318
8
9 gcc/
10 * tree-ssa-math-opts.c (convert_plusminus_to_widen): Correct
11 typo in use of mult_rhs1 and mult_rhs2.
12
13 gcc/testsuite/
14 * gcc.target/arm/pr50318-1.c: New file.
15
16=== added file 'gcc/testsuite/gcc.target/arm/pr50318-1.c'
17--- old/gcc/testsuite/gcc.target/arm/pr50318-1.c 1970-01-01 00:00:00 +0000
18+++ new/gcc/testsuite/gcc.target/arm/pr50318-1.c 2011-09-08 20:11:43 +0000
19@@ -0,0 +1,11 @@
20+/* { dg-do compile } */
21+/* { dg-options "-O2" } */
22+/* { dg-require-effective-target arm_dsp } */
23+
24+long long test (unsigned int sec, unsigned long long nsecs)
25+{
26+ return (long long)(long)sec * 1000000000L + (long long)(unsigned
27+ long)nsecs;
28+}
29+
30+/* { dg-final { scan-assembler "umlal" } } */
31
32=== modified file 'gcc/tree-ssa-math-opts.c'
33--- old/gcc/tree-ssa-math-opts.c 2011-08-09 10:26:48 +0000
34+++ new/gcc/tree-ssa-math-opts.c 2011-09-08 20:11:43 +0000
35@@ -1699,9 +1699,9 @@
36
37 /* Handle constants. */
38 if (TREE_CODE (mult_rhs1) == INTEGER_CST)
39- rhs1 = fold_convert (type1, mult_rhs1);
40+ mult_rhs1 = fold_convert (type1, mult_rhs1);
41 if (TREE_CODE (mult_rhs2) == INTEGER_CST)
42- rhs2 = fold_convert (type2, mult_rhs2);
43+ mult_rhs2 = fold_convert (type2, mult_rhs2);
44
45 gimple_assign_set_rhs_with_ops_1 (gsi, wmult_code, mult_rhs1, mult_rhs2,
46 add_rhs);
47
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
new file mode 100644
index 0000000000..2b96854c95
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106806.patch
@@ -0,0 +1,92 @@
12011-09-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 gcc/testsuite/
4 * gcc.target/arm/pr50099.c: Fix testcase from previous commit.
5
62011-09-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
7
8 LP:838994
9 gcc/
10 Backport from mainline.
11
12 2011-09-06 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
13
14 PR target/50099
15 * config/arm/iterators.md (qhs_zextenddi_cstr): New.
16 (qhs_zextenddi_op): New.
17 * config/arm/arm.md ("zero_extend<mode>di2"): Use them.
18 * config/arm/predicates.md ("arm_extendqisi_mem_op"):
19 Distinguish between ARM and Thumb2 states.
20
21 gcc/testsuite/
22 * gcc.target/arm/pr50099.c: New test.
23
24=== modified file 'gcc/config/arm/arm.md'
25--- old/gcc/config/arm/arm.md 2011-08-25 13:26:58 +0000
26+++ new/gcc/config/arm/arm.md 2011-09-12 12:32:29 +0000
27@@ -4136,8 +4136,8 @@
28
29 (define_insn "zero_extend<mode>di2"
30 [(set (match_operand:DI 0 "s_register_operand" "=r")
31- (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
32- "<qhs_extenddi_cstr>")))]
33+ (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
34+ "<qhs_zextenddi_cstr>")))]
35 "TARGET_32BIT <qhs_zextenddi_cond>"
36 "#"
37 [(set_attr "length" "8")
38
39=== modified file 'gcc/config/arm/iterators.md'
40--- old/gcc/config/arm/iterators.md 2011-05-03 15:14:56 +0000
41+++ new/gcc/config/arm/iterators.md 2011-09-06 14:29:24 +0000
42@@ -379,10 +379,14 @@
43 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
44 (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
45 (QI "&& arm_arch6")])
46+(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
47+ (HI "nonimmediate_operand")
48+ (QI "nonimmediate_operand")])
49 (define_mode_attr qhs_extenddi_op [(SI "s_register_operand")
50 (HI "nonimmediate_operand")
51- (QI "nonimmediate_operand")])
52-(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
53+ (QI "arm_reg_or_extendqisi_mem_op")])
54+(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")])
55+(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")])
56
57 ;;----------------------------------------------------------------------------
58 ;; Code attributes
59
60=== modified file 'gcc/config/arm/predicates.md'
61--- old/gcc/config/arm/predicates.md 2011-09-12 11:24:34 +0000
62+++ new/gcc/config/arm/predicates.md 2011-09-12 12:32:29 +0000
63@@ -289,8 +289,11 @@
64
65 (define_special_predicate "arm_extendqisi_mem_op"
66 (and (match_operand 0 "memory_operand")
67- (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0),
68- SIGN_EXTEND, 0)")))
69+ (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
70+ XEXP (op, 0),
71+ SIGN_EXTEND,
72+ 0)
73+ : memory_address_p (QImode, XEXP (op, 0))")))
74
75 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
76 (ior (match_operand 0 "arm_extendqisi_mem_op")
77
78=== added file 'gcc/testsuite/gcc.target/arm/pr50099.c'
79--- old/gcc/testsuite/gcc.target/arm/pr50099.c 1970-01-01 00:00:00 +0000
80+++ new/gcc/testsuite/gcc.target/arm/pr50099.c 2011-09-09 16:42:45 +0000
81@@ -0,0 +1,10 @@
82+/* { dg-do compile } */
83+/* { dg-options "-O2" } */
84+
85+long long foo (signed char * arg)
86+{
87+ long long temp_1;
88+
89+ temp_1 = arg[256];
90+ return temp_1;
91+}
92
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
new file mode 100644
index 0000000000..9474030f57
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106807.patch
@@ -0,0 +1,767 @@
12011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2
3 Backport from FSF mainline:
4 2011-04-06 Wei Guozhi <carrot@google.com>
5
6 PR target/47855
7 gcc/
8 * config/arm/arm.md (arm_cmpsi_insn): Compute attr "length".
9 (arm_cond_branch): Likewise.
10 (arm_cond_branch_reversed): Likewise.
11 (arm_jump): Likewise.
12 (push_multi): Likewise.
13 * config/arm/constraints.md (Py): New constraint.
14
15 2011-04-08 Wei Guozhi <carrot@google.com>
16
17 PR target/47855
18 * config/arm/arm-protos.h (arm_attr_length_push_multi): New prototype.
19 * config/arm/arm.c (arm_attr_length_push_multi): New function.
20 * config/arm/arm.md (*push_multi): Change the length computation to
21 call a C function.
22
232011-08-26 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
24
25 Backport from FSF mainline:
26
27 2011-08-18 Jiangning Liu <jiangning.liu@arm.com>
28
29 gcc/
30 * config/arm/arm.md (*ior_scc_scc): Enable for Thumb2 as well.
31 (*ior_scc_scc_cmp): Likewise
32 (*and_scc_scc): Likewise.
33 (*and_scc_scc_cmp): Likewise.
34 (*and_scc_scc_nodom): Likewise.
35 (*cmp_ite0, *cmp_ite1, *cmp_and, *cmp_ior): Handle Thumb2.
36
37 gcc/testsuite
38 * gcc.target/arm/thumb2-cond-cmp-1.c: New. Make sure conditional
39 compare can be generated.
40 * gcc.target/arm/thumb2-cond-cmp-2.c: Likewise.
41 * gcc.target/arm/thumb2-cond-cmp-3.c: Likewise.
42 * gcc.target/arm/thumb2-cond-cmp-4.c: Likewise.
43
44=== modified file 'gcc/config/arm/arm-protos.h'
45--- old/gcc/config/arm/arm-protos.h 2011-09-12 11:03:11 +0000
46+++ new/gcc/config/arm/arm-protos.h 2011-09-12 14:14:00 +0000
47@@ -156,6 +156,7 @@
48 extern const char *arm_output_memory_barrier (rtx *);
49 extern const char *arm_output_sync_insn (rtx, rtx *);
50 extern unsigned int arm_sync_loop_insns (rtx , rtx *);
51+extern int arm_attr_length_push_multi(rtx, rtx);
52
53 #if defined TREE_CODE
54 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
55
56=== modified file 'gcc/config/arm/arm.c'
57--- old/gcc/config/arm/arm.c 2011-09-12 11:03:11 +0000
58+++ new/gcc/config/arm/arm.c 2011-09-12 14:14:00 +0000
59@@ -24391,4 +24391,30 @@
60 return NO_REGS;
61 }
62
63+/* Compute the atrribute "length" of insn "*push_multi".
64+ So this function MUST be kept in sync with that insn pattern. */
65+int
66+arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
67+{
68+ int i, regno, hi_reg;
69+ int num_saves = XVECLEN (parallel_op, 0);
70+
71+ /* ARM mode. */
72+ if (TARGET_ARM)
73+ return 4;
74+
75+ /* Thumb2 mode. */
76+ regno = REGNO (first_op);
77+ hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
78+ for (i = 1; i < num_saves && !hi_reg; i++)
79+ {
80+ regno = REGNO (XEXP (XVECEXP (parallel_op, 0, i), 0));
81+ hi_reg |= (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
82+ }
83+
84+ if (!hi_reg)
85+ return 2;
86+ return 4;
87+}
88+
89 #include "gt-arm.h"
90
91=== modified file 'gcc/config/arm/arm.md'
92--- old/gcc/config/arm/arm.md 2011-09-12 12:32:29 +0000
93+++ new/gcc/config/arm/arm.md 2011-09-12 14:14:00 +0000
94@@ -48,6 +48,15 @@
95 (DOM_CC_X_OR_Y 2)
96 ]
97 )
98+;; conditional compare combination
99+(define_constants
100+ [(CMP_CMP 0)
101+ (CMN_CMP 1)
102+ (CMP_CMN 2)
103+ (CMN_CMN 3)
104+ (NUM_OF_COND_CMP 4)
105+ ]
106+)
107
108 ;; UNSPEC Usage:
109 ;; Note: sin and cos are no-longer used.
110@@ -7198,13 +7207,17 @@
111
112 (define_insn "*arm_cmpsi_insn"
113 [(set (reg:CC CC_REGNUM)
114- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
115- (match_operand:SI 1 "arm_add_operand" "rI,L")))]
116+ (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r")
117+ (match_operand:SI 1 "arm_add_operand" "Py,r,rI,L")))]
118 "TARGET_32BIT"
119 "@
120 cmp%?\\t%0, %1
121+ cmp%?\\t%0, %1
122+ cmp%?\\t%0, %1
123 cmn%?\\t%0, #%n1"
124- [(set_attr "conds" "set")]
125+ [(set_attr "conds" "set")
126+ (set_attr "arch" "t2,t2,any,any")
127+ (set_attr "length" "2,2,4,4")]
128 )
129
130 (define_insn "*cmpsi_shiftsi"
131@@ -7375,7 +7388,14 @@
132 return \"b%d1\\t%l0\";
133 "
134 [(set_attr "conds" "use")
135- (set_attr "type" "branch")]
136+ (set_attr "type" "branch")
137+ (set (attr "length")
138+ (if_then_else
139+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
140+ (and (ge (minus (match_dup 0) (pc)) (const_int -250))
141+ (le (minus (match_dup 0) (pc)) (const_int 256))))
142+ (const_int 2)
143+ (const_int 4)))]
144 )
145
146 (define_insn "*arm_cond_branch_reversed"
147@@ -7394,7 +7414,14 @@
148 return \"b%D1\\t%l0\";
149 "
150 [(set_attr "conds" "use")
151- (set_attr "type" "branch")]
152+ (set_attr "type" "branch")
153+ (set (attr "length")
154+ (if_then_else
155+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
156+ (and (ge (minus (match_dup 0) (pc)) (const_int -250))
157+ (le (minus (match_dup 0) (pc)) (const_int 256))))
158+ (const_int 2)
159+ (const_int 4)))]
160 )
161
162
163@@ -7846,7 +7873,14 @@
164 return \"b%?\\t%l0\";
165 }
166 "
167- [(set_attr "predicable" "yes")]
168+ [(set_attr "predicable" "yes")
169+ (set (attr "length")
170+ (if_then_else
171+ (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
172+ (and (ge (minus (match_dup 0) (pc)) (const_int -2044))
173+ (le (minus (match_dup 0) (pc)) (const_int 2048))))
174+ (const_int 2)
175+ (const_int 4)))]
176 )
177
178 (define_insn "*thumb_jump"
179@@ -8931,40 +8965,85 @@
180 (set_attr "length" "8,12")]
181 )
182
183-;; ??? Is it worth using these conditional patterns in Thumb-2 mode?
184 (define_insn "*cmp_ite0"
185 [(set (match_operand 6 "dominant_cc_register" "")
186 (compare
187 (if_then_else:SI
188 (match_operator 4 "arm_comparison_operator"
189- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
190- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
191+ [(match_operand:SI 0 "s_register_operand"
192+ "l,l,l,r,r,r,r,r,r")
193+ (match_operand:SI 1 "arm_add_operand"
194+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
195 (match_operator:SI 5 "arm_comparison_operator"
196- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
197- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
198+ [(match_operand:SI 2 "s_register_operand"
199+ "l,r,r,l,l,r,r,r,r")
200+ (match_operand:SI 3 "arm_add_operand"
201+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
202 (const_int 0))
203 (const_int 0)))]
204- "TARGET_ARM"
205+ "TARGET_32BIT"
206 "*
207 {
208- static const char * const opcodes[4][2] =
209- {
210- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
211- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
212- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
213- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
214- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
215- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
216- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
217- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
218- };
219+ static const char * const cmp1[NUM_OF_COND_CMP][2] =
220+ {
221+ {\"cmp%d5\\t%0, %1\",
222+ \"cmp%d4\\t%2, %3\"},
223+ {\"cmn%d5\\t%0, #%n1\",
224+ \"cmp%d4\\t%2, %3\"},
225+ {\"cmp%d5\\t%0, %1\",
226+ \"cmn%d4\\t%2, #%n3\"},
227+ {\"cmn%d5\\t%0, #%n1\",
228+ \"cmn%d4\\t%2, #%n3\"}
229+ };
230+ static const char * const cmp2[NUM_OF_COND_CMP][2] =
231+ {
232+ {\"cmp\\t%2, %3\",
233+ \"cmp\\t%0, %1\"},
234+ {\"cmp\\t%2, %3\",
235+ \"cmn\\t%0, #%n1\"},
236+ {\"cmn\\t%2, #%n3\",
237+ \"cmp\\t%0, %1\"},
238+ {\"cmn\\t%2, #%n3\",
239+ \"cmn\\t%0, #%n1\"}
240+ };
241+ static const char * const ite[2] =
242+ {
243+ \"it\\t%d5\",
244+ \"it\\t%d4\"
245+ };
246+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
247+ CMP_CMP, CMN_CMP, CMP_CMP,
248+ CMN_CMP, CMP_CMN, CMN_CMN};
249 int swap =
250 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
251
252- return opcodes[which_alternative][swap];
253+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
254+ if (TARGET_THUMB2) {
255+ output_asm_insn (ite[swap], operands);
256+ }
257+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
258+ return \"\";
259 }"
260 [(set_attr "conds" "set")
261- (set_attr "length" "8")]
262+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
263+ (set_attr_alternative "length"
264+ [(const_int 6)
265+ (const_int 8)
266+ (const_int 8)
267+ (const_int 8)
268+ (const_int 8)
269+ (if_then_else (eq_attr "is_thumb" "no")
270+ (const_int 8)
271+ (const_int 10))
272+ (if_then_else (eq_attr "is_thumb" "no")
273+ (const_int 8)
274+ (const_int 10))
275+ (if_then_else (eq_attr "is_thumb" "no")
276+ (const_int 8)
277+ (const_int 10))
278+ (if_then_else (eq_attr "is_thumb" "no")
279+ (const_int 8)
280+ (const_int 10))])]
281 )
282
283 (define_insn "*cmp_ite1"
284@@ -8972,35 +9051,81 @@
285 (compare
286 (if_then_else:SI
287 (match_operator 4 "arm_comparison_operator"
288- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
289- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
290+ [(match_operand:SI 0 "s_register_operand"
291+ "l,l,l,r,r,r,r,r,r")
292+ (match_operand:SI 1 "arm_add_operand"
293+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
294 (match_operator:SI 5 "arm_comparison_operator"
295- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
296- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")])
297+ [(match_operand:SI 2 "s_register_operand"
298+ "l,r,r,l,l,r,r,r,r")
299+ (match_operand:SI 3 "arm_add_operand"
300+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")])
301 (const_int 1))
302 (const_int 0)))]
303- "TARGET_ARM"
304+ "TARGET_32BIT"
305 "*
306 {
307- static const char * const opcodes[4][2] =
308- {
309- {\"cmp\\t%0, %1\;cmp%d4\\t%2, %3\",
310- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
311- {\"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\",
312- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
313- {\"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\",
314- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
315- {\"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\",
316- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
317- };
318+ static const char * const cmp1[NUM_OF_COND_CMP][2] =
319+ {
320+ {\"cmp\\t%0, %1\",
321+ \"cmp\\t%2, %3\"},
322+ {\"cmn\\t%0, #%n1\",
323+ \"cmp\\t%2, %3\"},
324+ {\"cmp\\t%0, %1\",
325+ \"cmn\\t%2, #%n3\"},
326+ {\"cmn\\t%0, #%n1\",
327+ \"cmn\\t%2, #%n3\"}
328+ };
329+ static const char * const cmp2[NUM_OF_COND_CMP][2] =
330+ {
331+ {\"cmp%d4\\t%2, %3\",
332+ \"cmp%D5\\t%0, %1\"},
333+ {\"cmp%d4\\t%2, %3\",
334+ \"cmn%D5\\t%0, #%n1\"},
335+ {\"cmn%d4\\t%2, #%n3\",
336+ \"cmp%D5\\t%0, %1\"},
337+ {\"cmn%d4\\t%2, #%n3\",
338+ \"cmn%D5\\t%0, #%n1\"}
339+ };
340+ static const char * const ite[2] =
341+ {
342+ \"it\\t%d4\",
343+ \"it\\t%D5\"
344+ };
345+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
346+ CMP_CMP, CMN_CMP, CMP_CMP,
347+ CMN_CMP, CMP_CMN, CMN_CMN};
348 int swap =
349 comparison_dominates_p (GET_CODE (operands[5]),
350 reverse_condition (GET_CODE (operands[4])));
351
352- return opcodes[which_alternative][swap];
353+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
354+ if (TARGET_THUMB2) {
355+ output_asm_insn (ite[swap], operands);
356+ }
357+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
358+ return \"\";
359 }"
360 [(set_attr "conds" "set")
361- (set_attr "length" "8")]
362+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
363+ (set_attr_alternative "length"
364+ [(const_int 6)
365+ (const_int 8)
366+ (const_int 8)
367+ (const_int 8)
368+ (const_int 8)
369+ (if_then_else (eq_attr "is_thumb" "no")
370+ (const_int 8)
371+ (const_int 10))
372+ (if_then_else (eq_attr "is_thumb" "no")
373+ (const_int 8)
374+ (const_int 10))
375+ (if_then_else (eq_attr "is_thumb" "no")
376+ (const_int 8)
377+ (const_int 10))
378+ (if_then_else (eq_attr "is_thumb" "no")
379+ (const_int 8)
380+ (const_int 10))])]
381 )
382
383 (define_insn "*cmp_and"
384@@ -9008,34 +9133,80 @@
385 (compare
386 (and:SI
387 (match_operator 4 "arm_comparison_operator"
388- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
389- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
390+ [(match_operand:SI 0 "s_register_operand"
391+ "l,l,l,r,r,r,r,r,r")
392+ (match_operand:SI 1 "arm_add_operand"
393+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
394 (match_operator:SI 5 "arm_comparison_operator"
395- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
396- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
397+ [(match_operand:SI 2 "s_register_operand"
398+ "l,r,r,l,l,r,r,r,r")
399+ (match_operand:SI 3 "arm_add_operand"
400+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
401 (const_int 0)))]
402- "TARGET_ARM"
403+ "TARGET_32BIT"
404 "*
405 {
406- static const char *const opcodes[4][2] =
407- {
408- {\"cmp\\t%2, %3\;cmp%d5\\t%0, %1\",
409- \"cmp\\t%0, %1\;cmp%d4\\t%2, %3\"},
410- {\"cmp\\t%2, %3\;cmn%d5\\t%0, #%n1\",
411- \"cmn\\t%0, #%n1\;cmp%d4\\t%2, %3\"},
412- {\"cmn\\t%2, #%n3\;cmp%d5\\t%0, %1\",
413- \"cmp\\t%0, %1\;cmn%d4\\t%2, #%n3\"},
414- {\"cmn\\t%2, #%n3\;cmn%d5\\t%0, #%n1\",
415- \"cmn\\t%0, #%n1\;cmn%d4\\t%2, #%n3\"}
416- };
417+ static const char *const cmp1[NUM_OF_COND_CMP][2] =
418+ {
419+ {\"cmp%d5\\t%0, %1\",
420+ \"cmp%d4\\t%2, %3\"},
421+ {\"cmn%d5\\t%0, #%n1\",
422+ \"cmp%d4\\t%2, %3\"},
423+ {\"cmp%d5\\t%0, %1\",
424+ \"cmn%d4\\t%2, #%n3\"},
425+ {\"cmn%d5\\t%0, #%n1\",
426+ \"cmn%d4\\t%2, #%n3\"}
427+ };
428+ static const char *const cmp2[NUM_OF_COND_CMP][2] =
429+ {
430+ {\"cmp\\t%2, %3\",
431+ \"cmp\\t%0, %1\"},
432+ {\"cmp\\t%2, %3\",
433+ \"cmn\\t%0, #%n1\"},
434+ {\"cmn\\t%2, #%n3\",
435+ \"cmp\\t%0, %1\"},
436+ {\"cmn\\t%2, #%n3\",
437+ \"cmn\\t%0, #%n1\"}
438+ };
439+ static const char *const ite[2] =
440+ {
441+ \"it\\t%d5\",
442+ \"it\\t%d4\"
443+ };
444+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
445+ CMP_CMP, CMN_CMP, CMP_CMP,
446+ CMN_CMP, CMP_CMN, CMN_CMN};
447 int swap =
448 comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
449
450- return opcodes[which_alternative][swap];
451+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
452+ if (TARGET_THUMB2) {
453+ output_asm_insn (ite[swap], operands);
454+ }
455+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
456+ return \"\";
457 }"
458 [(set_attr "conds" "set")
459 (set_attr "predicable" "no")
460- (set_attr "length" "8")]
461+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
462+ (set_attr_alternative "length"
463+ [(const_int 6)
464+ (const_int 8)
465+ (const_int 8)
466+ (const_int 8)
467+ (const_int 8)
468+ (if_then_else (eq_attr "is_thumb" "no")
469+ (const_int 8)
470+ (const_int 10))
471+ (if_then_else (eq_attr "is_thumb" "no")
472+ (const_int 8)
473+ (const_int 10))
474+ (if_then_else (eq_attr "is_thumb" "no")
475+ (const_int 8)
476+ (const_int 10))
477+ (if_then_else (eq_attr "is_thumb" "no")
478+ (const_int 8)
479+ (const_int 10))])]
480 )
481
482 (define_insn "*cmp_ior"
483@@ -9043,34 +9214,80 @@
484 (compare
485 (ior:SI
486 (match_operator 4 "arm_comparison_operator"
487- [(match_operand:SI 0 "s_register_operand" "r,r,r,r")
488- (match_operand:SI 1 "arm_add_operand" "rI,L,rI,L")])
489+ [(match_operand:SI 0 "s_register_operand"
490+ "l,l,l,r,r,r,r,r,r")
491+ (match_operand:SI 1 "arm_add_operand"
492+ "lPy,lPy,lPy,rI,L,rI,L,rI,L")])
493 (match_operator:SI 5 "arm_comparison_operator"
494- [(match_operand:SI 2 "s_register_operand" "r,r,r,r")
495- (match_operand:SI 3 "arm_add_operand" "rI,rI,L,L")]))
496+ [(match_operand:SI 2 "s_register_operand"
497+ "l,r,r,l,l,r,r,r,r")
498+ (match_operand:SI 3 "arm_add_operand"
499+ "lPy,rI,L,lPy,lPy,rI,rI,L,L")]))
500 (const_int 0)))]
501- "TARGET_ARM"
502+ "TARGET_32BIT"
503 "*
504-{
505- static const char *const opcodes[4][2] =
506 {
507- {\"cmp\\t%0, %1\;cmp%D4\\t%2, %3\",
508- \"cmp\\t%2, %3\;cmp%D5\\t%0, %1\"},
509- {\"cmn\\t%0, #%n1\;cmp%D4\\t%2, %3\",
510- \"cmp\\t%2, %3\;cmn%D5\\t%0, #%n1\"},
511- {\"cmp\\t%0, %1\;cmn%D4\\t%2, #%n3\",
512- \"cmn\\t%2, #%n3\;cmp%D5\\t%0, %1\"},
513- {\"cmn\\t%0, #%n1\;cmn%D4\\t%2, #%n3\",
514- \"cmn\\t%2, #%n3\;cmn%D5\\t%0, #%n1\"}
515- };
516- int swap =
517- comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
518+ static const char *const cmp1[NUM_OF_COND_CMP][2] =
519+ {
520+ {\"cmp\\t%0, %1\",
521+ \"cmp\\t%2, %3\"},
522+ {\"cmn\\t%0, #%n1\",
523+ \"cmp\\t%2, %3\"},
524+ {\"cmp\\t%0, %1\",
525+ \"cmn\\t%2, #%n3\"},
526+ {\"cmn\\t%0, #%n1\",
527+ \"cmn\\t%2, #%n3\"}
528+ };
529+ static const char *const cmp2[NUM_OF_COND_CMP][2] =
530+ {
531+ {\"cmp%D4\\t%2, %3\",
532+ \"cmp%D5\\t%0, %1\"},
533+ {\"cmp%D4\\t%2, %3\",
534+ \"cmn%D5\\t%0, #%n1\"},
535+ {\"cmn%D4\\t%2, #%n3\",
536+ \"cmp%D5\\t%0, %1\"},
537+ {\"cmn%D4\\t%2, #%n3\",
538+ \"cmn%D5\\t%0, #%n1\"}
539+ };
540+ static const char *const ite[2] =
541+ {
542+ \"it\\t%D4\",
543+ \"it\\t%D5\"
544+ };
545+ static const int cmp_idx[9] = {CMP_CMP, CMP_CMP, CMP_CMN,
546+ CMP_CMP, CMN_CMP, CMP_CMP,
547+ CMN_CMP, CMP_CMN, CMN_CMN};
548+ int swap =
549+ comparison_dominates_p (GET_CODE (operands[5]), GET_CODE (operands[4]));
550
551- return opcodes[which_alternative][swap];
552-}
553-"
554+ output_asm_insn (cmp1[cmp_idx[which_alternative]][swap], operands);
555+ if (TARGET_THUMB2) {
556+ output_asm_insn (ite[swap], operands);
557+ }
558+ output_asm_insn (cmp2[cmp_idx[which_alternative]][swap], operands);
559+ return \"\";
560+ }
561+ "
562 [(set_attr "conds" "set")
563- (set_attr "length" "8")]
564+ (set_attr "arch" "t2,t2,t2,t2,t2,any,any,any,any")
565+ (set_attr_alternative "length"
566+ [(const_int 6)
567+ (const_int 8)
568+ (const_int 8)
569+ (const_int 8)
570+ (const_int 8)
571+ (if_then_else (eq_attr "is_thumb" "no")
572+ (const_int 8)
573+ (const_int 10))
574+ (if_then_else (eq_attr "is_thumb" "no")
575+ (const_int 8)
576+ (const_int 10))
577+ (if_then_else (eq_attr "is_thumb" "no")
578+ (const_int 8)
579+ (const_int 10))
580+ (if_then_else (eq_attr "is_thumb" "no")
581+ (const_int 8)
582+ (const_int 10))])]
583 )
584
585 (define_insn_and_split "*ior_scc_scc"
586@@ -9082,11 +9299,11 @@
587 [(match_operand:SI 4 "s_register_operand" "r")
588 (match_operand:SI 5 "arm_add_operand" "rIL")])))
589 (clobber (reg:CC CC_REGNUM))]
590- "TARGET_ARM
591+ "TARGET_32BIT
592 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y)
593 != CCmode)"
594 "#"
595- "TARGET_ARM && reload_completed"
596+ "TARGET_32BIT && reload_completed"
597 [(set (match_dup 7)
598 (compare
599 (ior:SI
600@@ -9115,9 +9332,9 @@
601 (set (match_operand:SI 7 "s_register_operand" "=r")
602 (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
603 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
604- "TARGET_ARM"
605+ "TARGET_32BIT"
606 "#"
607- "TARGET_ARM && reload_completed"
608+ "TARGET_32BIT && reload_completed"
609 [(set (match_dup 0)
610 (compare
611 (ior:SI
612@@ -9138,11 +9355,11 @@
613 [(match_operand:SI 4 "s_register_operand" "r")
614 (match_operand:SI 5 "arm_add_operand" "rIL")])))
615 (clobber (reg:CC CC_REGNUM))]
616- "TARGET_ARM
617+ "TARGET_32BIT
618 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
619 != CCmode)"
620 "#"
621- "TARGET_ARM && reload_completed
622+ "TARGET_32BIT && reload_completed
623 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
624 != CCmode)"
625 [(set (match_dup 7)
626@@ -9173,9 +9390,9 @@
627 (set (match_operand:SI 7 "s_register_operand" "=r")
628 (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])
629 (match_op_dup 6 [(match_dup 4) (match_dup 5)])))]
630- "TARGET_ARM"
631+ "TARGET_32BIT"
632 "#"
633- "TARGET_ARM && reload_completed"
634+ "TARGET_32BIT && reload_completed"
635 [(set (match_dup 0)
636 (compare
637 (and:SI
638@@ -9200,11 +9417,11 @@
639 [(match_operand:SI 4 "s_register_operand" "r,r,r")
640 (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")])))
641 (clobber (reg:CC CC_REGNUM))]
642- "TARGET_ARM
643+ "TARGET_32BIT
644 && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y)
645 == CCmode)"
646 "#"
647- "TARGET_ARM && reload_completed"
648+ "TARGET_32BIT && reload_completed"
649 [(parallel [(set (match_dup 0)
650 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
651 (clobber (reg:CC CC_REGNUM))])
652@@ -10314,6 +10531,8 @@
653 ;; Push multiple registers to the stack. Registers are in parallel (use ...)
654 ;; expressions. For simplicity, the first register is also in the unspec
655 ;; part.
656+;; To avoid the usage of GNU extension, the length attribute is computed
657+;; in a C function arm_attr_length_push_multi.
658 (define_insn "*push_multi"
659 [(match_parallel 2 "multi_register_push"
660 [(set (match_operand:BLK 0 "memory_operand" "=m")
661@@ -10353,7 +10572,9 @@
662
663 return \"\";
664 }"
665- [(set_attr "type" "store4")]
666+ [(set_attr "type" "store4")
667+ (set (attr "length")
668+ (symbol_ref "arm_attr_length_push_multi (operands[2], operands[1])"))]
669 )
670
671 (define_insn "stack_tie"
672
673=== modified file 'gcc/config/arm/constraints.md'
674--- old/gcc/config/arm/constraints.md 2011-08-25 13:26:58 +0000
675+++ new/gcc/config/arm/constraints.md 2011-09-12 14:14:00 +0000
676@@ -31,7 +31,7 @@
677 ;; The following multi-letter normal constraints have been used:
678 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dz
679 ;; in Thumb-1 state: Pa, Pb, Pc, Pd
680-;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px
681+;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
682
683 ;; The following memory constraints have been used:
684 ;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
685@@ -201,6 +201,11 @@
686 (and (match_code "const_int")
687 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
688
689+(define_constraint "Py"
690+ "@internal In Thumb-2 state a constant in the range 0 to 255"
691+ (and (match_code "const_int")
692+ (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
693+
694 (define_constraint "G"
695 "In ARM/Thumb-2 state a valid FPA immediate constant."
696 (and (match_code "const_double")
697
698=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c'
699--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c 1970-01-01 00:00:00 +0000
700+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c 2011-09-12 14:14:00 +0000
701@@ -0,0 +1,13 @@
702+/* Use conditional compare */
703+/* { dg-options "-O2" } */
704+/* { dg-skip-if "" { arm_thumb1_ok } } */
705+/* { dg-final { scan-assembler "cmpne" } } */
706+
707+int f(int i, int j)
708+{
709+ if ( (i == '+') || (j == '-') ) {
710+ return 1;
711+ } else {
712+ return 0;
713+ }
714+}
715
716=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c'
717--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c 1970-01-01 00:00:00 +0000
718+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c 2011-09-12 14:14:00 +0000
719@@ -0,0 +1,13 @@
720+/* Use conditional compare */
721+/* { dg-options "-O2" } */
722+/* { dg-skip-if "" { arm_thumb1_ok } } */
723+/* { dg-final { scan-assembler "cmpeq" } } */
724+
725+int f(int i, int j)
726+{
727+ if ( (i == '+') && (j == '-') ) {
728+ return 1;
729+ } else {
730+ return 0;
731+ }
732+}
733
734=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c'
735--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c 1970-01-01 00:00:00 +0000
736+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c 2011-09-12 14:14:00 +0000
737@@ -0,0 +1,12 @@
738+/* Use conditional compare */
739+/* { dg-options "-O2" } */
740+/* { dg-skip-if "" { arm_thumb1_ok } } */
741+/* { dg-final { scan-assembler "cmpgt" } } */
742+
743+int f(int i, int j)
744+{
745+ if ( (i >= '+') ? (j > '-') : 0)
746+ return 1;
747+ else
748+ return 0;
749+}
750
751=== added file 'gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c'
752--- old/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c 1970-01-01 00:00:00 +0000
753+++ new/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c 2011-09-12 14:14:00 +0000
754@@ -0,0 +1,12 @@
755+/* Use conditional compare */
756+/* { dg-options "-O2" } */
757+/* { dg-skip-if "" { arm_thumb1_ok } } */
758+/* { dg-final { scan-assembler "cmpgt" } } */
759+
760+int f(int i, int j)
761+{
762+ if ( (i >= '+') ? (j <= '-') : 1)
763+ return 1;
764+ else
765+ return 0;
766+}
767
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
new file mode 100644
index 0000000000..41b5c6dbf9
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106811.patch
@@ -0,0 +1,203 @@
12011-09-15 Richard Sandiford <richard.sandiford@linaro.org>
2
3 Revert:
4
5 gcc/
6 PR target/49030
7 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
8 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
9 reusing the old code from get_arm_condition_code. Return ARM_NV
10 for invalid comparison codes.
11 (get_arm_condition_code): Redefine in terms of
12 maybe_get_arm_condition_code.
13 * config/arm/predicates.md (arm_comparison_operator): Use
14 maybe_get_arm_condition_code.
15
16 gcc/testsuite/
17 PR target/49030
18 * gcc.dg/torture/pr49030.c: New test.
19
20=== modified file 'gcc/config/arm/arm-protos.h'
21--- old/gcc/config/arm/arm-protos.h 2011-09-12 14:14:00 +0000
22+++ new/gcc/config/arm/arm-protos.h 2011-09-15 09:45:31 +0000
23@@ -180,7 +180,6 @@
24 #endif
25 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
26 #ifdef RTX_CODE
27-extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
28 extern void thumb1_final_prescan_insn (rtx);
29 extern void thumb2_final_prescan_insn (rtx);
30 extern const char *thumb_load_double_from_address (rtx *);
31
32=== modified file 'gcc/config/arm/arm.c'
33--- old/gcc/config/arm/arm.c 2011-09-12 14:14:00 +0000
34+++ new/gcc/config/arm/arm.c 2011-09-15 09:45:31 +0000
35@@ -17494,10 +17494,10 @@
36 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
37
38 /* Returns the index of the ARM condition code string in
39- `arm_condition_codes', or ARM_NV if the comparison is invalid.
40- COMPARISON should be an rtx like `(eq (...) (...))'. */
41-enum arm_cond_code
42-maybe_get_arm_condition_code (rtx comparison)
43+ `arm_condition_codes'. COMPARISON should be an rtx like
44+ `(eq (...) (...))'. */
45+static enum arm_cond_code
46+get_arm_condition_code (rtx comparison)
47 {
48 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
49 enum arm_cond_code code;
50@@ -17521,11 +17521,11 @@
51 case CC_DLTUmode: code = ARM_CC;
52
53 dominance:
54+ gcc_assert (comp_code == EQ || comp_code == NE);
55+
56 if (comp_code == EQ)
57 return ARM_INVERSE_CONDITION_CODE (code);
58- if (comp_code == NE)
59- return code;
60- return ARM_NV;
61+ return code;
62
63 case CC_NOOVmode:
64 switch (comp_code)
65@@ -17534,7 +17534,7 @@
66 case EQ: return ARM_EQ;
67 case GE: return ARM_PL;
68 case LT: return ARM_MI;
69- default: return ARM_NV;
70+ default: gcc_unreachable ();
71 }
72
73 case CC_Zmode:
74@@ -17542,7 +17542,7 @@
75 {
76 case NE: return ARM_NE;
77 case EQ: return ARM_EQ;
78- default: return ARM_NV;
79+ default: gcc_unreachable ();
80 }
81
82 case CC_Nmode:
83@@ -17550,7 +17550,7 @@
84 {
85 case NE: return ARM_MI;
86 case EQ: return ARM_PL;
87- default: return ARM_NV;
88+ default: gcc_unreachable ();
89 }
90
91 case CCFPEmode:
92@@ -17575,7 +17575,7 @@
93 /* UNEQ and LTGT do not have a representation. */
94 case UNEQ: /* Fall through. */
95 case LTGT: /* Fall through. */
96- default: return ARM_NV;
97+ default: gcc_unreachable ();
98 }
99
100 case CC_SWPmode:
101@@ -17591,7 +17591,7 @@
102 case GTU: return ARM_CC;
103 case LEU: return ARM_CS;
104 case LTU: return ARM_HI;
105- default: return ARM_NV;
106+ default: gcc_unreachable ();
107 }
108
109 case CC_Cmode:
110@@ -17599,7 +17599,7 @@
111 {
112 case LTU: return ARM_CS;
113 case GEU: return ARM_CC;
114- default: return ARM_NV;
115+ default: gcc_unreachable ();
116 }
117
118 case CC_CZmode:
119@@ -17611,7 +17611,7 @@
120 case GTU: return ARM_HI;
121 case LEU: return ARM_LS;
122 case LTU: return ARM_CC;
123- default: return ARM_NV;
124+ default: gcc_unreachable ();
125 }
126
127 case CC_NCVmode:
128@@ -17621,7 +17621,7 @@
129 case LT: return ARM_LT;
130 case GEU: return ARM_CS;
131 case LTU: return ARM_CC;
132- default: return ARM_NV;
133+ default: gcc_unreachable ();
134 }
135
136 case CCmode:
137@@ -17637,22 +17637,13 @@
138 case GTU: return ARM_HI;
139 case LEU: return ARM_LS;
140 case LTU: return ARM_CC;
141- default: return ARM_NV;
142+ default: gcc_unreachable ();
143 }
144
145 default: gcc_unreachable ();
146 }
147 }
148
149-/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
150-static enum arm_cond_code
151-get_arm_condition_code (rtx comparison)
152-{
153- enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
154- gcc_assert (code != ARM_NV);
155- return code;
156-}
157-
158 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
159 instructions. */
160 void
161
162=== modified file 'gcc/config/arm/predicates.md'
163--- old/gcc/config/arm/predicates.md 2011-09-12 12:32:29 +0000
164+++ new/gcc/config/arm/predicates.md 2011-09-15 09:45:31 +0000
165@@ -243,9 +243,10 @@
166 ;; True for integer comparisons and, if FP is active, for comparisons
167 ;; other than LTGT or UNEQ.
168 (define_special_predicate "arm_comparison_operator"
169- (and (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
170- unordered,ordered,unlt,unle,unge,ungt")
171- (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
172+ (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
173+ (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
174+ && (TARGET_FPA || TARGET_VFP)")
175+ (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
176
177 (define_special_predicate "lt_ge_comparison_operator"
178 (match_code "lt,ge"))
179
180=== removed file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
181--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-09-05 09:40:19 +0000
182+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
183@@ -1,19 +0,0 @@
184-void
185-sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
186- unsigned long dst_skip)
187-{
188- long long y;
189- while (nsamples--)
190- {
191- y = (long long) (*src * 8388608.0f) << 8;
192- if (y > 2147483647) {
193- *(int *) dst = 2147483647;
194- } else if (y < -2147483647 - 1) {
195- *(int *) dst = -2147483647 - 1;
196- } else {
197- *(int *) dst = (int) y;
198- }
199- dst += dst_skip;
200- src++;
201- }
202-}
203
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