diff options
| author | Naveen Saini <naveen.kumar.saini@intel.com> | 2021-08-27 15:28:26 +0800 |
|---|---|---|
| committer | Anuj Mittal <anuj.mittal@intel.com> | 2021-08-27 23:28:04 +0800 |
| commit | 61efde5c41f73784d1c771b7ff1a63ba655326c0 (patch) | |
| tree | 137c00a1ff3030ba3119b8732459085b8a8e00fd | |
| parent | 224b7c75116e5b9755816e692612ef6c12698476 (diff) | |
| download | meta-intel-61efde5c41f73784d1c771b7ff1a63ba655326c0.tar.gz | |
llvm/12.0.0: apply ispc recommended patches
ISPC recommends building LLVM 12 with some additional patches to work
around some bugs in this version. Add those patches to our build as well.
https://github.com/ispc/ispc/tree/v1.16.1/llvm_patches
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
3 files changed, 104 insertions, 0 deletions
diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch new file mode 100644 index 00000000..fb15d19c --- /dev/null +++ b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | From 0c4ba4947d1630f2e13fc260399f0892b2c9b323 Mon Sep 17 00:00:00 2001 | ||
| 2 | From: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 3 | Date: Fri, 27 Aug 2021 10:55:13 +0800 | ||
| 4 | Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only | ||
| 5 | |||
| 6 | 1. Transformation of add to or is not safe for VC backend. | ||
| 7 | 2. bswap intrinsics is not supported in VC backend yet. | ||
| 8 | |||
| 9 | Upstream-Status: Backport [Taken from ispc, https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch] | ||
| 10 | |||
| 11 | Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 12 | --- | ||
| 13 | llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 10 +++++++--- | ||
| 14 | .../lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 9 ++++++--- | ||
| 15 | 2 files changed, 13 insertions(+), 6 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | ||
| 18 | index bacb8689892a..f3d0120db256 100644 | ||
| 19 | --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | ||
| 20 | +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | ||
| 21 | @@ -15,6 +15,7 @@ | ||
| 22 | #include "llvm/ADT/APInt.h" | ||
| 23 | #include "llvm/ADT/STLExtras.h" | ||
| 24 | #include "llvm/ADT/SmallVector.h" | ||
| 25 | +#include "llvm/ADT/Triple.h" | ||
| 26 | #include "llvm/Analysis/InstructionSimplify.h" | ||
| 27 | #include "llvm/Analysis/ValueTracking.h" | ||
| 28 | #include "llvm/IR/Constant.h" | ||
| 29 | @@ -1363,9 +1364,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) { | ||
| 30 | } | ||
| 31 | } | ||
| 32 | |||
| 33 | - // A+B --> A|B iff A and B have no bits set in common. | ||
| 34 | - if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT)) | ||
| 35 | - return BinaryOperator::CreateOr(LHS, RHS); | ||
| 36 | + // Disable this transformation for ISPC SPIR-V | ||
| 37 | + if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) { | ||
| 38 | + // A+B --> A|B iff A and B have no bits set in common. | ||
| 39 | + if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT)) | ||
| 40 | + return BinaryOperator::CreateOr(LHS, RHS); | ||
| 41 | + } | ||
| 42 | |||
| 43 | // add (select X 0 (sub n A)) A --> select X A n | ||
| 44 | { | ||
| 45 | diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | ||
| 46 | index 68c4156af2c4..b145b863ca84 100644 | ||
| 47 | --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | ||
| 48 | +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | ||
| 49 | @@ -2584,9 +2584,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { | ||
| 50 | if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I)) | ||
| 51 | return FoldedLogic; | ||
| 52 | |||
| 53 | - if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true, | ||
| 54 | - /*MatchBitReversals*/ false)) | ||
| 55 | - return BSwap; | ||
| 56 | + // Disable this transformation for ISPC SPIR-V | ||
| 57 | + if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) { | ||
| 58 | + if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true, | ||
| 59 | + /*MatchBitReversals*/ false)) | ||
| 60 | + return BSwap; | ||
| 61 | + } | ||
| 62 | |||
| 63 | if (Instruction *Funnel = matchFunnelShift(I, *this)) | ||
| 64 | return Funnel; | ||
| 65 | -- | ||
| 66 | 2.17.1 | ||
| 67 | |||
diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0005-ispc-12_0_fix_for_2111.patch b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0005-ispc-12_0_fix_for_2111.patch new file mode 100644 index 00000000..4951a63d --- /dev/null +++ b/dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0005-ispc-12_0_fix_for_2111.patch | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | From 913e07ea5acf2148e3748b45ddfe3fac3b2d051c Mon Sep 17 00:00:00 2001 | ||
| 2 | From: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 3 | Date: Fri, 27 Aug 2021 10:56:57 +0800 | ||
| 4 | Subject: [PATCH 2/2] This patch is a fix for #2111 | ||
| 5 | |||
| 6 | It ensures that shuffle is lowered for this particular case correctly. | ||
| 7 | |||
| 8 | Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/9ab99f773fec7da4183495a3fdc655a797d3bea2] | ||
| 9 | |||
| 10 | Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com> | ||
| 11 | --- | ||
| 12 | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++++--- | ||
| 13 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
| 16 | index 6b816c710f98..3121b0e818ac 100644 | ||
| 17 | --- a/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
| 18 | +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp | ||
| 19 | @@ -43192,9 +43192,10 @@ static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG, | ||
| 20 | ShuffleVectorSDNode::commuteMask(ShuffleMask1); | ||
| 21 | } | ||
| 22 | if ((Op00 == Op10) && (Op01 == Op11)) { | ||
| 23 | - SmallVector<int, 4> ShuffleMask; | ||
| 24 | - ShuffleMask.append(ShuffleMask0.begin(), ShuffleMask0.end()); | ||
| 25 | - ShuffleMask.append(ShuffleMask1.begin(), ShuffleMask1.end()); | ||
| 26 | + const int Map[4] = {0, 2, 1, 3}; | ||
| 27 | + SmallVector<int, 4> ShuffleMask( | ||
| 28 | + {Map[ShuffleMask0[0]], Map[ShuffleMask1[0]], Map[ShuffleMask0[1]], | ||
| 29 | + Map[ShuffleMask1[1]]}); | ||
| 30 | SDLoc DL(N); | ||
| 31 | MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64; | ||
| 32 | SDValue Res = DAG.getNode(Opcode, DL, VT, Op00, Op01); | ||
| 33 | -- | ||
| 34 | 2.17.1 | ||
| 35 | |||
diff --git a/dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend b/dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend index 01af38c2..8b4f6e31 100644 --- a/dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend +++ b/dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend | |||
| @@ -34,6 +34,8 @@ SRC_URI_LLVM12_PATCHES = " \ | |||
| 34 | file://llvm12-0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \ | 34 | file://llvm12-0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \ |
| 35 | file://llvm12-0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \ | 35 | file://llvm12-0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \ |
| 36 | file://llvm12-0003-Support-cl_ext_float_atomics.patch \ | 36 | file://llvm12-0003-Support-cl_ext_float_atomics.patch \ |
| 37 | file://llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch \ | ||
| 38 | file://llvm12-0005-ispc-12_0_fix_for_2111.patch \ | ||
| 37 | " | 39 | " |
| 38 | 40 | ||
| 39 | 41 | ||
