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| author | Ernest Van Hoecke <ernest.vanhoecke@toradex.com> | 2025-08-08 17:36:32 +0200 |
|---|---|---|
| committer | Hiago De Franco <hiago.franco@toradex.com> | 2025-09-09 16:36:55 -0300 |
| commit | 8e1ebe57dec8748effffe80cc0a29b8b5446206b (patch) | |
| tree | 7b11396bf2754291d9c412d7e6284f0d7652af04 | |
| parent | 8e02ec952d04d5f52c9c96f57efe5f866d07c094 (diff) | |
| download | meta-freescale-8e1ebe57dec8748effffe80cc0a29b8b5446206b.tar.gz | |
imx-base.inc: Update i.MX95 default Rev to B0
This is necessary to align with NXP BSP LF6.6.52-2.2.1.
In imx-oei, the default DDR timings have been updated to B0, and anyone
building for A0/A1 is expected to pass the argument DDR_CONFIG with the
A1 timings to imx-oei.
Therefore, a machine conf for A0/A1 support that also sets the desired
timings is always necessary, and we have to drop A0/A1 from
imx-base.inc. It is not enough to override IMX_SOC_REV to support A0/A1.
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
(cherry picked from commit e43eb830443b70b82a67e90dd785736fac90f16d)
| -rw-r--r-- | conf/machine/include/imx-base.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/conf/machine/include/imx-base.inc b/conf/machine/include/imx-base.inc index f9151e4f9..50e89e9be 100644 --- a/conf/machine/include/imx-base.inc +++ b/conf/machine/include/imx-base.inc | |||
| @@ -185,6 +185,7 @@ IMX_SOC_REV:mx8ulp-generic-bsp ??= \ | |||
| 185 | "${@bb.utils.contains('MACHINE_FEATURES', 'soc-reva0', 'A0', \ | 185 | "${@bb.utils.contains('MACHINE_FEATURES', 'soc-reva0', 'A0', \ |
| 186 | 'A2', d)}" | 186 | 'A2', d)}" |
| 187 | IMX_SOC_REV:mx93-generic-bsp ??= "A1" | 187 | IMX_SOC_REV:mx93-generic-bsp ??= "A1" |
| 188 | IMX_SOC_REV:mx95-generic-bsp ??= "B0" | ||
| 188 | 189 | ||
| 189 | IMX_SOC_REV_LOWER = "${@d.getVar('IMX_SOC_REV').lower()}" | 190 | IMX_SOC_REV_LOWER = "${@d.getVar('IMX_SOC_REV').lower()}" |
| 190 | IMX_SOC_REV_UPPER = "${@d.getVar('IMX_SOC_REV').upper()}" | 191 | IMX_SOC_REV_UPPER = "${@d.getVar('IMX_SOC_REV').upper()}" |