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* qemu.inc: drop duplicates with default-providers.incDmitry Baryshkov2025-06-241-7/+0
| | | | | | | | | | | default-providers.inc already includes PREFERRED_PROVIDER values for xserver and GL libraries. Drop the same values being set in the machine config. (From OE-Core rev: 882e8c3cf28b33cdd6cb26ec412e63a0da8a3199) Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* meta: remove consecutive blank linesAlexander Kanavin2025-06-203-5/+0
| | | | | | | | | | | | | | | | | Some of them were introduced by mass-removal of S = WORKDIR/git assignments; rather than try to fix up (or redo) just these, I've run this sed command over the whole tree: sed -i -z -E 's/([ \t\f\v\r]*\n){3,}/\n\n/g' `find . -name *.bb -o -name *.inc` The rationale is that more than one empty line is wasting vertical screen space, and does nothing for readability. (From OE-Core rev: cedc4ff7c9bcfb22a20e43e47f9759f4007a4f1a) Signed-off-by: Alexander Kanavin <alex@linutronix.de> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* riscv tunes: ISA Implementation of RISC-V tune featuresMark Hatle2025-06-203-35/+265
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-cortexr52: Remove aarch64 for ARM Cortex-R52Sandeep Gundlupet Raju2025-06-121-3/+2
| | | | | | | | | | | | Remove aarch64 for ARM Cortex-R52 processor as it supports only 32-bit ISA but not 64-bit ISA. Also update ARMPKGARCH for cortexr52hf. (From OE-Core rev: efe2e5289333bb6e7fca9cdeff784ab7e4872227) Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> Signed-off-by: Sandeep Gundlupet Raju <grsandeep85@gmail.com> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arch-powerpc: Use -maltivec in compiler flags if altivec is in tune featuresKhem Raj2025-05-121-0/+1
| | | | | | | (From OE-Core rev: 80ecd2c42e9e1215de403ef9b69ab290f26cd750) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arch-mips.inc: Use -EB/-EL for denoting endiannessKhem Raj2025-05-081-1/+1
| | | | | | | | | | | | | | While -meb/-mel works it is not documented as supported and using -EL/-EB also makes clang work without tweaking TUNE_CCARGS Fixes mips-poky-linux-musl-clang: error: unknown argument: '-meb' (From OE-Core rev: 3d4bbd917613968ef0a7059ec11cf236b290c43c) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuriscv: Enable Sv39 memory address scheme by defaultYash Shinde2025-02-051-0/+1
| | | | | | | | | | | | | | | | | | | | Currently, GCC Asan supports only Sv39 on RISC-V 64 due to custom allocator configurations optimized for large allocations. These configurations are incompatible with larger address spaces like Sv48/Sv57. This fix enables RISC-V 64 configuration for RVA22S64 profile(which has sv39 mode and other extensions) by default when running `runqemu nographic`, eliminating the need for manual configuration via command line flags (`qemuparams="-cpu rv64, sv39=true"`). Fixes [YOCTO #15691] https://bugzilla.yoctoproject.org/show_bug.cgi?id=15691 Reference: https://github.com/qemu/qemu/commit/af651969eb23ecf018bcaa8e0761b58425de550c https://git.openembedded.org/openembedded-core/commit/?id=4b4450ff695ef73bf7a2437e142d2e0730d6a547 (From OE-Core rev: 5e749a2576698e390392b5d522a2dc5fdc9556cd) Signed-off-by: Yash Shinde <Yash.Shinde@windriver.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemu/machine: rename QEMU_EXTRAOPTIONS for consistencyRoss Burton2025-01-1112-38/+38
| | | | | | | | | | | | | | | | | The per-tune qemu options variable is QEMU_EXTRAOPTIONS_${TUNE_PKGARCH}, but this doesn't follow the pattern of all of the other tune-specific variables in the machine configuration which is VARIABLE:tune-[name]. Rename QEMU_EXTRAOPTIONS_${TUNE_PKGARCH} to QEMU_EXTRAOPTIONS:tune-${TUNE_PKGARCH} for consistency. Note that this will mean that BSPs need to update any assignments of this variable. (From OE-Core rev: 7f981d074442b901f7e64dbdb9db851ff31c3733) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* classes/qemu: move QEMU_EXTRAOPTIONS for PPC to the relevant tunesRoss Burton2025-01-116-0/+8
| | | | | | | | | | Every other architecture has the QEMU_EXTRAOPTIONS assignments in the tune files, so move the PPC ones too. (From OE-Core rev: ba05251c89d8cc243e861886124573c83197e949) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemu/testimage: Ensure GNU tar is in test imagesRichard Purdie2024-11-211-0/+3
| | | | | | | | | | | | | | | | We've seen cases where a ptest (strace) has a 43GB sparse file in the test directory. busybox tar doesn't work well with this. The resulting 1.4GB archive takes hours to extract too. Ensure tar is added to our full images and use the sparse option to collect files for debugging. This stops crazy build hangs. Since tar is GPLv3, we have to exclude it from that test code. We don't boot any of those images so the debug collection code is safe there, at least for now. (From OE-Core rev: fefeb919696b6ac76f0997acfb0f612203ef7f1b) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-cortexa32: set tune feature as armv8aJagadeesh Krishnanjanappa2024-10-221-1/+1
| | | | | | | | | | | | | | | | | | Cortexa32 is a 32-bit armv8a architecture processor, so set the tune feature as armv8a instead of aarch64 which is 64-bit armv8a architecture. It solves the following build error while compiling libgcc-initial and libssp-nonshared. -- snip -- aarch64-poky-linux-musl-gcc: error: unrecognized command-line option '-mfpu=neon' aarch64-poky-linux-musl-gcc: error: unrecognized command-line option '-mfloat-abi=hard' -- snip -- (From OE-Core rev: 3b898270aca62559dfa42ed71d296fe8a8b46a41) Signed-off-by: Jagadeesh Krishnanjanappa <workjagadeesh@gmail.com> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tclibc-picolibc: Adds a new TCLIBC variant to build with picolibc as C libraryAlejandro Hernandez Samaniego2024-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables usage of TCLIBC=picolibc extending OE functionality to build and use picolibc based toolchains to build baremetal applications. Picolibc is a set of standard C libraries, both libc and libm, designed for smaller embedded systems with limited ROM and RAM. Picolibc includes code from Newlib and AVR Libc, but adresses some of newlibs concerns, it retains newlibs directory structure, math, string and locale implementations, but removed the GPL bits used to build the library, swiches old C style code for C18 and replaces autotools with meson. This patch adds a picolibc recipe for the C library, a picolibc-helloworld recipe that contains an example application and a testcase that builds it. Picolibc can be built for ARM and RISCV architectures, its been tested both for 32 and 64 bits, the provided example recipe produces the following output: hello, world Runqemu does not automatically show any output since it hides QEMU stderr which is where the QEMU monitors output is directed to when using semihosting, but, manually running the same QEMU command does work properly. (From OE-Core rev: c7535ecaccb72ef21a61f9aec5c68e61fb4f6fb6) Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandro@enedino.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* classes/qemuboot: add depends on qemu-system-native and qemu-helper-nativeRoss Burton2024-03-251-2/+0
| | | | | | | | | | | | | | | | | Any image that inherits qemuboot must also add image dependencies on qemu-system-native and qemu-helper-native, otherwise the image won't be able to be booted. Currently this is done by conf/machine/include/qemu.inc, but not every machine that uses qemuboot includes that file. Move the EXTRA_IMAGEDEPENDS from qemu.inc into qemuboot.bbclass, so that the dependencies don't have to be duplicated. (From OE-Core rev: dd54cf058f632e985917ff227483995f368e6a7d) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuriscv: Fix kbd and mouse emulation for qemuriscv64Khem Raj2024-03-221-1/+2
| | | | | | | (From OE-Core rev: 870bfc48f1d051831a9326b7f320abbbb6fa26d6) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* loongarch64: change -march to loongarch64Xiaotian Wu2024-02-271-1/+1
| | | | | | | | | Now both gcc and clang all support -march=loongarch64, so we can use it. (From OE-Core rev: acc08582293709c73011083aa7d5c631a9ae8c8c) Signed-off-by: Xiaotian Wu <wuxiaotian@loongson.cn> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* feature-microblaze-versions.inc: python 3.12 regexAdrian Freihofer2024-02-131-1/+1
| | | | | | | | | | | | | | | Python 3 interprets string literals as Unicode strings, and therefore \s is treated as an escaped Unicode character which is not correct. Declaring the RegEx pattern as a raw string instead of unicode is required for Python 3. (From OE-Core rev: 662f52f1713c9f070550fc0c874eb62312218ea4) Signed-off-by: Adrian Freihofer <adrian.freihofer@siemens.com> feature-microblaze-versions.inc# Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* conf/machine: Add Power8 tune to PowerPC architectureAleksey Smirnov2024-02-091-0/+31
| | | | | | | | | | Description: now we can tune our build only for power7 or power9 processor for PowerPC arch, this patch add posibility to choose power8 tune. (From OE-Core rev: 10f7eeafd16c8b825b3c9b96b8433311f122df1e) Signed-off-by: Aleksey Smirnov <aleksey.smirnov@yadro.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arm/armv*: add all the Arm tunes in GCC 13.2.0Jon Mason2024-02-0616-0/+257
| | | | | | | (From OE-Core rev: 5af154b66459ac05409619c81dd247c252b673f3) Signed-off-by: Jon Mason <jon.mason@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tunes/sve: Add support for sve2 instructionsJon Mason2024-02-063-3/+8
| | | | | | | | | | Add support for SVE2 and add to 8-2a, as it can be used there. Also, clean up the comments (From OE-Core rev: 683443d57cb18b3b54245b1a09b6e5d2bae4f5d0) Signed-off-by: Jon Mason <jon.mason@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-cortexr52: Add hard-float variantMark Hatle2024-02-031-0/+5
| | | | | | | | | | | Add the ability to specify cortexr52hf to get a version that enables the hard-float calling convention. (From OE-Core rev: be83bc937a76efaead4690237db25459a57673fc) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-cortexr5: Add hard-float variantMark Hatle2024-02-031-0/+5
| | | | | | | | | | | Add the ability to specify cortexr5hf to get a version that enables the hard-float calling convention. (From OE-Core rev: 992149023a896ecb38d07c54fa9ae9df82249a07) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* feature-arm-vfp.inc: Allow hard-float on newer simd targetsMark Hatle2024-02-031-1/+2
| | | | | | | | | | | | | | | | Currently hard-float is dependency upon the special TUNE_CCARGS_MFPU which contains custom -mfpu= values. However, newer 32-bit architectures like cortex-r52 use 'simd' instead. There is no 'simd' entry for -mfpu= according to the GCC manual, it's more or less automatic based on the cpu settings. Add this as an exception to the TUNE_CCARGS_FLOAT setting of hard or softfp. (From OE-Core rev: f122eb8b19528e1192fd0b68b0639d84aa288155) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-cortexa78.inc: Add cortexa78 tune, based on cortexa77Mark Hatle2024-02-031-0/+17
| | | | | | | | (From OE-Core rev: 6750384cbb4f8d90c8c32a85db66e8e3344d4ce6) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* armv8/armv9: Avoid using -march when -mcpu is chosenKhem Raj2024-02-0229-29/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current include logic goes into generic arm v8/v9 architecture tunes and adds corresponding -march option after synthesizing it from various tune fragments, this is fine for a machine which is using armv8/armv9 based tunes but cortex tunes are intentionally using -mcpu option based on selected tune value. So when cortex based default tune is selected for a machine, it will add both -mcpu and -march to the compiler commandline which can result in invalid combinations for this pair in gcc's own logic. This can then result in compiler warnings/errors reporting this e.g. aarch64-yoe-linux-gcc -mcpu=cortex-a72.cortex-a53 -march=armv8-a+crc+crypto -mbranch-protection=standard ... cc1: error: switch '-mcpu=cortex-a72.cortex-a53' conflicts with '-march=armv8-a+crc+crypto' switch and resulted in options '+crc+crypto' being added [-Werror] This is seen in lot of configure test results in glibc 2.39 and the warning is promoted to errors by gcc in some of these checks especially with gcc-14, the logs also show it as warning in other places in configure checks. mcpu option will compute relevant march implicitly as it specifies a cpu implementation and this will be the right value to use, therefore do not specify -march when -mcpu is already describing the cpu. (From OE-Core rev: e64f0c1b6ac5d598a79a21de5f3060f83cb9523e) Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Ross Burton <ross.burton@arm.com> Cc: Jon Mason <jdmason@kudzu.us> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-core2: Update qemu cpu to supported modelSimone Weiß2024-01-211-3/+3
| | | | | | | | | | | | | | | | | | Fixes [YOCTO #12388] QEMUs documentation does recommend to not use n270 and core2duo as an argument to -cpu anymore. See also the QEMU documentation for this at [0]. Update therefore the QEMU cpu option for the core2duo tune to Nehalam. Tested it locally with QEMU and KVM. [0]: https://qemu-project.gitlab.io/qemu/system/qemu-cpu-models.html#other-non-recommended-x86-cpus (From OE-Core rev: f2383a2bff3eb756740ecaf48147bea89303e443) Signed-off-by: Simone Weiß <simone.p.weiss@posteo.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* machine/arch-armv9: remove crc and sve tunes, they are mandatoryRoss Burton2023-12-211-18/+4
| | | | | | | | | | | | | | | | | As per the Arm ARM section A2.3.2, FEAT_CRC32 is mandatory in Armv8.1 onwards, so there's no need to have an explicit optional tune for it. SVE (which was a choice here) and SVE2 (which was not) are both optional with v9.0, but GCC's -march=armv9-a defaults to enabling both SVE and SVE2 on the grounds that there are no implementations of Armv9 that don't support SVE2. This means there's no point having an explicit sve feature as it's enabled out of the box. (From OE-Core rev: 28fabebf812cdf8e76eb508115a4b76944f1e729) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuriscv: Add to common MACHINE_FEATURES instead of overriding themKhem Raj2023-11-051-1/+1
| | | | | | | | | | | | machine features like vfat are needed for ptests to pass ( e..g. parted) This brings it closer to what x86 qemu config looks like as well. (From OE-Core rev: a6d97ecb25567ec7e56c061be9ab281b54b4d524) Signed-off-by: Khem Raj <raj.khem@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* meta/conf/machine: remove SERIAL_CONSOLES_CHECKRoss Burton2023-10-111-1/+0
| | | | | | | | | | | There's no need for this variable anymore, as all consoles listed in SERIAL_CONSOLES are checked for their existence before a getty is started. (From OE-Core rev: 8a1060952f8b6956acf747f3853401ac8a981fc3) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* runqemu/qemurunner: Use nodelay with tcp serial connectionsRichard Purdie2023-10-102-2/+2
| | | | | | | | | This disables Nagle's algorithm for our tcp serial connections which may be causing data transfer issues. (From OE-Core rev: f8eff4c427881a98333fdf7c42f66ed6603e4f03) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemux86/qemuarm: Drop kernel version overridesRichard Purdie2023-10-101-1/+0
| | | | | | | | | | | Drop the version overrides for the kernel for the x86 and arm machines so we can go back to following the distro versions. The reasons for these versions is mostly historical at this point as the issues were resolved. (From OE-Core rev: 298fa078fab58b64246376ffd70ad6a0c7589876) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* machine/qemu*: add modesetting drivers to XSERVERRoss Burton2023-09-121-0/+1
| | | | | | | | | | | | | | | The modesetting driver works well in qemu, so install it by default. The plain framebuffer has been buggy in recent 6.4 kernels, a sign that it's not getting much testing. The Xorg modesetting driver that can use more powerful virtualised hardware is much better. We override the default XSERVER because we want to pull in the GLX extension to exercise that. (From OE-Core rev: 7b5fc42488a514bf51d49ee5274731c6432efd1b) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuloongarch.inc:Change to use virtio-serial-pciZang Ruochen2023-09-071-2/+2
| | | | | | | | | | If virtio-serial-device is used, the following error occurs on loongarch64: qemu-system-loongarch64: -device virtio-serial-device: No "virtio-bus" bus found for device "virtio-serial-device" (From OE-Core rev: 08734ec0c2083e90207559ecc659809b86b8779d) Signed-off-by: Zang Ruochen <zangruochen@loongson.cn> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arch-armv8,arch-armv9: Add sve based tune optionsKhem Raj2023-08-293-3/+18
| | | | | | | | | | | (From OE-Core rev: 3109a48740546f6defc652fa1a6736dc484e6021) (From OE-Core rev: d388bf00314639f82cd9143e786c482731d2719b) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tunes: Add support for sve instructions on armv8/armv9Khem Raj2023-08-291-0/+5
| | | | | | | | | | | | | | This helps in defining correct compiler options and configure options for glibc and overall ABI for toolchain (From OE-Core rev: 58330ce58719bd82530b1143623db7af7a85e897) (From OE-Core rev: 43c980ad688cc4df5a5e687b0f693cf46778ce64) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* conf/machine: set preferred kernel to be 6.4Bruce Ashfield2023-08-161-1/+1
| | | | | | | | | | (From OE-Core rev: b544e62827d2a3606fbc886ea520256c948e197c) (From OE-Core rev: 505ea7fe653d4c61f348e737c409d43bb490ee4f) Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arch-mips: Ensure TUNE_LDARGS is set correctlyRichard Purdie2023-08-151-0/+2
| | | | | | | | | | Similarly to x86, ensure we have the flags to the linker operating correctly (it defaults to 32 bit). Normally it is driven by gcc so this hasn't shown up but it does lead to hundreds of binutils test failures. (From OE-Core rev: 2cf9013fd8df2bb67f93ffd44ccc23453cedf42a) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* mips/tune-mips64r2: Set qemu cpu option correctlyRichard Purdie2023-08-151-0/+12
| | | | | | | | Ensure the CPU enabled in QEMU is correct for this architecture. (From OE-Core rev: 6e0d176c4ce2bbbd975b74e41f63e60df7e3a554) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* machine/arch-arm64: add -mbranch-protection=standardRoss Burton2023-07-141-0/+5
| | | | | | | | | | | | Enable branch protection (PAC/BTI) for all aarch64 builds. This was previously enabled at a global level in the GCC build, but that breaks the gcc test suite. (From OE-Core rev: 8905639d1cdc5ce809cc5ecd9672f5e86bf8a579) Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuboot-x86.inc: allow overwrite of QB_CPUThomas Roos2023-03-061-4/+4
| | | | | | | | | | | | | To test nested kvm with qemu QB_CPU* needs to be modified. E.g. set to "-cpu Haswell-noTSX-IBRS,vmx=on" This allows to overwrite this from local.conf etc. (From OE-Core rev: aa9d145d90893b04cde197e9b5f4dc574e4738e1) Signed-off-by: Thomas Roos <throos@amazon.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv.inc: Add riscv64nc to available tunes listKhem Raj2023-02-241-1/+1
| | | | | | | | | This was missed when riscv64nc was added (From OE-Core rev: 0c549ef5732afdcd96407ceb045983eed2ca75f4) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* QB_SMP: allow user modificationTrevor Woerner2023-02-232-2/+2
| | | | | | | | | | Allow a user to override the QM_SMP value giving them the opportunity to select for themselves the number of CPUs to use in qemu. (From OE-Core rev: 70a91e6d0357149c00b97f7e66e16cbc52997a92) Signed-off-by: Trevor Woerner <twoerner@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* base: add support for loongarch64Xiaotian Wu2023-02-043-0/+55
| | | | | | | (From OE-Core rev: 759baaceb4dd623d5da12ba0d01540fa080154ba) Signed-off-by: Xiaotian Wu <wuxiaotian@loongson.cn> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* conf/qemu: bump preferred kernel version to 6.1Bruce Ashfield2023-01-261-1/+1
| | | | | | | | | | | 6.1 has been soaking for a while now, so it is time to bump the default qemu version to 6.1 and prepare to remove 5.19. (From OE-Core rev: 91c1f7d4eb9ec5ad683c798812395df3a56747ba) Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-x86-64-v3.inc: set QEMU_EXTRAOPTIONS like other tune-* filesMartin Jansa2023-01-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * use Skylake-Client to match QB_CPU_KVM as changed in: https://git.openembedded.org/openembedded-core/commit/?id=6f2af1e5d1537b4d31e14946292bf58f0fd76fc9 * explicitly set -cpu instead of letting qemu to choose based on host cpu * check=false is still useful as e.g. on on AMD Threadripper 3970X: orc/0.4.33-r0 $ PSEUDO_UNLOAD=1 qemu-x86_64 -r 3.2.0 -cpu Skylake-Client -L recipe-sysroot -E LD_LIBRARY_PATH=recipe-sysroot//usr/lib:recipe-sysroot//lib orc/0.4.33-r0/build/meson-private/sanitycheckc_cross.exe qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.01H:ECX.pcid [bit 17] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.01H:ECX.x2apic [bit 21] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.01H:ECX.tsc-deadline [bit 24] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.07H:EBX.hle [bit 4] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.07H:EBX.invpcid [bit 10] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.07H:EBX.rtm [bit 11] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.07H:EBX.rdseed [bit 18] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.80000001H:ECX.3dnowprefetch [bit 8] qemu-x86_64: warning: TCG doesn't support requested feature: CPUID.0DH:EAX.xsavec [bit 1] * if this still doesn't work for you on your host, you might need to downgrade DEFAULTTUNE to e.g. corei7-64 (all all the way back to core2-64), for more details see: https://www.openembedded.org/pipermail/openembedded-core/2018-April/150178.html * the leading space shouldn't be needed, I've kept it for consistency with other QEMU_EXTRAOPTIONS (From OE-Core rev: d1a52559670921389a66a4c26d37481d6611042a) Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemux86-64: Reduce tuning to core2-64Richard Purdie2023-01-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Effectively revert "qemux86-64: build for x86-64-v3 (2013 Haswell and later) rather than Core 2 from 2006" (commit 6f2af1e5d1537b4d31e14946292bf58f0fd76fc9) Much as I'd love us to use the latest tuning, we do have some autobuilder hardware which isn't ready for this yet which breaks KVM and some qemu user mode usage as there appear to be TCG bugs too. I suspect we're not the only ones with such hardware. Drop the tune back to core2-64, anyone can easily customise it themselves if they need it. We can revisit this in a year or two as we should be ready then. It has beena good test of the rest of the support which all seems ready. I'd have preferred to use corei7-64 but that causes runqemu.RunqemuTests.test_boot_machine_iso to hang. Leave the newer tune file inclusion so people can change tunes more easily. (From OE-Core rev: 369b1dfa28b1791d45f068acc765190defecd460) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemux86-64: build for x86-64-v3 (2013 Haswell and later) rather than Core 2 ↵Alexander Kanavin2023-01-061-2/+2
| | | | | | | | | | | | | | | | | | | | from 2006 This allows us to - test those more recent instruction sets (AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE) - benefit from improved performance across the stack both in kvm-driven system emulation and when running on real silicon. For example, glibc: https://www.phoronix.com/news/Glibc-strcasecmp-AVX2-EVEX v4 level is adding AVX-512, which is far less established, particularly Intel has famously backtracked from supporting it in Alder Lake/Raport Lake client CPUs and AMD has only implemented it in very recent Zen4 products: https://www.phoronix.com/news/GCC-11-x86-64-Feature-Levels (From OE-Core rev: 6f2af1e5d1537b4d31e14946292bf58f0fd76fc9) Signed-off-by: Alexander Kanavin <alex@linutronix.de> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* conf/machine/include: add x86-64-v3 tunes (AVX, AVX2, BMI1, BMI2, F16C, FMA, ↵Alexander Kanavin2022-12-311-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LZCNT, MOVBE, XSAVE) Qemu 7.2 finally allows us to move beyond building for original Core 2/Core i7 era hardware, and this patch adds support for the newer generations. But first, a bit of background: Recently toolchains gained support for specifying x86-64 'levels' of instruction set support; v3 corresponds to 2013-era Haswell CPUs (and later), with AVX, AVX2 and a few other instructions that were introduced in that generation. I believe this is preferrable to picking a specific CPU model as the baseline. Here's Phoronix's feature article that explains the feature and the available levels: "Both LLVM Clang 12 and GCC 11 are ready to go in offering the new x86-64-v2, x86-64-v3, and x86-64-v4 targets. These x86_64 micro-architecture feature levels have been about coming up with a few "classes" of Intel/AMD CPU processor support rather than continuing to rely on just the x86_64 baseline or targeting a specific CPU family for optimizations. These new levels make it easier to raise the base requirements around Linux x86-64 whether it be for a Linux distribution or a particular software application where the developer/ISV may be wanting to compile with greater instruction set extensions enabled in catering to more recent Intel/AMD CPUs." https://www.phoronix.com/news/GCC-11-x86-64-Feature-Levels Here's gcc docs for it: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html And here's the formal specification (click on the pdf link): https://gitlab.com/x86-psABIs/x86-64-ABI The actual tune file was created by copying corei7 tunes and doing search/replace on them. Qemu options were dropped as unnecessary. 32 bit tune was dropped as well, as there is no 32 bit only CPU that also supports these new instructions; all of the v3 capable chips are 64 bit. (From OE-Core rev: ac041f90e71dba83b7144c91f929de88aaeae519) Signed-off-by: Alexander Kanavin <alex@linutronix.de> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-neoversen2: support tune-neoversen2 base on armv9aRuiqiang Hao2022-09-212-6/+32
| | | | | | | | | | | We supported neoversen2 base on armv8.5a in the past, add tune include for armv9a and support neoversen2 base on armv9a. (From OE-Core rev: 4a2c4cfaaa5a6d7175c81064939e21bcfe3e736a) Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* meta/conf: update preferred linux-yocto version to v5.19Bruce Ashfield2022-08-091-1/+1
| | | | | | | | | | v5.19 is the latest reference kernel, we bump our qemu machines to use it by default. (From OE-Core rev: 8f3b5cab696704fdc2060c710e3429859736a63a) Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* powerpc: Remove invalid GLIBC_EXTRA_OECONFRobert Joslyn2022-05-016-19/+0
| | | | | | | | | | | | | | | | | | | | OE-core previously carried patches to glibc that added optimized sqrt implementations for various PowerPC chips. These were recently removed, which now results in errors when compiling glibc with certian PowerPC machine tunes: checking sysdep dirs... configure: error: The 603e subspecies of powerpc is not supported. Remove setting GLIBC_EXTRA_OECONF with parameters that are no longer valid. Also remove a commented out setting of the variable that probably isn't vaild anyway. Fixes: 2511e937f445 ("glibc: Drop ppc sqrt optimisations") (From OE-Core rev: 40f15066c24720aae36713c9856ffb4fae146a45) Signed-off-by: Robert Joslyn <robert.joslyn@redrectangle.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-07-15 20:52:30 +0000