summaryrefslogtreecommitdiffstats
path: root/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch')
-rw-r--r--meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch2083
1 files changed, 2083 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch
new file mode 100644
index 0000000000..14b9e535e5
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-pcieqos.patch
@@ -0,0 +1,2083 @@
1
2
3From: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
4Subject: OKI Semiconductor PCH PCIEQOS driver
5
6This driver implements PCH PCIEQOS controls for PCH.
7
8Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
9Acked-by: Wang Qi <qi.wang@intel.com>
10
11---
12 drivers/char/Kconfig | 7++
13 drivers/char/Makefile | 1
14 drivers/char/pch_pcieqos/Makefile | 9
15 drivers/char/pch_pcieqos/pch_common.h | 146
16 driers/char/pch_pcieqos/pch_debug.h | 60
17 drivers/char/pch_pcieqos/pch_pcieqos.c | 392
18 drivers/char/pch_pcieqos/pch_pcieqos.h | 196
19 drivers/char/pch_pcieqos/pch_pcieqos_hal.c | 550
20 drivers/char/pch_pcieqos/pch_pcieqos_hal.h | 125
21 drivers/char/pch_pcieqos/pch_pcieqos_pci.c | 523
22+++++++++++++++++++++++++++++++ 10 files changed, 2009 insertions(+)
23diff -urN linux-2.6.33-rc3/drivers/char/Kconfig topcliff-2.6.33-rc3/drivers/char/Kconfig
24--- linux-2.6.33-rc3/drivers/char/Kconfig 2010-03-12 14:46:34.000000000 +0900
25+++ topcliff-2.6.33-rc3/drivers/char/Kconfig 2010-03-09 10:14:52.000000000 +0900
26@@ -11,6 +11,13 @@
27 If you say yes to this option, support will be included for the
28 PCH IEEE1588 Host controller.
29
30+config PCH_PCIEQOS
31+ tristate "PCH PCIEQOS"
32+ depends on PCI
33+ help
34+ If you say yes to this option, support will be included for the
35+ PCH PCIEQOS Host controller.
36+
37 config VT
38 bool "Virtual terminal" if EMBEDDED
39 depends on !S390
40diff -urN linux-2.6.33-rc3/drivers/char/Makefile topcliff-2.6.33-rc3/drivers/char/Makefile
41--- linux-2.6.33-rc3/drivers/char/Makefile 2010-03-12 14:46:34.000000000 +0900
42+++ topcliff-2.6.33-rc3/drivers/char/Makefile 2010-03-05 22:57:39.000000000 +0900
43@@ -112,6 +112,7 @@
44 js-rtc-y = rtc.o
45
46 obj-$(CONFIG_PCH_IEEE1588) += pch_ieee1588/
47+obj-$(CONFIG_PCH_PCIEQOS) += pch_pcieqos/
48
49 # Files generated that shall be removed upon make clean
50 clean-files := consolemap_deftbl.c defkeymap.c
51diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/Makefile topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/Makefile
52--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/Makefile 1970-01-01 09:00:00.000000000 +0900
53+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/Makefile 2010-03-09 09:15:41.000000000 +0900
54@@ -0,0 +1,9 @@
55+ifeq ($(CONFIG_PCIEQOS_DEBUG),y)
56+EXTRA_CFLAGS += -DDEBUG
57+endif
58+
59+obj-$(CONFIG_PCH_PCIEQOS) += pch_pcieqos_drv.o
60+#to set CAN clock to 50Mhz
61+EXTRA_CFLAGS+=-DIOH_CAN_PCLK_50MHZ
62+
63+pch_pcieqos_drv-objs := pch_pcieqos.o pch_pcieqos_pci.o pch_pcieqos_hal.o
64diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_common.h topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_common.h
65--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_common.h 1970-01-01 09:00:00.000000000 +0900
66+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_common.h 2010-03-09 05:56:11.000000000 +0900
67@@ -0,0 +1,146 @@
68+/*!
69+ * @file ioh_common.h
70+ * @brief Provides the macro definitions used by all files.
71+ * @version 1.0.0.0
72+ * @section
73+ * This program is free software; you can redistribute it and/or modify
74+ * it under the terms of the GNU General Public License as published by
75+ * the Free Software Foundation; version 2 of the License.
76+ *
77+ * This program is distributed in the hope that it will be useful,
78+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
79+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
80+ * GNU General Public License for more details.
81+ *
82+ * You should have received a copy of the GNU General Public License
83+ * along with this program; if not, write to the Free Software
84+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
85+ */
86+
87+/*
88+ * History:
89+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
90+ * All rights reserved.
91+ *
92+ * created:
93+ * WIPRO 03/07/2009
94+ * modified:
95+ * WIPRO 05/08/2009
96+ *
97+ */
98+
99+#ifndef __IOH_COMMON_H__
100+#define __IOH_COMMON_H__
101+
102+/*! @ingroup Global
103+@def IOH_WRITE8
104+@brief Macro for writing 8 bit data to an io/mem address
105+*/
106+#define IOH_WRITE8(val, addr) iowrite8((val), (void __iomem *)(addr))
107+/*! @ingroup Global
108+@def IOH_LOG
109+@brief Macro for writing 16 bit data to an io/mem address
110+*/
111+#define IOH_WRITE16(val, addr) iowrite16((val), (void __iomem *)(addr))
112+/*! @ingroup Global
113+@def IOH_LOG
114+@brief Macro for writing 32 bit data to an io/mem address
115+*/
116+#define IOH_WRITE32(val, addr) iowrite32((val), (void __iomem *)(addr))
117+
118+/*! @ingroup Global
119+@def IOH_READ8
120+@brief Macro for reading 8 bit data from an io/mem address
121+*/
122+#define IOH_READ8(addr) ioread8((void __iomem *)(addr))
123+/*! @ingroup Global
124+@def IOH_READ16
125+@brief Macro for reading 16 bit data from an io/mem address
126+*/
127+#define IOH_READ16(addr) ioread16((void __iomem *)(addr))
128+/*! @ingroup Global
129+@def IOH_READ32
130+@brief Macro for reading 32 bit data from an io/mem address
131+*/
132+#define IOH_READ32(addr) ioread32((void __iomem *)(addr))
133+/*! @ingroup Global
134+@def IOH_WRITE32_F
135+@brief Macro for writing 32 bit data to an io/mem address
136+*/
137+#define IOH_WRITE32_F(val, addr) do \
138+ { IOH_WRITE32((val), (addr)); (void)IOH_READ32((addr)); } while (0);
139+
140+/*! @ingroup Global
141+@def IOH_WRITE_BYTE
142+@brief Macro for writing 1 byte data to an io/mem address
143+*/
144+#define IOH_WRITE_BYTE IOH_WRITE8
145+/*! @ingroup Global
146+@def IOH_WRITE_WORD
147+@brief Macro for writing 1 word data to an io/mem address
148+*/
149+#define IOH_WRITE_WORD IOH_WRITE16
150+/*! @ingroup Global
151+@def IOH_WRITE_LONG
152+@brief Macro for writing long data to an io/mem address
153+*/
154+#define IOH_WRITE_LONG IOH_WRITE32
155+
156+/*! @ingroup Global
157+@def IOH_READ_BYTE
158+@brief Macro for reading 1 byte data from an io/mem address
159+*/
160+#define IOH_READ_BYTE IOH_READ8
161+/*! @ingroup Global
162+@def IOH_READ_WORD
163+@brief Macro for reading 1 word data from an io/mem address
164+*/
165+#define IOH_READ_WORD IOH_READ16
166+/*! @ingroup Global
167+@def IOH_READ_LONG
168+@brief Macro for reading long data from an io/mem address
169+*/
170+#define IOH_READ_LONG IOH_READ32
171+
172+/* Bit Manipulation Macros */
173+
174+/*! @ingroup Global
175+@def IOH_READ_LONG
176+@brief macro to set a specified bit(mask) at the
177+ specified address
178+*/
179+#define IOH_SET_ADDR_BIT(addr, bitmask) IOH_WRITE_LONG((IOH_READ_LONG(addr) |\
180+ (bitmask)), (addr))
181+
182+/*! @ingroup Global
183+@def IOH_READ_LONG
184+@brief macro to clear a specified bit(mask) at the specified address
185+*/
186+#define IOH_CLR_ADDR_BIT(addr, bitmask) IOH_WRITE_LONG((IOH_READ_LONG(addr) &\
187+ ~(bitmask)), (addr))
188+
189+/*! @ingroup Global
190+@def IOH_READ_LONG
191+@brief macro to set a specified bitmask for a variable
192+*/
193+#define IOH_SET_BITMSK(var, bitmask) ((var) |= (bitmask))
194+
195+/*! @ingroup Global
196+@def IOH_READ_LONG
197+@brief macro to clear a specified bitmask for a variable
198+*/
199+#define IOH_CLR_BITMSK(var, bitmask) ((var) &= (~(bitmask)))
200+
201+/*! @ingroup Global
202+@def IOH_READ_LONG
203+@brief macro to set a specified bit for a variable
204+*/
205+#define IOH_SET_BIT(var, bit) ((var) |= (1<<(bit)))
206+
207+/*! @ingroup Global
208+@def IOH_READ_LONG
209+@brief macro to clear a specified bit for a variable
210+*/
211+#define IOH_CLR_BIT(var, bit) ((var) &= ~(1<<(bit)))
212+
213+#endif
214diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_debug.h topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_debug.h
215--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_debug.h 1970-01-01 09:00:00.000000000 +0900
216+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_debug.h 2010-03-09 05:37:47.000000000 +0900
217@@ -0,0 +1,60 @@
218+/*!
219+ * @file ioh_debug.h
220+ * @brief Provides the macro definitions used for debugging.
221+ * @version 1.0.0.0
222+ * @section
223+ * This program is free software; you can redistribute it and/or modify
224+ * it under the terms of the GNU General Public License as published by
225+ * the Free Software Foundation; version 2 of the License.
226+ *
227+ * This program is distributed in the hope that it will be useful,
228+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
229+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
230+ * GNU General Public License for more details.
231+ *
232+ * You should have received a copy of the GNU General Public License
233+ * along with this program; if not, write to the Free Software
234+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
235+ */
236+
237+/*
238+ * History:
239+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
240+ * All rights reserved.
241+ *
242+ * created:
243+ * WIPRO 03/07/2009
244+ * modified:
245+ * WIPRO 05/08/2009
246+ *
247+ */
248+
249+#ifndef __IOH_DEBUG_H__
250+#define __IOH_DEBUG_H__
251+
252+#ifdef MODULE
253+#define IOH_LOG(level, fmt, args...) printk(level "%s:" fmt "\n",\
254+ THIS_MODULE->name, ##args)
255+#else
256+#define IOH_LOG(level, fmt, args...) printk(level "%s:" fmt "\n" ,\
257+ __FILE__, ##args)
258+#endif
259+
260+
261+#ifdef DEBUG
262+ #define IOH_DEBUG(fmt, args...) IOH_LOG(KERN_DEBUG, fmt, ##args)
263+#else
264+ #define IOH_DEBUG(fmt, args...)
265+#endif
266+
267+#ifdef IOH_TRACE_ENABLED
268+ #define IOH_TRACE IOH_DEBUG
269+#else
270+ #define IOH_TRACE(fmt, args...)
271+#endif
272+
273+#define IOH_TRACE_ENTER IOH_TRACE("Enter %s", __func__)
274+#define IOH_TRACE_EXIT IOH_TRACE("Exit %s", __func__)
275+
276+
277+#endif
278diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.c topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.c
279--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.c 1970-01-01 09:00:00.000000000 +0900
280+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.c 2010-03-12 14:16:44.000000000 +0900
281@@ -0,0 +1,392 @@
282+/*!
283+ * @file ioh_pcieqos.c
284+ * @brief Provides all the implementation of the interfaces pertaining to the PCIEQOS module.
285+ * @version 1.0.0.0
286+ * @section
287+ * This program is free software; you can redistribute it and/or modify
288+ * it under the terms of the GNU General Public License as published by
289+ * the Free Software Foundation; version 2 of the License.
290+ *
291+ * This program is distributed in the hope that it will be useful,
292+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
293+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
294+ * GNU General Public License for more details.
295+ *
296+ * You should have received a copy of the GNU General Public License
297+ * along with this program; if not, write to the Free Software
298+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
299+ */
300+
301+/*
302+ * History:
303+ * Copyright (C) 2009 OKI SEMICONDUCTOR Co., LTD.
304+ * All rights reserved.
305+ *
306+ * created:
307+ * OKI SEMICONDUCTOR 06/20/2009
308+ * modified:
309+ *
310+ */
311+
312+/* includes */
313+
314+#include <linux/module.h>
315+#include <linux/kernel.h>
316+#include <linux/types.h>
317+#include <linux/fs.h>
318+#include <linux/uaccess.h>
319+#include <linux/string.h>
320+
321+#include "pch_common.h"
322+#include "pch_debug.h"
323+#include "pch_pcieqos.h"
324+#include "pch_pcieqos_hal.h"
325+
326+#define MODULE_NAME "pch_pcieqos"
327+
328+/* global variables */
329+s32 ioh_pcieqos_opencount; /* check whether opened or not */
330+
331+DEFINE_SPINLOCK(ioh_pcieqos_lock); /* for spin lock */
332+
333+/**
334+ * file_operations structure initialization
335+ */
336+const struct file_operations ioh_pcieqos_fops = {
337+ .owner = THIS_MODULE,
338+ .open = ioh_pcieqos_open,
339+ .release = ioh_pcieqos_release,
340+ .ioctl = ioh_pcieqos_ioctl,
341+};
342+
343+/*function implementations*/
344+
345+/*! @ingroup PCIEQOS_InterfaceLayerAPI
346+ @fn int ioh_pcieqos_open( struct inode *inode,struct file *file)
347+ @remarks Implements the Initializing and opening of the pcieqos module.
348+ @param inode [@ref INOUT] Contains the reference of the inode
349+ structure
350+ @param file [@ref INOUT] Contains the reference of the file structure
351+ @retval returnvalue [@ref OUT] contains the result for the concerned
352+ attempt.
353+ The result would generally comprise of success code
354+ or failure code. The failure code will indicate reason for
355+ failure.
356+ @see
357+ EBUSY
358+ */
359+int ioh_pcieqos_open(struct inode *inode, struct file *file)
360+{
361+ int ret;
362+
363+ spin_lock(&ioh_pcieqos_lock);
364+ IOH_DEBUG("ioh_pcieqos_open : open count value = %d",
365+ ioh_pcieqos_opencount);
366+ if (ioh_pcieqos_opencount) {
367+ IOH_LOG(KERN_ERR,
368+ "ioh_pcieqos_open : device already opened\n");
369+ ret = -EBUSY;
370+ } else {
371+ ioh_pcieqos_opencount++;
372+ ret = IOH_PCIEQOS_SUCCESS;
373+ }
374+ spin_unlock(&ioh_pcieqos_lock);
375+
376+ IOH_DEBUG("ioh_pcieqos_open returns=%d\n", ret);
377+ return ret;
378+}
379+
380+/*! @ingroup PCIEQOS_InterfaceLayerAPI
381+ @fn int ioh_pcieqos_release(struct inode *inode,struct file *file)
382+ @remarks Implements the release functionality of the pcieqos module.
383+ @param inode [@ref INOUT] Contains the reference of the inode
384+ structure
385+ @param file [@ref INOUT] Contains the reference of the file structure
386+ @retval returnvalue [@ref OUT] contains the result for the concerned
387+ attempt.
388+ The result would generally comprise of success code
389+ or failure code. The failure code will indicate reason for
390+ failure.
391+ @see
392+ SUCCESS
393+ */
394+int ioh_pcieqos_release(struct inode *inode, struct file *file)
395+{
396+ spin_lock(&ioh_pcieqos_lock);
397+
398+ if (ioh_pcieqos_opencount > 0)
399+ ioh_pcieqos_opencount--;
400+ spin_unlock(&ioh_pcieqos_lock);
401+
402+ IOH_DEBUG("ioh_pcieqos_release : ioh_pcieqos_opencount =%d\n",
403+ ioh_pcieqos_opencount);
404+
405+ IOH_DEBUG("ioh_pcieqos_release returning=%d\n", IOH_PCIEQOS_SUCCESS);
406+ return IOH_PCIEQOS_SUCCESS;
407+}
408+
409+/*! @ingroup PCIEQOS_InterfaceLayerAPI
410+ @fn int ioh_pcieqos_ioctl(struct inode * inode,struct file * file,
411+ unsigned int cmd,unsigned long arg)
412+ @remarks Implements the various ioctl functionalities of the pcieqos module.
413+ @param inode [@ref INOUT] Contains the reference of the inode
414+ structure
415+ @param file [@ref INOUT] Contains the reference of the file structure
416+ @param cmd [@ref IN] Contains the command value
417+ @param arg [@ref IN] Contains the command argument value
418+ @retval returnvalue [@ref OUT] contains the result for the concerned
419+ attempt.
420+ The result would generally comprise of success code
421+ or failure code. The failure code will indicate reason for
422+ failure.
423+ @see
424+ EINVAL
425+ EFAULT
426+ */
427+int ioh_pcieqos_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
428+ unsigned long arg)
429+{
430+
431+ int ret_value = IOH_PCIEQOS_SUCCESS;
432+ struct ioh_pcieqos_reqt *p_ioh_pcieqos_reqt;
433+ unsigned long addr_offset;
434+ unsigned long data;
435+ unsigned long mask;
436+
437+ do {
438+ if (ioh_pcieqos_suspended == true) {
439+ IOH_LOG(KERN_ERR,
440+ "ioh_pcieqos_ioctl : suspend initiated\
441+ returning =%d\n",
442+ IOH_PCIEQOS_FAIL);
443+ ret_value = IOH_PCIEQOS_FAIL;
444+ break;
445+ }
446+
447+ p_ioh_pcieqos_reqt = (struct ioh_pcieqos_reqt *)arg;
448+ ret_value =
449+ copy_from_user((void *)&addr_offset,
450+ (void *)&p_ioh_pcieqos_reqt->addr_offset,
451+ sizeof(addr_offset));
452+ if (ret_value) {
453+ IOH_LOG(KERN_ERR,
454+ "ioh_pcieqos_ioctl : copy_from_user fail\
455+ returning =%d\n",
456+ -EFAULT);
457+ ret_value = -EFAULT;
458+ break;
459+ }
460+ IOH_DEBUG("ioh_pcieqos_ioctl : copy_from_user returns =%d\n",
461+ ret_value);
462+
463+ switch (cmd) {
464+ case IOCTL_PCIEQOS_READ_REG:
465+ {
466+
467+ ioh_pcieqos_read_reg(addr_offset, &data);
468+ IOH_DEBUG
469+ ("ioh_pcieqos_ioctl : Invoked\
470+ ioh_pcieqos_read_reg successfully\n");
471+
472+ ret_value =
473+ copy_to_user((void *)&p_ioh_pcieqos_reqt->
474+ data, (void *)&data,
475+ sizeof(data));
476+ if (ret_value) {
477+ IOH_LOG(KERN_ERR,
478+ "ioh_pcieqos_ioctl :\
479+ copy_to_user fail returning =%d\n",
480+ -EFAULT);
481+ ret_value = -EFAULT;
482+ break;
483+ }
484+ break;
485+ }
486+
487+ case IOCTL_PCIEQOS_WRITE_REG:
488+ {
489+
490+ ret_value =
491+ copy_from_user((void *)&data,
492+ (void *)&p_ioh_pcieqos_reqt->
493+ data, sizeof(data));
494+ if (ret_value) {
495+ IOH_LOG(KERN_ERR,
496+ "ioh_pcieqos_ioctl :\
497+ copy_from_user fail returning =%d\n",
498+ -EFAULT);
499+ ret_value = -EFAULT;
500+ break;
501+ }
502+ ioh_pcieqos_write_reg(addr_offset, data);
503+ IOH_DEBUG
504+ ("ioh_pcieqos_ioctl : Invoked\
505+ ioh_pcieqos_write_reg successfully\n");
506+ break;
507+ }
508+
509+ case IOCTL_PCIEQOS_READ_MODIFY_WRITE_REG:
510+ {
511+
512+ ret_value =
513+ copy_from_user((void *)&data,
514+ (void *)&p_ioh_pcieqos_reqt->
515+ data, sizeof(data));
516+ if (ret_value) {
517+ IOH_LOG(KERN_ERR,
518+ "ioh_pcieqos_ioctl :\
519+ copy_from_user fail returning =%d\n",
520+ -EFAULT);
521+ ret_value = -EFAULT;
522+ break;
523+ }
524+ ret_value =
525+ copy_from_user((void *)&mask,
526+ (void *)&p_ioh_pcieqos_reqt->
527+ mask, sizeof(mask));
528+ if (ret_value) {
529+ IOH_LOG(KERN_ERR,
530+ "ioh_pcieqos_ioctl :\
531+ copy_from_user fail returning =%d\n",
532+ -EFAULT);
533+ ret_value = -EFAULT;
534+ break;
535+ }
536+ ioh_pcieqos_read_modify_write_reg(addr_offset,
537+ data, mask);
538+ IOH_DEBUG
539+ ("ioh_pcieqos_ioctl : Invoked\
540+ ioh_pcieqos_read_modify_write_reg successfully\n");
541+ break;
542+ }
543+
544+ case IOCTL_PCIEQOS_READ_OROM:
545+ {
546+
547+ ret_value =
548+ ioh_pcieqos_read_serial_rom(addr_offset,
549+ (unsigned char *)&data);
550+ if (ret_value) {
551+ IOH_LOG(KERN_ERR,
552+ "ioh_pcieqos_ioctl :\
553+ Invoked ioh_pcieqos_read_serial_rom =%d\n",
554+ -EFAULT);
555+ ret_value = -EFAULT;
556+ break;
557+ } else {
558+ IOH_DEBUG
559+ ("ioh_pcieqos_ioctl :\
560+ Invoked ioh_pcieqos_read_serial_rom successfully\n");
561+ }
562+
563+ ret_value =
564+ copy_to_user((void *)&p_ioh_pcieqos_reqt->
565+ data, (void *)&data,
566+ sizeof(data));
567+ if (ret_value) {
568+ IOH_LOG(KERN_ERR,
569+ "ioh_pcieqos_ioctl :\
570+ copy_to_user fail returning =%d\n",
571+ -EFAULT);
572+ ret_value = -EFAULT;
573+ break;
574+ }
575+ break;
576+ }
577+
578+ case IOCTL_PCIEQOS_WRITE_OROM:
579+ {
580+
581+ ret_value =
582+ copy_from_user((void *)&data,
583+ (void *)&p_ioh_pcieqos_reqt->
584+ data, sizeof(data));
585+ if (ret_value) {
586+ IOH_LOG(KERN_ERR,
587+ "ioh_pcieqos_ioctl :\
588+ copy_from_user fail returning =%d\n",
589+ -EFAULT);
590+ ret_value = -EFAULT;
591+ break;
592+ }
593+ ret_value =
594+ ioh_pcieqos_write_serial_rom(addr_offset,
595+ data);
596+ if (ret_value) {
597+ IOH_LOG(KERN_ERR,
598+ "ioh_pcieqos_ioctl :\
599+ Invoked ioh_pcieqos_write_serial_rom =%d\n",
600+ -EFAULT);
601+ ret_value = -EFAULT;
602+ break;
603+ } else {
604+ IOH_DEBUG
605+ ("ioh_pcieqos_ioctl :\
606+ Invoked ioh_pcieqos_write_serial_rom successfully\n");
607+ }
608+ break;
609+ }
610+
611+ case IOCTL_PCIEQOS_READ_MAC_ADDR:
612+ {
613+
614+ ioh_pcieqos_read_gbe_mac_addr(addr_offset,
615+ (unsigned char *)&data);
616+ IOH_DEBUG
617+ ("ioh_pcieqos_ioctl : Invoked\
618+ ioh_pcieqos_read_gbe_mac_addr successfully\n");
619+
620+ ret_value =
621+ copy_to_user((void *)&p_ioh_pcieqos_reqt->
622+ data, (void *)&data,
623+ sizeof(data));
624+ if (ret_value) {
625+ IOH_LOG(KERN_ERR,
626+ "ioh_pcieqos_ioctl :\
627+ copy_to_user fail returning =%d\n",
628+ -EFAULT);
629+ ret_value = -EFAULT;
630+ break;
631+ }
632+ break;
633+ }
634+
635+ case IOCTL_PCIEQOS_WRITE_MAC_ADDR:
636+ {
637+
638+ ret_value =
639+ copy_from_user((void *)&data,
640+ (void *)&p_ioh_pcieqos_reqt->
641+ data, sizeof(data));
642+ if (ret_value) {
643+ IOH_LOG(KERN_ERR,
644+ "ioh_pcieqos_ioctl :\
645+ copy_from_user fail returning =%d\n",
646+ -EFAULT);
647+ ret_value = -EFAULT;
648+ break;
649+ }
650+ ioh_pcieqos_write_gbe_mac_addr(addr_offset,
651+ data);
652+ IOH_DEBUG
653+ ("ioh_pcieqos_ioctl : Invoked\
654+ ioh_pcieqos_write_gbe_mac_addr successfully\n");
655+ break;
656+ }
657+
658+ default:
659+ {
660+ IOH_LOG(KERN_ERR,
661+ "ioh_write_ioctl invalid command\
662+ returning=%d\n",
663+ -EINVAL);
664+ ret_value = -EINVAL;
665+ break;
666+ }
667+ }
668+ break;
669+
670+ } while (0);
671+ IOH_LOG(KERN_ERR, "ioh_write_ioctl returns=%d\n", ret_value);
672+ return ret_value;
673+}
674diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.h topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.h
675--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.h 1970-01-01 09:00:00.000000000 +0900
676+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos.h 2010-03-08 12:14:32.000000000 +0900
677@@ -0,0 +1,196 @@
678+#ifndef __IOH_PCIEQOS_H__
679+#define __IOH_PCIEQOS_H__
680+/*!
681+ * @file ioh_pcieqos.h
682+ * @brief Provides all the interfaces pertaining to the PCIEQOS module.
683+ * @version 1.0.0.0
684+ * @section
685+ * This program is free software; you can redistribute it and/or modify
686+ * it under the terms of the GNU General Public License as published by
687+ * the Free Software Foundation; version 2 of the License.
688+ *
689+ * This program is distributed in the hope that it will be useful,
690+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
691+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
692+ * GNU General Public License for more details.
693+ *
694+ * You should have received a copy of the GNU General Public License
695+ * along with this program; if not, write to the Free Software
696+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
697+ */
698+
699+/*
700+ * History:
701+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
702+ * All rights reserved.
703+ *
704+ * created:
705+ * OKI SEMICONDUCTOR 06/20/2009
706+ * modified:
707+ *
708+ */
709+
710+/*! @defgroup PCIEQOS */
711+/*! @defgroup PCIEQOS_Global Global
712+ @ingroup PCIEQOS */
713+/*! @defgroup PCIEQOS_GlobalGeneral General
714+ @ingroup PCIEQOS_Global */
715+/*! @defgroup PCIEQOS_GlobalResultCodes StatusCodes
716+ @ingroup PCIEQOS_Global */
717+/*! @defgroup PCIEQOS_InterfaceLayer InterfaceLayer
718+ @ingroup PCIEQOS */
719+/*! @defgroup PCIEQOS_InterfaceLayerAPI Providers
720+ @ingroup PCIEQOS_InterfaceLayer
721+ */
722+/*! @defgroup PCIEQOS_InterfaceLayerNotifyRoutines Notifiers
723+ @ingroup PCIEQOS_InterfaceLayer
724+ */
725+/*! @defgroup PCIEQOS_PCILayer PCILayer
726+ @ingroup PCIEQOS */
727+/*! @defgroup PCIEQOS_PCILayerAPI Providers
728+ @ingroup PCIEQOS_PCILayer
729+ */
730+/*! @defgroup PCIEQOS_PCILayerFacilitators Facilitators
731+ @ingroup PCIEQOS_PCILayer
732+ */
733+/*! @defgroup PCIEQOS_HALLayer HALLayer
734+ @ingroup PCIEQOS */
735+/*! @defgroup PCIEQOS_HALLayerAPI Providers
736+ @ingroup PCIEQOS_HALLayer
737+ */
738+/*! @defgroup PCIEQOS_HALLayerFacilitators Facilitators
739+ @ingroup PCIEQOS_HALLayer
740+ */
741+/*! @defgroup PCIEQOS_Utilities Utilities
742+ @ingroup PCIEQOS */
743+/*! @defgroup PCIEQOS_UtilitiesAPI Providers
744+ @ingroup PCIEQOS_Utilities
745+ */
746+
747+/*! @ingroup PCIEQOS_InterfaceLayer
748+ @def PCIEQOS_IOCTL_MAGIC
749+ @brief Outlines the ioctl magic.
750+ */
751+#define PCIEQOS_IOCTL_MAGIC (0xf7)
752+
753+/*! @ingroup PCIEQOS_InterfaceLayer
754+ @def IOCTL_PCIEQOS_READ_REG
755+ @brief Outlines the read register function signature.
756+ */
757+#define IOCTL_PCIEQOS_READ_REG (_IOW(PCIEQOS_IOCTL_MAGIC, 1, unsigned long))
758+
759+/*! @ingroup PCIEQOS_InterfaceLayer
760+ @def IOCTL_PCIEQOS_WRITE_REG
761+ @brief Outlines the write register function signature.
762+ */
763+#define IOCTL_PCIEQOS_WRITE_REG (_IOW(PCIEQOS_IOCTL_MAGIC, 2, unsigned long))
764+
765+/*! @ingroup PCIEQOS_InterfaceLayer
766+ @def IOCTL_PCIEQOS_READ_MODIFY_WRITE_REG
767+ @brief Outlines the read, modify and write register function signature.
768+ */
769+#define IOCTL_PCIEQOS_READ_MODIFY_WRITE_REG (_IOW(PCIEQOS_IOCTL_MAGIC, 3,\
770+ unsigned long))
771+
772+/*! @ingroup PCIEQOS_InterfaceLayer
773+ @def IOCTL_PCIEQOS_READ_OROM
774+ @brief Outlines the read option rom function signature.
775+ */
776+#define IOCTL_PCIEQOS_READ_OROM (_IOW(PCIEQOS_IOCTL_MAGIC, 4, unsigned long))
777+
778+/*! @ingroup PCIEQOS_InterfaceLayer
779+ @def IOCTL_PCIEQOS_WRITE_OROM
780+ @brief Outlines the write option rom function signature.
781+ */
782+#define IOCTL_PCIEQOS_WRITE_OROM (_IOW(PCIEQOS_IOCTL_MAGIC, 5, unsigned long))
783+
784+/*! @ingroup PCIEQOS_InterfaceLayer
785+ @def IOCTL_PCIEQOS_READ_MAC_ADDR
786+ @brief Outlines the read mac address function signature.
787+ */
788+#define IOCTL_PCIEQOS_READ_MAC_ADDR (_IOW(PCIEQOS_IOCTL_MAGIC, 6,\
789+ unsigned long))
790+
791+/*! @ingroup PCIEQOS_InterfaceLayer
792+ @def IOCTL_PCIEQOS_WRITE_MAC_ADDR
793+ @brief Outlines the write mac address function signature.
794+ */
795+#define IOCTL_PCIEQOS_WRITE_MAC_ADDR (_IOW(PCIEQOS_IOCTL_MAGIC, 7,\
796+ unsigned long))
797+
798+/*! @ingroup PCIEQOS_InterfaceLayer
799+ @def PCIEQOS STATUS CODE
800+ @brief Outlines PCIEQOS SUCCESS STATUS CODE
801+ */
802+#define IOH_PCIEQOS_SUCCESS (0)
803+
804+/*! @ingroup PCIEQOS_InterfaceLayer
805+ @def PCIEQOS STATUS CODE
806+ @brief Outlines PCIEQOS ERROR STATUS CODE
807+ */
808+#define IOH_PCIEQOS_FAIL (-1)
809+
810+/* Registers address offset */
811+#define IOH_PCIEQOS_PHUB_ID_REG (0x0000)
812+#define IOH_PCIEQOS_QUEUE_PRI_VAL_REG (0x0004)
813+#define IOH_PCIEQOS_RC_QUEUE_MAXSIZE_REG (0x0008)
814+#define IOH_PCIEQOS_BRI_QUEUE_MAXSIZE_REG (0x000C)
815+#define IOH_PCIEQOS_COMP_RESP_TIMEOUT_REG (0x0010)
816+#define IOH_PCIEQOS_BUS_SLAVE_CONTROL_REG (0x0014)
817+#define IOH_PCIEQOS_DEADLOCK_AVOID_TYPE_REG (0x0018)
818+#define IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG0 (0x0020)
819+#define IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG1 (0x0024)
820+#define IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG2 (0x0028)
821+#define IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG3 (0x002C)
822+#define IOH_PCIEQOS_INT_REDUCE_CONTROL_REG_BASE (0x0040)
823+#define CLKCFG_REG_OFFSET (0x500)
824+
825+/*structures*/
826+/*! @ingroup PCIEQOS_InterfaceLayer
827+ @struct ioh_pcieqos_reqt
828+ @brief It is a structure used for perserving information related to the
829+ pcieqos request.
830+ @note
831+ The concerned details should be provided during the read register,
832+ write register and read / modify / write register.
833+ @see
834+ ioh_pcieqos_ioctl
835+ */
836+struct ioh_pcieqos_reqt {
837+ unsigned long addr_offset; /*specifies the register address
838+ offset */
839+ unsigned long data; /*specifies the data */
840+ unsigned long mask; /*specifies the mask */
841+};
842+
843+/* exported function prototypes */
844+/*! @ingroup PCIEQOS_InterfaceLayerAPI
845+ @fn nt ioh_pcieqos_open( struct inode *inode,struct file *file )
846+ @brief Provides the functionality of initialization of the module
847+ */
848+int ioh_pcieqos_open(struct inode *inode, struct file *file);
849+
850+/*! @ingroup PCIEQOS_InterfaceLayerAPI
851+ @fn int ioh_pcieqos_release(struct inode *inode,struct file *file)
852+ @brief Provides the functionality of releasing the module
853+ */
854+int ioh_pcieqos_release(struct inode *inode, struct file *file);
855+
856+/*! @ingroup PCIEQOS_InterfaceLayerAPI
857+ @fn int ioh_pcieqos_ioctl(struct inode * inode,struct file * file,
858+ unsigned int cmd,
859+ unsigned long arg)
860+ @brief Provides the functionality of invoking various functionalities of
861+ the PCIEQOS.
862+ */
863+int ioh_pcieqos_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
864+ unsigned long arg);
865+
866+/**global variables*/
867+extern u32 ioh_pcieqos_base_address; /* base address */
868+extern s32 ioh_pcieqos_suspended; /* suspend status */
869+
870+extern s32 ioh_pcieqos_opencount;
871+extern spinlock_t ioh_pcieqos_lock;
872+extern const struct file_operations ioh_pcieqos_fops;
873+#endif
874diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.c topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.c
875--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.c 1970-01-01 09:00:00.000000000 +0900
876+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.c 2010-03-08 17:51:33.000000000 +0900
877@@ -0,0 +1,550 @@
878+/*!
879+ * @file ioh_pcieqos_hal.c
880+ * @brief Provides all the implementation of the interfaces pertaining to the
881+ * HAL.
882+ * @version 1.0.0.0
883+ * @section
884+ * This program is free software; you can redistribute it and/or modify
885+ * it under the terms of the GNU General Public License as published by
886+ * the Free Software Foundation; version 2 of the License.
887+ *
888+ * This program is distributed in the hope that it will be useful,
889+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
890+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
891+ * GNU General Public License for more details.
892+ *
893+ * You should have received a copy of the GNU General Public License
894+ * along with this program; if not, write to the Free Software
895+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
896+ */
897+
898+/*
899+ * History:
900+ * Copyright (C) 2009 OKI SEMICONDUCTOR Co., LTD.
901+ * All rights reserved.
902+ *
903+ * created:
904+ * OKI SEMICONDUCTOR 06/20/2009
905+ * modified:
906+ *
907+ */
908+
909+/*includes*/
910+#include <linux/kernel.h>
911+#include <linux/module.h>
912+#include <linux/pci.h>
913+#include <linux/io.h>
914+#include <linux/delay.h>
915+#include "pch_common.h"
916+#include "pch_debug.h"
917+#include "pch_pcieqos.h"
918+#include "pch_pcieqos_hal.h"
919+
920+/* Status Register offset */
921+#define PCIEQOS_STATUS (0x00)
922+
923+/* Control Register offset */
924+#define PCIEQOS_CONTROL (0x04)
925+
926+/* Time out value for Status Register */
927+#define PCIEQOS_TIMEOUT (0x05)
928+
929+/* Enabling for writing ROM */
930+#define IOH_PCIEQOS_ROM_WRITE_ENABLE (0x01)
931+
932+/* Disabling for writing ROM */
933+#define IOH_PCIEQOS_ROM_WRITE_DISABLE (0x00)
934+
935+/* ROM data area start address offset */
936+#define IOH_PCIEQOS_ROM_START_ADDR (0x14)
937+
938+/* MAX number of INT_REDUCE_CONTROL registers */
939+#define MAX_NUM_INT_REDUCE_CONTROL_REG (128)
940+
941+/* global variables */
942+struct ioh_pcieqos_reg {
943+ u32 phub_id_reg; /* PHUB_ID register val */
944+ u32 q_pri_val_reg; /* QUEUE_PRI_VAL register val */
945+ u32 rc_q_maxsize_reg; /* RC_QUEUE_MAXSIZE register val */
946+ u32 bri_q_maxsize_reg; /* BRI_QUEUE_MAXSIZE register val */
947+ u32 comp_resp_timeout_reg; /* COMP_RESP_TIMEOUT register val */
948+ u32 bus_slave_control_reg; /* BUS_SLAVE_CONTROL_REG register val */
949+ u32 deadlock_avoid_type_reg; /* DEADLOCK_AVOID_TYPE register val */
950+ u32 intpin_reg_wpermit_reg0; /* INTPIN_REG_WPERMIT register 0 val */
951+ u32 intpin_reg_wpermit_reg1; /* INTPIN_REG_WPERMIT register 1 val */
952+ u32 intpin_reg_wpermit_reg2; /* INTPIN_REG_WPERMIT register 2 val */
953+ u32 intpin_reg_wpermit_reg3; /* INTPIN_REG_WPERMIT register 3 val */
954+ /* INT_REDUCE_CONTROL registers val */
955+ u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG];
956+#ifdef IOH_CAN_PCLK_50MHZ
957+ u32 clkcfg_reg; /* CLK CFG register val */
958+#endif
959+} g_ioh_pcieqos_reg;
960+
961+/*functions implementations*/
962+/*! @ingroup PCIEQOS_HALLayerAPI
963+ @fn void ioh_pcieqos_read_reg(unsigned long reg_addr_offset,
964+ unsigned long *data)
965+ @remarks Implements the functionality of reading register.
966+ @param reg_addr_offset [@ref IN] Contains the register offset address value
967+ @param *data [@ref INOUT] Contains the register value
968+ @retval NONE
969+ @see
970+ */
971+void ioh_pcieqos_read_reg(unsigned long reg_addr_offset, unsigned long *data)
972+{
973+ unsigned long reg_addr = ioh_pcieqos_base_address + reg_addr_offset;
974+ *data = IOH_READ32(reg_addr);
975+
976+ return;
977+}
978+
979+/*! @ingroup PCIEQOS_HALLayerAPI
980+ @fn void ioh_pcieqos_write_reg(unsigned long reg_addr_offset,
981+ unsigned long data)
982+ @remarks Implements the functionality of writing register.
983+ @param reg_addr_offset [@ref IN] Contains the register offset address value
984+ @param data [@ref IN] Contains the writing value
985+ @retval NONE
986+ @see
987+ */
988+void ioh_pcieqos_write_reg(unsigned long reg_addr_offset, unsigned long data)
989+{
990+ unsigned long reg_addr = ioh_pcieqos_base_address + reg_addr_offset;
991+ IOH_WRITE32(data, reg_addr);
992+
993+ return;
994+}
995+
996+/*! @ingroup PCIEQOS_HALLayerAPI
997+ @fn void ioh_pcieqos_read_modify_write_reg(unsigned long reg_addr_offset,
998+ unsigned long data, unsigned long mask)
999+ @remarks Implements the functionality of reading, modifying and writing
1000+ register.
1001+ @param reg_addr_offset [@ref IN] Contains the register offset address value
1002+ @param data [@ref IN] Contains the writing value
1003+ @param mask [@ref IN] Contains the mask value
1004+ @retval NONE
1005+ @see
1006+ */
1007+void ioh_pcieqos_read_modify_write_reg(unsigned long reg_addr_offset,
1008+ unsigned long data, unsigned long mask)
1009+{
1010+ unsigned long reg_addr = ioh_pcieqos_base_address + reg_addr_offset;
1011+ IOH_WRITE32(((IOH_READ32(reg_addr) & ~mask)) | data, reg_addr);
1012+
1013+ return;
1014+}
1015+
1016+/*! @ingroup PCIEQOS_HALLayerAPI
1017+ @fn int ioh_pcieqos_read_gbe_mac_addr(unsigned long offset_address,
1018+ unsigned char *data)
1019+ @param unsigned long offset_address [@ref IN] Contains the Gigabit
1020+ Ethernet MAC address offset value
1021+ @param *data [@ref INOUT] Contains the Gigabit
1022+ Ethernet MAC address value
1023+ @retval return value [@ref OUT] contains the result
1024+ for the reading Gigabit Ethernet MAC address attempt
1025+ @see
1026+ */
1027+int ioh_pcieqos_read_gbe_mac_addr(unsigned long offset_address,
1028+ unsigned char *data)
1029+{
1030+ int retval = IOH_PCIEQOS_SUCCESS;
1031+
1032+ retval = ioh_pcieqos_read_serial_rom_val(offset_address, data);
1033+
1034+ return retval;
1035+}
1036+EXPORT_SYMBOL(ioh_pcieqos_read_gbe_mac_addr);
1037+
1038+/*! @ingroup PCIEQOS_HALLayerAPI
1039+ @fn int ioh_pcieqos_write_gbe_mac_addr(unsigned long offset_address,
1040+ unsigned char data)
1041+ @param unsigned long offset_address [@ref IN] Contains the Gigabit
1042+ Ethernet MAC address offset value
1043+ @param data [@ref IN] Contains the Gigabit Ethernet
1044+ MAC address value
1045+ @retval return value [@ref OUT] contains the result for the
1046+ writing Gigabit Ethernet MAC address attempt
1047+ @see
1048+ */
1049+int ioh_pcieqos_write_gbe_mac_addr(unsigned long offset_address,
1050+ unsigned char data)
1051+{
1052+ int retval = IOH_PCIEQOS_SUCCESS;
1053+
1054+ retval = ioh_pcieqos_gbe_serial_rom_conf();
1055+ retval |= ioh_pcieqos_write_serial_rom_val(offset_address, data);
1056+
1057+ return retval;
1058+}
1059+EXPORT_SYMBOL(ioh_pcieqos_write_gbe_mac_addr);
1060+
1061+/*! @ingroup PCIEQOS_HALLayerAPI
1062+ @fn void ioh_pcieqos_save_reg_conf(void)
1063+ @remarks saves register configuration
1064+ @param NONE
1065+ @retval NONE
1066+ @see
1067+ ioh_pcieqos_suspend
1068+ */
1069+void ioh_pcieqos_save_reg_conf(void)
1070+{
1071+ u32 base_addr = ioh_pcieqos_base_address;
1072+ u32 i = 0;
1073+
1074+ IOH_DEBUG("ioh_pcieqos_save_reg_conf ENTRY\n");
1075+ /* to store contents of PHUB_ID register */
1076+ g_ioh_pcieqos_reg.phub_id_reg =
1077+ IOH_READ32(base_addr + IOH_PCIEQOS_PHUB_ID_REG);
1078+ /* to store contents of QUEUE_PRI_VAL register */
1079+ g_ioh_pcieqos_reg.q_pri_val_reg =
1080+ IOH_READ32(base_addr + IOH_PCIEQOS_QUEUE_PRI_VAL_REG);
1081+ /* to store contents of RC_QUEUE_MAXSIZE register */
1082+ g_ioh_pcieqos_reg.rc_q_maxsize_reg =
1083+ IOH_READ32(base_addr + IOH_PCIEQOS_RC_QUEUE_MAXSIZE_REG);
1084+ /* to store contents of BRI_QUEUE_MAXSIZE register */
1085+ g_ioh_pcieqos_reg.bri_q_maxsize_reg =
1086+ IOH_READ32(base_addr + IOH_PCIEQOS_BRI_QUEUE_MAXSIZE_REG);
1087+ /* to store contents of COMP_RESP_TIMEOUT register */
1088+ g_ioh_pcieqos_reg.comp_resp_timeout_reg =
1089+ IOH_READ32(base_addr + IOH_PCIEQOS_COMP_RESP_TIMEOUT_REG);
1090+ /* to store contents of BUS_SLAVE_CONTROL_REG register */
1091+ g_ioh_pcieqos_reg.bus_slave_control_reg =
1092+ IOH_READ32(base_addr + IOH_PCIEQOS_BUS_SLAVE_CONTROL_REG);
1093+ /* to store contents of DEADLOCK_AVOID_TYPE register */
1094+ g_ioh_pcieqos_reg.deadlock_avoid_type_reg =
1095+ IOH_READ32(base_addr + IOH_PCIEQOS_DEADLOCK_AVOID_TYPE_REG);
1096+ /* to store contents of INTPIN_REG_WPERMIT register 0 */
1097+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0 =
1098+ IOH_READ32(base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG0);
1099+ /* to store contents of INTPIN_REG_WPERMIT register 1 */
1100+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1 =
1101+ IOH_READ32(base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG1);
1102+ /* to store contents of INTPIN_REG_WPERMIT register 2 */
1103+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2 =
1104+ IOH_READ32(base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG2);
1105+ /* to store contents of INTPIN_REG_WPERMIT register 3 */
1106+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3 =
1107+ IOH_READ32(base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG3);
1108+ IOH_DEBUG
1109+ ("ioh_pcieqos_save_reg_conf : g_ioh_pcieqos_reg.phub_id_reg=%x, \
1110+ g_ioh_pcieqos_reg.q_pri_val_reg=%x, \
1111+ g_ioh_pcieqos_reg.rc_q_maxsize_reg=%x, \
1112+ g_ioh_pcieqos_reg.bri_q_maxsize_reg=%x, \
1113+ g_ioh_pcieqos_reg.comp_resp_timeout_reg=%x, \
1114+ g_ioh_pcieqos_reg.bus_slave_control_reg=%x, \
1115+ g_ioh_pcieqos_reg.deadlock_avoid_type_reg=%x, \
1116+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0=%x, \
1117+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1=%x, \
1118+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2=%x, \
1119+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3=%x\n",
1120+ g_ioh_pcieqos_reg.phub_id_reg,
1121+ g_ioh_pcieqos_reg.q_pri_val_reg,
1122+ g_ioh_pcieqos_reg.rc_q_maxsize_reg,
1123+ g_ioh_pcieqos_reg.bri_q_maxsize_reg,
1124+ g_ioh_pcieqos_reg.comp_resp_timeout_reg,
1125+ g_ioh_pcieqos_reg.bus_slave_control_reg,
1126+ g_ioh_pcieqos_reg.deadlock_avoid_type_reg,
1127+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0,
1128+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1,
1129+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2,
1130+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3);
1131+ /* to store contents of INT_REDUCE_CONTROL registers */
1132+ for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
1133+ g_ioh_pcieqos_reg.int_reduce_control_reg[i] =
1134+ IOH_READ32(base_addr +
1135+ IOH_PCIEQOS_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
1136+ IOH_DEBUG
1137+ ("ioh_pcieqos_save_reg_conf : \
1138+ g_ioh_pcieqos_reg.int_reduce_control_reg[%d]=%x\n",
1139+ i, g_ioh_pcieqos_reg.int_reduce_control_reg[i]);
1140+ }
1141+#ifdef IOH_CAN_PCLK_50MHZ
1142+ /* save clk cfg register */
1143+ g_ioh_pcieqos_reg.clkcfg_reg =
1144+ IOH_READ32(base_addr + CLKCFG_REG_OFFSET);
1145+#endif
1146+ return;
1147+}
1148+
1149+/*! @ingroup PCIEQOS_HALLayerAPI
1150+ @fn void ioh_pcieqos_restore_reg_conf(void)
1151+ @remarks restore register configuration
1152+ @param NONE
1153+ @retval NONE
1154+ @see
1155+ ioh_pcieqos_resume
1156+ */
1157+void ioh_pcieqos_restore_reg_conf(void)
1158+{
1159+ u32 base_addr = ioh_pcieqos_base_address;
1160+ u32 i = 0;
1161+
1162+ IOH_DEBUG("ioh_pcieqos_restore_reg_conf ENTRY\n");
1163+ /* to store contents of PHUB_ID register */
1164+ IOH_WRITE32(g_ioh_pcieqos_reg.phub_id_reg,
1165+ base_addr + IOH_PCIEQOS_PHUB_ID_REG);
1166+ /* to store contents of QUEUE_PRI_VAL register */
1167+ IOH_WRITE32(g_ioh_pcieqos_reg.q_pri_val_reg,
1168+ base_addr + IOH_PCIEQOS_QUEUE_PRI_VAL_REG);
1169+ /* to store contents of RC_QUEUE_MAXSIZE register */
1170+ IOH_WRITE32(g_ioh_pcieqos_reg.rc_q_maxsize_reg,
1171+ base_addr + IOH_PCIEQOS_RC_QUEUE_MAXSIZE_REG);
1172+ /* to store contents of BRI_QUEUE_MAXSIZE register */
1173+ IOH_WRITE32(g_ioh_pcieqos_reg.bri_q_maxsize_reg,
1174+ base_addr + IOH_PCIEQOS_BRI_QUEUE_MAXSIZE_REG);
1175+ /* to store contents of COMP_RESP_TIMEOUT register */
1176+ IOH_WRITE32(g_ioh_pcieqos_reg.comp_resp_timeout_reg,
1177+ base_addr + IOH_PCIEQOS_COMP_RESP_TIMEOUT_REG);
1178+ /* to store contents of BUS_SLAVE_CONTROL_REG register */
1179+ IOH_WRITE32(g_ioh_pcieqos_reg.bus_slave_control_reg,
1180+ base_addr + IOH_PCIEQOS_BUS_SLAVE_CONTROL_REG);
1181+ /* to store contents of DEADLOCK_AVOID_TYPE register */
1182+ IOH_WRITE32(g_ioh_pcieqos_reg.deadlock_avoid_type_reg,
1183+ base_addr + IOH_PCIEQOS_DEADLOCK_AVOID_TYPE_REG);
1184+ /* to store contents of INTPIN_REG_WPERMIT register 0 */
1185+ IOH_WRITE32(g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0,
1186+ base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG0);
1187+ /* to store contents of INTPIN_REG_WPERMIT register 1 */
1188+ IOH_WRITE32(g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1,
1189+ base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG1);
1190+ /* to store contents of INTPIN_REG_WPERMIT register 2 */
1191+ IOH_WRITE32(g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2,
1192+ base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG2);
1193+ /* to store contents of INTPIN_REG_WPERMIT register 3 */
1194+ IOH_WRITE32(g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3,
1195+ base_addr + IOH_PCIEQOS_INTPIN_REG_WPERMIT_REG3);
1196+ IOH_DEBUG
1197+ ("ioh_pcieqos_save_reg_conf : g_ioh_pcieqos_reg.phub_id_reg=%x, \
1198+ g_ioh_pcieqos_reg.q_pri_val_reg=%x, \
1199+ g_ioh_pcieqos_reg.rc_q_maxsize_reg=%x, \
1200+ g_ioh_pcieqos_reg.bri_q_maxsize_reg=%x, \
1201+ g_ioh_pcieqos_reg.comp_resp_timeout_reg=%x, \
1202+ g_ioh_pcieqos_reg.bus_slave_control_reg=%x, \
1203+ g_ioh_pcieqos_reg.deadlock_avoid_type_reg=%x, \
1204+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0=%x, \
1205+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1=%x, \
1206+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2=%x, \
1207+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3=%x\n",
1208+ g_ioh_pcieqos_reg.phub_id_reg, g_ioh_pcieqos_reg.q_pri_val_reg,
1209+ g_ioh_pcieqos_reg.rc_q_maxsize_reg,
1210+ g_ioh_pcieqos_reg.bri_q_maxsize_reg,
1211+ g_ioh_pcieqos_reg.comp_resp_timeout_reg,
1212+ g_ioh_pcieqos_reg.bus_slave_control_reg,
1213+ g_ioh_pcieqos_reg.deadlock_avoid_type_reg,
1214+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg0,
1215+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg1,
1216+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg2,
1217+ g_ioh_pcieqos_reg.intpin_reg_wpermit_reg3);
1218+ /* to store contents of INT_REDUCE_CONTROL register */
1219+ for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) {
1220+ IOH_WRITE32(g_ioh_pcieqos_reg.int_reduce_control_reg[i],
1221+ base_addr +
1222+ IOH_PCIEQOS_INT_REDUCE_CONTROL_REG_BASE + 4 * i);
1223+ IOH_DEBUG
1224+ ("ioh_pcieqos_save_reg_conf : \
1225+ g_ioh_pcieqos_reg.int_reduce_control_reg[%d]=%x\n",
1226+ i, g_ioh_pcieqos_reg.int_reduce_control_reg[i]);
1227+ }
1228+
1229+#ifdef IOH_CAN_PCLK_50MHZ
1230+ /*restore the clock config reg */
1231+ IOH_WRITE32(g_ioh_pcieqos_reg.clkcfg_reg,
1232+ base_addr + CLKCFG_REG_OFFSET);
1233+#endif
1234+
1235+ return;
1236+}
1237+
1238+/*! @ingroup PCIEQOS_HALLayerAPI
1239+ @fn void ioh_pcieqos_read_serial_rom(unsigned long offset_address,
1240+ unsigned char *data)
1241+ @remarks Implements the functionality of reading Serial ROM.
1242+ @param unsigned long offset_address [@ref IN] Contains the Serial ROM
1243+ address offset value
1244+ @param *data [@ref INOUT] Contains the Serial
1245+ ROM value
1246+ @retval returnvalue [@ref OUT] contains the result for the reading Serial
1247+ ROM attempt
1248+ @see
1249+ */
1250+int ioh_pcieqos_read_serial_rom(unsigned long offset_address,
1251+ unsigned char *data)
1252+{
1253+ unsigned long mem_addr =
1254+ ioh_pcieqos_extrom_base_address + offset_address;
1255+
1256+ IOH_DEBUG("ioh_pcieqos_read_serial_rom:mem_addr=0x%08x\n", mem_addr);
1257+ *data = IOH_READ8(mem_addr);
1258+
1259+ return IOH_PCIEQOS_SUCCESS;
1260+}
1261+
1262+/*! @ingroup PCIEQOS_HALLayerAPI
1263+ @fn void ioh_pcieqos_write_serial_rom(unsigned long offset_address,
1264+ unsigned char data)
1265+ @remarks Implements the functionality of writing Serial ROM.
1266+ @param unsigned long offset_address [@ref IN] Contains the Serial ROM
1267+ address offset value
1268+ @param data [@ref IN] Contains the Serial ROM value
1269+ @retval returnvalue [@ref OUT] contains the result for the writing Serial
1270+ ROM attempt
1271+ @see
1272+ */
1273+int ioh_pcieqos_write_serial_rom(unsigned long offset_address,
1274+ unsigned char data)
1275+{
1276+ int retval = IOH_PCIEQOS_SUCCESS;
1277+ unsigned long mem_addr =
1278+ ioh_pcieqos_extrom_base_address + offset_address;
1279+ int i = 0;
1280+ unsigned long word_data = 0;
1281+
1282+ IOH_DEBUG("ioh_pcieqos_write_serial_rom:mem_addr=0x%08x\n", mem_addr);
1283+ IOH_WRITE32(IOH_PCIEQOS_ROM_WRITE_ENABLE,
1284+ ioh_pcieqos_extrom_base_address + PCIEQOS_CONTROL);
1285+
1286+ word_data = IOH_READ32((mem_addr & 0xFFFFFFFC));
1287+ IOH_DEBUG("word_data=0x%08x\n", word_data);
1288+ IOH_DEBUG("data=0x%02x\n", data);
1289+ switch (mem_addr % 4) {
1290+ case 0:
1291+ {
1292+ word_data &= 0xFFFFFF00;
1293+ IOH_WRITE32((word_data | (unsigned long)data),
1294+ (mem_addr & 0xFFFFFFFC));
1295+ }
1296+ case 1:
1297+ {
1298+ word_data &= 0xFFFF00FF;
1299+ IOH_WRITE32((word_data | ((unsigned long)data << 8)),
1300+ (mem_addr & 0xFFFFFFFC));
1301+ }
1302+ case 2:
1303+ {
1304+ word_data &= 0xFF00FFFF;
1305+ IOH_WRITE32((word_data | ((unsigned long)data << 16)),
1306+ (mem_addr & 0xFFFFFFFC));
1307+ }
1308+ case 3:
1309+ {
1310+ word_data &= 0x00FFFFFF;
1311+ IOH_WRITE32((word_data | ((unsigned long)data << 24)),
1312+ (mem_addr & 0xFFFFFFFC));
1313+ }
1314+ }
1315+ while (0x00 !=
1316+ IOH_READ8(ioh_pcieqos_extrom_base_address + PCIEQOS_STATUS)) {
1317+ msleep(1);
1318+ if (PCIEQOS_TIMEOUT == i) {
1319+ retval = IOH_PCIEQOS_FAIL;
1320+ break;
1321+ }
1322+ i++;
1323+ }
1324+
1325+ IOH_WRITE32(IOH_PCIEQOS_ROM_WRITE_DISABLE,
1326+ ioh_pcieqos_extrom_base_address + PCIEQOS_CONTROL);
1327+
1328+ return retval;
1329+}
1330+
1331+/*! @ingroup PCIEQOS_HALLayerAPI
1332+ @fn void ioh_pcieqos_read_serial_rom_val(unsigned long offset_address,
1333+ unsigned char *data)
1334+ @remarks Implements the functionality of reading Serial ROM value.
1335+ @param unsigned long offset_address [@ref IN] Contains the Serial ROM
1336+ address offset value
1337+ @param *data [@ref INOUT] Contains the Serial
1338+ ROM value
1339+ @retval returnvalue [@ref OUT] contains the result for the reading Serial
1340+ ROM attempt
1341+ @see
1342+ */
1343+int ioh_pcieqos_read_serial_rom_val(unsigned long offset_address,
1344+ unsigned char *data)
1345+{
1346+ int retval = IOH_PCIEQOS_SUCCESS;
1347+ unsigned long mem_addr;
1348+
1349+ mem_addr =
1350+ (offset_address / 4 * 8) + 3 - (offset_address % 4) +
1351+ IOH_PCIEQOS_ROM_START_ADDR;
1352+ retval = ioh_pcieqos_read_serial_rom(mem_addr, data);
1353+
1354+ return retval;
1355+}
1356+
1357+/*! @ingroup PCIEQOS_HALLayerAPI
1358+ @fn void ioh_pcieqos_write_serial_rom_val(unsigned long offset_address,
1359+ unsigned char data)
1360+ @remarks Implements the functionality of writing Serial ROM value.
1361+ @param unsigned long offset_address [@ref IN] Contains the Serial ROM
1362+ address offset value
1363+ @param data [@ref IN] Contains the Serial ROM value
1364+ @retval returnvalue [@ref OUT] contains the result for the writing Serial
1365+ ROM attempt
1366+ @see
1367+ */
1368+int ioh_pcieqos_write_serial_rom_val(unsigned long offset_address,
1369+ unsigned char data)
1370+{
1371+ int retval = IOH_PCIEQOS_SUCCESS;
1372+ unsigned long mem_addr;
1373+
1374+ mem_addr =
1375+ (offset_address / 4 * 8) + 3 - (offset_address % 4) +
1376+ IOH_PCIEQOS_ROM_START_ADDR;
1377+ retval = ioh_pcieqos_write_serial_rom(mem_addr, data);
1378+
1379+ return retval;
1380+}
1381+
1382+/*! @ingroup PCIEQOS_HALLayerAPI
1383+ @fn int ioh_pcieqos_gbe_serial_rom_conf(void)
1384+ @remarks makes Serial ROM header format configuration for Gigabit Ethernet
1385+ MAC address
1386+ @param NONE
1387+ @retval returnvalue [@ref OUT] contains the result for the writing Serial
1388+ ROM attempt
1389+ @see
1390+ */
1391+int ioh_pcieqos_gbe_serial_rom_conf(void)
1392+{
1393+ int retval = IOH_PCIEQOS_SUCCESS;
1394+
1395+ retval |= ioh_pcieqos_write_serial_rom(0x0b, 0xbc);
1396+ retval |= ioh_pcieqos_write_serial_rom(0x0a, 0x10);
1397+ retval |= ioh_pcieqos_write_serial_rom(0x09, 0x01);
1398+ retval |= ioh_pcieqos_write_serial_rom(0x08, 0x02);
1399+
1400+ retval |= ioh_pcieqos_write_serial_rom(0x0f, 0x00);
1401+ retval |= ioh_pcieqos_write_serial_rom(0x0e, 0x00);
1402+ retval |= ioh_pcieqos_write_serial_rom(0x0d, 0x00);
1403+ retval |= ioh_pcieqos_write_serial_rom(0x0c, 0x80);
1404+
1405+ retval |= ioh_pcieqos_write_serial_rom(0x13, 0xbc);
1406+ retval |= ioh_pcieqos_write_serial_rom(0x12, 0x10);
1407+ retval |= ioh_pcieqos_write_serial_rom(0x11, 0x01);
1408+ retval |= ioh_pcieqos_write_serial_rom(0x10, 0x18);
1409+
1410+ retval |= ioh_pcieqos_write_serial_rom(0x1b, 0xbc);
1411+ retval |= ioh_pcieqos_write_serial_rom(0x1a, 0x10);
1412+ retval |= ioh_pcieqos_write_serial_rom(0x19, 0x01);
1413+ retval |= ioh_pcieqos_write_serial_rom(0x18, 0x19);
1414+
1415+ retval |= ioh_pcieqos_write_serial_rom(0x23, 0xbc);
1416+ retval |= ioh_pcieqos_write_serial_rom(0x22, 0x10);
1417+ retval |= ioh_pcieqos_write_serial_rom(0x21, 0x01);
1418+ retval |= ioh_pcieqos_write_serial_rom(0x20, 0x3a);
1419+
1420+ retval |= ioh_pcieqos_write_serial_rom(0x27, 0x01);
1421+ retval |= ioh_pcieqos_write_serial_rom(0x26, 0x00);
1422+ retval |= ioh_pcieqos_write_serial_rom(0x25, 0x00);
1423+ retval |= ioh_pcieqos_write_serial_rom(0x24, 0x00);
1424+
1425+ return retval;
1426+}
1427+
1428diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.h topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.h
1429--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.h 1970-01-01 09:00:00.000000000 +0900
1430+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_hal.h 2010-03-08 12:02:57.000000000 +0900
1431@@ -0,0 +1,125 @@
1432+#ifndef __IOH_PCIEQOS_HAL_H__
1433+#define __IOH_PCIEQOS_HAL_H__
1434+/*!
1435+ * @file ioh_pcieqos_hal.h
1436+ * @brief Provides all the interfaces pertaining to the HAL.
1437+ * @version 1.0.0.0
1438+ * @section
1439+ * This program is free software; you can redistribute it and/or modify
1440+ * it under the terms of the GNU General Public License as published by
1441+ * the Free Software Foundation; version 2 of the License.
1442+ *
1443+ * This program is distributed in the hope that it will be useful,
1444+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1445+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1446+ * GNU General Public License for more details.
1447+ *
1448+ * You should have received a copy of the GNU General Public License
1449+ * along with this program; if not, write to the Free Software
1450+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1451+ */
1452+
1453+/*
1454+ * History:
1455+ * Copyright (C) 2009 OKI SEMICONDUCTOR Co., LTD.
1456+ * All rights reserved.
1457+ *
1458+ * created:
1459+ * OKI SEMICONDUCTOR 06/20/2009
1460+ * modified:
1461+ *
1462+ */
1463+
1464+/* exported function prototypes */
1465+/*! @ingroup PCIEQOS_HALLayerAPI
1466+ @fn void ioh_pcieqos_read_reg(unsigned long reg_addr_offset,
1467+ unsigned long *data)
1468+ @brief Provides the functionality of reading register
1469+ */
1470+void ioh_pcieqos_read_reg(unsigned long reg_addr_offset, unsigned long *data);
1471+
1472+/*! @ingroup PCIEQOS_HALLayerAPI
1473+ @fn ioh_pcieqos_write_reg(unsigned long reg_addr_offset, unsigned long data)
1474+ @brief Provides the functionality of writing register
1475+ */
1476+void ioh_pcieqos_write_reg(unsigned long reg_addr_offset, unsigned long data);
1477+
1478+/*! @ingroup PCIEQOS_HALLayerAPI
1479+ @fn ioh_pcieqos_read_modify_write_reg(unsigned long reg_addr_offset,
1480+ unsigned long data, unsigned long mask)
1481+ @brief Provides the functionality of reading, modifying and writing register
1482+ */
1483+void ioh_pcieqos_read_modify_write_reg(unsigned long reg_addr_offset,
1484+ unsigned long data, unsigned long mask);
1485+
1486+/*! @ingroup PCIEQOS_HALLayerAPI
1487+ @fn int ioh_pcieqos_read_gbe_mac_addr(unsigned long offset_address,
1488+ unsigned char *data)
1489+ @brief Provides the functionality of reading Gigabit Ethernet MAC address
1490+ */
1491+int ioh_pcieqos_read_gbe_mac_addr(unsigned long offset_address,
1492+ unsigned char *data);
1493+
1494+/*! @ingroup PCIEQOS_HALLayerAPI
1495+ @fn int ioh_pcieqos_write_gbe_mac_addr(unsigned long offset_address,
1496+ unsigned char data)
1497+ @brief Provides the functionality of writing Gigabit Ethernet MAC address
1498+ */
1499+int ioh_pcieqos_write_gbe_mac_addr(unsigned long offset_address,
1500+ unsigned char data);
1501+
1502+/*! @ingroup PCIEQOS_HALLayerAPI
1503+ @fn void ioh_pcieqos_save_reg_conf(void)
1504+ @brief saves register configuration
1505+ */
1506+void ioh_pcieqos_save_reg_conf(void);
1507+
1508+/*! @ingroup PCIEQOS_HALLayerAPI
1509+ @fn void ioh_pcieqos_restore_reg_conf(void)
1510+ @brief restores register configuration
1511+ */
1512+void ioh_pcieqos_restore_reg_conf(void);
1513+
1514+/*! @ingroup PCIEQOS_HALLayerAPI
1515+ @fn int ioh_pcieqos_read_serial_rom(unsigned long offset_address,
1516+ unsigned char *data)
1517+ @brief Provides the functionality of reading Serial ROM
1518+ */
1519+int ioh_pcieqos_read_serial_rom(unsigned long offset_address,
1520+ unsigned char *data);
1521+
1522+/*! @ingroup PCIEQOS_HALLayerAPI
1523+ @fn int ioh_pcieqos_write_serial_rom(unsigned long offset_address,
1524+ unsigned char data)
1525+ @brief Provides the functionality of writing Serial ROM
1526+ */
1527+int ioh_pcieqos_write_serial_rom(unsigned long offset_address,
1528+ unsigned char data);
1529+
1530+/*! @ingroup PCIEQOS_HALLayerAPI
1531+ @fn int ioh_pcieqos_read_serial_rom_val(unsigned long offset_address,
1532+ unsigned char *data)
1533+ @brief Provides the functionality of reading Serial ROM value
1534+ */
1535+int ioh_pcieqos_read_serial_rom_val(unsigned long offset_address,
1536+ unsigned char *data);
1537+
1538+/*! @ingroup PCIEQOS_HALLayerAPI
1539+ @fn int ioh_pcieqos_write_serial_rom_val(unsigned long offset_address,
1540+ unsigned char data)
1541+ @brief Provides the functionality of writing Serial ROM value
1542+ */
1543+int ioh_pcieqos_write_serial_rom_val(unsigned long offset_address,
1544+ unsigned char data);
1545+
1546+/*! @ingroup PCIEQOS_HALLayerAPI
1547+ @fn int ioh_pcieqos_gbe_serial_rom_conf(void)
1548+ @brief makes Serial ROM data format configuration for Gigabit Ethernet
1549+ MAC address
1550+ */
1551+int ioh_pcieqos_gbe_serial_rom_conf(void);
1552+
1553+/* global variables */
1554+extern u32 ioh_pcieqos_base_address;
1555+extern u32 ioh_pcieqos_extrom_base_address;
1556+#endif
1557diff -urN linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_pci.c topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_pci.c
1558--- linux-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_pci.c 1970-01-01 09:00:00.000000000 +0900
1559+++ topcliff-2.6.33-rc3/drivers/char/pch_pcieqos/pch_pcieqos_pci.c 2010-03-08 17:51:26.000000000 +0900
1560@@ -0,0 +1,523 @@
1561+/*!
1562+ * @file ioh_pcieqos_pci.c
1563+ * @brief Provides all the implementation of the interfaces pertaining to the
1564+ * pci and gpic registrations.
1565+ * @version 1.0.0.0
1566+ * @section
1567+ * This program is free software; you can redistribute it and/or modify
1568+ * it under the terms of the GNU General Public License as published by
1569+ * the Free Software Foundation; version 2 of the License.
1570+ *
1571+ * This program is distributed in the hope that it will be useful,
1572+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1573+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1574+ * GNU General Public License for more details.
1575+ *
1576+ * You should have received a copy of the GNU General Public License
1577+ * along with this program; if not, write to the Free Software
1578+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1579+ */
1580+
1581+/*
1582+ * History:
1583+ * Copyright (C) 2009 OKI SEMICONDUCTOR Co., LTD.
1584+ * All rights reserved.
1585+ *
1586+ * created:
1587+ * OKI SEMICONDUCTOR 06/20/2009
1588+ * modified:
1589+ *
1590+ */
1591+/*includes*/
1592+#include <linux/module.h>
1593+#include <linux/kernel.h>
1594+#include <linux/pci.h>
1595+#include <linux/fs.h>
1596+#include <linux/cdev.h>
1597+#include <linux/string.h>
1598+
1599+#include "pch_common.h"
1600+#include "pch_debug.h"
1601+#include "pch_pcieqos.h"
1602+#include "pch_pcieqos_hal.h"
1603+
1604+/*macros*/
1605+
1606+/*! @ingroup PCIEQOS_PCILayer
1607+ @def PCI_DEVICE_ID_IOH1_PCIEQOS
1608+ @brief Outlines the PCI Device ID.
1609+ */
1610+#define PCI_DEVICE_ID_IOH1_PCIEQOS (0x8801)
1611+
1612+/*! @ingroup PCIEQOS_PCILayer
1613+ @def IOH_MINOR_NOS
1614+ @brief Outlines the PCIEQOS minor numbers limit.
1615+ */
1616+#define IOH_MINOR_NOS (1)
1617+
1618+/*values for configuring CLKCFG reg
1619+ * for CAN clock of 50Mhz*/
1620+
1621+/*! @ingroup PCIEQOS_PCILayer
1622+ @def CLKCFG_CAN_50MHZ
1623+ @brief CLKCFG register setting for CAN clock of 50Mhz.
1624+ */
1625+#define CLKCFG_CAN_50MHZ (0x12000000)
1626+
1627+/*! @ingroup PCIEQOS_PCILayer
1628+ @def CLKCFG_CANCLK_MASK
1629+ @brief Bit mask for bit fields in CLKCFG register
1630+ to set CAN clock to 50Mhz.
1631+ */
1632+#define CLKCFG_CANCLK_MASK (0xFF000000)
1633+
1634+/**global variables*/
1635+u32 ioh_pcieqos_base_address;
1636+u32 ioh_pcieqos_extrom_base_address;
1637+s32 ioh_pcieqos_suspended;
1638+
1639+/* ToDo: major number allocation via module parameter */
1640+static dev_t ioh_pcieqos_dev_no;
1641+static int ioh_pcieqos_major_no;
1642+
1643+static struct cdev ioh_pcieqos_dev;
1644+
1645+/*! @ingroup PCIEQOS_PCILayerAPI
1646+ @fn static int __devinit ioh_pcieqos_probe(struct pci_dev* ioh_pci_dev,
1647+ const struct pci_device_id* pci_id)
1648+ @brief Provides the functionality of probing the module
1649+ */
1650+static int __devinit ioh_pcieqos_probe(struct pci_dev *pdev, const
1651+ struct pci_device_id *id);
1652+
1653+/*! @ingroup PCIEQOS_PCILayerAPI
1654+ @fn static void __devexit ioh_pcieqos_remove(struct pci_dev * ioh_pci_dev)
1655+ @brief Provides the functionality of removing the module
1656+ */
1657+static void __devexit ioh_pcieqos_remove(struct pci_dev *pdev);
1658+
1659+/*! @ingroup PCIEQOS_PCILayerAPI
1660+ @fn static int ioh_pcieqos_suspend(struct pci_dev* pDev,pm_message_t state)
1661+ @brief Provides the functionality of suspending the module
1662+ */
1663+static int ioh_pcieqos_suspend(struct pci_dev *pdev, pm_message_t state);
1664+
1665+/*! @ingroup PCIEQOS_PCILayerAPI
1666+ @fn static int ioh_pcieqos_resume(struct pci_dev* pDev)
1667+ @brief Provides the functionality of resuming the module
1668+ */
1669+static int ioh_pcieqos_resume(struct pci_dev *pdev);
1670+
1671+/*structures*/
1672+/*! @ingroup PCIEQOS_PCILayerFacilitators
1673+ @static struct pci_device_id
1674+ @brief It is a structure used for perserving information related to the
1675+ device id.
1676+ @note
1677+ The concerned details should be provided as a reference in the pci driver
1678+ structure.
1679+ */
1680+static struct pci_device_id ioh_pcieqos_pcidev_id[] = {
1681+
1682+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IOH1_PCIEQOS)},
1683+ {0,}
1684+};
1685+
1686+/*! @ingroup PCIEQOS_PCILayerFacilitators
1687+ @static struct ioh_pcieqos_driver
1688+ @brief It is a structure used for perserving information related to the
1689+ pcieqos device and preserves function signatures to manipulate the device.
1690+ @note
1691+ The structure contains the various interfaces aspects
1692+ provided to the pci layer.
1693+ @see
1694+ ioh_pcieqos_probe
1695+ ioh_pcieqos_suspend
1696+ ioh_pcieqos_resume
1697+ ioh_pcieqos_remove
1698+ */
1699+static struct pci_driver ioh_pcieqos_driver = {
1700+ .name = "ioh_pcieqos",
1701+ .id_table = ioh_pcieqos_pcidev_id,
1702+ .probe = ioh_pcieqos_probe,
1703+ .remove = __devexit_p(ioh_pcieqos_remove),
1704+#ifdef CONFIG_PM
1705+ .suspend = ioh_pcieqos_suspend,
1706+ .resume = ioh_pcieqos_resume
1707+#endif
1708+};
1709+
1710+/*! @ingroup PCIEQOS_PCILayerAPI
1711+ * @fn static int __init ioh_pcieqos_pci_init(void)
1712+ * @brief Provides the functionality of initializing the module
1713+ * */
1714+static int __init ioh_pcieqos_pci_init(void);
1715+/*! @ingroup PCIEQOS_PCILayerAPI
1716+ * @fn static void __exit ioh_pcieqos_pci_exit(void)
1717+ * @brief Provides the functionality of exiting the module
1718+ * */
1719+static void __exit ioh_pcieqos_pci_exit(void);
1720+
1721+MODULE_DESCRIPTION("IOH PCIEQOS PCI Driver");
1722+MODULE_LICENSE("GPL");
1723+module_init(ioh_pcieqos_pci_init);
1724+module_exit(ioh_pcieqos_pci_exit);
1725+module_param(ioh_pcieqos_major_no, int, S_IRUSR | S_IWUSR);
1726+
1727+/*function implementations*/
1728+
1729+/*! @ingroup PCIEQOS_PCILayerAPI
1730+ @fn static int __init ioh_pcieqos_pci_init(void)
1731+ @remarks Implements the initialization functionality of the module.
1732+ @param NONE
1733+ @retval returnvalue [@ref OUT] contains the result for the concerned
1734+ attempt.
1735+ The result would generally comprise of success code
1736+ or failure code. The failure code will indicate reason for
1737+ failure.
1738+ @see
1739+ ioh_pcieqos_pci_exit
1740+ */
1741+static int __init ioh_pcieqos_pci_init(void)
1742+{
1743+ s32 ret;
1744+ ret = pci_register_driver(&ioh_pcieqos_driver);
1745+ IOH_DEBUG
1746+ ("ioh_pcieqos_pci_init : Invoked pci_register_driver\
1747+ successfully\n");
1748+ IOH_DEBUG("ioh_pcieqos_pci_init returns %d\n", ret);
1749+ return ret;
1750+}
1751+
1752+/*! @ingroup PCIEQOS_PCILayerAPI
1753+ @fn static void __exit ioh_pcieqos_pci_exit(void)
1754+ @remarks Implements the exit functionality of the module.
1755+ @param NONE
1756+ @retval returnvalue [@ref OUT] contains the result for the concerned
1757+ attempt.
1758+ The result would generally comprise of success code
1759+ or failure code. The failure code will indicate reason for
1760+ failure.
1761+ @see
1762+ ioh_pcieqos_pci_init
1763+ */
1764+static void __exit ioh_pcieqos_pci_exit(void)
1765+{
1766+ pci_unregister_driver(&ioh_pcieqos_driver);
1767+ IOH_DEBUG
1768+ ("ioh_pcieqos_pci_exit : Invoked pci_unregister_driver\
1769+ successfully\n");
1770+}
1771+
1772+/*! @ingroup PCIEQOS_PCILayerAPI
1773+ @fn static int __devinit ioh_pcieqos_probe(struct pci_dev* pdev,
1774+ const struct pci_device_id* id)
1775+ @remarks Implements the probe functionality of the module.
1776+ @param pdev [@ref INOUT] Contains the reference of the pci_dev structure
1777+ @param id [@ref INOUT] Contains the reference of the pci_device_id structure
1778+ @retval returnvalue [@ref OUT] contains the result for the concerned
1779+ attempt.
1780+ The result would generally comprise of success code
1781+ or failure code. The failure code will indicate reason for
1782+ failure.
1783+ @see
1784+ ioh_pcieqos_pci_init
1785+ */
1786+static int __devinit ioh_pcieqos_probe(struct pci_dev *pdev,
1787+ const struct pci_device_id *id)
1788+{
1789+
1790+ char *DRIVER_NAME = "ioh_pcieqos";
1791+ int ret;
1792+ unsigned int rom_size;
1793+
1794+ ioh_pcieqos_major_no = (ioh_pcieqos_major_no < 0
1795+ || ioh_pcieqos_major_no >
1796+ 254) ? 0 : ioh_pcieqos_major_no;
1797+
1798+ do {
1799+
1800+ ret = pci_enable_device(pdev);
1801+ if (ret) {
1802+ IOH_LOG(KERN_ERR,
1803+ "\nioh_pcieqos_probe : pci_enable_device\
1804+ FAILED");
1805+ break;
1806+ }
1807+ IOH_DEBUG("ioh_pcieqos_probe : pci_enable_device returns %d\n",
1808+ ret);
1809+
1810+ ret = pci_request_regions(pdev, DRIVER_NAME);
1811+ if (ret) {
1812+ IOH_LOG(KERN_ERR,
1813+ "ioh_pcieqos_probe : pci_request_regions\
1814+ FAILED");
1815+ pci_disable_device(pdev);
1816+ break;
1817+ }
1818+ IOH_DEBUG
1819+ ("ioh_pcieqos_probe : pci_request_regions returns %d\n",
1820+ ret);
1821+
1822+ ioh_pcieqos_base_address = (unsigned long)pci_iomap(pdev, 1, 0);
1823+
1824+ if (ioh_pcieqos_base_address == 0) {
1825+ IOH_LOG(KERN_ERR,
1826+ "ioh_pcieqos_probe : pci_iomap FAILED");
1827+ pci_release_regions(pdev);
1828+ pci_disable_device(pdev);
1829+ ret = -ENOMEM;
1830+ break;
1831+ }
1832+ IOH_DEBUG
1833+ ("ioh_pcieqos_probe : pci_iomap SUCCESS and value in\
1834+ ioh_pcieqos_base_address variable is 0x%08x\n",
1835+ ioh_pcieqos_base_address);
1836+
1837+ ioh_pcieqos_extrom_base_address =
1838+ (unsigned long)pci_map_rom(pdev, &rom_size);
1839+ if (ioh_pcieqos_extrom_base_address == 0) {
1840+ IOH_LOG(KERN_ERR,
1841+ "ioh_pcieqos_probe : pci_map_rom FAILED");
1842+ pci_iounmap(pdev, (void *)ioh_pcieqos_base_address);
1843+ pci_release_regions(pdev);
1844+ pci_disable_device(pdev);
1845+ ret = -ENOMEM;
1846+ break;
1847+ }
1848+ IOH_DEBUG
1849+ ("ioh_pcieqos_probe : pci_map_rom SUCCESS and value in\
1850+ ioh_pcieqos_extrom_base_address variable is 0x%08x\n",
1851+ ioh_pcieqos_extrom_base_address);
1852+
1853+ if (ioh_pcieqos_major_no) {
1854+ ioh_pcieqos_dev_no = MKDEV(ioh_pcieqos_major_no, 0);
1855+ ret =
1856+ register_chrdev_region(ioh_pcieqos_dev_no,
1857+ IOH_MINOR_NOS, DRIVER_NAME);
1858+ if (ret) {
1859+ IOH_LOG(KERN_ERR,
1860+ "ioh_pcieqos_probe :\
1861+ register_chrdev_region FAILED");
1862+ pci_unmap_rom(pdev,
1863+ (void *)
1864+ ioh_pcieqos_extrom_base_address);
1865+ pci_iounmap(pdev,
1866+ (void *)ioh_pcieqos_base_address);
1867+ pci_release_regions(pdev);
1868+ pci_disable_device(pdev);
1869+ break;
1870+ }
1871+ IOH_DEBUG
1872+ ("ioh_pcieqos_probe :\
1873+ register_chrdev_region returns %d\n",
1874+ ret);
1875+ } else {
1876+ ret =
1877+ alloc_chrdev_region(&ioh_pcieqos_dev_no, 0,
1878+ IOH_MINOR_NOS, DRIVER_NAME);
1879+ if (ret) {
1880+ IOH_LOG(KERN_ERR,
1881+ "ioh_pcieqos_probe :\
1882+ alloc_chrdev_region FAILED");
1883+ pci_unmap_rom(pdev,
1884+ (void *)
1885+ ioh_pcieqos_extrom_base_address);
1886+ pci_iounmap(pdev,
1887+ (void *)ioh_pcieqos_base_address);
1888+ pci_release_regions(pdev);
1889+ pci_disable_device(pdev);
1890+ break;
1891+ }
1892+ IOH_DEBUG
1893+ ("ioh_pcieqos_probe :\
1894+ alloc_chrdev_region returns %d\n",
1895+ ret);
1896+ }
1897+
1898+ cdev_init(&ioh_pcieqos_dev, &ioh_pcieqos_fops);
1899+ IOH_DEBUG
1900+ ("ioh_pcieqos_probe : cdev_init invoked successfully\n");
1901+
1902+ ioh_pcieqos_dev.owner = THIS_MODULE;
1903+ ioh_pcieqos_dev.ops = &ioh_pcieqos_fops;
1904+
1905+ ret =
1906+ cdev_add(&ioh_pcieqos_dev, ioh_pcieqos_dev_no,
1907+ IOH_MINOR_NOS);
1908+ if (ret) {
1909+ IOH_LOG(KERN_ERR,
1910+ "ioh_pcieqos_probe : cdev_add FAILED");
1911+ unregister_chrdev_region(ioh_pcieqos_dev_no,
1912+ IOH_MINOR_NOS);
1913+ pci_unmap_rom(pdev,
1914+ (void *)ioh_pcieqos_extrom_base_address);
1915+ pci_iounmap(pdev, (void *)ioh_pcieqos_base_address);
1916+ pci_release_regions(pdev);
1917+ pci_disable_device(pdev);
1918+ break;
1919+ }
1920+ IOH_DEBUG("ioh_pcieqos_probe : cdev_add returns %d\n", ret);
1921+
1922+#ifdef IOH_CAN_PCLK_50MHZ
1923+ /*set the clock config reg if CAN clock is 50Mhz */
1924+ IOH_DEBUG
1925+ ("ioh_pcieqos_probe : invoking\
1926+ ioh_pcieqos_read_modify_write_reg to set CLKCFG reg\
1927+ for CAN clk 50Mhz\n");
1928+ ioh_pcieqos_read_modify_write_reg(CLKCFG_REG_OFFSET,
1929+ CLKCFG_CAN_50MHZ,
1930+ CLKCFG_CANCLK_MASK);
1931+#endif
1932+ return IOH_PCIEQOS_SUCCESS;
1933+ } while (0);
1934+ IOH_DEBUG("ioh_pcieqos_probe returns %d\n", ret);
1935+ return ret;
1936+}
1937+
1938+/*! @ingroup PCIEQOS_PCILayerAPI
1939+ @fn static void __devexit ioh_pcieqos_remove(struct pci_dev * pdev)
1940+ @remarks Implements the remove functionality of the module.
1941+ @param pdev [@ref INOUT] Contains the reference of the pci_dev structure
1942+ @retval returnvalue [@ref OUT] contains the result for the concerned
1943+ attempt.
1944+ The result would generally comprise of success code
1945+ or failure code. The failure code will indicate reason for
1946+ failure.
1947+ @see
1948+ ioh_pcieqos_pci_init
1949+ */
1950+static void __devexit ioh_pcieqos_remove(struct pci_dev *pdev)
1951+{
1952+
1953+ cdev_del(&ioh_pcieqos_dev);
1954+ IOH_DEBUG("ioh_pcieqos_remove - cdev_del Invoked successfully\n");
1955+
1956+ unregister_chrdev_region(ioh_pcieqos_dev_no, IOH_MINOR_NOS);
1957+ IOH_DEBUG
1958+ ("ioh_pcieqos_remove - unregister_chrdev_region Invoked\
1959+ successfully\n");
1960+
1961+ pci_unmap_rom(pdev, (void *)ioh_pcieqos_extrom_base_address);
1962+
1963+ pci_iounmap(pdev, (void *)ioh_pcieqos_base_address);
1964+
1965+ IOH_DEBUG("ioh_pcieqos_remove - pci_iounmap Invoked successfully\n");
1966+
1967+ pci_release_regions(pdev);
1968+ IOH_DEBUG
1969+ ("ioh_pcieqos_remove - pci_release_regions Invoked successfully\n");
1970+
1971+ pci_disable_device(pdev);
1972+ IOH_DEBUG
1973+ ("ioh_pcieqos_remove - pci_disable_device Invoked successfully\n");
1974+
1975+}
1976+
1977+#ifdef CONFIG_PM
1978+
1979+/*! @ingroup PCIEQOS_PCILayerAPI
1980+ @fn static int ioh_pcieqos_suspend(struct pci_dev* pdev,pm_message_t state)
1981+ @remarks Implements the suspend functionality of the module.
1982+ @param pdev [@ref INOUT] Contains the reference of the pci_dev structure
1983+ @param state [@ref INOUT] Contains the reference of the pm_message_t
1984+ structure
1985+ @retval returnvalue [@ref OUT] contains the result for the concerned
1986+ attempt.
1987+ The result would generally comprise of success code
1988+ or failure code. The failure code will indicate reason for
1989+ failure.
1990+ @see
1991+ ioh_pcieqos_pci_init
1992+ ioh_pcieqos_resume
1993+ */
1994+static int ioh_pcieqos_suspend(struct pci_dev *pdev, pm_message_t state)
1995+{
1996+ int ret;
1997+
1998+ ioh_pcieqos_suspended = true; /* For blocking further IOCTLs */
1999+
2000+ ioh_pcieqos_save_reg_conf();
2001+ IOH_DEBUG
2002+ ("ioh_pcieqos_suspend - ioh_pcieqos_save_reg_conf Invoked\
2003+ successfully\n");
2004+
2005+ ret = pci_save_state(pdev);
2006+ if (ret) {
2007+ IOH_LOG(KERN_ERR,
2008+ " ioh_pcieqos_suspend -pci_save_state returns-%d\n",
2009+ ret);
2010+ return ret;
2011+ }
2012+
2013+ pci_enable_wake(pdev, PCI_D3hot, 0);
2014+ IOH_DEBUG
2015+ ("ioh_pcieqos_suspend - pci_enable_wake Invoked successfully\n");
2016+
2017+ IOH_DEBUG("ioh_pcieqos_suspend - pci_save_state returns %d\n", ret);
2018+
2019+ pci_disable_device(pdev);
2020+ IOH_DEBUG
2021+ ("ioh_pcieqos_suspend - pci_disable_device Invoked successfully\n");
2022+
2023+ pci_set_power_state(pdev, pci_choose_state(pdev, state));
2024+ IOH_DEBUG
2025+ ("ioh_pcieqos_suspend - pci_set_power_state Invoked\
2026+ successfully\n");
2027+
2028+ IOH_DEBUG("ioh_pcieqos_suspend - return %d\n", IOH_PCIEQOS_SUCCESS);
2029+
2030+ return IOH_PCIEQOS_SUCCESS;
2031+}
2032+
2033+/*! @ingroup PCIEQOS_PCILayerAPI
2034+ @fn static int ioh_pcieqos_resume(struct pci_dev* pdev)
2035+ @remarks Implements the resume functionality of the module.
2036+ @param pdev [@ref INOUT] Contains the reference of the pci_dev structure
2037+ @retval returnvalue [@ref OUT] contains the result for the concerned\
2038+ attempt.
2039+ The result would generally comprise of success code
2040+ or failure code. The failure code will indicate reason for
2041+ failure.
2042+ @see
2043+ ioh_pcieqos_pci_init
2044+ ioh_pcieqos_suspend
2045+ */
2046+static int ioh_pcieqos_resume(struct pci_dev *pdev)
2047+{
2048+
2049+ int ret;
2050+
2051+ pci_set_power_state(pdev, PCI_D0);
2052+ IOH_DEBUG
2053+ ("ioh_pcieqos_resume - pci_set_power_state Invoked successfully\n");
2054+
2055+ pci_restore_state(pdev);
2056+ IOH_DEBUG
2057+ ("ioh_pcieqos_resume - pci_restore_state Invoked successfully\n");
2058+
2059+ ret = pci_enable_device(pdev);
2060+ if (ret) {
2061+ IOH_LOG(KERN_ERR,
2062+ "ioh_pcieqos_resume-pci_enable_device failed ");
2063+ return ret;
2064+ }
2065+
2066+ IOH_DEBUG("ioh_pcieqos_resume - pci_enable_device returns -%d\n", ret);
2067+
2068+ pci_enable_wake(pdev, PCI_D3hot, 0);
2069+ IOH_DEBUG
2070+ ("ioh_pcieqos_resume - pci_enable_wake Invoked successfully\n");
2071+
2072+ ioh_pcieqos_restore_reg_conf();
2073+ IOH_DEBUG
2074+ ("ioh_pcieqos_resume - ioh_pcieqos_restore_reg_conf Invoked\
2075+ successfully\n");
2076+
2077+ ioh_pcieqos_suspended = false;
2078+
2079+ IOH_DEBUG("ioh_pcieqos_resume returns- %d\n", IOH_PCIEQOS_SUCCESS);
2080+ return IOH_PCIEQOS_SUCCESS;
2081+}
2082+
2083+#endif
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-20 07:30:30 +0000