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-rw-r--r--meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-gpio.patch2700
1 files changed, 2700 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-gpio.patch b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-gpio.patch
new file mode 100644
index 0000000000..c57f949078
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.34-pch-gpio.patch
@@ -0,0 +1,2700 @@
1
2
3From: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
4Subject: OKI Semiconductor PCH GPIO driver
5
6This driver implements GPIO controls for PCH.
7
8Signed-off-by: Masayuki Ohtake <masa-korg@dsn.okisemi.com>
9Acked-by: Wang Qi <qi.wang@intel.com>
10
11---
12 drivers/gpio/Kconfig |
13 drivers/gpio/Makefile |
14 drivers/gpio/pch_gpio/Makefile |
15 drivers/gpio/pch_gpio/pch_common.h |
16 drivers/gpio/pch_gpio/pch_debug.h |
17 drivers/gpio/pch_gpio/pch_gpio_hal.c |
18 drivers/gpio/pch_gpio/pch_gpio_hal.h |
19 drivers/gpio/pch_gpio/pch_gpio_main.c |
20 drivers/gpio/pch_gpio/pch_gpio_main.h |
21 drivers/gpio/pch_gpio/pch_gpio_pci.c |
22+++++++++++++++++++++++++++++++ 10 files changed, yy insertions(+)(-)
23diff -urN linux-2.6.33.1/drivers/gpio/Kconfig topcliff-2.6.33.1/drivers/gpio/Kconfig
24--- linux-2.6.33.1/drivers/gpio/Kconfig 2010-03-16 01:09:39.000000000 +0900
25+++ topcliff-2.6.33.1/drivers/gpio/Kconfig 2010-04-01 10:58:31.000000000 +0900
26@@ -87,6 +87,13 @@
27
28 comment "I2C GPIO expanders:"
29
30+config PCH_GPIO
31+ tristate "PCH GPIO"
32+ depends on PCI
33+ help
34+ If you say yes to this option, support will be included for the SMB
35+ PCH GPIO Host controller.
36+
37 config GPIO_MAX732X
38 tristate "MAX7319, MAX7320-7327 I2C Port Expanders"
39 depends on I2C
40diff -urN linux-2.6.33.1/drivers/gpio/Makefile topcliff-2.6.33.1/drivers/gpio/Makefile
41--- linux-2.6.33.1/drivers/gpio/Makefile 2010-03-16 01:09:39.000000000 +0900
42+++ topcliff-2.6.33.1/drivers/gpio/Makefile 2010-04-01 10:58:31.000000000 +0900
43@@ -22,3 +22,4 @@
44 obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o
45 obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
46 obj-$(CONFIG_GPIO_WM831X) += wm831x-gpio.o
47+obj-$(CONFIG_PCH_GPIO) += pch_gpio/
48diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/Makefile topcliff-2.6.33.1/drivers/gpio/pch_gpio/Makefile
49--- linux-2.6.33.1/drivers/gpio/pch_gpio/Makefile 1970-01-01 09:00:00.000000000 +0900
50+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/Makefile 2010-04-01 10:58:31.000000000 +0900
51@@ -0,0 +1,7 @@
52+ifeq ($(CONFIG_GPIO_DEBUG_CORE),y)
53+EXTRA_CFLAGS += -DDEBUG
54+endif
55+
56+obj-$(CONFIG_PCH_GPIO) += pch_gpio.o
57+pch_gpio-objs := pch_gpio_hal.o pch_gpio_main.o pch_gpio_pci.o
58+
59diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_common.h topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_common.h
60--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_common.h 1970-01-01 09:00:00.000000000 +0900
61+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_common.h 2010-04-01 10:58:31.000000000 +0900
62@@ -0,0 +1,146 @@
63+/*!
64+ * @file ioh_common.h
65+ * @brief Provides the macro definitions used by all files.
66+ * @version 1.0.0.0
67+ * @section
68+ * This program is free software; you can redistribute it and/or modify
69+ * it under the terms of the GNU General Public License as published by
70+ * the Free Software Foundation; version 2 of the License.
71+ *
72+ * This program is distributed in the hope that it will be useful,
73+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
74+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
75+ * GNU General Public License for more details.
76+ *
77+ * You should have received a copy of the GNU General Public License
78+ * along with this program; if not, write to the Free Software
79+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
80+ */
81+
82+/*
83+ * History:
84+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
85+ * All rights reserved.
86+ *
87+ * created:
88+ * WIPRO 03/07/2009
89+ * modified:
90+ * WIPRO 05/08/2009
91+ *
92+ */
93+
94+#ifndef __IOH_COMMON_H__
95+#define __IOH_COMMON_H__
96+
97+/*! @ingroup Global
98+@def IOH_WRITE8
99+@brief Macro for writing 8 bit data to an io/mem address
100+*/
101+#define IOH_WRITE8(val, addr) iowrite8((val), (void __iomem *)(addr))
102+/*! @ingroup Global
103+@def IOH_LOG
104+@brief Macro for writing 16 bit data to an io/mem address
105+*/
106+#define IOH_WRITE16(val, addr) iowrite16((val), (void __iomem *)(addr))
107+/*! @ingroup Global
108+@def IOH_LOG
109+@brief Macro for writing 32 bit data to an io/mem address
110+*/
111+#define IOH_WRITE32(val, addr) iowrite32((val), (void __iomem *)(addr))
112+
113+/*! @ingroup Global
114+@def IOH_READ8
115+@brief Macro for reading 8 bit data from an io/mem address
116+*/
117+#define IOH_READ8(addr) ioread8((void __iomem *)(addr))
118+/*! @ingroup Global
119+@def IOH_READ16
120+@brief Macro for reading 16 bit data from an io/mem address
121+*/
122+#define IOH_READ16(addr) ioread16((void __iomem *)(addr))
123+/*! @ingroup Global
124+@def IOH_READ32
125+@brief Macro for reading 32 bit data from an io/mem address
126+*/
127+#define IOH_READ32(addr) ioread32((void __iomem *)(addr))
128+/*! @ingroup Global
129+@def IOH_WRITE32_F
130+@brief Macro for writing 32 bit data to an io/mem address
131+*/
132+#define IOH_WRITE32_F(val, addr) do \
133+ { IOH_WRITE32((val), (addr)); (void)IOH_READ32((addr)); } while (0);
134+
135+/*! @ingroup Global
136+@def IOH_WRITE_BYTE
137+@brief Macro for writing 1 byte data to an io/mem address
138+*/
139+#define IOH_WRITE_BYTE IOH_WRITE8
140+/*! @ingroup Global
141+@def IOH_WRITE_WORD
142+@brief Macro for writing 1 word data to an io/mem address
143+*/
144+#define IOH_WRITE_WORD IOH_WRITE16
145+/*! @ingroup Global
146+@def IOH_WRITE_LONG
147+@brief Macro for writing long data to an io/mem address
148+*/
149+#define IOH_WRITE_LONG IOH_WRITE32
150+
151+/*! @ingroup Global
152+@def IOH_READ_BYTE
153+@brief Macro for reading 1 byte data from an io/mem address
154+*/
155+#define IOH_READ_BYTE IOH_READ8
156+/*! @ingroup Global
157+@def IOH_READ_WORD
158+@brief Macro for reading 1 word data from an io/mem address
159+*/
160+#define IOH_READ_WORD IOH_READ16
161+/*! @ingroup Global
162+@def IOH_READ_LONG
163+@brief Macro for reading long data from an io/mem address
164+*/
165+#define IOH_READ_LONG IOH_READ32
166+
167+/* Bit Manipulation Macros */
168+
169+/*! @ingroup Global
170+@def IOH_READ_LONG
171+@brief macro to set a specified bit(mask) at the
172+ specified address
173+*/
174+#define IOH_SET_ADDR_BIT(addr, bitmask) IOH_WRITE_LONG((IOH_READ_LONG(addr) |\
175+ (bitmask)), (addr))
176+
177+/*! @ingroup Global
178+@def IOH_READ_LONG
179+@brief macro to clear a specified bit(mask) at the specified address
180+*/
181+#define IOH_CLR_ADDR_BIT(addr, bitmask) IOH_WRITE_LONG((IOH_READ_LONG(addr) &\
182+ ~(bitmask)), (addr))
183+
184+/*! @ingroup Global
185+@def IOH_READ_LONG
186+@brief macro to set a specified bitmask for a variable
187+*/
188+#define IOH_SET_BITMSK(var, bitmask) ((var) |= (bitmask))
189+
190+/*! @ingroup Global
191+@def IOH_READ_LONG
192+@brief macro to clear a specified bitmask for a variable
193+*/
194+#define IOH_CLR_BITMSK(var, bitmask) ((var) &= (~(bitmask)))
195+
196+/*! @ingroup Global
197+@def IOH_READ_LONG
198+@brief macro to set a specified bit for a variable
199+*/
200+#define IOH_SET_BIT(var, bit) ((var) |= (1<<(bit)))
201+
202+/*! @ingroup Global
203+@def IOH_READ_LONG
204+@brief macro to clear a specified bit for a variable
205+*/
206+#define IOH_CLR_BIT(var, bit) ((var) &= ~(1<<(bit)))
207+
208+#endif
209diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_debug.h topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_debug.h
210--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_debug.h 1970-01-01 09:00:00.000000000 +0900
211+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_debug.h 2010-04-01 10:58:31.000000000 +0900
212@@ -0,0 +1,60 @@
213+/*!
214+ * @file ioh_debug.h
215+ * @brief Provides the macro definitions used for debugging.
216+ * @version 1.0.0.0
217+ * @section
218+ * This program is free software; you can redistribute it and/or modify
219+ * it under the terms of the GNU General Public License as published by
220+ * the Free Software Foundation; version 2 of the License.
221+ *
222+ * This program is distributed in the hope that it will be useful,
223+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
224+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
225+ * GNU General Public License for more details.
226+ *
227+ * You should have received a copy of the GNU General Public License
228+ * along with this program; if not, write to the Free Software
229+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
230+ */
231+
232+/*
233+ * History:
234+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
235+ * All rights reserved.
236+ *
237+ * created:
238+ * WIPRO 03/07/2009
239+ * modified:
240+ * WIPRO 05/08/2009
241+ *
242+ */
243+
244+#ifndef __IOH_DEBUG_H__
245+#define __IOH_DEBUG_H__
246+
247+#ifdef MODULE
248+#define IOH_LOG(level, fmt, args...) printk(level "%s:" fmt "\n",\
249+ THIS_MODULE->name, ##args)
250+#else
251+#define IOH_LOG(level, fmt, args...) printk(level "%s:" fmt "\n" ,\
252+ __FILE__, ##args)
253+#endif
254+
255+
256+#ifdef DEBUG
257+ #define IOH_DEBUG(fmt, args...) IOH_LOG(KERN_DEBUG, fmt, ##args)
258+#else
259+ #define IOH_DEBUG(fmt, args...)
260+#endif
261+
262+#ifdef IOH_TRACE_ENABLED
263+ #define IOH_TRACE IOH_DEBUG
264+#else
265+ #define IOH_TRACE(fmt, args...)
266+#endif
267+
268+#define IOH_TRACE_ENTER IOH_TRACE("Enter %s", __func__)
269+#define IOH_TRACE_EXIT IOH_TRACE("Exit %s", __func__)
270+
271+
272+#endif
273diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.c topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.c
274--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.c 1970-01-01 09:00:00.000000000 +0900
275+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.c 2010-04-01 10:58:31.000000000 +0900
276@@ -0,0 +1,595 @@
277+/*!
278+ * @file ioh_gpio_hal.c
279+ * @brief Provides all the implementation of the interfaces pertaining to the
280+ * HAL.
281+ * @version 0.92
282+ * @section
283+ * This program is free software; you can redistribute it and/or modify
284+ * it under the terms of the GNU General Public License as published by
285+ * the Free Software Foundation; version 2 of the License.
286+ *
287+ * This program is distributed in the hope that it will be useful,
288+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
289+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
290+ * GNU General Public License for more details.
291+ *
292+ * You should have received a copy of the GNU General Public License
293+ * along with this program; if not, write to the Free Software
294+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
295+ */
296+
297+/*
298+ * History:
299+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
300+ * All rights reserved.
301+ *
302+ * created:
303+ * WIPRO 02/20/2009
304+ * modified:
305+ * WIPRO 01/05/2010
306+ * Added the interfaces provided by the gpio module.
307+ *
308+ */
309+
310+/*includes*/
311+#include <linux/io.h>
312+#include <linux/sched.h>
313+#include <linux/interrupt.h>
314+#include <linux/module.h>
315+
316+#include "pch_common.h"
317+#include "pch_debug.h"
318+#include "pch_gpio_main.h"
319+#include "pch_gpio_hal.h"
320+
321+/* mask for interrupt mode configuration */
322+#define GPIO_INT_MODE_MSK (0xF)
323+
324+/* mask for interrupt mode bit position */
325+#define GPIO_INT_MODE_POS (0x4)
326+
327+/* interrupt mode valid value */
328+#define GPIO_INT_MODE_VALID (0x4)
329+
330+/*! @ingroup GPIO_InterfaceLayer
331+ @def BITS_32
332+ @brief Corresponds to the 32 bit position.
333+*/
334+#define BITS_32 (32)
335+
336+
337+/*! @ingroup GPIO_Global
338+ @var ioh_gpio_cbr
339+ @brief The global variable for storing the callback function pointer.
340+ @remarks This variable is used to store the function pointer
341+ to the callback function of the GPIO module.
342+
343+ @see
344+ - ioh_gpio_cb_register
345+*/
346+void (*ioh_gpio_cbr) (u32);
347+
348+/*! @ingroup GPIO_HALLayer
349+ struct ioh_gpio_reg_data
350+ @brief The register data.
351+*/
352+struct ioh_gpio_reg_data {
353+ u32 ien_reg; /**< To store contents of IEN register. */
354+ u32 imask_reg; /**< To store contents of IMASK register. */
355+ u32 po_reg; /**< To store contents of PO register. */
356+ u32 pm_reg; /**< To store contents of PM register. */
357+ u32 im0_reg; /**< To store contents of IM0 register. */
358+ u32 im1_reg; /**< To store contents of IM1 register. */
359+} ioh_gpio_reg;
360+
361+/*functions implementations*/
362+/*! @ingroup GPIO_HALLayerAPI
363+@fn void ioh_gpio_cb_register(void(*ioh_gpio_ptr)(u32))
364+@brief Registers the callback function.
365+@remarks This function registers the callback function used
366+ by the gpio module. The main task performed by this
367+ function is:
368+ - If the function argument is non NULL, update the
369+ same in the global callback pointer variable
370+ @ref ioh_gpio_cbr.
371+@param ioh_gpio_cb_register [@ref INOUT]
372+ Contains the reference of the function pointer
373+@retval None
374+@see
375+ - ioh_gpio_int_mode
376+*/
377+void ioh_gpio_cb_register(void (*ioh_gpio_ptr) (u32))
378+{
379+ if (ioh_gpio_ptr != NULL) {
380+
381+ init_waitqueue_head(&ioh_gpio_event);
382+ IOH_DEBUG
383+ (" In ioh_gpio_cb_register: value of ioh_gpio_ptr = %p\n",
384+ ioh_gpio_ptr);
385+ ioh_gpio_cbr = ioh_gpio_ptr;
386+ IOH_DEBUG("ioh_gpio_cb_register Registered callback\n");
387+ IOH_DEBUG
388+ ("In ioh_gpio_cb_register : value of ioh_gpio_cbr =%p\n",
389+ ioh_gpio_cbr);
390+ }
391+
392+}
393+
394+/*! @ingroup GPIO_HALLayerAPI
395+@fn void ioh_gpio_int_mode(struct ioh_gpio_reqt * gpio_reqt)
396+@remarks Implements the functionality of disabling or enabling interrupts.
397+ The main tasks performed by this function are:
398+ - If the request is for disabling the interrupts, then the
399+ corresponding bits in the IEN register are set to 0.
400+ - If the request is for enabling the interrupts, then the
401+ corresponding bits in the IEN register are set to 1.
402+
403+@param gpio_reqt [@ref INOUT]
404+ Contains the reference of the ioh_gpio_reqt structure
405+@retval s32
406+ - @ref IOH_GPIO_SUCCESS --> If the operation is successful.
407+ - -EINVAL --> Failure.
408+@see
409+ - ioh_gpio_dir_mode
410+*/
411+s32 ioh_gpio_int_mode(struct ioh_gpio_reqt *gpio_reqt)
412+{
413+ u32 ioh_pins;
414+ u32 base_addr;
415+ u32 i;
416+ u32 ien_val;
417+ u64 temp;
418+ u64 mode_val;
419+
420+ /* initialize locals */
421+ ioh_pins = gpio_reqt->pins;
422+ base_addr = ioh_gpio_base_address;
423+ ien_val = IOH_READ_LONG(base_addr + IOH_IEN);
424+
425+ /* Disable applicable bits in IEN register */
426+ ien_val &= (~ioh_pins);
427+ IOH_WRITE_LONG(ien_val, (base_addr + IOH_IEN));
428+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IEN\n", ien_val);
429+
430+ /* Reading the modes of all the 12 pins. */
431+ mode_val = ((((u64) IOH_READ_LONG(base_addr + IOH_IM1)) << BITS_32) |
432+ (IOH_READ_LONG(base_addr + IOH_IM0)));
433+
434+ /* enable interrupts */
435+ if (gpio_reqt->enable == 1) {
436+ IOH_DEBUG("ioh_gpio_int_mode Enabling interrupts\n");
437+
438+ for (i = 0; i < GPIO_NUM_PINS; i++) {
439+ /*GPIO_NUM_PINS = max num. pins for the GPIO port. */
440+ if (ioh_pins & (1 << i)) {
441+ /*If interrupt for the pin has to be enabled. */
442+ /* int. mode setting for each pin is specified
443+ by 3 bits
444+ 000 Generates an interrupt
445+ at the falling edge.
446+ 001 Generates an interrupt
447+ at the rising edge.
448+ 010 Generates an interrupt
449+ at the input of a L level.
450+ 011 Generates an interrupt
451+ at the input of a H level.
452+ 100 Generates an interrupt
453+ at both edges (rising edge/falling edge).
454+ */
455+ /* Clear the existing interrupt mode
456+ setting for the current pin. */
457+ mode_val &=
458+ ~(((u64) GPIO_INT_MODE_MSK) <<
459+ (i * GPIO_INT_MODE_POS));
460+
461+ /* Update the new setting. */
462+ temp =
463+ (gpio_reqt->
464+ mode) & (((u64) GPIO_INT_MODE_MSK) << (i *
465+ GPIO_INT_MODE_POS));
466+
467+ mode_val |= temp;
468+
469+ if (((temp >> (i * GPIO_INT_MODE_POS)) >
470+ GPIO_INT_MODE_VALID)) {
471+ IOH_LOG(KERN_ERR,
472+ "ioh_gpio_int_mode Invalid\
473+ mode selection for "
474+ "pin %d\n", i);
475+ return -EINVAL;
476+ }
477+ IOH_DEBUG
478+ ("ioh_gpio_int_mode Interrupt enabled\
479+ for pin %d \n",
480+ i);
481+ } else {
482+ IOH_DEBUG
483+ ("ioh_gpio_int_mode Interrupt not enabled\
484+ for pin %d \n",
485+ i);
486+ }
487+ }
488+ /* Set the mode register IM0 */
489+ IOH_WRITE_LONG(((u32) (mode_val & BIT_MASK_32)),
490+ (base_addr + IOH_IM0));
491+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IM0\n",
492+ ((u32) (mode_val & BIT_MASK_32)));
493+
494+ /* Set the mode register IM1 */
495+ IOH_WRITE_LONG(((u32) (mode_val >> BITS_32)),
496+ (base_addr + IOH_IM1));
497+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IM1\n",
498+ ((u32) (mode_val >> BITS_32)));
499+
500+ /* Clear the status */
501+ IOH_WRITE_LONG(ioh_pins, (base_addr + IOH_ICLR));
502+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_ICLR\n",
503+ ioh_pins);
504+ IOH_DEBUG("ioh_gpio_int_mode value in to IOH_ISTATUS %x\n",
505+ IOH_READ_LONG(base_addr + IOH_ISTATUS));
506+
507+ /* Clear the mask register */
508+ IOH_WRITE_LONG(ioh_pins, (base_addr + IOH_IMASKCLR));
509+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IMASKCLR\n",
510+ ioh_pins);
511+
512+ ien_val = (ien_val | ioh_pins);
513+
514+ /*Enable applicable bits in IEN register */
515+ IOH_WRITE_LONG(ien_val, (base_addr + IOH_IEN));
516+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IEN\n", ien_val);
517+
518+ }
519+
520+ /* disable interrupts */
521+ else {
522+ IOH_DEBUG("ioh_gpio_int_mode Disabling interrupts\n");
523+ /* Clear the status */
524+ IOH_WRITE_LONG(ioh_pins, (base_addr + IOH_ICLR));
525+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_ICLR\n",
526+ ioh_pins);
527+
528+ /* Set the mask register */
529+ IOH_WRITE_LONG(ioh_pins, (base_addr + IOH_IMASK));
530+ IOH_DEBUG("ioh_gpio_int_mode wrote %x to IOH_IMASK\n",
531+ ioh_pins);
532+
533+ /* IEN bits are already disabled initially */
534+
535+ }
536+ IOH_DEBUG("ioh_gpio_int_mode returning=%d\n", IOH_GPIO_SUCCESS);
537+ return IOH_GPIO_SUCCESS;
538+}
539+
540+/*! @ingroup GPIO_HALLayerAPI
541+@fn void ioh_gpio_dir_mode(struct ioh_gpio_reqt * gpio_reqt)
542+@remarks Implements the functionalities for setting GPIO pin
543+ directions[input/output].
544+ The main tasks performed by this function are:
545+ - Reads the current value of PM register
546+ - If input mode is specified @ref GPIO_IN, performs logical
547+ AND between the present PM register value and the 1's
548+ complement of gpio_reqt->pins (@ref ioh_gpio_reqt) and
549+ updates the value in the PM register.
550+ - Else performs logical OR between the present PM register value
551+ and gpio_reqt->pins (@ref ioh_gpio_reqt) and updates the value
552+ in the PM register.
553+
554+@param gpio_reqt [@ref INOUT] Contains the reference of
555+ the ioh_gpio_reqt structure
556+@retval None
557+@see
558+ - ioh_gpio_read
559+*/
560+void ioh_gpio_dir_mode(struct ioh_gpio_reqt *gpio_reqt)
561+{
562+ u32 ioh_pm_regval;
563+ u32 ioh_pins;
564+ u32 base_addr;
565+
566+ base_addr = ioh_gpio_base_address;
567+ ioh_pm_regval = IOH_READ_LONG(base_addr + IOH_PM);
568+ ioh_pins = gpio_reqt->pins;
569+
570+ /* input mode */
571+ if (gpio_reqt->mode == GPIO_IN) {
572+ IOH_DEBUG("ioh_gpio_dir_mode GPIO_IN\n");
573+ (ioh_pm_regval &= (~ioh_pins));
574+ } else {
575+ ioh_pm_regval |= ioh_pins;
576+ IOH_DEBUG("ioh_gpio_dir_mode GPIO_OUT\n");
577+ }
578+
579+ IOH_WRITE_LONG(ioh_pm_regval, (base_addr + IOH_PM));
580+ IOH_DEBUG("ioh_gpio_dir_mode wrote %x to IOH_PM\n", ioh_pm_regval);
581+}
582+
583+/*! @ingroup GPIO_HALLayerAPI
584+ @fn int ioh_gpio_read(struct ioh_gpio_reqt * gpio_reqt)
585+ @remarks Implements the register read functionality of the
586+ gpio module.
587+ The main tasks performed by this function are:
588+ - Reads the value from PI[Port Input] Register.
589+ Masks the value with 0xff and updates the value in
590+ gpio_reqt->pins
591+ (@ref ioh_gpio_reqt).
592+
593+ @param gpio_reqt [@ref INOUT]
594+ Contains the reference of the ioh_gpio_reqt structure
595+ @retval s32
596+ - @ref IOH_GPIO_SUCCESS -->
597+ If the operation is successful.
598+ @see
599+ - IOCTL_GPIO_READ
600+*/
601+s32 ioh_gpio_read(struct ioh_gpio_reqt *gpio_reqt)
602+{
603+
604+ gpio_reqt->pins =
605+ (ioh_gpio_bit_mask & IOH_READ_LONG(ioh_gpio_base_address + IOH_PI));
606+ return IOH_GPIO_SUCCESS;
607+
608+}
609+
610+/*! @ingroup GPIO_HALLayerAPI
611+@fn int ioh_gpio_write(struct ioh_gpio_reqt * gpio_reqt)
612+@remarks Implements the register write functionality of the gpio module.
613+ The main tasks performed by this function are:
614+- Masks gpio_reqt->pins (@ref ioh_gpio_reqt) with 0xFF to
615+ retrieve the valid 8 bits.
616+- Reads the current value of PO register
617+- If (gpio_reqt->mode == GPIO_LOW), performs logical AND
618+ between the present PM register value and the 1.s complement
619+ of gpio_reqt->pins and updates the value in the PO register.
620+- Else, (gpio_reqt->mode != GPIO_LOW; implies Output High), performs
621+ logical OR between the present PO register value and gpio_reqt->pins
622+ and updates the value in the PO register.
623+
624+ @param gpio_reqt [@ref INOUT]
625+ Contains the reference of the ioh_gpio_reqt structure
626+ @retval s32
627+ - @ref IOH_GPIO_SUCCESS
628+ --> If the operation is successful.
629+ @see
630+ - IOCTL_GPIO_WRITE
631+*/
632+s32 ioh_gpio_write(struct ioh_gpio_reqt *gpio_reqt)
633+{
634+ u32 reg_val;
635+
636+ reg_val = IOH_READ_LONG(ioh_gpio_base_address + IOH_PO);
637+
638+ if (gpio_reqt->mode == GPIO_LOW) {
639+ reg_val &= ~(gpio_reqt->pins);
640+ IOH_DEBUG("ioh_gpio_write GPIO_LOW\n");
641+ } else {
642+ reg_val |= gpio_reqt->pins;
643+ IOH_DEBUG("ioh_gpio_write GPIO_HIGH\n");
644+ }
645+
646+ IOH_WRITE_LONG(reg_val, ioh_gpio_base_address + IOH_PO);
647+ IOH_DEBUG("ioh_gpio_write writing value=%x\n", reg_val);
648+
649+ IOH_DEBUG("ioh_gpio_write returning %d\n", IOH_GPIO_SUCCESS);
650+ return IOH_GPIO_SUCCESS;
651+}
652+
653+/*! @ingroup GPIO_HALLayerAPI
654+@fn irqreturn_t ioh_gpio_handler(int irq,void * pData)
655+@remarks Implements the interrupt handler functionality of the gpio module.
656+The main tasks performed by this function are:
657+- Reads the IDISP register
658+- If IDISP register content is zero, then returns IRQ_NONE.
659+- Else clears the Interrupt status by writing to the ICLR register,
660+ invokes the call back function specified by @ref ioh_gpio_cbr
661+ with the value of IDISP as parameter and returns IRQ_HANDLED.
662+
663+@param irq [@ref INOUT] Contains the irq value
664+@param pData [@ref INOUT] Contains the reference to the base
665+ gpio address.
666+@retval irqreturn_t
667+ - IRQ_HANDLED --> If GPIO hardware is responsible
668+ for the interrupt.
669+ - IRQ_NONE --> Non-GPIO interrupt.
670+*/
671+irqreturn_t ioh_gpio_handler(int irq, void *pData)
672+{
673+ irqreturn_t ret = IRQ_NONE;
674+ u32 base_addr = ioh_gpio_base_address;
675+ u32 ioh_idisp_regval;
676+
677+ ioh_idisp_regval =
678+ (ioh_gpio_bit_mask & IOH_READ_LONG(base_addr + IOH_IDISP));
679+ if (ioh_idisp_regval != 0) {
680+ /*invoke the callback */
681+ (*ioh_gpio_cbr) (ioh_idisp_regval);
682+
683+ IOH_DEBUG
684+ ("ioh_gpio_handler : ioh_gpio_cb invoked successfully %d\n",
685+ ret);
686+ /*clear the interrupt */
687+ IOH_LOG(KERN_ERR, "Value at idisp 8 = %x",
688+ (IOH_READ_LONG(base_addr + IOH_IDISP)));
689+ IOH_LOG(KERN_ERR, "Value at pin 8 = %x",
690+ ((IOH_READ_LONG(base_addr + IOH_PI) & 0x80)));
691+
692+ IOH_WRITE_LONG(ioh_idisp_regval, (base_addr + IOH_ICLR));
693+
694+ ret = IRQ_HANDLED;
695+ IOH_DEBUG("ioh_gpio_handler returns IRQ_HANDLED\n");
696+ } else {
697+
698+ IOH_DEBUG("ioh_gpio_handler returns IRQ_NONE\n");
699+ }
700+ return ret;
701+}
702+
703+/*! @ingroup GPIO_HALLayerAPI
704+@fn void ioh_gpio_cb(u32 value)
705+@brief The interrupt handler callback function.
706+@remarks The main tasks performed by this function are:
707+ - Updates the GPIO event flag with the parameter value.
708+ This sets the appropriate event flag bits based on the
709+ bits set in IDISP register.
710+ - Wakes up the blocking ioctl call @ref IOCTL_GPIO_NOTIFY.
711+
712+@param value [@ref INOUT] Contains the value data
713+@retval None
714+@see
715+ - ioh_gpio_cb_register
716+*/
717+void ioh_gpio_cb(u32 value)
718+{
719+ /* update the event flag */
720+ ioh_gpio_event_flag = value;
721+
722+ IOH_DEBUG
723+ ("ioh_gpio_cb : event flag value = %x\tIDISP register value = %x\n",
724+ ioh_gpio_event_flag,
725+ (IOH_READ_LONG(ioh_gpio_base_address + IOH_IDISP)));
726+ wake_up_interruptible(&ioh_gpio_event);
727+}
728+
729+/*! @ingroup GPIO_HALLayerAPI
730+@fn void ioh_gpio_save_reg_conf(void)
731+@remarks Save register configuration and disable interrupts.
732+ The main tasks performed by this function are:
733+ - Read the registers PM, PO, IEN, IM0, IM1 and IMASK
734+ and stores the values for further use.
735+ - Disables the interrupts by clearing IEN register.
736+
737+@param None
738+@retval None
739+@see
740+ - ioh_gpio_suspend
741+*/
742+void ioh_gpio_save_reg_conf(void)
743+{
744+ u32 base_addr = ioh_gpio_base_address;
745+ IOH_DEBUG("ioh_gpio_save_reg_conf ENTRY\n");
746+ /* to store contents of IEN register */
747+ ioh_gpio_reg.ien_reg = IOH_READ_LONG(base_addr + IOH_IEN);
748+
749+ /* to store contents of IMASK register */
750+ ioh_gpio_reg.imask_reg = IOH_READ_LONG(base_addr + IOH_IMASK);
751+
752+ /* to store contents of PO register */
753+ ioh_gpio_reg.po_reg = IOH_READ_LONG(base_addr + IOH_PO);
754+
755+ /* to store contents of PM register */
756+ ioh_gpio_reg.pm_reg = IOH_READ_LONG(base_addr + IOH_PM);
757+
758+ /* to store contents of IM0 register */
759+ ioh_gpio_reg.im0_reg = IOH_READ_LONG(base_addr + IOH_IM0);
760+
761+ /* to store contents of IM1 register */
762+ ioh_gpio_reg.im1_reg = IOH_READ_LONG(base_addr + IOH_IM1);
763+
764+ IOH_DEBUG
765+ ("ioh_gpio_save_reg_conf : IOH_IEN=%x, IOH_IMASK=%x, IOH_PO=%x,"
766+ "IOH_PM=%x, IOH_IM0=%x, IOH_IM1=%x\n",
767+ IOH_READ_LONG(base_addr + IOH_IEN),
768+ IOH_READ_LONG(base_addr + IOH_IMASK),
769+ IOH_READ_LONG(base_addr + IOH_PO),
770+ IOH_READ_LONG(base_addr + IOH_PM),
771+ IOH_READ_LONG(base_addr + IOH_IM0),
772+ IOH_READ_LONG(base_addr + IOH_IM1));
773+
774+ IOH_DEBUG("ioh_gpio_save_reg_conf : ioh_gpio_reg.ien_reg=%x, "
775+ "ioh_gpio_reg.imask_reg=%x, ioh_gpio_reg.po_reg=%x,\
776+ ioh_gpio_reg.pm_reg=%x,"
777+ "ioh_gpio_reg.im0_reg=%x, ioh_gpio_reg.im1_reg=%x\n",
778+ ioh_gpio_reg.ien_reg, ioh_gpio_reg.imask_reg,
779+ ioh_gpio_reg.po_reg, ioh_gpio_reg.pm_reg,
780+ ioh_gpio_reg.im0_reg, ioh_gpio_reg.im1_reg);
781+
782+ /* Disable all gpio interrupts */
783+ IOH_WRITE_LONG(0, (base_addr + IOH_IEN));
784+ IOH_DEBUG("ioh_gpio_save_reg_conf disabled interrupts\n");
785+}
786+
787+/*! @ingroup GPIO_HALLayerAPI
788+@fn void ioh_gpio_restore_reg_conf(void)
789+@remarks This function restores the register configuration of the
790+ GPIO device. The main task performed by this function
791+ is:
792+ - Restores the previous register values into the registers
793+ PM, PO, IEN, IM0, IM1 and IMASK.
794+
795+@param None
796+@retval None
797+@see
798+ - ioh_gpio_resume
799+*/
800+void ioh_gpio_restore_reg_conf(void)
801+{
802+ u32 base_addr = ioh_gpio_base_address;
803+ IOH_DEBUG("ioh_gpio_restore_reg_conf ENTRY\n");
804+ /* to store contents of IEN register */
805+ IOH_WRITE_LONG(ioh_gpio_reg.ien_reg, base_addr + IOH_IEN);
806+
807+ /* to store contents of IMASK register */
808+ IOH_WRITE_LONG(ioh_gpio_reg.imask_reg, base_addr + IOH_IMASK);
809+
810+ /* to store contents of IMASK register */
811+ IOH_WRITE_LONG(~ioh_gpio_reg.imask_reg, base_addr + IOH_IMASKCLR);
812+
813+ /* to store contents of PO register */
814+ IOH_WRITE_LONG(ioh_gpio_reg.po_reg, base_addr + IOH_PO);
815+
816+ /* to store contents of PM register */
817+ IOH_WRITE_LONG(ioh_gpio_reg.pm_reg, base_addr + IOH_PM);
818+
819+ /* to store contents of IM0 register */
820+ IOH_WRITE_LONG(ioh_gpio_reg.im0_reg, base_addr + IOH_IM0);
821+
822+ /* to store contents of IM1 register */
823+ IOH_WRITE_LONG(ioh_gpio_reg.im1_reg, base_addr + IOH_IM1);
824+
825+ IOH_DEBUG
826+ ("ioh_gpio_save_reg_conf : ioh_gpio_reg.ien_reg=%x,\
827+ ioh_gpio_reg.imask_reg=%x,"\
828+ "ioh_gpio_reg.po_reg=%x, ioh_gpio_reg.pm_reg=%x,\
829+ ioh_gpio_reg.im0_reg=%x,"\
830+ "ioh_gpio_reg.im1_reg=%x\n", ioh_gpio_reg.ien_reg,
831+ ioh_gpio_reg.imask_reg, ioh_gpio_reg.po_reg, ioh_gpio_reg.pm_reg,
832+ ioh_gpio_reg.im0_reg, ioh_gpio_reg.im1_reg);
833+
834+ IOH_DEBUG
835+ ("ioh_gpio_save_reg_conf : IOH_IEN=%x, IOH_IMASK=%x, IOH_PO=%x,\
836+ IOH_PM=%x, IOH_IM0=%x, IOH_IM1=%x\n",\
837+ IOH_READ_LONG(base_addr + IOH_IEN),
838+ IOH_READ_LONG(base_addr + IOH_IMASK),
839+ IOH_READ_LONG(base_addr + IOH_PO),
840+ IOH_READ_LONG(base_addr + IOH_PM),
841+ IOH_READ_LONG(base_addr + IOH_IM0),
842+ IOH_READ_LONG(base_addr + IOH_IM1));
843+
844+ IOH_DEBUG("ioh_gpio_restore_reg_conf enabled interrupts\n");
845+}
846+
847+/*! @ingroup GPIO_HALLayerAPI
848+ @fn u32 ioh_gpio_readreg(int offset)
849+ @brief Reads the register.
850+ @remarks This function reads the register located at
851+ the passed offset and returns the read value.
852+ @param Offset [@reg IN] The offset to be read.
853+ @retval u32 --> Register value
854+
855+*/
856+u32 ioh_gpio_readreg(int offset)
857+{
858+ u32 reg_val;
859+ reg_val = (IOH_READ_LONG(ioh_gpio_base_address + offset));
860+ IOH_DEBUG("ioh_gpio_readreg read reg=%x,value=%x\n",
861+ (ioh_gpio_base_address + offset), reg_val);
862+ return reg_val;
863+}
864+
865+int ioh_gpio_writereg(int offset, u32 val)
866+{
867+ IOH_WRITE_LONG(val, ioh_gpio_base_address + offset);
868+ IOH_DEBUG("%s read reg=%x,value=%x\n", __func__,
869+ (ioh_gpio_base_address + offset), val);
870+ return 0;
871+}
872diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.h topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.h
873--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.h 1970-01-01 09:00:00.000000000 +0900
874+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_hal.h 2010-04-01 10:58:31.000000000 +0900
875@@ -0,0 +1,170 @@
876+/*!
877+ * @file ioh_gpio_hal.h
878+ * @brief Provides all the interfaces pertaining to the HAL.
879+ * @version 0.92
880+ * @section
881+ * This program is free software; you can redistribute it and/or modify
882+ * it under the terms of the GNU General Public License as published by
883+ * the Free Software Foundation; version 2 of the License.
884+ *
885+ * This program is distributed in the hope that it will be useful,
886+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
887+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
888+ * GNU General Public License for more details.
889+ *
890+ * You should have received a copy of the GNU General Public License
891+ * along with this program; if not, write to the Free Software
892+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
893+ */
894+
895+/*
896+ * History:
897+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
898+ * All rights reserved.
899+ *
900+ * created:
901+ * WIPRO 02/20/2009
902+ * modified:
903+ * WIPRO 01/05/2010
904+ * Added the interfaces provided by the HAL.
905+ *
906+ */
907+
908+#ifndef __IOH_GPIO_HAL_H__
909+#define __IOH_GPIO_HAL_H__
910+
911+/*! @ingroup GPIO_InterfaceLayer
912+ @def IOH_IEN
913+ @brief Offset for IEN register.
914+*/
915+#define IOH_IEN (0x00)
916+
917+/*! @ingroup GPIO_InterfaceLayer
918+ @def IOH_ISTATUS
919+ @brief Offset for ISTATUS register.
920+*/
921+#define IOH_ISTATUS (0x04)
922+
923+/*! @ingroup GPIO_InterfaceLayer
924+ @def IOH_IDISP
925+ @brief Offset for IDISP register.
926+*/
927+#define IOH_IDISP (0x08)
928+
929+/*! @ingroup GPIO_InterfaceLayer
930+ @def IOH_ICLR
931+ @brief Offset for ICLR register.
932+*/
933+#define IOH_ICLR (0x0C)
934+
935+/*! @ingroup GPIO_InterfaceLayer
936+ @def IOH_IMASK
937+ @brief Offset for IMASK register.
938+*/
939+#define IOH_IMASK (0x10)
940+
941+/*! @ingroup GPIO_InterfaceLayer
942+ @def IOH_IMASKCLR
943+ @brief Offset for IMASKCLR register.
944+*/
945+#define IOH_IMASKCLR (0x14)
946+
947+/*! @ingroup GPIO_InterfaceLayer
948+ @def IOH_PO
949+ @brief Offset for IMASKCLR register.
950+*/
951+#define IOH_PO (0x18)
952+
953+/*! @ingroup GPIO_InterfaceLayer
954+ @def IOH_PI
955+ @brief Offset for PI register.
956+*/
957+#define IOH_PI (0x1C)
958+
959+/*! @ingroup GPIO_InterfaceLayer
960+ @def IOH_PM
961+ @brief Offset for PM register.
962+*/
963+#define IOH_PM (0x20)
964+
965+/*! @ingroup GPIO_InterfaceLayer
966+ @def IOH_IM0
967+ @brief Offset for IM0 register.
968+*/
969+#define IOH_IM0 (0x24)
970+
971+/*! @ingroup GPIO_InterfaceLayer
972+ @def IOH_IM1
973+ @brief Offset for IM1 register.
974+*/
975+#define IOH_IM1 (0x28)
976+
977+/* exported function prototypes */
978+/*! @ingroup GPIO_HALLayerAPI
979+ @fn void ioh_gpio_cb(int)
980+ @brief Interrupt handler callback function
981+*/
982+void ioh_gpio_cb(u32);
983+
984+/*! @ingroup GPIO_HALLayerAPI
985+ @fn void ioh_gpio_cb_register(void(*ioh_gpio_cbr)(u32))
986+ @brief Interrupt handler callback register function
987+*/
988+void ioh_gpio_cb_register(void (*ioh_gpio_cbr) (u32));
989+
990+/*! @ingroup GPIO_HALLayerAPI
991+@fn s32 ioh_gpio_int_mode(struct ioh_gpio_reqt * gpio_reqt)
992+@brief This function sets the interrupt mode for each of the GPIO input pins
993+*/
994+s32 ioh_gpio_int_mode(struct ioh_gpio_reqt *gpio_reqt);
995+
996+/*! @ingroup GPIO_HALLayerAPI
997+@fn void ioh_gpio_dir_mode(struct ioh_gpio_reqt * gpio_reqt)
998+@brief Provides the functionality of setting gpio pin directions[input/output]
999+*/
1000+void ioh_gpio_dir_mode(struct ioh_gpio_reqt *gpio_reqt);
1001+
1002+/*! @ingroup GPIO_HALLayerAPI
1003+ @fn s32 ioh_gpio_read(struct ioh_gpio_reqt * gpio_reqt)
1004+ @brief Provides the functionality of reading GPIO pin status
1005+*/
1006+s32 ioh_gpio_read(struct ioh_gpio_reqt *gpio_reqt);
1007+
1008+/*! @ingroup GPIO_HALLayerAPI
1009+@fn s32 ioh_gpio_write(struct ioh_gpio_reqt * gpio_reqt)
1010+@brief Provides the functionality of writing data to the GPIO port
1011+*/
1012+s32 ioh_gpio_write(struct ioh_gpio_reqt *gpio_reqt);
1013+
1014+/*! @ingroup GPIO_HALLayerAPI
1015+@fn irqreturn_t ioh_gpio_handler(int irq,void * pData)
1016+@brief Provides the functionality of handling interrupts from GPIO h/w
1017+*/
1018+irqreturn_t ioh_gpio_handler(int irq, void *pData);
1019+
1020+/*! @ingroup GPIO_HALLayerAPI
1021+@fn void ioh_gpio_save_reg_conf(void)
1022+@brief Saves register configuration and also disables GPIO interrupts
1023+*/
1024+void ioh_gpio_save_reg_conf(void);
1025+
1026+/*! @ingroup GPIO_HALLayerAPI
1027+ @fn void ioh_gpio_restore_reg_conf(void)
1028+ @brief Restores register configuration
1029+*/
1030+void ioh_gpio_restore_reg_conf(void);
1031+
1032+/*! @ingroup GPIO_HALLayerAPI
1033+ @fn u32 ioh_gpio_readreg(int offset)
1034+ @brief Function to read the value of a GPIO register
1035+*/
1036+u32 ioh_gpio_readreg(int offset);
1037+int ioh_gpio_writereg(int offset, u32 val);
1038+
1039+/* global variables */
1040+extern u32 ioh_gpio_base_address;
1041+extern u32 ioh_gpio_event_flag;
1042+extern wait_queue_head_t ioh_gpio_event;
1043+extern u32 ioh_gpio_bit_mask;
1044+
1045+#endif
1046diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.c topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.c
1047--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.c 1970-01-01 09:00:00.000000000 +0900
1048+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.c 2010-04-01 11:41:01.000000000 +0900
1049@@ -0,0 +1,420 @@
1050+/*!
1051+ * @file ioh_gpio_main.c
1052+ * @brief Provides all the implementation of the interfaces pertaining to the
1053+ * GPIO module.
1054+ * @version 0.92
1055+ * @section
1056+ * This program is free software; you can redistribute it and/or modify
1057+ * it under the terms of the GNU General Public License as published by
1058+ * the Free Software Foundation; version 2 of the License.
1059+ *
1060+ * This program is distributed in the hope that it will be useful,
1061+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1062+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1063+ * GNU General Public License for more details.
1064+ *
1065+ * You should have received a copy of the GNU General Public License
1066+ * along with this program; if not, write to the Free Software
1067+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1068+ */
1069+
1070+/*
1071+ * History:
1072+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
1073+ * All rights reserved.
1074+ *
1075+ * created:
1076+ * WIPRO 02/20/2009
1077+ * modified:
1078+ * WIPRO 01/05/2010
1079+ * Added the interfaces provided by the GPIO module.
1080+ *
1081+ */
1082+
1083+/* includes */
1084+
1085+#include <linux/module.h>
1086+#include <linux/kernel.h>
1087+#include <linux/types.h>
1088+#include <linux/fs.h>
1089+#include <linux/interrupt.h>
1090+#include <linux/uaccess.h>
1091+#include <linux/string.h>
1092+#include <linux/sched.h>
1093+
1094+#include "pch_common.h"
1095+#include "pch_debug.h"
1096+#include "pch_gpio_main.h"
1097+#include "pch_gpio_hal.h"
1098+
1099+#define MODULE_NAME "ioh_gpio"
1100+
1101+DEFINE_SPINLOCK(ioh_gpio_lock); /* for spin lock */
1102+u32 ioh_gpio_event_flag; /* flag for event */
1103+s32 ioh_gpio_opencount; /* check whether opened or not */
1104+
1105+/*spinlock_t ioh_gpio_lock = SPIN_LOCK_UNLOCKED; for spin lock */
1106+wait_queue_head_t ioh_gpio_event; /* wait queue head */
1107+
1108+/*! @ingroup GPIO_InterfaceLayerFacilitators
1109+ @struct ioh_gpio_fops
1110+ @brief Instance of the Kernel structure file_operations.
1111+*/
1112+const struct file_operations ioh_gpio_fops = {
1113+ .owner = THIS_MODULE,
1114+ .open = ioh_gpio_open,
1115+ .release = ioh_gpio_release,
1116+ .ioctl = ioh_gpio_ioctl,
1117+};
1118+
1119+/*function implementations*/
1120+
1121+/*! @ingroup GPIO_InterfaceLayerAPI
1122+@fn int ioh_gpio_open( struct inode *inode,struct file *file)
1123+@remarks The main tasks performed by this function are:
1124+- Ensures that the device is not opened before by checking the open count.
1125+ If it is already opened, then returns EBUSY status code.
1126+- Registers the interrupt handler by invoking request_irq.
1127+ If this fails then returns its error code.
1128+ Otherwise returns @ref IOH_GPIO_SUCCESS
1129+
1130+@param inode [@ref INOUT] Contains the reference of the inode structure
1131+@param file [@ref INOUT] Contains the reference of the file structure
1132+@retval int
1133+ - @ref IOH_GPIO_SUCCESS --> If operation is successful.
1134+ - -EBUSY --> If already opened/ request_irq
1135+ error status code.
1136+ - -EINVAL --> request_irq error status code.
1137+ - -ENOMEM --> request_irq error status code.
1138+ - -ENOSYS --> request_irq error status code.
1139+
1140+@see
1141+ - ioh_gpio_fops
1142+*/
1143+int ioh_gpio_open(struct inode *inode, struct file *file)
1144+{
1145+ int ret;
1146+
1147+ spin_lock(&ioh_gpio_lock);
1148+ IOH_DEBUG("ioh_gpio_open : open count value = %d", ioh_gpio_opencount);
1149+ if (ioh_gpio_opencount) {
1150+ IOH_LOG(KERN_ERR, "ioh_gpio_open : device already opened\n");
1151+ ret = -EBUSY;
1152+ } else {
1153+
1154+ ret =
1155+ (request_irq
1156+ (ioh_gpio_irq, &ioh_gpio_handler, IRQF_SHARED, MODULE_NAME,
1157+ (void *)ioh_gpio_base_address));
1158+ if (ret) {
1159+ IOH_LOG(KERN_ERR,
1160+ "ioh_gpio_open : request_irq failed\n");
1161+ } else {
1162+ ioh_gpio_opencount++;
1163+ IOH_DEBUG
1164+ ("ioh_gpio_open : request_irq invoked\
1165+ successfully\n");
1166+ ret = IOH_GPIO_SUCCESS;
1167+ }
1168+ }
1169+ spin_unlock(&ioh_gpio_lock);
1170+
1171+ IOH_DEBUG("ioh_gpio_open returns=%d\n", ret);
1172+ return ret;
1173+}
1174+
1175+/*! @ingroup GPIO_InterfaceLayerAPI
1176+@fn int ioh_gpio_release(struct inode *inode,struct file *file)
1177+@remarks The main tasks performed by this function are:
1178+-Ensures that device is opened successfully by checking the open count value.
1179+ If it is not opened, then returns with IOH_GPIO_SUCCESS status code.
1180+-Disables interrupts for all pins by using @ref ioh_gpio_int_mode
1181+ API.
1182+-Un-registers interrupt handler and returns @ref IOH_GPIO_SUCCESS.
1183+
1184+@param inode [@ref INOUT] Contains the reference of the inode structure
1185+@param file [@ref INOUT] Contains the reference of the file structure
1186+@retval int
1187+ - @ref IOH_GPIO_SUCCESS -->
1188+ If the operation is successful.
1189+@see
1190+ - ioh_gpio_fops
1191+*/
1192+int ioh_gpio_release(struct inode *inode, struct file *file)
1193+{
1194+ struct ioh_gpio_reqt req;
1195+ spin_lock(&ioh_gpio_lock);
1196+
1197+ if (ioh_gpio_opencount > 0) {
1198+ memset(&req, 0, sizeof(req));
1199+ req.pins = IOH_GPIO_ALL_PINS;
1200+
1201+ /* disable interrupts for all gpio pins */
1202+ (void)ioh_gpio_int_mode(&req);
1203+
1204+ free_irq(ioh_gpio_irq, (void *)ioh_gpio_base_address);
1205+ IOH_DEBUG("ioh_gpio_release : free_irq invoked successfully");
1206+
1207+ ioh_gpio_opencount--;
1208+ }
1209+ spin_unlock(&ioh_gpio_lock);
1210+
1211+ IOH_DEBUG("ioh_gpio_release : ioh_gpio_opencount =%d\n",
1212+ ioh_gpio_opencount);
1213+
1214+ IOH_DEBUG("ioh_gpio_release returning=%d\n", IOH_GPIO_SUCCESS);
1215+ return IOH_GPIO_SUCCESS;
1216+}
1217+
1218+/*! @ingroup GPIO_InterfaceLayerAPI
1219+@fn int ioh_gpio_ioctl(struct inode * inode,struct file * file,
1220+ unsigned int cmd,unsigned long arg)
1221+@remarks The main tasks performed by this function are:
1222+ - Copies the arg from user space to kernel space.
1223+ If this fails, returns EFAULT status code.
1224+ - Checks the cmd specified. If not a valid command,
1225+ returns EINVAL status code.
1226+ - Verifies the validity of the command argument based on
1227+ the operation requested. If invalid, returns EINVAL.
1228+ - Performs the requested action based on the ioctl command,
1229+ by calling the appropriate HAL API functions.
1230+ - Returns @ref IOH_GPIO_SUCCESS if the command is completed
1231+ successfully.
1232+
1233+@param inode [@ref INOUT] Contains the reference of the inode structure
1234+@param file [@ref INOUT] Contains the reference of the file structure
1235+@param cmd [@ref IN] Contains the command value
1236+@param arg [@ref IN] Contains the command argument value
1237+@retval int
1238+- @ref IOH_GPIO_SUCCES --> If the operation is successful.
1239+- -EFAULT --> wait_event_interruptible API
1240+ is interrupted by a signal.
1241+- -ERESTARTSYS --> wait_event_interruptible API
1242+ is interrupted by a signal.
1243+- -EINVAL --> Invalid address/parameter.
1244+
1245+@see
1246+ - ioh_gpio_fops
1247+*/
1248+int ioh_gpio_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1249+ unsigned long arg)
1250+{
1251+
1252+ struct ioh_gpio_reqt gpio_reqt;
1253+ s32 ret_value;
1254+
1255+ IOH_DEBUG(KERN_INFO"%s:cmd = 0x%x\n", __func__, cmd);
1256+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_INT_ENABLE= 0x%x\n", __func__,
1257+ IOCTL_GPIO_INT_ENABLE);
1258+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_INT_DISABLE= 0x%x\n", __func__,
1259+ IOCTL_GPIO_INT_DISABLE);
1260+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_DIRECTION= 0x%x\n", __func__,
1261+ IOCTL_GPIO_DIRECTION);
1262+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_WRITE= 0x%x\n", __func__,
1263+ IOCTL_GPIO_WRITE);
1264+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_READ= 0x%x\n", __func__,
1265+ IOCTL_GPIO_READ);
1266+ IOH_DEBUG(KERN_INFO"%s: IOCTL_GPIO_NOTIFY= 0x%x\n", __func__,
1267+ IOCTL_GPIO_NOTIFY);
1268+
1269+ do {
1270+ if (ioh_gpio_suspended == true) {
1271+ IOH_LOG(KERN_ERR,
1272+ "ioh_gpio_ioctl : suspend initiated returning\
1273+ =%d\n",
1274+ IOH_GPIO_FAIL);
1275+ ret_value = IOH_GPIO_FAIL;
1276+ break;
1277+ }
1278+
1279+ ret_value =
1280+ copy_from_user(&gpio_reqt, (void *)arg,
1281+ sizeof(struct ioh_gpio_reqt));
1282+ if (ret_value) {
1283+ IOH_LOG(KERN_ERR,
1284+ "ioh_gpio_ioctl : copy_from_user fail returning\
1285+ =%d\n",
1286+ -EFAULT);
1287+ ret_value = -EFAULT;
1288+ break;
1289+ }
1290+ IOH_DEBUG("ioh_gpio_ioctl : copy_from_user returns =%d\n",
1291+ ret_value);
1292+
1293+ if (((gpio_reqt.enable) > 1)
1294+ || ((gpio_reqt.pins) > GPIO_MAX_PINS_MASK)
1295+ || ((gpio_reqt.port) > GPIO_NUM_PORT_MAX)) {
1296+ IOH_LOG(KERN_ERR,
1297+ "ioh_gpio_ioctl : Invalid parameter\
1298+ returning=%d\n",
1299+ -EINVAL);
1300+ ret_value = -EINVAL;
1301+ break;
1302+ }
1303+ switch (cmd) {
1304+ case IOCTL_GPIO_INT_ENABLE:
1305+ {
1306+
1307+ if (gpio_reqt.enable == 0) {
1308+ ret_value = -EINVAL;
1309+ IOH_DEBUG
1310+ ("ioh_gpio_ioctl : Invalid\
1311+ parameter in enable\n");
1312+ } else {
1313+ ret_value =
1314+ ioh_gpio_int_mode(&gpio_reqt);
1315+ IOH_DEBUG
1316+ ("ioh_gpio_ioctl : Invoked\
1317+ ioh_gpio_int_mode successfully\n");
1318+ }
1319+ break;
1320+ }
1321+
1322+ case IOCTL_GPIO_INT_DISABLE:
1323+ {
1324+ if (gpio_reqt.enable != 0) {
1325+ ret_value = -EINVAL;
1326+ IOH_DEBUG
1327+ ("ioh_gpio_ioctl : Invalid\
1328+ parameter in enable\n");
1329+ } else {
1330+ ret_value =
1331+ ioh_gpio_int_mode(&gpio_reqt);
1332+ IOH_DEBUG
1333+ ("ioh_gpio_ioctl : Invoked\
1334+ ioh_gpio_int_mode successfully\n");
1335+ }
1336+ break;
1337+ }
1338+
1339+ case IOCTL_GPIO_DIRECTION:
1340+ {
1341+ if ((gpio_reqt.mode > 1)) {
1342+
1343+ IOH_DEBUG
1344+ ("ioh_gpio_ioctl : Invalid\
1345+ direction\n");
1346+ ret_value = -EINVAL;
1347+ } else {
1348+ ioh_gpio_dir_mode(&gpio_reqt);
1349+ IOH_DEBUG
1350+ ("ioh_gpio_ioctl : Invoked\
1351+ ioh_gpio_dir_mode successfully\n");
1352+ ret_value = IOH_GPIO_SUCCESS;
1353+ }
1354+ break;
1355+ }
1356+
1357+ case IOCTL_GPIO_WRITE:
1358+ {
1359+ ret_value = ioh_gpio_write(&gpio_reqt);
1360+ IOH_DEBUG
1361+ ("ioh_gpio_ioctl : Invoked\
1362+ ioh_gpio_write_mode successfully\n");
1363+ break;
1364+ }
1365+
1366+ case IOCTL_GPIO_READ:
1367+ {
1368+ (void)ioh_gpio_read(&gpio_reqt);
1369+ IOH_DEBUG
1370+ ("ioh_gpio_ioctl : Invoked\
1371+ ioh_gpio_read_mode successfully\n");
1372+ ret_value =
1373+ copy_to_user((void *)arg, &gpio_reqt,
1374+ sizeof(struct ioh_gpio_reqt));
1375+
1376+ if (ret_value) {
1377+ IOH_LOG(KERN_ERR,
1378+ "ioh_gpio_ioctl copy_to_user\
1379+ failed returning=%d\n",
1380+ -EFAULT);
1381+ ret_value = -EFAULT;
1382+ } else {
1383+ IOH_DEBUG
1384+ ("ioh_gpio_ioctl copy_to_user\
1385+ returns=%d\n",
1386+ ret_value);
1387+ ret_value = IOH_GPIO_SUCCESS;
1388+ }
1389+ break;
1390+ }
1391+
1392+ case IOCTL_GPIO_NOTIFY:
1393+ {
1394+ ioh_gpio_event_flag = 0;
1395+ if ((((ioh_gpio_readreg(IOH_IEN)) &
1396+ (gpio_reqt.pins)) != (gpio_reqt.pins))
1397+ ||
1398+ (((ioh_gpio_readreg(IOH_PM) &
1399+ (gpio_reqt.pins)) != false))) {
1400+ /* if interrupts are not enabled on the
1401+ pins for which notify is requested */
1402+ /* or the pins are not in input mode */
1403+ IOH_DEBUG
1404+ ("ioh_gpio_ioctl GPIO pins not in\
1405+ input mode or interrupts\
1406+ not enabled!");
1407+ ret_value = -EINVAL;
1408+ } else {
1409+ ret_value =
1410+ wait_event_interruptible
1411+ (ioh_gpio_event,
1412+ (ioh_gpio_event_flag & gpio_reqt.
1413+ pins) != 0);
1414+ if (ret_value) {
1415+ IOH_LOG(KERN_ERR,
1416+ "ioh_gpio_ioctl wait_ev\
1417+ ent_interruptible\
1418+ failed returning=%d\n",
1419+ -ERESTARTSYS);
1420+ ret_value = -ERESTARTSYS;
1421+ } else {
1422+ IOH_DEBUG
1423+ ("ioh_gpio_ioctl wait_event\
1424+ _interruptible returns=%d\n",
1425+ ret_value);
1426+ (void)ioh_gpio_read(&gpio_reqt);
1427+ ret_value =
1428+ copy_to_user((void *)arg,
1429+ &gpio_reqt,
1430+ sizeof(struct
1431+ ioh_gpio_reqt));
1432+ if (ret_value) {
1433+ IOH_LOG(KERN_ERR,
1434+ "ioh_gpio_ioctl\
1435+ copy_to_user\
1436+ failed returni\
1437+ ng=%d\n",
1438+ -EFAULT);
1439+ ret_value = -EFAULT;
1440+ } else {
1441+ IOH_DEBUG
1442+ ("ioh_gpio_ioctl\
1443+ copy_to_user\
1444+ returns=%d\n",
1445+ ret_value);
1446+ ret_value =
1447+ IOH_GPIO_SUCCESS;
1448+ }
1449+ }
1450+ }
1451+ break;
1452+ }
1453+
1454+ default:
1455+ {
1456+ IOH_LOG(KERN_ERR,
1457+ "ioh_gpio_ioctl invalid command\
1458+ returning=%d\n",
1459+ -EINVAL);
1460+ ret_value = -EINVAL;
1461+ break;
1462+ }
1463+ }
1464+ break;
1465+
1466+ } while (0);
1467+ IOH_LOG(KERN_ERR, "ioh_gpio_ioctl returns=%d\n", ret_value);
1468+ return ret_value;
1469+}
1470diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.h topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.h
1471--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.h 1970-01-01 09:00:00.000000000 +0900
1472+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_main.h 2010-04-01 10:58:31.000000000 +0900
1473@@ -0,0 +1,686 @@
1474+#ifndef __IOH_GPIO_MAIN_H__
1475+#define __IOH_GPIO_MAIN_H__
1476+/*!
1477+ * @file ioh_gpio_main.h
1478+ * @brief Provides all the interfaces pertaining to the GPIO module.
1479+ * @version 0.92
1480+ * @section
1481+ * This program is free software; you can redistribute it and/or modify
1482+ * it under the terms of the GNU General Public License as published by
1483+ * the Free Software Foundation; version 2 of the License.
1484+ *
1485+ * This program is distributed in the hope that it will be useful,
1486+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1487+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1488+ * GNU General Public License for more details.
1489+ *
1490+ * You should have received a copy of the GNU General Public License
1491+ * along with this program; if not, write to the Free Software
1492+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1493+*/
1494+
1495+/*
1496+ * History:
1497+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
1498+ * All rights reserved.
1499+ *
1500+ * created:
1501+ * WIPRO 02/20/2009
1502+ * modified:
1503+ * WIPRO 01/05/2010
1504+ * Added the interfaces provided by the gpio module.
1505+ *
1506+*/
1507+
1508+/*! @defgroup GPIO*/
1509+/*! @defgroup GPIO_Global
1510+ @ingroup GPIO*/
1511+
1512+/* @defgroup GlobalGeneral
1513+ @ingroup GPIO_Global*/
1514+/* @defgroup GlobalResultCodes
1515+ @ingroup GPIO_Global*/
1516+
1517+/*! @defgroup GPIO_InterfaceLayer
1518+ @ingroup GPIO*/
1519+/*! @defgroup GPIO_InterfaceLayerAPI
1520+ @ingroup GPIO_InterfaceLayer
1521+*/
1522+
1523+/* @defgroup InterfaceLayerNotifyRoutines
1524+ @ingroup GPIO_InterfaceLayer
1525+*/
1526+
1527+/*! @defgroup GPIO_PCILayer
1528+ @ingroup GPIO*/
1529+/*! @defgroup GPIO_PCILayerAPI
1530+ @ingroup GPIO_PCILayer
1531+*/
1532+/*! @defgroup GPIO_PCILayerFacilitators
1533+ @ingroup GPIO_PCILayer
1534+*/
1535+/*! @defgroup GPIO_HALLayer
1536+ @ingroup GPIO*/
1537+/*! @defgroup GPIO_HALLayerAPI
1538+ @ingroup GPIO_HALLayer
1539+*/
1540+
1541+/* @defgroup HALLayerFacilitators
1542+ @ingroup GPIO_HALLayer
1543+*/
1544+
1545+/*! @ingroup GPIO_InterfaceLayer
1546+ @def GPIO_IOCTL_MAGIC
1547+ @brief The ioctl magic number.
1548+*/
1549+#define GPIO_IOCTL_MAGIC (0xf7)
1550+
1551+/*! @ingroup GPIO_InterfaceLayer
1552+ @def IOCTL_GPIO_INT_ENABLE
1553+ @brief IOCTL for GPIO interrupt enable.
1554+*/
1555+#define IOCTL_GPIO_INT_ENABLE (_IOW(GPIO_IOCTL_MAGIC, 1, struct ioh_gpio_reqt))
1556+
1557+/*! @ingroup GPIO_InterfaceLayer
1558+ @def IOCTL_GPIO_INT_DISABLE
1559+ @brief IOCTL for GPIO interrupt disable.
1560+*/
1561+#define IOCTL_GPIO_INT_DISABLE (_IOW(GPIO_IOCTL_MAGIC, 2, struct ioh_gpio_reqt))
1562+
1563+/*! @ingroup GPIO_InterfaceLayer
1564+ @def IOCTL_GPIO_DIRECTION
1565+ @brief IOCTL for GPIO direction setting.
1566+*/
1567+#define IOCTL_GPIO_DIRECTION (_IOW(GPIO_IOCTL_MAGIC, 3, struct ioh_gpio_reqt))
1568+
1569+/*! @ingroup GPIO_InterfaceLayer
1570+ @def IOCTL_GPIO_WRITE
1571+ @brief IOCTL for GPIO write.
1572+*/
1573+#define IOCTL_GPIO_WRITE (_IOW(GPIO_IOCTL_MAGIC, 4, struct ioh_gpio_reqt))
1574+
1575+/*! @ingroup GPIO_InterfaceLayer
1576+ @def IOCTL_GPIO_READ
1577+ @brief IOCTL for GPIO read.
1578+*/
1579+#define IOCTL_GPIO_READ (_IOR(GPIO_IOCTL_MAGIC, 5, struct ioh_gpio_reqt))
1580+
1581+/*! @ingroup GPIO_InterfaceLayer
1582+ @def IOCTL_GPIO_NOTIFY
1583+ @brief IOCTL for GPIO pin status change notification.
1584+*/
1585+#define IOCTL_GPIO_NOTIFY (_IOR(GPIO_IOCTL_MAGIC, 6, struct ioh_gpio_reqt))
1586+
1587+/*! @ingroup GPIO_InterfaceLayer
1588+ @def IOH_GPIO_PIN0
1589+ @brief GPIO PIN 0
1590+*/
1591+#define IOH_GPIO_PIN0 (0x1)
1592+
1593+/*! @ingroup GPIO_InterfaceLayer
1594+ @def IOH_GPIO_PIN1
1595+ @brief GPIO PIN 1
1596+*/
1597+#define IOH_GPIO_PIN1 (0x2)
1598+
1599+/*! @ingroup GPIO_InterfaceLayer
1600+ @def IOH_GPIO_PIN2
1601+ @brief GPIO PIN 2
1602+*/
1603+#define IOH_GPIO_PIN2 (0x4)
1604+
1605+/*! @ingroup GPIO_InterfaceLayer
1606+ @def IOH_GPIO_PIN3
1607+ @brief GPIO PIN 3
1608+*/
1609+#define IOH_GPIO_PIN3 (0x8)
1610+
1611+/*! @ingroup GPIO_InterfaceLayer
1612+ @def IOH_GPIO_PIN4
1613+ @brief GPIO PIN 4
1614+*/
1615+#define IOH_GPIO_PIN4 (0x10)
1616+
1617+/*! @ingroup GPIO_InterfaceLayer
1618+ @def IOH_GPIO_PIN5
1619+ @brief GPIO PIN 5
1620+*/
1621+#define IOH_GPIO_PIN5 (0x20)
1622+
1623+/*! @ingroup GPIO_InterfaceLayer
1624+ @def IOH_GPIO_PIN6
1625+ @brief GPIO PIN 6
1626+*/
1627+#define IOH_GPIO_PIN6 (0x40)
1628+
1629+/*! @ingroup GPIO_InterfaceLayer
1630+ @def IOH_GPIO_PIN7
1631+ @brief GPIO PIN 7
1632+*/
1633+#define IOH_GPIO_PIN7 (0x80)
1634+
1635+/*! @ingroup GPIO_InterfaceLayer
1636+ @def IOH_GPIO_PIN8
1637+ @brief GPIO PIN 8
1638+*/
1639+#define IOH_GPIO_PIN8 (0x100)
1640+
1641+/*! @ingroup GPIO_InterfaceLayer
1642+ @def IOH_GPIO_PIN9
1643+ @brief GPIO PIN 9
1644+*/
1645+#define IOH_GPIO_PIN9 (0x200)
1646+
1647+/*! @ingroup GPIO_InterfaceLayer
1648+ @def IOH_GPIO_PIN10
1649+ @brief GPIO PIN 10
1650+*/
1651+#define IOH_GPIO_PIN10 (0x400)
1652+
1653+/*! @ingroup GPIO_InterfaceLayer
1654+ @def IOH_GPIO_PIN11
1655+ @brief GPIO PIN 11
1656+*/
1657+#define IOH_GPIO_PIN11 (0x800)
1658+
1659+/*! @ingroup GPIO_InterfaceLayer
1660+ @def IOH_GPIO_ALL_PINS
1661+ @brief Mask for GPIO pins 0 to 11
1662+*/
1663+#define IOH_GPIO_ALL_PINS (IOH_GPIO_PIN0 | IOH_GPIO_PIN1 | IOH_GPIO_PIN2\
1664+| IOH_GPIO_PIN3 | IOH_GPIO_PIN4 | IOH_GPIO_PIN5 | IOH_GPIO_PIN6 | IOH_GPIO_PIN7\
1665+| IOH_GPIO_PIN8 | IOH_GPIO_PIN9 | IOH_GPIO_PIN10 | IOH_GPIO_PIN11)
1666+
1667+/*! @ingroup GPIO_InterfaceLayer
1668+ @def INT_FL_EDG_PIN0
1669+ @brief Falling Edge interrupt on Pin0
1670+*/
1671+#define INT_FL_EDG_PIN0 (0x0)
1672+
1673+/*! @ingroup GPIO_InterfaceLayer
1674+ @def INT_FL_EDG_PIN1
1675+ @brief Falling Edge interrupt on Pin1
1676+*/
1677+#define INT_FL_EDG_PIN1 (0x0)
1678+
1679+/*! @ingroup GPIO_InterfaceLayer
1680+ @def INT_FL_EDG_PIN2
1681+ @brief Falling Edge interrupt on Pin2
1682+*/
1683+#define INT_FL_EDG_PIN2 (0x0)
1684+
1685+/*! @ingroup GPIO_InterfaceLayer
1686+ @def INT_FL_EDG_PIN3
1687+ @brief Falling Edge interrupt on Pin3
1688+*/
1689+#define INT_FL_EDG_PIN3 (0x0)
1690+
1691+/*! @ingroup GPIO_InterfaceLayer
1692+ @def INT_FL_EDG_PIN4
1693+ @brief Falling Edge interrupt on Pin4
1694+*/
1695+#define INT_FL_EDG_PIN4 (0x0)
1696+
1697+/*! @ingroup GPIO_InterfaceLayer
1698+ @def INT_FL_EDG_PIN5
1699+ @brief Falling Edge interrupt on Pin5
1700+*/
1701+#define INT_FL_EDG_PIN5 (0x0)
1702+
1703+/*! @ingroup GPIO_InterfaceLayer
1704+ @def INT_FL_EDG_PIN6
1705+ @brief Falling Edge interrupt on Pin6
1706+*/
1707+#define INT_FL_EDG_PIN6 (0x0)
1708+
1709+/*! @ingroup GPIO_InterfaceLayer
1710+ @def INT_FL_EDG_PIN7
1711+ @brief Falling Edge interrupt on Pin7
1712+*/
1713+#define INT_FL_EDG_PIN7 (0x0)
1714+
1715+/*! @ingroup GPIO_InterfaceLayer
1716+ @def INT_FL_EDG_PIN8
1717+ @brief Falling Edge interrupt on Pin8
1718+*/
1719+#define INT_FL_EDG_PIN8 (0x0)
1720+
1721+/*! @ingroup GPIO_InterfaceLayer
1722+ @def INT_FL_EDG_PIN9
1723+ @brief Falling Edge interrupt on Pin9
1724+*/
1725+#define INT_FL_EDG_PIN9 (0x0)
1726+
1727+/*! @ingroup GPIO_InterfaceLayer
1728+ @def INT_FL_EDG_PIN10
1729+ @brief Falling Edge interrupt on Pin10
1730+*/
1731+#define INT_FL_EDG_PIN10 (0x0)
1732+
1733+/*! @ingroup GPIO_InterfaceLayer
1734+ @def INT_FL_EDG_PIN11
1735+ @brief Falling Edge interrupt on Pin11
1736+*/
1737+#define INT_FL_EDG_PIN11 (0x0)
1738+
1739+/*! @ingroup GPIO_InterfaceLayer
1740+ @def INT_RS_EDG_PIN0
1741+ @brief Rising Edge interrupt on Pin0
1742+*/
1743+#define INT_RS_EDG_PIN0 (0x1)
1744+
1745+/*! @ingroup GPIO_InterfaceLayer
1746+ @def INT_RS_EDG_PIN1
1747+ @brief Rising Edge interrupt on Pin1
1748+*/
1749+#define INT_RS_EDG_PIN1 (0x10)
1750+
1751+/*! @ingroup GPIO_InterfaceLayer
1752+ @def INT_RS_EDG_PIN2
1753+ @brief Rising Edge interrupt on Pin2
1754+*/
1755+#define INT_RS_EDG_PIN2 (0x100)
1756+
1757+/*! @ingroup GPIO_InterfaceLayer
1758+ @def INT_RS_EDG_PIN3
1759+ @brief Rising Edge interrupt on Pin3
1760+*/
1761+#define INT_RS_EDG_PIN3 (0x1000)
1762+
1763+/*! @ingroup GPIO_InterfaceLayer
1764+ @def INT_RS_EDG_PIN4
1765+ @brief Rising Edge interrupt on Pin4
1766+*/
1767+#define INT_RS_EDG_PIN4 (0x10000)
1768+
1769+/*! @ingroup GPIO_InterfaceLayer
1770+ @def INT_RS_EDG_PIN5
1771+ @brief Rising Edge interrupt on Pin5
1772+*/
1773+#define INT_RS_EDG_PIN5 (0x100000)
1774+
1775+/*! @ingroup GPIO_InterfaceLayer
1776+ @def INT_RS_EDG_PIN6
1777+ @brief Rising Edge interrupt on Pin6
1778+*/
1779+#define INT_RS_EDG_PIN6 (0x1000000)
1780+
1781+/*! @ingroup GPIO_InterfaceLayer
1782+ @def INT_RS_EDG_PIN7
1783+ @brief Rising Edge interrupt on Pin7
1784+*/
1785+#define INT_RS_EDG_PIN7 (0x10000000)
1786+
1787+/*! @ingroup GPIO_InterfaceLayer
1788+ @def INT_RS_EDG_PIN8
1789+ @brief Rising Edge interrupt on Pin8
1790+*/
1791+#define INT_RS_EDG_PIN8 ((0x100000000ULL))
1792+
1793+/*! @ingroup GPIO_InterfaceLayer
1794+ @def INT_RS_EDG_PIN9
1795+ @brief Rising Edge interrupt on Pin9
1796+*/
1797+#define INT_RS_EDG_PIN9 ((0x1000000000ULL))
1798+
1799+/*! @ingroup GPIO_InterfaceLayer
1800+ @def INT_RS_EDG_PIN10
1801+ @brief Rising Edge interrupt on Pin10
1802+*/
1803+#define INT_RS_EDG_PIN10 ((0x10000000000ULL))
1804+
1805+/*! @ingroup GPIO_InterfaceLayer
1806+ @def INT_RS_EDG_PIN11
1807+ @brief Rising Edge interrupt on Pin11
1808+*/
1809+#define INT_RS_EDG_PIN11 ((0x100000000000ULL))
1810+
1811+/*! @ingroup GPIO_InterfaceLayer
1812+ @def INT_LVL_LO_PIN0
1813+ @brief Low Level Interrupt on Pin0
1814+*/
1815+#define INT_LVL_LO_PIN0 (0x2)
1816+
1817+/*! @ingroup GPIO_InterfaceLayer
1818+ @def INT_LVL_LO_PIN1
1819+ @brief Low Level Interrupt on Pin1
1820+*/
1821+#define INT_LVL_LO_PIN1 (0x20)
1822+
1823+/*! @ingroup GPIO_InterfaceLayer
1824+ @def INT_LVL_LO_PIN2
1825+ @brief Low Level Interrupt on Pin2
1826+*/
1827+#define INT_LVL_LO_PIN2 (0x200)
1828+
1829+/*! @ingroup GPIO_InterfaceLayer
1830+ @def INT_LVL_LO_PIN3
1831+ @brief Low Level Interrupt on Pin3
1832+*/
1833+#define INT_LVL_LO_PIN3 (0x2000)
1834+
1835+/*! @ingroup GPIO_InterfaceLayer
1836+ @def INT_LVL_LO_PIN4
1837+ @brief Low Level Interrupt on Pin4
1838+*/
1839+#define INT_LVL_LO_PIN4 (0x20000)
1840+
1841+/*! @ingroup GPIO_InterfaceLayer
1842+ @def INT_LVL_LO_PIN5
1843+ @brief Low Level Interrupt on Pin5
1844+*/
1845+#define INT_LVL_LO_PIN5 (0x200000)
1846+
1847+/*! @ingroup GPIO_InterfaceLayer
1848+ @def INT_LVL_LO_PIN6
1849+ @brief Low Level Interrupt on Pin6
1850+*/
1851+#define INT_LVL_LO_PIN6 (0x2000000)
1852+
1853+/*! @ingroup GPIO_InterfaceLayer
1854+ @def INT_LVL_LO_PIN7
1855+ @brief Low Level Interrupt on Pin7
1856+*/
1857+#define INT_LVL_LO_PIN7 (0x20000000)
1858+
1859+/*! @ingroup GPIO_InterfaceLayer
1860+ @def INT_LVL_LO_PIN8
1861+ @brief Low Level Interrupt on Pin8
1862+*/
1863+#define INT_LVL_LO_PIN8 ((0x200000000ULL))
1864+
1865+/*! @ingroup GPIO_InterfaceLayer
1866+ @def INT_LVL_LO_PIN9
1867+ @brief Low Level Interrupt on Pin9
1868+*/
1869+#define INT_LVL_LO_PIN9 ((0x2000000000ULL))
1870+
1871+/*! @ingroup GPIO_InterfaceLayer
1872+ @def INT_LVL_LO_PIN10
1873+ @brief Low Level Interrupt on Pin10
1874+*/
1875+#define INT_LVL_LO_PIN10 ((0x20000000000ULL))
1876+
1877+/*! @ingroup GPIO_InterfaceLayer
1878+ @def INT_LVL_LO_PIN11
1879+ @brief Low Level Interrupt on Pin11
1880+*/
1881+#define INT_LVL_LO_PIN11 ((0x200000000000ULL))
1882+
1883+/*! @ingroup GPIO_InterfaceLayer
1884+ @def INT_LVL_HI_PIN0
1885+ @brief High Level Interrupt on Pin0
1886+*/
1887+#define INT_LVL_HI_PIN0 (0x3)
1888+
1889+/*! @ingroup GPIO_InterfaceLayer
1890+ @def INT_LVL_HI_PIN1
1891+ @brief High Level Interrupt on Pin1
1892+*/
1893+#define INT_LVL_HI_PIN1 (0x30)
1894+
1895+/*! @ingroup GPIO_InterfaceLayer
1896+ @def INT_LVL_HI_PIN2
1897+ @brief High Level Interrupt on Pin2
1898+*/
1899+#define INT_LVL_HI_PIN2 (0x300)
1900+
1901+/*! @ingroup GPIO_InterfaceLayer
1902+ @def INT_LVL_HI_PIN3
1903+ @brief High Level Interrupt on Pin3
1904+*/
1905+#define INT_LVL_HI_PIN3 (0x3000)
1906+
1907+/*! @ingroup GPIO_InterfaceLayer
1908+ @def INT_LVL_HI_PIN4
1909+ @brief High Level Interrupt on Pin4
1910+*/
1911+#define INT_LVL_HI_PIN4 (0x30000)
1912+
1913+/*! @ingroup GPIO_InterfaceLayer
1914+ @def INT_LVL_HI_PIN5
1915+ @brief High Level Interrupt on Pin5
1916+*/
1917+#define INT_LVL_HI_PIN5 (0x300000)
1918+
1919+/*! @ingroup GPIO_InterfaceLayer
1920+ @def INT_LVL_HI_PIN6
1921+ @brief High Level Interrupt on Pin6
1922+*/
1923+#define INT_LVL_HI_PIN6 (0x3000000)
1924+
1925+/*! @ingroup GPIO_InterfaceLayer
1926+ @def INT_LVL_HI_PIN7
1927+ @brief High Level Interrupt on Pin7
1928+*/
1929+#define INT_LVL_HI_PIN7 (0x30000000)
1930+
1931+/*! @ingroup GPIO_InterfaceLayer
1932+ @def INT_LVL_HI_PIN8
1933+ @brief High Level Interrupt on Pin8
1934+*/
1935+#define INT_LVL_HI_PIN8 ((0x300000000ULL))
1936+
1937+/*! @ingroup GPIO_InterfaceLayer
1938+ @def INT_LVL_HI_PIN9
1939+ @brief High Level Interrupt on Pin9
1940+*/
1941+#define INT_LVL_HI_PIN9 ((0x3000000000ULL))
1942+
1943+/*! @ingroup GPIO_InterfaceLayer
1944+ @def INT_LVL_HI_PIN10
1945+ @brief High Level Interrupt on Pin10
1946+*/
1947+#define INT_LVL_HI_PIN10 ((0x30000000000ULL))
1948+
1949+/*! @ingroup GPIO_InterfaceLayer
1950+ @def INT_LVL_HI_PIN11
1951+ @brief High Level Interrupt on Pin11
1952+*/
1953+#define INT_LVL_HI_PIN11 ((0x300000000000ULL))
1954+
1955+/*! @ingroup GPIO_InterfaceLayer
1956+ @def INT_FL_RS_EDG_PIN0
1957+ @brief Falling and rising Edge on Pin0
1958+*/
1959+#define INT_FL_RS_EDG_PIN0 (0x4)
1960+
1961+/*! @ingroup GPIO_InterfaceLayer
1962+ @def INT_FL_RS_EDG_PIN1
1963+ @brief Falling and rising Edge on Pin1
1964+*/
1965+#define INT_FL_RS_EDG_PIN1 (0x40)
1966+
1967+/*! @ingroup GPIO_InterfaceLayer
1968+ @def INT_FL_RS_EDG_PIN2
1969+ @brief Falling and rising Edge on Pin2
1970+*/
1971+#define INT_FL_RS_EDG_PIN2 (0x400)
1972+
1973+/*! @ingroup GPIO_InterfaceLayer
1974+ @def INT_FL_RS_EDG_PIN3
1975+ @brief Falling and rising Edge on Pin3
1976+*/
1977+#define INT_FL_RS_EDG_PIN3 (0x4000)
1978+
1979+/*! @ingroup GPIO_InterfaceLayer
1980+ @def INT_FL_RS_EDG_PIN4
1981+ @brief Falling and rising Edge on Pin4
1982+*/
1983+#define INT_FL_RS_EDG_PIN4 (0x40000)
1984+
1985+/*! @ingroup GPIO_InterfaceLayer
1986+ @def INT_FL_RS_EDG_PIN5
1987+ @brief Falling and rising Edge on Pin5
1988+*/
1989+#define INT_FL_RS_EDG_PIN5 (0x400000)
1990+
1991+/*! @ingroup GPIO_InterfaceLayer
1992+ @def INT_FL_RS_EDG_PIN6
1993+ @brief Falling and rising Edge on Pin6
1994+*/
1995+#define INT_FL_RS_EDG_PIN6 (0x4000000)
1996+
1997+/*! @ingroup GPIO_InterfaceLayer
1998+ @def INT_FL_RS_EDG_PIN7
1999+ @brief Falling and rising Edge on Pin7
2000+*/
2001+#define INT_FL_RS_EDG_PIN7 (0x40000000)
2002+
2003+/*! @ingroup GPIO_InterfaceLayer
2004+ @def INT_FL_RS_EDG_PIN8
2005+ @brief Falling and rising Edge on Pin8
2006+*/
2007+#define INT_FL_RS_EDG_PIN8 ((0x400000000ULL))
2008+
2009+/*! @ingroup GPIO_InterfaceLayer
2010+ @def INT_FL_RS_EDG_PIN9
2011+ @brief Falling and rising Edge on Pin9
2012+*/
2013+#define INT_FL_RS_EDG_PIN9 ((0x4000000000ULL))
2014+
2015+/*! @ingroup GPIO_InterfaceLayer
2016+ @def INT_FL_RS_EDG_PIN10
2017+ @brief Falling and rising Edge on Pin10
2018+*/
2019+#define INT_FL_RS_EDG_PIN10 ((0x40000000000ULL))
2020+
2021+/*! @ingroup GPIO_InterfaceLayer
2022+ @def INT_FL_RS_EDG_PIN11
2023+ @brief Falling and rising Edge on Pin11
2024+*/
2025+#define INT_FL_RS_EDG_PIN11 ((0x400000000000ULL))
2026+
2027+/*! @ingroup GPIO_InterfaceLayer
2028+
2029+ @def GPIO_MAX_PINS_MASK
2030+ @brief Mask used for all pins.
2031+*/
2032+#define GPIO_MAX_PINS_MASK (0xFFF)
2033+
2034+/*! @ingroup GPIO_InterfaceLayer
2035+ @def GPIO_NUM_PORT_MAX
2036+ @brief Maximum number of ports.
2037+*/
2038+#define GPIO_NUM_PORT_MAX (0)
2039+
2040+/*! @ingroup GPIO_InterfaceLayer
2041+ @def GPIO_NUM_PINS
2042+ @brief Specifies number of GPIO PINS
2043+*/
2044+#define GPIO_NUM_PINS (12)
2045+
2046+/*! @ingroup GPIO_InterfaceLayer
2047+ @def GPIO_IN
2048+ @brief Specifies GPIO input mode.
2049+*/
2050+#define GPIO_IN (0)
2051+
2052+/*! @ingroup GPIO_InterfaceLayer
2053+ @def GPIO_OUT
2054+ @brief Specifies GPIO output mode.
2055+*/
2056+#define GPIO_OUT (1)
2057+
2058+/*! @ingroup GPIO_InterfaceLayer
2059+ @def GPIO_HIGH
2060+ @brief Specifies GPIO HIGH level.
2061+*/
2062+#define GPIO_HIGH (1)
2063+
2064+/*! @ingroup GPIO_InterfaceLayer
2065+ @def GPIO_LOW
2066+ @brief Specifies GPIO LOW level.
2067+*/
2068+#define GPIO_LOW (0)
2069+
2070+/*! @ingroup GPIO_InterfaceLayer
2071+ @def IOH_GPIO_SUCCESS
2072+ @brief Specifies GPIO SUCCESS STATUS CODE
2073+*/
2074+#define IOH_GPIO_SUCCESS (0)
2075+
2076+/*! @ingroup GPIO_InterfaceLayer
2077+ @def IOH_GPIO_FAIL
2078+ @brief Specifies GPIO ERROR STATUS CODE
2079+*/
2080+#define IOH_GPIO_FAIL (-1)
2081+
2082+/*! @ingroup GPIO_InterfaceLayer
2083+ @def BIT_MASK_16
2084+ @brief Mask for 16 bits
2085+*/
2086+#define BIT_MASK_16 (0xFFFF)
2087+
2088+/*! @ingroup GPIO_InterfaceLayer
2089+ @def BIT_MASK_8
2090+ @brief Mask for 8 bits
2091+*/
2092+#define BIT_MASK_8 (0xFF)
2093+
2094+/*! @ingroup GPIO_InterfaceLayer
2095+ @def BIT_MASK_12
2096+ @brief Mask for 12 bits
2097+*/
2098+#define BIT_MASK_12 (0xFFF)
2099+
2100+/*! @ingroup GPIO_InterfaceLayer
2101+ @def BIT_MASK_32
2102+ @brief Maks value for 32 bits.
2103+*/
2104+#define BIT_MASK_32 (0xFFFFFFFF)
2105+
2106+/*structures*/
2107+/*! @ingroup GPIO_InterfaceLayer
2108+@struct ioh_gpio_reqt
2109+@brief This structure specifies information such the GPIO port, pins,
2110+ interrupt and direction
2111+ mode details associated with a user request. The GPIO port
2112+ status is also returned to
2113+ the user using this structure.
2114+@see
2115+ - ioh_gpio_int_mode
2116+ - ioh_gpio_dir_mode
2117+ - ioh_gpio_read
2118+ - ioh_gpio_write
2119+*/
2120+struct ioh_gpio_reqt {
2121+ unsigned long port; /**< Specifies the port. */
2122+ unsigned long pins; /**< Specifies the pins. */
2123+ unsigned long long mode;/**< Specifies the direction/interrupt mode.*/
2124+ unsigned long enable; /**< Interrupt enable/disable. */
2125+};
2126+
2127+extern s32 ioh_gpio_opencount;
2128+extern spinlock_t ioh_gpio_lock;
2129+extern const struct file_operations ioh_gpio_fops;
2130+
2131+/* exported function prototypes*/
2132+/*! @ingroup GPIO_InterfaceLayerAPI
2133+@fn int ioh_gpio_open( struct inode *inode,struct file *file )
2134+@brief This function is invoked when a process opens the device node
2135+*/
2136+int ioh_gpio_open(struct inode *inode, struct file *file);
2137+
2138+/*! @ingroup GPIO_InterfaceLayerAPI
2139+@fn int ioh_gpio_release(struct inode *inode,struct file *file)
2140+@brief This function is invoked when a process closes the device node
2141+*/
2142+int ioh_gpio_release(struct inode *inode, struct file *file);
2143+
2144+/*! @ingroup GPIO_InterfaceLayerAPI
2145+@fn int ioh_gpio_ioctl(struct inode * inode,struct file * file,unsigned int cmd,
2146+ unsigned long arg)
2147+@brief This function is registered at the driver initialization point
2148+ (module_init)
2149+ and invoked when user process invokes an ioctl call on the device.
2150+*/
2151+int ioh_gpio_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
2152+ unsigned long arg);
2153+
2154+/* global variables*/
2155+extern u32 ioh_gpio_base_address; /* base address*/
2156+extern u32 ioh_gpio_irq; /* irq number*/
2157+extern s32 ioh_gpio_suspended; /* suspend status*/
2158+
2159+#endif
2160diff -urN linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_pci.c topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_pci.c
2161--- linux-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_pci.c 1970-01-01 09:00:00.000000000 +0900
2162+++ topcliff-2.6.33.1/drivers/gpio/pch_gpio/pch_gpio_pci.c 2010-04-01 10:58:31.000000000 +0900
2163@@ -0,0 +1,537 @@
2164+/*!
2165+ * @file ioh_gpio_pci.c
2166+ * @brief Provides all the implementation of the interfaces pertaining to the
2167+ * pci and gpio registrations.
2168+ * @version 0.92
2169+ * @section
2170+ * This program is free software; you can redistribute it and/or modify
2171+ * it under the terms of the GNU General Public License as published by
2172+ * the Free Software Foundation; version 2 of the License.
2173+ *
2174+ * This program is distributed in the hope that it will be useful,
2175+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2176+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2177+ * GNU General Public License for more details.
2178+ *
2179+ * You should have received a copy of the GNU General Public License
2180+ * along with this program; if not, write to the Free Software
2181+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2182+ */
2183+
2184+/*
2185+ * History:
2186+ * Copyright (C) 2008 OKI SEMICONDUCTOR Co., LTD.
2187+ * All rights reserved.
2188+ *
2189+ * created:
2190+ * WIPRO 02/20/2009
2191+ * modified:
2192+ * WIPRO 01/05/2010
2193+ * Added the interfaces provided by the gpio module.
2194+ *
2195+ */
2196+/*includes*/
2197+#include <linux/module.h>
2198+#include <linux/kernel.h>
2199+#include <linux/pci.h>
2200+#include <linux/fs.h>
2201+#include <linux/cdev.h>
2202+#include <linux/interrupt.h>
2203+#include <linux/string.h>
2204+
2205+#include "pch_common.h"
2206+#include "pch_debug.h"
2207+#include "pch_gpio_main.h"
2208+#include "pch_gpio_hal.h"
2209+
2210+/*macros*/
2211+/*! @ingroup GPIO_PCILayer
2212+ @def PCI_VENDOR_ID_IOH
2213+ @brief Outlines the PCI Vendor ID.
2214+*/
2215+#define PCI_VENDOR_ID_IOH (0x10DB)
2216+
2217+/*! @ingroup GPIO_PCILayer
2218+ @def PCI_DEVICE_ID_GE_GPIO
2219+ @brief Outlines the PCI Device ID for IOH GPIO.
2220+*/
2221+/* #define PCI_DEVICE_ID_GE_GPIO (0x8000)*/
2222+#define PCI_DEVICE_ID_GE_GPIO (0x8803) /* OKISEMI for LSI */
2223+
2224+/*! @ingroup GPIO_PCILayer
2225+ @def PCI_DEVICE_ID_MP_GPIO
2226+ @brief Outlines the PCI Device ID for MP GPIO.
2227+*/
2228+#define PCI_DEVICE_ID_MP_GPIO (0x8004)
2229+
2230+/*! @ingroup GPIO_PCILayer
2231+ @def PCI_DEVICE_ID_IVI_GPIO
2232+ @brief Outlines the PCI Device ID for IVI GPIO.
2233+*/
2234+#define PCI_DEVICE_ID_IVI_GPIO (0x8001)
2235+
2236+/*! @ingroup GPIO_PCILayer
2237+ @def IOH_MINOR_NOS
2238+ @brief Outlines the GPIO minor number limit.
2239+*/
2240+#define IOH_MINOR_NOS (1)
2241+
2242+/* Global variables*/
2243+u32 ioh_gpio_base_address;
2244+u32 ioh_gpio_irq;
2245+s32 ioh_gpio_suspended;
2246+
2247+/* Major number allocation via module parameter */
2248+static dev_t ioh_gpio_dev_no;
2249+static int ioh_gpio_major_no;
2250+static struct cdev ioh_gpio_dev;
2251+
2252+u32 ioh_gpio_bit_mask;
2253+
2254+/*! @ingroup GPIO_PCILayerAPI
2255+ @fn static s32 __devinit ioh_gpio_probe
2256+ (struct pci_dev* ioh_pci_dev,
2257+ const struct pci_device_id* pci_id)
2258+ @brief Provides the functionality of probing the module.
2259+*/
2260+static int __devinit ioh_gpio_probe(struct pci_dev *pdev, const
2261+ struct pci_device_id *id);
2262+
2263+/*! @ingroup GPIO_PCILayerAPI
2264+ @fn static void __devexit ioh_gpio_remove
2265+ (struct pci_dev * ioh_pci_dev)
2266+ @brief Provides the functionality of removing the module.
2267+*/
2268+static void __devexit ioh_gpio_remove(struct pci_dev *pdev);
2269+
2270+/*! @ingroup GPIO_PCILayerAPI
2271+ @fn static s32 ioh_gpio_suspend(struct pci_dev* pDev,
2272+ pm_message_t state)
2273+ @brief Provides the functionality of suspending the module.
2274+*/
2275+static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state);
2276+
2277+/*! @ingroup GPIO_PCILayerAPI
2278+ @fn static s32 ioh_gpio_resume(struct pci_dev* pDev)
2279+ @brief Provides the functionalities of resuming the module.
2280+*/
2281+static int ioh_gpio_resume(struct pci_dev *pdev);
2282+
2283+/*structures*/
2284+/*! @ingroup GPIO_PCILayerFacilitators
2285+@static struct pci_device_id
2286+@brief It is a structure used for preserving information related to the
2287+ device id.
2288+@note
2289+The concerned details should be provided as a reference in the pci driver
2290+structure.
2291+
2292+@see
2293+ - ioh_gpio_driver
2294+
2295+*/
2296+static struct pci_device_id ioh_gpio_pcidev_id[] = {
2297+
2298+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_GPIO)},
2299+ {PCI_DEVICE(PCI_VENDOR_ID_IOH, PCI_DEVICE_ID_MP_GPIO)},
2300+ {PCI_DEVICE(PCI_VENDOR_ID_IOH, PCI_DEVICE_ID_IVI_GPIO)},
2301+ {0,}
2302+};
2303+
2304+/*! @ingroup GPIO_PCILayerFacilitators
2305+@struct ioh_gpio_driver
2306+@brief This structure specifies the pci driver methods pertaining to
2307+ GPIO module.
2308+@see
2309+ - ioh_gpio_pci_init
2310+ - ioh_gpio_pci_exit
2311+*/
2312+static struct pci_driver ioh_gpio_driver = {
2313+ .name = "ioh_gpio_empty",
2314+ .id_table = ioh_gpio_pcidev_id,
2315+ .probe = ioh_gpio_probe,
2316+ .remove = __devexit_p(ioh_gpio_remove),
2317+#ifdef CONFIG_PM
2318+ .suspend = ioh_gpio_suspend, /* OKISEMI for PM bug fix */
2319+ .resume = ioh_gpio_resume /* OKISEMI for PM bug fix */
2320+#endif
2321+};
2322+
2323+/*! @ingroup GPIO_PCILayerAPI
2324+ @fn static int __init ioh_gpio_pci_init(void)
2325+ @brief Provides the functionality of initializing the module
2326+*/
2327+static int __init ioh_gpio_pci_init(void);
2328+/*! @ingroup GPIO_PCILayerAPI
2329+ @fn static void __exit ioh_gpio_pci_exit(void)
2330+ @brief Provides the functionality of exiting the module
2331+*/
2332+static void __exit ioh_gpio_pci_exit(void);
2333+
2334+MODULE_DESCRIPTION("IOH GPIO PCI Driver");
2335+MODULE_LICENSE("GPL");
2336+module_init(ioh_gpio_pci_init);
2337+module_exit(ioh_gpio_pci_exit);
2338+module_param(ioh_gpio_major_no, int, S_IRUSR | S_IWUSR);
2339+
2340+/*function implementations*/
2341+
2342+/*! @ingroup GPIO_PCILayerAPI
2343+@fn static int __init ioh_gpio_pci_init(void)
2344+@remarks Implements the initialization functionality of the module.
2345+ The main task performed by this function is:
2346+ - Register the module as PCI Driver.
2347+
2348+@param None
2349+@retval int
2350+ - @ref IOH_GPIO_SUCCESS --> Loading successful.
2351+ - -EEXIST --> pci_register_driver failed.
2352+ - -EINVAL --> pci_register_driver failed.
2353+ - -ENOMEM --> pci_register_driver failed.
2354+*/
2355+static int __init ioh_gpio_pci_init(void)
2356+{
2357+ s32 ret;
2358+ ret = pci_register_driver(&ioh_gpio_driver);
2359+ IOH_DEBUG
2360+ ("ioh_gpio_pci_init : Invoked pci_register_driver successfully\n");
2361+ IOH_DEBUG("ioh_gpio_pci_init returns -%d\n", ret);
2362+ return ret;
2363+}
2364+
2365+/*! @ingroup GPIO_PCILayerAPI
2366+ @fn static void __exit ioh_gpio_pci_exit(void)
2367+ @remarks Implements the exit functionality of the module.
2368+ The main task performed by this function is:
2369+ - Un-register the module as a PCI Driver.
2370+
2371+ @param None
2372+ @retval None
2373+*/
2374+static void __exit ioh_gpio_pci_exit(void)
2375+{
2376+ pci_unregister_driver(&ioh_gpio_driver);
2377+ IOH_DEBUG
2378+ ("ioh_gpio_pci_exit : Invoked pci_unregister_driver\
2379+ successfully\n");
2380+}
2381+
2382+/*! @ingroup GPIO_PCILayerAPI
2383+@fn static int __devinit ioh_gpio_probe(struct pci_dev* pdev,
2384+ const struct pci_device_id* id)
2385+@remarks Implements the probe functionality of the module.
2386+ This function is invoked
2387+ when a PCI device with the Vendor and Device ID supported by this module
2388+ is detected. The main tasks performed by this function are:
2389+ - Enables the device.
2390+ - Acquires the device resources and the remapped base address of
2391+ the device.
2392+ - Registers a character device driver for the user space application
2393+ to interact with the system.
2394+ - Registers the callback function.
2395+@note This function is invoked by the Kernel subsystem when a PCI device
2396+ with a supported vendor ID and Device ID is detected.
2397+
2398+@param pdev [@ref INOUT] Contains the reference of the pci_dev structure
2399+@param id [@ref IN] Contains the reference of the pci_device_id structure
2400+@retval int
2401+ - @ref IOH_GPIO_SUCCESS --> Operation successful.
2402+ - -EIO --> pci_enable_device error status code.
2403+ - -EINVAL --> pci_enable_device error status code.
2404+ - -EBUSY --> pci_request_regions/ alloc_chrdev_region
2405+ error status code.
2406+ - -ENOMEM --> pci_iomap/alloc_chrdev_region/cdev_add
2407+ error status code.
2408+
2409+@see
2410+ - ioh_gpio_driver
2411+*/
2412+static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
2413+ const struct pci_device_id *id)
2414+{
2415+
2416+ char *DRIVER_NAME = "ioh_gpio";
2417+ int ret;
2418+ ioh_gpio_bit_mask =
2419+ (pdev->device ==
2420+ PCI_DEVICE_ID_IVI_GPIO) ? BIT_MASK_16 : BIT_MASK_12;
2421+ IOH_DEBUG("ioh_gpio_probe : The value of ioh_gpio_bit_mask is: %x\n",
2422+ ioh_gpio_bit_mask);
2423+
2424+ ioh_gpio_major_no = (ioh_gpio_major_no < 0
2425+ || ioh_gpio_major_no >
2426+ 254) ? 0 : ioh_gpio_major_no;
2427+
2428+ do {
2429+
2430+ ret = pci_enable_device(pdev);
2431+ if (ret) {
2432+ IOH_LOG(KERN_ERR,
2433+ "\nioh_gpio_probe : pci_enable_device FAILED");
2434+ break;
2435+ }
2436+ IOH_DEBUG("ioh_gpio_probe : pci_enable_device returns %d\n",
2437+ ret);
2438+
2439+ ret = pci_request_regions(pdev, DRIVER_NAME);
2440+ if (ret) {
2441+ IOH_LOG(KERN_ERR,
2442+ "ioh_gpio_probe : pci_request_regions FAILED");
2443+ pci_disable_device(pdev);
2444+ break;
2445+ }
2446+ IOH_DEBUG("ioh_gpio_probe : pci_request_regions returns %d\n",
2447+ ret);
2448+
2449+ ioh_gpio_base_address = (unsigned long)pci_iomap(pdev, 1, 0);
2450+
2451+ if (ioh_gpio_base_address == 0) {
2452+ IOH_LOG(KERN_ERR, "ioh_gpio_probe : pci_iomap FAILED");
2453+ pci_release_regions(pdev);
2454+ pci_disable_device(pdev);
2455+ ret = -ENOMEM;
2456+ break;
2457+ }
2458+
2459+ IOH_DEBUG
2460+ ("ioh_gpio_probe : pci_iomap SUCCESS and value in\
2461+ ioh_gpio_base_address"
2462+ "variable is %d\n", ioh_gpio_base_address);
2463+
2464+ if (ioh_gpio_major_no) {
2465+ ioh_gpio_dev_no = MKDEV(ioh_gpio_major_no, 0);
2466+ ret =
2467+ register_chrdev_region(ioh_gpio_dev_no,
2468+ IOH_MINOR_NOS, DRIVER_NAME);
2469+ if (ret) {
2470+ IOH_LOG(KERN_ERR,
2471+ "ioh_gpio_probe : register_chrdev_\
2472+ region FAILED");
2473+ pci_iounmap(pdev,
2474+ (void *)ioh_gpio_base_address);
2475+ pci_release_regions(pdev);
2476+ pci_disable_device(pdev);
2477+ break;
2478+ }
2479+ IOH_DEBUG
2480+ ("ioh_gpio_probe : register_chrdev_region\
2481+ returns %d\n",
2482+ ret);
2483+ } else {
2484+ ret =
2485+ alloc_chrdev_region(&ioh_gpio_dev_no, 0,
2486+ IOH_MINOR_NOS, DRIVER_NAME);
2487+ if (ret) {
2488+ IOH_LOG(KERN_ERR,
2489+ "ioh_gpio_probe : alloc_chrdev_region\
2490+ FAILED");
2491+ pci_iounmap(pdev,
2492+ (void *)ioh_gpio_base_address);
2493+ pci_release_regions(pdev);
2494+ pci_disable_device(pdev);
2495+ break;
2496+ }
2497+ IOH_DEBUG
2498+ ("ioh_gpio_probe : alloc_chrdev_region\
2499+ returns %d\n",
2500+ ret);
2501+ }
2502+
2503+ cdev_init(&ioh_gpio_dev, &ioh_gpio_fops);
2504+ IOH_DEBUG("ioh_gpio_probe : cdev_init invoked successfully\n");
2505+
2506+ ioh_gpio_dev.owner = THIS_MODULE;
2507+ ioh_gpio_dev.ops = &ioh_gpio_fops;
2508+
2509+ ret = cdev_add(&ioh_gpio_dev, ioh_gpio_dev_no, IOH_MINOR_NOS);
2510+ if (ret) {
2511+ IOH_LOG(KERN_ERR, "ioh_gpio_probe : cdev_add FAILED");
2512+ unregister_chrdev_region(ioh_gpio_dev_no,
2513+ IOH_MINOR_NOS);
2514+ pci_iounmap(pdev, (void *)ioh_gpio_base_address);
2515+ pci_release_regions(pdev);
2516+ pci_disable_device(pdev);
2517+ break;
2518+ }
2519+ IOH_DEBUG("ioh_gpio_probe : cdev_add returns- %d\n", ret);
2520+
2521+ ioh_gpio_cb_register(ioh_gpio_cb);
2522+ ioh_gpio_irq = pdev->irq;
2523+ IOH_DEBUG("ioh_gpio_probe returns %d\n", IOH_GPIO_SUCCESS);
2524+ device_set_wakeup_enable(&pdev->dev, 1);
2525+ return IOH_GPIO_SUCCESS;
2526+ } while (0);
2527+ IOH_DEBUG("ioh_gpio_probe returns %d\n", ret);
2528+ return ret;
2529+}
2530+
2531+/*! @ingroup GPIO_PCILayerAPI
2532+@fn static void __devexit ioh_gpio_remove(struct pci_dev * pdev)
2533+@remarks Implements the remove functionality of the module.
2534+The main tasks performed by this function are:
2535+-Disables the interrupts by invoking @ref ioh_gpio_int_mode API.
2536+-Removes the device from the system using cdev_del API
2537+-Un-registers the char device number by invoking unregister_chrdev_region API.
2538+-Releases the IO memory using pci_iounmap API
2539+-Releases the resources acquired using pci_release_regions API
2540+-Disables the pci device using pci_disable_device API
2541+
2542+@param pdev [@ref INOUT] Contains the reference of the pci_dev structure
2543+@retval None
2544+@see
2545+ - ioh_gpio_driver
2546+*/
2547+static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
2548+{
2549+
2550+ struct ioh_gpio_reqt req;
2551+ memset(&req, 0, sizeof(req));
2552+ req.pins = IOH_GPIO_ALL_PINS;
2553+ /* disable interrupts for all gpio pins */
2554+ (void)ioh_gpio_int_mode(&req);
2555+
2556+ cdev_del(&ioh_gpio_dev);
2557+ IOH_DEBUG("ioh_gpio_remove - cdev_del Invoked successfully\n");
2558+
2559+ unregister_chrdev_region(ioh_gpio_dev_no, IOH_MINOR_NOS);
2560+ IOH_DEBUG
2561+ ("ioh_gpio_remove - unregister_chrdev_region Invoked\
2562+ successfully\n");
2563+
2564+ pci_iounmap(pdev, (void *)ioh_gpio_base_address);
2565+
2566+ IOH_DEBUG("ioh_gpio_remove - pci_iounmap Invoked successfully\n");
2567+
2568+ pci_release_regions(pdev);
2569+ IOH_DEBUG
2570+ ("ioh_gpio_remove - pci_release_regions Invoked successfully\n");
2571+
2572+ pci_disable_device(pdev);
2573+ IOH_DEBUG
2574+ ("ioh_gpio_remove - pci_disable_device Invoked successfully\n");
2575+
2576+}
2577+
2578+#ifdef CONFIG_PM
2579+
2580+/*! @ingroup GPIO_PCILayerAPI
2581+@fn static s32 ioh_gpio_suspend(struct pci_dev* pdev,pm_message_t state)
2582+@remarks Implements the suspend functionality of the module. The main
2583+tasks performed by this function are:
2584+- Saves the current pin configuration by invoking
2585+ @ref ioh_gpio_save_reg_conf API.
2586+- Invokes pci_enable_wake with the enable parameter as 0,
2587+ so as to ensure that the device has its "wake" ability disabled
2588+- Saves the current state by invoking pci_save_state API.
2589+ If it fails then return with its error code.
2590+- Disables PCI device by invoking pci_disable_device API.
2591+- Sets the power state to low power mode by invoking
2592+ pci_set_power_state API and return @ref IOH_GPIO_SUCCESS status code.
2593+
2594+@param pdev [@ref INOUT] Contains the reference of the pci_dev structure
2595+@param state [@ref INOUT] Contains the reference of the pm_message_t
2596+ structure
2597+@retval int
2598+ - @ref IOH_GPIO_SUCCESS --> Operation successful.
2599+ - -ENOMEM --> pci_save_state error status code.
2600+@see
2601+ - ioh_gpio_driver
2602+
2603+*/
2604+static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
2605+{
2606+ int ret;
2607+
2608+ ioh_gpio_suspended = true; /* For blocking further IOCTLs */
2609+
2610+ ioh_gpio_save_reg_conf();
2611+ IOH_DEBUG
2612+ ("ioh_gpio_suspend - ioh_gpio_save_reg_conf Invoked successfully\n");
2613+ ioh_gpio_restore_reg_conf();
2614+
2615+ ret = pci_save_state(pdev);
2616+ if (ret) {
2617+ IOH_LOG(KERN_ERR,
2618+ " ioh_gpio_suspend -pci_save_state returns-%d\n", ret);
2619+ return ret;
2620+ }
2621+
2622+ IOH_DEBUG("ioh_gpio_suspend - pci_save_state returns %d\n", ret);
2623+
2624+ pci_disable_device(pdev);
2625+ IOH_DEBUG
2626+ ("ioh_gpio_suspend - pci_disable_device Invoked successfully\n");
2627+
2628+ pci_set_power_state(pdev, PCI_D0);
2629+ IOH_DEBUG
2630+ ("ioh_gpio_suspend - pci_set_power_state Invoked successfully\n");
2631+
2632+ ret = pci_enable_wake(pdev, PCI_D0, 1);
2633+ if (!ret) {
2634+ IOH_DEBUG
2635+ ("ioh_gpio_suspend - pci_enable_wake Invoked successfully\n");
2636+ } else {
2637+ IOH_DEBUG("ioh_gpio_suspend - pci_enable_wake failed\n");
2638+ }
2639+ IOH_LOG(KERN_ERR, "ioh_gpio_suspend - return %d\n", IOH_GPIO_SUCCESS);
2640+
2641+ return IOH_GPIO_SUCCESS;
2642+}
2643+
2644+/*! @ingroup GPIO_PCILayerAPI
2645+@fn static s32 ioh_gpio_resume(struct pci_dev* pdev)
2646+@remarks Implements the resume functionality of the module. The main
2647+tasks performed by this function are:
2648+-Changes the power state of the device to D0 using pci_set_power_state API.
2649+-Invokes pci_restore_state API to restore the PCI register state
2650+-Invokes pci_enable_device API to enable the PCI device.
2651+If it fails, then return its error code.
2652+-To ensure that the device has its "wake" ability disabled,
2653+invokes pci_enable_wake with the enable parameter as 0
2654+-Invokes @ref ioh_gpio_restore_reg_conf API to restore the GPIO register
2655+configuration values and returns @ref IOH_GPIO_SUCCESS status code.
2656+
2657+@param pdev [@ref INOUT] Contains the reference of the pci_dev structure
2658+@retval int
2659+ - @ref IOH_GPIO_SUCCESS --> Operation successful.
2660+ - -EIO --> pci_enable_device error status code.
2661+ - -EINVAL --> pci_enable_device error status code.
2662+
2663+@see
2664+ - ioh_gpio_driver
2665+
2666+*/
2667+static int ioh_gpio_resume(struct pci_dev *pdev)
2668+{
2669+
2670+ int ret;
2671+
2672+ ret = pci_enable_wake(pdev, PCI_D0, 0);
2673+ IOH_LOG(KERN_ERR,
2674+ "ioh_gpio_resume - pci_set_power_state Invoked successfully\n");
2675+
2676+ pci_set_power_state(pdev, PCI_D0);
2677+ IOH_DEBUG
2678+ ("ioh_gpio_resume - pci_set_power_state Invoked successfully\n");
2679+
2680+ ret = pci_enable_device(pdev);
2681+ if (ret) {
2682+ IOH_LOG(KERN_ERR, "ioh_gpio_resume-pci_enable_device failed ");
2683+ return ret;
2684+ }
2685+
2686+ IOH_DEBUG("ioh_gpio_resume - pci_enable_device returns -%d\n", ret);
2687+
2688+ pci_restore_state(pdev);
2689+ IOH_DEBUG("ioh_gpio_resume - pci_restore_state Invoked successfully\n");
2690+
2691+ ioh_gpio_writereg(0x3c, 0x00000001); /*reset*/
2692+ ioh_gpio_writereg(0x3c, 0x00000000);
2693+ ioh_gpio_restore_reg_conf();
2694+ ioh_gpio_suspended = false;
2695+
2696+ IOH_DEBUG("ioh_gpio_resume returns- %d\n", IOH_GPIO_SUCCESS);
2697+ return IOH_GPIO_SUCCESS;
2698+}
2699+
2700+#endif
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-31 07:23:37 +0000