diff options
Diffstat (limited to 'meta/recipes-devtools/qemu/qemu')
-rw-r--r-- | meta/recipes-devtools/qemu/qemu/ppc.patch | 91 |
1 files changed, 46 insertions, 45 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/ppc.patch b/meta/recipes-devtools/qemu/qemu/ppc.patch index 1fe6a3b413..e14c48cf85 100644 --- a/meta/recipes-devtools/qemu/qemu/ppc.patch +++ b/meta/recipes-devtools/qemu/qemu/ppc.patch | |||
@@ -1,11 +1,12 @@ | |||
1 | From d92b63b7d15d4fd202c5802dfe444a96f5d8109c Mon Sep 17 00:00:00 2001 | 1 | From 31f02021ac17442c514593f7b9ed750ea87c21b1 Mon Sep 17 00:00:00 2001 |
2 | From: Richard Purdie <richard.purdie@linuxfoundation.org> | 2 | From: Richard Purdie <richard.purdie@linuxfoundation.org> |
3 | Date: Sat, 6 May 2023 07:42:35 +0100 | 3 | Date: Sat, 6 May 2023 07:42:35 +0100 |
4 | Cc: Víctor Colombo <victor.colombo@eldorado.org.br> | 4 | Cc: Víctor Colombo <victor.colombo@eldorado.org.br> |
5 | Cc: Matheus Ferst <matheus.ferst@eldorado.org.br> | 5 | Cc: Matheus Ferst <matheus.ferst@eldorado.org.br> |
6 | Cc: Daniel Henrique Barboza <danielhb413@gmail.com> | 6 | Cc: Daniel Henrique Barboza <danielhb413@gmail.com> |
7 | Cc: Richard Henderson <richard.henderson@linaro.org> | 7 | Cc: Richard Henderson <richard.henderson@linaro.org> |
8 | Subject: [PATCH v2] target/ppc: Fix fallback to MFSS for MFFS* instructions on | 8 | Cc: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Subject: [PATCH v3] target/ppc: Fix fallback to MFSS for MFFS* instructions on | ||
9 | pre 3.0 ISAs | 10 | pre 3.0 ISAs |
10 | 11 | ||
11 | The following commits changed the code such that the fallback to MFSS for MFFSCRN, | 12 | The following commits changed the code such that the fallback to MFSS for MFFSCRN, |
@@ -22,25 +23,25 @@ instructions which is used in glibc libm functions for example. | |||
22 | The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing. | 23 | The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing. |
23 | 24 | ||
24 | This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs | 25 | This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs |
25 | as the hardware decoder would, fixing the segfaulting libm code. It and also ensures | 26 | as the hardware decoder would, fixing the segfaulting libm code. It doesn't have |
26 | the MFSS instruction is used for currently reserved bits to handle other potential | 27 | the fallback for 3.0 onwards to match hardware behaviour. |
27 | ISA additions more correctly. | ||
28 | |||
29 | Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230506065240.3177798-1-richard.purdie@linuxfoundation.org/] | ||
30 | 28 | ||
31 | Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> | 29 | Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> |
32 | --- | 30 | --- |
33 | target/ppc/insn32.decode | 19 ++++++++++++------- | 31 | target/ppc/insn32.decode | 20 +++++++++++++------- |
34 | target/ppc/translate/fp-impl.c.inc | 30 ++++++++++++++++++++++++------ | 32 | target/ppc/translate/fp-impl.c.inc | 22 ++++++++++++++++------ |
35 | 2 files changed, 36 insertions(+), 13 deletions(-) | 33 | 2 files changed, 29 insertions(+), 13 deletions(-) |
36 | 34 | ||
35 | v3 - drop fallback to MFFS for 3.0 ISA to match hardware | ||
37 | v2 - switch to use decodetree pattern groups per feedback | 36 | v2 - switch to use decodetree pattern groups per feedback |
38 | 37 | ||
38 | Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230506065240.3177798-1-richard.purdie@linuxfoundation.org/] | ||
39 | |||
39 | diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode | 40 | diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode |
40 | index f8f589e9fd..3c4e2c2fc2 100644 | 41 | index f8f589e9fd..4fcf3af8d0 100644 |
41 | --- a/target/ppc/insn32.decode | 42 | --- a/target/ppc/insn32.decode |
42 | +++ b/target/ppc/insn32.decode | 43 | +++ b/target/ppc/insn32.decode |
43 | @@ -390,13 +390,18 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi | 44 | @@ -390,13 +390,19 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi |
44 | 45 | ||
45 | ### Move To/From FPSCR | 46 | ### Move To/From FPSCR |
46 | 47 | ||
@@ -51,9 +52,11 @@ index f8f589e9fd..3c4e2c2fc2 100644 | |||
51 | -MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 | 52 | -MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2 |
52 | -MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 | 53 | -MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 |
53 | -MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t | 54 | -MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t |
54 | +{ | 55 | +{ |
55 | + # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored | 56 | + # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored |
57 | + MFFS_ISA207 111111 ..... ----- ----- 1001000111 . @X_t_rc | ||
56 | + [ | 58 | + [ |
59 | + MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc | ||
57 | + MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t | 60 | + MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t |
58 | + MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb | 61 | + MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb |
59 | + MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb | 62 | + MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb |
@@ -61,84 +64,82 @@ index f8f589e9fd..3c4e2c2fc2 100644 | |||
61 | + MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 | 64 | + MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3 |
62 | + MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t | 65 | + MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t |
63 | + ] | 66 | + ] |
64 | + MFFS 111111 ..... ----- ----- 1001000111 . @X_t_rc | ||
65 | +} | 67 | +} |
66 | 68 | ||
67 | ### Decimal Floating-Point Arithmetic Instructions | 69 | ### Decimal Floating-Point Arithmetic Instructions |
68 | 70 | ||
69 | diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc | 71 | diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc |
70 | index 57d8437851..10dfd91aa4 100644 | 72 | index 57d8437851..874774eade 100644 |
71 | --- a/target/ppc/translate/fp-impl.c.inc | 73 | --- a/target/ppc/translate/fp-impl.c.inc |
72 | +++ b/target/ppc/translate/fp-impl.c.inc | 74 | +++ b/target/ppc/translate/fp-impl.c.inc |
73 | @@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) | 75 | @@ -568,6 +568,22 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t clear_mask, |
74 | { | 76 | gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); |
75 | TCGv_i64 fpscr; | 77 | } |
76 | 78 | ||
77 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 79 | +static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a) |
80 | +{ | ||
78 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | 81 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { |
79 | + return false; | 82 | + /* |
83 | + * Before Power ISA v3.0, MFFS bits 11~15 were reserved, any instruction | ||
84 | + * with OPCD=63 and XO=583 should be decoded as MFFS. | ||
85 | + */ | ||
86 | + return trans_MFFS(ctx, a); | ||
80 | + } | 87 | + } |
88 | + /* | ||
89 | + * For Power ISA v3.0+, return false and let the pattern group | ||
90 | + * select the correct instruction. | ||
91 | + */ | ||
92 | + return false; | ||
93 | +} | ||
81 | + | 94 | + |
95 | static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) | ||
96 | { | ||
97 | REQUIRE_FPU(ctx); | ||
98 | @@ -584,7 +600,6 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) | ||
99 | { | ||
100 | TCGv_i64 fpscr; | ||
101 | |||
102 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | ||
82 | REQUIRE_FPU(ctx); | 103 | REQUIRE_FPU(ctx); |
83 | 104 | ||
84 | gen_reset_fpstatus(); | 105 | gen_reset_fpstatus(); |
85 | @@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) | 106 | @@ -597,7 +612,6 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a) |
86 | { | 107 | { |
87 | TCGv_i64 t1, fpscr; | 108 | TCGv_i64 t1, fpscr; |
88 | 109 | ||
89 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 110 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); |
90 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | ||
91 | + return false; | ||
92 | + } | ||
93 | + | ||
94 | REQUIRE_FPU(ctx); | 111 | REQUIRE_FPU(ctx); |
95 | 112 | ||
96 | t1 = tcg_temp_new_i64(); | 113 | t1 = tcg_temp_new_i64(); |
97 | @@ -614,7 +620,10 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a) | 114 | @@ -614,7 +628,6 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a) |
98 | { | 115 | { |
99 | TCGv_i64 t1, fpscr; | 116 | TCGv_i64 t1, fpscr; |
100 | 117 | ||
101 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 118 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); |
102 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | ||
103 | + return false; | ||
104 | + } | ||
105 | + | ||
106 | REQUIRE_FPU(ctx); | 119 | REQUIRE_FPU(ctx); |
107 | 120 | ||
108 | t1 = tcg_temp_new_i64(); | 121 | t1 = tcg_temp_new_i64(); |
109 | @@ -631,7 +640,10 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) | 122 | @@ -631,7 +644,6 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a) |
110 | { | 123 | { |
111 | TCGv_i64 t1, fpscr; | 124 | TCGv_i64 t1, fpscr; |
112 | 125 | ||
113 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 126 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); |
114 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | ||
115 | + return false; | ||
116 | + } | ||
117 | + | ||
118 | REQUIRE_FPU(ctx); | 127 | REQUIRE_FPU(ctx); |
119 | 128 | ||
120 | t1 = tcg_temp_new_i64(); | 129 | t1 = tcg_temp_new_i64(); |
121 | @@ -647,7 +659,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) | 130 | @@ -647,7 +659,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) |
122 | { | 131 | { |
123 | TCGv_i64 t1, fpscr; | 132 | TCGv_i64 t1, fpscr; |
124 | 133 | ||
125 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 134 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); |
126 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | ||
127 | + return false; | ||
128 | + } | ||
129 | + | ||
130 | REQUIRE_FPU(ctx); | 135 | REQUIRE_FPU(ctx); |
131 | 136 | ||
132 | t1 = tcg_temp_new_i64(); | 137 | t1 = tcg_temp_new_i64(); |
133 | @@ -661,7 +676,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) | 138 | @@ -661,7 +672,6 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a) |
134 | 139 | ||
135 | static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) | 140 | static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) |
136 | { | 141 | { |
137 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); | 142 | - REQUIRE_INSNS_FLAGS2(ctx, ISA300); |
138 | + if (!(ctx->insns_flags2 & PPC2_ISA300)) { | ||
139 | + return false; | ||
140 | + } | ||
141 | + | ||
142 | REQUIRE_FPU(ctx); | 143 | REQUIRE_FPU(ctx); |
143 | 144 | ||
144 | gen_reset_fpstatus(); | 145 | gen_reset_fpstatus(); |