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1Upstream-Status: Backport
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From patchwork Fri Apr 19 09:34:49 2013
5Content-Type: text/plain; charset="utf-8"
6MIME-Version: 1.0
7Content-Transfer-Encoding: 7bit
8Subject: [ARM] Fix PR56797
9Date: Thu, 18 Apr 2013 23:34:49 -0000
10From: Greta Yorsh <Greta.Yorsh@arm.com>
11X-Patchwork-Id: 237891
12Message-Id: <000801ce3ce1$23fbdd60$6bf39820$@yorsh@arm.com>
13To: "GCC Patches" <gcc-patches@gcc.gnu.org>
14Cc: <raj.khem@gmail.com>, "Richard Earnshaw" <Richard.Earnshaw@arm.com>,
15 "Ramana Radhakrishnan" <Ramana.Radhakrishnan@arm.com>
16
17Fix PR56797
18http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56797
19
20The problem is that peephole optimizer thinks it can generate an ldm, but
21the pattern for ldm no longer matches, because after r188738 it requires
22that if one of the destination registers is SP then the base register must
23be SP, and it's not SP in the test case.
24
25The test case fails on armv5t but doesn't fail on armv6t2 or armv7-a because
26peephole doesn't trigger there (because there is a different epilogue
27sequence). It looks like a latent problem for other architecture or CPUs.
28
29This patch adds this condition to the peephole optimizer.
30
31No regression on qemu for arm-none-eabi and fixes the test reported in the
32PR. I couldn't minimize the test sufficiently to include it in the
33testsuite.
34
35Ok for trunk?
36
37Thanks,
38Greta
39
40gcc/
41
422013-04-18 Greta Yorsh <Greta.Yorsh@arm.com>
43
44 PR target/56797
45 * config/arm/arm.c (load_multiple_sequence): Require SP
46 as base register for loads if SP is in the register list.
47
48
49diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
50index d00849c..60fef78 100644
51--- a/gcc/config/arm/arm.c
52+++ b/gcc/config/arm/arm.c
53@@ -10347,6 +10347,13 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
54 || (i != nops - 1 && unsorted_regs[i] == base_reg))
55 return 0;
56
57+ /* Don't allow SP to be loaded unless it is also the base
58+ register. It guarantees that SP is reset correctly when
59+ an LDM instruction is interruptted. Otherwise, we might
60+ end up with a corrupt stack. */
61+ if (unsorted_regs[i] == SP_REGNUM && base_reg != SP_REGNUM)
62+ return 0;
63+
64 unsorted_offsets[i] = INTVAL (offset);
65 if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]])
66 order[0] = i;