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-rw-r--r--meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch402
1 files changed, 402 insertions, 0 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch b/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch
new file mode 100644
index 0000000..a199918
--- /dev/null
+++ b/meta/recipes-devtools/binutils/binutils/binutils-xlp-support.patch
@@ -0,0 +1,402 @@
1Upstream-Status: Unknown
2Signed-off-by: Khem Raj <raj.khem@gmail.com>
3
4From 26adb06ce515aadfec08ce13109b4b98287f677b Mon Sep 17 00:00:00 2001
5From: Nebu Philips <nphilips@netlogicmicro.com>
6Date: Fri, 30 Jul 2010 15:10:03 -0700
7Subject: [PATCH] Add support for Netlogic XLP
8
9Using the mipsisa64r2nlm target, add support for XLP from
10Netlogic. Also, update vendor name to NLM wherever applicable.
11---
12 bfd/aoutx.h | 1 +
13 bfd/archures.c | 1 +
14 bfd/bfd-in2.h | 1 +
15 bfd/config.bfd | 5 +++++
16 bfd/cpu-mips.c | 6 ++++--
17 bfd/elfxx-mips.c | 8 ++++++++
18 binutils/readelf.c | 1 +
19 config.sub | 6 ++++++
20 gas/config/tc-mips.c | 7 ++++++-
21 gas/configure | 3 +++
22 gas/configure.tgt | 2 +-
23 gas/doc/c-mips.texi | 3 ++-
24 include/elf/mips.h | 1 +
25 include/opcode/mips.h | 6 +++++-
26 ld/configure.tgt | 2 ++
27 opcodes/mips-dis.c | 6 ++++++
28 opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
29 17 files changed, 73 insertions(+), 17 deletions(-)
30
31Index: binutils-2.24/bfd/aoutx.h
32===================================================================
33--- binutils-2.24.orig/bfd/aoutx.h 2013-12-15 13:07:57.180399300 -0800
34+++ binutils-2.24/bfd/aoutx.h 2013-12-15 13:08:03.397065919 -0800
35@@ -798,6 +798,7 @@
36 case bfd_mach_mipsisa64r2:
37 case bfd_mach_mips_sb1:
38 case bfd_mach_mips_xlr:
39+ case bfd_mach_mips_xlp:
40 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
41 arch_flags = M_MIPS2;
42 break;
43Index: binutils-2.24/bfd/archures.c
44===================================================================
45--- binutils-2.24.orig/bfd/archures.c 2013-12-15 13:07:57.180399300 -0800
46+++ binutils-2.24/bfd/archures.c 2013-12-15 13:08:03.397065919 -0800
47@@ -178,6 +178,7 @@
48 .#define bfd_mach_mips_octeonp 6601
49 .#define bfd_mach_mips_octeon2 6502
50 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
51+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP' *}
52 .#define bfd_mach_mipsisa32 32
53 .#define bfd_mach_mipsisa32r2 33
54 .#define bfd_mach_mipsisa64 64
55Index: binutils-2.24/bfd/bfd-in2.h
56===================================================================
57--- binutils-2.24.orig/bfd/bfd-in2.h 2013-12-15 13:07:57.180399300 -0800
58+++ binutils-2.24/bfd/bfd-in2.h 2013-12-15 13:08:03.400399254 -0800
59@@ -1933,6 +1933,7 @@
60 #define bfd_mach_mips_octeonp 6601
61 #define bfd_mach_mips_octeon2 6502
62 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
63+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP' */
64 #define bfd_mach_mipsisa32 32
65 #define bfd_mach_mipsisa32r2 33
66 #define bfd_mach_mipsisa64 64
67Index: binutils-2.24/bfd/config.bfd
68===================================================================
69--- binutils-2.24.orig/bfd/config.bfd 2013-12-15 13:08:03.047065922 -0800
70+++ binutils-2.24/bfd/config.bfd 2013-12-15 13:08:03.400399254 -0800
71@@ -1032,6 +1032,11 @@
72 targ_defvec=bfd_elf32_littlemips_vec
73 targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
74 ;;
75+ mipsisa64*-*-elf*)
76+ targ_defvec=bfd_elf32_tradbigmips_vec
77+ targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec"
78+ want64=true
79+ ;;
80 mips*-*-elf* | mips*-*-rtems* | mips*-*-vxworks | mips*-*-windiss)
81 targ_defvec=bfd_elf32_bigmips_vec
82 targ_selvecs="bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec"
83Index: binutils-2.24/bfd/cpu-mips.c
84===================================================================
85--- binutils-2.24.orig/bfd/cpu-mips.c 2013-12-15 13:07:57.180399300 -0800
86+++ binutils-2.24/bfd/cpu-mips.c 2013-12-15 13:08:03.400399254 -0800
87@@ -99,7 +99,8 @@
88 I_mipsocteonp,
89 I_mipsocteon2,
90 I_xlr,
91- I_micromips
92+ I_micromips,
93+ I_xlp
94 };
95
96 #define NN(index) (&arch_info_struct[(index) + 1])
97@@ -143,7 +144,8 @@
98 N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
99 N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
100 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
101- N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
102+ N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,NN(I_micromips)),
103+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, 0)
104 };
105
106 /* The default architecture is mips:3000, but with a machine number of
107Index: binutils-2.24/bfd/elfxx-mips.c
108===================================================================
109--- binutils-2.24.orig/bfd/elfxx-mips.c 2013-12-15 13:07:57.180399300 -0800
110+++ binutils-2.24/bfd/elfxx-mips.c 2013-12-15 13:08:03.400399254 -0800
111@@ -6404,6 +6404,9 @@
112 case E_MIPS_MACH_XLR:
113 return bfd_mach_mips_xlr;
114
115+ case E_MIPS_MACH_XLP:
116+ return bfd_mach_mips_xlp;
117+
118 default:
119 switch (flags & EF_MIPS_ARCH)
120 {
121@@ -11622,6 +11625,10 @@
122 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
123 break;
124
125+ case bfd_mach_mips_xlp:
126+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
127+ break;
128+
129 case bfd_mach_mipsisa32:
130 val = E_MIPS_ARCH_32;
131 break;
132@@ -14202,6 +14209,7 @@
133 { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
134 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
135 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
136+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
137
138 /* MIPS64 extensions. */
139 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
140Index: binutils-2.24/binutils/readelf.c
141===================================================================
142--- binutils-2.24.orig/binutils/readelf.c 2013-12-15 13:07:57.180399300 -0800
143+++ binutils-2.24/binutils/readelf.c 2013-12-15 13:08:03.403732587 -0800
144@@ -2602,6 +2602,7 @@
145 case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
146 case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
147 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
148+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
149 case 0:
150 /* We simply ignore the field in this case to avoid confusion:
151 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
152Index: binutils-2.24/gas/config/tc-mips.c
153===================================================================
154--- binutils-2.24.orig/gas/config/tc-mips.c 2013-12-15 13:07:57.180399300 -0800
155+++ binutils-2.24/gas/config/tc-mips.c 2013-12-15 13:17:19.943728439 -0800
156@@ -486,6 +486,7 @@
157 || mips_opts.arch == CPU_RM7000 \
158 || mips_opts.arch == CPU_VR5500 \
159 || mips_opts.micromips \
160+ || mips_opts.arch == CPU_XLP \
161 )
162
163 /* Whether the processor uses hardware interlocks to protect reads
164@@ -515,6 +516,7 @@
165 && mips_opts.isa != ISA_MIPS3) \
166 || mips_opts.arch == CPU_R4300 \
167 || mips_opts.micromips \
168+ || mips_opts.arch == CPU_XLP \
169 )
170
171 /* Whether the processor uses hardware interlocks to protect reads
172@@ -17794,7 +17796,7 @@
173 /* Broadcom XLP.
174 XLP is mostly like XLR, with the prominent exception that it is
175 MIPS64R2 rather than MIPS64. */
176- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
177+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
178
179 /* End marker */
180 { NULL, 0, 0, 0, 0 }
181Index: binutils-2.24/gas/configure
182===================================================================
183--- binutils-2.24.orig/gas/configure 2013-12-15 13:08:01.127065936 -0800
184+++ binutils-2.24/gas/configure 2013-12-15 13:08:03.407065920 -0800
185@@ -12697,6 +12697,9 @@
186 mipsisa64r2 | mipsisa64r2el)
187 mips_cpu=mips64r2
188 ;;
189+ mipsisa64r2nlm | mipsisa64r2nlmel)
190+ mips_cpu=xlp
191+ ;;
192 mipstx39 | mipstx39el)
193 mips_cpu=r3900
194 ;;
195Index: binutils-2.24/gas/configure.tgt
196===================================================================
197--- binutils-2.24.orig/gas/configure.tgt 2013-12-15 13:08:00.783732605 -0800
198+++ binutils-2.24/gas/configure.tgt 2013-12-15 13:08:03.407065920 -0800
199@@ -325,7 +325,7 @@
200 fmt=elf em=freebsd ;;
201 mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;;
202 mips*-sde-elf* | mips*-mti-elf*) fmt=elf em=tmips ;;
203- mips-*-elf* | mips-*-rtems*) fmt=elf ;;
204+ mips-*-elf* | mips-*-rtems*) fmt=elf em=tmips ;;
205 mips-*-netbsd*) fmt=elf em=tmips ;;
206 mips-*-openbsd*) fmt=elf em=tmips ;;
207
208Index: binutils-2.24/include/elf/mips.h
209===================================================================
210--- binutils-2.24.orig/include/elf/mips.h 2013-12-15 13:07:57.180399300 -0800
211+++ binutils-2.24/include/elf/mips.h 2013-12-15 13:08:03.407065920 -0800
212@@ -274,6 +274,7 @@
213 #define E_MIPS_MACH_SB1 0x008a0000
214 #define E_MIPS_MACH_OCTEON 0x008b0000
215 #define E_MIPS_MACH_XLR 0x008c0000
216+#define E_MIPS_MACH_XLP 0x008e0000
217 #define E_MIPS_MACH_OCTEON2 0x008d0000
218 #define E_MIPS_MACH_5400 0x00910000
219 #define E_MIPS_MACH_5900 0x00920000
220Index: binutils-2.24/include/opcode/mips.h
221===================================================================
222--- binutils-2.24.orig/include/opcode/mips.h 2013-12-15 13:07:57.180399300 -0800
223+++ binutils-2.24/include/opcode/mips.h 2013-12-15 13:40:11.130384844 -0800
224@@ -1092,8 +1092,10 @@
225 #define INSN_LOONGSON_2F 0x80000000
226 /* Loongson 3A. */
227 #define INSN_LOONGSON_3A 0x00000400
228-/* RMI Xlr instruction */
229-#define INSN_XLR 0x00000020
230+/* Netlogic Xlr instruction */
231+#define INSN_XLR 0x00000020
232+/* Netlogic XlP instruction */
233+#define INSN_XLP 0x00000040
234
235 /* DSP ASE */
236 #define ASE_DSP 0x00000001
237@@ -1172,6 +1174,7 @@
238 #define CPU_OCTEONP 6601
239 #define CPU_OCTEON2 6502
240 #define CPU_XLR 887682 /* decimal 'XLR' */
241+#define CPU_XLP 887680 /* decimal 'XLP' */
242
243 /* Return true if the given CPU is included in INSN_* mask MASK. */
244
245@@ -1239,6 +1242,9 @@
246 case CPU_XLR:
247 return (mask & INSN_XLR) != 0;
248
249+ case CPU_XLP:
250+ return (mask & INSN_XLP) != 0;
251+
252 default:
253 return FALSE;
254 }
255Index: binutils-2.24/ld/configure.tgt
256===================================================================
257--- binutils-2.24.orig/ld/configure.tgt 2013-12-15 13:08:03.047065922 -0800
258+++ binutils-2.24/ld/configure.tgt 2013-12-15 13:08:03.407065920 -0800
259@@ -457,6 +457,8 @@
260 mips*-sde-elf* | mips*-mti-elf*)
261 targ_emul=elf32btsmip
262 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
263+mipsisa64*-*-elf*) targ_emul=elf32btsmip
264+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip" ;;
265 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
266 targ_extra_emuls="elf32lr5900"
267 targ_extra_libpath=$targ_extra_emuls ;;
268Index: binutils-2.24/opcodes/mips-dis.c
269===================================================================
270--- binutils-2.24.orig/opcodes/mips-dis.c 2013-12-15 13:07:57.180399300 -0800
271+++ binutils-2.24/opcodes/mips-dis.c 2013-12-15 13:39:50.243718329 -0800
272@@ -554,13 +554,11 @@
273 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
274 mips_hwr_names_numeric },
275
276- /* XLP is mostly like XLR, with the prominent exception it is being
277- MIPS64R2. */
278- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
279- ISA_MIPS64R2 | INSN_XLR, 0,
280- mips_cp0_names_xlr,
281- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
282- mips_hwr_names_numeric },
283+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
284+ ISA_MIPS64R2 | INSN_XLP, 0,
285+ mips_cp0_names_mips3264r2,
286+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
287+ mips_hwr_names_mips3264r2 },
288
289 /* This entry, mips16, is here only for ISA/processor selection; do
290 not print its name. */
291Index: binutils-2.24/opcodes/mips-opc.c
292===================================================================
293--- binutils-2.24.orig/opcodes/mips-opc.c 2013-12-15 13:07:57.180399300 -0800
294+++ binutils-2.24/opcodes/mips-opc.c 2013-12-15 13:27:30.573724118 -0800
295@@ -262,7 +262,8 @@
296 #define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
297 #define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
298 #define IOCT2 INSN_OCTEON2
299-#define XLR INSN_XLR
300+#define XLR INSN_XLR
301+#define XLP INSN_XLP
302 #define IVIRT ASE_VIRT
303 #define IVIRT64 ASE_VIRT64
304
305@@ -881,6 +882,7 @@
306 {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
307 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 },
308 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 },
309+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
310 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
311 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 },
312 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 },
313@@ -913,10 +915,11 @@
314 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
315 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
316 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
317-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
318+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
319 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
320 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 },
321 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 },
322+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
323 /* dctr and dctw are used on the r5000. */
324 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
325 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
326@@ -980,6 +983,7 @@
327 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I64, 0, 0 },
328 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 },
329 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT64, 0 },
330+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
331 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
332 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
333 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I3, 0, EE },
334@@ -994,6 +998,8 @@
335 /* dmtc2 is at the bottom of the table. */
336 /* dmfc3 is at the bottom of the table. */
337 /* dmtc3 is at the bottom of the table. */
338+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
339+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
340 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
341 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 },
342 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 },
343@@ -1134,9 +1140,9 @@
344 /* The macro has to be first to handle o32 correctly. */
345 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
346 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 },
347-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
348-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
349-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
350+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
351+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
352+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
353 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
354 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
355 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
356@@ -1288,7 +1294,7 @@
357 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
358 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
359 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
360-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 },
361+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
362 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
363 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
364 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
365@@ -1332,10 +1338,13 @@
366 /* move is at the top of the table. */
367 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
368 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
369+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
370 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
371 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
372-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
373-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
374+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
375+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
376+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
377+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
378 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 },
379 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
380 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
381@@ -1381,7 +1390,7 @@
382 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
383 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
384 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
385-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 },
386+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
387 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
388 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
389 {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
390@@ -1802,9 +1811,9 @@
391 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, 0},
392 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
393 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
394-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
395-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
396-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 },
397+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
398+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
399+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
400 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2 },
401 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 },
402 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },