diff options
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch')
-rw-r--r-- | meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch b/meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch index 4ae1580102..502ce82928 100644 --- a/meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch +++ b/meta/recipes-devtools/binutils/binutils/0007-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch | |||
@@ -1,4 +1,4 @@ | |||
1 | From 883b6c0930410f8553b3bce0dd98131bc1694fa6 Mon Sep 17 00:00:00 2001 | 1 | From ef9aa69324a209e546956a2f674462717ec5af0f Mon Sep 17 00:00:00 2001 |
2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> | 2 | From: Zhenhua Luo <zhenhua.luo@nxp.com> |
3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 | 3 | Date: Sat, 11 Jun 2016 22:08:29 -0500 |
4 | Subject: [PATCH] fix the incorrect assembling for ppc wait mnemonic | 4 | Subject: [PATCH] fix the incorrect assembling for ppc wait mnemonic |
@@ -14,10 +14,10 @@ Signed-off-by: Zhenhua Luo <zhenhua.luo@nxp.com> | |||
14 | 1 file changed, 1 insertion(+), 3 deletions(-) | 14 | 1 file changed, 1 insertion(+), 3 deletions(-) |
15 | 15 | ||
16 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c | 16 | diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c |
17 | index 7637d3e349e..8e074e13208 100644 | 17 | index 37f1aeb780c..45774c7cf79 100644 |
18 | --- a/opcodes/ppc-opc.c | 18 | --- a/opcodes/ppc-opc.c |
19 | +++ b/opcodes/ppc-opc.c | 19 | +++ b/opcodes/ppc-opc.c |
20 | @@ -6947,8 +6947,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 20 | @@ -7138,8 +7138,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
21 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, | 21 | {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, |
22 | {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}}, | 22 | {"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}}, |
23 | {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}}, | 23 | {"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}}, |
@@ -26,7 +26,7 @@ index 7637d3e349e..8e074e13208 100644 | |||
26 | 26 | ||
27 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, | 27 | {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, |
28 | 28 | ||
29 | @@ -7002,7 +7000,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { | 29 | @@ -7193,7 +7191,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { |
30 | 30 | ||
31 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, | 31 | {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, |
32 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, | 32 | {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, |