diff options
Diffstat (limited to 'meta/recipes-core/glibc/glibc/eglibc-ppc8xx-cache-line-workaround.patch')
| -rw-r--r-- | meta/recipes-core/glibc/glibc/eglibc-ppc8xx-cache-line-workaround.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/meta/recipes-core/glibc/glibc/eglibc-ppc8xx-cache-line-workaround.patch b/meta/recipes-core/glibc/glibc/eglibc-ppc8xx-cache-line-workaround.patch new file mode 100644 index 0000000000..bb83d6d36e --- /dev/null +++ b/meta/recipes-core/glibc/glibc/eglibc-ppc8xx-cache-line-workaround.patch | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | 2007-06-13 Nathan Sidwell <nathan@codesourcery.com> | ||
| 2 | Mark Shinwell <shinwell@codesourcery.com> | ||
| 3 | |||
| 4 | * sysdeps/unix/sysv/linux/powerpc/libc-start.c | ||
| 5 | (__libc_start_main): Detect 8xx parts and clear | ||
| 6 | __cache_line_size if detected. | ||
| 7 | * sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c | ||
| 8 | (DL_PLATFORM_AUXV): Likewise. | ||
| 9 | |||
| 10 | Upstream-Status: Pending | ||
| 11 | |||
| 12 | Index: git/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c | ||
| 13 | =================================================================== | ||
| 14 | --- git.orig/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c 2014-08-27 18:49:23.996070587 +0000 | ||
| 15 | +++ git/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c 2014-08-27 18:49:27.332070587 +0000 | ||
| 16 | @@ -24,9 +24,21 @@ | ||
| 17 | /* Scan the Aux Vector for the "Data Cache Block Size" entry. If found | ||
| 18 | verify that the static extern __cache_line_size is defined by checking | ||
| 19 | for not NULL. If it is defined then assign the cache block size | ||
| 20 | - value to __cache_line_size. */ | ||
| 21 | + value to __cache_line_size. This is used by memset to | ||
| 22 | + optimize setting to zero. We have to detect 8xx processors, which | ||
| 23 | + have buggy dcbz implementations that cannot report page faults | ||
| 24 | + correctly. That requires reading SPR, which is a privileged | ||
| 25 | + operation. Fortunately 2.2.18 and later emulates PowerPC mfspr | ||
| 26 | + reads from the PVR register. */ | ||
| 27 | #define DL_PLATFORM_AUXV \ | ||
| 28 | case AT_DCACHEBSIZE: \ | ||
| 29 | + if (__LINUX_KERNEL_VERSION >= 0x020218) \ | ||
| 30 | + { \ | ||
| 31 | + unsigned pvr = 0; \ | ||
| 32 | + asm ("mfspr %0, 287" : "=r" (pvr)); \ | ||
| 33 | + if ((pvr & 0xffff0000) == 0x00500000) \ | ||
| 34 | + break; \ | ||
| 35 | + } \ | ||
| 36 | __cache_line_size = av->a_un.a_val; \ | ||
| 37 | break; | ||
| 38 | |||
| 39 | Index: git/sysdeps/unix/sysv/linux/powerpc/libc-start.c | ||
| 40 | =================================================================== | ||
| 41 | --- git.orig/sysdeps/unix/sysv/linux/powerpc/libc-start.c 2014-08-27 18:49:23.996070587 +0000 | ||
| 42 | +++ git/sysdeps/unix/sysv/linux/powerpc/libc-start.c 2014-08-27 18:49:27.332070587 +0000 | ||
| 43 | @@ -68,11 +68,24 @@ | ||
| 44 | rtld_fini = NULL; | ||
| 45 | } | ||
| 46 | |||
| 47 | - /* Initialize the __cache_line_size variable from the aux vector. */ | ||
| 48 | + /* Initialize the __cache_line_size variable from the aux vector. | ||
| 49 | + This is used by memset to optimize setting to zero. We have to | ||
| 50 | + detect 8xx processors, which have buggy dcbz implementations that | ||
| 51 | + cannot report page faults correctly. That requires reading SPR, | ||
| 52 | + which is a privileged operation. Fortunately 2.2.18 and later | ||
| 53 | + emulates PowerPC mfspr reads from the PVR register. */ | ||
| 54 | for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av) | ||
| 55 | switch (av->a_type) | ||
| 56 | { | ||
| 57 | case AT_DCACHEBSIZE: | ||
| 58 | + if (__LINUX_KERNEL_VERSION >= 0x020218) | ||
| 59 | + { | ||
| 60 | + unsigned pvr = 0; | ||
| 61 | + | ||
| 62 | + asm ("mfspr %0, 287" : "=r" (pvr) :); | ||
| 63 | + if ((pvr & 0xffff0000) == 0x00500000) | ||
| 64 | + break; | ||
| 65 | + } | ||
| 66 | __cache_line_size = av->a_un.a_val; | ||
| 67 | break; | ||
| 68 | } | ||