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-rw-r--r--meta/packages/qemu/qemu-0.9.1/41_arm_fpa_sigfpe.patch104
1 files changed, 0 insertions, 104 deletions
diff --git a/meta/packages/qemu/qemu-0.9.1/41_arm_fpa_sigfpe.patch b/meta/packages/qemu/qemu-0.9.1/41_arm_fpa_sigfpe.patch
deleted file mode 100644
index cea3afc7ff..0000000000
--- a/meta/packages/qemu/qemu-0.9.1/41_arm_fpa_sigfpe.patch
+++ /dev/null
@@ -1,104 +0,0 @@
1#DPATCHLEVEL=0
2---
3# linux-user/main.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++-
4# target-arm/nwfpe/fpa11.c | 7 ++++++
5# 2 files changed, 57 insertions(+), 1 deletion(-)
6#
7Index: linux-user/main.c
8===================================================================
9--- linux-user/main.c.orig 2007-12-03 15:59:10.000000000 +0000
10+++ linux-user/main.c 2007-12-03 16:01:27.000000000 +0000
11@@ -377,18 +377,67 @@ void cpu_loop(CPUARMState *env)
12 {
13 TaskState *ts = env->opaque;
14 uint32_t opcode;
15+ int rc;
16
17 /* we handle the FPU emulation here, as Linux */
18 /* we get the opcode */
19 /* FIXME - what to do if get_user() fails? */
20 get_user_u32(opcode, env->regs[15]);
21
22- if (EmulateAll(opcode, &ts->fpa, env) == 0) {
23+ rc = EmulateAll(opcode, &ts->fpa, env);
24+ if (rc == 0) { /* illegal instruction */
25 info.si_signo = SIGILL;
26 info.si_errno = 0;
27 info.si_code = TARGET_ILL_ILLOPN;
28 info._sifields._sigfault._addr = env->regs[15];
29 queue_signal(info.si_signo, &info);
30+ } else if (rc < 0) { /* FP exception */
31+ int arm_fpe=0;
32+
33+ /* translate softfloat flags to FPSR flags */
34+ if (-rc & float_flag_invalid)
35+ arm_fpe |= BIT_IOC;
36+ if (-rc & float_flag_divbyzero)
37+ arm_fpe |= BIT_DZC;
38+ if (-rc & float_flag_overflow)
39+ arm_fpe |= BIT_OFC;
40+ if (-rc & float_flag_underflow)
41+ arm_fpe |= BIT_UFC;
42+ if (-rc & float_flag_inexact)
43+ arm_fpe |= BIT_IXC;
44+
45+ FPSR fpsr = ts->fpa.fpsr;
46+ //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
47+
48+ if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
49+ info.si_signo = SIGFPE;
50+ info.si_errno = 0;
51+
52+ /* ordered by priority, least first */
53+ if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
54+ if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
55+ if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
56+ if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
57+ if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
58+
59+ info._sifields._sigfault._addr = env->regs[15];
60+ queue_signal(info.si_signo, &info);
61+ } else {
62+ env->regs[15] += 4;
63+ }
64+
65+ /* accumulate unenabled exceptions */
66+ if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
67+ fpsr |= BIT_IXC;
68+ if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
69+ fpsr |= BIT_UFC;
70+ if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
71+ fpsr |= BIT_OFC;
72+ if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
73+ fpsr |= BIT_DZC;
74+ if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
75+ fpsr |= BIT_IOC;
76+ ts->fpa.fpsr=fpsr;
77 } else {
78 /* increment PC */
79 env->regs[15] += 4;
80Index: target-arm/nwfpe/fpa11.c
81===================================================================
82--- target-arm/nwfpe/fpa11.c.orig 2007-12-03 15:40:26.000000000 +0000
83+++ target-arm/nwfpe/fpa11.c 2007-12-03 15:59:11.000000000 +0000
84@@ -162,6 +162,8 @@ unsigned int EmulateAll(unsigned int opc
85 fpa11->initflag = 1;
86 }
87
88+ set_float_exception_flags(0, &fpa11->fp_status);
89+
90 if (TEST_OPCODE(opcode,MASK_CPRT))
91 {
92 //fprintf(stderr,"emulating CPRT\n");
93@@ -191,6 +193,11 @@ unsigned int EmulateAll(unsigned int opc
94 }
95
96 // restore_flags(flags);
97+ if(nRc == 1 && get_float_exception_flags(&fpa11->fp_status))
98+ {
99+ //printf("fef 0x%x\n",float_exception_flags);
100+ nRc=-get_float_exception_flags(&fpa11->fp_status);
101+ }
102
103 //printf("returning %d\n",nRc);
104 return(nRc);