4 files changed, 281 insertions, 36 deletions

diff --git a/meta/conf/machine/include/riscv/README b/meta/conf/machine/include/riscv/README
new file mode 100644
index 0000000000..beef68f523
--- /dev/null
+++ b/meta/conf/machine/include/riscv/README
@@ -0,0 +1,122 @@
+2025/06/08 - Mark Hatle <mark.hatle@amd.com>
+ - Initial Revision
+
+The RISC-V ISA is broken into two parts, a base ISA and extensions.  As
+of the writing of this document these are documented at:
+
+https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications
+
+Specifically "The RISC-V Instruction Set Manual Volume I: Unprivileged ISA"
+was used to create this implementation.
+
+Requirements
+------------
+As RISC-V is a “variable” ISA (a base isa plus numerous extensions), a
+mechanism is required to specify a series of ISA features that a user or
+tune can use to specify a specific CPU instantiation.
+
+Not all ratified or draft features should or can be implemented with the
+available resources.
+
+The implementation should work for Linux, baremetal (newlib), zephyr and
+other operating systems.  Supported extensions should be based on
+real-world examples.
+
+Linux
+-----
+Linux required base and support extensions should be available.  Linux
+requires:
+* Base: rv32ima & rv64ima
+* Optional FPU: fd
+* Optional RISCV_ISA_C: c
+* Optiona RISCV_ISA_V: v
+* Required additional: _zicsr_zifencei
+* Optional RISCV_ISA_ZBA: _zba
+* Optional RISCV_ISA_ZBB: _zbb
+* Optional RISCV_ISA_ZBC: _zbc (not supported by current QEMU design)
+
+See: https://git.yoctoproject.org/linux-yocto/tree/arch/riscv/Makefile?h=v6.12/base
+
+Baremetal
+---------
+AMD Microblaze-V FPGA support uses the following static configurations:
+Base: rv32e, rv32i, rv64i
+Extensions: m, a, f, d, c, b, zicsr, zifencei
+
+Zephyr
+------
+AMD Microblaze-V development for Zephyr is the same as Baremetal, with a
+few additional extensions: zbc, zicbom
+
+ABI
+---
+The following ABIs are supported GNU tools and some combination of systems.
+* ilp32 - Integer, long and pointer are 32-bit
+* lp64 - Long and pointer are 64-bit (integer is 32-bit)
+
+The ABI is dependent upon the core system implementation, as ilp32 can
+only used on an ‘rv32’ system, while lp64 can only be used on an ‘rv64’
+system.
+
+There are additional variations of each ABI:
+* e - used with the Reduced register extension
+* f - used when single precision floating point (but not double precision) is
+      enabled
+* d - used when both single and double precision floating point is enabled
+
+Based on the above, the ABI should be automatically determined based on
+the selected Base ISA and Extensions.
+
+Implementation
+--------------
+To make it easier to generate the RISC-V canonical arch, ISA based -march,
+and the ABI string, a few new variables are added for specific RISC-V items.
+
+TUNE_RISCV_ARCH - This contains the canonical GNU style arch, generally this
+                  will evaluate to "riscv32" or "riscv64".
+
+TUNE_RISCV_MARCH - This will contain an ISA based -march string compatible
+                   with gcc and similar toolchains.  For example:
+                   rv32imacfd_zicsr_zifencei
+
+TUNE_RISCV_ABI - This is the generated ABI that corresponds to the ARCH and
+                 MARCH/ISA values.  For riscv32, the value will be ilp32
+                 (int, long and pointer is 32-bit) with the ISA
+                 variation.  For riscv64, the value will be lp64 (long
+                 and pointer are 64-bit bit, while int is 32-bit) with the
+                 ISA variation.  The ISA affects the ABI when the 'e', 'f'
+                 and 'd' extension are used.
+
+TUNE_RISCV_PKGARCH - This is the generated PKGARCH value.
+
+The standard variables are defined as:
+
+TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}"
+
+The above will allow the user to specify an implementation specific
+TUNE_CCARGS for a given processor tune if the default implementtion is
+not adequate for some reason.  It is expected that most, if not all,
+implementations will use the default behavior.
+
+TUNE_ARCH = "${TUNE_RISCV_ARCH}"
+TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}"
+
+The above two will always base their setting off the standard TUNE_FEATURES.
+
+Ratified and draft extensions should be implemented as TUNE_FEATURES in
+the arch-riscv.inc file.
+
+Vendor specific extensions and processor specific settings should go
+into a 'tune-<vendor>.inc' file, with tune-riscv.inc being reserved for
+general purpose tunes.
+
+TUNE_FEATURE Helper
+-------------------
+A special helper function has been written that will convert RISC-V ISA
+notation into TUNE_FEATURE notion, for example:
+
+rv32g -> rv 32 i m a f d zicsr zifencei
+
+The helper can be called using oe.tune.riscv_isa_to_tune("<ISA>") such as
+oe.tune.riscv_isa_to_tune("rv64gc") which would return:
+ rv 64 i m a f d c zicsr zifencei
diff --git a/meta/conf/machine/include/riscv/arch-riscv.inc b/meta/conf/machine/include/riscv/arch-riscv.inc
index eae2b88778..99bed8fde5 100644
--- a/meta/conf/machine/include/riscv/arch-riscv.inc
+++ b/meta/conf/machine/include/riscv/arch-riscv.inc
@@ -1,13 +1,142 @@
 # RISCV Architecture definition
 
-DEFAULTTUNE ?= "riscv64"
+# Based on the RISC-V Instruction Set Manual Volume I: Unprivileged ISA from May 2025
+# As well as the RISC-V options for using GCC (as of June 2025)
 
-TUNE_ARCH = "${TUNE_ARCH_tune-${DEFAULTTUNE}}"
-TUNE_PKGARCH = "${TUNE_PKGARCH_tune-${DEFAULTTUNE}}"
-TUNE_CCARGS_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
-TUNE_CCARGS_append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
+# Note: the following should be implemented in the order that GCC expects
+# -march= values to be defined in.
 
+# Base ISA
+# All supported march strings must start with rv32 or rv64
+TUNEVALID[rv] = "RISC-V"
+TUNE_RISCV_ARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "riscv", "", d)}"
+TUNE_RISCV_MARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "rv", "", d)}"
+TUNE_RISCV_ABI = ""
+
+# There are two primary ABIs, ilp32 and lp64
+# There are variants of both, that appears to be based on extensions above
+# For example:
+#   rv32i uses ilp32, rv32e uses ilp32e, rv32f uses ilp32f
+#   rv64i uses lp64, rv64if uses lp64f, rv64id uses lp64d
+TUNEVALID[32] = "ISA XLEN - 32-bit"
+TUNECONFLICTS[32] = "64"
+TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}"
+TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "32", "ilp32", "", d)}"
+
+TUNEVALID[64] = "ISA XLEN - 64-bit"
+TUNECONFLICTS[64] = "32"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}"
+TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}"
+TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "64", "lp64", "", d)}"
+
+# The package arch starts with the canonical arch, but adds some extensions to make
+# package compatibility clear
+TUNE_RISCV_PKGARCH = "${TUNE_RISCV_ARCH}"
+
+# i, e, or g are defined by gcc, but 'g' refers to 'i' + extensions 'MAFD Zicsr Zifencei'
+# So 'g' will not be defined here as it is an abbreviation of the expanded version
+TUNEVALID[e] = "Reduced register base integer extension"
+TUNECONFLICTS[e] = "i"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
+TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
+
+TUNEVALID[i] = "Base integer extension"
+TUNECONFLICTS[i] = "e"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
+
+# Extensions
+TUNEVALID[m] = "Integer multiplication and division extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
+
+TUNEVALID[a] = "Atomic extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
+
+TUNEVALID[f] = "Single-precision floating-point extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
+
+TUNEVALID[d] = "Double-precision floating-point extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
+
+# Only f OR d, but just one
+TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", bb.utils.contains("TUNE_FEATURES", "f", "f", "", d), d)}"
+
+TUNEVALID[c] = "Compressed extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
+
+TUNEVALID[b] = "Bit Manipulation extension"
+# Handled below via zba, zbb, zbs
+# This matches current Linux kernel behavior
+#TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
+#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
+
+TUNEVALID[v] = "Vector operations extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
+
+# Now the special Z extensions
+TUNEVALID[zicbom] = "Cache-block management extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
+
+TUNEVALID[zicsr] = "Control and status register access extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
+# If zicsr (or zifencei) is in the path, OpenSBI fails to use the extensions, do to (Makefile):
+#   # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
+#   CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep -e "zicsr" -e "zifencei" > /dev/null && echo n || echo y)
+# this will match on the path containing zicsr or zifencei when an error is reported, which
+# will always happens in this check.
+#
+# Yocto Project Bugzilla 15897
+#
+#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
+
+TUNEVALID[zifencei] = "Instruction-fetch fence extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+# See above Bug 15897
+#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
+
+TUNEVALID[zba] = "Address bit manipulation extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
+
+TUNEVALID[zbb] = "Basic bit manipulation extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
+
+TUNEVALID[zbc] = "Carry-less multiplication extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
+
+TUNEVALID[zbs] = "Single-bit manipulation extension"
+TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
+TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
+
+# Construct TUNE_CCARGS
+# This should result in a CCARG similar to:
+#   -march=rv32imac -mabi=ilp32
+TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}"
+
+# Construct TUNE_ARCH
+# This should result in an arch string similar to:
+#   riscv32
+TUNE_ARCH = "${TUNE_RISCV_ARCH}"
+
+# Construct TUNE_PKGARCH
+# This should result in a package are like:
+#    riscv32imac
+TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}"
+
+# Misc settings
 # Fix: ld: unrecognized option '--hash-style=sysv'
-LINKER_HASH_STYLE_libc-newlib = ""
+LINKER_HASH_STYLE:libc-newlib = ""
+LINKER_HASH_STYLE:libc-picolibc = ""
 # Fix: ld: unrecognized option '--hash-style=gnu'
-LINKER_HASH_STYLE_libc-baremetal = ""
+LINKER_HASH_STYLE:libc-baremetal = ""
diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc
index 47d7e9b174..65cbfd66ee 100644
--- a/meta/conf/machine/include/riscv/qemuriscv.inc
+++ b/meta/conf/machine/include/riscv/qemuriscv.inc
@@ -3,14 +3,13 @@ PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
 require conf/machine/include/qemu.inc
 require conf/machine/include/riscv/tune-riscv.inc
 
-MACHINE_FEATURES = "screen keyboard ext2 ext3 serial"
+MACHINE_FEATURES += "keyboard ext2 ext3 serial"
 
 KERNEL_IMAGETYPE = "Image"
 KERNEL_IMAGETYPES += "uImage"
 KEEPUIMAGE = "no"
 
 SERIAL_CONSOLES ?= "115200;ttyS0 115200;hvc0"
-SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}"
 
 IMAGE_FSTYPES += "ext4 wic.qcow2"
 
@@ -22,15 +21,20 @@ EXTRA_IMAGEDEPENDS += "opensbi"
 RISCV_SBI_PLAT ?= "generic"
 RISCV_SBI_PAYLOAD ?= "${KERNEL_IMAGETYPE}-${MACHINE}.bin"
 
-UBOOT_ENTRYPOINT_riscv32 = "0x80400000"
-UBOOT_ENTRYPOINT_riscv64 = "0x80200000"
+UBOOT_ENTRYPOINT:riscv32 = "0x80400000"
+UBOOT_ENTRYPOINT:riscv64 = "0x80200000"
 
 # qemuboot options
+QB_SMP ?= "-smp 4"
 QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi"
+QB_CPU:riscv64 ?= "-cpu rva22s64"
 QB_MACHINE = "-machine virt"
 QB_DEFAULT_BIOS = "fw_jump.elf"
 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"
 QB_NETWORK_DEVICE = "-device virtio-net-device,netdev=net0,mac=@MAC@"
 QB_ROOTFS_OPT = "-drive id=disk0,file=@ROOTFS@,if=none,format=raw -device virtio-blk-device,drive=disk0"
 QB_SERIAL_OPT = "-device virtio-serial-device -chardev null,id=virtcon -device virtconsole,chardev=virtcon"
-QB_TCPSERIAL_OPT = " -device virtio-serial-device -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1 -device virtconsole,chardev=virtcon"
+QB_TCPSERIAL_OPT = " -device virtio-serial-device -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1,nodelay=on -device virtconsole,chardev=virtcon"
+QB_GRAPHICS = "-device bochs-display"
+QB_OPT_APPEND = "-device qemu-xhci -device usb-tablet -device usb-kbd"
+QB_OPT_APPEND:riscv32 = "-device virtio-tablet-pci -device virtio-keyboard-pci"
diff --git a/meta/conf/machine/include/riscv/tune-riscv.inc b/meta/conf/machine/include/riscv/tune-riscv.inc
index 028548bf56..12c1125c8b 100644
--- a/meta/conf/machine/include/riscv/tune-riscv.inc
+++ b/meta/conf/machine/include/riscv/tune-riscv.inc
@@ -1,33 +1,23 @@
 require conf/machine/include/riscv/arch-riscv.inc
 
-TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
-TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
+DEFAULTTUNE ?= "riscv64"
 
-TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
-TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
-
-TUNEVALID[bigendian] = "Big endian mode"
-
-AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
+AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
 
 # Default
-TUNE_FEATURES_tune-riscv64 = "riscv64"
-TUNE_ARCH_tune-riscv64 = "riscv64"
-TUNE_PKGARCH_tune-riscv64 = "riscv64"
-PACKAGE_EXTRA_ARCHS_tune-riscv64 = "riscv64"
+TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}"
 
-TUNE_FEATURES_tune-riscv32 = "riscv32"
-TUNE_ARCH_tune-riscv32 = "riscv32"
-TUNE_PKGARCH_tune-riscv32 = "riscv32"
-PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32"
+TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}"
 
 # No float
-TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf"
-TUNE_ARCH_tune-riscv64nf = "riscv64"
-TUNE_PKGARCH_tune-riscv64nf = "riscv64nf"
-PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64nf"
+TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64nf = "${TUNE_RISCV_PKGARCH}"
+
+TUNE_FEATURES:tune-riscv32nf := "${@oe.tune.riscv_isa_to_tune("rv32imac_zicsr_zifencei")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "${TUNE_RISCV_PKGARCH}"
 
-TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf"
-TUNE_ARCH_tune-riscv32nf = "riscv32"
-TUNE_PKGARCH_tune-riscv32nf = "riscv32nf"
-PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32nf"
+# no compressed
+TUNE_FEATURES:tune-riscv64nc := "${@oe.tune.riscv_isa_to_tune("rv64imafd_zicsr_zifencei")}"
+PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "${TUNE_RISCV_PKGARCH}"