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1#
2# Copyright OpenEmbedded Contributors
3#
4# SPDX-License-Identifier: MIT
5#
6
7# Right now this is focused on arm-specific tune features.
8# We get away with this for now as one can only use x86-64 as the build host
9# (not arm).
10# Note that TUNE_FEATURES is _always_ refering to the target, so we really
11# don't want to use this for the host/build.
12def llvm_features_from_tune(d):
13 f = []
14 feat = d.getVar('TUNE_FEATURES')
15 if not feat:
16 return []
17 feat = frozenset(feat.split())
18
19 mach_overrides = d.getVar('MACHINEOVERRIDES')
20 mach_overrides = frozenset(mach_overrides.split(':'))
21
22 if 'vfpv4' in feat:
23 f.append("+vfp4")
24 elif 'vfpv4d16' in feat:
25 f.append("+vfp4")
26 f.append("-d32")
27 elif 'vfpv3' in feat:
28 f.append("+vfp3")
29 elif 'vfpv3d16' in feat:
30 f.append("+vfp3")
31 f.append("-d32")
32 elif 'vfpv2' in feat or 'vfp' in feat:
33 f.append("+vfp2")
34
35 if 'neon' in feat:
36 f.append("+neon")
37 elif target_is_armv7(d):
38 f.append("-neon")
39
40 if 'mips32' in feat:
41 f.append("+mips32")
42
43 if 'mips32r2' in feat:
44 f.append("+mips32r2")
45
46 if target_is_armv7(d):
47 f.append('+v7')
48
49 if ('armv6' in mach_overrides) or ('armv6' in feat):
50 f.append("+v6")
51 if 'armv5te' in feat:
52 f.append("+strict-align")
53 f.append("+v5te")
54 elif 'armv5' in feat:
55 f.append("+strict-align")
56 f.append("+v5")
57
58 if ('armv4' in mach_overrides) or ('armv4' in feat):
59 f.append("+strict-align")
60
61 if 'dsp' in feat:
62 f.append("+dsp")
63
64 if 'thumb' in feat:
65 if d.getVar('ARM_THUMB_OPT') == "thumb":
66 if target_is_armv7(d):
67 f.append('+thumb2')
68 f.append("+thumb-mode")
69
70 if 'cortexa5' in feat:
71 f.append("+a5")
72 if 'cortexa7' in feat:
73 f.append("+a7")
74 if 'cortexa9' in feat:
75 f.append("+a9")
76 if 'cortexa15' in feat:
77 f.append("+a15")
78 if 'cortexa17' in feat:
79 f.append("+a17")
80 if 'rv' in feat:
81 if 'm' in feat:
82 f.append("+m")
83 if 'a' in feat:
84 f.append("+a")
85 if 'f' in feat:
86 f.append("+f")
87 if 'd' in feat:
88 f.append("+d")
89 if 'c' in feat:
90 f.append("+c")
91 if 'v' in feat:
92 f.append("+v")
93 if 'zicbom' in feat:
94 f.append("+zicbom")
95 if 'zicsr' in feat:
96 f.append("+zicsr")
97 if 'zifencei' in feat:
98 f.append("+zifencei")
99 if 'zba' in feat:
100 f.append("+zba")
101 if 'zbb' in feat:
102 f.append("+zbb")
103 if 'zbc' in feat:
104 f.append("+zbc")
105 if 'zbs' in feat:
106 f.append("+zbs")
107 return f
108llvm_features_from_tune[vardepvalue] = "${@llvm_features_from_tune(d)}"
109
110# TARGET_CC_ARCH changes from build/cross/target so it'll do the right thing
111# this should go away when https://github.com/rust-lang/rust/pull/31709 is
112# stable (1.9.0?)
113def llvm_features_from_cc_arch(d):
114 f = []
115 feat = d.getVar('TARGET_CC_ARCH')
116 if not feat:
117 return []
118 feat = frozenset(feat.split())
119
120 if '-mmmx' in feat:
121 f.append("+mmx")
122 if '-msse' in feat:
123 f.append("+sse")
124 if '-msse2' in feat:
125 f.append("+sse2")
126 if '-msse3' in feat:
127 f.append("+sse3")
128 if '-mssse3' in feat:
129 f.append("+ssse3")
130 if '-msse4.1' in feat:
131 f.append("+sse4.1")
132 if '-msse4.2' in feat:
133 f.append("+sse4.2")
134 if '-msse4a' in feat:
135 f.append("+sse4a")
136 if '-mavx' in feat:
137 f.append("+avx")
138 if '-mavx2' in feat:
139 f.append("+avx2")
140
141 return f
142
143def llvm_features_from_target_fpu(d):
144 # TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float
145 # ABI. There is no option for hard.
146
147 fpu = d.getVar('TARGET_FPU')
148 return ["+soft-float"] if fpu == "soft" else []
149
150def llvm_features(d):
151 return ','.join(llvm_features_from_tune(d) +
152 llvm_features_from_cc_arch(d) +
153 llvm_features_from_target_fpu(d))
154
155llvm_features[vardepvalue] = "${@llvm_features(d)}"
156
157## arm-unknown-linux-gnueabihf
158DATA_LAYOUT[arm-eabi] = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
159TARGET_ENDIAN[arm-eabi] = "little"
160TARGET_POINTER_WIDTH[arm-eabi] = "32"
161TARGET_C_INT_WIDTH[arm-eabi] = "32"
162MAX_ATOMIC_WIDTH[arm-eabi] = "64"
163FEATURES[arm-eabi] = "+v6,+vfp2"
164
165## armv7-unknown-linux-gnueabihf
166DATA_LAYOUT[armv7-eabi] = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
167TARGET_ENDIAN[armv7-eabi] = "little"
168TARGET_POINTER_WIDTH[armv7-eabi] = "32"
169TARGET_C_INT_WIDTH[armv7-eabi] = "32"
170MAX_ATOMIC_WIDTH[armv7-eabi] = "64"
171FEATURES[armv7-eabi] = "+v7,+vfp2,+thumb2"
172
173## aarch64-unknown-linux-{gnu, musl}
174DATA_LAYOUT[aarch64] = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
175TARGET_ENDIAN[aarch64] = "little"
176TARGET_POINTER_WIDTH[aarch64] = "64"
177TARGET_C_INT_WIDTH[aarch64] = "32"
178MAX_ATOMIC_WIDTH[aarch64] = "128"
179
180## x86_64-unknown-linux-{gnu, musl}
181DATA_LAYOUT[x86_64] = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
182TARGET_ENDIAN[x86_64] = "little"
183TARGET_POINTER_WIDTH[x86_64] = "64"
184TARGET_C_INT_WIDTH[x86_64] = "32"
185MAX_ATOMIC_WIDTH[x86_64] = "64"
186
187## x86_64-unknown-linux-gnux32
188DATA_LAYOUT[x86_64-x32] = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
189TARGET_ENDIAN[x86_64-x32] = "little"
190TARGET_POINTER_WIDTH[x86_64-x32] = "32"
191TARGET_C_INT_WIDTH[x86_64-x32] = "32"
192MAX_ATOMIC_WIDTH[x86_64-x32] = "64"
193
194## i686-unknown-linux-{gnu, musl}
195DATA_LAYOUT[i686] = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128"
196TARGET_ENDIAN[i686] = "little"
197TARGET_POINTER_WIDTH[i686] = "32"
198TARGET_C_INT_WIDTH[i686] = "32"
199MAX_ATOMIC_WIDTH[i686] = "64"
200
201## XXX: a bit of a hack so qemux86 builds, clone of i686-unknown-linux-{gnu, musl} above
202DATA_LAYOUT[i586] = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128"
203TARGET_ENDIAN[i586] = "little"
204TARGET_POINTER_WIDTH[i586] = "32"
205TARGET_C_INT_WIDTH[i586] = "32"
206MAX_ATOMIC_WIDTH[i586] = "64"
207
208## mips-unknown-linux-{gnu, musl}
209DATA_LAYOUT[mips] = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
210TARGET_ENDIAN[mips] = "big"
211TARGET_POINTER_WIDTH[mips] = "32"
212TARGET_C_INT_WIDTH[mips] = "32"
213MAX_ATOMIC_WIDTH[mips] = "32"
214
215## mipsel-unknown-linux-{gnu, musl}
216DATA_LAYOUT[mipsel] = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
217TARGET_ENDIAN[mipsel] = "little"
218TARGET_POINTER_WIDTH[mipsel] = "32"
219TARGET_C_INT_WIDTH[mipsel] = "32"
220MAX_ATOMIC_WIDTH[mipsel] = "32"
221
222## mips64-unknown-linux-{gnu, musl}
223DATA_LAYOUT[mips64] = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
224TARGET_ENDIAN[mips64] = "big"
225TARGET_POINTER_WIDTH[mips64] = "64"
226TARGET_C_INT_WIDTH[mips64] = "32"
227MAX_ATOMIC_WIDTH[mips64] = "64"
228
229## mips64-n32-unknown-linux-{gnu, musl}
230DATA_LAYOUT[mips64-n32] = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
231TARGET_ENDIAN[mips64-n32] = "big"
232TARGET_POINTER_WIDTH[mips64-n32] = "32"
233TARGET_C_INT_WIDTH[mips64-n32] = "32"
234MAX_ATOMIC_WIDTH[mips64-n32] = "64"
235
236## mips64el-unknown-linux-{gnu, musl}
237DATA_LAYOUT[mips64el] = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
238TARGET_ENDIAN[mips64el] = "little"
239TARGET_POINTER_WIDTH[mips64el] = "64"
240TARGET_C_INT_WIDTH[mips64el] = "32"
241MAX_ATOMIC_WIDTH[mips64el] = "64"
242
243## powerpc-unknown-linux-{gnu, musl}
244DATA_LAYOUT[powerpc] = "E-m:e-p:32:32-Fn32-i64:64-n32"
245TARGET_ENDIAN[powerpc] = "big"
246TARGET_POINTER_WIDTH[powerpc] = "32"
247TARGET_C_INT_WIDTH[powerpc] = "32"
248MAX_ATOMIC_WIDTH[powerpc] = "32"
249
250## powerpc64-unknown-linux-{gnu, musl}
251DATA_LAYOUT[powerpc64] = "E-m:e-Fi64-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512"
252TARGET_ENDIAN[powerpc64] = "big"
253TARGET_POINTER_WIDTH[powerpc64] = "64"
254TARGET_C_INT_WIDTH[powerpc64] = "32"
255MAX_ATOMIC_WIDTH[powerpc64] = "64"
256
257## powerpc64le-unknown-linux-{gnu, musl}
258DATA_LAYOUT[powerpc64le] = "e-m:e-Fn32-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512"
259TARGET_ENDIAN[powerpc64le] = "little"
260TARGET_POINTER_WIDTH[powerpc64le] = "64"
261TARGET_C_INT_WIDTH[powerpc64le] = "32"
262MAX_ATOMIC_WIDTH[powerpc64le] = "64"
263
264## riscv32-unknown-linux-{gnu, musl}
265DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128"
266TARGET_ENDIAN[riscv32] = "little"
267TARGET_POINTER_WIDTH[riscv32] = "32"
268TARGET_C_INT_WIDTH[riscv32] = "32"
269MAX_ATOMIC_WIDTH[riscv32] = "32"
270
271## riscv64-unknown-linux-{gnu, musl}
272DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
273TARGET_ENDIAN[riscv64] = "little"
274TARGET_POINTER_WIDTH[riscv64] = "64"
275TARGET_C_INT_WIDTH[riscv64] = "32"
276MAX_ATOMIC_WIDTH[riscv64] = "64"
277
278## loongarch64-unknown-linux-{gnu, musl}
279DATA_LAYOUT[loongarch64] = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
280TARGET_ENDIAN[loongarch64] = "little"
281TARGET_POINTER_WIDTH[loongarch64] = "64"
282TARGET_C_INT_WIDTH[loongarch64] = "32"
283MAX_ATOMIC_WIDTH[loongarch64] = "64"
284FEATURES[loongarch64] = "+d"
285
286# Convert a normal arch (HOST_ARCH, TARGET_ARCH, BUILD_ARCH, etc) to something
287# rust's internals won't choke on.
288def arch_to_rust_target_arch(arch):
289 if arch == "i586" or arch == "i686":
290 return "x86"
291 elif arch == "mipsel":
292 return "mips"
293 elif arch == "mip64sel":
294 return "mips64"
295 elif arch == "armv7":
296 return "arm"
297 elif arch == "powerpc64le":
298 return "powerpc64"
299 else:
300 return arch
301
302# Convert a rust target string to a llvm-compatible triplet
303def rust_sys_to_llvm_target(sys):
304 return sys
305
306# generates our target CPU value
307def llvm_cpu(d):
308 cpu = d.getVar('PACKAGE_ARCH')
309 target = d.getVar('TRANSLATED_TARGET_ARCH')
310
311 trans = {}
312 trans['corei7-64'] = "corei7"
313 trans['core2-32'] = "core2"
314 trans['x86-64'] = "x86-64"
315 trans['i686'] = "i686"
316 trans['i586'] = "i586"
317 trans['mips64'] = "mips64"
318 trans['mips64el'] = "mips64"
319 trans['powerpc64le'] = "ppc64le"
320 trans['powerpc64'] = "ppc64"
321 trans['riscv64'] = "generic-rv64"
322 trans['riscv32'] = "generic-rv32"
323 trans['loongarch64'] = "la464"
324
325 if target in ["mips", "mipsel", "powerpc"]:
326 feat = frozenset(d.getVar('TUNE_FEATURES').split())
327 if "mips32r2" in feat:
328 trans['mipsel'] = "mips32r2"
329 trans['mips'] = "mips32r2"
330 elif "mips32" in feat:
331 trans['mipsel'] = "mips32"
332 trans['mips'] = "mips32"
333 elif "ppc7400" in feat:
334 trans['powerpc'] = "7400"
335
336 try:
337 return trans[cpu]
338 except:
339 return trans.get(target, "generic")
340
341llvm_cpu[vardepvalue] = "${@llvm_cpu(d)}"
342
343def rust_gen_target(d, thing, wd, arch):
344 import json
345
346 build_sys = d.getVar('BUILD_SYS')
347 target_sys = d.getVar('TARGET_SYS')
348
349 sys = d.getVar('{}_SYS'.format(thing))
350 prefix = d.getVar('{}_PREFIX'.format(thing))
351 rustsys = d.getVar('RUST_{}_SYS'.format(thing))
352 os = d.getVar('{}_OS'.format(thing))
353
354 abi = None
355 cpu = "generic"
356 features = ""
357
358 # Need to apply the target tuning consitently, only if the triplet applies to the target
359 # and not in the native case
360 if sys == target_sys and sys != build_sys:
361 abi = d.getVar('ABIEXTENSION')
362 cpu = llvm_cpu(d)
363 if bb.data.inherits_class('native', d):
364 features = ','.join(llvm_features_from_cc_arch(d))
365 else:
366 features = llvm_features(d) or ""
367 # arm and armv7 have different targets in llvm
368 if arch == "arm" and target_is_armv7(d):
369 arch = 'armv7'
370
371 rust_arch = oe.rust.arch_to_rust_arch(arch)
372
373 if abi:
374 arch_abi = "{}-{}".format(rust_arch, abi)
375 else:
376 arch_abi = rust_arch
377
378 features = features or d.getVarFlag('FEATURES', arch_abi) or ""
379 features = features.strip()
380
381 # build tspec
382 tspec = {}
383 tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys)
384 tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi)
385 if tspec['data-layout'] is None:
386 bb.fatal("No rust target defined for %s" % arch_abi)
387 tspec['max-atomic-width'] = int(d.getVarFlag('MAX_ATOMIC_WIDTH', arch_abi))
388 tspec['target-pointer-width'] = d.getVarFlag('TARGET_POINTER_WIDTH', arch_abi)
389 tspec['target-c-int-width'] = int(d.getVarFlag('TARGET_C_INT_WIDTH', arch_abi))
390 tspec['target-endian'] = d.getVarFlag('TARGET_ENDIAN', arch_abi)
391 tspec['arch'] = arch_to_rust_target_arch(rust_arch)
392 if "elf" in os:
393 tspec['os'] = "none"
394 else:
395 tspec['os'] = "linux"
396 if "musl" in tspec['llvm-target']:
397 tspec['env'] = "musl"
398 else:
399 tspec['env'] = "gnu"
400 if "riscv64" in tspec['llvm-target']:
401 tspec['llvm-abiname'] = d.getVar('TUNE_RISCV_ABI')
402 if "riscv32" in tspec['llvm-target']:
403 tspec['llvm-abiname'] = d.getVar('TUNE_RISCV_ABI')
404 if "loongarch64" in tspec['llvm-target']:
405 tspec['llvm-abiname'] = "lp64d"
406 if "powerpc64le" in tspec['llvm-target']:
407 tspec['llvm-abiname'] = "elfv2"
408 elif "powerpc64" in tspec['llvm-target']:
409 tspec['llvm-abiname'] = "elfv1"
410 tspec['vendor'] = "unknown"
411 tspec['target-family'] = "unix"
412 tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)
413 tspec['cpu'] = cpu
414 if features != "":
415 tspec['features'] = features
416 fpu = d.getVar('TARGET_FPU')
417 if fpu in ["soft", "softfp"]:
418 tspec['llvm-floatabi'] = "soft"
419 elif fpu == "hard":
420 tspec['llvm-floatabi'] = "hard"
421 tspec['dynamic-linking'] = True
422 tspec['executables'] = True
423 tspec['linker-is-gnu'] = True
424 tspec['linker-flavor'] = "gcc"
425 tspec['has-rpath'] = True
426 tspec['has-thread-local'] = True
427 tspec['position-independent-executables'] = True
428 tspec['panic-strategy'] = d.getVar("RUST_PANIC_STRATEGY")
429
430 # write out the target spec json file
431 with open(wd + rustsys + '.json', 'w') as f:
432 json.dump(tspec, f, indent=4)
433
434# These are accounted for in tmpdir path names so don't need to be in the task sig
435rust_gen_target[vardepsexclude] += "ABIEXTENSION llvm_cpu"
436
437do_rust_gen_targets[vardeps] += "DATA_LAYOUT TARGET_ENDIAN TARGET_POINTER_WIDTH TARGET_C_INT_WIDTH MAX_ATOMIC_WIDTH FEATURES"
438
439RUST_TARGETS_DIR = "${WORKDIR}/rust-targets/"
440export RUST_TARGET_PATH = "${RUST_TARGETS_DIR}"
441
442python do_rust_gen_targets () {
443 wd = d.getVar('RUST_TARGETS_DIR')
444 # Order of BUILD, HOST, TARGET is important in case the files overwrite, most specific last
445 rust_gen_target(d, 'BUILD', wd, d.getVar('BUILD_ARCH'))
446 rust_gen_target(d, 'HOST', wd, d.getVar('HOST_ARCH'))
447 rust_gen_target(d, 'TARGET', wd, d.getVar('TARGET_ARCH'))
448}
449
450addtask rust_gen_targets after do_patch before do_configure
451do_rust_gen_targets[dirs] += "${RUST_TARGETS_DIR}"
452
453# For building target C dependecies use only compiler parameters defined in OE
454# and ignore the CC crate defaults which conflicts with OE ones in some cases.
455# https://github.com/rust-lang/cc-rs#external-configuration-via-environment-variables
456# Some CC crate compiler flags are still required.
457# We apply them conditionally in rust wrappers.
458
459CRATE_CC_FLAGS:class-native = ""
460CRATE_CC_FLAGS:class-nativesdk = ""
461CRATE_CC_FLAGS:class-target = " -ffunction-sections -fdata-sections -fPIC"
462
463do_compile:prepend:class-target() {
464 export CRATE_CC_NO_DEFAULTS=1
465}
466do_install:prepend:class-target() {
467 export CRATE_CC_NO_DEFAULTS=1
468}
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2025-11-07 21:33:36 +0000