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| author | Bruce Ashfield <bruce.ashfield@windriver.com> | 2015-09-29 10:31:34 -0400 |
|---|---|---|
| committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2015-10-01 07:43:34 +0100 |
| commit | b0545068c761b41051fe6a41ea6f61e46b44ae05 (patch) | |
| tree | db76652e6b811afb8e28538f5ccb8b06bbf9d2dc /meta/site/mips-linux-uclibc | |
| parent | c6c093b6f787fb2104cff76924bc6473e65e70d3 (diff) | |
| download | poky-b0545068c761b41051fe6a41ea6f61e46b44ae05.tar.gz | |
linux-yocto/4.1: braswell bug fixes
Updating the 4.1 SRCREVs to integrate the following DRM backports:
a8abc111a96d drm/i915: Only wait for required lanes in vlv_wait_port_ready()
81354180432b Revert "drm/i915: Hack to tie both common lanes together on chv"
d660fc117731 drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV
0e797e9cb717 drm/i915: Implement chv display PHY lane stagger setup
(From OE-Core rev: 2ea7533b5d45bb459284dd1c3f81d4bcac88f882)
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/site/mips-linux-uclibc')
0 files changed, 0 insertions, 0 deletions