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authorSaul Wold <Saul.Wold@intel.com>2010-09-24 15:36:24 -0700
committerSaul Wold <Saul.Wold@intel.com>2010-09-24 16:43:21 -0700
commit239a368d5715d8f5b7733f9400339c2350c49369 (patch)
tree2953f12b45e590d9e14b6f72f8e4ee7188e41508 /meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch
parentc5b9525263dac6844d152e40acf8cee4d27b60bc (diff)
downloadpoky-239a368d5715d8f5b7733f9400339c2350c49369.tar.gz
netbook: Correct netbook build by moving netbook configuration from moblin to meta
Signed-off-by: Saul Wold <Saul.Wold@intel.com>
Diffstat (limited to 'meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch')
-rw-r--r--meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch10167
1 files changed, 10167 insertions, 0 deletions
diff --git a/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch
new file mode 100644
index 0000000000..6a9c431dbc
--- /dev/null
+++ b/meta/recipes-kernel/linux/linux-netbook-2.6.33.2/linux-2.6.35-moorestown-camera-driver-10.0-1-3.patch
@@ -0,0 +1,10167 @@
1From 3c67994c10958001bebd89356a96358904ac9779 Mon Sep 17 00:00:00 2001
2From: Zheng Ba <zheng.ba@intel.com>
3Date: Thu, 1 Apr 2010 16:16:57 +0800
4Subject: [PATCH 1/3] Moorestown Camera Imaging driver Beta 10.0
5
6Patch-mainline: 2.6.35?
7
8Changes from Beta 9.0:
91. Fixed hsd sighting
10 3469638 3469639 3469710 3469822 (high)
11 3469697 (medium)
12
13Changes from Beta 8.0:
141. Fixed hsd sighting
15 3469056 3469058 (critical)
16 3469705 3469696 3469709 3469510 (medium)
17
18Changes from Beta 7.0:
191. Fixed hsd sighting 3469681,3469682,3469683 (high)
20
21Changes from Beta 6.0:
221. Fixed hsd sighting 3469668 (high)
232. Fixed ov5630 v4l2 view-finding dark issue
243. Enabled support for popular v4l2 applications (cheese, skype, ffmpeg)
25
26Changes from Beta 5.1:
271. Fixed CRITICAL sighting 3469558 -- ciapp fails to launch with segment fault
282. Fixed HIGH sighting 3479513 -- ov5630 AWB unstable
293. Improved KMOT sensor 720p fps from 30 to 40
30
31Changes from Beta 5.0:
32Fixed a critical issue of camera driver not loading -- hsd 3469557
33
34Main changes from Beta 4.0:
35Fixed 4 HSD sightings: 3469392,3469099,3469470,3469500
36
37Main changes from Beta 3.0:
38Fixed 7 HSD sightings: 3469264,3469112,3469395,3469103,3469105,3469471,3469484
39
40Main changes from Beta 2.0:
41Fixed 6 HSD sightings: 3469047,3469315,3469317,3469101,3468409,3469391
42
43Main changes from Beta 1.1:
441. Added interrupt mode for jpeg capture and KMOT viewfinding
452. Fixed HSD sighting 3469228 and 3469147
46
47Main changes from Alpha2:
48Enabled MIPI interface in ISP driver and KMOT sensor s5k4e1.
49Enabled FIFO in ISP driver, which doubled the fps in view-finding mode.
50Enabled Subdev Framework in CI kernel driver.
51Enabled AF Continuous Mode.
52Enabled AE scene evaluation.
53
54Enabled the camera drivers in kernel:
55Device Drivers --> Multimedia support --> Video For Linux
56Device Drivers --> Mulitmedia support --> Video capture adapters -->
57--> Moorestown Langwell Camera Imaging Subsystem support.
58
59Kernel configs:
601. camera driver depends on GPIO library and I2C driver.
61CONFIG_GENERIC_GPIO=y
62CONFIG_I2C=y
63CONFIG_GPIOLIB=y
642. camera driver depends on videobuf-core and videobuf-dma-contig.
65VIDEOBUF_GEN=y
66VIDEOBUF_DMA_CONTIG=y
673. enable multimedia support and video capture.
68CONFIG_MEDIA_SUPPORT=y
69CONFIG_VIDEO_DEV=y
70CONFIG_VIDEO_V4L2_COMMON=y
71CONFIG_VIDEO_MEDIA=y
72CONFIG_VIDEO_V4L2=y
734. camera drivers incluing ISP, 5630, 5630-motor, s5k4e1, s5k4e1-motor, 2650,
749665, flash.
75CONFIG_VIDEO_MRSTCI=y
76CONFIG_VIDEO_MRST_ISP=y
77CONFIG_VIDEO_MRST_OV5630=y
78CONFIG_VIDEO_MRST_OV5630_MOTOR=y
79CONFIG_VIDEO_MRST_S5K4E1=y
80CONFIG_VIDEO_MRST_S5K4E1_MOTOR=y
81CONFIG_VIDEO_MRST_FLASH=y
82CONFIG_VIDEO_MRST_OV2650=y
83CONFIG_VIDEO_MRST_OV9665=y
84
85Signed-off-by: Zheng Ba <zheng.ba@intel.com>
86---
87 drivers/media/video/Kconfig | 1
88 drivers/media/video/Makefile | 9
89 drivers/media/video/mrstci/include/ci_isp_common.h | 1422 +++
90 drivers/media/video/mrstci/include/ci_isp_fmts_common.h | 128
91 drivers/media/video/mrstci/include/ci_sensor_common.h | 1233 ++
92 drivers/media/video/mrstci/include/ci_va.h | 42
93 drivers/media/video/mrstci/include/v4l2_jpg_review.h | 48
94 drivers/media/video/mrstci/mrstisp/include/def.h | 122
95 drivers/media/video/mrstci/mrstisp/include/mrstisp.h | 279
96 drivers/media/video/mrstci/mrstisp/include/mrstisp_dp.h | 317
97 drivers/media/video/mrstci/mrstisp/include/mrstisp_hw.h | 245
98 drivers/media/video/mrstci/mrstisp/include/mrstisp_isp.h | 42
99 drivers/media/video/mrstci/mrstisp/include/mrstisp_jpe.h | 426
100 drivers/media/video/mrstci/mrstisp/include/mrstisp_reg.h | 4698 ++++++++++
101 drivers/media/video/mrstci/mrstisp/include/mrstisp_stdinc.h | 119
102 drivers/media/video/mrstci/mrstisp/include/project_settings_mrv.h | 622 +
103 drivers/media/video/mrstci/mrstisp/include/reg_access.h | 233
104 17 files changed, 9986 insertions(+)
105 create mode 100644 drivers/media/video/mrstci/include/ci_isp_common.h
106 create mode 100644 drivers/media/video/mrstci/include/ci_isp_fmts_common.h
107 create mode 100644 drivers/media/video/mrstci/include/ci_sensor_common.h
108 create mode 100644 drivers/media/video/mrstci/include/ci_va.h
109 create mode 100644 drivers/media/video/mrstci/include/v4l2_jpg_review.h
110 create mode 100644 drivers/media/video/mrstci/mrstisp/include/def.h
111 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp.h
112 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_dp.h
113 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_hw.h
114 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_isp.h
115 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_jpe.h
116 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_reg.h
117 create mode 100644 drivers/media/video/mrstci/mrstisp/include/mrstisp_stdinc.h
118 create mode 100644 drivers/media/video/mrstci/mrstisp/include/project_settings_mrv.h
119 create mode 100644 drivers/media/video/mrstci/mrstisp/include/reg_access.h
120
121--- a/drivers/media/video/Kconfig
122+++ b/drivers/media/video/Kconfig
123@@ -1074,4 +1074,5 @@ config USB_S2255
124 This driver can be compiled as a module, called s2255drv.
125
126 endif # V4L_USB_DRIVERS
127+source "drivers/media/video/mrstci/Kconfig"
128 endif # VIDEO_CAPTURE_DRIVERS
129--- a/drivers/media/video/Makefile
130+++ b/drivers/media/video/Makefile
131@@ -169,6 +169,15 @@ obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2
132
133 obj-$(CONFIG_ARCH_DAVINCI) += davinci/
134
135+obj-$(CONFIG_VIDEO_MRST_OV2650) += mrstci/mrstov2650/
136+obj-$(CONFIG_VIDEO_MRST_OV5630) += mrstci/mrstov5630/
137+obj-$(CONFIG_VIDEO_MRST_OV5630_MOTOR) += mrstci/mrstov5630_motor/
138+obj-$(CONFIG_VIDEO_MRST_S5K4E1) += mrstci/mrsts5k4e1/
139+obj-$(CONFIG_VIDEO_MRST_S5K4E1_MOTOR) += mrstci/mrsts5k4e1_motor/
140+obj-$(CONFIG_VIDEO_MRST_OV9665) += mrstci/mrstov9665/
141+obj-$(CONFIG_VIDEO_MRST_FLASH) += mrstci/mrstflash/
142+obj-$(CONFIG_VIDEO_MRST_ISP) += mrstci/mrstisp/
143+
144 EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
145 EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
146 EXTRA_CFLAGS += -Idrivers/media/common/tuners
147--- /dev/null
148+++ b/drivers/media/video/mrstci/include/ci_isp_common.h
149@@ -0,0 +1,1422 @@
150+/*
151+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
152+ *
153+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
154+ *
155+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
156+ *
157+ * This program is free software; you can redistribute it and/or
158+ * modify it under the terms of the GNU General Public License version
159+ * 2 as published by the Free Software Foundation.
160+ *
161+ * This program is distributed in the hope that it will be useful,
162+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
163+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
164+ * GNU General Public License for more details.
165+ *
166+ * You should have received a copy of the GNU General Public License
167+ * along with this program; if not, write to the Free Software
168+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
169+ * 02110-1301, USA.
170+ *
171+ *
172+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
173+ */
174+
175+#ifndef _CI_ISP_COMMON_H
176+#define _CI_ISP_COMMON_H
177+
178+#include "v4l2_jpg_review.h"
179+
180+/*
181+ * MARVIN VI ID defines -> changed to MARVIN_FEATURE_CHIP_ID and moved to
182+ * the other chip features in project_settings.h
183+ * JPEG compression ratio defines
184+ */
185+
186+#define CI_ISP_JPEG_HIGH_COMPRESSION 1
187+#define CI_ISP_JPEG_LOW_COMPRESSION 2
188+/* Low Compression / High Quality */
189+#define CI_ISP_JPEG_01_PERCENT 3
190+#define CI_ISP_JPEG_20_PERCENT 4
191+#define CI_ISP_JPEG_30_PERCENT 5
192+#define CI_ISP_JPEG_40_PERCENT 6
193+/* Mid Compression / Mid Quality */
194+#define CI_ISP_JPEG_50_PERCENT 7
195+#define CI_ISP_JPEG_60_PERCENT 8
196+#define CI_ISP_JPEG_70_PERCENT 9
197+#define CI_ISP_JPEG_80_PERCENT 10
198+#define CI_ISP_JPEG_90_PERCENT 11
199+/* High Compression / Low Quality */
200+#define CI_ISP_JPEG_99_PERCENT 12
201+
202+/* Size of lens shading data table in 16 Bit words */
203+#define CI_ISP_DATA_TBL_SIZE 289
204+/* Size of lens shading grad table in 16 Bit words */
205+#define CI_ISP_GRAD_TBL_SIZE 8
206+/* Number of lens shading sectors in x or y direction */
207+#define CI_ISP_MAX_LSC_SECTORS 16
208+
209+/*
210+ * Value representing 1.0 for fixed-point values
211+ * used by marvin drivers
212+ */
213+#define CI_ISP_FIXEDPOINT_ONE (0x1000)
214+/* JPEG encoding */
215+
216+enum ci_isp_jpe_enc_mode {
217+ /* motion JPEG with header generation */
218+ CI_ISP_JPE_LARGE_CONT_MODE = 0x04,
219+ /* motion JPEG only first frame with header */
220+ CI_ISP_JPE_SHORT_CONT_MODE = 0x02,
221+ /* JPEG with single snapshot */
222+ CI_ISP_JPE_SINGLE_SHOT = 0x01
223+};
224+
225+/* for demosaic mode */
226+enum ci_isp_demosaic_mode {
227+ CI_ISP_DEMOSAIC_STANDARD,
228+ CI_ISP_DEMOSAIC_ENHANCED
229+};
230+
231+struct ci_isp_window{
232+ unsigned short hoffs;
233+ unsigned short voffs;
234+ unsigned short hsize;
235+ unsigned short vsize;
236+};
237+
238+/* scale settings for both self and main resize unit */
239+struct ci_isp_scale {
240+ u32 scale_hy;
241+ u32 scale_hcb;
242+ u32 scale_hcr;
243+ u32 scale_vy;
244+ u32 scale_vc;
245+ u16 phase_hy;
246+ u16 phase_hc;
247+ u16 phase_vy;
248+ u16 phase_vc;
249+};
250+
251+/* A Lookup table for the upscale parameter in the self and main scaler */
252+struct ci_isp_rsz_lut{
253+ u8 rsz_lut[64];
254+};
255+
256+#if (MARVIN_FEATURE_SCALE_FACTORWIDTH == MARVIN_FEATURE_16BITS)
257+/* flag to set in scalefactor values to enable upscaling */
258+#define RSZ_UPSCALE_ENABLE 0x20000
259+#else
260+/* flag to set in scalefactor values to enable upscaling */
261+#define RSZ_UPSCALE_ENABLE 0x8000
262+/* #if (MARVIN_FEATURE_SCALE_FACTORWIDTH == MARVIN_FEATURE_16BITS) */
263+#endif
264+
265+/*
266+ * Flag to set in scalefactor values to bypass the scaler block.
267+ * Since this define is also used in calculations of scale factors and
268+ * coordinates, it needs to reflect the scale factor precision. In other
269+ * words:
270+ * RSZ_SCALER_BYPASS = max. scalefactor value> + 1
271+ */
272+#if (MARVIN_FEATURE_SCALE_FACTORWIDTH == MARVIN_FEATURE_12BITS)
273+#define RSZ_SCALER_BYPASS 0x1000
274+#elif (MARVIN_FEATURE_SCALE_FACTORWIDTH == MARVIN_FEATURE_14BITS)
275+#define RSZ_SCALER_BYPASS 0x4000
276+#elif (MARVIN_FEATURE_SCALE_FACTORWIDTH == MARVIN_FEATURE_16BITS)
277+#define RSZ_SCALER_BYPASS 0x10000
278+#endif
279+
280+#define RSZ_FLAGS_MASK (RSZ_UPSCALE_ENABLE | RSZ_SCALER_BYPASS)
281+
282+/* color settings */
283+struct ci_isp_color_settings {
284+ u8 contrast;
285+ u8 brightness;
286+ u8 saturation;
287+ u8 hue;
288+ u32 flags;
289+};
290+
291+/* color processing chrominance clipping range */
292+#define CI_ISP_CPROC_C_OUT_RANGE 0x08
293+/* color processing luminance input range (offset processing) */
294+#define CI_ISP_CPROC_Y_IN_RANGE 0x04
295+/* color processing luminance output clipping range */
296+#define CI_ISP_CPROC_Y_OUT_RANGE 0x02
297+/* color processing enable */
298+#define CI_ISP_CPROC_ENABLE 0x01
299+
300+/* black level config */
301+struct ci_isp_blc_config {
302+ int bls_auto;
303+ int henable;
304+ int venable;
305+ u16 hstart;
306+ u16 hstop;
307+ u16 vstart;
308+ u16 vstop;
309+ u8 blc_samples;
310+ u8 ref_a;
311+ u8 ref_b;
312+ u8 ref_c;
313+ u8 ref_d;
314+};
315+
316+/* black level compensation mean values */
317+struct ci_isp_blc_mean {
318+ u8 mean_a;
319+ u8 mean_b;
320+ u8 mean_c;
321+ u8 mean_d;
322+};
323+
324+/* BLS window */
325+struct ci_isp_bls_window {
326+
327+ /* En-/disable the measurement window. */
328+ int enable_window;
329+ /* Horizontal start address. */
330+ u16 start_h;
331+ /* Horizontal stop address. */
332+ u16 stop_h;
333+ /* Vertical start address. */
334+ u16 start_v;
335+ /* Vertical stop address. */
336+ u16 stop_v;
337+};
338+
339+/* BLS mean measured values */
340+struct ci_isp_bls_measured {
341+ /* Mean measured value for Bayer pattern position A. */
342+ u16 meas_a;
343+ /* Mean measured value for Bayer pattern position B. */
344+ u16 meas_b;
345+ /* Mean measured value for Bayer pattern position C. */
346+ u16 meas_c;
347+ /* Mean measured value for Bayer pattern position D. */
348+ u16 meas_d;
349+};
350+
351+/*
352+ * BLS fixed subtraction values. The values will be subtracted from the sensor
353+ * values. Therefore a negative value means addition instead of subtraction
354+ */
355+struct ci_isp_bls_subtraction {
356+ /* Fixed (signed ) subtraction value for Bayer pattern position A. */
357+ s16 fixed_a;
358+ /* Fixed (signed ) subtraction value for Bayer pattern position B. */
359+ s16 fixed_b;
360+ /* Fixed (signed ) subtraction value for Bayer pattern position C. */
361+ s16 fixed_c;
362+ /* Fixed (signed ) subtraction value for Bayer pattern position D. */
363+ s16 fixed_d;
364+};
365+
366+/* BLS configuration */
367+struct ci_isp_bls_config {
368+ /*
369+ * Automatic mode activated means that the measured values are
370+ * subtracted. Otherwise the fixed subtraction values will be
371+ * subtracted.
372+ */
373+ int enable_automatic;
374+ /* En-/disable horizontal accumulation for mean black value. */
375+ int disable_h;
376+ /*
377+ * BLS module versions 4 or higher imply that it is enabled.
378+ * En-/disable vertical accumulation for mean black value.
379+ */
380+ int disable_v;
381+ /* Measurement window 1. */
382+ struct ci_isp_bls_window isp_bls_window1;
383+ /* Measurement window 2. */
384+ struct ci_isp_bls_window isp_bls_window2;
385+
386+ /*
387+ * BLS module version 3 and lower do not support a second
388+ * measurement window. Therefore the second window has to
389+ * be disabled for these versions.
390+ */
391+
392+ /*
393+ * Set amount of measured pixels for each Bayer position (A, B,
394+ * C and D) to 2^bls_samples.
395+ */
396+ u8 bls_samples;
397+ /* Fixed subtraction values. */
398+ struct ci_isp_bls_subtraction bls_subtraction;
399+};
400+
401+/* white balancing modes for the marvin hardware */
402+enum ci_isp_awb_mode {
403+ CI_ISP_AWB_COMPLETELY_OFF = 0,
404+ CI_ISP_AWB_AUTO,
405+ CI_ISP_AWB_MAN_MEAS,
406+ CI_ISP_AWB_MAN_NOMEAS,
407+ CI_ISP_AWB_MAN_PUSH_AUTO,
408+ CI_ISP_AWB_ONLY_MEAS
409+};
410+
411+/* white balancing modes for the marvin hardware */
412+enum ci_isp_awb_sub_mode {
413+ CI_ISP_AWB_SUB_OFF = 0,
414+ CI_ISP_AWB_MAN_DAYLIGHT,
415+ CI_ISP_AWB_MAN_CLOUDY,
416+ CI_ISP_AWB_MAN_SHADE,
417+ CI_ISP_AWB_MAN_FLUORCNT,
418+ CI_ISP_AWB_MAN_FLUORCNTH,
419+ CI_ISP_AWB_MAN_TUNGSTEN,
420+ CI_ISP_AWB_MAN_TWILIGHT,
421+ CI_ISP_AWB_MAN_SUNSET,
422+ CI_ISP_AWB_MAN_FLASH,
423+ CI_ISP_AWB_MAN_CIE_D65,
424+ CI_ISP_AWB_MAN_CIE_D75,
425+ CI_ISP_AWB_MAN_CIE_F2,
426+ CI_ISP_AWB_MAN_CIE_F11,
427+ CI_ISP_AWB_MAN_CIE_F12,
428+ CI_ISP_AWB_MAN_CIE_A,
429+ CI_ISP_AWB_AUTO_ON
430+};
431+
432+/*
433+ * white balancing gains
434+ * xiaolin, typedef ci_sensor_component_gain tsMrvWbGains;
435+ * white balancing measurement configuration
436+ */
437+struct ci_isp_wb_meas_config {
438+ /* white balance measurement window (in pixels) */
439+ struct ci_isp_window awb_window;
440+ /*
441+ * only pixels values max_y contribute to WB measurement
442+ * (set to 0 to disable this feature)
443+ */
444+ u8 max_y;
445+ /* only pixels values > min_y contribute to WB measurement */
446+ u8 ref_cr_MaxR;
447+ u8 minY_MaxG;
448+ u8 ref_cb_MaxB;
449+ /*
450+ * Chrominance sum maximum value, only consider pixels with Cb+Cr
451+ * smaller than threshold for WB measurements
452+ */
453+ u8 max_csum;
454+
455+ /*
456+ * Chrominance minimum value, only consider pixels with Cb/Cr each
457+ * greater than threshold value for WB measurements
458+ */
459+ u8 min_c;
460+ /*
461+ * number of frames+1 used for mean value calculation (frames=0
462+ * means 1 Frame)
463+ */
464+ u8 frames;
465+ u8 meas_mode;
466+};
467+
468+/* white balancing measurement configuration limits */
469+struct ci_isp_wb_meas_conf_limit {
470+ /* maximum value for MinY */
471+ u8 min_y_max;
472+ /* minimum value for MinY */
473+ u8 min_y_min;
474+ /* maximum value for MinC */
475+ u8 min_c_max;
476+ /* minimum value for MinC */
477+ u8 min_c_min;
478+ /* maximum value for MaxCSum */
479+ u8 max_csum_max;
480+ /* minimum value for MaxCSum */
481+ u8 max_csum_min;
482+ /* maximum value for white pixel percentage */
483+ u8 white_percent_max;
484+ /* minimum value for white pixel percentage */
485+ u8 white_percent_min;
486+ /*
487+ * maximum number of not measured frames until the gain values
488+ * will be set to their initial values
489+ */
490+ u8 error_counter;
491+};
492+
493+/* white balancing HW automatic configuration */
494+struct ci_isp_wb_auto_hw_config {
495+ /* reference C values */
496+ u8 ref_cr;
497+ u8 ref_cb;
498+ /* lock / unlock settings */
499+ u8 unlock_dly;
500+ u8 unlock_rng;
501+ u8 lock_dly;
502+ u8 lock_rng;
503+ /* maximum gain step size */
504+ u8 step;
505+ /* gain limits */
506+ u8 max_gain;
507+ u8 min_gain;
508+};
509+
510+/* white balancing configuration */
511+struct ci_isp_wb_config {
512+ /* mode of operation */
513+ enum ci_isp_awb_mode mrv_wb_mode;
514+ enum ci_isp_awb_sub_mode mrv_wb_sub_mode;
515+ /* measurement configuration */
516+ struct ci_isp_wb_meas_config mrv_wb_meas_conf;
517+ /* HW automatic configuration */
518+ struct ci_isp_wb_auto_hw_config mrv_wb_auto_hw_conf;
519+ /*
520+ * gain values
521+ * xiaolin, tsMrvWbGains mrv_wb_gains;
522+ * measurement limits
523+ */
524+ struct ci_isp_wb_meas_conf_limit mrv_wb_meas_conf_limit;
525+ /* Pca Damping for awb auto mode */
526+ u8 awb_pca_damping;
527+ /* PriorExp Damping for awb auto mode */
528+ u8 awb_prior_exp_damping;
529+ /* Pca Damping for AWB auto push mode */
530+ u8 awb_pca_push_damping;
531+ /* PriorExp Damping for AWB auto push mode */
532+ u8 awb_prior_exp_push_damping;
533+ /* Max Y in AWB auto mode */
534+ u8 awb_auto_max_y;
535+ /* Max Y in AWB auto push mode */
536+ u8 awb_push_max_y;
537+ /* Max Y in AWB measurement only mode */
538+ u8 awb_measure_max_y;
539+ /* Distance for underexposure detecture */
540+ u16 awb_underexp_det;
541+ /* Distance for underexposure push detecture */
542+ u16 awb_push_underexp_det;
543+
544+};
545+
546+/* possible AEC modes */
547+enum ci_isp_aec_mode {
548+ /* AEC turned off */
549+ CI_ISP_AEC_OFF,
550+ /* AEC measurements based on (almost) the entire picture */
551+ CI_ISP_AEC_INTEGRAL,
552+ /*
553+ * AEC measurements based on a single little square in the center of
554+ * the picture
555+ */
556+ CI_ISP_AEC_SPOT,
557+ /*
558+ * AEC measurements based on 5 little squares spread over the picture
559+ */
560+ CI_ISP_AEC_MFIELD5,
561+ /*
562+ * AEC measurements based on 9 little squares spread over the picture
563+ */
564+ CI_ISP_AEC_MFIELD9
565+};
566+
567+
568+/*
569+ * histogram weight 5x5 matrix coefficients
570+* (possible values are 1=0x10,15/16=0x0F,14/16,...,1/16,0)
571+*/
572+struct ci_isp_hist_matrix {
573+ u8 weight_00; u8 weight_10; u8 weight_20; u8 weight_30; u8 weight_40;
574+ u8 weight_01; u8 weight_11; u8 weight_21; u8 weight_31; u8 weight_41;
575+ u8 weight_02; u8 weight_12; u8 weight_22; u8 weight_32; u8 weight_42;
576+ u8 weight_03; u8 weight_13; u8 weight_23; u8 weight_33; u8 weight_43;
577+ u8 weight_04; u8 weight_14; u8 weight_24; u8 weight_34; u8 weight_44;
578+};
579+
580+/* autoexposure config */
581+struct ci_isp_aec_config {
582+ /*
583+ * Size of 1 window of MARVIN's 5x5 mean luminance
584+ * measurement grid and offset of grid
585+ */
586+ struct ci_isp_window isp_aecmean_lumaWindow;
587+ /* Size and offset of histogram window */
588+ struct ci_isp_window isp_aechist_calcWindow;
589+ /* Weight martix of histogram */
590+ struct ci_isp_hist_matrix isp_aechist_calcWeight;
591+ /* possible AEC modes */
592+ enum ci_isp_aec_mode advanced_aec_mode;
593+};
594+
595+/* autoexposure mean values */
596+struct ci_isp_aec_mean {
597+ u8 occ;
598+ u8 mean;
599+ u8 max;
600+ u8 min;
601+};
602+
603+
604+
605+/* histogram weight 5x5 matrix coefficients
606+ * (possible values are 1=0x10,15/16=0x0F,14/16,...,1/16,0)
607+ */
608+struct tsMrvHistMatrix {
609+ u8 weight_00; u8 weight_10; u8 weight_20; u8 weight_30; u8 weight_40;
610+ u8 weight_01; u8 weight_11; u8 weight_21; u8 weight_31; u8 weight_41;
611+ u8 weight_02; u8 weight_12; u8 weight_22; u8 weight_32; u8 weight_42;
612+ u8 weight_03; u8 weight_13; u8 weight_23; u8 weight_33; u8 weight_43;
613+ u8 weight_04; u8 weight_14; u8 weight_24; u8 weight_34; u8 weight_44;
614+};
615+
616+/*
617+ * vi_dpcl path selector, channel mode
618+ * Configuration of the Y/C splitter
619+ */
620+enum ci_isp_ycs_chn_mode {
621+ /*
622+ * 8bit data/Y only output (depreciated, please use CI_ISP_YCS_MVRaw for
623+ * new implementations)
624+ */
625+ CI_ISP_YCS_Y,
626+ /* separated 8bit Y, C routed to both main and self path */
627+ CI_ISP_YCS_MV_SP,
628+ /*
629+ * separated 8bit Y, C routed to main path only (self path input
630+ * switched off)
631+ */
632+ CI_ISP_YCS_MV,
633+ /*
634+ * separated 8bit Y, C routed to self path only (main path input
635+ * switched off)
636+ */
637+ CI_ISP_YCS_SP,
638+ /*
639+ * raw camera data routed to main path (8 or 16 bits, depends on
640+ * marvin drivative)
641+ */
642+ CI_ISP_YCS_MVRaw,
643+ /* both main and self path input switched off */
644+ CI_ISP_YCS_OFF
645+};
646+
647+/* vi_dpcl path selector, main path cross-switch */
648+enum ci_isp_dp_switch {
649+ /* raw data mode */
650+ CI_ISP_DP_RAW,
651+ /* JPEG encoding mode */
652+ CI_ISP_DP_JPEG,
653+ /* main video path only */
654+ CI_ISP_DP_MV
655+};
656+
657+/* DMA-read mode selector */
658+enum ci_isp_dma_read_mode {
659+ /* DMA-read feature deactivated */
660+ CI_ISP_DMA_RD_OFF = 0,
661+ /* data from the DMA-read block feeds the self path */
662+ CI_ISP_DMA_RD_SELF_PATH = 1,
663+ /* data from the DMA-read block feeds the Superimpose block */
664+ CI_ISP_DMA_RD_SUPERIMPOSE = 2,
665+ /* data from the DMA-read block feeds the Image effects path */
666+ CI_ISP_DMA_RD_IE_PATH = 3,
667+ /* data from the DMA-read block feeds the JPEG encoder directly */
668+ CI_ISP_DMA_RD_JPG_ENC = 4
669+};
670+
671+/* ISP path selector */
672+enum ci_isp_path {
673+ /* Isp path is unknown or invalid */
674+ CI_ISP_PATH_UNKNOWN = 0,
675+ /* Raw data bypass */
676+ CI_ISP_PATH_RAW = 1,
677+ /* YCbCr path */
678+ CI_ISP_PATH_YCBCR = 2,
679+ /* Bayer RGB path */
680+ CI_ISP_PATH_BAYER = 3
681+};
682+
683+/* possible autofocus measurement modes */
684+enum ci_isp_afm_mode {
685+ /* no autofocus measurement */
686+ CI_ISP_AFM_OFF,
687+ /* use AF hardware to measure sharpness */
688+ CI_ISP_AFM_HW,
689+ /* use "Tenengrad" algorithm implemented in software */
690+ CI_ISP_AFM_SW_TENENGRAD,
691+ /*
692+ * use "Threshold Squared Gradient" algorithm implemented in software
693+ */
694+ CI_ISP_AFM_SW_TRESH_SQRT_GRAD,
695+ /*
696+ * use "Frequency selective weighted median" algorithm implemented in
697+ * software
698+ */
699+ CI_ISP_AFM_SW_FSWMEDIAN,
700+ /* use AF hardware and normalize with mean luminance */
701+ CI_ISP_AFM_HW_norm,
702+ /* use "Tenengrad" algorithm and normalize with mean luminance */
703+ CI_ISP_AFM_SW_TENENGRAD_norm,
704+ /*
705+ * use "Frequency selective weighted median" algorithm and normalize
706+ * with mean luminance
707+ */
708+ CI_ISP_AFM_SW_FSWMEDIAN_norm
709+};
710+
711+/* possible autofocus search strategy modes */
712+enum ci_isp_afss_mode {
713+ /* no focus searching */
714+ CI_ISP_AFSS_OFF,
715+ /* scan the full focus range to find the point of best focus */
716+ CI_ISP_AFSS_FULL_RANGE,
717+ /* use hillclimbing search */
718+ CI_ISP_AFSS_HILLCLIMBING,
719+ /*
720+ * similar to full range search, but with multiple subsequent scans
721+ * with
722+ */
723+ CI_ISP_AFSS_ADAPTIVE_RANGE,
724+ /*
725+ * decreasing range and step size will be performed. search strategy
726+ * suggested by OneLimited for their Helimorph actuator
727+ */
728+ CI_ISP_AFSS_HELIMORPH_OPT,
729+ /*
730+ * search strategy optimized for omnivision 2630 module equipped with
731+ */
732+ CI_ISP_AFSS_OV2630_LPD4_OPT
733+ /*
734+ * autofocus lend driven through a LPD4 stepper motor produced by
735+ * Nidec Copal USA Corp. of Torrance, CA.
736+ */
737+};
738+
739+/* possible bad pixel correction type */
740+enum ci_isp_bp_corr_type {
741+ /* correction of bad pixel from the table */
742+ CI_ISP_BP_CORR_TABLE,
743+ /* direct detection and correction */
744+ CI_ISP_BP_CORR_DIRECT
745+};
746+
747+/* possible bad pixel replace approach */
748+enum ci_isp_bp_corr_rep {
749+ /* nearest neighbour approach */
750+ CI_ISP_BP_CORR_REP_NB,
751+ /* simple bilinear interpolation approach */
752+ CI_ISP_BP_CORR_REP_LIN
753+};
754+
755+/* possible bad pixel correction mode */
756+enum ci_isp_bp_corr_mode {
757+ /* hot pixel correction */
758+ CI_ISP_BP_CORR_HOT_EN,
759+ /* dead pixel correction */
760+ CI_ISP_BP_CORR_DEAD_EN,
761+ /* hot and dead pixel correction */
762+ CI_ISP_BP_CORR_HOT_DEAD_EN
763+};
764+
765+/* Gamma out curve (independent from the sensor characteristic). */
766+#define CI_ISP_GAMMA_OUT_CURVE_ARR_SIZE (17)
767+
768+struct ci_isp_gamma_out_curve {
769+ u16 isp_gamma_y[CI_ISP_GAMMA_OUT_CURVE_ARR_SIZE];
770+ u8 gamma_segmentation;
771+};
772+
773+/* configuration of autofocus measurement block */
774+struct ci_isp_af_config {
775+ /* position and size of measurement window A */
776+ struct ci_isp_window wnd_pos_a;
777+ /* position and size of measurement window B */
778+ struct ci_isp_window wnd_pos_b;
779+ /* position and size of measurement window C */
780+ struct ci_isp_window wnd_pos_c;
781+ /* AF measurment threshold */
782+ u32 threshold;
783+ /* measurement variable shift (before sum operation) */
784+ u32 var_shift;
785+};
786+
787+/* measurement results of autofocus measurement block */
788+struct ci_isp_af_meas {
789+ /* sharpness value of window A */
790+ u32 afm_sum_a;
791+ /* sharpness value of window B */
792+ u32 afm_sum_b;
793+ /* sharpness value of window C */
794+ u32 afm_sum_c;
795+ /* luminance value of window A */
796+ u32 afm_lum_a;
797+ /* luminance value of window B */
798+ u32 afm_lum_b;
799+ /* luminance value of window C */
800+ u32 afm_lum_c;
801+};
802+
803+/* configuration for correction of bad pixel block */
804+struct ci_isp_bp_corr_config {
805+ /* bad pixel correction type */
806+ enum ci_isp_bp_corr_type bp_corr_type;
807+ /* replace approach */
808+ enum ci_isp_bp_corr_rep bp_corr_rep;
809+ /* bad pixel correction mode */
810+ enum ci_isp_bp_corr_mode bp_corr_mode;
811+ /* Absolute hot pixel threshold */
812+ u16 bp_abs_hot_thres;
813+ /* Absolute dead pixel threshold */
814+ u16 bp_abs_dead_thres;
815+ /* Hot Pixel deviation Threshold */
816+ u16 bp_dev_hot_thres;
817+ /* Dead Pixel deviation Threshold */
818+ u16 bp_dev_dead_thres;
819+};
820+
821+/* configuration for correction of lens shading */
822+struct ci_isp_ls_corr_config {
823+ /* correction values of R color part */
824+ u16 ls_rdata_tbl[CI_ISP_DATA_TBL_SIZE];
825+ /* correction values of G color part */
826+ u16 ls_gdata_tbl[CI_ISP_DATA_TBL_SIZE];
827+ /* correction values of B color part */
828+ u16 ls_bdata_tbl[CI_ISP_DATA_TBL_SIZE];
829+ /* multiplication factors of x direction */
830+ u16 ls_xgrad_tbl[CI_ISP_GRAD_TBL_SIZE];
831+ /* multiplication factors of y direction */
832+ u16 ls_ygrad_tbl[CI_ISP_GRAD_TBL_SIZE];
833+ /* sector sizes of x direction */
834+ u16 ls_xsize_tbl[CI_ISP_GRAD_TBL_SIZE];
835+ /* sector sizes of y direction */
836+ u16 ls_ysize_tbl[CI_ISP_GRAD_TBL_SIZE];
837+
838+};
839+
840+/* configuration for detection of bad pixel block */
841+struct ci_isp_bp_det_config {
842+ /* abs_dead_thres Absolute dead pixel threshold */
843+ u32 bp_dead_thres;
844+};
845+
846+/* new table element */
847+struct ci_isp_bp_new_table_elem {
848+ /* Bad Pixel vertical address */
849+ u16 bp_ver_addr;
850+ /* Bad Pixel horizontal address */
851+ u16 bp_hor_addr;
852+ /* MSB value of fixed pixel (deceide if dead or hot) */
853+ u8 bp_msb_value;
854+};
855+
856+/* new Bad Pixel table */
857+struct ci_isp_bp_new_table {
858+ /* Number of possible new detected bad pixel */
859+ u32 bp_number;
860+ /* Array of Table element */
861+ struct ci_isp_bp_new_table_elem bp_new_table_elem[8];
862+};
863+
864+/* image effect modes */
865+enum ci_isp_ie_mode {
866+ /* no image effect (bypass) */
867+ CI_ISP_IE_MODE_OFF,
868+ /* Set a fixed chrominance of 128 (neutral grey) */
869+ CI_ISP_IE_MODE_GRAYSCALE,
870+ /* Luminance and chrominance data is being inverted */
871+ CI_ISP_IE_MODE_NEGATIVE,
872+ /*
873+ * Chrominance is changed to produce a historical like brownish image
874+ * color
875+ */
876+ CI_ISP_IE_MODE_SEPIA,
877+ /*
878+ * Converting picture to grayscale while maintaining one color
879+ * component.
880+ */
881+ CI_ISP_IE_MODE_COLOR_SEL,
882+ /* Edge detection, will look like an relief made of metal */
883+ CI_ISP_IE_MODE_EMBOSS,
884+ /* Edge detection, will look like a pencil drawing */
885+ CI_ISP_IE_MODE_SKETCH
886+};
887+
888+/* image effect color selection */
889+enum ci_isp_ie_color_sel {
890+ /* in CI_ISP_IE_MODE_COLOR_SEL mode, maintain the red color */
891+ CI_ISP_IE_MAINTAIN_RED = 0x04,
892+ /* in CI_ISP_IE_MODE_COLOR_SEL mode, maintain the green color */
893+ CI_ISP_IE_MAINTAIN_GREEN = 0x02,
894+ /* in CI_ISP_IE_MODE_COLOR_SEL mode, maintain the blue color */
895+ CI_ISP_IE_MAINTAIN_BLUE = 0x01
896+};
897+
898+/*
899+ * image effect 3x3 matrix coefficients (possible values are -8, -4, -2, -1,
900+ * 0, 1, 2, 4, 8)
901+ */
902+struct ci_isp_ie_matrix {
903+ s8 coeff_11;
904+ s8 coeff_12;
905+ s8 coeff_13;
906+ s8 coeff_21;
907+ s8 coeff_22;
908+ s8 coeff_23;
909+ s8 coeff_31;
910+ s8 coeff_32;
911+ s8 coeff_33;
912+};
913+
914+/* image effect configuration struct */
915+struct ci_isp_ie_config {
916+ /* image effect mode */
917+ enum ci_isp_ie_mode mode;
918+ u8 color_sel;
919+ /* threshold for color selection */
920+ u8 color_thres;
921+ /* Cb chroma component of 'tint' color for sepia effect */
922+ u8 tint_cb;
923+ /* Cr chroma component of 'tint' color for sepia effect */
924+ u8 tint_cr;
925+ /* coefficient maxrix for emboss effect */
926+ struct ci_isp_ie_matrix mat_emboss;
927+ /* coefficient maxrix for sketch effect */
928+ struct ci_isp_ie_matrix mat_sketch;
929+};
930+
931+/* super impose transparency modes */
932+enum ci_isp_si_trans_mode {
933+ /* SI transparency mode is unknown (module is switched off) */
934+ CI_ISP_SI_TRANS_UNKNOWN = 0,
935+ /* SI transparency mode enabled */
936+ CI_ISP_SI_TRANS_ENABLE = 1,
937+ /* SI transparency mode disabled */
938+ CI_ISP_SI_TRANS_DISABLE = 2
939+};
940+
941+/* super impose reference image */
942+enum ci_isp_si_ref_image {
943+ /* SI reference image is unknown (module is switched off) */
944+ CI_ISP_SI_REF_IMG_UNKNOWN = 0,
945+ /* SI reference image from sensor */
946+ CI_ISP_SI_REF_IMG_SENSOR = 1,
947+ /* SI reference image from memory */
948+ CI_ISP_SI_REF_IMG_MEMORY = 2
949+};
950+
951+/* super impose configuration struct */
952+struct ci_isp_si_config {
953+ /* transparency mode on/off */
954+ enum ci_isp_si_trans_mode trans_mode;
955+ /* reference image from sensor/memory */
956+ enum ci_isp_si_ref_image ref_image;
957+ /* x offset (coordinate system of the reference image) */
958+ u16 offs_x;
959+ /* y offset (coordinate system of the reference image) */
960+ u16 offs_y;
961+ /* Y component of transparent key color */
962+ u8 trans_comp_y;
963+ /* Cb component of transparent key color */
964+ u8 trans_comp_cb;
965+ /* Cr component of transparent key color */
966+ u8 trans_comp_cr;
967+};
968+
969+/* image stabilisation modes */
970+enum ci_isp_is_mode {
971+ /* IS mode is unknown (module is switched off) */
972+ CI_ISP_IS_MODE_UNKNOWN = 0,
973+ /* IS mode enabled */
974+ CI_ISP_IS_MODE_ON = 1,
975+ /* IS mode disabled */
976+ CI_ISP_IS_MODE_OFF = 2
977+};
978+
979+/* image stabilisation configuration struct */
980+struct ci_isp_is_config {
981+ /* position and size of image stabilisation window */
982+ struct ci_isp_window mrv_is_window;
983+ /* maximal margin distance for X */
984+ u16 max_dx;
985+ /* maximal margin distance for Y */
986+ u16 max_dy;
987+};
988+
989+/* image stabilisation control struct */
990+struct ci_isp_is_ctrl {
991+ /* image stabilisation mode on/off */
992+ enum ci_isp_is_mode is_mode;
993+ /* recenter every frame by ((cur_v_offsxV_OFFS)/(2^RECENTER)) */
994+ u8 recenter;
995+};
996+
997+/* for data path switching */
998+enum ci_isp_data_path {
999+ CI_ISP_PATH_RAW816,
1000+ CI_ISP_PATH_RAW8,
1001+ CI_ISP_PATH_JPE,
1002+ CI_ISP_PATH_OFF,
1003+ CI_ISP_PATH_ON
1004+};
1005+
1006+/* buffer for memory interface */
1007+struct ci_isp_bufferOld {
1008+ u8 *pucbuffer;
1009+ u32 size;
1010+ u32 offs;
1011+ /* not used for Cb and Cr buffers, IRQ offset for */
1012+ u32 irq_offs_llength;
1013+ /* stores the malloc pointer address */
1014+ u8 *pucmalloc_start;
1015+ /* main buffer and line length for self buffer */
1016+};
1017+
1018+/* buffer for DMA memory interface */
1019+struct ci_isp_dma_buffer {
1020+ /*
1021+ * start of the buffer memory. Note that panning in an larger picture
1022+ * memory is possible by altering the buffer start address (and
1023+ * choosing pic_width llength)
1024+ */
1025+ u8 *pucbuffer;
1026+ /* size of the entire picture in bytes */
1027+ u32 pic_size;
1028+ /*
1029+ * width of the picture area of interest (not necessaryly the entire
1030+ * picture)
1031+ */
1032+ u32 pic_width;
1033+ /* inter-line-increment. This is the amount of bytes between */
1034+ u32 llength;
1035+ /* pixels in the same column but on different lines. */
1036+
1037+};
1038+
1039+/* color format for self picture input/output and DMA input */
1040+enum ci_isp_mif_col_format {
1041+ /* YCbCr 4:2:2 format */
1042+ CI_ISP_MIF_COL_FORMAT_YCBCR_422 = 0,
1043+ /* YCbCr 4:4:4 format */
1044+ CI_ISP_MIF_COL_FORMAT_YCBCR_444 = 1,
1045+ /* YCbCr 4:2:0 format */
1046+ CI_ISP_MIF_COL_FORMAT_YCBCR_420 = 2,
1047+ /* YCbCr 4:0:0 format */
1048+ CI_ISP_MIF_COL_FORMAT_YCBCR_400 = 3,
1049+ /* RGB 565 format */
1050+ CI_ISP_MIF_COL_FORMAT_RGB_565 = 4,
1051+ /* RGB 666 format */
1052+ CI_ISP_MIF_COL_FORMAT_RGB_666 = 5,
1053+ /* RGB 888 format */
1054+ CI_ISP_MIF_COL_FORMAT_RGB_888 = 6
1055+};
1056+
1057+/* color range for self picture input of RGB m*/
1058+enum ci_isp_mif_col_range {
1059+ mrv_mif_col_range_std = 0,
1060+ mrv_mif_col_range_full = 1
1061+};
1062+
1063+/* color phase for self picture input of RGB */
1064+enum ci_isp_mif_col_phase {
1065+ mrv_mif_col_phase_cosited = 0,
1066+ mrv_mif_col_phase_non_cosited = 1
1067+};
1068+
1069+/*
1070+ * picture write/read format
1071+ * The following examples apply to YCbCr 4:2:2 images, as all modes
1072+ */
1073+ enum ci_isp_mif_pic_form {
1074+ /* planar : separated buffers for Y, Cb and Cr */
1075+ CI_ISP_MIF_PIC_FORM_PLANAR = 0,
1076+ /* semi-planar: one buffer for Y and a combined buffer for Cb and Cr */
1077+ CI_ISP_MIF_PIC_FORM_SEMI_PLANAR = 1,
1078+ /* interleaved: one buffer for all */
1079+ CI_ISP_MIF_PIC_FORM_INTERLEAVED = 2
1080+};
1081+
1082+/* self picture operating modes */
1083+enum ci_isp_mif_sp_mode {
1084+ /* no rotation, no horizontal or vertical flipping */
1085+ CI_ISP_MIF_SP_ORIGINAL = 0,
1086+ /* vertical flipping (no additional rotation) */
1087+ CI_ISP_MIF_SP_VERTICAL_FLIP = 1,
1088+ /* horizontal flipping (no additional rotation) */
1089+ CI_ISP_MIF_SP_HORIZONTAL_FLIP = 2,
1090+ /* rotation 90 degrees ccw (no additional flipping) */
1091+ CI_ISP_MIF_SP_ROTATION_090_DEG = 3,
1092+ /*
1093+ * rotation 180 degrees ccw (equal to horizontal plus vertical
1094+ * flipping)
1095+ */
1096+ CI_ISP_MIF_SP_ROTATION_180_DEG = 4,
1097+ /* rotation 270 degrees ccw (no additional flipping) */
1098+ CI_ISP_MIF_SP_ROTATION_270_DEG = 5,
1099+ /* rotation 90 degrees ccw plus vertical flipping */
1100+ CI_ISP_MIF_SP_ROT_090_V_FLIP = 6,
1101+ /* rotation 270 degrees ccw plus vertical flipping */
1102+ CI_ISP_MIF_SP_ROT_270_V_FLIP = 7
1103+};
1104+
1105+/* MI burst length settings */
1106+enum ci_isp_mif_burst_length {
1107+ /* burst length = 4 */
1108+ CI_ISP_MIF_BURST_LENGTH_4 = 0,
1109+ /* burst length = 8 */
1110+ CI_ISP_MIF_BURST_LENGTH_8 = 1,
1111+ /* burst length = 16 */
1112+ CI_ISP_MIF_BURST_LENGTH_16 = 2
1113+};
1114+
1115+
1116+/* MI apply initial values settings */
1117+enum ci_isp_mif_init_vals {
1118+ /* do not set initial values */
1119+ CI_ISP_MIF_NO_INIT_VALS = 0,
1120+ /* set initial values for offset registers */
1121+ CI_ISP_MIF_INIT_OFFS = 1,
1122+ /* set initial values for base address registers */
1123+ CI_ISP_MIF_INIT_BASE = 2,
1124+ /* set initial values for offset and base address registers */
1125+ CI_ISP_MIF_INIT_OFFSAndBase = 3
1126+};
1127+
1128+/* MI when to update configuration */
1129+enum ci_isp_conf_update_time {
1130+ CI_ISP_CFG_UPDATE_FRAME_SYNC = 0,
1131+ CI_ISP_CFG_UPDATE_IMMEDIATE = 1,
1132+ CI_ISP_CFG_UPDATE_LATER = 2
1133+};
1134+
1135+/* control register of the MI */
1136+struct ci_isp_mi_ctrl {
1137+ /* self picture path output format */
1138+ enum ci_isp_mif_col_format mrv_mif_sp_out_form;
1139+ /* self picture path input format */
1140+ enum ci_isp_mif_col_format mrv_mif_sp_in_form;
1141+ enum ci_isp_mif_col_range mrv_mif_sp_in_range;
1142+ enum ci_isp_mif_col_phase mrv_mif_sp_in_phase;
1143+ /* self picture path write format */
1144+ enum ci_isp_mif_pic_form mrv_mif_sp_pic_form;
1145+ /* main picture path write format */
1146+ enum ci_isp_mif_pic_form mrv_mif_mp_pic_form;
1147+ /* burst length for chrominance for write port */
1148+ enum ci_isp_mif_burst_length burst_length_chrom;
1149+ /* burst length for luminance for write port */
1150+ enum ci_isp_mif_burst_length burst_length_lum;
1151+ /* enable updating of the shadow registers */
1152+ enum ci_isp_mif_init_vals init_vals;
1153+ /*
1154+ * for main and self picture to their init values
1155+ */
1156+ /* enable change of byte order for write port */
1157+ int byte_swap_enable;
1158+ /* enable the last pixel signalization */
1159+ int last_pixel_enable;
1160+ /* self picture path operating mode */
1161+ enum ci_isp_mif_sp_mode mrv_mif_sp_mode;
1162+ /* enable path */
1163+ enum ci_isp_data_path main_path;
1164+ /* enable path */
1165+ enum ci_isp_data_path self_path;
1166+ /*
1167+ * offset counter interrupt generation for fill_mp_y (counted in
1168+ * bytes)
1169+ */
1170+ u32 irq_offs_init;
1171+
1172+};
1173+
1174+/* buffer for memory interface */
1175+struct ci_isp_buffer {
1176+ /* buffer start address */
1177+ u8 *pucbuffer;
1178+ /* buffer size (counted in bytes) */
1179+ u32 size;
1180+ /* buffer offset count (counted in bytes) */
1181+ u32 offs;
1182+};
1183+
1184+/* main or self picture path, or DMA configuration */
1185+struct ci_isp_mi_path_conf {
1186+ /* Y picture width (counted in pixels) */
1187+ u32 ypic_width;
1188+ /* Y picture height (counted in pixels) */
1189+ u32 ypic_height;
1190+ /*
1191+ * line length means the distance from one pixel to the vertically
1192+ * next
1193+ */
1194+ u32 llength;
1195+ /*
1196+ * pixel below including the not-used blanking area, etc.
1197+ * (counted in pixels)
1198+ */
1199+ /* Y buffer structure */
1200+ struct ci_isp_buffer ybuffer;
1201+ /* Cb buffer structure */
1202+ struct ci_isp_buffer cb_buffer;
1203+ /* Cr buffer structure */
1204+ struct ci_isp_buffer cr_buffer;
1205+};
1206+
1207+/* DMA configuration */
1208+struct ci_isp_mi_dma_conf {
1209+ /* start DMA immediately after configuration */
1210+ int start_dma;
1211+ /* suppress v_end so that no frame end can be */
1212+ int frame_end_disable;
1213+ /*
1214+ * detected by the following instances
1215+ * enable change of byte order for read port
1216+ */
1217+ int byte_swap_enable;
1218+ /*
1219+ * Enables continuous mode. If set the same frame is read back
1220+ * over and over. A start pulse on dma_start is need only for the
1221+ * first time. To stop continuous mode reset this bit (takes
1222+ * effect after the next frame end) or execute a soft reset.
1223+ */
1224+ int continuous_enable;
1225+ /* DMA input color format */
1226+ enum ci_isp_mif_col_format mrv_mif_col_format;
1227+ /* DMA read buffer format */
1228+ enum ci_isp_mif_pic_form mrv_mif_pic_form;
1229+ /* burst length for chrominance for read port */
1230+ enum ci_isp_mif_burst_length burst_length_chrom;
1231+ /* burst length for luminance for read port */
1232+ enum ci_isp_mif_burst_length burst_length_lum;
1233+ /*
1234+ * Set this to TRUE if the DMA-read data is routed through
1235+ * the path that is normally used for the live camera
1236+ * data (e.g. through the image effects module).
1237+ */
1238+ int via_cam_path;
1239+};
1240+
1241+/* Public CAC Defines and Typedefs */
1242+
1243+/*
1244+ * configuration of chromatic aberration correction block (given to the
1245+ * CAC driver)
1246+ */
1247+struct ci_isp_cac_config {
1248+ /* size of the input image in pixels */
1249+ u16 hsize;
1250+ u16 vsize;
1251+ /* offset between image center and optical */
1252+ s16 hcenter_offset;
1253+ /* center of the input image in pixels */
1254+ s16 vcenter_offset;
1255+ /* maximum red/blue pixel shift in horizontal */
1256+ u8 hclip_mode;
1257+ /* and vertival direction, range 0..2 */
1258+ u8 vclip_mode;
1259+ /* parameters for radial shift calculation, */
1260+ u16 ablue;
1261+ /* 9 bit twos complement with 4 fractional */
1262+ u16 ared;
1263+ /* digits, valid range -16..15.9375 */
1264+ u16 bblue;
1265+ u16 bred;
1266+ u16 cblue;
1267+ u16 cred;
1268+ /* 0 = square pixel sensor, all other = aspect */
1269+ float aspect_ratio;
1270+ /* ratio of non-square pixel sensor */
1271+
1272+};
1273+
1274+/*
1275+ * register values of chromatic aberration correction block (delivered by
1276+ * the CAC driver)
1277+ */
1278+struct ci_isp_cac_reg_values {
1279+ /* maximum red/blue pixel shift in horizontal */
1280+ u8 hclip_mode;
1281+ /* and vertival direction, range 0..2 */
1282+ u8 vclip_mode;
1283+ /* TRUE=enabled, FALSE=disabled */
1284+ int cac_enabled;
1285+ /*
1286+ * preload value of the horizontal CAC pixel
1287+ * counter, range 1..4095
1288+ */
1289+ u16 hcount_start;
1290+ /*
1291+ * preload value of the vertical CAC pixel
1292+ * counter, range 1..4095
1293+ */
1294+ u16 vcount_start;
1295+ /* parameters for radial shift calculation, */
1296+ u16 ablue;
1297+ /* 9 bit twos complement with 4 fractional */
1298+ u16 ared;
1299+ /* digits, valid range -16..15.9375 */
1300+ u16 bblue;
1301+ u16 bred;
1302+ u16 cblue;
1303+ u16 cred;
1304+ /* horizontal normalization shift, range 0..7 */
1305+ u8 xnorm_shift;
1306+ /* horizontal normalization factor, range 16..31 */
1307+ u8 xnorm_factor;
1308+ /* vertical normalization shift, range 0..7 */
1309+ u8 ynorm_shift;
1310+ /* vertical normalization factor, range 16..31 */
1311+ u8 ynorm_factor;
1312+};
1313+
1314+struct ci_snapshot_config {
1315+ /* snapshot flags */
1316+ u32 flags;
1317+ /* user zoom factor to use ( Zoomfactor = 1 + (<value>*1024) ) */
1318+ int user_zoom;
1319+ /* user width (in pixel) */
1320+ int user_w;
1321+ /* user height (in pixel) */
1322+ int user_h;
1323+ /* compression ratio for JPEG snapshots */
1324+ u8 compression_ratio;
1325+};
1326+
1327+struct ci_isp_view_finder_config {
1328+ /* how to display the viewfinder */
1329+ u32 flags;
1330+ /* zoom factor to use ( Zoomfactor = 1 + (<value>*1024) ) */
1331+ int zoom;
1332+ /* contrast setting for LCD */
1333+ int lcd_contrast;
1334+ /* following settings are only used in VFFLAG_MODE_USER mode */
1335+
1336+ /* start pixel of upper left corner on LCD */
1337+ int x;
1338+ /* start pixel of upper left corner on LCD */
1339+ int y;
1340+ /* width (in pixel) */
1341+ int w;
1342+ /* height (in pixel) */
1343+ int h;
1344+ /* keeps the aspect ratio by cropping the input to match the output
1345+ * aspect ratio. */
1346+ int keep_aspect;
1347+};
1348+
1349+/* ! Number of supported DIP-Switches */
1350+#define FF_DIPSWITCH_COUNT 10
1351+
1352+
1353+#define CI_ISP_HIST_DATA_BIN_ARR_SIZE 16
1354+
1355+struct ci_isp_hist_data_bin {
1356+ u8 hist_bin[CI_ISP_HIST_DATA_BIN_ARR_SIZE];
1357+};
1358+
1359+#define MRV_MEAN_LUMA_ARR_SIZE_COL 5
1360+#define MRV_MEAN_LUMA_ARR_SIZE_ROW 5
1361+#define MRV_MEAN_LUMA_ARR_SIZE \
1362+ (MRV_MEAN_LUMA_ARR_SIZE_COL*MRV_MEAN_LUMA_ARR_SIZE_ROW)
1363+
1364+/* Structure contains a 2-dim 5x5 array
1365+ * for mean luminance values from 5x5 MARVIN measurement grid.
1366+ */
1367+struct ci_isp_mean_luma {
1368+ u8 mean_luma_block[MRV_MEAN_LUMA_ARR_SIZE_COL][MRV_MEAN_LUMA_ARR_SIZE_ROW];
1369+};
1370+
1371+/* Structure contains bits autostop and exp_meas_mode of isp_exp_ctrl */
1372+struct ci_isp_exp_ctrl {
1373+ int auto_stop;
1374+ int exp_meas_mode;
1375+ int exp_start;
1376+} ;
1377+
1378+
1379+struct ci_isp_cfg_flags {
1380+ /*
1381+ * following flag tripels controls the behaviour of the associated
1382+ * marvin control loops.
1383+ * For feature XXX, the 3 flags are totally independant and
1384+ * have the following meaning:
1385+ * fXXX:
1386+ * If set, there is any kind of software interaction during runtime
1387+ * thatmay lead to a modification of the feature-dependant settings.
1388+ * For each frame, a feature specific loop control routine is called
1389+ * may perform other actions based on feature specific configuration.
1390+ * If not set, only base settings will be applied during setup, or the
1391+ * reset values are left unchanged. No control routine will be called
1392+ * inside the processing loop.
1393+ * fXXXprint:
1394+ * If set, some status informations will be printed out inside
1395+ * the processing loop. Status printing is independant of the
1396+ * other flags regarding this feature.
1397+ * fXXX_dis:
1398+ * If set, the feature dependant submodule of the marvin is
1399+ * disabled or is turned into bypass mode. Note that it is
1400+ * still possible to set one or more of the other flags too,
1401+ * but this wouldn't make much sense...
1402+ * lens shading correction
1403+ */
1404+
1405+ unsigned int lsc:1;
1406+ unsigned int lscprint:1;
1407+ unsigned int lsc_dis:1;
1408+
1409+ /* bad pixel correction */
1410+
1411+ unsigned int bpc:1;
1412+ unsigned int bpcprint:1;
1413+ unsigned int bpc_dis:1;
1414+
1415+ /* black level correction */
1416+
1417+ unsigned int bls:1;
1418+ /* only fixed values */
1419+ unsigned int bls_man:1;
1420+ /* fixed value read from smia interface */
1421+ unsigned int bls_smia:1;
1422+ unsigned int blsprint:1;
1423+ unsigned int bls_dis:1;
1424+
1425+ /* (automatic) white balancing
1426+ * (if automatic or manual can be configured elsewhere) */
1427+
1428+ unsigned int awb:1;
1429+ unsigned int awbprint:1;
1430+ unsigned int awbprint2:1;
1431+ unsigned int awb_dis:1;
1432+
1433+ /* automatic exposure (and gain) control */
1434+
1435+ unsigned int aec:1;
1436+ unsigned int aecprint:1;
1437+ unsigned int aec_dis:1;
1438+ unsigned int aec_sceval:1;
1439+
1440+ /* auto focus */
1441+
1442+ unsigned int af:1;
1443+ unsigned int afprint:1;
1444+ unsigned int af_dis:1;
1445+
1446+ /* enable flags for various other components of the marvin */
1447+
1448+ /* color processing (brightness, contrast, saturation, hue) */
1449+ unsigned int cp:1;
1450+ /* input gamma block */
1451+ unsigned int gamma:1;
1452+ /* color conversion matrix */
1453+ unsigned int cconv:1;
1454+ /* demosaicing */
1455+ unsigned int demosaic:1;
1456+ /* output gamma block */
1457+ unsigned int gamma2:1;
1458+ /* Isp de-noise and sharpenize filters */
1459+ unsigned int isp_filters:1;
1460+ /* Isp CAC */
1461+ unsigned int cac:1;
1462+
1463+ /* demo stuff */
1464+
1465+ /* demo: saturation loop enable */
1466+ unsigned int cp_sat_loop:1;
1467+ /* demo: contrast loop enable */
1468+ unsigned int cp_contr_loop:1;
1469+ /* demo: brightness loop enable */
1470+ unsigned int cp_bright_loop:1;
1471+ /* demo: scaler loop enable */
1472+ unsigned int scaler_loop:1;
1473+ /* demo: use standard color conversion matrix */
1474+ unsigned int cconv_basic:1;
1475+
1476+ /* demo: use joystick to cycle through the image effect modes */
1477+ unsigned int cycle_ie_mode:1;
1478+
1479+ /* others */
1480+
1481+ /* enable continous autofocus */
1482+ unsigned int continous_af:1;
1483+
1484+ unsigned int bad_pixel_generation:1;
1485+ /* enable YCbCr full range */
1486+ unsigned int ycbcr_full_range:1;
1487+ /* enable YCbCr color phase non cosited */
1488+ unsigned int ycbcr_non_cosited:1;
1489+
1490+};
1491+
1492+struct ci_isp_config {
1493+ struct ci_isp_cfg_flags flags;
1494+ struct ci_sensor_ls_corr_config lsc_cfg;
1495+ struct ci_isp_bp_corr_config bpc_cfg;
1496+ struct ci_isp_bp_det_config bpd_cfg;
1497+ struct ci_isp_wb_config wb_config;
1498+ struct ci_isp_cac_config cac_config;
1499+ struct ci_isp_aec_config aec_cfg;
1500+ struct ci_isp_window aec_v2_wnd;
1501+ struct ci_isp_bls_config bls_cfg;
1502+ struct ci_isp_af_config af_cfg;
1503+ struct ci_isp_color_settings color;
1504+ struct ci_isp_ie_config img_eff_cfg;
1505+ enum ci_isp_demosaic_mode demosaic_mode;
1506+ u8 demosaic_th;
1507+ u8 exposure;
1508+ enum ci_isp_aec_mode advanced_aec_mode;
1509+ /* what to include in reports; */
1510+ u32 report_details;
1511+ /* an or'ed combination of the FF_REPORT_xxx defines */
1512+ struct ci_isp_view_finder_config view_finder;
1513+ /* primary snapshot */
1514+ struct ci_snapshot_config snapshot_a;
1515+ /* secondary snapshot */
1516+ struct ci_snapshot_config snapshot_b;
1517+ /* auto focus measurement mode */
1518+ enum ci_isp_afm_mode afm_mode;
1519+ /* auto focus search strategy mode */
1520+ enum ci_isp_afss_mode afss_mode;
1521+ int wb_get_gains_from_sensor_driver;
1522+ u8 filter_level_noise_reduc;
1523+ u8 filter_level_sharp;
1524+ u8 jpeg_enc_ratio;
1525+};
1526+
1527+struct ci_isp_mem_info {
1528+ u32 isp_bar0_pa;
1529+ u32 isp_bar0_size;
1530+ u32 isp_bar1_pa;
1531+ u32 isp_bar1_size;
1532+};
1533+
1534+struct ci_pl_system_config {
1535+ /* to be removed */
1536+ struct ci_sensor_config *isi_config;
1537+ struct ci_sensor_caps *isi_caps;
1538+ struct ci_sensor_awb_profile *sensor_awb_profile;
1539+
1540+ struct ci_isp_config isp_cfg;
1541+ u32 focus_max;
1542+ unsigned int isp_hal_enable;
1543+ struct v4l2_jpg_review_buffer jpg_review;
1544+ int jpg_review_enable;
1545+};
1546+
1547+/* intel private ioctl code for ci isp hal interface */
1548+#define BASE BASE_VIDIOC_PRIVATE
1549+
1550+#define VIDIOC_SET_SYS_CFG _IOWR('V', BASE + 1, struct ci_pl_system_config)
1551+#define VIDIOC_SET_JPG_ENC_RATIO _IOWR('V', BASE + 2, int)
1552+#define VIDIOC_GET_ISP_MEM_INFO _IOWR('V', BASE + 4, struct ci_isp_mem_info)
1553+
1554+#include "ci_va.h"
1555+
1556+/* support camera flash on CDK */
1557+struct ci_isp_flash_cmd {
1558+ int preflash_on;
1559+ int flash_on;
1560+ int prelight_on;
1561+};
1562+
1563+struct ci_isp_flash_config {
1564+ int prelight_off_at_end_of_flash;
1565+ int vsync_edge_positive;
1566+ int output_polarity_low_active;
1567+ int use_external_trigger;
1568+ u8 capture_delay;
1569+};
1570+
1571+#endif
1572--- /dev/null
1573+++ b/drivers/media/video/mrstci/include/ci_isp_fmts_common.h
1574@@ -0,0 +1,128 @@
1575+/*
1576+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
1577+ *
1578+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
1579+ *
1580+ * This program is free software; you can redistribute it and/or
1581+ * modify it under the terms of the GNU General Public License version
1582+ * 2 as published by the Free Software Foundation.
1583+ *
1584+ * This program is distributed in the hope that it will be useful,
1585+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1586+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1587+ * GNU General Public License for more details.
1588+ *
1589+ * You should have received a copy of the GNU General Public License
1590+ * along with this program; if not, write to the Free Software
1591+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
1592+ * 02110-1301, USA.
1593+ *
1594+ *
1595+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
1596+ */
1597+
1598+#ifndef _ISP_FMTS_COMMON_H
1599+#define _ISP_FMTS_COMMON_H
1600+
1601+#define intel_fourcc(d, c, b, a) \
1602+ (((__u32)(d)<<0)|((__u32)(c)<<8)|((__u32)(b)<<16)|((__u32)(a)<<24))
1603+
1604+/* more bayer pattern formats support by ISP */
1605+
1606+/* RAW 8-bit */
1607+#define INTEL_PIX_FMT_RAW08 intel_fourcc('R', 'W', '0', '8')
1608+/* RAW 10-bit */
1609+#define INTEL_PIX_FMT_RAW10 intel_fourcc('R', 'W', '1', '0')
1610+/* RAW 12-bit */
1611+#define INTEL_PIX_FMT_RAW12 intel_fourcc('R', 'W', '1', '2')
1612+
1613+
1614+/*
1615+ * various config and info structs concentrated into one struct
1616+ * for simplification
1617+ */
1618+#define FORMAT_FLAGS_DITHER 0x01
1619+#define FORMAT_FLAGS_PACKED 0x02
1620+#define FORMAT_FLAGS_PLANAR 0x04
1621+#define FORMAT_FLAGS_RAW 0x08
1622+#define FORMAT_FLAGS_CrCb 0x10
1623+
1624+struct intel_fmt {
1625+ char *name;
1626+ unsigned long fourcc; /* v4l2 format id */
1627+ int depth;
1628+ int flags;
1629+};
1630+
1631+static struct intel_fmt fmts[] = {
1632+ {
1633+ .name = "565 bpp RGB",
1634+ .fourcc = V4L2_PIX_FMT_RGB565,
1635+ .depth = 16,
1636+ .flags = FORMAT_FLAGS_PACKED,
1637+ },
1638+ {
1639+ .name = "888 bpp BGR",
1640+ .fourcc = V4L2_PIX_FMT_BGR32,
1641+ .depth = 32,
1642+ .flags = FORMAT_FLAGS_PLANAR,
1643+ },
1644+ {
1645+ .name = "4:2:2, packed, YUYV",
1646+ .fourcc = V4L2_PIX_FMT_YUYV,
1647+ .depth = 16,
1648+ .flags = FORMAT_FLAGS_PACKED,
1649+ },
1650+ {
1651+ .name = "4:2:2 planar, YUV422P",
1652+ .fourcc = V4L2_PIX_FMT_YUV422P,
1653+ .depth = 16,
1654+ .flags = FORMAT_FLAGS_PLANAR,
1655+ },
1656+ {
1657+ .name = "4:2:0 planar, YUV420",
1658+ .fourcc = V4L2_PIX_FMT_YUV420,
1659+ .depth = 12,
1660+ .flags = FORMAT_FLAGS_PLANAR,
1661+ },
1662+ {
1663+ .name = "4:2:0 planar, YVU420",
1664+ .fourcc = V4L2_PIX_FMT_YVU420,
1665+ .depth = 12,
1666+ .flags = FORMAT_FLAGS_PLANAR,
1667+ },
1668+ {
1669+ .name = "4:2:0 semi planar, NV12",
1670+ .fourcc = V4L2_PIX_FMT_NV12,
1671+ .depth = 12,
1672+ .flags = FORMAT_FLAGS_PLANAR,
1673+ },
1674+ {
1675+ .name = "Compressed format, JPEG",
1676+ .fourcc = V4L2_PIX_FMT_JPEG,
1677+ .depth = 12,
1678+ .flags = FORMAT_FLAGS_PLANAR,
1679+ },
1680+ {
1681+ .name = "Sequential RGB",
1682+ .fourcc = INTEL_PIX_FMT_RAW08,
1683+ .depth = 8,
1684+ .flags = FORMAT_FLAGS_RAW,
1685+ },
1686+ {
1687+ .name = "Sequential RGB",
1688+ .fourcc = INTEL_PIX_FMT_RAW10,
1689+ .depth = 16,
1690+ .flags = FORMAT_FLAGS_RAW,
1691+ },
1692+ {
1693+ .name = "Sequential RGB",
1694+ .fourcc = INTEL_PIX_FMT_RAW12,
1695+ .depth = 16,
1696+ .flags = FORMAT_FLAGS_RAW,
1697+ },
1698+};
1699+
1700+static int NUM_FORMATS = sizeof(fmts) / sizeof(struct intel_fmt);
1701+#endif /* _ISP_FMTS_H */
1702+
1703--- /dev/null
1704+++ b/drivers/media/video/mrstci/include/ci_sensor_common.h
1705@@ -0,0 +1,1233 @@
1706+/*
1707+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
1708+ *
1709+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
1710+ *
1711+ * This program is free software; you can redistribute it and/or
1712+ * modify it under the terms of the GNU General Public License version
1713+ * 2 as published by the Free Software Foundation.
1714+ *
1715+ * This program is distributed in the hope that it will be useful,
1716+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
1717+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1718+ * GNU General Public License for more details.
1719+ *
1720+ * You should have received a copy of the GNU General Public License
1721+ * along with this program; if not, write to the Free Software
1722+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
1723+ * 02110-1301, USA.
1724+ *
1725+ *
1726+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
1727+ */
1728+
1729+#ifndef _SENSOR_COMMON_H
1730+#define _SENSOR_COMMON_H
1731+
1732+#include <media/v4l2-subdev.h>
1733+
1734+#define AEC_ALGO_V1 1
1735+#define AEC_ALGO_V2 2
1736+#define AEC_ALGO_V3 3
1737+#define AEC_ALGO_V4 4
1738+
1739+#ifndef AEC_ALGO
1740+#define AEC_ALGO AEC_ALGO_V3 /*AEC_ALGO_V2*/
1741+#endif
1742+/*
1743+ * interface version
1744+ * please increment the version if you add something new to the interface.
1745+ * This helps upper layer software to deal with different interface versions.
1746+ */
1747+#define SENSOR_INTERFACE_VERSION 4
1748+#define SENSOR_TYPE_SOC 0
1749+#define SENSOR_TYPE_RAW 1
1750+/* Just for current use case */
1751+#define SENSOR_TYPE_2M 0
1752+#define SENSOR_TYPE_5M 1
1753+
1754+/*
1755+ * capabilities / configuration
1756+ */
1757+
1758+/* ulBusWidth; */
1759+/*
1760+ * to expand to a (possibly higher) resolution in marvin, the LSBs will be set
1761+ * to zero
1762+ */
1763+#define SENSOR_BUSWIDTH_8BIT_ZZ 0x00000001
1764+/*
1765+ * to expand to a (possibly higher) resolution in marvin, the LSBs will be
1766+ * copied from the MSBs
1767+ */
1768+#define SENSOR_BUSWIDTH_8BIT_EX 0x00000002
1769+/*
1770+ * formerly known as SENSOR_BUSWIDTH_10BIT (at times no marvin derivative was
1771+ * able to process more than 10 bit)
1772+ */
1773+#define SENSOR_BUSWIDTH_10BIT_EX 0x00000004
1774+#define SENSOR_BUSWIDTH_10BIT_ZZ 0x00000008
1775+#define SENSOR_BUSWIDTH_12BIT 0x00000010
1776+
1777+#define SENSOR_BUSWIDTH_10BIT SENSOR_BUSWIDTH_10BIT_EX
1778+
1779+/*
1780+ * ulMode, operating mode of the image sensor in termns of output data format
1781+ * and
1782+ */
1783+
1784+/* timing data transmission */
1785+
1786+/* YUV-Data with separate h/v sync lines (ITU-R BT.601) */
1787+#define SENSOR_MODE_BT601 0x00000001
1788+/* YUV-Data with sync words inside the datastream (ITU-R BT.656) */
1789+#define SENSOR_MODE_BT656 0x00000002
1790+/* Bayer data with separate h/v sync lines */
1791+#define SENSOR_MODE_BAYER 0x00000004
1792+/*
1793+ * Any binary data without line/column-structure, (e.g. already JPEG encoded)
1794+ * h/v sync lines act as data valid signals
1795+ */
1796+#define SENSOR_MODE_DATA 0x00000008
1797+/* RAW picture data with separate h/v sync lines */
1798+#define SENSOR_MODE_PICT 0x00000010
1799+/* RGB565 data with separate h/v sync lines */
1800+#define SENSOR_MODE_RGB565 0x00000020
1801+/* SMIA conform data stream (see ulSmiaMode for details) */
1802+#define SENSOR_MODE_SMIA 0x00000040
1803+/* MIPI conform data stream (see ulMipiMode for details) */
1804+#define SENSOR_MODE_MIPI 0x00000080
1805+/*
1806+ * Bayer data with sync words inside the datastream (similar to ITU-R BT.656)
1807+ */
1808+#define SENSOR_MODE_BAY_BT656 0x00000100
1809+/*
1810+ * Raw picture data with sync words inside the datastream (similar to ITU-R
1811+ * BT.656)
1812+ */
1813+#define SENSOR_MODE_RAW_BT656 0x00000200
1814+
1815+/* ulSmiaMode */
1816+
1817+/* compression mode */
1818+#define SENSOR_SMIA_MODE_COMPRESSED 0x00000001
1819+/* 8bit to 10 bit decompression */
1820+#define SENSOR_SMIA_MODE_RAW_8_TO_10_DECOMP 0x00000002
1821+/* 12 bit RAW Bayer Data */
1822+#define SENSOR_SMIA_MODE_RAW_12 0x00000004
1823+/* 10 bit RAW Bayer Data */
1824+#define SENSOR_SMIA_MODE_RAW_10 0x00000008
1825+/* 8 bit RAW Bayer Data */
1826+#define SENSOR_SMIA_MODE_RAW_8 0x00000010
1827+/* 7 bit RAW Bayer Data */
1828+#define SENSOR_SMIA_MODE_RAW_7 0x00000020
1829+/* 6 bit RAW Bayer Data */
1830+#define SENSOR_SMIA_MODE_RAW_6 0x00000040
1831+/* RGB 888 Display ready Data */
1832+#define SENSOR_SMIA_MODE_RGB_888 0x00000080
1833+/* RGB 565 Display ready Data */
1834+#define SENSOR_SMIA_MODE_RGB_565 0x00000100
1835+/* RGB 444 Display ready Data */
1836+#define SENSOR_SMIA_MODE_RGB_444 0x00000200
1837+/* YUV420 Data */
1838+#define SENSOR_SMIA_MODE_YUV_420 0x00000400
1839+/* YUV422 Data */
1840+#define SENSOR_SMIA_MODE_YUV_422 0x00000800
1841+/* SMIA is disabled */
1842+#define SENSOR_SMIA_OFF 0x80000000
1843+
1844+/* ulMipiMode */
1845+
1846+/* YUV 420 8-bit */
1847+#define SENSOR_MIPI_MODE_YUV420_8 0x00000001
1848+/* YUV 420 10-bit */
1849+#define SENSOR_MIPI_MODE_YUV420_10 0x00000002
1850+/* Legacy YUV 420 8-bit */
1851+#define SENSOR_MIPI_MODE_LEGACY_YUV420_8 0x00000004
1852+/* YUV 420 8-bit (CSPS) */
1853+#define SENSOR_MIPI_MODE_YUV420_CSPS_8 0x00000008
1854+/* YUV 420 10-bit (CSPS) */
1855+#define SENSOR_MIPI_MODE_YUV420_CSPS_10 0x00000010
1856+/* YUV 422 8-bit */
1857+#define SENSOR_MIPI_MODE_YUV422_8 0x00000020
1858+/* YUV 422 10-bit */
1859+#define SENSOR_MIPI_MODE_YUV422_10 0x00000040
1860+/* RGB 444 */
1861+#define SENSOR_MIPI_MODE_RGB444 0x00000080
1862+/* RGB 555 */
1863+#define SENSOR_MIPI_MODE_RGB555 0x00000100
1864+/* RGB 565 */
1865+#define SENSOR_MIPI_MODE_RGB565 0x00000200
1866+/* RGB 666 */
1867+#define SENSOR_MIPI_MODE_RGB666 0x00000400
1868+/* RGB 888 */
1869+#define SENSOR_MIPI_MODE_RGB888 0x00000800
1870+/* RAW_6 */
1871+#define SENSOR_MIPI_MODE_RAW_6 0x00001000
1872+/* RAW_7 */
1873+#define SENSOR_MIPI_MODE_RAW_7 0x00002000
1874+/* RAW_8 */
1875+#define SENSOR_MIPI_MODE_RAW_8 0x00004000
1876+/* RAW_10 */
1877+#define SENSOR_MIPI_MODE_RAW_10 0x00008000
1878+/* RAW_12 */
1879+#define SENSOR_MIPI_MODE_RAW_12 0x00010000
1880+/* MIPI is disabled */
1881+#define SENSOR_MIPI_OFF 0x80000000
1882+
1883+/* ulFieldInv; */
1884+
1885+#define SENSOR_FIELDINV_NOSWAP 0x00000001
1886+#define SENSOR_FIELDINV_SWAP 0x00000002
1887+
1888+/* ulFieldSel; */
1889+
1890+#define SENSOR_FIELDSEL_BOTH 0x00000001
1891+#define SENSOR_FIELDSEL_EVEN 0x00000002
1892+#define SENSOR_FIELDSEL_ODD 0x00000004
1893+
1894+/* ulYCSeq; */
1895+
1896+#define SENSOR_YCSEQ_YCBYCR 0x00000001
1897+#define SENSOR_YCSEQ_YCRYCB 0x00000002
1898+#define SENSOR_YCSEQ_CBYCRY 0x00000004
1899+#define SENSOR_YCSEQ_CRYCBY 0x00000008
1900+
1901+/* ulConv422; */
1902+#if 0
1903+#define SENSOR_CONV422_COSITED 0x00000001
1904+#define SENSOR_CONV422_NOCOSITED 0x00000002
1905+#define SENSOR_CONV422_COLORINT 0x00000004
1906+#endif
1907+#define SENSOR_CONV422_COSITED 0x00000001
1908+#define SENSOR_CONV422_INTER 0x00000002
1909+#define SENSOR_CONV422_NOCOSITED 0x00000004
1910+
1911+/* ulBPat; */
1912+
1913+#define SENSOR_BPAT_RGRGGBGB 0x00000001
1914+#define SENSOR_BPAT_GRGRBGBG 0x00000002
1915+#define SENSOR_BPAT_GBGBRGRG 0x00000004
1916+#define SENSOR_BPAT_BGBGGRGR 0x00000008
1917+
1918+/* ulHPol; */
1919+
1920+/* sync signal pulses high between lines */
1921+#define SENSOR_HPOL_SYNCPOS 0x00000001
1922+/* sync signal pulses low between lines */
1923+#define SENSOR_HPOL_SYNCNEG 0x00000002
1924+/* reference signal is high as long as sensor puts out line data */
1925+#define SENSOR_HPOL_REFPOS 0x00000004
1926+/* reference signal is low as long as sensor puts out line data */
1927+#define SENSOR_HPOL_REFNEG 0x00000008
1928+
1929+/* ulVPol; */
1930+
1931+#define SENSOR_VPOL_POS 0x00000001
1932+#define SENSOR_VPOL_NEG 0x00000002
1933+
1934+/* ulEdge; */
1935+
1936+#define SENSOR_EDGE_RISING 0x00000001
1937+#define SENSOR_EDGE_FALLING 0x00000002
1938+
1939+/* ulBls; */
1940+
1941+/* turns on/off additional black lines at frame start */
1942+#define SENSOR_BLS_OFF 0x00000001
1943+#define SENSOR_BLS_TWO_LINES 0x00000002
1944+/* two lines top and two lines bottom */
1945+#define SENSOR_BLS_FOUR_LINES 0x00000004
1946+
1947+/* ulGamma; */
1948+
1949+/* turns on/off gamma correction in the sensor ISP */
1950+#define SENSOR_GAMMA_ON 0x00000001
1951+#define SENSOR_GAMMA_OFF 0x00000002
1952+
1953+/* ulCConv; */
1954+
1955+/* turns on/off color conversion matrix in the sensor ISP */
1956+#define SENSOR_CCONV_ON 0x00000001
1957+#define SENSOR_CCONV_OFF 0x00000002
1958+
1959+/* ulRes; */
1960+
1961+/* 88x72 */
1962+#define SENSOR_RES_QQCIF 0x00000001
1963+/* 160x120 */
1964+#define SENSOR_RES_QQVGA 0x00000002
1965+/* 176x144 */
1966+#define SENSOR_RES_QCIF 0x00000004
1967+/* 320x240 */
1968+#define SENSOR_RES_QVGA 0x00000008
1969+/* 352x288 */
1970+#define SENSOR_RES_CIF 0x00000010
1971+/* 640x480 */
1972+#define SENSOR_RES_VGA 0x00000020
1973+/* 800x600 */
1974+#define SENSOR_RES_SVGA 0x00000040
1975+/* 1024x768 */
1976+#define SENSOR_RES_XGA 0x00000080
1977+/* 1280x960 max. resolution of OV9640 (QuadVGA) */
1978+#define SENSOR_RES_XGA_PLUS 0x00000100
1979+/* 1280x1024 */
1980+#define SENSOR_RES_SXGA 0x00000200
1981+/* 1600x1200 */
1982+#define SENSOR_RES_UXGA 0x00000400
1983+/* 2048x1536 */
1984+#define SENSOR_RES_QXGA 0x00000800
1985+#define SENSOR_RES_QXGA_PLUS 0x00001000
1986+#define SENSOR_RES_RAWMAX 0x00002000
1987+/* 4080x1024 */
1988+#define SENSOR_RES_YUV_HMAX 0x00004000
1989+/* 1024x4080 */
1990+#define SENSOR_RES_YUV_VMAX 0x00008000
1991+#ifdef _DEBUG
1992+/* depends on further defines (TEST_SIZE_H and TEST_SIZE_V) */
1993+#define SENSOR_RES_TEST 0x00010000
1994+
1995+#define TEST_SIZE_H (2600)
1996+#define TEST_SIZE_V (2046)
1997+/* #define TEST_SIZE_V (1950) */
1998+
1999+/* #ifdef _DEBUG */
2000+#endif
2001+/* 720x480 */
2002+#define SENSOR_RES_L_AFM 0x00020000
2003+/* 128x96 */
2004+#define SENSOR_RES_M_AFM 0x00040000
2005+/* 64x32 */
2006+#define SENSOR_RES_S_AFM 0x00080000
2007+/* 352x240 */
2008+#define SENSOR_RES_BP1 0x00100000
2009+/* 2586x2048, quadruple SXGA, 5,3 Mpix */
2010+#define SENSOR_RES_QSXGA 0x00200000
2011+/* 2600x2048, max. resolution of M5, 5,32 Mpix */
2012+#define SENSOR_RES_QSXGA_PLUS 0x00400000
2013+/* 2600x1950 */
2014+#define SENSOR_RES_QSXGA_PLUS2 0x00800000
2015+/* 2686x2048, 5.30M */
2016+#define SENSOR_RES_QSXGA_PLUS3 0x01000000
2017+/* 3200x2048, 6.56M */
2018+#define SENSOR_RES_WQSXGA 0x02000000
2019+/* 3200x2400, 7.68M */
2020+#define SENSOR_RES_QUXGA 0x04000000
2021+/* 3840x2400, 9.22M */
2022+#define SENSOR_RES_WQUXGA 0x08000000
2023+/* 4096x3072, 12.59M */
2024+#define SENSOR_RES_HXGA 0x10000000
2025+
2026+/* 2592x1044 replace with SENSOR_RES_QXGA_PLUS */
2027+/*#define SENSOR_RES_QSXGA_PLUS4 0x10000000*/
2028+/* 1920x1080 */
2029+#define SENSOR_RES_1080P 0x20000000
2030+/* 1280x720 */
2031+#define SENSOR_RES_720P 0x40000000
2032+
2033+/* FIXME 1304x980*/
2034+#define SENSOR_RES_VGA_PLUS 0x80000000
2035+#define VGA_PLUS_SIZE_H (1304)
2036+#define VGA_PLUS_SIZE_V (980)
2037+
2038+#define QSXGA_PLUS4_SIZE_H (2592)
2039+#define QSXGA_PLUS4_SIZE_V (1944)
2040+#define RES_1080P_SIZE_H (1920)
2041+#define RES_1080P_SIZE_V (1080)
2042+#define RES_720P_SIZE_H (1280)
2043+#define RES_720P_SIZE_V (720)
2044+#define QQCIF_SIZE_H (88)
2045+#define QQCIF_SIZE_V (72)
2046+#define QQVGA_SIZE_H (160)
2047+#define QQVGA_SIZE_V (120)
2048+#define QCIF_SIZE_H (176)
2049+#define QCIF_SIZE_V (144)
2050+#define QVGA_SIZE_H (320)
2051+#define QVGA_SIZE_V (240)
2052+#define CIF_SIZE_H (352)
2053+#define CIF_SIZE_V (288)
2054+#define VGA_SIZE_H (640)
2055+#define VGA_SIZE_V (480)
2056+#define SVGA_SIZE_H (800)
2057+#define SVGA_SIZE_V (600)
2058+#define XGA_SIZE_H (1024)
2059+#define XGA_SIZE_V (768)
2060+#define XGA_PLUS_SIZE_H (1280)
2061+#define XGA_PLUS_SIZE_V (960)
2062+#define SXGA_SIZE_H (1280)
2063+#define SXGA_SIZE_V (1024)
2064+/* will be removed soon */
2065+#define QSVGA_SIZE_H (1600)
2066+/* will be removed soon */
2067+#define QSVGA_SIZE_V (1200)
2068+#define UXGA_SIZE_H (1600)
2069+#define UXGA_SIZE_V (1200)
2070+#define QXGA_SIZE_H (2048)
2071+#define QXGA_SIZE_V (1536)
2072+#define QXGA_PLUS_SIZE_H (2592)
2073+#define QXGA_PLUS_SIZE_V (1944)
2074+#define RAWMAX_SIZE_H (4096)
2075+#define RAWMAX_SIZE_V (2048)
2076+#define YUV_HMAX_SIZE_H (4080)
2077+#define YUV_HMAX_SIZE_V (1024)
2078+#define YUV_VMAX_SIZE_H (1024)
2079+#define YUV_VMAX_SIZE_V (4080)
2080+#define BP1_SIZE_H (352)
2081+#define BP1_SIZE_V (240)
2082+#define L_AFM_SIZE_H (720)
2083+#define L_AFM_SIZE_V (480)
2084+#define M_AFM_SIZE_H (128)
2085+#define M_AFM_SIZE_V (96)
2086+#define S_AFM_SIZE_H (64)
2087+#define S_AFM_SIZE_V (32)
2088+#define QSXGA_SIZE_H (2560)
2089+#define QSXGA_SIZE_V (2048)
2090+#define QSXGA_MINUS_SIZE_V (1920)
2091+#define QSXGA_PLUS_SIZE_H (2600)
2092+#define QSXGA_PLUS_SIZE_V (2048)
2093+#define QSXGA_PLUS2_SIZE_H (2600)
2094+#define QSXGA_PLUS2_SIZE_V (1950)
2095+#define QUXGA_SIZE_H (3200)
2096+#define QUXGA_SIZE_V (2400)
2097+#define SIZE_H_2500 (2500)
2098+#define QSXGA_PLUS3_SIZE_H (2686)
2099+#define QSXGA_PLUS3_SIZE_V (2048)
2100+#define QSXGA_PLUS4_SIZE_V (1944)
2101+#define WQSXGA_SIZE_H (3200)
2102+#define WQSXGA_SIZE_V (2048)
2103+#define WQUXGA_SIZE_H (3200)
2104+#define WQUXGA_SIZE_V (2400)
2105+#define HXGA_SIZE_H (4096)
2106+#define HXGA_SIZE_V (3072)
2107+
2108+/* ulBLC; */
2109+#define SENSOR_DWNSZ_SUBSMPL 0x00000001
2110+#define SENSOR_DWNSZ_SCAL_BAY 0x00000002
2111+#define SENSOR_DWNSZ_SCAL_COS 0x00000004
2112+
2113+/* Camera BlackLevelCorrection on */
2114+#define SENSOR_BLC_AUTO 0x00000001
2115+/* Camera BlackLevelCorrection off */
2116+#define SENSOR_BLC_OFF 0x00000002
2117+
2118+/* ulAGC; */
2119+
2120+/* Camera AutoGainControl on */
2121+#define SENSOR_AGC_AUTO 0x00000001
2122+/* Camera AutoGainControl off */
2123+#define SENSOR_AGC_OFF 0x00000002
2124+
2125+/* ulAWB; */
2126+
2127+/* Camera AutoWhiteBalance on */
2128+#define SENSOR_AWB_AUTO 0x00000001
2129+/* Camera AutoWhiteBalance off */
2130+#define SENSOR_AWB_OFF 0x00000002
2131+
2132+/* ulAEC; */
2133+
2134+/* Camera AutoExposureControl on */
2135+#define SENSOR_AEC_AUTO 0x00000001
2136+/* Camera AutoExposureControl off */
2137+#define SENSOR_AEC_OFF 0x00000002
2138+
2139+/* ulCieProfile; */
2140+#define ISI_AEC_MODE_STAND 0x00000001
2141+#define ISI_AEC_MODE_SLOW 0x00000002
2142+#define ISI_AEC_MODE_FAST 0x00000004
2143+#define ISI_AEC_MODE_NORMAL 0x00000008
2144+#define SENSOR_CIEPROF_A 0x00000001
2145+#define SENSOR_CIEPROF_B 0x00000002
2146+#define SENSOR_CIEPROF_C 0x00000004
2147+#define SENSOR_CIEPROF_D50 0x00000008
2148+#define SENSOR_CIEPROF_D55 0x00000010
2149+#define SENSOR_CIEPROF_D65 0x00000020
2150+#define SENSOR_CIEPROF_D75 0x00000040
2151+#define SENSOR_CIEPROF_E 0x00000080
2152+#define SENSOR_CIEPROF_FLUOR 0x00000100
2153+#define SENSOR_CIEPROF_FLUORH 0x00000200
2154+#define SENSOR_CIEPROF_TUNG 0x00000400
2155+#define SENSOR_CIEPROF_TWI 0x00000800
2156+#define SENSOR_CIEPROF_SUN 0x00001000
2157+#define SENSOR_CIEPROF_FLASH 0x00002000
2158+#define SENSOR_CIEPROF_SHADE 0x00004000
2159+#define SENSOR_CIEPROF_DAY 0x00008000
2160+#define SENSOR_CIEPROF_F1 0x00010000
2161+#define SENSOR_CIEPROF_F2 0x00020000
2162+#define SENSOR_CIEPROF_F3 0x00040000
2163+#define SENSOR_CIEPROF_F4 0x00080000
2164+#define SENSOR_CIEPROF_F5 0x00100000
2165+#define SENSOR_CIEPROF_F6 0x00200000
2166+#define SENSOR_CIEPROF_F7 0x00400000
2167+#define SENSOR_CIEPROF_F8 0x00800000
2168+#define SENSOR_CIEPROF_F9 0x01000000
2169+#define SENSOR_CIEPROF_F10 0x02000000
2170+#define SENSOR_CIEPROF_F11 0x04000000
2171+#define SENSOR_CIEPROF_F12 0x08000000
2172+#define SENSOR_CIEPROF_CLOUDY 0x10000000
2173+#define SENSOR_CIEPROF_SUNNY 0x20000000
2174+#define SENSOR_CIEPROF_OLDISS 0x80000000
2175+#define SENSOR_CIEPROF_DEFAULT 0x00000000
2176+
2177+/* ulFlickerFreq */
2178+
2179+/* no compensation for flickering environmental illumination */
2180+#define SENSOR_FLICKER_OFF 0x00000001
2181+/* compensation for 100Hz flicker frequency (at 50Hz mains frequency) */
2182+#define SENSOR_FLICKER_100 0x00000002
2183+/* compensation for 120Hz flicker frequency (at 60Hz mains frequency) */
2184+#define SENSOR_FLICKER_120 0x00000004
2185+
2186+/*
2187+ * sensor capabilities struct: a struct member may have 0, 1 or several bits
2188+ * set according to the capabilities of the sensor. All struct members must be
2189+ * unsigned int and no padding is allowed. Thus, access to the fields is also
2190+ * possible by means of a field of unsigned int values. Indicees for the
2191+ * field-like access are given below.
2192+ */
2193+struct ci_sensor_caps{
2194+ unsigned int bus_width;
2195+ unsigned int mode;
2196+ unsigned int field_inv;
2197+ unsigned int field_sel;
2198+ unsigned int ycseq;
2199+ unsigned int conv422;
2200+ unsigned int bpat;
2201+ unsigned int hpol;
2202+ unsigned int vpol;
2203+ unsigned int edge;
2204+ unsigned int bls;
2205+ unsigned int gamma;
2206+ unsigned int cconv;
2207+ unsigned int res;
2208+ unsigned int dwn_sz;
2209+ unsigned int blc;
2210+ unsigned int agc;
2211+ unsigned int awb;
2212+ unsigned int aec;
2213+ /* extention SENSOR version 2 */
2214+ unsigned int cie_profile;
2215+
2216+ /* extention SENSOR version 3 */
2217+ unsigned int flicker_freq;
2218+
2219+ /* extension SENSOR version 4 */
2220+ unsigned int smia_mode;
2221+ unsigned int mipi_mode;
2222+
2223+ /* Add name here to load shared library */
2224+ unsigned int type;
2225+ char name[32];
2226+
2227+ struct v4l2_subdev sd;
2228+};
2229+
2230+#define SENSOR_CAP_BUSWIDTH 0
2231+#define SENSOR_CAP_MODE 1
2232+#define SENSOR_CAP_FIELDINV 2
2233+#define SENSOR_CAP_FIELDSEL 3
2234+#define SENSOR_CAP_YCSEQ 4
2235+#define SENSOR_CAP_CONV422 5
2236+#define SENSOR_CAP_BPAT 6
2237+#define SENSOR_CAP_HPOL 7
2238+#define SENSOR_CAP_VPOL 8
2239+#define SENSOR_CAP_EDGE 9
2240+#define SENSOR_CAP_BLS 10
2241+#define SENSOR_CAP_GAMMA 11
2242+#define SENSOR_CAP_CCONF 12
2243+#define SENSOR_CAP_RES 13
2244+#define SENSOR_CAP_DWNSZ 14
2245+#define SENSOR_CAP_BLC 15
2246+#define SENSOR_CAP_AGC 16
2247+#define SENSOR_CAP_AWB 17
2248+#define SENSOR_CAP_AEC 18
2249+#define SENSOR_CAP_CIEPROFILE 19
2250+#define SENSOR_CAP_FLICKERFREQ 20
2251+#define SENSOR_CAP_SMIAMODE 21
2252+#define SENSOR_CAP_MIPIMODE 22
2253+#define SENSOR_CAP_AECMODE 23
2254+
2255+
2256+/* size of capabilities array (in number of unsigned int fields) */
2257+#define SENSOR_CAP_COUNT 24
2258+
2259+/*
2260+ * Sensor configuration struct: same layout as the capabilities struct, but to
2261+ * configure the sensor all struct members which are supported by the sensor
2262+ * must have only 1 bit set. Members which are not supported by the sensor
2263+ * must not have any bits set.
2264+ */
2265+#define ci_sensor_config ci_sensor_caps
2266+
2267+/* single parameter support */
2268+
2269+/* exposure time */
2270+#define SENSOR_PARM_EXPOSURE 0
2271+/* index in the AE control table */
2272+#define SENSOR_PARM_EXPTBL_INDEX 1
2273+
2274+/* gain */
2275+/* overall gain (all components) */
2276+#define SENSOR_PARM_GAIN 2
2277+/* component gain of the red pixels */
2278+#define SENSOR_PARM_CGAIN_R 3
2279+/* component gain of the green pixels */
2280+#define SENSOR_PARM_CGAIN_G 4
2281+/* component gain of the blue pixels */
2282+#define SENSOR_PARM_CGAIN_B 5
2283+/*
2284+ * component gain of the green pixels sharing a bayer line with the red ones
2285+ */
2286+#define SENSOR_PARM_CGAINB_GR 6
2287+/*
2288+ * component gain of the green pixels sharing a bayer line with the blue ones
2289+ */
2290+#define SENSOR_PARM_CGAINB_GB 7
2291+
2292+/* blacklevel */
2293+
2294+/* black-level adjustment (all components) */
2295+#define SENSOR_PARM_BLKL 8
2296+/* component black-level of the red pixels */
2297+#define SENSOR_PARM_CBLKL_R 9
2298+/* component black-level of the green pixels */
2299+#define SENSOR_PARM_CBLKL_G 10
2300+/* component black-level of the blue pixels */
2301+#define SENSOR_PARM_CBLKL_B 11
2302+/*
2303+ * component black-level of the green pixels sharing a bayer line with the red
2304+ * ones
2305+ */
2306+#define SENSOR_PARM_CBLKLB_GR 12
2307+/*
2308+ * component black-level of the green pixels sharing a bayer line with the
2309+ * blue ones
2310+ */
2311+#define SENSOR_PARM_CBLKLB_GB 13
2312+
2313+/* resolution & cropping */
2314+
2315+/* base resolution in pixel (X) */
2316+#define SENSOR_PARM_BASERES_X 14
2317+/* base resolution in pixel (Y) */
2318+#define SENSOR_PARM_BASERES_Y 15
2319+/* window top-left pixel (X) */
2320+#define SENSOR_PARM_WINDOW_X 16
2321+/* window top-left pixel (Y) */
2322+#define SENSOR_PARM_WINDOW_Y 17
2323+/* window width in pixel */
2324+#define SENSOR_PARM_WINDOW_W 18
2325+/* window height in pixel */
2326+#define SENSOR_PARM_WINDOW_H 19
2327+
2328+/* frame rate / clock */
2329+
2330+/*
2331+ * frame rate in frames per second, fixed point format, 16 bit fractional part
2332+ */
2333+#define SENSOR_PARM_FRAMERATE_FPS 20
2334+/* frame rate fine adjustment */
2335+#define SENSOR_PARM_FRAMERATE_PITCH 21
2336+/* clock divider setting */
2337+#define SENSOR_PARM_CLK_DIVIDER 22
2338+/* input clock in Hz. */
2339+#define SENSOR_PARM_CLK_INPUT 23
2340+/*
2341+ * output (pixel-) clock in Hz. Note that for e.g. YUV422-formats, 2 pixel
2342+ * clock cycles are needed per pixel
2343+ */
2344+#define SENSOR_PARM_CLK_PIXEL 24
2345+
2346+/* number of parameter IDs */
2347+
2348+#define SENSOR_PARM__COUNT 25
2349+
2350+/* bit description of the result of the IsiParmInfo routine */
2351+
2352+/* parameter can be retrieved from the sensor */
2353+#define SENSOR_PARMINFO_GET 0x00000001
2354+/* parameter can be set into the sensor */
2355+#define SENSOR_PARMINFO_SET 0x00000002
2356+/* parameter can change at any time during operation */
2357+#define SENSOR_PARMINFO_VOLATILE 0x00000004
2358+/* range information available for the parameter in question */
2359+#define SENSOR_PARMINFO_RANGE 0x00000008
2360+/* range of possible values is not continous. */
2361+#define SENSOR_PARMINFO_DISCRETE 0x00000010
2362+/* parameter may change after a configuration update. */
2363+#define SENSOR_PARMINFO_CONFIG 0x00000020
2364+/* range information may change after a configuration update. */
2365+#define SENSOR_PARMINFO_RCONFIG 0x00000040
2366+
2367+/* multi-camera support */
2368+#define SENSOR_UNKNOWN_SENSOR_ID (0)
2369+
2370+/* structure / type definitions */
2371+/*
2372+ * Input gamma correction curve for R, G or B of the sensor. Since this gamma
2373+ * curve is sensor specific, it will be deliveres by the sensors specific code.
2374+ * This curve will be programmed into Marvin registers.
2375+ */
2376+#define SENSOR_GAMMA_CURVE_ARR_SIZE (17)
2377+
2378+struct ci_sensor_gamma_curve{
2379+ unsigned short isp_gamma_y[SENSOR_GAMMA_CURVE_ARR_SIZE];
2380+
2381+ /* if three curves are given separately for RGB */
2382+ unsigned int gamma_dx0;
2383+
2384+ /* only the struct for R holds valid DX values */
2385+ unsigned int gamma_dx1;
2386+};
2387+
2388+/*
2389+ * SENSOR fixed point constant values They are represented as signed fixed point
2390+ * numbers with 12 bit integer and 20 bit fractional part, thus ranging from
2391+ * -2048.0000000 (0x80000000) to +2047.9999990 (0x7FFFFFFF). In the following
2392+ * some frequently used constant values are defined.
2393+ */
2394+/* - 0.794944 */
2395+#define SENSOR_FP_M0000_794944 (0xFFF347E9)
2396+/* - 0.500000 */
2397+#define SENSOR_FP_M0000_500000 (0xFFF80000)
2398+/* - 0.404473 */
2399+#define SENSOR_FP_M0000_404473 (0xFFF98748)
2400+/* - 0.062227 */
2401+#define SENSOR_FP_M0000_062227 (0xFFFF011F)
2402+/* - 0.024891 */
2403+#define SENSOR_FP_M0000_024891 (0xFFFF9A0C)
2404+
2405+/* 0.000000 */
2406+#define SENSOR_FP_P0000_000000 (0x00000000)
2407+
2408+/* + 0.500000 */
2409+#define SENSOR_FP_P0000_500000 (0x00080000)
2410+/* + 1.000000 */
2411+#define SENSOR_FP_P0001_000000 (0x00100000)
2412+/* + 1.163636 */
2413+#define SENSOR_FP_P0001_163636 (0x00129E40)
2414+/* + 1.600778 */
2415+#define SENSOR_FP_P0001_600778 (0x00199CC9)
2416+/* + 1.991249 */
2417+#define SENSOR_FP_P0001_991249 (0x001FDC27)
2418+/* + 16.000000 */
2419+#define SENSOR_FP_P0016_000000 (0x01000000)
2420+/* + 128.000000 */
2421+#define SENSOR_FP_P0128_000000 (0x08000000)
2422+/* + 255.000000 */
2423+#define SENSOR_FP_P0255_000000 (0x0FF00000)
2424+/* + 256.000000 */
2425+#define SENSOR_FP_P0256_000000 (0x10000000)
2426+
2427+/*
2428+ * Matrix coefficients used for CrossTalk and/or color conversion. The 9
2429+ * coefficients are laid out as follows (zero based index):
2430+ * 0 | 1 | 2
2431+ * 3 | 4 | 5
2432+ * 6 | 7 | 8
2433+ * They are represented as signed fixed point numbers with 12 bit integer and
2434+ * 20 bit fractional part, thus ranging from -2048.0000000 (0x80000000) to
2435+ * +2047.9999990 (0x7FFFFFFF).
2436+ */
2437+struct ci_sensor_3x3_matrix{
2438+ int coeff[9];
2439+};
2440+
2441+/*
2442+ * Matrix coefficients used for CrossTalk and/or color conversion. The 9
2443+ * coefficients are laid out as follows (zero based index):
2444+ * 0 | 1 | 2
2445+ * 3 | 4 | 5
2446+ * 6 | 7 | 8
2447+ * They are represented as float numbers
2448+ */
2449+struct ci_sensor_3x3_float_matrix{
2450+ float coeff[9];
2451+};
2452+
2453+struct ci_sensor_3x1_float_matrix{
2454+ float coeff[3];
2455+};
2456+
2457+struct ci_sensor_4x1_float_matrix{
2458+ float coeff[4];
2459+};
2460+
2461+struct ci_sensor_3x2_float_matrix{
2462+ float coeff[6];
2463+};
2464+
2465+struct ci_sensor_2x1_float_matrix{
2466+ float coeff[2];
2467+};
2468+
2469+struct ci_sensor_2x2_float_matrix{
2470+ float coeff[4];
2471+};
2472+
2473+struct ci_sensor_1x1_float_matrix{
2474+ float coeff[1];
2475+};
2476+
2477+struct ci_sensor_gauss_factor{
2478+ float gauss_factor;
2479+};
2480+
2481+struct isp_pca_values{
2482+ float pcac1;
2483+ float pcac2;
2484+};
2485+
2486+/*
2487+ * CrossTalk offset. In addition to the matrix multiplication an offset can be
2488+ * added to the pixel values for R, G and B separately. This offset is applied
2489+ * after the matrix multiplication. The values are arranged as unified, see
2490+ * above.
2491+ */
2492+struct ci_sensor_xtalk_offset{
2493+ int ct_offset_red;
2494+ int ct_offset_green;
2495+ int ct_offset_blue;
2496+};
2497+
2498+struct ci_sensor_xtalk_float_offset{
2499+ float ct_offset_red;
2500+ float ct_offset_green;
2501+ float ct_offset_blue;
2502+};
2503+
2504+/*
2505+ * white balancing gains There are two green gains: One for the green Bayer
2506+ * patterns in the red and one for the blue line. In the case the used MARVIN
2507+ * derivative is not able to apply separate green gains the mean value of both
2508+ * greens will be used for the green gain. The component gains are represented
2509+ * as signed fixed point numbers with 12 bit integer and 20 bit fractional
2510+ * part, thus ranging from -2048.0000000 (0x80000000) to +2047.9999990
2511+ * (0x7FFFFFFF). Example: +1.0 is represented by 0x00100000.
2512+ */
2513+struct ci_sensor_component_gain{
2514+ float red;
2515+ float green_r;
2516+ float green_b;
2517+ float blue;
2518+};
2519+
2520+/*
2521+ * white balance values, default is 0x80 for all components. The struct can be
2522+ * used to provide linear scaling factors to achive a suitable white balance
2523+ * for certain lightning conditions.
2524+ */
2525+struct ci_sensor_comp_gain{
2526+ float red;
2527+ float green;
2528+ float blue;
2529+};
2530+
2531+/*
2532+ * cross-talk matrix dependent minimum / maximum red and blue gains
2533+ */
2534+struct ci_sensor_component_gain_limits{
2535+ unsigned short red_lower_limit;
2536+ unsigned short red_upper_limit;
2537+ unsigned short blue_lower_limit;
2538+ unsigned short blue_upper_limit;
2539+ unsigned int next_cie_higher_temp;
2540+ unsigned int next_cie_lower_temp;
2541+};
2542+
2543+/*
2544+* sensor characteristic struct. Is filled in by sensor specific code after
2545+* main configuration. Features not supported by the sensor driver code
2546+* will be initialized with default values (1x linear gamma, standard
2547+* color conversion, cross talk and component gain settings).
2548+*/
2549+struct ci_sensor_awb_profile{
2550+
2551+ /*
2552+ * In the case that all 3 gamma curves are identically, just
2553+ * set all 3 pointers to the same address.
2554+ */
2555+
2556+ /* input gammaR */
2557+ const struct ci_sensor_gamma_curve *gamma_curve_r;
2558+
2559+ /* input gammaG */
2560+ const struct ci_sensor_gamma_curve *gamma_curve_g;
2561+
2562+ /* input gammaB */
2563+ const struct ci_sensor_gamma_curve *gamma_curve_b;
2564+
2565+ /* ColorConversion matrix coefficients */
2566+ const struct ci_sensor_3x3_float_matrix *color_conv_coeff;
2567+
2568+ /* CrossTalk matrix coefficients */
2569+ const struct ci_sensor_3x3_float_matrix *cross_talk_coeff;
2570+
2571+ /* CrossTalk offsets */
2572+ const struct ci_sensor_xtalk_float_offset *cross_talk_offset;
2573+ const struct ci_sensor_3x1_float_matrix *svd_mean_value;
2574+ const struct ci_sensor_3x2_float_matrix *pca_matrix;
2575+ const struct ci_sensor_2x1_float_matrix *gauss_mean_value;
2576+ const struct ci_sensor_2x2_float_matrix *covariance_matrix;
2577+ const struct ci_sensor_gauss_factor *gauss_factor;
2578+ const struct ci_sensor_2x1_float_matrix *threshold;
2579+ const struct ci_sensor_1x1_float_matrix *k_factor;
2580+ const struct ci_sensor_1x1_float_matrix *gexp_middle;
2581+ const struct ci_sensor_1x1_float_matrix *var_distr_in;
2582+ const struct ci_sensor_1x1_float_matrix *mean_distr_in;
2583+ const struct ci_sensor_1x1_float_matrix *var_distr_out;
2584+ const struct ci_sensor_1x1_float_matrix *mean_distr_out;
2585+ const struct ci_sensor_component_gain *component_gain;
2586+ const struct ci_sensor_loc_dist *loc_dist;
2587+
2588+};
2589+
2590+/*
2591+ * General purpose window. Normally it is used to describe a WOI (Window Of
2592+ * Interest) inside the background area (e.g. image data area). The offset
2593+ * values count from 0 of the background area. The defined point is the upper
2594+ * left corner of the WOI with the specified width and height.
2595+ */
2596+struct ci_sensor_window{
2597+ unsigned short hoffs;
2598+ unsigned short voffs;
2599+ unsigned short hsize;
2600+ unsigned short vsize;
2601+};
2602+
2603+/*
2604+ * Image data description. The frame size describes the complete image data
2605+ * area output of the sensor. This includes dummy, black, dark, visible and
2606+ * manufacturer specific pixels which could be combined in rows and / or in
2607+ * columns. The visible window describes the visible pixel area inside the
2608+ * image data area. In the case the image data area does only contain visible
2609+ * pixels, the offset values have to be 0 and the horizontal and vertical
2610+ * sizes are equal to the frame size.
2611+ */
2612+struct ci_sensor_image_data_info{
2613+ unsigned short frame_h_size;
2614+ unsigned short frame_v_size;
2615+ struct ci_sensor_window visible_window;
2616+};
2617+
2618+/* black level compensation mean values */
2619+struct ci_sensor_blc_mean{
2620+ unsigned char mean_a;
2621+ unsigned char mean_b;
2622+ unsigned char mean_c;
2623+ unsigned char mean_d;
2624+};
2625+
2626+/* autowhitebalance mean values */
2627+
2628+struct ci_sensor_awb_mean{
2629+#if 0
2630+ unsigned int white;
2631+ unsigned char mean_y;
2632+ unsigned char mean_cb;
2633+ unsigned char mean_cr;
2634+#else
2635+ unsigned int white;
2636+ unsigned char mean_Y__G;
2637+ unsigned char mean_cb__B;
2638+ unsigned char mean_cr__R;
2639+#endif
2640+};
2641+
2642+/* autowhitebalance mean values */
2643+
2644+struct ci_sensor_awb_float_mean{
2645+ unsigned int white;
2646+ float mean_y;
2647+ float mean_cb;
2648+ float mean_cr;
2649+};
2650+
2651+/* autoexposure mean values */
2652+
2653+struct ci_sensor_aec_mean{
2654+ unsigned char occ;
2655+ unsigned char mean;
2656+ unsigned char max;
2657+ unsigned char min;
2658+};
2659+
2660+/* bad pixel element attribute */
2661+
2662+enum ci_sensor_bp_corr_attr{
2663+
2664+ /* hot pixel */
2665+ SENSOR_BP_HOT,
2666+
2667+ /* dead pixel */
2668+ SENSOR_BP_DEAD
2669+};
2670+
2671+/* table element */
2672+
2673+struct ci_sensor_bp_table_elem{
2674+
2675+ /* Bad Pixel vertical address */
2676+ unsigned short bp_ver_addr;
2677+
2678+ /* Bad Pixel horizontal address */
2679+ unsigned short bp_hor_addr;
2680+
2681+ /* Bad pixel type (dead or hot) */
2682+ enum ci_sensor_bp_corr_attr bp_type;
2683+};
2684+
2685+/* Bad Pixel table */
2686+
2687+struct ci_sensor_bp_table{
2688+
2689+ /* Number of detected bad pixel */
2690+ unsigned int bp_number;
2691+
2692+ /* Pointer to BP Table */
2693+ struct ci_sensor_bp_table_elem *bp_table_elem;
2694+
2695+ /* Number of Table elements */
2696+ unsigned int bp_table_elem_num;
2697+};
2698+
2699+#define SENSOR_CTRL_TYPE_INTEGER 1
2700+#define SENSOR_CTRL_TYPE_BOOLEAN 2
2701+#define SENSOR_CTRL_TYPE_MENU 3
2702+#define SENSOR_CTRL_TYPE_BUTTON 4
2703+#define SENSOR_CTRL_TYPE_INTEGER64 5
2704+#define SENSOR_CTRL_TYPE_CTRL_CLASS 6
2705+
2706+#define SENSOR_CTRL_CLASS_USER 0x00980000
2707+#define SENSOR_CID_BASE (SENSOR_CTRL_CLASS_USER | 0x900)
2708+#define SENSOR_CID_USER_BASE SENSOR_CID_BASE
2709+/* IDs reserved for driver specific controls */
2710+#define SENSOR_CID_PRIVATE_BASE 0x08000000
2711+
2712+#define SENSOR_CID_USER_CLASS (SENSOR_CTRL_CLASS_USER | 1)
2713+#define SENSOR_CID_BRIGHTNESS (SENSOR_CID_BASE+0)
2714+#define SENSOR_CID_CONTRAST (SENSOR_CID_BASE+1)
2715+#define SENSOR_CID_SATURATION (SENSOR_CID_BASE+2)
2716+#define SENSOR_CID_HUE (SENSOR_CID_BASE+3)
2717+#define SENSOR_CID_AUDIO_VOLUME (SENSOR_CID_BASE+5)
2718+#define SENSOR_CID_AUDIO_BALANCE (SENSOR_CID_BASE+6)
2719+#define SENSOR_CID_AUDIO_BASS (SENSOR_CID_BASE+7)
2720+#define SENSOR_CID_AUDIO_TREBLE (SENSOR_CID_BASE+8)
2721+#define SENSOR_CID_AUDIO_MUTE (SENSOR_CID_BASE+9)
2722+#define SENSOR_CID_AUDIO_LOUDNESS (SENSOR_CID_BASE+10)
2723+#define SENSOR_CID_BLACK_LEVEL (SENSOR_CID_BASE+11)
2724+#define SENSOR_CID_AUTO_WHITE_BALANCE (SENSOR_CID_BASE+12)
2725+#define SENSOR_CID_DO_WHITE_BALANCE (SENSOR_CID_BASE+13)
2726+#define SENSOR_CID_RED_BALANCE (SENSOR_CID_BASE+14)
2727+#define SENSOR_CID_BLUE_BALANCE (SENSOR_CID_BASE+15)
2728+#define SENSOR_CID_GAMMA (SENSOR_CID_BASE+16)
2729+#define SENSOR_CID_WHITENESS (SENSOR_CID_GAMMA)
2730+#define SENSOR_CID_EXPOSURE (SENSOR_CID_BASE+17)
2731+#define SENSOR_CID_AUTOGAIN (SENSOR_CID_BASE+18)
2732+#define SENSOR_CID_GAIN (SENSOR_CID_BASE+19)
2733+#define SENSOR_CID_HFLIP (SENSOR_CID_BASE+20)
2734+#define SENSOR_CID_VFLIP (SENSOR_CID_BASE+21)
2735+#define SENSOR_CID_HCENTER (SENSOR_CID_BASE+22)
2736+#define SENSOR_CID_VCENTER (SENSOR_CID_BASE+23)
2737+#define SENSOR_CID_LASTP1 (SENSOR_CID_BASE+24)
2738+
2739+struct ci_sensor_parm{
2740+ unsigned int index;
2741+ int value;
2742+ int max;
2743+ int min;
2744+ int info;
2745+ int type;
2746+ char name[32];
2747+ int step;
2748+ int def_value;
2749+ int flags;
2750+};
2751+
2752+#define MRV_GRAD_TBL_SIZE 8
2753+#define MRV_DATA_TBL_SIZE 289
2754+struct ci_sensor_ls_corr_config{
2755+ /* correction values of R color part */
2756+ unsigned short ls_rdata_tbl[MRV_DATA_TBL_SIZE];
2757+ /* correction values of G color part */
2758+ unsigned short ls_gdata_tbl[MRV_DATA_TBL_SIZE];
2759+ /* correction values of B color part */
2760+ unsigned short ls_bdata_tbl[MRV_DATA_TBL_SIZE];
2761+ /* multiplication factors of x direction */
2762+ unsigned short ls_xgrad_tbl[MRV_GRAD_TBL_SIZE];
2763+ /* multiplication factors of y direction */
2764+ unsigned short ls_ygrad_tbl[MRV_GRAD_TBL_SIZE];
2765+ /* sector sizes of x direction */
2766+ unsigned short ls_xsize_tbl[MRV_GRAD_TBL_SIZE];
2767+ /* sector sizes of y direction */
2768+ unsigned short ls_ysize_tbl[MRV_GRAD_TBL_SIZE];
2769+};
2770+
2771+struct ci_sensor_reg{
2772+ unsigned int addr;
2773+ unsigned int value;
2774+};
2775+
2776+struct ci_sensor_loc_dist{
2777+ float pca1_low_temp;
2778+ float pca1_high_temp;
2779+ float locus_distance;
2780+ float a2;
2781+ float a1;
2782+ float a0;
2783+};
2784+
2785+static inline int ci_sensor_res2size(unsigned int res, unsigned short *h_size,
2786+ unsigned short *v_size)
2787+{
2788+ unsigned short hsize;
2789+ unsigned short vsize;
2790+ int err = 0;
2791+
2792+ switch (res) {
2793+ case SENSOR_RES_QQCIF:
2794+ hsize = QQCIF_SIZE_H;
2795+ vsize = QQCIF_SIZE_V;
2796+ break;
2797+ case SENSOR_RES_QQVGA:
2798+ hsize = QQVGA_SIZE_H;
2799+ vsize = QQVGA_SIZE_V;
2800+ break;
2801+ case SENSOR_RES_QCIF:
2802+ hsize = QCIF_SIZE_H;
2803+ vsize = QCIF_SIZE_V;
2804+ break;
2805+ case SENSOR_RES_QVGA:
2806+ hsize = QVGA_SIZE_H;
2807+ vsize = QVGA_SIZE_V;
2808+ break;
2809+ case SENSOR_RES_CIF:
2810+ hsize = CIF_SIZE_H;
2811+ vsize = CIF_SIZE_V;
2812+ break;
2813+ case SENSOR_RES_VGA:
2814+ hsize = VGA_SIZE_H;
2815+ vsize = VGA_SIZE_V;
2816+ break;
2817+ case SENSOR_RES_SVGA:
2818+ hsize = SVGA_SIZE_H;
2819+ vsize = SVGA_SIZE_V;
2820+ break;
2821+ case SENSOR_RES_XGA:
2822+ hsize = XGA_SIZE_H;
2823+ vsize = XGA_SIZE_V;
2824+ break;
2825+ case SENSOR_RES_XGA_PLUS:
2826+ hsize = XGA_PLUS_SIZE_H;
2827+ vsize = XGA_PLUS_SIZE_V;
2828+ break;
2829+ case SENSOR_RES_SXGA:
2830+ hsize = SXGA_SIZE_H;
2831+ vsize = SXGA_SIZE_V;
2832+ break;
2833+ case SENSOR_RES_UXGA:
2834+ hsize = UXGA_SIZE_H;
2835+ vsize = UXGA_SIZE_V;
2836+ break;
2837+ case SENSOR_RES_QXGA:
2838+ hsize = QXGA_SIZE_H;
2839+ vsize = QXGA_SIZE_V;
2840+ break;
2841+ case SENSOR_RES_QSXGA:
2842+ hsize = QSXGA_SIZE_H;
2843+ vsize = QSXGA_SIZE_V;
2844+ break;
2845+ case SENSOR_RES_QSXGA_PLUS:
2846+ hsize = QSXGA_PLUS_SIZE_H;
2847+ vsize = QSXGA_PLUS_SIZE_V;
2848+ break;
2849+ case SENSOR_RES_QSXGA_PLUS2:
2850+ hsize = QSXGA_PLUS2_SIZE_H;
2851+ vsize = QSXGA_PLUS2_SIZE_V;
2852+ break;
2853+ case SENSOR_RES_QSXGA_PLUS3:
2854+ hsize = QSXGA_PLUS3_SIZE_H;
2855+ vsize = QSXGA_PLUS3_SIZE_V;
2856+ break;
2857+ case SENSOR_RES_WQSXGA:
2858+ hsize = WQSXGA_SIZE_H;
2859+ vsize = WQSXGA_SIZE_V;
2860+ break;
2861+ case SENSOR_RES_QUXGA:
2862+ hsize = QUXGA_SIZE_H;
2863+ vsize = QUXGA_SIZE_V;
2864+ break;
2865+ case SENSOR_RES_WQUXGA:
2866+ hsize = WQUXGA_SIZE_H;
2867+ vsize = WQUXGA_SIZE_V;
2868+ break;
2869+ case SENSOR_RES_HXGA:
2870+ hsize = HXGA_SIZE_H;
2871+ vsize = HXGA_SIZE_V;
2872+ break;
2873+ case SENSOR_RES_RAWMAX:
2874+ hsize = RAWMAX_SIZE_H;
2875+ vsize = RAWMAX_SIZE_V;
2876+ break;
2877+ case SENSOR_RES_YUV_HMAX:
2878+ hsize = YUV_HMAX_SIZE_H;
2879+ vsize = YUV_HMAX_SIZE_V;
2880+ break;
2881+ case SENSOR_RES_YUV_VMAX:
2882+ hsize = YUV_VMAX_SIZE_H;
2883+ vsize = YUV_VMAX_SIZE_V;
2884+ break;
2885+ case SENSOR_RES_BP1:
2886+ hsize = BP1_SIZE_H;
2887+ vsize = BP1_SIZE_V;
2888+ break;
2889+ case SENSOR_RES_L_AFM:
2890+ hsize = L_AFM_SIZE_H;
2891+ vsize = L_AFM_SIZE_V;
2892+ break;
2893+ case SENSOR_RES_M_AFM:
2894+ hsize = M_AFM_SIZE_H;
2895+ vsize = M_AFM_SIZE_V;
2896+ break;
2897+ case SENSOR_RES_S_AFM:
2898+ hsize = S_AFM_SIZE_H;
2899+ vsize = S_AFM_SIZE_V;
2900+ break;
2901+
2902+ case SENSOR_RES_QXGA_PLUS:
2903+ hsize = QXGA_PLUS_SIZE_H;
2904+ vsize = QXGA_PLUS_SIZE_V;
2905+ break;
2906+
2907+ case SENSOR_RES_1080P:
2908+ hsize = RES_1080P_SIZE_H;
2909+ vsize = 1080;
2910+ break;
2911+
2912+ case SENSOR_RES_720P:
2913+ hsize = RES_720P_SIZE_H;
2914+ vsize = RES_720P_SIZE_V;
2915+ break;
2916+
2917+ case SENSOR_RES_VGA_PLUS:
2918+ hsize = VGA_PLUS_SIZE_H;
2919+ vsize = VGA_PLUS_SIZE_V;
2920+ break;
2921+
2922+ default:
2923+ hsize = 0;
2924+ vsize = 0;
2925+ err = -1;
2926+ printk(KERN_ERR "ci_sensor_res2size: Resolution 0x%08x"
2927+ "unknown\n", res);
2928+ break;
2929+ }
2930+
2931+ if (h_size != NULL)
2932+ *h_size = hsize;
2933+ if (v_size != NULL)
2934+ *v_size = vsize;
2935+
2936+ return err;
2937+}
2938+#endif
2939--- /dev/null
2940+++ b/drivers/media/video/mrstci/include/ci_va.h
2941@@ -0,0 +1,42 @@
2942+/*
2943+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
2944+ *
2945+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
2946+ *
2947+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
2948+ *
2949+ * This program is free software; you can redistribute it and/or
2950+ * modify it under the terms of the GNU General Public License version
2951+ * 2 as published by the Free Software Foundation.
2952+ *
2953+ * This program is distributed in the hope that it will be useful,
2954+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2955+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2956+ * GNU General Public License for more details.
2957+ *
2958+ * You should have received a copy of the GNU General Public License
2959+ * along with this program; if not, write to the Free Software
2960+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
2961+ * 02110-1301, USA.
2962+ *
2963+ *
2964+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
2965+ */
2966+
2967+/* for buffer sharing between CI and VA */
2968+#ifndef _CI_VA_H
2969+#define _CI_VA_H
2970+
2971+struct ci_frame_info {
2972+ unsigned long frame_id; /* in */
2973+ unsigned int width; /* out */
2974+ unsigned int height; /* out */
2975+ unsigned int stride; /* out */
2976+ unsigned int fourcc; /* out */
2977+ unsigned int offset; /* out */
2978+};
2979+
2980+#define ISP_IOCTL_GET_FRAME_INFO _IOWR('V', 192 + 5, struct ci_frame_info)
2981+
2982+#endif
2983+
2984--- /dev/null
2985+++ b/drivers/media/video/mrstci/include/v4l2_jpg_review.h
2986@@ -0,0 +1,48 @@
2987+/*
2988+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
2989+ *
2990+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
2991+ *
2992+ * This program is free software; you can redistribute it and/or
2993+ * modify it under the terms of the GNU General Public License version
2994+ * 2 as published by the Free Software Foundation.
2995+ *
2996+ * This program is distributed in the hope that it will be useful,
2997+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
2998+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2999+ * GNU General Public License for more details.
3000+ *
3001+ * You should have received a copy of the GNU General Public License
3002+ * along with this program; if not, write to the Free Software
3003+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
3004+ * 02110-1301, USA.
3005+ *
3006+ *
3007+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
3008+ */
3009+
3010+#ifndef __V4L2_JPG_REVIEW_EXT_H
3011+#define __V4L2_JPG_REVIEW_EXT_H
3012+
3013+#include <linux/videodev2.h>
3014+
3015+/*
3016+ * Moorestown JPG image auto review structure and IOCTL.
3017+ */
3018+struct v4l2_jpg_review_buffer{
3019+ __u32 width; /* in: frame width */
3020+ __u32 height; /* in: frame height */
3021+ __u32 pix_fmt; /* in: frame fourcc */
3022+ __u32 jpg_frame; /* in: corresponding jpg frame id */
3023+ __u32 bytesperline; /* out: 0 if not used */
3024+ __u32 frame_size; /* out: frame size */
3025+ __u32 offset; /* out: mmap offset */
3026+};
3027+
3028+#define BASE_VIDIOC_PRIVATE_JPG_REVIEW (BASE_VIDIOC_PRIVATE + 10)
3029+
3030+#define VIDIOC_CREATE_JPG_REVIEW_BUF _IOWR('V', \
3031+ BASE_VIDIOC_PRIVATE_JPG_REVIEW + 1, \
3032+ struct v4l2_jpg_review_buffer)
3033+
3034+#endif
3035--- /dev/null
3036+++ b/drivers/media/video/mrstci/mrstisp/include/def.h
3037@@ -0,0 +1,122 @@
3038+/*
3039+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
3040+ *
3041+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
3042+ *
3043+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
3044+ *
3045+ * This program is free software; you can redistribute it and/or
3046+ * modify it under the terms of the GNU General Public License version
3047+ * 2 as published by the Free Software Foundation.
3048+ *
3049+ * This program is distributed in the hope that it will be useful,
3050+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3051+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3052+ * GNU General Public License for more details.
3053+ *
3054+ * You should have received a copy of the GNU General Public License
3055+ * along with this program; if not, write to the Free Software
3056+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
3057+ * 02110-1301, USA.
3058+ *
3059+ *
3060+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
3061+ */
3062+
3063+#ifndef _DEF_H
3064+#define _DEF_H
3065+
3066+#include <linux/stddef.h>
3067+
3068+#ifndef ON
3069+/* all bits to '1' but prevent "shift overflow" warning */
3070+#define ON -1
3071+#endif
3072+#ifndef OFF
3073+#define OFF 0
3074+#endif
3075+
3076+#ifndef ENABLE
3077+/* all bits to '1' but prevent "shift overflow" warning */
3078+#define ENABLE -1
3079+#endif
3080+#ifndef DISABLE
3081+#define DISABLE 0
3082+#endif
3083+
3084+/* this is crop flag, to enable crop, define it to be 1*/
3085+#define crop_flag 0
3086+
3087+/* this has to be 0, if clauses rely on it */
3088+#define CI_STATUS_SUCCESS 0
3089+/* general failure */
3090+#define CI_STATUS_FAILURE 1
3091+/* feature not supported */
3092+#define CI_STATUS_NOTSUPP 2
3093+/* there's already something going on... */
3094+#define CI_STATUS_BUSY 3
3095+/* operation canceled */
3096+#define CI_STATUS_CANCELED 4
3097+/* out of memory */
3098+#define CI_STATUS_OUTOFMEM 5
3099+/* parameter/value out of range */
3100+#define CI_STATUS_OUTOFRANGE 6
3101+/* feature/subsystem is in idle state */
3102+#define CI_STATUS_IDLE 7
3103+/* handle is wrong */
3104+#define CI_STATUS_WRONG_HANDLE 8
3105+/* the/one/all parameter(s) is a(are) NULL pointer(s) */
3106+#define CI_STATUS_NULL_POINTER 9
3107+/* profile not available */
3108+#define CI_STATUS_NOTAVAILABLE 10
3109+
3110+#ifndef UNUSED_PARAM
3111+#define UNUSED_PARAM(x) ((x) = (x))
3112+#endif
3113+
3114+/* to avoid Lint warnings, use it within const context */
3115+
3116+#ifndef UNUSED_PARAM1
3117+#define UNUSED_PARAM1(x)
3118+#endif
3119+
3120+/*
3121+ * documentation keywords for pointer arguments, to tell the direction of the
3122+ * passing
3123+ */
3124+
3125+#ifndef OUT
3126+/* pointer content is expected to be filled by called function */
3127+#define OUT
3128+#endif
3129+#ifndef IN
3130+/* pointer content contains parameters from the caller */
3131+#define IN
3132+#endif
3133+#ifndef INOUT
3134+/* content is expected to be read and changed */
3135+#define INOUT
3136+#endif
3137+
3138+/* some useful macros */
3139+
3140+#ifndef MIN
3141+#define MIN(x, y) ((x) < (y) ? (x) : (y))
3142+#endif
3143+
3144+#ifndef MAX
3145+#define MAX(x, y) ((x) > (y) ? (x) : (y))
3146+#endif
3147+
3148+#ifndef ABS
3149+#define ABS(val) ((val) < 0 ? -(val) : (val))
3150+#endif
3151+
3152+/*
3153+ * converts a term to a string (two macros are required, never use _VAL2STR()
3154+ * directly)
3155+ */
3156+#define _VAL2STR(x) #x
3157+#define VAL2STR(x) _VAL2STR(x)
3158+
3159+#endif
3160--- /dev/null
3161+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp.h
3162@@ -0,0 +1,279 @@
3163+/*
3164+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
3165+ *
3166+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
3167+ *
3168+ * This program is free software; you can redistribute it and/or
3169+ * modify it under the terms of the GNU General Public License version
3170+ * 2 as published by the Free Software Foundation.
3171+ *
3172+ * This program is distributed in the hope that it will be useful,
3173+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3174+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3175+ * GNU General Public License for more details.
3176+ *
3177+ * You should have received a copy of the GNU General Public License
3178+ * along with this program; if not, write to the Free Software
3179+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
3180+ * 02110-1301, USA.
3181+ *
3182+ *
3183+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
3184+ */
3185+
3186+#ifndef _MRSTISP_H
3187+#define _MRSTISP_H
3188+
3189+#define INTEL_MAJ_VER 0
3190+#define INTEL_MIN_VER 5
3191+#define INTEL_PATCH_VER 0
3192+#define DRIVER_NAME "lnw isp"
3193+#define VID_HARDWARE_INTEL 100
3194+
3195+#define INTEL_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c))
3196+
3197+#define MRST_ISP_REG_MEMORY_MAP 0xFF0E0000
3198+
3199+/* self path maximum width/height, VGA */
3200+#define INTEL_MAX_WIDTH 640
3201+#define INTEL_MAX_HEIGHT 480
3202+
3203+#define INTEL_MIN_WIDTH 32
3204+#define INTEL_MIN_HEIGHT 16
3205+
3206+/* main path maximum widh/height, 5M */
3207+#define INTEL_MAX_WIDTH_MP 2600
3208+#define INTEL_MAX_HEIGHT_MP 2048
3209+
3210+/* image size returned by the driver */
3211+#define INTEL_IMAGE_WIDTH 640
3212+#define INTEL_IMAGE_HEIGHT 480
3213+
3214+/* Default capture queue buffers. */
3215+#define INTEL_CAPTURE_BUFFERS 3
3216+
3217+/* Default capture buffer size. */
3218+#define INTEL_CAPTURE_BUFSIZE PAGE_ALIGN(INTEL_MAX_WIDTH * INTEL_MAX_HEIGHT * 2)
3219+#define INTEL_IMAGE_BUFSIEZE (INTEL_IMAGE_WIDTH * INTEL_IMAGE_HEIGHT * 2)
3220+
3221+#define MAX_KMALLOC_MEM (4*1024*1024)
3222+
3223+#define MEM_SNAPSHOT_MAX_SIZE (1*1024*1024)
3224+
3225+#include <media/v4l2-device.h>
3226+
3227+enum frame_state {
3228+ S_UNUSED = 0, /* unused */
3229+ S_QUEUED, /* ready to capture */
3230+ S_GRABBING, /* in the process of being captured */
3231+ S_DONE, /* finished grabbing, but not been synced yet */
3232+ S_ERROR, /* something bad happened while capturing */
3233+};
3234+
3235+struct frame_info {
3236+ enum frame_state state;
3237+ u32 flags;
3238+};
3239+
3240+struct fifo {
3241+ int front;
3242+ int back;
3243+ int data[INTEL_CAPTURE_BUFFERS + 1];
3244+ struct frame_info info[INTEL_CAPTURE_BUFFERS + 1];
3245+};
3246+
3247+enum mrst_isp_state {
3248+ S_NOTREADY, /* Not yet initialized */
3249+ S_IDLE, /* Just hanging around */
3250+ S_FLAKED, /* Some sort of problem */
3251+ S_STREAMING /* Streaming data */
3252+};
3253+
3254+struct mrst_isp_buffer {
3255+ struct videobuf_buffer vb;
3256+ int fmt_useless;
3257+};
3258+
3259+struct mrst_isp_device {
3260+ struct v4l2_device v4l2_dev;
3261+ /* v4l2 device handler */
3262+ struct video_device *vdev;
3263+
3264+ /* locks this structure */
3265+ struct mutex mutex;
3266+
3267+ /* if the port is open or not */
3268+ int open;
3269+
3270+ /* pci information */
3271+ struct pci_dev *pci_dev;
3272+ unsigned long mb0;
3273+ unsigned long mb0_size;
3274+ unsigned char *regs;
3275+ unsigned long mb1;
3276+ unsigned long mb1_size;
3277+ unsigned char *mb1_va;
3278+ unsigned short vendorID;
3279+ unsigned short deviceID;
3280+ unsigned char revision;
3281+
3282+ /* subdev */
3283+ struct v4l2_subdev *sensor_soc;
3284+ int sensor_soc_index;
3285+ struct v4l2_subdev *sensor_raw;
3286+ int sensor_raw_index;
3287+ struct v4l2_subdev *sensor_curr;
3288+ struct v4l2_subdev *motor;
3289+ struct v4l2_subdev *flash;
3290+ struct i2c_adapter *adapter_sensor;
3291+ struct i2c_adapter *adapter_flash;
3292+
3293+ int streaming;
3294+ int buffer_required;
3295+
3296+ /* interrupt */
3297+ unsigned char int_enable;
3298+ unsigned long int_flag;
3299+ unsigned long interrupt_count;
3300+
3301+ /* frame management */
3302+
3303+ /* allocated memory for km_mmap */
3304+ char *fbuffer;
3305+
3306+ /* virtual address of cap buf */
3307+ char *capbuf;
3308+
3309+ /* physcial address of cap buf */
3310+ u32 capbuf_pa;
3311+
3312+ struct fifo frame_queue;
3313+
3314+ /* current capture frame number */
3315+ int cap_frame;
3316+ /* total frames */
3317+ int num_frames;
3318+
3319+ u32 field_count;
3320+ u32 pixelformat;
3321+ u16 depth;
3322+ u32 bufwidth;
3323+ u32 bufheight;
3324+ u32 frame_size;
3325+ u32 frame_size_used;
3326+
3327+
3328+ enum mrst_isp_state state;
3329+
3330+ /* active mappings*/
3331+ int vmas;
3332+
3333+ /* isp system configuration */
3334+ struct ci_pl_system_config sys_conf;
3335+
3336+ struct completion jpe_complete;
3337+ struct completion mi_complete;
3338+ int irq_stat;
3339+
3340+ spinlock_t lock;
3341+ spinlock_t qlock;
3342+ struct videobuf_buffer *active;
3343+ struct videobuf_buffer *next;
3344+ struct list_head capture;
3345+ u32 streambufs;
3346+ u32 stopbuf;
3347+ u32 stopflag;
3348+};
3349+
3350+struct mrst_isp_fh {
3351+ struct mrst_isp_device *dev;
3352+ struct videobuf_queue vb_q;
3353+ u32 qbuf_flag;
3354+};
3355+
3356+/* viewfinder mode mask */
3357+#define VFFLAG_MODE_MASK 0x0000000F
3358+/*
3359+ * play on complete LCD, but do not use upscaler
3360+ * or small camera resolutions, the picture will be
3361+ * played in the upper left corner)
3362+ */
3363+#define VFFLAG_MODE_FULLLCD_DSONLY 0x00000000
3364+/* display on complete LCD, use upscaler if necessary */
3365+#define VFFLAG_MODE_FULLLCD_USDS 0x00000001
3366+/* display full camera picture with black borders on top and bottom */
3367+#define VFFLAG_MODE_LETTERBOX 0x00000002
3368+/* use the values given by the user (x, y, w, h, keep_aspect) */
3369+#define VFFLAG_MODE_USER 0x00000003
3370+/* hardware RGB conversion */
3371+#define VFFLAG_HWRGB 0x00000010
3372+/* horizontal mirror */
3373+#define VFFLAG_MIRROR 0x00000020
3374+/* use the main path for viewfinding too. */
3375+#define VFFLAG_USE_MAINPATH 0x00000040
3376+/* vertical flipping (mirror) (MARVIN_FEATURE_MI_V3) */
3377+#define VFFLAG_V_FLIP 0x00000100
3378+/* rotation 90 degree counterclockwise (left) (MARVIN_FEATURE_MI_V3) */
3379+#define VFFLAG_ROT90_CCW 0x00000200
3380+
3381+/* abbreviations for local debug control ( level | module ) */
3382+#define DERR (DBG_ERR | DBG_MRV)
3383+#define DWARN (DBG_WARN | DBG_MRV)
3384+#define DINFO (DBG_INFO | DBG_MRV)
3385+
3386+struct ci_isp_rect {
3387+ /* zero based x coordinate of the upper left edge of the
3388+ * rectangle (in pixels)
3389+ */
3390+ int x;
3391+ /* zero based y coordinate of the upper left edge of the
3392+ * rectangle (in pixels)
3393+ */
3394+ int y;
3395+ /* width of the rectangle in pixels */
3396+ int w;
3397+ /* height of the rectangle in pixels */
3398+ int h;
3399+};
3400+
3401+/* the address/size of one region */
3402+struct ci_frame_region {
3403+ unsigned char *phy_addr;
3404+ unsigned int size;
3405+};
3406+
3407+struct ci_frame_addr {
3408+ /*
3409+ * how many regions of the frame, a region is
3410+ * pages with contiguous physical address
3411+ */
3412+ int num_of_regs;
3413+ struct ci_frame_region *regs;
3414+};
3415+
3416+/* type in mrst_camer*/
3417+#define MRST_CAMERA_NONE -1
3418+#define MRST_CAMERA_SOC 0
3419+#define MRST_CAMERA_RAW 1
3420+
3421+struct mrst_camera {
3422+ int type;
3423+ char *name;
3424+ u8 sensor_addr;
3425+ char *motor_name;
3426+ u8 motor_addr;
3427+};
3428+
3429+#define MRST_I2C_BUS_FLASH 0
3430+#define MRST_I2C_BUS_SENSOR 1
3431+
3432+long mrst_isp_vidioc_default(struct file *file, void *fh,
3433+ int cmd, void *arg);
3434+
3435+void mrst_timer_start(void);
3436+
3437+void mrst_timer_stop(void);
3438+
3439+unsigned long mrst_get_micro_sec(void);
3440+
3441+#endif
3442--- /dev/null
3443+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_dp.h
3444@@ -0,0 +1,317 @@
3445+/*
3446+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
3447+ *
3448+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
3449+ *
3450+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
3451+ *
3452+ * This program is free software; you can redistribute it and/or
3453+ * modify it under the terms of the GNU General Public License version
3454+ * 2 as published by the Free Software Foundation.
3455+ *
3456+ * This program is distributed in the hope that it will be useful,
3457+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3458+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3459+ * GNU General Public License for more details.
3460+ *
3461+ * You should have received a copy of the GNU General Public License
3462+ * along with this program; if not, write to the Free Software
3463+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
3464+ * 02110-1301, USA.
3465+ *
3466+ *
3467+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
3468+ */
3469+
3470+
3471+#ifndef _MRV_SLS_H
3472+#define _MRV_SLS_H
3473+
3474+/*
3475+ * simplified datapath and output formatter/resizer adjustment
3476+ * can be used to setup the main and self datapathes in a convenient way.
3477+ */
3478+
3479+/* data path descriptor */
3480+struct ci_isp_datapath_desc {
3481+ /* width of output picture (after scaling) in pixels */
3482+ u16 out_w;
3483+ /* height of output picture (after scaling) in pixels */
3484+ u16 out_h;
3485+ /* how to configure the datapath. An or'ed combination of the */
3486+ u32 flags;
3487+ /* MRV_DPD_xxx defines */
3488+};
3489+
3490+/*
3491+ * possible Frags for the Datapath descriptor general features
3492+ */
3493+
3494+/* disables the datapath */
3495+#define CI_ISP_DPD_DISABLE 0x00000000
3496+/* enables the datapath in general */
3497+#define CI_ISP_DPD_ENABLE 0x00000001
3498+/*
3499+ * the out_w and out_h members will be ignored. and the
3500+ * resize module of the datapath is switched off. Note that
3501+ * the resize module is also needed for croma subsampling
3502+ */
3503+#define CI_ISP_DPD_NORESIZE 0x00000002
3504+/*
3505+ * The input picture from ISP is being cropped to match the
3506+ * aspect ratio of the desired output. If this flag is not
3507+ * set, different scaling factors for X and Y axis
3508+ * may be used.
3509+ */
3510+#define CI_ISP_DPD_KEEPRATIO 0x00000004
3511+/* mirror the output picture (only applicable for self path) data path mode */
3512+#define CI_ISP_DPD_MIRROR 0x00000008
3513+/* mode mask (3 bits) */
3514+#define CI_ISP_DPD_MODE_MASK 0x00000070
3515+/* 16(12) bit raw data from ISP block (only applicable for main path) */
3516+#define CI_ISP_DPD_MODE_ISPRAW_16B 0x00000000
3517+/* separated Y, Cb and Cr data from ISP block */
3518+#define CI_ISP_DPD_MODE_ISPYC 0x00000010
3519+/* raw data from ISP block (only applicable for main path) */
3520+#define CI_ISP_DPD_MODE_ISPRAW 0x00000020
3521+/* Jpeg encoding with data from ISP block (only applicable for main path) */
3522+#define CI_ISP_DPD_MODE_ISPJPEG 0x00000030
3523+/*
3524+ * YCbCr data from system memory directly routed to the main/self
3525+ * path (DMA-read, only applicable for self path)
3526+ */
3527+#define CI_ISP_DPD_MODE_DMAYC_DIRECT 0x00000040
3528+/*
3529+ * YCbCr data from system memory routed through the main processing
3530+ * chain substituting ISP data (DMA-read)
3531+ */
3532+#define CI_ISP_DPD_MODE_DMAYC_ISP 0x00000050
3533+/*
3534+ * YCbCr data from system memory directly routed to the jpeg encoder
3535+ * (DMA-read, R2B-bufferless encoding, only applicable for main path)
3536+ */
3537+#define CI_ISP_DPD_MODE_DMAJPEG_DIRECT 0x00000060
3538+/*
3539+ * Jpeg encoding with YCbCr data from system memory routed through the
3540+ * main processing chain substituting ISP data (DMA-read, only applicable
3541+ * for main path) top blackline support
3542+ */
3543+#define CI_ISP_DPD_MODE_DMAJPEG_ISP 0x00000070
3544+
3545+/*
3546+ * If set, blacklines at the top of the sensor are
3547+ * shown in the output (if there are any). Note that this
3548+ * will move the window of interest out of the center
3549+ * to the upper border, so especially at configurations
3550+ * with digital zoom, the field of sight is not centered
3551+ * on the optical axis anymore. If the sensor does not deliver
3552+ * blacklines, setting this bit has no effect.
3553+ * additional chroma subsampling (CSS) amount and sample position
3554+ */
3555+#define CI_ISP_DPD_BLACKLINES_TOP 0x00000080
3556+/* horizontal subsampling */
3557+#define CI_ISP_DPD_CSS_H_MASK 0x00000700
3558+/* no horizontal subsampling */
3559+#define CI_ISP_DPD_CSS_H_OFF 0x00000000
3560+/* horizontal subsampling by 2 */
3561+#define CI_ISP_DPD_CSS_H2 0x00000100
3562+/* horizontal subsampling by 4 */
3563+#define CI_ISP_DPD_CSS_H4 0x00000200
3564+/* 2 times horizontal upsampling */
3565+#define CI_ISP_DPD_CSS_HUP2 0x00000500
3566+/* 4 times horizontal upsampling */
3567+#define CI_ISP_DPD_CSS_HUP4 0x00000600
3568+/* vertical subsampling */
3569+#define CI_ISP_DPD_CSS_V_MASK 0x00003800
3570+/* no vertical subsampling */
3571+#define CI_ISP_DPD_CSS_V_OFF 0x00000000
3572+/* vertical subsampling by 2 */
3573+#define CI_ISP_DPD_CSS_V2 0x00000800
3574+/* vertical subsampling by 4 */
3575+#define CI_ISP_DPD_CSS_V4 0x00001000
3576+/* 2 times vertical upsampling */
3577+#define CI_ISP_DPD_CSS_VUP2 0x00002800
3578+/* 4 times vertical upsampling */
3579+#define CI_ISP_DPD_CSS_VUP4 0x00003000
3580+/* apply horizontal chroma phase shift by half the sample distance */
3581+#define CI_ISP_DPD_CSS_HSHIFT 0x00004000
3582+/* apply vertical chroma phase shift by half the sample distance */
3583+#define CI_ISP_DPD_CSS_VSHIFT 0x00008000
3584+
3585+/*
3586+ * Hardware RGB conversion (currly, only supported for self path)
3587+ * output mode mask (3 bits, not all combination used yet)
3588+ */
3589+#define CI_ISP_DPD_HWRGB_MASK 0x00070000
3590+/* no rgb conversion */
3591+#define CI_ISP_DPD_HWRGB_OFF 0x00000000
3592+/* conversion to RGB565 */
3593+#define CI_ISP_DPD_HWRGB_565 0x00010000
3594+/* conversion to RGB666 */
3595+#define CI_ISP_DPD_HWRGB_666 0x00020000
3596+/* conversion to RGB888 */
3597+#define CI_ISP_DPD_HWRGB_888 0x00030000
3598+
3599+#define CI_ISP_DPD_YUV_420 0x00040000
3600+#define CI_ISP_DPD_YUV_422 0x00050000
3601+#define CI_ISP_DPD_YUV_NV12 0x00060000
3602+#define CI_ISP_DPD_YUV_YUYV 0x00070000
3603+/*
3604+ * DMA-read feature input format. (depends on chip derivative if
3605+ * supported for both pathes, self or not at all)
3606+ */
3607+
3608+/* input mode mask (2 bits) */
3609+#define CI_ISP_DPD_DMA_IN_MASK 0x00180000
3610+/* input is YCbCr 422 */
3611+#define CI_ISP_DPD_DMA_IN_422 0x00000000
3612+/* input is YCbCr 444 */
3613+#define CI_ISP_DPD_DMA_IN_444 0x00080000
3614+/* input is YCbCr 420 */
3615+#define CI_ISP_DPD_DMA_IN_420 0x00100000
3616+/* input is YCbCr 411 */
3617+#define CI_ISP_DPD_DMA_IN_411 0x00180000
3618+
3619+/*
3620+ * Upscaling interpolation mode (tells how newly created pixels
3621+ * will be interpolated from the existing ones)
3622+ * Upscaling interpolation mode mask (2 bits, not all combinations
3623+ * used yet)
3624+ */
3625+#define CI_ISP_DPD_UPSCALE_MASK 0x00600000
3626+/* smooth edges, linear interpolation */
3627+#define CI_ISP_DPD_UPSCALE_SMOOTH_LIN 0x00000000
3628+/*
3629+ * sharp edges, no interpolation, just duplicate pixels, creates
3630+ * the typical 'blocky' effect.
3631+ */
3632+#define CI_ISP_DPD_UPSCALE_SHARP 0x00200000
3633+
3634+/*
3635+ * additional luminance phase shift
3636+ * apply horizontal luminance phase shift by half the sample distance
3637+ */
3638+#define CI_ISP_DPD_LUMA_HSHIFT 0x00800000
3639+/* apply vertical luminance phase shift by half the sample distance */
3640+#define CI_ISP_DPD_LUMA_VSHIFT 0x01000000
3641+
3642+/*
3643+ * picture flipping and rotation
3644+ * Note that when combining the flags, the rotation is applied first.
3645+ * This enables to configure all 8 possible orientations
3646+ */
3647+
3648+/* horizontal flipping - same as mirroring */
3649+#define CI_ISP_DPD_H_FLIP CI_ISP_DPD_MIRROR
3650+/* vertical flipping */
3651+#define CI_ISP_DPD_V_FLIP 0x02000000
3652+/* rotation 90 degrees counter-clockwise */
3653+#define CI_ISP_DPD_90DEG_CCW 0x04000000
3654+
3655+/*
3656+ * switch to differentiate between full range of values for YCbCr (0-255)
3657+ * and restricted range (16-235 for Y) (16-240 for CbCr)'
3658+ * if set leads to unrestricted range (0-255) for YCbCr
3659+ * package length of a system interface transfer
3660+ */
3661+#define CI_ISP_DPD_YCBCREXT 0x10000000
3662+/* burst mask (2 bits) */
3663+#define CI_ISP_DPD_BURST_MASK 0x60000000
3664+/* AHB 4 beat burst */
3665+#define CI_ISP_DPD_BURST_4 0x00000000
3666+/* AHB 8 beat burst */
3667+#define CI_ISP_DPD_BURST_8 0x20000000
3668+/* AHB 16 beat burst */
3669+#define CI_ISP_DPD_BURST_16 0x40000000
3670+
3671+/* configures main and self datapathes and scaler for data coming from the
3672+ * ISP */
3673+
3674+
3675+int ci_datapath_isp(const struct ci_pl_system_config *sys_conf,
3676+ const struct ci_sensor_config *isi_config,
3677+ const struct ci_isp_datapath_desc *main,
3678+ const struct ci_isp_datapath_desc *self, int zoom);
3679+
3680+
3681+/*
3682+ * Coordinate transformations: The pixel data coming from the sensor passes
3683+ * through the ISP output formatter where they may be cropped and through
3684+ * the main path scaler where they may be stretched and/or squeezed. Thus,
3685+ * the coordinate systems of input and output are different, but somewhat
3686+ * related. Further, we can do digital zoom, which adds a third coordinate
3687+ * system: the virtual input (e.g. a cropped sensor frame zoomed in to the
3688+ * full sensor frame size. Following routines are intended to transform
3689+ * pixel resp. window positions from one coordinate systen to another.
3690+ * Folloin coordinate systems exist: Cam : original frame coming from the
3691+ * camera VCam : virtual camera; a system in which a cropped original
3692+ * camera frame is up-scaled to the camera frame size. If no digital zoom
3693+ * is to be done, Cam and VCam are identical. Main : output of main path
3694+ * Self : output of self path
3695+ */
3696+/* coordinate transformation from (real) camera coordinate system to main
3697+ * path output */
3698+int ci_transform_cam2_main(
3699+ const struct ci_isp_window *wnd_in,
3700+ struct ci_isp_window *wnd_out
3701+);
3702+/* coordinate transformation from (real) camera coordinate system to self
3703+ * path output */
3704+int ci_transform_cam2_self(
3705+ const struct ci_isp_window *wnd_in,
3706+ struct ci_isp_window *wnd_out
3707+);
3708+/* coordinate transformation from virtual camera to real camera coordinate
3709+ * system */
3710+void ci_transform_vcam2_cam(
3711+ const struct ci_sensor_config *isi_sensor_config,
3712+ const struct ci_isp_window *wnd_in,
3713+ struct ci_isp_window *wnd_out
3714+);
3715+
3716+/*
3717+ * Still image snapshot support
3718+ * The routine re-configures the main path for taking the snapshot. On
3719+ * successful return, the snapshot has been stored in the given memory
3720+ * location. Note that the settings of MARVIN will not be restored.
3721+ */
3722+
3723+/*
3724+ * take the desired snapshot. The type of snapshot (YUV, RAW or JPEG) is
3725+ * determined by the datapath selection bits in ci_isp_datapath_desc::flags.
3726+ * Note that the MARVIN configuration may be changed but will not be
3727+ * restored after the snapshot.
3728+ */
3729+int ci_do_snapshot(
3730+ const struct ci_sensor_config *isi_sensor_config,
3731+ const struct ci_isp_datapath_desc *main,
3732+ int zoom,
3733+ u8 jpeg_compression,
3734+ struct ci_isp_mi_path_conf *isp_mi_path_conf
3735+);
3736+
3737+
3738+/* Initialization of the Bad Pixel Detection and Correction */
3739+int ci_bp_init(
3740+ const struct ci_isp_bp_corr_config *bp_corr_config,
3741+ const struct ci_isp_bp_det_config *bp_det_config
3742+);
3743+/* Bad Pixel Correction */
3744+int ci_bp_correction(void);
3745+/* Disable Bad Pixel Correction and dectection */
3746+int ci_bp_end(const struct ci_isp_bp_corr_config *bp_corr_config);
3747+
3748+/* Capture a whole JPEG snapshot */
3749+u32 ci_jpe_capture(struct mrst_isp_device *intel,
3750+ enum ci_isp_conf_update_time update_time);
3751+int ci_jpe_encode(struct mrst_isp_device *intel,
3752+ enum ci_isp_conf_update_time update_time,
3753+ enum ci_isp_jpe_enc_mode mrv_jpe_encMode);
3754+/* Encode motion JPEG */
3755+int ci_isp_jpe_enc_motion(enum ci_isp_jpe_enc_mode jpe_enc_mode,
3756+ u16 frames_num, u32 *byte_count);
3757+
3758+void ci_isp_set_yc_mode(void);
3759+
3760+/* _MRV_SLS_H */
3761+#endif
3762--- /dev/null
3763+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_hw.h
3764@@ -0,0 +1,245 @@
3765+/*
3766+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
3767+ *
3768+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
3769+ *
3770+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
3771+ *
3772+ * This program is free software; you can redistribute it and/or
3773+ * modify it under the terms of the GNU General Public License version
3774+ * 2 as published by the Free Software Foundation.
3775+ *
3776+ * This program is distributed in the hope that it will be useful,
3777+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
3778+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3779+ * GNU General Public License for more details.
3780+ *
3781+ * You should have received a copy of the GNU General Public License
3782+ * along with this program; if not, write to the Free Software
3783+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
3784+ * 02110-1301, USA.
3785+ *
3786+ *
3787+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
3788+ */
3789+
3790+
3791+#ifndef _MRV_H
3792+#define _MRV_H
3793+
3794+/* move structure definination to ci_isp_common.h */
3795+#include "ci_isp_common.h"
3796+
3797+/*
3798+ * FUNCTIONS
3799+ */
3800+
3801+/* sensor struct related functions */
3802+int ci_isp_bp_write_table(
3803+ const struct ci_sensor_bp_table *bp_table
3804+);
3805+
3806+int ci_isp_bp_read_table(struct ci_sensor_bp_table *bp_table);
3807+
3808+enum ci_isp_path ci_isp_select_path(
3809+ const struct ci_sensor_config *isi_cfg,
3810+ u8 *words_per_pixel
3811+);
3812+
3813+int ci_isp_set_input_aquisition(
3814+ const struct ci_sensor_config *isi_cfg
3815+);
3816+
3817+void ci_isp_set_gamma(
3818+ const struct ci_sensor_gamma_curve *r,
3819+ const struct ci_sensor_gamma_curve *g,
3820+ const struct ci_sensor_gamma_curve *b
3821+);
3822+
3823+int ci_isp_get_wb_meas(struct ci_sensor_awb_mean *awb_mean);
3824+
3825+int ci_isp_set_bp_correction(
3826+ const struct ci_isp_bp_corr_config *bp_corr_config
3827+);
3828+
3829+int ci_isp_set_bp_detection(
3830+ const struct ci_isp_bp_det_config *bp_det_config
3831+);
3832+
3833+
3834+int ci_isp_clear_bp_int(void);
3835+
3836+u32 ci_isp_get_frame_end_irq_mask_dma(void);
3837+
3838+u32 ci_isp_get_frame_end_irq_mask_isp(void);
3839+int ci_isp_wait_for_frame_end(struct mrst_isp_device *intel);
3840+
3841+void ci_isp_set_output_formatter(
3842+ const struct ci_isp_window *window,
3843+ enum ci_isp_conf_update_time update_time
3844+);
3845+
3846+int ci_isp_is_set_config(const struct ci_isp_is_config *is_config);
3847+
3848+int ci_isp_set_data_path(
3849+ enum ci_isp_ycs_chn_mode ycs_chn_mode,
3850+ enum ci_isp_dp_switch dp_switch
3851+);
3852+
3853+void ci_isp_res_set_main_resize(const struct ci_isp_scale *scale,
3854+ enum ci_isp_conf_update_time update_time,
3855+ const struct ci_isp_rsz_lut *rsz_lut
3856+);
3857+
3858+void ci_isp_res_get_main_resize(struct ci_isp_scale *scale);
3859+
3860+void ci_isp_res_set_self_resize(const struct ci_isp_scale *scale,
3861+ enum ci_isp_conf_update_time update_time,
3862+ const struct ci_isp_rsz_lut *rsz_lut
3863+);
3864+
3865+void ci_isp_res_get_self_resize(struct ci_isp_scale *scale);
3866+
3867+int ci_isp_mif_set_main_buffer(
3868+ const struct ci_isp_mi_path_conf *mrv_mi_path_conf,
3869+ enum ci_isp_conf_update_time update_time
3870+);
3871+
3872+int ci_isp_mif_set_self_buffer(
3873+ const struct ci_isp_mi_path_conf *mrv_mi_path_conf,
3874+ enum ci_isp_conf_update_time update_time
3875+);
3876+
3877+int ci_isp_mif_set_dma_buffer(
3878+ const struct ci_isp_mi_path_conf *mrv_mi_path_conf
3879+);
3880+
3881+void ci_isp_mif_disable_all_paths(int perform_wait_for_frame_end);
3882+
3883+int ci_isp_mif_get_main_buffer(
3884+ struct ci_isp_mi_path_conf *mrv_mi_path_conf
3885+);
3886+
3887+int ci_isp_mif_get_self_buffer(
3888+ struct ci_isp_mi_path_conf *mrv_mi_path_conf
3889+);
3890+
3891+int ci_isp_mif_set_path_and_orientation(
3892+ const struct ci_isp_mi_ctrl *mrv_mi_ctrl
3893+);
3894+
3895+int ci_isp_mif_get_path_and_orientation(
3896+ struct ci_isp_mi_ctrl *mrv_mi_ctrl
3897+);
3898+
3899+int ci_isp_mif_set_configuration(
3900+ const struct ci_isp_mi_ctrl *mrv_mi_ctrl,
3901+ const struct ci_isp_mi_path_conf *mrv_mi_mp_path_conf,
3902+ const struct ci_isp_mi_path_conf *mrv_mi_sp_path_conf,
3903+ const struct ci_isp_mi_dma_conf *mrv_mi_dma_conf
3904+);
3905+
3906+int ci_isp_mif_set_dma_config(
3907+ const struct ci_isp_mi_dma_conf *mrv_mi_dma_conf
3908+);
3909+
3910+int ci_isp_mif_get_pixel_per32_bit_of_line(
3911+ u8 *pixel_per32_bit,
3912+ enum ci_isp_mif_col_format mrv_mif_sp_format,
3913+ enum ci_isp_mif_pic_form mrv_mif_pic_form,
3914+ int luminance_buffer
3915+);
3916+
3917+void ci_isp_set_ext_ycmode(void);
3918+
3919+int ci_isp_set_mipi_smia(u32 mode);
3920+
3921+void ci_isp_sml_out_set_path(enum ci_isp_data_path main_path);
3922+
3923+void ci_isp_set_dma_read_mode(
3924+ enum ci_isp_dma_read_mode mode,
3925+ enum ci_isp_conf_update_time update_time
3926+);
3927+
3928+u32 ci_isp_mif_get_byte_cnt(void);
3929+
3930+void ci_isp_start(
3931+ u16 number_of_frames,
3932+ enum ci_isp_conf_update_time update_time
3933+);
3934+
3935+int ci_isp_jpe_init_ex(
3936+ u16 hsize,
3937+ u16 vsize,
3938+ u8 compression_ratio,
3939+ u8 jpe_scale
3940+);
3941+
3942+void ci_isp_reset_interrupt_status(void);
3943+
3944+void ci_isp_get_output_formatter(struct ci_isp_window *window);
3945+
3946+int ci_isp_set_auto_focus(const struct ci_isp_af_config *af_config);
3947+
3948+void ci_isp_get_auto_focus_meas(struct ci_isp_af_meas *af_meas);
3949+
3950+int ci_isp_chk_bp_int_stat(void);
3951+
3952+int ci_isp_bls_get_measured_values(
3953+ struct ci_isp_bls_measured *bls_measured
3954+);
3955+
3956+int ci_isp_get_wb_measConfig(
3957+ struct ci_isp_wb_meas_config *wb_meas_config
3958+);
3959+
3960+void ci_isp_col_set_color_processing(
3961+ const struct ci_isp_color_settings *col
3962+);
3963+
3964+int ci_isp_ie_set_config(const struct ci_isp_ie_config *ie_config);
3965+
3966+int ci_isp_set_ls_correction(struct ci_sensor_ls_corr_config *ls_corr_config);
3967+
3968+int ci_isp_ls_correction_on_off(int ls_corr_on_off);
3969+
3970+int ci_isp_activate_filter(int activate_filter);
3971+
3972+int ci_isp_set_filter_params(u8 noise_reduc_level, u8 sharp_level);
3973+
3974+int ci_isp_bls_set_config(const struct ci_isp_bls_config *bls_config);
3975+
3976+int ci_isp_set_wb_mode(enum ci_isp_awb_mode wb_mode);
3977+
3978+int ci_isp_set_wb_meas_config(
3979+ const struct ci_isp_wb_meas_config *wb_meas_config
3980+);
3981+
3982+int ci_isp_set_wb_auto_hw_config(
3983+ const struct ci_isp_wb_auto_hw_config *wb_auto_hw_config
3984+);
3985+
3986+void ci_isp_init(void);
3987+void ci_isp_off(void);
3988+
3989+void ci_isp_stop(enum ci_isp_conf_update_time update_time);
3990+
3991+void ci_isp_mif_reset_offsets(enum ci_isp_conf_update_time update_time);
3992+
3993+int ci_isp_get_wb_measConfig(
3994+ struct ci_isp_wb_meas_config *wb_meas_config
3995+);
3996+
3997+void ci_isp_set_gamma2(const struct ci_isp_gamma_out_curve *gamma);
3998+
3999+void ci_isp_set_demosaic(
4000+ enum ci_isp_demosaic_mode demosaic_mode,
4001+ u8 demosaic_th
4002+);
4003+
4004+void mrst_isp_disable_interrupt(struct mrst_isp_device *isp);
4005+
4006+void mrst_isp_enable_interrupt(struct mrst_isp_device *isp);
4007+
4008+/* #ifndef _MRV_H */
4009+#endif
4010--- /dev/null
4011+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_isp.h
4012@@ -0,0 +1,42 @@
4013+/*
4014+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
4015+ *
4016+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
4017+ *
4018+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
4019+ *
4020+ * This program is free software; you can redistribute it and/or
4021+ * modify it under the terms of the GNU General Public License version
4022+ * 2 as published by the Free Software Foundation.
4023+ *
4024+ * This program is distributed in the hope that it will be useful,
4025+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4026+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4027+ * GNU General Public License for more details.
4028+ *
4029+ * You should have received a copy of the GNU General Public License
4030+ * along with this program; if not, write to the Free Software
4031+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
4032+ * 02110-1301, USA.
4033+ *
4034+ *
4035+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
4036+ */
4037+#define MRV_MEAN_LUMA_ARR_SIZE_COL 5
4038+#define MRV_MEAN_LUMA_ARR_SIZE_ROW 5
4039+#define MRV_MEAN_LUMA_ARR_SIZE \
4040+ (MRV_MEAN_LUMA_ARR_SIZE_COL*MRV_MEAN_LUMA_ARR_SIZE_ROW)
4041+int ci_isp_meas_exposure_initialize_module(void);
4042+
4043+int ci_isp_meas_exposure_set_config(const struct ci_isp_window *wnd,
4044+ const struct ci_isp_exp_ctrl *isp_exp_ctrl);
4045+int ci_isp_meas_exposure_get_config(struct ci_isp_window *wnd,
4046+ struct ci_isp_exp_ctrl *isp_exp_ctrl);
4047+
4048+int ci_isp_meas_exposure_get_mean_luma_values(
4049+ struct ci_isp_mean_luma *mrv_mean_luma);
4050+int ci_isp_meas_exposure_get_mean_luma_by_num(
4051+ u8 BlockNum, u8 *luma);
4052+int ci_isp_meas_exposure_get_mean_luma_by_pos(
4053+ u8 XPos, u8 YPos, u8 *luma);
4054+int mrst_isp_set_color_conversion_ex(void);
4055--- /dev/null
4056+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_jpe.h
4057@@ -0,0 +1,426 @@
4058+/*
4059+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
4060+ *
4061+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
4062+ *
4063+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
4064+ *
4065+ * This program is free software; you can redistribute it and/or
4066+ * modify it under the terms of the GNU General Public License version
4067+ * 2 as published by the Free Software Foundation.
4068+ *
4069+ * This program is distributed in the hope that it will be useful,
4070+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4071+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4072+ * GNU General Public License for more details.
4073+ *
4074+ * You should have received a copy of the GNU General Public License
4075+ * along with this program; if not, write to the Free Software
4076+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
4077+ * 02110-1301, USA.
4078+ *
4079+ *
4080+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
4081+ */
4082+
4083+#include "mrstisp.h"
4084+
4085+/* DC luma table according to ISO/IEC 10918-1 annex K */
4086+static const u8 ci_isp_dc_luma_table_annex_k[] = {
4087+ 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01,
4088+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
4089+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
4090+ 0x08, 0x09, 0x0a, 0x0b
4091+};
4092+
4093+/* DC chroma table according to ISO/IEC 10918-1 annex K */
4094+static const u8 ci_isp_dc_chroma_table_annex_k[] = {
4095+ 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4096+ 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
4097+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
4098+ 0x08, 0x09, 0x0a, 0x0b
4099+};
4100+
4101+/* AC luma table according to ISO/IEC 10918-1 annex K */
4102+static const u8 ci_isp_ac_luma_table_annex_k[] = {
4103+ 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03,
4104+ 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7d,
4105+ 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
4106+ 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
4107+ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
4108+ 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
4109+ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
4110+ 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
4111+ 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
4112+ 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
4113+ 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
4114+ 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
4115+ 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
4116+ 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
4117+ 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
4118+ 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
4119+ 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
4120+ 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
4121+ 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
4122+ 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
4123+ 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
4124+ 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
4125+ 0xf9, 0xfa
4126+};
4127+
4128+/* AC Chroma table according to ISO/IEC 10918-1 annex K */
4129+static const u8 ci_isp_ac_chroma_table_annex_k[] = {
4130+ 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04,
4131+ 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77,
4132+ 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,
4133+ 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
4134+ 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
4135+ 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
4136+ 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
4137+ 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
4138+ 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
4139+ 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
4140+ 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
4141+ 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
4142+ 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
4143+ 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
4144+ 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
4145+ 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
4146+ 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
4147+ 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
4148+ 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
4149+ 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
4150+ 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
4151+ 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
4152+ 0xf9, 0xfa
4153+};
4154+
4155+/* luma quantization table 75% quality setting */
4156+static const u8 ci_isp_yq_table75_per_cent[] = {
4157+ 0x08, 0x06, 0x06, 0x07, 0x06, 0x05, 0x08, 0x07,
4158+ 0x07, 0x07, 0x09, 0x09, 0x08, 0x0a, 0x0c, 0x14,
4159+ 0x0d, 0x0c, 0x0b, 0x0b, 0x0c, 0x19, 0x12, 0x13,
4160+ 0x0f, 0x14, 0x1d, 0x1a, 0x1f, 0x1e, 0x1d, 0x1a,
4161+ 0x1c, 0x1c, 0x20, 0x24, 0x2e, 0x27, 0x20, 0x22,
4162+ 0x2c, 0x23, 0x1c, 0x1c, 0x28, 0x37, 0x29, 0x2c,
4163+ 0x30, 0x31, 0x34, 0x34, 0x34, 0x1f, 0x27, 0x39,
4164+ 0x3d, 0x38, 0x32, 0x3c, 0x2e, 0x33, 0x34, 0x32
4165+};
4166+
4167+/* chroma quantization table 75% quality setting */
4168+static const u8 ci_isp_uv_qtable75_per_cent[] = {
4169+ 0x09, 0x09, 0x09, 0x0c, 0x0b, 0x0c, 0x18, 0x0d,
4170+ 0x0d, 0x18, 0x32, 0x21, 0x1c, 0x21, 0x32, 0x32,
4171+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
4172+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
4173+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
4174+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
4175+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
4176+ 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32
4177+};
4178+
4179+/*
4180+ * luma quantization table very low compression(about factor 2)
4181+ */
4182+static const u8 ci_isp_yq_table_low_comp1[] = {
4183+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4184+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4185+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4186+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4187+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4188+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4189+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4190+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
4191+};
4192+
4193+/*
4194+ * chroma quantization table very low compression
4195+ * (about factor 2)
4196+ */
4197+static const u8 ci_isp_uv_qtable_low_comp1[] = {
4198+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4199+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4200+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4201+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4202+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4203+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4204+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4205+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
4206+};
4207+
4208+/*
4209+ * The jpg Quantization Tables were parsed by jpeg_parser from
4210+ * jpg images generated by Jasc PaintShopPro.
4211+ *
4212+ */
4213+
4214+/* 01% */
4215+
4216+/* luma quantization table */
4217+static const u8 ci_isp_yq_table01_per_cent[] = {
4218+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4219+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4220+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4221+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4222+ 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x01, 0x01,
4223+ 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02,
4224+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02,
4225+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
4226+};
4227+
4228+/* chroma quantization table */
4229+static const u8 ci_isp_uv_qtable01_per_cent[] = {
4230+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
4231+ 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02,
4232+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4233+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4234+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4235+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4236+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
4237+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02
4238+};
4239+
4240+/* 20% */
4241+
4242+/* luma quantization table */
4243+static const u8 ci_isp_yq_table20_per_cent[] = {
4244+ 0x06, 0x04, 0x05, 0x06, 0x05, 0x04, 0x06, 0x06,
4245+ 0x05, 0x06, 0x07, 0x07, 0x06, 0x08, 0x0a, 0x10,
4246+ 0x0a, 0x0a, 0x09, 0x09, 0x0a, 0x14, 0x0e, 0x0f,
4247+ 0x0c, 0x10, 0x17, 0x14, 0x18, 0x18, 0x17, 0x14,
4248+ 0x16, 0x16, 0x1a, 0x1d, 0x25, 0x1f, 0x1a, 0x1b,
4249+ 0x23, 0x1c, 0x16, 0x16, 0x20, 0x2c, 0x20, 0x23,
4250+ 0x26, 0x27, 0x29, 0x2a, 0x29, 0x19, 0x1f, 0x2d,
4251+ 0x30, 0x2d, 0x28, 0x30, 0x25, 0x28, 0x29, 0x28
4252+};
4253+
4254+/* chroma quantization table */
4255+static const u8 ci_isp_uv_qtable20_per_cent[] = {
4256+ 0x07, 0x07, 0x07, 0x0a, 0x08, 0x0a, 0x13, 0x0a,
4257+ 0x0a, 0x13, 0x28, 0x1a, 0x16, 0x1a, 0x28, 0x28,
4258+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
4259+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
4260+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
4261+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
4262+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28,
4263+ 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28
4264+};
4265+
4266+/* 30% */
4267+
4268+/* luma quantization table */
4269+static const u8 ci_isp_yq_table30_per_cent[] = {
4270+ 0x0a, 0x07, 0x07, 0x08, 0x07, 0x06, 0x0a, 0x08,
4271+ 0x08, 0x08, 0x0b, 0x0a, 0x0a, 0x0b, 0x0e, 0x18,
4272+ 0x10, 0x0e, 0x0d, 0x0d, 0x0e, 0x1d, 0x15, 0x16,
4273+ 0x11, 0x18, 0x23, 0x1f, 0x25, 0x24, 0x22, 0x1f,
4274+ 0x22, 0x21, 0x26, 0x2b, 0x37, 0x2f, 0x26, 0x29,
4275+ 0x34, 0x29, 0x21, 0x22, 0x30, 0x41, 0x31, 0x34,
4276+ 0x39, 0x3b, 0x3e, 0x3e, 0x3e, 0x25, 0x2e, 0x44,
4277+ 0x49, 0x43, 0x3c, 0x48, 0x37, 0x3d, 0x3e, 0x3b
4278+};
4279+
4280+/* chroma quantization table */
4281+static const u8 ci_isp_uv_qtable30_per_cent[] = {
4282+ 0x0a, 0x0b, 0x0b, 0x0e, 0x0d, 0x0e, 0x1c, 0x10,
4283+ 0x10, 0x1c, 0x3b, 0x28, 0x22, 0x28, 0x3b, 0x3b,
4284+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
4285+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
4286+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
4287+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
4288+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
4289+ 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b
4290+};
4291+
4292+
4293+/* 40% */
4294+
4295+/* luma quantization table */
4296+static const u8 ci_isp_yq_table40_per_cent[] = {
4297+ 0x0d, 0x09, 0x0a, 0x0b, 0x0a, 0x08, 0x0d, 0x0b,
4298+ 0x0a, 0x0b, 0x0e, 0x0e, 0x0d, 0x0f, 0x13, 0x20,
4299+ 0x15, 0x13, 0x12, 0x12, 0x13, 0x27, 0x1c, 0x1e,
4300+ 0x17, 0x20, 0x2e, 0x29, 0x31, 0x30, 0x2e, 0x29,
4301+ 0x2d, 0x2c, 0x33, 0x3a, 0x4a, 0x3e, 0x33, 0x36,
4302+ 0x46, 0x37, 0x2c, 0x2d, 0x40, 0x57, 0x41, 0x46,
4303+ 0x4c, 0x4e, 0x52, 0x53, 0x52, 0x32, 0x3e, 0x5a,
4304+ 0x61, 0x5a, 0x50, 0x60, 0x4a, 0x51, 0x52, 0x4f
4305+};
4306+
4307+/* chroma quantization table */
4308+static const u8 ci_isp_uv_qtable40_per_cent[] = {
4309+ 0x0e, 0x0e, 0x0e, 0x13, 0x11, 0x13, 0x26, 0x15,
4310+ 0x15, 0x26, 0x4f, 0x35, 0x2d, 0x35, 0x4f, 0x4f,
4311+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
4312+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
4313+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
4314+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
4315+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f,
4316+ 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f
4317+};
4318+
4319+/* 50% */
4320+
4321+/* luma quantization table */
4322+static const u8 ci_isp_yq_table50_per_cent[] = {
4323+ 0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e,
4324+ 0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28,
4325+ 0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25,
4326+ 0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33,
4327+ 0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44,
4328+ 0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57,
4329+ 0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71,
4330+ 0x79, 0x70, 0x64, 0x78, 0x5c, 0x65, 0x67, 0x63
4331+};
4332+
4333+/* chroma quantization table */
4334+static const u8 ci_isp_uv_qtable50_per_cent[] = {
4335+ 0x11, 0x12, 0x12, 0x18, 0x15, 0x18, 0x2f, 0x1a,
4336+ 0x1a, 0x2f, 0x63, 0x42, 0x38, 0x42, 0x63, 0x63,
4337+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
4338+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
4339+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
4340+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
4341+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63,
4342+ 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63
4343+};
4344+
4345+/* 60% */
4346+
4347+/* luma quantization table */
4348+static const u8 ci_isp_yq_table60_per_cent[] = {
4349+ 0x14, 0x0e, 0x0f, 0x12, 0x0f, 0x0d, 0x14, 0x12,
4350+ 0x10, 0x12, 0x17, 0x15, 0x14, 0x18, 0x1e, 0x32,
4351+ 0x21, 0x1e, 0x1c, 0x1c, 0x1e, 0x3d, 0x2c, 0x2e,
4352+ 0x24, 0x32, 0x49, 0x40, 0x4c, 0x4b, 0x47, 0x40,
4353+ 0x46, 0x45, 0x50, 0x5a, 0x73, 0x62, 0x50, 0x55,
4354+ 0x6d, 0x56, 0x45, 0x46, 0x64, 0x88, 0x65, 0x6d,
4355+ 0x77, 0x7b, 0x81, 0x82, 0x81, 0x4e, 0x60, 0x8d,
4356+ 0x97, 0x8c, 0x7d, 0x96, 0x73, 0x7e, 0x81, 0x7c
4357+};
4358+
4359+/* chroma quantization table */
4360+static const u8 ci_isp_uv_qtable60_per_cent[] = {
4361+ 0x15, 0x17, 0x17, 0x1e, 0x1a, 0x1e, 0x3b, 0x21,
4362+ 0x21, 0x3b, 0x7c, 0x53, 0x46, 0x53, 0x7c, 0x7c,
4363+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
4364+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
4365+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
4366+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
4367+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c,
4368+ 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c, 0x7c
4369+};
4370+
4371+/* 70% */
4372+
4373+/* luma quantization table */
4374+static const u8 ci_isp_yq_table70_per_cent[] = {
4375+ 0x1b, 0x12, 0x14, 0x17, 0x14, 0x11, 0x1b, 0x17,
4376+ 0x16, 0x17, 0x1e, 0x1c, 0x1b, 0x20, 0x28, 0x42,
4377+ 0x2b, 0x28, 0x25, 0x25, 0x28, 0x51, 0x3a, 0x3d,
4378+ 0x30, 0x42, 0x60, 0x55, 0x65, 0x64, 0x5f, 0x55,
4379+ 0x5d, 0x5b, 0x6a, 0x78, 0x99, 0x81, 0x6a, 0x71,
4380+ 0x90, 0x73, 0x5b, 0x5d, 0x85, 0xb5, 0x86, 0x90,
4381+ 0x9e, 0xa3, 0xab, 0xad, 0xab, 0x67, 0x80, 0xbc,
4382+ 0xc9, 0xba, 0xa6, 0xc7, 0x99, 0xa8, 0xab, 0xa4
4383+};
4384+
4385+/* chroma quantization table */
4386+static const u8 ci_isp_uv_qtable70_per_cent[] = {
4387+ 0x1c, 0x1e, 0x1e, 0x28, 0x23, 0x28, 0x4e, 0x2b,
4388+ 0x2b, 0x4e, 0xa4, 0x6e, 0x5d, 0x6e, 0xa4, 0xa4,
4389+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
4390+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
4391+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
4392+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
4393+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4,
4394+ 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4, 0xa4
4395+};
4396+
4397+/* 80% */
4398+
4399+/* luma quantization table */
4400+static const u8 ci_isp_yq_table80_per_cent[] = {
4401+ 0x28, 0x1c, 0x1e, 0x23, 0x1e, 0x19, 0x28, 0x23,
4402+ 0x21, 0x23, 0x2d, 0x2b, 0x28, 0x30, 0x3c, 0x64,
4403+ 0x41, 0x3c, 0x37, 0x37, 0x3c, 0x7b, 0x58, 0x5d,
4404+ 0x49, 0x64, 0x91, 0x80, 0x99, 0x96, 0x8f, 0x80,
4405+ 0x8c, 0x8a, 0xa0, 0xb4, 0xe6, 0xc3, 0xa0, 0xaa,
4406+ 0xda, 0xad, 0x8a, 0x8c, 0xc8, 0xff, 0xcb, 0xda,
4407+ 0xee, 0xf5, 0xff, 0xff, 0xff, 0x9b, 0xc1, 0xff,
4408+ 0xff, 0xff, 0xfa, 0xff, 0xe6, 0xfd, 0xff, 0xf8
4409+};
4410+
4411+/* chroma quantization table */
4412+static const u8 ci_isp_uv_qtable80_per_cent[] = {
4413+ 0x2b, 0x2d, 0x2d, 0x3c, 0x35, 0x3c, 0x76, 0x41,
4414+ 0x41, 0x76, 0xf8, 0xa5, 0x8c, 0xa5, 0xf8, 0xf8,
4415+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
4416+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
4417+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
4418+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
4419+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8,
4420+ 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8
4421+};
4422+
4423+/* 90% */
4424+
4425+/* luma quantization table */
4426+static const u8 ci_isp_yq_table90_per_cent[] = {
4427+ 0x50, 0x37, 0x3c, 0x46, 0x3c, 0x32, 0x50, 0x46,
4428+ 0x41, 0x46, 0x5a, 0x55, 0x50, 0x5f, 0x78, 0xc8,
4429+ 0x82, 0x78, 0x6e, 0x6e, 0x78, 0xf5, 0xaf, 0xb9,
4430+ 0x91, 0xc8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4431+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4432+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4433+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4434+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4435+};
4436+
4437+/* chroma quantization table */
4438+static const u8 ci_isp_uv_qtable90_per_cent[] = {
4439+ 0x55, 0x5a, 0x5a, 0x78, 0x69, 0x78, 0xeb, 0x82,
4440+ 0x82, 0xeb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4441+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4442+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4443+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4444+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4445+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4446+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4447+};
4448+
4449+/* 99% */
4450+
4451+/* luma quantization table */
4452+static const u8 ci_isp_yq_table99_per_cent[] = {
4453+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4454+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4455+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4456+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4457+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4458+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4459+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4460+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4461+};
4462+
4463+/* chroma quantization table */
4464+static const u8 ci_isp_uv_qtable99_per_cent[] = {
4465+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4466+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4467+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4468+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4469+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4470+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4471+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4472+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4473+};
4474+
4475+int ci_isp_wait_for_vsyncHelper(void);
4476+void ci_isp_jpe_set_tables(u8 compression_ratio);
4477+void ci_isp_jpe_select_tables(void);
4478+void ci_isp_jpe_set_config(u16 hsize, u16 vsize, int jpe_scale);
4479+int ci_isp_jpe_generate_header(struct mrst_isp_device *intel, u8 header_mode);
4480+void ci_isp_jpe_prep_enc(enum ci_isp_jpe_enc_mode jpe_enc_mode);
4481+int ci_isp_jpe_wait_for_header_gen_done(struct mrst_isp_device *intel);
4482+int ci_isp_jpe_wait_for_encode_done(struct mrst_isp_device *intel);
4483+
4484--- /dev/null
4485+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_reg.h
4486@@ -0,0 +1,4698 @@
4487+/*
4488+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
4489+ *
4490+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
4491+ *
4492+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
4493+ *
4494+ * This program is free software; you can redistribute it and/or
4495+ * modify it under the terms of the GNU General Public License version
4496+ * 2 as published by the Free Software Foundation.
4497+ *
4498+ * This program is distributed in the hope that it will be useful,
4499+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
4500+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4501+ * GNU General Public License for more details.
4502+ *
4503+ * You should have received a copy of the GNU General Public License
4504+ * along with this program; if not, write to the Free Software
4505+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
4506+ * 02110-1301, USA.
4507+ *
4508+ *
4509+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
4510+ */
4511+
4512+#ifndef _MRV_PRIV_H
4513+#define _MRV_PRIV_H
4514+
4515+
4516+#define MRV_ISP_GAMMA_R_Y_ARR_SIZE 17
4517+#define MRV_ISP_GAMMA_G_Y_ARR_SIZE 17
4518+#define MRV_ISP_GAMMA_B_Y_ARR_SIZE 17
4519+#define MRV_ISP_CT_COEFF_ARR_SIZE 9
4520+#define MRV_ISP_GAMMA_OUT_Y_ARR_SIZE 17
4521+#define MRV_ISP_BP_NEW_TABLE_ARR_SIZE 8
4522+#define MRV_ISP_HIST_BIN_ARR_SIZE 16
4523+
4524+struct isp_register {
4525+ u32 vi_ccl;
4526+ u32 vi_custom_reg1;
4527+ u32 vi_id;
4528+ u32 vi_custom_reg2;
4529+ u32 vi_iccl;
4530+ u32 vi_ircl;
4531+ u32 vi_dpcl;
4532+
4533+ u32 notused_mrvbase1;
4534+
4535+
4536+ u32 notused_mrvbase2[(0x200 - 0x20) / 4];
4537+
4538+ u32 img_eff_ctrl;
4539+ u32 img_eff_color_sel;
4540+ u32 img_eff_mat_1;
4541+ u32 img_eff_mat_2;
4542+ u32 img_eff_mat_3;
4543+ u32 img_eff_mat_4;
4544+ u32 img_eff_mat_5;
4545+ u32 img_eff_tint;
4546+ u32 img_eff_ctrl_shd;
4547+ u32 notused_imgeff[(0x300 - 0x224) / 4];
4548+
4549+
4550+ u32 super_imp_ctrl;
4551+ u32 super_imp_offset_x;
4552+ u32 super_imp_offset_y;
4553+ u32 super_imp_color_y;
4554+ u32 super_imp_color_cb;
4555+ u32 super_imp_color_cr;
4556+ u32 notused_simp[(0x400 - 0x318) / 4];
4557+
4558+ u32 isp_ctrl;
4559+ u32 isp_acq_prop;
4560+ u32 isp_acq_h_offs;
4561+ u32 isp_acq_v_offs;
4562+ u32 isp_acq_h_size;
4563+ u32 isp_acq_v_size;
4564+ u32 isp_acq_nr_frames;
4565+ u32 isp_gamma_dx_lo;
4566+ u32 isp_gamma_dx_hi;
4567+ u32 isp_gamma_r_y[MRV_ISP_GAMMA_R_Y_ARR_SIZE];
4568+ u32 isp_gamma_g_y[MRV_ISP_GAMMA_G_Y_ARR_SIZE];
4569+ u32 isp_gamma_b_y[MRV_ISP_GAMMA_B_Y_ARR_SIZE];
4570+
4571+
4572+ u32 notused_ispbls1[(0x510 - 0x4F0) / 4];
4573+
4574+ u32 isp_awb_prop;
4575+ u32 isp_awb_h_offs;
4576+ u32 isp_awb_v_offs;
4577+ u32 isp_awb_h_size;
4578+ u32 isp_awb_v_size;
4579+ u32 isp_awb_frames;
4580+ u32 isp_awb_ref;
4581+ u32 isp_awb_thresh;
4582+
4583+ u32 notused_ispawb2[(0x538-0x530)/4];
4584+
4585+ u32 isp_awb_gain_g;
4586+ u32 isp_awb_gain_rb;
4587+
4588+ u32 isp_awb_white_cnt;
4589+ u32 isp_awb_mean;
4590+
4591+ u32 notused_ispae[(0x570 - 0x548) / 4];
4592+ u32 isp_cc_coeff_0;
4593+ u32 isp_cc_coeff_1;
4594+ u32 isp_cc_coeff_2;
4595+ u32 isp_cc_coeff_3;
4596+ u32 isp_cc_coeff_4;
4597+ u32 isp_cc_coeff_5;
4598+ u32 isp_cc_coeff_6;
4599+ u32 isp_cc_coeff_7;
4600+ u32 isp_cc_coeff_8;
4601+
4602+ u32 isp_out_h_offs;
4603+ u32 isp_out_v_offs;
4604+ u32 isp_out_h_size;
4605+ u32 isp_out_v_size;
4606+
4607+
4608+ u32 isp_demosaic;
4609+ u32 isp_flags_shd;
4610+
4611+ u32 isp_out_h_offs_shd;
4612+ u32 isp_out_v_offs_shd;
4613+ u32 isp_out_h_size_shd;
4614+ u32 isp_out_v_size_shd;
4615+
4616+
4617+ u32 isp_imsc;
4618+ u32 isp_ris;
4619+ u32 isp_mis;
4620+ u32 isp_icr;
4621+ u32 isp_isr;
4622+
4623+ u32 isp_ct_coeff[MRV_ISP_CT_COEFF_ARR_SIZE];
4624+
4625+ u32 isp_gamma_out_mode;
4626+ u32 isp_gamma_out_y[MRV_ISP_GAMMA_OUT_Y_ARR_SIZE];
4627+
4628+
4629+ u32 isp_err;
4630+ u32 isp_err_clr;
4631+
4632+
4633+ u32 isp_frame_count;
4634+
4635+ u32 isp_ct_offset_r;
4636+ u32 isp_ct_offset_g;
4637+ u32 isp_ct_offset_b;
4638+ u32 notused_ispctoffs[(0x660 - 0x654) / 4];
4639+
4640+
4641+ u32 isp_flash_cmd;
4642+ u32 isp_flash_config;
4643+ u32 isp_flash_prediv;
4644+ u32 isp_flash_delay;
4645+ u32 isp_flash_time;
4646+ u32 isp_flash_maxp;
4647+ u32 notused_ispflash[(0x680 - 0x678) / 4];
4648+
4649+
4650+ u32 isp_sh_ctrl;
4651+ u32 isp_sh_prediv;
4652+ u32 isp_sh_delay;
4653+ u32 isp_sh_time;
4654+ u32 notused_ispsh[(0x800 - 0x690) / 4];
4655+
4656+ u32 c_proc_ctrl;
4657+ u32 c_proc_contrast;
4658+ u32 c_proc_brightness;
4659+ u32 c_proc_saturation;
4660+ u32 c_proc_hue;
4661+ u32 notused_cproc[(0xC00 - 0x814) / 4];
4662+
4663+ u32 mrsz_ctrl;
4664+ u32 mrsz_scale_hy;
4665+ u32 mrsz_scale_hcb;
4666+ u32 mrsz_scale_hcr;
4667+ u32 mrsz_scale_vy;
4668+ u32 mrsz_scale_vc;
4669+ u32 mrsz_phase_hy;
4670+ u32 mrsz_phase_hc;
4671+ u32 mrsz_phase_vy;
4672+ u32 mrsz_phase_vc;
4673+ u32 mrsz_scale_lut_addr;
4674+ u32 mrsz_scale_lut;
4675+ u32 mrsz_ctrl_shd;
4676+ u32 mrsz_scale_hy_shd;
4677+ u32 mrsz_scale_hcb_shd;
4678+ u32 mrsz_scale_hcr_shd;
4679+ u32 mrsz_scale_vy_shd;
4680+ u32 mrsz_scale_vc_shd;
4681+ u32 mrsz_phase_hy_shd;
4682+ u32 mrsz_phase_hc_shd;
4683+ u32 mrsz_phase_vy_shd;
4684+ u32 mrsz_phase_vc_shd;
4685+ u32 notused_mrsz[(0x1000 - 0x0C58) / 4];
4686+
4687+ u32 srsz_ctrl;
4688+ u32 srsz_scale_hy;
4689+ u32 srsz_scale_hcb;
4690+ u32 srsz_scale_hcr;
4691+ u32 srsz_scale_vy;
4692+ u32 srsz_scale_vc;
4693+ u32 srsz_phase_hy;
4694+ u32 srsz_phase_hc;
4695+ u32 srsz_phase_vy;
4696+ u32 srsz_phase_vc;
4697+ u32 srsz_scale_lut_addr;
4698+ u32 srsz_scale_lut;
4699+ u32 srsz_ctrl_shd;
4700+ u32 srsz_scale_hy_shd;
4701+ u32 srsz_scale_hcb_shd;
4702+ u32 srsz_scale_hcr_shd;
4703+ u32 srsz_scale_vy_shd;
4704+ u32 srsz_scale_vc_shd;
4705+ u32 srsz_phase_hy_shd;
4706+ u32 srsz_phase_hc_shd;
4707+ u32 srsz_phase_vy_shd;
4708+ u32 srsz_phase_vc_shd;
4709+ u32 notused_srsz[(0x1400 - 0x1058) / 4];
4710+
4711+ u32 mi_ctrl;
4712+ u32 mi_init;
4713+ u32 mi_mp_y_base_ad_init;
4714+ u32 mi_mp_y_size_init;
4715+ u32 mi_mp_y_offs_cnt_init;
4716+ u32 mi_mp_y_offs_cnt_start;
4717+ u32 mi_mp_y_irq_offs_init;
4718+ u32 mi_mp_cb_base_ad_init;
4719+ u32 mi_mp_cb_size_init;
4720+ u32 mi_mp_cb_offs_cnt_init;
4721+ u32 mi_mp_cb_offs_cnt_start;
4722+ u32 mi_mp_cr_base_ad_init;
4723+ u32 mi_mp_cr_size_init;
4724+ u32 mi_mp_cr_offs_cnt_init;
4725+ u32 mi_mp_cr_offs_cnt_start;
4726+ u32 mi_sp_y_base_ad_init;
4727+ u32 mi_sp_y_size_init;
4728+ u32 mi_sp_y_offs_cnt_init;
4729+ u32 mi_sp_y_offs_cnt_start;
4730+ u32 mi_sp_y_llength;
4731+ u32 mi_sp_cb_base_ad_init;
4732+ u32 mi_sp_cb_size_init;
4733+ u32 mi_sp_cb_offs_cnt_init;
4734+ u32 mi_sp_cb_offs_cnt_start;
4735+ u32 mi_sp_cr_base_ad_init;
4736+ u32 mi_sp_cr_size_init;
4737+ u32 mi_sp_cr_offs_cnt_init;
4738+ u32 mi_sp_cr_offs_cnt_start;
4739+ u32 mi_byte_cnt;
4740+ u32 mi_ctrl_shd;
4741+ u32 mi_mp_y_base_ad_shd;
4742+ u32 mi_mp_y_size_shd;
4743+ u32 mi_mp_y_offs_cnt_shd;
4744+ u32 mi_mp_y_irq_offs_shd;
4745+ u32 mi_mp_cb_base_ad_shd;
4746+ u32 mi_mp_cb_size_shd;
4747+ u32 mi_mp_cb_offs_cnt_shd;
4748+ u32 mi_mp_cr_base_ad_shd;
4749+ u32 mi_mp_cr_size_shd;
4750+ u32 mi_mp_cr_offs_cnt_shd;
4751+ u32 mi_sp_y_base_ad_shd;
4752+ u32 mi_sp_y_size_shd;
4753+ u32 mi_sp_y_offs_cnt_shd;
4754+
4755+ u32 notused_mi1;
4756+
4757+ u32 mi_sp_cb_base_ad_shd;
4758+ u32 mi_sp_cb_size_shd;
4759+ u32 mi_sp_cb_offs_cnt_shd;
4760+ u32 mi_sp_cr_base_ad_shd;
4761+ u32 mi_sp_cr_size_shd;
4762+ u32 mi_sp_cr_offs_cnt_shd;
4763+ u32 mi_dma_y_pic_start_ad;
4764+ u32 mi_dma_y_pic_width;
4765+ u32 mi_dma_y_llength;
4766+ u32 mi_dma_y_pic_size;
4767+ u32 mi_dma_cb_pic_start_ad;
4768+ u32 notused_mi2[(0x14E8 - 0x14DC) / 4];
4769+ u32 mi_dma_cr_pic_start_ad;
4770+ u32 notused_mi3[(0x14F8 - 0x14EC) / 4];
4771+ u32 mi_imsc;
4772+ u32 mi_ris;
4773+ u32 mi_mis;
4774+ u32 mi_icr;
4775+ u32 mi_isr;
4776+ u32 mi_status;
4777+ u32 mi_status_clr;
4778+ u32 mi_sp_y_pic_width;
4779+ u32 mi_sp_y_pic_height;
4780+ u32 mi_sp_y_pic_size;
4781+ u32 mi_dma_ctrl;
4782+ u32 mi_dma_start;
4783+ u32 mi_dma_status;
4784+ u32 notused_mi6[(0x1800 - 0x152C) / 4];
4785+ u32 jpe_gen_header;
4786+ u32 jpe_encode;
4787+
4788+ u32 jpe_init;
4789+
4790+ u32 jpe_y_scale_en;
4791+ u32 jpe_cbcr_scale_en;
4792+ u32 jpe_table_flush;
4793+ u32 jpe_enc_hsize;
4794+ u32 jpe_enc_vsize;
4795+ u32 jpe_pic_format;
4796+ u32 jpe_restart_interval;
4797+ u32 jpe_tq_y_select;
4798+ u32 jpe_tq_u_select;
4799+ u32 jpe_tq_v_select;
4800+ u32 jpe_dc_table_select;
4801+ u32 jpe_ac_table_select;
4802+ u32 jpe_table_data;
4803+ u32 jpe_table_id;
4804+ u32 jpe_tac0_len;
4805+ u32 jpe_tdc0_len;
4806+ u32 jpe_tac1_len;
4807+ u32 jpe_tdc1_len;
4808+ u32 notused_jpe2;
4809+ u32 jpe_encoder_busy;
4810+ u32 jpe_header_mode;
4811+ u32 jpe_encode_mode;
4812+ u32 jpe_debug;
4813+ u32 jpe_error_imr;
4814+ u32 jpe_error_ris;
4815+ u32 jpe_error_mis;
4816+ u32 jpe_error_icr;
4817+ u32 jpe_error_isr;
4818+ u32 jpe_status_imr;
4819+ u32 jpe_status_ris;
4820+ u32 jpe_status_mis;
4821+ u32 jpe_status_icr;
4822+ u32 jpe_status_isr;
4823+ u32 notused_jpe3[(0x1A00 - 0x1890) / 4];
4824+
4825+ u32 smia_ctrl;
4826+ u32 smia_status;
4827+ u32 smia_imsc;
4828+ u32 smia_ris;
4829+ u32 smia_mis;
4830+ u32 smia_icr;
4831+ u32 smia_isr;
4832+ u32 smia_data_format_sel;
4833+ u32 smia_sof_emb_data_lines;
4834+
4835+ u32 smia_emb_hstart;
4836+ u32 smia_emb_hsize;
4837+ u32 smia_emb_vstart;
4838+
4839+ u32 smia_num_lines;
4840+ u32 smia_emb_data_fifo;
4841+
4842+ u32 smia_fifo_fill_level;
4843+ u32 notused_smia2[(0x1A40 - 0x1A3C) / 4];
4844+
4845+ u32 notused_smia3[(0x1A60 - 0x1A40) / 4];
4846+ u32 notused_smia4[(0x1C00 - 0x1A60) / 4];
4847+
4848+
4849+ u32 mipi_ctrl;
4850+ u32 mipi_status;
4851+ u32 mipi_imsc;
4852+ u32 mipi_ris;
4853+ u32 mipi_mis;
4854+ u32 mipi_icr;
4855+ u32 mipi_isr;
4856+ u32 mipi_cur_data_id;
4857+ u32 mipi_img_data_sel;
4858+ u32 mipi_add_data_sel_1;
4859+ u32 mipi_add_data_sel_2;
4860+ u32 mipi_add_data_sel_3;
4861+ u32 mipi_add_data_sel_4;
4862+ u32 mipi_add_data_fifo;
4863+ u32 mipi_add_data_fill_level;
4864+ u32 notused_mipi[(0x2000 - 0x1C3C) / 4];
4865+
4866+
4867+ u32 isp_afm_ctrl;
4868+ u32 isp_afm_lt_a;
4869+ u32 isp_afm_rb_a;
4870+ u32 isp_afm_lt_b;
4871+ u32 isp_afm_rb_b;
4872+ u32 isp_afm_lt_c;
4873+ u32 isp_afm_rb_c;
4874+ u32 isp_afm_thres;
4875+ u32 isp_afm_var_shift;
4876+ u32 isp_afm_sum_a;
4877+ u32 isp_afm_sum_b;
4878+ u32 isp_afm_sum_c;
4879+ u32 isp_afm_lum_a;
4880+ u32 isp_afm_lum_b;
4881+ u32 isp_afm_lum_c;
4882+ u32 notused_ispafm[(0x2100 - 0x203C) / 4];
4883+
4884+
4885+ u32 isp_bp_ctrl;
4886+ u32 isp_bp_cfg1;
4887+ u32 isp_bp_cfg2;
4888+ u32 isp_bp_number;
4889+ u32 isp_bp_table_addr;
4890+ u32 isp_bp_table_data;
4891+ u32 isp_bp_new_number;
4892+ u32 isp_bp_new_table[MRV_ISP_BP_NEW_TABLE_ARR_SIZE];
4893+
4894+ u32 notused_ispbp[(0x2200 - 0x213C) / 4];
4895+
4896+
4897+ u32 isp_lsc_ctrl;
4898+ u32 isp_lsc_r_table_addr;
4899+ u32 isp_lsc_g_table_addr;
4900+ u32 isp_lsc_b_table_addr;
4901+ u32 isp_lsc_r_table_data;
4902+ u32 isp_lsc_g_table_data;
4903+ u32 isp_lsc_b_table_data;
4904+ u32 notused_isplsc1;
4905+ u32 isp_lsc_xgrad_01;
4906+ u32 isp_lsc_xgrad_23;
4907+ u32 isp_lsc_xgrad_45;
4908+ u32 isp_lsc_xgrad_67;
4909+ u32 isp_lsc_ygrad_01;
4910+ u32 isp_lsc_ygrad_23;
4911+ u32 isp_lsc_ygrad_45;
4912+ u32 isp_lsc_ygrad_67;
4913+ u32 isp_lsc_xsize_01;
4914+ u32 isp_lsc_xsize_23;
4915+ u32 isp_lsc_xsize_45;
4916+ u32 isp_lsc_xsize_67;
4917+ u32 isp_lsc_ysize_01;
4918+ u32 isp_lsc_ysize_23;
4919+ u32 isp_lsc_ysize_45;
4920+ u32 isp_lsc_ysize_67;
4921+ u32 notused_isplsc2[(0x2300 - 0x2260) / 4];
4922+
4923+
4924+ u32 isp_is_ctrl;
4925+ u32 isp_is_recenter;
4926+
4927+ u32 isp_is_h_offs;
4928+ u32 isp_is_v_offs;
4929+ u32 isp_is_h_size;
4930+ u32 isp_is_v_size;
4931+
4932+ u32 isp_is_max_dx;
4933+ u32 isp_is_max_dy;
4934+ u32 isp_is_displace;
4935+
4936+ u32 isp_is_h_offs_shd;
4937+ u32 isp_is_v_offs_shd;
4938+ u32 isp_is_h_size_shd;
4939+ u32 isp_is_v_size_shd;
4940+ u32 notused_ispis4[(0x2400 - 0x2334) / 4];
4941+
4942+ u32 isp_hist_prop;
4943+ u32 isp_hist_h_offs;
4944+ u32 isp_hist_v_offs;
4945+ u32 isp_hist_h_size;
4946+ u32 isp_hist_v_size;
4947+ u32 isp_hist_bin[MRV_ISP_HIST_BIN_ARR_SIZE];
4948+ u32 notused_isphist[(0x2500-0x2454)/4];
4949+
4950+ u32 isp_filt_mode;
4951+ u32 _notused_28[(0x2528 - 0x2504) / 4];
4952+ u32 isp_filt_thresh_bl0;
4953+ u32 isp_filt_thresh_bl1;
4954+ u32 isp_filt_thresh_sh0;
4955+ u32 isp_filt_thresh_sh1;
4956+ u32 isp_filt_lum_weight;
4957+ u32 isp_filt_fac_sh1;
4958+ u32 isp_filt_fac_sh0;
4959+ u32 isp_filt_fac_mid;
4960+ u32 isp_filt_fac_bl0;
4961+ u32 isp_filt_fac_bl1;
4962+ u32 notused_ispfilt[(0x2580 - 0x2550) / 4];
4963+
4964+ u32 notused_ispcac[(0x2600 - 0x2580) / 4];
4965+
4966+ u32 isp_exp_ctrl;
4967+ u32 isp_exp_h_offset;
4968+ u32 isp_exp_v_offset;
4969+ u32 isp_exp_h_size;
4970+ u32 isp_exp_v_size;
4971+ u32 isp_exp_mean_00;
4972+ u32 isp_exp_mean_10;
4973+ u32 isp_exp_mean_20;
4974+ u32 isp_exp_mean_30;
4975+ u32 isp_exp_mean_40;
4976+ u32 isp_exp_mean_01;
4977+ u32 isp_exp_mean_11;
4978+ u32 isp_exp_mean_21;
4979+ u32 isp_exp_mean_31;
4980+ u32 isp_exp_mean_41;
4981+ u32 isp_exp_mean_02;
4982+ u32 isp_exp_mean_12;
4983+ u32 isp_exp_mean_22;
4984+ u32 isp_exp_mean_32;
4985+ u32 isp_exp_mean_42;
4986+ u32 isp_exp_mean_03;
4987+ u32 isp_exp_mean_13;
4988+ u32 isp_exp_mean_23;
4989+ u32 isp_exp_mean_33;
4990+ u32 isp_exp_mean_43;
4991+ u32 isp_exp_mean_04;
4992+ u32 isp_exp_mean_14;
4993+ u32 isp_exp_mean_24;
4994+ u32 isp_exp_mean_34;
4995+ u32 isp_exp_mean_44;
4996+ u32 notused_ispexp[(0x2700 - 0x2678) / 4];
4997+
4998+ u32 isp_bls_ctrl;
4999+ u32 isp_bls_samples;
5000+ u32 isp_bls_h1_start;
5001+ u32 isp_bls_h1_stop;
5002+ u32 isp_bls_v1_start;
5003+ u32 isp_bls_v1_stop;
5004+ u32 isp_bls_h2_start;
5005+ u32 isp_bls_h2_stop;
5006+ u32 isp_bls_v2_start;
5007+ u32 isp_bls_v2_stop;
5008+ u32 isp_bls_a_fixed;
5009+ u32 isp_bls_b_fixed;
5010+ u32 isp_bls_c_fixed;
5011+ u32 isp_bls_d_fixed;
5012+ u32 isp_bls_a_measured;
5013+ u32 isp_bls_b_measured;
5014+ u32 isp_bls_c_measured;
5015+ u32 isp_bls_d_measured;
5016+ u32 notused_ispbls2[(0x2800 - 0x2748) / 4];
5017+
5018+
5019+};
5020+
5021+
5022+
5023+
5024+
5025+
5026+
5027+#define MRV_VI_CCLFDIS
5028+#define MRV_VI_CCLFDIS_MASK 0x00000004
5029+#define MRV_VI_CCLFDIS_SHIFT 2
5030+#define MRV_VI_CCLFDIS_ENABLE 0
5031+#define MRV_VI_CCLFDIS_DISABLE 1
5032+
5033+#define MRV_VI_CCLDISS
5034+#define MRV_VI_CCLDISS_MASK 0x00000002
5035+#define MRV_VI_CCLDISS_SHIFT 1
5036+
5037+#define MRV_REV_ID
5038+#define MRV_REV_ID_MASK 0xFFFFFFFF
5039+#define MRV_REV_ID_SHIFT 0
5040+
5041+#define MRV_VI_MIPI_CLK_ENABLE
5042+#define MRV_VI_MIPI_CLK_ENABLE_MASK 0x00000800
5043+#define MRV_VI_MIPI_CLK_ENABLE_SHIFT 11
5044+
5045+
5046+#define MRV_VI_SMIA_CLK_ENABLE
5047+#define MRV_VI_SMIA_CLK_ENABLE_MASK 0x00000400
5048+#define MRV_VI_SMIA_CLK_ENABLE_SHIFT 10
5049+#define MRV_VI_SIMP_CLK_ENABLE
5050+#define MRV_VI_SIMP_CLK_ENABLE_MASK 0x00000200
5051+#define MRV_VI_SIMP_CLK_ENABLE_SHIFT 9
5052+
5053+#define MRV_VI_IE_CLK_ENABLE
5054+#define MRV_VI_IE_CLK_ENABLE_MASK 0x00000100
5055+#define MRV_VI_IE_CLK_ENABLE_SHIFT 8
5056+
5057+#define MRV_VI_EMP_CLK_ENABLE_MASK 0
5058+#define MRV_VI_MI_CLK_ENABLE
5059+#define MRV_VI_MI_CLK_ENABLE_MASK 0x00000040
5060+#define MRV_VI_MI_CLK_ENABLE_SHIFT 6
5061+
5062+#define MRV_VI_JPEG_CLK_ENABLE
5063+#define MRV_VI_JPEG_CLK_ENABLE_MASK 0x00000020
5064+#define MRV_VI_JPEG_CLK_ENABLE_SHIFT 5
5065+#define MRV_VI_SRSZ_CLK_ENABLE
5066+#define MRV_VI_SRSZ_CLK_ENABLE_MASK 0x00000010
5067+#define MRV_VI_SRSZ_CLK_ENABLE_SHIFT 4
5068+
5069+#define MRV_VI_MRSZ_CLK_ENABLE
5070+#define MRV_VI_MRSZ_CLK_ENABLE_MASK 0x00000008
5071+#define MRV_VI_MRSZ_CLK_ENABLE_SHIFT 3
5072+#define MRV_VI_CP_CLK_ENABLE
5073+#define MRV_VI_CP_CLK_ENABLE_MASK 0x00000002
5074+#define MRV_VI_CP_CLK_ENABLE_SHIFT 1
5075+#define MRV_VI_ISP_CLK_ENABLE
5076+#define MRV_VI_ISP_CLK_ENABLE_MASK 0x00000001
5077+#define MRV_VI_ISP_CLK_ENABLE_SHIFT 0
5078+
5079+
5080+#define MRV_VI_ALL_CLK_ENABLE
5081+#define MRV_VI_ALL_CLK_ENABLE_MASK \
5082+(0 \
5083+| MRV_VI_MIPI_CLK_ENABLE_MASK \
5084+| MRV_VI_SMIA_CLK_ENABLE_MASK \
5085+| MRV_VI_SIMP_CLK_ENABLE_MASK \
5086+| MRV_VI_IE_CLK_ENABLE_MASK \
5087+| MRV_VI_EMP_CLK_ENABLE_MASK \
5088+| MRV_VI_MI_CLK_ENABLE_MASK \
5089+| MRV_VI_JPEG_CLK_ENABLE_MASK \
5090+| MRV_VI_SRSZ_CLK_ENABLE_MASK \
5091+| MRV_VI_MRSZ_CLK_ENABLE_MASK \
5092+| MRV_VI_CP_CLK_ENABLE_MASK \
5093+| MRV_VI_ISP_CLK_ENABLE_MASK \
5094+)
5095+#define MRV_VI_ALL_CLK_ENABLE_SHIFT 0
5096+
5097+#define MRV_VI_MIPI_SOFT_RST
5098+#define MRV_VI_MIPI_SOFT_RST_MASK 0x00000800
5099+#define MRV_VI_MIPI_SOFT_RST_SHIFT 11
5100+
5101+#define MRV_VI_SMIA_SOFT_RST
5102+#define MRV_VI_SMIA_SOFT_RST_MASK 0x00000400
5103+#define MRV_VI_SMIA_SOFT_RST_SHIFT 10
5104+#define MRV_VI_SIMP_SOFT_RST
5105+#define MRV_VI_SIMP_SOFT_RST_MASK 0x00000200
5106+#define MRV_VI_SIMP_SOFT_RST_SHIFT 9
5107+
5108+#define MRV_VI_IE_SOFT_RST
5109+#define MRV_VI_IE_SOFT_RST_MASK 0x00000100
5110+#define MRV_VI_IE_SOFT_RST_SHIFT 8
5111+#define MRV_VI_MARVIN_RST
5112+#define MRV_VI_MARVIN_RST_MASK 0x00000080
5113+#define MRV_VI_MARVIN_RST_SHIFT 7
5114+
5115+#define MRV_VI_EMP_SOFT_RST_MASK 0
5116+#define MRV_VI_MI_SOFT_RST
5117+#define MRV_VI_MI_SOFT_RST_MASK 0x00000040
5118+#define MRV_VI_MI_SOFT_RST_SHIFT 6
5119+
5120+#define MRV_VI_JPEG_SOFT_RST
5121+#define MRV_VI_JPEG_SOFT_RST_MASK 0x00000020
5122+#define MRV_VI_JPEG_SOFT_RST_SHIFT 5
5123+#define MRV_VI_SRSZ_SOFT_RST
5124+#define MRV_VI_SRSZ_SOFT_RST_MASK 0x00000010
5125+#define MRV_VI_SRSZ_SOFT_RST_SHIFT 4
5126+
5127+#define MRV_VI_MRSZ_SOFT_RST
5128+#define MRV_VI_MRSZ_SOFT_RST_MASK 0x00000008
5129+#define MRV_VI_MRSZ_SOFT_RST_SHIFT 3
5130+#define MRV_VI_YCS_SOFT_RST
5131+#define MRV_VI_YCS_SOFT_RST_MASK 0x00000004
5132+#define MRV_VI_YCS_SOFT_RST_SHIFT 2
5133+#define MRV_VI_CP_SOFT_RST
5134+#define MRV_VI_CP_SOFT_RST_MASK 0x00000002
5135+#define MRV_VI_CP_SOFT_RST_SHIFT 1
5136+#define MRV_VI_ISP_SOFT_RST
5137+#define MRV_VI_ISP_SOFT_RST_MASK 0x00000001
5138+#define MRV_VI_ISP_SOFT_RST_SHIFT 0
5139+
5140+#define MRV_VI_ALL_SOFT_RST
5141+#define MRV_VI_ALL_SOFT_RST_MASK \
5142+(0 \
5143+| MRV_VI_MIPI_SOFT_RST_MASK \
5144+| MRV_VI_SMIA_SOFT_RST_MASK \
5145+| MRV_VI_SIMP_SOFT_RST_MASK \
5146+| MRV_VI_IE_SOFT_RST_MASK \
5147+| MRV_VI_EMP_SOFT_RST_MASK \
5148+| MRV_VI_MI_SOFT_RST_MASK \
5149+| MRV_VI_JPEG_SOFT_RST_MASK \
5150+| MRV_VI_SRSZ_SOFT_RST_MASK \
5151+| MRV_VI_MRSZ_SOFT_RST_MASK \
5152+| MRV_VI_YCS_SOFT_RST_MASK \
5153+| MRV_VI_CP_SOFT_RST_MASK \
5154+| MRV_VI_ISP_SOFT_RST_MASK \
5155+)
5156+#define MRV_VI_ALL_SOFT_RST_SHIFT 0
5157+
5158+
5159+#define MRV_VI_DMA_SPMUX
5160+#define MRV_VI_DMA_SPMUX_MASK 0x00000800
5161+#define MRV_VI_DMA_SPMUX_SHIFT 11
5162+#define MRV_VI_DMA_SPMUX_CAM 0
5163+#define MRV_VI_DMA_SPMUX_DMA 1
5164+#define MRV_VI_DMA_IEMUX
5165+#define MRV_VI_DMA_IEMUX_MASK 0x00000400
5166+#define MRV_VI_DMA_IEMUX_SHIFT 10
5167+#define MRV_VI_DMA_IEMUX_CAM 0
5168+#define MRV_VI_DMA_IEMUX_DMA 1
5169+#define MRV_IF_SELECT
5170+#define MRV_IF_SELECT_MASK 0x00000300
5171+#define MRV_IF_SELECT_SHIFT 8
5172+#define MRV_IF_SELECT_PAR 0
5173+#define MRV_IF_SELECT_SMIA 1
5174+#define MRV_IF_SELECT_MIPI 2
5175+#define MRV_VI_DMA_SWITCH
5176+#define MRV_VI_DMA_SWITCH_MASK 0x00000070
5177+#define MRV_VI_DMA_SWITCH_SHIFT 4
5178+#define MRV_VI_DMA_SWITCH_SELF 0
5179+#define MRV_VI_DMA_SWITCH_SI 1
5180+#define MRV_VI_DMA_SWITCH_IE 2
5181+#define MRV_VI_DMA_SWITCH_JPG 3
5182+#define MRV_VI_CHAN_MODE
5183+#define MRV_VI_CHAN_MODE_MASK 0x0000000C
5184+#define MRV_VI_CHAN_MODE_SHIFT 2
5185+
5186+#define MRV_VI_CHAN_MODE_OFF 0x00
5187+#define MRV_VI_CHAN_MODE_Y 0xFF
5188+#define MRV_VI_CHAN_MODE_MP_RAW 0x01
5189+#define MRV_VI_CHAN_MODE_MP 0x01
5190+#define MRV_VI_CHAN_MODE_SP 0x02
5191+#define MRV_VI_CHAN_MODE_MP_SP 0x03
5192+
5193+#define MRV_VI_MP_MUX
5194+#define MRV_VI_MP_MUX_MASK 0x00000003
5195+#define MRV_VI_MP_MUX_SHIFT 0
5196+
5197+#define MRV_VI_MP_MUX_JPGDIRECT 0x00
5198+#define MRV_VI_MP_MUX_MP 0x01
5199+#define MRV_VI_MP_MUX_RAW 0x01
5200+#define MRV_VI_MP_MUX_JPEG 0x02
5201+
5202+
5203+
5204+
5205+#define MRV_IMGEFF_CFG_UPD
5206+#define MRV_IMGEFF_CFG_UPD_MASK 0x00000010
5207+#define MRV_IMGEFF_CFG_UPD_SHIFT 4
5208+#define MRV_IMGEFF_EFFECT_MODE
5209+#define MRV_IMGEFF_EFFECT_MODE_MASK 0x0000000E
5210+#define MRV_IMGEFF_EFFECT_MODE_SHIFT 1
5211+#define MRV_IMGEFF_EFFECT_MODE_GRAY 0
5212+#define MRV_IMGEFF_EFFECT_MODE_NEGATIVE 1
5213+#define MRV_IMGEFF_EFFECT_MODE_SEPIA 2
5214+#define MRV_IMGEFF_EFFECT_MODE_COLOR_SEL 3
5215+#define MRV_IMGEFF_EFFECT_MODE_EMBOSS 4
5216+#define MRV_IMGEFF_EFFECT_MODE_SKETCH 5
5217+#define MRV_IMGEFF_BYPASS_MODE
5218+#define MRV_IMGEFF_BYPASS_MODE_MASK 0x00000001
5219+#define MRV_IMGEFF_BYPASS_MODE_SHIFT 0
5220+#define MRV_IMGEFF_BYPASS_MODE_PROCESS 1
5221+#define MRV_IMGEFF_BYPASS_MODE_BYPASS 0
5222+
5223+#define MRV_IMGEFF_COLOR_THRESHOLD
5224+#define MRV_IMGEFF_COLOR_THRESHOLD_MASK 0x0000FF00
5225+#define MRV_IMGEFF_COLOR_THRESHOLD_SHIFT 8
5226+#define MRV_IMGEFF_COLOR_SELECTION
5227+#define MRV_IMGEFF_COLOR_SELECTION_MASK 0x00000007
5228+#define MRV_IMGEFF_COLOR_SELECTION_SHIFT 0
5229+#define MRV_IMGEFF_COLOR_SELECTION_RGB 0
5230+#define MRV_IMGEFF_COLOR_SELECTION_B 1
5231+#define MRV_IMGEFF_COLOR_SELECTION_G 2
5232+#define MRV_IMGEFF_COLOR_SELECTION_BG 3
5233+#define MRV_IMGEFF_COLOR_SELECTION_R 4
5234+#define MRV_IMGEFF_COLOR_SELECTION_BR 5
5235+#define MRV_IMGEFF_COLOR_SELECTION_GR 6
5236+#define MRV_IMGEFF_COLOR_SELECTION_BGR 7
5237+
5238+#define MRV_IMGEFF_EMB_COEF_21_EN
5239+#define MRV_IMGEFF_EMB_COEF_21_EN_MASK 0x00008000
5240+#define MRV_IMGEFF_EMB_COEF_21_EN_SHIFT 15
5241+#define MRV_IMGEFF_EMB_COEF_21
5242+#define MRV_IMGEFF_EMB_COEF_21_MASK 0x00007000
5243+#define MRV_IMGEFF_EMB_COEF_21_SHIFT 12
5244+
5245+#define MRV_IMGEFF_EMB_COEF_21_4
5246+#define MRV_IMGEFF_EMB_COEF_21_4_MASK 0x0000F000
5247+#define MRV_IMGEFF_EMB_COEF_21_4_SHIFT 12
5248+#define MRV_IMGEFF_EMB_COEF_13_EN
5249+#define MRV_IMGEFF_EMB_COEF_13_EN_MASK 0x00000800
5250+#define MRV_IMGEFF_EMB_COEF_13_EN_SHIFT 11
5251+#define MRV_IMGEFF_EMB_COEF_13
5252+#define MRV_IMGEFF_EMB_COEF_13_MASK 0x00000700
5253+#define MRV_IMGEFF_EMB_COEF_13_SHIFT 8
5254+
5255+#define MRV_IMGEFF_EMB_COEF_13_4
5256+#define MRV_IMGEFF_EMB_COEF_13_4_MASK 0x00000F00
5257+#define MRV_IMGEFF_EMB_COEF_13_4_SHIFT 8
5258+#define MRV_IMGEFF_EMB_COEF_12_EN
5259+#define MRV_IMGEFF_EMB_COEF_12_EN_MASK 0x00000080
5260+#define MRV_IMGEFF_EMB_COEF_12_EN_SHIFT 7
5261+#define MRV_IMGEFF_EMB_COEF_12
5262+#define MRV_IMGEFF_EMB_COEF_12_MASK 0x00000070
5263+#define MRV_IMGEFF_EMB_COEF_12_SHIFT 4
5264+
5265+#define MRV_IMGEFF_EMB_COEF_12_4
5266+#define MRV_IMGEFF_EMB_COEF_12_4_MASK 0x000000F0
5267+#define MRV_IMGEFF_EMB_COEF_12_4_SHIFT 4
5268+#define MRV_IMGEFF_EMB_COEF_11_EN
5269+#define MRV_IMGEFF_EMB_COEF_11_EN_MASK 0x00000008
5270+#define MRV_IMGEFF_EMB_COEF_11_EN_SHIFT 3
5271+#define MRV_IMGEFF_EMB_COEF_11
5272+#define MRV_IMGEFF_EMB_COEF_11_MASK 0x00000007
5273+#define MRV_IMGEFF_EMB_COEF_11_SHIFT 0
5274+
5275+#define MRV_IMGEFF_EMB_COEF_11_4
5276+#define MRV_IMGEFF_EMB_COEF_11_4_MASK 0x0000000F
5277+#define MRV_IMGEFF_EMB_COEF_11_4_SHIFT 0
5278+
5279+#define MRV_IMGEFF_EMB_COEF_32_EN
5280+#define MRV_IMGEFF_EMB_COEF_32_EN_MASK 0x00008000
5281+#define MRV_IMGEFF_EMB_COEF_32_EN_SHIFT 15
5282+#define MRV_IMGEFF_EMB_COEF_32
5283+#define MRV_IMGEFF_EMB_COEF_32_MASK 0x00007000
5284+#define MRV_IMGEFF_EMB_COEF_32_SHIFT 12
5285+
5286+#define MRV_IMGEFF_EMB_COEF_32_4
5287+#define MRV_IMGEFF_EMB_COEF_32_4_MASK 0x0000F000
5288+#define MRV_IMGEFF_EMB_COEF_32_4_SHIFT 12
5289+#define MRV_IMGEFF_EMB_COEF_31_EN
5290+#define MRV_IMGEFF_EMB_COEF_31_EN_MASK 0x00000800
5291+#define MRV_IMGEFF_EMB_COEF_31_EN_SHIFT 11
5292+#define MRV_IMGEFF_EMB_COEF_31
5293+#define MRV_IMGEFF_EMB_COEF_31_MASK 0x00000700
5294+#define MRV_IMGEFF_EMB_COEF_31_SHIFT 8
5295+
5296+#define MRV_IMGEFF_EMB_COEF_31_4
5297+#define MRV_IMGEFF_EMB_COEF_31_4_MASK 0x00000F00
5298+#define MRV_IMGEFF_EMB_COEF_31_4_SHIFT 8
5299+#define MRV_IMGEFF_EMB_COEF_23_EN
5300+#define MRV_IMGEFF_EMB_COEF_23_EN_MASK 0x00000080
5301+#define MRV_IMGEFF_EMB_COEF_23_EN_SHIFT 7
5302+#define MRV_IMGEFF_EMB_COEF_23
5303+#define MRV_IMGEFF_EMB_COEF_23_MASK 0x00000070
5304+#define MRV_IMGEFF_EMB_COEF_23_SHIFT 4
5305+
5306+#define MRV_IMGEFF_EMB_COEF_23_4
5307+#define MRV_IMGEFF_EMB_COEF_23_4_MASK 0x000000F0
5308+#define MRV_IMGEFF_EMB_COEF_23_4_SHIFT 4
5309+
5310+#define MRV_IMGEFF_EMB_COEF_22_EN
5311+#define MRV_IMGEFF_EMB_COEF_22_EN_MASK 0x00000008
5312+#define MRV_IMGEFF_EMB_COEF_22_EN_SHIFT 3
5313+#define MRV_IMGEFF_EMB_COEF_22
5314+#define MRV_IMGEFF_EMB_COEF_22_MASK 0x00000007
5315+#define MRV_IMGEFF_EMB_COEF_22_SHIFT 0
5316+
5317+#define MRV_IMGEFF_EMB_COEF_22_4
5318+#define MRV_IMGEFF_EMB_COEF_22_4_MASK 0x0000000F
5319+#define MRV_IMGEFF_EMB_COEF_22_4_SHIFT 0
5320+
5321+#define MRV_IMGEFF_SKET_COEF_13_EN
5322+#define MRV_IMGEFF_SKET_COEF_13_EN_MASK 0x00008000
5323+#define MRV_IMGEFF_SKET_COEF_13_EN_SHIFT 15
5324+#define MRV_IMGEFF_SKET_COEF_13
5325+#define MRV_IMGEFF_SKET_COEF_13_MASK 0x00007000
5326+#define MRV_IMGEFF_SKET_COEF_13_SHIFT 12
5327+
5328+#define MRV_IMGEFF_SKET_COEF_13_4
5329+#define MRV_IMGEFF_SKET_COEF_13_4_MASK 0x0000F000
5330+#define MRV_IMGEFF_SKET_COEF_13_4_SHIFT 12
5331+#define MRV_IMGEFF_SKET_COEF_12_EN
5332+#define MRV_IMGEFF_SKET_COEF_12_EN_MASK 0x00000800
5333+#define MRV_IMGEFF_SKET_COEF_12_EN_SHIFT 11
5334+#define MRV_IMGEFF_SKET_COEF_12
5335+#define MRV_IMGEFF_SKET_COEF_12_MASK 0x00000700
5336+#define MRV_IMGEFF_SKET_COEF_12_SHIFT 8
5337+
5338+#define MRV_IMGEFF_SKET_COEF_12_4
5339+#define MRV_IMGEFF_SKET_COEF_12_4_MASK 0x00000F00
5340+#define MRV_IMGEFF_SKET_COEF_12_4_SHIFT 8
5341+#define MRV_IMGEFF_SKET_COEF_11_EN
5342+#define MRV_IMGEFF_SKET_COEF_11_EN_MASK 0x00000080
5343+#define MRV_IMGEFF_SKET_COEF_11_EN_SHIFT 7
5344+#define MRV_IMGEFF_SKET_COEF_11
5345+#define MRV_IMGEFF_SKET_COEF_11_MASK 0x00000070
5346+#define MRV_IMGEFF_SKET_COEF_11_SHIFT 4
5347+
5348+#define MRV_IMGEFF_SKET_COEF_11_4
5349+#define MRV_IMGEFF_SKET_COEF_11_4_MASK 0x000000F0
5350+#define MRV_IMGEFF_SKET_COEF_11_4_SHIFT 4
5351+#define MRV_IMGEFF_EMB_COEF_33_EN
5352+#define MRV_IMGEFF_EMB_COEF_33_EN_MASK 0x00000008
5353+#define MRV_IMGEFF_EMB_COEF_33_EN_SHIFT 3
5354+#define MRV_IMGEFF_EMB_COEF_33
5355+#define MRV_IMGEFF_EMB_COEF_33_MASK 0x00000007
5356+#define MRV_IMGEFF_EMB_COEF_33_SHIFT 0
5357+
5358+#define MRV_IMGEFF_EMB_COEF_33_4
5359+#define MRV_IMGEFF_EMB_COEF_33_4_MASK 0x0000000F
5360+#define MRV_IMGEFF_EMB_COEF_33_4_SHIFT 0
5361+
5362+#define MRV_IMGEFF_SKET_COEF_31_EN
5363+#define MRV_IMGEFF_SKET_COEF_31_EN_MASK 0x00008000
5364+#define MRV_IMGEFF_SKET_COEF_31_EN_SHIFT 15
5365+#define MRV_IMGEFF_SKET_COEF_31
5366+#define MRV_IMGEFF_SKET_COEF_31_MASK 0x00007000
5367+#define MRV_IMGEFF_SKET_COEF_31_SHIFT 12
5368+
5369+#define MRV_IMGEFF_SKET_COEF_31_4
5370+#define MRV_IMGEFF_SKET_COEF_31_4_MASK 0x0000F000
5371+#define MRV_IMGEFF_SKET_COEF_31_4_SHIFT 12
5372+#define MRV_IMGEFF_SKET_COEF_23_EN
5373+#define MRV_IMGEFF_SKET_COEF_23_EN_MASK 0x00000800
5374+#define MRV_IMGEFF_SKET_COEF_23_EN_SHIFT 11
5375+#define MRV_IMGEFF_SKET_COEF_23
5376+#define MRV_IMGEFF_SKET_COEF_23_MASK 0x00000700
5377+#define MRV_IMGEFF_SKET_COEF_23_SHIFT 8
5378+
5379+#define MRV_IMGEFF_SKET_COEF_23_4
5380+#define MRV_IMGEFF_SKET_COEF_23_4_MASK 0x00000F00
5381+#define MRV_IMGEFF_SKET_COEF_23_4_SHIFT 8
5382+#define MRV_IMGEFF_SKET_COEF_22_EN
5383+#define MRV_IMGEFF_SKET_COEF_22_EN_MASK 0x00000080
5384+#define MRV_IMGEFF_SKET_COEF_22_EN_SHIFT 7
5385+#define MRV_IMGEFF_SKET_COEF_22
5386+#define MRV_IMGEFF_SKET_COEF_22_MASK 0x00000070
5387+#define MRV_IMGEFF_SKET_COEF_22_SHIFT 4
5388+
5389+#define MRV_IMGEFF_SKET_COEF_22_4
5390+#define MRV_IMGEFF_SKET_COEF_22_4_MASK 0x000000F0
5391+#define MRV_IMGEFF_SKET_COEF_22_4_SHIFT 4
5392+#define MRV_IMGEFF_SKET_COEF_21_EN
5393+#define MRV_IMGEFF_SKET_COEF_21_EN_MASK 0x00000008
5394+#define MRV_IMGEFF_SKET_COEF_21_EN_SHIFT 3
5395+#define MRV_IMGEFF_SKET_COEF_21
5396+#define MRV_IMGEFF_SKET_COEF_21_MASK 0x00000007
5397+#define MRV_IMGEFF_SKET_COEF_21_SHIFT 0
5398+
5399+#define MRV_IMGEFF_SKET_COEF_21_4
5400+#define MRV_IMGEFF_SKET_COEF_21_4_MASK 0x0000000F
5401+#define MRV_IMGEFF_SKET_COEF_21_4_SHIFT 0
5402+
5403+#define MRV_IMGEFF_SKET_COEF_33_EN
5404+#define MRV_IMGEFF_SKET_COEF_33_EN_MASK 0x00000080
5405+#define MRV_IMGEFF_SKET_COEF_33_EN_SHIFT 7
5406+#define MRV_IMGEFF_SKET_COEF_33
5407+#define MRV_IMGEFF_SKET_COEF_33_MASK 0x00000070
5408+#define MRV_IMGEFF_SKET_COEF_33_SHIFT 4
5409+
5410+#define MRV_IMGEFF_SKET_COEF_33_4
5411+#define MRV_IMGEFF_SKET_COEF_33_4_MASK 0x000000F0
5412+#define MRV_IMGEFF_SKET_COEF_33_4_SHIFT 4
5413+#define MRV_IMGEFF_SKET_COEF_32_EN
5414+#define MRV_IMGEFF_SKET_COEF_32_EN_MASK 0x00000008
5415+#define MRV_IMGEFF_SKET_COEF_32_EN_SHIFT 3
5416+#define MRV_IMGEFF_SKET_COEF_32
5417+#define MRV_IMGEFF_SKET_COEF_32_MASK 0x00000007
5418+#define MRV_IMGEFF_SKET_COEF_32_SHIFT 0
5419+
5420+#define MRV_IMGEFF_SKET_COEF_32_4
5421+#define MRV_IMGEFF_SKET_COEF_32_4_MASK 0x0000000F
5422+#define MRV_IMGEFF_SKET_COEF_32_4_SHIFT 0
5423+
5424+#define MRV_IMGEFF_INCR_CR
5425+#define MRV_IMGEFF_INCR_CR_MASK 0x0000FF00
5426+#define MRV_IMGEFF_INCR_CR_SHIFT 8
5427+#define MRV_IMGEFF_INCR_CB
5428+#define MRV_IMGEFF_INCR_CB_MASK 0x000000FF
5429+#define MRV_IMGEFF_INCR_CB_SHIFT 0
5430+
5431+#define MRV_IMGEFF_EFFECT_MODE_SHD
5432+#define MRV_IMGEFF_EFFECT_MODE_SHD_MASK 0x0000000E
5433+#define MRV_IMGEFF_EFFECT_MODE_SHD_SHIFT 1
5434+
5435+
5436+#define MRV_SI_TRANSPARENCY_MODE
5437+#define MRV_SI_TRANSPARENCY_MODE_MASK 0x00000004
5438+#define MRV_SI_TRANSPARENCY_MODE_SHIFT 2
5439+#define MRV_SI_TRANSPARENCY_MODE_DISABLED 1
5440+#define MRV_SI_TRANSPARENCY_MODE_ENABLED 0
5441+#define MRV_SI_REF_IMAGE
5442+#define MRV_SI_REF_IMAGE_MASK 0x00000002
5443+#define MRV_SI_REF_IMAGE_SHIFT 1
5444+#define MRV_SI_REF_IMAGE_MEM 1
5445+#define MRV_SI_REF_IMAGE_IE 0
5446+#define MRV_SI_BYPASS_MODE
5447+#define MRV_SI_BYPASS_MODE_MASK 0x00000001
5448+#define MRV_SI_BYPASS_MODE_SHIFT 0
5449+#define MRV_SI_BYPASS_MODE_BYPASS 0
5450+#define MRV_SI_BYPASS_MODE_PROCESS 1
5451+
5452+#define MRV_SI_OFFSET_X
5453+#define MRV_SI_OFFSET_X_MASK 0x00001FFE
5454+#define MRV_SI_OFFSET_X_SHIFT 0
5455+#define MRV_SI_OFFSET_X_MAX 0x00001FFE
5456+
5457+#define MRV_SI_OFFSET_Y
5458+#define MRV_SI_OFFSET_Y_MASK 0x00000FFF
5459+#define MRV_SI_OFFSET_Y_SHIFT 0
5460+#define MRV_SI_OFFSET_Y_MAX 0x00000FFF
5461+
5462+#define MRV_SI_Y_COMP
5463+#define MRV_SI_Y_COMP_MASK 0x000000FF
5464+#define MRV_SI_Y_COMP_SHIFT 0
5465+
5466+#define MRV_SI_CB_COMP
5467+#define MRV_SI_CB_COMP_MASK 0x000000FF
5468+#define MRV_SI_CB_COMP_SHIFT 0
5469+
5470+#define MRV_SI_CR_COMP
5471+#define MRV_SI_CR_COMP_MASK 0x000000FF
5472+#define MRV_SI_CR_COMP_SHIFT 0
5473+
5474+#define MRV_ISP_ISP_CSM_C_RANGE
5475+#define MRV_ISP_ISP_CSM_C_RANGE_MASK 0x00004000
5476+#define MRV_ISP_ISP_CSM_C_RANGE_SHIFT 14
5477+#define MRV_ISP_ISP_CSM_C_RANGE_BT601 0
5478+#define MRV_ISP_ISP_CSM_C_RANGE_FULL 1
5479+
5480+#define MRV_ISP_ISP_CSM_Y_RANGE
5481+#define MRV_ISP_ISP_CSM_Y_RANGE_MASK 0x00002000
5482+#define MRV_ISP_ISP_CSM_Y_RANGE_SHIFT 13
5483+#define MRV_ISP_ISP_CSM_Y_RANGE_BT601 0
5484+#define MRV_ISP_ISP_CSM_Y_RANGE_FULL 1
5485+#define MRV_ISP_ISP_FLASH_MODE
5486+#define MRV_ISP_ISP_FLASH_MODE_MASK 0x00001000
5487+#define MRV_ISP_ISP_FLASH_MODE_SHIFT 12
5488+#define MRV_ISP_ISP_FLASH_MODE_INDEP 0
5489+#define MRV_ISP_ISP_FLASH_MODE_SYNC 1
5490+#define MRV_ISP_ISP_GAMMA_OUT_ENABLE
5491+#define MRV_ISP_ISP_GAMMA_OUT_ENABLE_MASK 0x00000800
5492+#define MRV_ISP_ISP_GAMMA_OUT_ENABLE_SHIFT 11
5493+
5494+#define MRV_ISP_ISP_GEN_CFG_UPD
5495+#define MRV_ISP_ISP_GEN_CFG_UPD_MASK 0x00000400
5496+#define MRV_ISP_ISP_GEN_CFG_UPD_SHIFT 10
5497+
5498+#define MRV_ISP_ISP_CFG_UPD
5499+#define MRV_ISP_ISP_CFG_UPD_MASK 0x00000200
5500+#define MRV_ISP_ISP_CFG_UPD_SHIFT 9
5501+
5502+
5503+#define MRV_ISP_ISP_AWB_ENABLE
5504+#define MRV_ISP_ISP_AWB_ENABLE_MASK 0x00000080
5505+#define MRV_ISP_ISP_AWB_ENABLE_SHIFT 7
5506+#define MRV_ISP_ISP_GAMMA_IN_ENABLE
5507+#define MRV_ISP_ISP_GAMMA_IN_ENABLE_MASK 0x00000040
5508+#define MRV_ISP_ISP_GAMMA_IN_ENABLE_SHIFT 6
5509+
5510+#define MRV_ISP_ISP_INFORM_ENABLE
5511+#define MRV_ISP_ISP_INFORM_ENABLE_MASK 0x00000010
5512+#define MRV_ISP_ISP_INFORM_ENABLE_SHIFT 4
5513+#define MRV_ISP_ISP_MODE
5514+#define MRV_ISP_ISP_MODE_MASK 0x0000000E
5515+#define MRV_ISP_ISP_MODE_SHIFT 1
5516+#define MRV_ISP_ISP_MODE_RAW 0
5517+#define MRV_ISP_ISP_MODE_656 1
5518+#define MRV_ISP_ISP_MODE_601 2
5519+#define MRV_ISP_ISP_MODE_RGB 3
5520+#define MRV_ISP_ISP_MODE_DATA 4
5521+#define MRV_ISP_ISP_MODE_RGB656 5
5522+#define MRV_ISP_ISP_MODE_RAW656 6
5523+#define MRV_ISP_ISP_ENABLE
5524+#define MRV_ISP_ISP_ENABLE_MASK 0x00000001
5525+#define MRV_ISP_ISP_ENABLE_SHIFT 0
5526+
5527+#define MRV_ISP_INPUT_SELECTION
5528+#define MRV_ISP_INPUT_SELECTION_MASK 0x00007000
5529+#define MRV_ISP_INPUT_SELECTION_SHIFT 12
5530+#define MRV_ISP_INPUT_SELECTION_12EXT 0
5531+#define MRV_ISP_INPUT_SELECTION_10ZERO 1
5532+#define MRV_ISP_INPUT_SELECTION_10MSB 2
5533+#define MRV_ISP_INPUT_SELECTION_8ZERO 3
5534+#define MRV_ISP_INPUT_SELECTION_8MSB 4
5535+#define MRV_ISP_FIELD_SELECTION
5536+#define MRV_ISP_FIELD_SELECTION_MASK 0x00000600
5537+#define MRV_ISP_FIELD_SELECTION_SHIFT 9
5538+#define MRV_ISP_FIELD_SELECTION_BOTH 0
5539+#define MRV_ISP_FIELD_SELECTION_EVEN 1
5540+#define MRV_ISP_FIELD_SELECTION_ODD 2
5541+#define MRV_ISP_CCIR_SEQ
5542+#define MRV_ISP_CCIR_SEQ_MASK 0x00000180
5543+#define MRV_ISP_CCIR_SEQ_SHIFT 7
5544+#define MRV_ISP_CCIR_SEQ_YCBYCR 0
5545+#define MRV_ISP_CCIR_SEQ_YCRYCB 1
5546+#define MRV_ISP_CCIR_SEQ_CBYCRY 2
5547+#define MRV_ISP_CCIR_SEQ_CRYCBY 3
5548+#define MRV_ISP_CONV_422
5549+#define MRV_ISP_CONV_422_MASK 0x00000060
5550+#define MRV_ISP_CONV_422_SHIFT 5
5551+#define MRV_ISP_CONV_422_CO 0
5552+#define MRV_ISP_CONV_422_INTER 1
5553+#define MRV_ISP_CONV_422_NONCO 2
5554+#define MRV_ISP_BAYER_PAT
5555+#define MRV_ISP_BAYER_PAT_MASK 0x00000018
5556+#define MRV_ISP_BAYER_PAT_SHIFT 3
5557+#define MRV_ISP_BAYER_PAT_RG 0
5558+#define MRV_ISP_BAYER_PAT_GR 1
5559+#define MRV_ISP_BAYER_PAT_GB 2
5560+#define MRV_ISP_BAYER_PAT_BG 3
5561+#define MRV_ISP_VSYNC_POL
5562+#define MRV_ISP_VSYNC_POL_MASK 0x00000004
5563+#define MRV_ISP_VSYNC_POL_SHIFT 2
5564+#define MRV_ISP_HSYNC_POL
5565+#define MRV_ISP_HSYNC_POL_MASK 0x00000002
5566+#define MRV_ISP_HSYNC_POL_SHIFT 1
5567+#define MRV_ISP_SAMPLE_EDGE
5568+#define MRV_ISP_SAMPLE_EDGE_MASK 0x00000001
5569+#define MRV_ISP_SAMPLE_EDGE_SHIFT 0
5570+
5571+#define MRV_ISP_ACQ_H_OFFS
5572+#define MRV_ISP_ACQ_H_OFFS_MASK 0x00003FFF
5573+#define MRV_ISP_ACQ_H_OFFS_SHIFT 0
5574+
5575+#define MRV_ISP_ACQ_V_OFFS
5576+#define MRV_ISP_ACQ_V_OFFS_MASK 0x00000FFF
5577+#define MRV_ISP_ACQ_V_OFFS_SHIFT 0
5578+
5579+#define MRV_ISP_ACQ_H_SIZE
5580+#define MRV_ISP_ACQ_H_SIZE_MASK 0x00003FFF
5581+#define MRV_ISP_ACQ_H_SIZE_SHIFT 0
5582+
5583+#define MRV_ISP_ACQ_V_SIZE
5584+#define MRV_ISP_ACQ_V_SIZE_MASK 0x00000FFF
5585+#define MRV_ISP_ACQ_V_SIZE_SHIFT 0
5586+
5587+
5588+#define MRV_ISP_ACQ_NR_FRAMES
5589+#define MRV_ISP_ACQ_NR_FRAMES_MASK 0x000003FF
5590+#define MRV_ISP_ACQ_NR_FRAMES_SHIFT 0
5591+#define MRV_ISP_ACQ_NR_FRAMES_MAX \
5592+ (MRV_ISP_ACQ_NR_FRAMES_MASK >> MRV_ISP_ACQ_NR_FRAMES_SHIFT)
5593+
5594+#define MRV_ISP_GAMMA_DX_8
5595+#define MRV_ISP_GAMMA_DX_8_MASK 0x70000000
5596+#define MRV_ISP_GAMMA_DX_8_SHIFT 28
5597+
5598+#define MRV_ISP_GAMMA_DX_7
5599+#define MRV_ISP_GAMMA_DX_7_MASK 0x07000000
5600+#define MRV_ISP_GAMMA_DX_7_SHIFT 24
5601+
5602+#define MRV_ISP_GAMMA_DX_6
5603+#define MRV_ISP_GAMMA_DX_6_MASK 0x00700000
5604+#define MRV_ISP_GAMMA_DX_6_SHIFT 20
5605+
5606+#define MRV_ISP_GAMMA_DX_5
5607+#define MRV_ISP_GAMMA_DX_5_MASK 0x00070000
5608+#define MRV_ISP_GAMMA_DX_5_SHIFT 16
5609+
5610+#define MRV_ISP_GAMMA_DX_4
5611+#define MRV_ISP_GAMMA_DX_4_MASK 0x00007000
5612+#define MRV_ISP_GAMMA_DX_4_SHIFT 12
5613+
5614+#define MRV_ISP_GAMMA_DX_3
5615+#define MRV_ISP_GAMMA_DX_3_MASK 0x00000700
5616+#define MRV_ISP_GAMMA_DX_3_SHIFT 8
5617+
5618+#define MRV_ISP_GAMMA_DX_2
5619+#define MRV_ISP_GAMMA_DX_2_MASK 0x00000070
5620+#define MRV_ISP_GAMMA_DX_2_SHIFT 4
5621+
5622+#define MRV_ISP_GAMMA_DX_1
5623+#define MRV_ISP_GAMMA_DX_1_MASK 0x00000007
5624+#define MRV_ISP_GAMMA_DX_1_SHIFT 0
5625+
5626+#define MRV_ISP_GAMMA_DX_16
5627+#define MRV_ISP_GAMMA_DX_16_MASK 0x70000000
5628+#define MRV_ISP_GAMMA_DX_16_SHIFT 28
5629+
5630+#define MRV_ISP_GAMMA_DX_15
5631+#define MRV_ISP_GAMMA_DX_15_MASK 0x07000000
5632+#define MRV_ISP_GAMMA_DX_15_SHIFT 24
5633+
5634+#define MRV_ISP_GAMMA_DX_14
5635+#define MRV_ISP_GAMMA_DX_14_MASK 0x00700000
5636+#define MRV_ISP_GAMMA_DX_14_SHIFT 20
5637+
5638+#define MRV_ISP_GAMMA_DX_13
5639+#define MRV_ISP_GAMMA_DX_13_MASK 0x00070000
5640+#define MRV_ISP_GAMMA_DX_13_SHIFT 16
5641+
5642+#define MRV_ISP_GAMMA_DX_12
5643+#define MRV_ISP_GAMMA_DX_12_MASK 0x00007000
5644+#define MRV_ISP_GAMMA_DX_12_SHIFT 12
5645+
5646+#define MRV_ISP_GAMMA_DX_11
5647+#define MRV_ISP_GAMMA_DX_11_MASK 0x00000700
5648+#define MRV_ISP_GAMMA_DX_11_SHIFT 8
5649+
5650+#define MRV_ISP_GAMMA_DX_10
5651+#define MRV_ISP_GAMMA_DX_10_MASK 0x00000070
5652+#define MRV_ISP_GAMMA_DX_10_SHIFT 4
5653+
5654+#define MRV_ISP_GAMMA_DX_9
5655+#define MRV_ISP_GAMMA_DX_9_MASK 0x00000007
5656+#define MRV_ISP_GAMMA_DX_9_SHIFT 0
5657+
5658+#define MRV_ISP_GAMMA_Y
5659+
5660+#define MRV_ISP_GAMMA_Y_MASK 0x00000FFF
5661+
5662+#define MRV_ISP_GAMMA_Y_SHIFT 0
5663+#define MRV_ISP_GAMMA_Y_MAX (MRV_ISP_GAMMA_Y_MASK >> MRV_ISP_GAMMA_Y_SHIFT)
5664+
5665+#define MRV_ISP_GAMMA_R_Y
5666+#define MRV_ISP_GAMMA_R_Y_MASK MRV_ISP_GAMMA_Y_MASK
5667+#define MRV_ISP_GAMMA_R_Y_SHIFT MRV_ISP_GAMMA_Y_SHIFT
5668+
5669+#define MRV_ISP_GAMMA_G_Y
5670+#define MRV_ISP_GAMMA_G_Y_MASK MRV_ISP_GAMMA_Y_MASK
5671+#define MRV_ISP_GAMMA_G_Y_SHIFT MRV_ISP_GAMMA_Y_SHIFT
5672+
5673+#define MRV_ISP_GAMMA_B_Y
5674+#define MRV_ISP_GAMMA_B_Y_MASK MRV_ISP_GAMMA_Y_MASK
5675+#define MRV_ISP_GAMMA_B_Y_SHIFT MRV_ISP_GAMMA_Y_SHIFT
5676+
5677+ #define MRV_ISP_AWB_MEAS_MODE
5678+ #define MRV_ISP_AWB_MEAS_MODE_MASK 0x80000000
5679+ #define MRV_ISP_AWB_MEAS_MODE_SHIFT 31
5680+#define MRV_ISP_AWB_MAX_EN
5681+#define MRV_ISP_AWB_MAX_EN_MASK 0x00000004
5682+#define MRV_ISP_AWB_MAX_EN_SHIFT 2
5683+#define MRV_ISP_AWB_MODE
5684+#define MRV_ISP_AWB_MODE_MASK 0x00000003
5685+#define MRV_ISP_AWB_MODE_SHIFT 0
5686+#define MRV_ISP_AWB_MODE_MEAS 2
5687+#define MRV_ISP_AWB_MODE_NOMEAS 0
5688+
5689+#define MRV_ISP_AWB_H_OFFS
5690+#define MRV_ISP_AWB_H_OFFS_MASK 0x00000FFF
5691+#define MRV_ISP_AWB_H_OFFS_SHIFT 0
5692+
5693+#define MRV_ISP_AWB_V_OFFS
5694+#define MRV_ISP_AWB_V_OFFS_MASK 0x00000FFF
5695+#define MRV_ISP_AWB_V_OFFS_SHIFT 0
5696+
5697+#define MRV_ISP_AWB_H_SIZE
5698+#define MRV_ISP_AWB_H_SIZE_MASK 0x00001FFF
5699+#define MRV_ISP_AWB_H_SIZE_SHIFT 0
5700+
5701+#define MRV_ISP_AWB_V_SIZE
5702+#define MRV_ISP_AWB_V_SIZE_MASK 0x00000FFF
5703+#define MRV_ISP_AWB_V_SIZE_SHIFT 0
5704+
5705+
5706+#define MRV_ISP_AWB_FRAMES
5707+#define MRV_ISP_AWB_FRAMES_MASK 0x00000007
5708+#define MRV_ISP_AWB_FRAMES_SHIFT 0
5709+
5710+#define MRV_ISP_AWB_REF_CR__MAX_R
5711+#define MRV_ISP_AWB_REF_CR__MAX_R_MASK 0x0000FF00
5712+#define MRV_ISP_AWB_REF_CR__MAX_R_SHIFT 8
5713+#define MRV_ISP_AWB_REF_CB__MAX_B
5714+#define MRV_ISP_AWB_REF_CB__MAX_B_MASK 0x000000FF
5715+#define MRV_ISP_AWB_REF_CB__MAX_B_SHIFT 0
5716+
5717+#define MRV_ISP_AWB_MAX_Y
5718+#define MRV_ISP_AWB_MAX_Y_MASK 0xFF000000
5719+#define MRV_ISP_AWB_MAX_Y_SHIFT 24
5720+
5721+#define MRV_ISP_AWB_MIN_Y__MAX_G
5722+#define MRV_ISP_AWB_MIN_Y__MAX_G_MASK 0x00FF0000
5723+#define MRV_ISP_AWB_MIN_Y__MAX_G_SHIFT 16
5724+
5725+#define MRV_ISP_AWB_MAX_CSUM
5726+#define MRV_ISP_AWB_MAX_CSUM_MASK 0x0000FF00
5727+#define MRV_ISP_AWB_MAX_CSUM_SHIFT 8
5728+#define MRV_ISP_AWB_MIN_C
5729+#define MRV_ISP_AWB_MIN_C_MASK 0x000000FF
5730+#define MRV_ISP_AWB_MIN_C_SHIFT 0
5731+
5732+#define MRV_ISP_AWB_GAIN_GR
5733+#define MRV_ISP_AWB_GAIN_GR_MASK 0x03FF0000
5734+#define MRV_ISP_AWB_GAIN_GR_SHIFT 16
5735+#define MRV_ISP_AWB_GAIN_GR_MAX (MRV_ISP_AWB_GAIN_GR_MASK >> \
5736+ MRV_ISP_AWB_GAIN_GR_SHIFT)
5737+#define MRV_ISP_AWB_GAIN_GB
5738+#define MRV_ISP_AWB_GAIN_GB_MASK 0x000003FF
5739+#define MRV_ISP_AWB_GAIN_GB_SHIFT 0
5740+#define MRV_ISP_AWB_GAIN_GB_MAX (MRV_ISP_AWB_GAIN_GB_MASK >> \
5741+ MRV_ISP_AWB_GAIN_GB_SHIFT)
5742+
5743+#define MRV_ISP_AWB_GAIN_R
5744+#define MRV_ISP_AWB_GAIN_R_MASK 0x03FF0000
5745+#define MRV_ISP_AWB_GAIN_R_SHIFT 16
5746+#define MRV_ISP_AWB_GAIN_R_MAX (MRV_ISP_AWB_GAIN_R_MASK >> \
5747+ MRV_ISP_AWB_GAIN_R_SHIFT)
5748+#define MRV_ISP_AWB_GAIN_B
5749+#define MRV_ISP_AWB_GAIN_B_MASK 0x000003FF
5750+#define MRV_ISP_AWB_GAIN_B_SHIFT 0
5751+#define MRV_ISP_AWB_GAIN_B_MAX (MRV_ISP_AWB_GAIN_B_MASK >> \
5752+ MRV_ISP_AWB_GAIN_B_SHIFT)
5753+
5754+#define MRV_ISP_AWB_WHITE_CNT
5755+#define MRV_ISP_AWB_WHITE_CNT_MASK 0x03FFFFFF
5756+#define MRV_ISP_AWB_WHITE_CNT_SHIFT 0
5757+
5758+#define MRV_ISP_AWB_MEAN_Y__G
5759+#define MRV_ISP_AWB_MEAN_Y__G_MASK 0x00FF0000
5760+#define MRV_ISP_AWB_MEAN_Y__G_SHIFT 16
5761+#define MRV_ISP_AWB_MEAN_CB__B
5762+#define MRV_ISP_AWB_MEAN_CB__B_MASK 0x0000FF00
5763+#define MRV_ISP_AWB_MEAN_CB__B_SHIFT 8
5764+#define MRV_ISP_AWB_MEAN_CR__R
5765+#define MRV_ISP_AWB_MEAN_CR__R_MASK 0x000000FF
5766+#define MRV_ISP_AWB_MEAN_CR__R_SHIFT 0
5767+
5768+
5769+
5770+#define MRV_ISP_CC_COEFF_0
5771+#define MRV_ISP_CC_COEFF_0_MASK 0x000001FF
5772+#define MRV_ISP_CC_COEFF_0_SHIFT 0
5773+
5774+#define MRV_ISP_CC_COEFF_1
5775+#define MRV_ISP_CC_COEFF_1_MASK 0x000001FF
5776+#define MRV_ISP_CC_COEFF_1_SHIFT 0
5777+
5778+#define MRV_ISP_CC_COEFF_2
5779+#define MRV_ISP_CC_COEFF_2_MASK 0x000001FF
5780+#define MRV_ISP_CC_COEFF_2_SHIFT 0
5781+
5782+#define MRV_ISP_CC_COEFF_3
5783+#define MRV_ISP_CC_COEFF_3_MASK 0x000001FF
5784+#define MRV_ISP_CC_COEFF_3_SHIFT 0
5785+
5786+#define MRV_ISP_CC_COEFF_4
5787+#define MRV_ISP_CC_COEFF_4_MASK 0x000001FF
5788+#define MRV_ISP_CC_COEFF_4_SHIFT 0
5789+
5790+#define MRV_ISP_CC_COEFF_5
5791+#define MRV_ISP_CC_COEFF_5_MASK 0x000001FF
5792+#define MRV_ISP_CC_COEFF_5_SHIFT 0
5793+
5794+#define MRV_ISP_CC_COEFF_6
5795+#define MRV_ISP_CC_COEFF_6_MASK 0x000001FF
5796+#define MRV_ISP_CC_COEFF_6_SHIFT 0
5797+
5798+#define MRV_ISP_CC_COEFF_7
5799+#define MRV_ISP_CC_COEFF_7_MASK 0x000001FF
5800+#define MRV_ISP_CC_COEFF_7_SHIFT 0
5801+
5802+#define MRV_ISP_CC_COEFF_8
5803+#define MRV_ISP_CC_COEFF_8_MASK 0x000001FF
5804+#define MRV_ISP_CC_COEFF_8_SHIFT 0
5805+
5806+#define MRV_ISP_ISP_OUT_H_OFFS
5807+#define MRV_ISP_ISP_OUT_H_OFFS_MASK 0x00000FFF
5808+#define MRV_ISP_ISP_OUT_H_OFFS_SHIFT 0
5809+
5810+#define MRV_ISP_ISP_OUT_V_OFFS
5811+#define MRV_ISP_ISP_OUT_V_OFFS_MASK 0x00000FFF
5812+#define MRV_ISP_ISP_OUT_V_OFFS_SHIFT 0
5813+
5814+#define MRV_ISP_ISP_OUT_H_SIZE
5815+#define MRV_ISP_ISP_OUT_H_SIZE_MASK 0x00003FFF
5816+#define MRV_ISP_ISP_OUT_H_SIZE_SHIFT 0
5817+
5818+#define MRV_ISP_ISP_OUT_V_SIZE
5819+#define MRV_ISP_ISP_OUT_V_SIZE_MASK 0x00000FFF
5820+#define MRV_ISP_ISP_OUT_V_SIZE_SHIFT 0
5821+
5822+#define MRV_ISP_DEMOSAIC_BYPASS
5823+#define MRV_ISP_DEMOSAIC_BYPASS_MASK 0x00000400
5824+#define MRV_ISP_DEMOSAIC_BYPASS_SHIFT 10
5825+
5826+#define MRV_ISP_DEMOSAIC_MODE
5827+#define MRV_ISP_DEMOSAIC_MODE_MASK 0x00000300
5828+#define MRV_ISP_DEMOSAIC_MODE_SHIFT 8
5829+#define MRV_ISP_DEMOSAIC_MODE_STD 0
5830+#define MRV_ISP_DEMOSAIC_MODE_ENH 1
5831+#define MRV_ISP_DEMOSAIC_TH
5832+#define MRV_ISP_DEMOSAIC_TH_MASK 0x000000FF
5833+#define MRV_ISP_DEMOSAIC_TH_SHIFT 0
5834+
5835+#define MRV_ISP_S_HSYNC
5836+
5837+#define MRV_ISP_S_HSYNC_MASK 0x80000000
5838+#define MRV_ISP_S_HSYNC_SHIFT 31
5839+
5840+#define MRV_ISP_S_VSYNC
5841+
5842+#define MRV_ISP_S_VSYNC_MASK 0x40000000
5843+#define MRV_ISP_S_VSYNC_SHIFT 30
5844+
5845+#define MRV_ISP_S_DATA
5846+
5847+#define MRV_ISP_S_DATA_MASK 0x0FFF0000
5848+
5849+#define MRV_ISP_S_DATA_SHIFT 16
5850+#define MRV_ISP_INFORM_FIELD
5851+#define MRV_ISP_INFORM_FIELD_MASK 0x00000004
5852+#define MRV_ISP_INFORM_FIELD_SHIFT 2
5853+#define MRV_ISP_INFORM_FIELD_ODD 0
5854+#define MRV_ISP_INFORM_FIELD_EVEN 1
5855+#define MRV_ISP_INFORM_EN_SHD
5856+#define MRV_ISP_INFORM_EN_SHD_MASK 0x00000002
5857+#define MRV_ISP_INFORM_EN_SHD_SHIFT 1
5858+#define MRV_ISP_ISP_ON_SHD
5859+#define MRV_ISP_ISP_ON_SHD_MASK 0x00000001
5860+#define MRV_ISP_ISP_ON_SHD_SHIFT 0
5861+
5862+
5863+#define MRV_ISP_ISP_OUT_H_OFFS_SHD
5864+#define MRV_ISP_ISP_OUT_H_OFFS_SHD_MASK 0x00000FFF
5865+#define MRV_ISP_ISP_OUT_H_OFFS_SHD_SHIFT 0
5866+
5867+#define MRV_ISP_ISP_OUT_V_OFFS_SHD
5868+#define MRV_ISP_ISP_OUT_V_OFFS_SHD_MASK 0x00000FFF
5869+#define MRV_ISP_ISP_OUT_V_OFFS_SHD_SHIFT 0
5870+
5871+
5872+#define MRV_ISP_ISP_OUT_H_SIZE_SHD
5873+#define MRV_ISP_ISP_OUT_H_SIZE_SHD_MASK 0x00003FFF
5874+#define MRV_ISP_ISP_OUT_H_SIZE_SHD_SHIFT 0
5875+
5876+
5877+#define MRV_ISP_ISP_OUT_V_SIZE_SHD
5878+#define MRV_ISP_ISP_OUT_V_SIZE_SHD_MASK 0x00000FFF
5879+#define MRV_ISP_ISP_OUT_V_SIZE_SHD_SHIFT 0
5880+
5881+#define MRV_ISP_IMSC_EXP_END
5882+#define MRV_ISP_IMSC_EXP_END_MASK 0x00040000
5883+#define MRV_ISP_IMSC_EXP_END_SHIFT 18
5884+
5885+#define MRV_ISP_IMSC_FLASH_CAP
5886+#define MRV_ISP_IMSC_FLASH_CAP_MASK 0x00020000
5887+#define MRV_ISP_IMSC_FLASH_CAP_SHIFT 17
5888+
5889+#define MRV_ISP_IMSC_BP_DET
5890+#define MRV_ISP_IMSC_BP_DET_MASK 0x00010000
5891+#define MRV_ISP_IMSC_BP_DET_SHIFT 16
5892+#define MRV_ISP_IMSC_BP_NEW_TAB_FUL
5893+#define MRV_ISP_IMSC_BP_NEW_TAB_FUL_MASK 0x00008000
5894+#define MRV_ISP_IMSC_BP_NEW_TAB_FUL_SHIFT 15
5895+#define MRV_ISP_IMSC_AFM_FIN
5896+#define MRV_ISP_IMSC_AFM_FIN_MASK 0x00004000
5897+#define MRV_ISP_IMSC_AFM_FIN_SHIFT 14
5898+#define MRV_ISP_IMSC_AFM_LUM_OF
5899+#define MRV_ISP_IMSC_AFM_LUM_OF_MASK 0x00002000
5900+#define MRV_ISP_IMSC_AFM_LUM_OF_SHIFT 13
5901+#define MRV_ISP_IMSC_AFM_SUM_OF
5902+#define MRV_ISP_IMSC_AFM_SUM_OF_MASK 0x00001000
5903+#define MRV_ISP_IMSC_AFM_SUM_OF_SHIFT 12
5904+#define MRV_ISP_IMSC_SHUTTER_OFF
5905+#define MRV_ISP_IMSC_SHUTTER_OFF_MASK 0x00000800
5906+#define MRV_ISP_IMSC_SHUTTER_OFF_SHIFT 11
5907+#define MRV_ISP_IMSC_SHUTTER_ON
5908+#define MRV_ISP_IMSC_SHUTTER_ON_MASK 0x00000400
5909+#define MRV_ISP_IMSC_SHUTTER_ON_SHIFT 10
5910+#define MRV_ISP_IMSC_FLASH_OFF
5911+#define MRV_ISP_IMSC_FLASH_OFF_MASK 0x00000200
5912+#define MRV_ISP_IMSC_FLASH_OFF_SHIFT 9
5913+#define MRV_ISP_IMSC_FLASH_ON
5914+#define MRV_ISP_IMSC_FLASH_ON_MASK 0x00000100
5915+#define MRV_ISP_IMSC_FLASH_ON_SHIFT 8
5916+
5917+#define MRV_ISP_IMSC_H_START
5918+#define MRV_ISP_IMSC_H_START_MASK 0x00000080
5919+#define MRV_ISP_IMSC_H_START_SHIFT 7
5920+#define MRV_ISP_IMSC_V_START
5921+#define MRV_ISP_IMSC_V_START_MASK 0x00000040
5922+#define MRV_ISP_IMSC_V_START_SHIFT 6
5923+#define MRV_ISP_IMSC_FRAME_IN
5924+#define MRV_ISP_IMSC_FRAME_IN_MASK 0x00000020
5925+#define MRV_ISP_IMSC_FRAME_IN_SHIFT 5
5926+#define MRV_ISP_IMSC_AWB_DONE
5927+#define MRV_ISP_IMSC_AWB_DONE_MASK 0x00000010
5928+#define MRV_ISP_IMSC_AWB_DONE_SHIFT 4
5929+#define MRV_ISP_IMSC_PIC_SIZE_ERR
5930+#define MRV_ISP_IMSC_PIC_SIZE_ERR_MASK 0x00000008
5931+#define MRV_ISP_IMSC_PIC_SIZE_ERR_SHIFT 3
5932+#define MRV_ISP_IMSC_DATA_LOSS
5933+#define MRV_ISP_IMSC_DATA_LOSS_MASK 0x00000004
5934+#define MRV_ISP_IMSC_DATA_LOSS_SHIFT 2
5935+#define MRV_ISP_IMSC_FRAME
5936+#define MRV_ISP_IMSC_FRAME_MASK 0x00000002
5937+#define MRV_ISP_IMSC_FRAME_SHIFT 1
5938+#define MRV_ISP_IMSC_ISP_OFF
5939+#define MRV_ISP_IMSC_ISP_OFF_MASK 0x00000001
5940+#define MRV_ISP_IMSC_ISP_OFF_SHIFT 0
5941+
5942+#define MRV_ISP_IMSC_ALL
5943+#define MRV_ISP_IMSC_ALL_MASK \
5944+(0 \
5945+| MRV_ISP_IMSC_EXP_END_MASK \
5946+| MRV_ISP_IMSC_FLASH_CAP_MASK \
5947+| MRV_ISP_IMSC_BP_DET_MASK \
5948+| MRV_ISP_IMSC_BP_NEW_TAB_FUL_MASK \
5949+| MRV_ISP_IMSC_AFM_FIN_MASK \
5950+| MRV_ISP_IMSC_AFM_LUM_OF_MASK \
5951+| MRV_ISP_IMSC_AFM_SUM_OF_MASK \
5952+| MRV_ISP_IMSC_SHUTTER_OFF_MASK \
5953+| MRV_ISP_IMSC_SHUTTER_ON_MASK \
5954+| MRV_ISP_IMSC_FLASH_OFF_MASK \
5955+| MRV_ISP_IMSC_FLASH_ON_MASK \
5956+| MRV_ISP_IMSC_H_START_MASK \
5957+| MRV_ISP_IMSC_V_START_MASK \
5958+| MRV_ISP_IMSC_FRAME_IN_MASK \
5959+| MRV_ISP_IMSC_AWB_DONE_MASK \
5960+| MRV_ISP_IMSC_PIC_SIZE_ERR_MASK \
5961+| MRV_ISP_IMSC_DATA_LOSS_MASK \
5962+| MRV_ISP_IMSC_FRAME_MASK \
5963+| MRV_ISP_IMSC_ISP_OFF_MASK \
5964+)
5965+#define MRV_ISP_IMSC_ALL_SHIFT 0
5966+
5967+#define MRV_ISP_RIS_EXP_END
5968+#define MRV_ISP_RIS_EXP_END_MASK 0x00040000
5969+#define MRV_ISP_RIS_EXP_END_SHIFT 18
5970+
5971+#define MRV_ISP_RIS_FLASH_CAP
5972+#define MRV_ISP_RIS_FLASH_CAP_MASK 0x00020000
5973+#define MRV_ISP_RIS_FLASH_CAP_SHIFT 17
5974+
5975+#define MRV_ISP_RIS_BP_DET
5976+#define MRV_ISP_RIS_BP_DET_MASK 0x00010000
5977+#define MRV_ISP_RIS_BP_DET_SHIFT 16
5978+#define MRV_ISP_RIS_BP_NEW_TAB_FUL
5979+#define MRV_ISP_RIS_BP_NEW_TAB_FUL_MASK 0x00008000
5980+#define MRV_ISP_RIS_BP_NEW_TAB_FUL_SHIFT 15
5981+#define MRV_ISP_RIS_AFM_FIN
5982+#define MRV_ISP_RIS_AFM_FIN_MASK 0x00004000
5983+#define MRV_ISP_RIS_AFM_FIN_SHIFT 14
5984+#define MRV_ISP_RIS_AFM_LUM_OF
5985+#define MRV_ISP_RIS_AFM_LUM_OF_MASK 0x00002000
5986+#define MRV_ISP_RIS_AFM_LUM_OF_SHIFT 13
5987+#define MRV_ISP_RIS_AFM_SUM_OF
5988+#define MRV_ISP_RIS_AFM_SUM_OF_MASK 0x00001000
5989+#define MRV_ISP_RIS_AFM_SUM_OF_SHIFT 12
5990+#define MRV_ISP_RIS_SHUTTER_OFF
5991+#define MRV_ISP_RIS_SHUTTER_OFF_MASK 0x00000800
5992+#define MRV_ISP_RIS_SHUTTER_OFF_SHIFT 11
5993+#define MRV_ISP_RIS_SHUTTER_ON
5994+#define MRV_ISP_RIS_SHUTTER_ON_MASK 0x00000400
5995+#define MRV_ISP_RIS_SHUTTER_ON_SHIFT 10
5996+#define MRV_ISP_RIS_FLASH_OFF
5997+#define MRV_ISP_RIS_FLASH_OFF_MASK 0x00000200
5998+#define MRV_ISP_RIS_FLASH_OFF_SHIFT 9
5999+#define MRV_ISP_RIS_FLASH_ON
6000+#define MRV_ISP_RIS_FLASH_ON_MASK 0x00000100
6001+#define MRV_ISP_RIS_FLASH_ON_SHIFT 8
6002+
6003+#define MRV_ISP_RIS_H_START
6004+#define MRV_ISP_RIS_H_START_MASK 0x00000080
6005+#define MRV_ISP_RIS_H_START_SHIFT 7
6006+#define MRV_ISP_RIS_V_START
6007+#define MRV_ISP_RIS_V_START_MASK 0x00000040
6008+#define MRV_ISP_RIS_V_START_SHIFT 6
6009+#define MRV_ISP_RIS_FRAME_IN
6010+#define MRV_ISP_RIS_FRAME_IN_MASK 0x00000020
6011+#define MRV_ISP_RIS_FRAME_IN_SHIFT 5
6012+#define MRV_ISP_RIS_AWB_DONE
6013+#define MRV_ISP_RIS_AWB_DONE_MASK 0x00000010
6014+#define MRV_ISP_RIS_AWB_DONE_SHIFT 4
6015+#define MRV_ISP_RIS_PIC_SIZE_ERR
6016+#define MRV_ISP_RIS_PIC_SIZE_ERR_MASK 0x00000008
6017+#define MRV_ISP_RIS_PIC_SIZE_ERR_SHIFT 3
6018+#define MRV_ISP_RIS_DATA_LOSS
6019+#define MRV_ISP_RIS_DATA_LOSS_MASK 0x00000004
6020+#define MRV_ISP_RIS_DATA_LOSS_SHIFT 2
6021+#define MRV_ISP_RIS_FRAME
6022+#define MRV_ISP_RIS_FRAME_MASK 0x00000002
6023+#define MRV_ISP_RIS_FRAME_SHIFT 1
6024+#define MRV_ISP_RIS_ISP_OFF
6025+#define MRV_ISP_RIS_ISP_OFF_MASK 0x00000001
6026+#define MRV_ISP_RIS_ISP_OFF_SHIFT 0
6027+
6028+#define MRV_ISP_RIS_ALL
6029+#define MRV_ISP_RIS_ALL_MASK \
6030+(0 \
6031+| MRV_ISP_RIS_EXP_END_MASK \
6032+| MRV_ISP_RIS_FLASH_CAP_MASK \
6033+| MRV_ISP_RIS_BP_DET_MASK \
6034+| MRV_ISP_RIS_BP_NEW_TAB_FUL_MASK \
6035+| MRV_ISP_RIS_AFM_FIN_MASK \
6036+| MRV_ISP_RIS_AFM_LUM_OF_MASK \
6037+| MRV_ISP_RIS_AFM_SUM_OF_MASK \
6038+| MRV_ISP_RIS_SHUTTER_OFF_MASK \
6039+| MRV_ISP_RIS_SHUTTER_ON_MASK \
6040+| MRV_ISP_RIS_FLASH_OFF_MASK \
6041+| MRV_ISP_RIS_FLASH_ON_MASK \
6042+| MRV_ISP_RIS_H_START_MASK \
6043+| MRV_ISP_RIS_V_START_MASK \
6044+| MRV_ISP_RIS_FRAME_IN_MASK \
6045+| MRV_ISP_RIS_AWB_DONE_MASK \
6046+| MRV_ISP_RIS_PIC_SIZE_ERR_MASK \
6047+| MRV_ISP_RIS_DATA_LOSS_MASK \
6048+| MRV_ISP_RIS_FRAME_MASK \
6049+| MRV_ISP_RIS_ISP_OFF_MASK \
6050+)
6051+#define MRV_ISP_RIS_ALL_SHIFT 0
6052+
6053+#define MRV_ISP_MIS_EXP_END
6054+#define MRV_ISP_MIS_EXP_END_MASK 0x00040000
6055+#define MRV_ISP_MIS_EXP_END_SHIFT 18
6056+
6057+#define MRV_ISP_MIS_FLASH_CAP
6058+#define MRV_ISP_MIS_FLASH_CAP_MASK 0x00020000
6059+#define MRV_ISP_MIS_FLASH_CAP_SHIFT 17
6060+
6061+#define MRV_ISP_MIS_BP_DET
6062+#define MRV_ISP_MIS_BP_DET_MASK 0x00010000
6063+#define MRV_ISP_MIS_BP_DET_SHIFT 16
6064+#define MRV_ISP_MIS_BP_NEW_TAB_FUL
6065+#define MRV_ISP_MIS_BP_NEW_TAB_FUL_MASK 0x00008000
6066+#define MRV_ISP_MIS_BP_NEW_TAB_FUL_SHIFT 15
6067+#define MRV_ISP_MIS_AFM_FIN
6068+#define MRV_ISP_MIS_AFM_FIN_MASK 0x00004000
6069+#define MRV_ISP_MIS_AFM_FIN_SHIFT 14
6070+#define MRV_ISP_MIS_AFM_LUM_OF
6071+#define MRV_ISP_MIS_AFM_LUM_OF_MASK 0x00002000
6072+#define MRV_ISP_MIS_AFM_LUM_OF_SHIFT 13
6073+#define MRV_ISP_MIS_AFM_SUM_OF
6074+#define MRV_ISP_MIS_AFM_SUM_OF_MASK 0x00001000
6075+#define MRV_ISP_MIS_AFM_SUM_OF_SHIFT 12
6076+#define MRV_ISP_MIS_SHUTTER_OFF
6077+#define MRV_ISP_MIS_SHUTTER_OFF_MASK 0x00000800
6078+#define MRV_ISP_MIS_SHUTTER_OFF_SHIFT 11
6079+#define MRV_ISP_MIS_SHUTTER_ON
6080+#define MRV_ISP_MIS_SHUTTER_ON_MASK 0x00000400
6081+#define MRV_ISP_MIS_SHUTTER_ON_SHIFT 10
6082+#define MRV_ISP_MIS_FLASH_OFF
6083+#define MRV_ISP_MIS_FLASH_OFF_MASK 0x00000200
6084+#define MRV_ISP_MIS_FLASH_OFF_SHIFT 9
6085+#define MRV_ISP_MIS_FLASH_ON
6086+#define MRV_ISP_MIS_FLASH_ON_MASK 0x00000100
6087+#define MRV_ISP_MIS_FLASH_ON_SHIFT 8
6088+
6089+#define MRV_ISP_MIS_H_START
6090+#define MRV_ISP_MIS_H_START_MASK 0x00000080
6091+#define MRV_ISP_MIS_H_START_SHIFT 7
6092+#define MRV_ISP_MIS_V_START
6093+#define MRV_ISP_MIS_V_START_MASK 0x00000040
6094+#define MRV_ISP_MIS_V_START_SHIFT 6
6095+#define MRV_ISP_MIS_FRAME_IN
6096+#define MRV_ISP_MIS_FRAME_IN_MASK 0x00000020
6097+#define MRV_ISP_MIS_FRAME_IN_SHIFT 5
6098+#define MRV_ISP_MIS_AWB_DONE
6099+#define MRV_ISP_MIS_AWB_DONE_MASK 0x00000010
6100+#define MRV_ISP_MIS_AWB_DONE_SHIFT 4
6101+#define MRV_ISP_MIS_PIC_SIZE_ERR
6102+#define MRV_ISP_MIS_PIC_SIZE_ERR_MASK 0x00000008
6103+#define MRV_ISP_MIS_PIC_SIZE_ERR_SHIFT 3
6104+#define MRV_ISP_MIS_DATA_LOSS
6105+#define MRV_ISP_MIS_DATA_LOSS_MASK 0x00000004
6106+#define MRV_ISP_MIS_DATA_LOSS_SHIFT 2
6107+#define MRV_ISP_MIS_FRAME
6108+#define MRV_ISP_MIS_FRAME_MASK 0x00000002
6109+#define MRV_ISP_MIS_FRAME_SHIFT 1
6110+#define MRV_ISP_MIS_ISP_OFF
6111+#define MRV_ISP_MIS_ISP_OFF_MASK 0x00000001
6112+#define MRV_ISP_MIS_ISP_OFF_SHIFT 0
6113+
6114+#define MRV_ISP_MIS_ALL
6115+#define MRV_ISP_MIS_ALL_MASK \
6116+(0 \
6117+| MRV_ISP_MIS_EXP_END_MASK \
6118+| MRV_ISP_MIS_FLASH_CAP_MASK \
6119+| MRV_ISP_MIS_BP_DET_MASK \
6120+| MRV_ISP_MIS_BP_NEW_TAB_FUL_MASK \
6121+| MRV_ISP_MIS_AFM_FIN_MASK \
6122+| MRV_ISP_MIS_AFM_LUM_OF_MASK \
6123+| MRV_ISP_MIS_AFM_SUM_OF_MASK \
6124+| MRV_ISP_MIS_SHUTTER_OFF_MASK \
6125+| MRV_ISP_MIS_SHUTTER_ON_MASK \
6126+| MRV_ISP_MIS_FLASH_OFF_MASK \
6127+| MRV_ISP_MIS_FLASH_ON_MASK \
6128+| MRV_ISP_MIS_H_START_MASK \
6129+| MRV_ISP_MIS_V_START_MASK \
6130+| MRV_ISP_MIS_FRAME_IN_MASK \
6131+| MRV_ISP_MIS_AWB_DONE_MASK \
6132+| MRV_ISP_MIS_PIC_SIZE_ERR_MASK \
6133+| MRV_ISP_MIS_DATA_LOSS_MASK \
6134+| MRV_ISP_MIS_FRAME_MASK \
6135+| MRV_ISP_MIS_ISP_OFF_MASK \
6136+)
6137+#define MRV_ISP_MIS_ALL_SHIFT 0
6138+
6139+#define MRV_ISP_ICR_EXP_END
6140+#define MRV_ISP_ICR_EXP_END_MASK 0x00040000
6141+#define MRV_ISP_ICR_EXP_END_SHIFT 18
6142+#define MRV_ISP_ICR_FLASH_CAP
6143+#define MRV_ISP_ICR_FLASH_CAP_MASK 0x00020000
6144+#define MRV_ISP_ICR_FLASH_CAP_SHIFT 17
6145+
6146+#define MRV_ISP_ICR_BP_DET
6147+#define MRV_ISP_ICR_BP_DET_MASK 0x00010000
6148+#define MRV_ISP_ICR_BP_DET_SHIFT 16
6149+#define MRV_ISP_ICR_BP_NEW_TAB_FUL
6150+#define MRV_ISP_ICR_BP_NEW_TAB_FUL_MASK 0x00008000
6151+#define MRV_ISP_ICR_BP_NEW_TAB_FUL_SHIFT 15
6152+#define MRV_ISP_ICR_AFM_FIN
6153+#define MRV_ISP_ICR_AFM_FIN_MASK 0x00004000
6154+#define MRV_ISP_ICR_AFM_FIN_SHIFT 14
6155+#define MRV_ISP_ICR_AFM_LUM_OF
6156+#define MRV_ISP_ICR_AFM_LUM_OF_MASK 0x00002000
6157+#define MRV_ISP_ICR_AFM_LUM_OF_SHIFT 13
6158+#define MRV_ISP_ICR_AFM_SUM_OF
6159+#define MRV_ISP_ICR_AFM_SUM_OF_MASK 0x00001000
6160+#define MRV_ISP_ICR_AFM_SUM_OF_SHIFT 12
6161+#define MRV_ISP_ICR_SHUTTER_OFF
6162+#define MRV_ISP_ICR_SHUTTER_OFF_MASK 0x00000800
6163+#define MRV_ISP_ICR_SHUTTER_OFF_SHIFT 11
6164+#define MRV_ISP_ICR_SHUTTER_ON
6165+#define MRV_ISP_ICR_SHUTTER_ON_MASK 0x00000400
6166+#define MRV_ISP_ICR_SHUTTER_ON_SHIFT 10
6167+#define MRV_ISP_ICR_FLASH_OFF
6168+#define MRV_ISP_ICR_FLASH_OFF_MASK 0x00000200
6169+#define MRV_ISP_ICR_FLASH_OFF_SHIFT 9
6170+#define MRV_ISP_ICR_FLASH_ON
6171+#define MRV_ISP_ICR_FLASH_ON_MASK 0x00000100
6172+#define MRV_ISP_ICR_FLASH_ON_SHIFT 8
6173+
6174+#define MRV_ISP_ICR_H_START
6175+#define MRV_ISP_ICR_H_START_MASK 0x00000080
6176+#define MRV_ISP_ICR_H_START_SHIFT 7
6177+#define MRV_ISP_ICR_V_START
6178+#define MRV_ISP_ICR_V_START_MASK 0x00000040
6179+#define MRV_ISP_ICR_V_START_SHIFT 6
6180+#define MRV_ISP_ICR_FRAME_IN
6181+#define MRV_ISP_ICR_FRAME_IN_MASK 0x00000020
6182+#define MRV_ISP_ICR_FRAME_IN_SHIFT 5
6183+#define MRV_ISP_ICR_AWB_DONE
6184+#define MRV_ISP_ICR_AWB_DONE_MASK 0x00000010
6185+#define MRV_ISP_ICR_AWB_DONE_SHIFT 4
6186+#define MRV_ISP_ICR_PIC_SIZE_ERR
6187+#define MRV_ISP_ICR_PIC_SIZE_ERR_MASK 0x00000008
6188+#define MRV_ISP_ICR_PIC_SIZE_ERR_SHIFT 3
6189+#define MRV_ISP_ICR_DATA_LOSS
6190+#define MRV_ISP_ICR_DATA_LOSS_MASK 0x00000004
6191+#define MRV_ISP_ICR_DATA_LOSS_SHIFT 2
6192+#define MRV_ISP_ICR_FRAME
6193+#define MRV_ISP_ICR_FRAME_MASK 0x00000002
6194+#define MRV_ISP_ICR_FRAME_SHIFT 1
6195+#define MRV_ISP_ICR_ISP_OFF
6196+#define MRV_ISP_ICR_ISP_OFF_MASK 0x00000001
6197+#define MRV_ISP_ICR_ISP_OFF_SHIFT 0
6198+
6199+#define MRV_ISP_ICR_ALL
6200+#define MRV_ISP_ICR_ALL_MASK \
6201+(0 \
6202+| MRV_ISP_ICR_EXP_END_MASK \
6203+| MRV_ISP_ICR_FLASH_CAP_MASK \
6204+| MRV_ISP_ICR_BP_DET_MASK \
6205+| MRV_ISP_ICR_BP_NEW_TAB_FUL_MASK \
6206+| MRV_ISP_ICR_AFM_FIN_MASK \
6207+| MRV_ISP_ICR_AFM_LUM_OF_MASK \
6208+| MRV_ISP_ICR_AFM_SUM_OF_MASK \
6209+| MRV_ISP_ICR_SHUTTER_OFF_MASK \
6210+| MRV_ISP_ICR_SHUTTER_ON_MASK \
6211+| MRV_ISP_ICR_FLASH_OFF_MASK \
6212+| MRV_ISP_ICR_FLASH_ON_MASK \
6213+| MRV_ISP_ICR_H_START_MASK \
6214+| MRV_ISP_ICR_V_START_MASK \
6215+| MRV_ISP_ICR_FRAME_IN_MASK \
6216+| MRV_ISP_ICR_AWB_DONE_MASK \
6217+| MRV_ISP_ICR_PIC_SIZE_ERR_MASK \
6218+| MRV_ISP_ICR_DATA_LOSS_MASK \
6219+| MRV_ISP_ICR_FRAME_MASK \
6220+| MRV_ISP_ICR_ISP_OFF_MASK \
6221+)
6222+#define MRV_ISP_ICR_ALL_SHIFT 0
6223+
6224+#define MRV_ISP_ISR_EXP_END
6225+#define MRV_ISP_ISR_EXP_END_MASK 0x00040000
6226+#define MRV_ISP_ISR_EXP_END_SHIFT 18
6227+#define MRV_ISP_ISR_FLASH_CAP
6228+#define MRV_ISP_ISR_FLASH_CAP_MASK 0x00020000
6229+#define MRV_ISP_ISR_FLASH_CAP_SHIFT 17
6230+
6231+#define MRV_ISP_ISR_BP_DET
6232+#define MRV_ISP_ISR_BP_DET_MASK 0x00010000
6233+#define MRV_ISP_ISR_BP_DET_SHIFT 16
6234+#define MRV_ISP_ISR_BP_NEW_TAB_FUL
6235+#define MRV_ISP_ISR_BP_NEW_TAB_FUL_MASK 0x00008000
6236+#define MRV_ISP_ISR_BP_NEW_TAB_FUL_SHIFT 15
6237+#define MRV_ISP_ISR_AFM_FIN
6238+#define MRV_ISP_ISR_AFM_FIN_MASK 0x00004000
6239+#define MRV_ISP_ISR_AFM_FIN_SHIFT 14
6240+#define MRV_ISP_ISR_AFM_LUM_OF
6241+#define MRV_ISP_ISR_AFM_LUM_OF_MASK 0x00002000
6242+#define MRV_ISP_ISR_AFM_LUM_OF_SHIFT 13
6243+#define MRV_ISP_ISR_AFM_SUM_OF
6244+#define MRV_ISP_ISR_AFM_SUM_OF_MASK 0x00001000
6245+#define MRV_ISP_ISR_AFM_SUM_OF_SHIFT 12
6246+#define MRV_ISP_ISR_SHUTTER_OFF
6247+#define MRV_ISP_ISR_SHUTTER_OFF_MASK 0x00000800
6248+#define MRV_ISP_ISR_SHUTTER_OFF_SHIFT 11
6249+#define MRV_ISP_ISR_SHUTTER_ON
6250+#define MRV_ISP_ISR_SHUTTER_ON_MASK 0x00000400
6251+#define MRV_ISP_ISR_SHUTTER_ON_SHIFT 10
6252+#define MRV_ISP_ISR_FLASH_OFF
6253+#define MRV_ISP_ISR_FLASH_OFF_MASK 0x00000200
6254+#define MRV_ISP_ISR_FLASH_OFF_SHIFT 9
6255+#define MRV_ISP_ISR_FLASH_ON
6256+#define MRV_ISP_ISR_FLASH_ON_MASK 0x00000100
6257+#define MRV_ISP_ISR_FLASH_ON_SHIFT 8
6258+
6259+#define MRV_ISP_ISR_H_START
6260+#define MRV_ISP_ISR_H_START_MASK 0x00000080
6261+#define MRV_ISP_ISR_H_START_SHIFT 7
6262+#define MRV_ISP_ISR_V_START
6263+#define MRV_ISP_ISR_V_START_MASK 0x00000040
6264+#define MRV_ISP_ISR_V_START_SHIFT 6
6265+#define MRV_ISP_ISR_FRAME_IN
6266+#define MRV_ISP_ISR_FRAME_IN_MASK 0x00000020
6267+#define MRV_ISP_ISR_FRAME_IN_SHIFT 5
6268+#define MRV_ISP_ISR_AWB_DONE
6269+#define MRV_ISP_ISR_AWB_DONE_MASK 0x00000010
6270+#define MRV_ISP_ISR_AWB_DONE_SHIFT 4
6271+#define MRV_ISP_ISR_PIC_SIZE_ERR
6272+#define MRV_ISP_ISR_PIC_SIZE_ERR_MASK 0x00000008
6273+#define MRV_ISP_ISR_PIC_SIZE_ERR_SHIFT 3
6274+#define MRV_ISP_ISR_DATA_LOSS
6275+#define MRV_ISP_ISR_DATA_LOSS_MASK 0x00000004
6276+#define MRV_ISP_ISR_DATA_LOSS_SHIFT 2
6277+#define MRV_ISP_ISR_FRAME
6278+#define MRV_ISP_ISR_FRAME_MASK 0x00000002
6279+#define MRV_ISP_ISR_FRAME_SHIFT 1
6280+#define MRV_ISP_ISR_ISP_OFF
6281+#define MRV_ISP_ISR_ISP_OFF_MASK 0x00000001
6282+#define MRV_ISP_ISR_ISP_OFF_SHIFT 0
6283+
6284+#define MRV_ISP_ISR_ALL
6285+#define MRV_ISP_ISR_ALL_MASK \
6286+(0 \
6287+| MRV_ISP_ISR_EXP_END_MASK \
6288+| MRV_ISP_ISR_FLASH_CAP_MASK \
6289+| MRV_ISP_ISR_BP_DET_MASK \
6290+| MRV_ISP_ISR_BP_NEW_TAB_FUL_MASK \
6291+| MRV_ISP_ISR_AFM_FIN_MASK \
6292+| MRV_ISP_ISR_AFM_LUM_OF_MASK \
6293+| MRV_ISP_ISR_AFM_SUM_OF_MASK \
6294+| MRV_ISP_ISR_SHUTTER_OFF_MASK \
6295+| MRV_ISP_ISR_SHUTTER_ON_MASK \
6296+| MRV_ISP_ISR_FLASH_OFF_MASK \
6297+| MRV_ISP_ISR_FLASH_ON_MASK \
6298+| MRV_ISP_ISR_H_START_MASK \
6299+| MRV_ISP_ISR_V_START_MASK \
6300+| MRV_ISP_ISR_FRAME_IN_MASK \
6301+| MRV_ISP_ISR_AWB_DONE_MASK \
6302+| MRV_ISP_ISR_PIC_SIZE_ERR_MASK \
6303+| MRV_ISP_ISR_DATA_LOSS_MASK \
6304+| MRV_ISP_ISR_FRAME_MASK \
6305+| MRV_ISP_ISR_ISP_OFF_MASK \
6306+)
6307+#define MRV_ISP_ISR_ALL_SHIFT 0
6308+
6309+#define MRV_ISP_CT_COEFF
6310+#define MRV_ISP_CT_COEFF_MASK 0x000007FF
6311+#define MRV_ISP_CT_COEFF_SHIFT 0
6312+#define MRV_ISP_CT_COEFF_MAX (MRV_ISP_CT_COEFF_MASK >> MRV_ISP_CT_COEFF_SHIFT)
6313+
6314+#define MRV_ISP_EQU_SEGM
6315+#define MRV_ISP_EQU_SEGM_MASK 0x00000001
6316+#define MRV_ISP_EQU_SEGM_SHIFT 0
6317+#define MRV_ISP_EQU_SEGM_LOG 0
6318+#define MRV_ISP_EQU_SEGM_EQU 1
6319+
6320+#define MRV_ISP_ISP_GAMMA_OUT_Y
6321+#define MRV_ISP_ISP_GAMMA_OUT_Y_MASK 0x000003FF
6322+#define MRV_ISP_ISP_GAMMA_OUT_Y_SHIFT 0
6323+
6324+#define MRV_ISP_OUTFORM_SIZE_ERR
6325+#define MRV_ISP_OUTFORM_SIZE_ERR_MASK 0x00000004
6326+#define MRV_ISP_OUTFORM_SIZE_ERR_SHIFT 2
6327+#define MRV_ISP_IS_SIZE_ERR
6328+#define MRV_ISP_IS_SIZE_ERR_MASK 0x00000002
6329+#define MRV_ISP_IS_SIZE_ERR_SHIFT 1
6330+#define MRV_ISP_INFORM_SIZE_ERR
6331+#define MRV_ISP_INFORM_SIZE_ERR_MASK 0x00000001
6332+#define MRV_ISP_INFORM_SIZE_ERR_SHIFT 0
6333+
6334+#define MRV_ISP_ALL_ERR
6335+#define MRV_ISP_ALL_ERR_MASK \
6336+(0 \
6337+| MRV_ISP_OUTFORM_SIZE_ERR_MASK \
6338+| MRV_ISP_IS_SIZE_ERR_MASK \
6339+| MRV_ISP_INFORM_SIZE_ERR_MASK \
6340+)
6341+#define MRV_ISP_ALL_ERR_SHIFT 0
6342+
6343+#define MRV_ISP_OUTFORM_SIZE_ERR_CLR
6344+#define MRV_ISP_OUTFORM_SIZE_ERR_CLR_MASK 0x00000004
6345+#define MRV_ISP_OUTFORM_SIZE_ERR_CLR_SHIFT 2
6346+#define MRV_ISP_IS_SIZE_ERR_CLR
6347+#define MRV_ISP_IS_SIZE_ERR_CLR_MASK 0x00000002
6348+#define MRV_ISP_IS_SIZE_ERR_CLR_SHIFT 1
6349+#define MRV_ISP_INFORM_SIZE_ERR_CLR
6350+#define MRV_ISP_INFORM_SIZE_ERR_CLR_MASK 0x00000001
6351+#define MRV_ISP_INFORM_SIZE_ERR_CLR_SHIFT 0
6352+
6353+
6354+#define MRV_ISP_FRAME_COUNTER
6355+#define MRV_ISP_FRAME_COUNTER_MASK 0x000003FF
6356+#define MRV_ISP_FRAME_COUNTER_SHIFT 0
6357+
6358+#define MRV_ISP_CT_OFFSET_R
6359+#define MRV_ISP_CT_OFFSET_R_MASK 0x00000FFF
6360+#define MRV_ISP_CT_OFFSET_R_SHIFT 0
6361+
6362+#define MRV_ISP_CT_OFFSET_G
6363+#define MRV_ISP_CT_OFFSET_G_MASK 0x00000FFF
6364+#define MRV_ISP_CT_OFFSET_G_SHIFT 0
6365+
6366+#define MRV_ISP_CT_OFFSET_B
6367+#define MRV_ISP_CT_OFFSET_B_MASK 0x00000FFF
6368+#define MRV_ISP_CT_OFFSET_B_SHIFT 0
6369+
6370+
6371+#define MRV_FLASH_PREFLASH_ON
6372+#define MRV_FLASH_PREFLASH_ON_MASK 0x00000004
6373+#define MRV_FLASH_PREFLASH_ON_SHIFT 2
6374+#define MRV_FLASH_FLASH_ON
6375+#define MRV_FLASH_FLASH_ON_MASK 0x00000002
6376+#define MRV_FLASH_FLASH_ON_SHIFT 1
6377+#define MRV_FLASH_PRELIGHT_ON
6378+#define MRV_FLASH_PRELIGHT_ON_MASK 0x00000001
6379+#define MRV_FLASH_PRELIGHT_ON_SHIFT 0
6380+
6381+#define MRV_FLASH_FL_CAP_DEL
6382+#define MRV_FLASH_FL_CAP_DEL_MASK 0x000000F0
6383+#define MRV_FLASH_FL_CAP_DEL_SHIFT 4
6384+#define MRV_FLASH_FL_CAP_DEL_MAX \
6385+ (MRV_FLASH_FL_CAP_DEL_MASK >> MRV_FLASH_FL_CAP_DEL_SHIFT)
6386+#define MRV_FLASH_FL_TRIG_SRC
6387+#define MRV_FLASH_FL_TRIG_SRC_MASK 0x00000008
6388+#define MRV_FLASH_FL_TRIG_SRC_SHIFT 3
6389+#define MRV_FLASH_FL_TRIG_SRC_VDS 0
6390+#define MRV_FLASH_FL_TRIG_SRC_FL 1
6391+#define MRV_FLASH_FL_POL
6392+#define MRV_FLASH_FL_POL_MASK 0x00000004
6393+#define MRV_FLASH_FL_POL_SHIFT 2
6394+#define MRV_FLASH_FL_POL_HIGH 0
6395+#define MRV_FLASH_FL_POL_LOW 1
6396+#define MRV_FLASH_VS_IN_EDGE
6397+#define MRV_FLASH_VS_IN_EDGE_MASK 0x00000002
6398+#define MRV_FLASH_VS_IN_EDGE_SHIFT 1
6399+#define MRV_FLASH_VS_IN_EDGE_NEG 0
6400+#define MRV_FLASH_VS_IN_EDGE_POS 1
6401+#define MRV_FLASH_PRELIGHT_MODE
6402+#define MRV_FLASH_PRELIGHT_MODE_MASK 0x00000001
6403+#define MRV_FLASH_PRELIGHT_MODE_SHIFT 0
6404+#define MRV_FLASH_PRELIGHT_MODE_OASF 0
6405+#define MRV_FLASH_PRELIGHT_MODE_OAEF 1
6406+
6407+#define MRV_FLASH_FL_PRE_DIV
6408+#define MRV_FLASH_FL_PRE_DIV_MASK 0x000003FF
6409+#define MRV_FLASH_FL_PRE_DIV_SHIFT 0
6410+#define MRV_FLASH_FL_PRE_DIV_MAX \
6411+ (MRV_FLASH_FL_PRE_DIV_MASK >> MRV_FLASH_FL_PRE_DIV_SHIFT)
6412+
6413+#define MRV_FLASH_FL_DELAY
6414+#define MRV_FLASH_FL_DELAY_MASK 0x0003FFFF
6415+#define MRV_FLASH_FL_DELAY_SHIFT 0
6416+#define MRV_FLASH_FL_DELAY_MAX \
6417+ (MRV_FLASH_FL_DELAY_MASK >> MRV_FLASH_FL_DELAY_SHIFT)
6418+
6419+#define MRV_FLASH_FL_TIME
6420+#define MRV_FLASH_FL_TIME_MASK 0x0003FFFF
6421+#define MRV_FLASH_FL_TIME_SHIFT 0
6422+#define MRV_FLASH_FL_TIME_MAX \
6423+ (MRV_FLASH_FL_TIME_MASK >> MRV_FLASH_FL_TIME_SHIFT)
6424+
6425+#define MRV_FLASH_FL_MAXP
6426+#define MRV_FLASH_FL_MAXP_MASK 0x0000FFFF
6427+#define MRV_FLASH_FL_MAXP_SHIFT 0
6428+#define MRV_FLASH_FL_MAXP_MAX \
6429+ (MRV_FLASH_FL_MAXP_MASK >> MRV_FLASH_FL_MAXP_SHIFT)
6430+
6431+#define MRV_SHUT_SH_OPEN_POL
6432+#define MRV_SHUT_SH_OPEN_POL_MASK 0x00000010
6433+#define MRV_SHUT_SH_OPEN_POL_SHIFT 4
6434+#define MRV_SHUT_SH_OPEN_POL_HIGH 0
6435+#define MRV_SHUT_SH_OPEN_POL_LOW 1
6436+#define MRV_SHUT_SH_TRIG_EN
6437+#define MRV_SHUT_SH_TRIG_EN_MASK 0x00000008
6438+#define MRV_SHUT_SH_TRIG_EN_SHIFT 3
6439+#define MRV_SHUT_SH_TRIG_EN_NEG 0
6440+#define MRV_SHUT_SH_TRIG_EN_POS 1
6441+#define MRV_SHUT_SH_TRIG_SRC
6442+#define MRV_SHUT_SH_TRIG_SRC_MASK 0x00000004
6443+#define MRV_SHUT_SH_TRIG_SRC_SHIFT 2
6444+#define MRV_SHUT_SH_TRIG_SRC_VDS 0
6445+#define MRV_SHUT_SH_TRIG_SRC_SHUT 1
6446+#define MRV_SHUT_SH_REP_EN
6447+#define MRV_SHUT_SH_REP_EN_MASK 0x00000002
6448+#define MRV_SHUT_SH_REP_EN_SHIFT 1
6449+#define MRV_SHUT_SH_REP_EN_ONCE 0
6450+#define MRV_SHUT_SH_REP_EN_REP 1
6451+#define MRV_SHUT_SH_EN
6452+#define MRV_SHUT_SH_EN_MASK 0x00000001
6453+#define MRV_SHUT_SH_EN_SHIFT 0
6454+
6455+#define MRV_SHUT_SH_PRE_DIV
6456+#define MRV_SHUT_SH_PRE_DIV_MASK 0x000003FF
6457+#define MRV_SHUT_SH_PRE_DIV_SHIFT 0
6458+#define MRV_SHUT_SH_PRE_DIV_MAX \
6459+ (MRV_SHUT_SH_PRE_DIV_MASK >> MRV_SHUT_SH_PRE_DIV_SHIFT)
6460+
6461+#define MRV_SHUT_SH_DELAY
6462+#define MRV_SHUT_SH_DELAY_MASK 0x000FFFFF
6463+#define MRV_SHUT_SH_DELAY_SHIFT 0
6464+#define MRV_SHUT_SH_DELAY_MAX \
6465+ (MRV_SHUT_SH_DELAY_MASK >> MRV_SHUT_SH_DELAY_SHIFT)
6466+
6467+#define MRV_SHUT_SH_TIME
6468+#define MRV_SHUT_SH_TIME_MASK 0x000FFFFF
6469+#define MRV_SHUT_SH_TIME_SHIFT 0
6470+#define MRV_SHUT_SH_TIME_MAX (MRV_SHUT_SH_TIME_MASK >> MRV_SHUT_SH_TIME_SHIFT)
6471+
6472+#define MRV_CPROC_CPROC_C_OUT_RANGE
6473+#define MRV_CPROC_CPROC_C_OUT_RANGE_MASK 0x00000008
6474+#define MRV_CPROC_CPROC_C_OUT_RANGE_SHIFT 3
6475+#define MRV_CPROC_CPROC_C_OUT_RANGE_BT601 0
6476+#define MRV_CPROC_CPROC_C_OUT_RANGE_FULL 1
6477+#define MRV_CPROC_CPROC_Y_IN_RANGE
6478+#define MRV_CPROC_CPROC_Y_IN_RANGE_MASK 0x00000004
6479+#define MRV_CPROC_CPROC_Y_IN_RANGE_SHIFT 2
6480+#define MRV_CPROC_CPROC_Y_IN_RANGE_BT601 0
6481+#define MRV_CPROC_CPROC_Y_IN_RANGE_FULL 1
6482+#define MRV_CPROC_CPROC_Y_OUT_RANGE
6483+#define MRV_CPROC_CPROC_Y_OUT_RANGE_MASK 0x00000002
6484+#define MRV_CPROC_CPROC_Y_OUT_RANGE_SHIFT 1
6485+#define MRV_CPROC_CPROC_Y_OUT_RANGE_BT601 0
6486+#define MRV_CPROC_CPROC_Y_OUT_RANGE_FULL 1
6487+#define MRV_CPROC_CPROC_ENABLE
6488+#define MRV_CPROC_CPROC_ENABLE_MASK 0x00000001
6489+#define MRV_CPROC_CPROC_ENABLE_SHIFT 0
6490+
6491+#define MRV_CPROC_CPROC_CONTRAST
6492+#define MRV_CPROC_CPROC_CONTRAST_MASK 0x000000FF
6493+#define MRV_CPROC_CPROC_CONTRAST_SHIFT 0
6494+
6495+#define MRV_CPROC_CPROC_BRIGHTNESS
6496+#define MRV_CPROC_CPROC_BRIGHTNESS_MASK 0x000000FF
6497+#define MRV_CPROC_CPROC_BRIGHTNESS_SHIFT 0
6498+
6499+#define MRV_CPROC_CPROC_SATURATION
6500+#define MRV_CPROC_CPROC_SATURATION_MASK 0x000000FF
6501+#define MRV_CPROC_CPROC_SATURATION_SHIFT 0
6502+
6503+#define MRV_CPROC_CPROC_HUE
6504+#define MRV_CPROC_CPROC_HUE_MASK 0x000000FF
6505+#define MRV_CPROC_CPROC_HUE_SHIFT 0
6506+
6507+#define MRV_RSZ_SCALE
6508+
6509+#define MRV_RSZ_SCALE_MASK 0x00003FFF
6510+
6511+#define MRV_RSZ_SCALE_SHIFT 0
6512+#define MRV_RSZ_SCALE_MAX (MRV_RSZ_SCALE_MASK >> MRV_RSZ_SCALE_SHIFT)
6513+
6514+
6515+
6516+#define MRV_MRSZ_CFG_UPD
6517+#define MRV_MRSZ_CFG_UPD_MASK 0x00000100
6518+#define MRV_MRSZ_CFG_UPD_SHIFT 8
6519+#define MRV_MRSZ_SCALE_VC_UP
6520+#define MRV_MRSZ_SCALE_VC_UP_MASK 0x00000080
6521+#define MRV_MRSZ_SCALE_VC_UP_SHIFT 7
6522+#define MRV_MRSZ_SCALE_VC_UP_UPSCALE 1
6523+#define MRV_MRSZ_SCALE_VC_UP_DOWNSCALE 0
6524+#define MRV_MRSZ_SCALE_VY_UP
6525+#define MRV_MRSZ_SCALE_VY_UP_MASK 0x00000040
6526+#define MRV_MRSZ_SCALE_VY_UP_SHIFT 6
6527+#define MRV_MRSZ_SCALE_VY_UP_UPSCALE 1
6528+#define MRV_MRSZ_SCALE_VY_UP_DOWNSCALE 0
6529+#define MRV_MRSZ_SCALE_HC_UP
6530+#define MRV_MRSZ_SCALE_HC_UP_MASK 0x00000020
6531+#define MRV_MRSZ_SCALE_HC_UP_SHIFT 5
6532+#define MRV_MRSZ_SCALE_HC_UP_UPSCALE 1
6533+#define MRV_MRSZ_SCALE_HC_UP_DOWNSCALE 0
6534+#define MRV_MRSZ_SCALE_HY_UP
6535+#define MRV_MRSZ_SCALE_HY_UP_MASK 0x00000010
6536+#define MRV_MRSZ_SCALE_HY_UP_SHIFT 4
6537+#define MRV_MRSZ_SCALE_HY_UP_UPSCALE 1
6538+#define MRV_MRSZ_SCALE_HY_UP_DOWNSCALE 0
6539+#define MRV_MRSZ_SCALE_VC_ENABLE
6540+#define MRV_MRSZ_SCALE_VC_ENABLE_MASK 0x00000008
6541+#define MRV_MRSZ_SCALE_VC_ENABLE_SHIFT 3
6542+#define MRV_MRSZ_SCALE_VY_ENABLE
6543+#define MRV_MRSZ_SCALE_VY_ENABLE_MASK 0x00000004
6544+#define MRV_MRSZ_SCALE_VY_ENABLE_SHIFT 2
6545+#define MRV_MRSZ_SCALE_HC_ENABLE
6546+#define MRV_MRSZ_SCALE_HC_ENABLE_MASK 0x00000002
6547+#define MRV_MRSZ_SCALE_HC_ENABLE_SHIFT 1
6548+#define MRV_MRSZ_SCALE_HY_ENABLE
6549+#define MRV_MRSZ_SCALE_HY_ENABLE_MASK 0x00000001
6550+#define MRV_MRSZ_SCALE_HY_ENABLE_SHIFT 0
6551+
6552+#define MRV_MRSZ_SCALE_HY
6553+#define MRV_MRSZ_SCALE_HY_MASK MRV_RSZ_SCALE_MASK
6554+#define MRV_MRSZ_SCALE_HY_SHIFT MRV_RSZ_SCALE_SHIFT
6555+
6556+#define MRV_MRSZ_SCALE_HCB
6557+#define MRV_MRSZ_SCALE_HCB_MASK MRV_RSZ_SCALE_MASK
6558+#define MRV_MRSZ_SCALE_HCB_SHIFT MRV_RSZ_SCALE_SHIFT
6559+
6560+#define MRV_MRSZ_SCALE_HCR
6561+#define MRV_MRSZ_SCALE_HCR_MASK MRV_RSZ_SCALE_MASK
6562+#define MRV_MRSZ_SCALE_HCR_SHIFT MRV_RSZ_SCALE_SHIFT
6563+
6564+#define MRV_MRSZ_SCALE_VY
6565+#define MRV_MRSZ_SCALE_VY_MASK MRV_RSZ_SCALE_MASK
6566+#define MRV_MRSZ_SCALE_VY_SHIFT MRV_RSZ_SCALE_SHIFT
6567+
6568+#define MRV_MRSZ_SCALE_VC
6569+#define MRV_MRSZ_SCALE_VC_MASK MRV_RSZ_SCALE_MASK
6570+#define MRV_MRSZ_SCALE_VC_SHIFT MRV_RSZ_SCALE_SHIFT
6571+
6572+
6573+#define MRV_MRSZ_PHASE_HY
6574+#define MRV_MRSZ_PHASE_HY_MASK MRV_RSZ_SCALE_MASK
6575+#define MRV_MRSZ_PHASE_HY_SHIFT MRV_RSZ_SCALE_SHIFT
6576+
6577+
6578+#define MRV_MRSZ_PHASE_HC
6579+#define MRV_MRSZ_PHASE_HC_MASK MRV_RSZ_SCALE_MASK
6580+#define MRV_MRSZ_PHASE_HC_SHIFT MRV_RSZ_SCALE_SHIFT
6581+
6582+
6583+#define MRV_MRSZ_PHASE_VY
6584+#define MRV_MRSZ_PHASE_VY_MASK MRV_RSZ_SCALE_MASK
6585+#define MRV_MRSZ_PHASE_VY_SHIFT MRV_RSZ_SCALE_SHIFT
6586+
6587+
6588+#define MRV_MRSZ_PHASE_VC
6589+#define MRV_MRSZ_PHASE_VC_MASK MRV_RSZ_SCALE_MASK
6590+#define MRV_MRSZ_PHASE_VC_SHIFT MRV_RSZ_SCALE_SHIFT
6591+
6592+
6593+#define MRV_MRSZ_SCALE_LUT_ADDR
6594+#define MRV_MRSZ_SCALE_LUT_ADDR_MASK 0x0000003F
6595+#define MRV_MRSZ_SCALE_LUT_ADDR_SHIFT 0
6596+
6597+
6598+#define MRV_MRSZ_SCALE_LUT
6599+#define MRV_MRSZ_SCALE_LUT_MASK 0x0000003F
6600+#define MRV_MRSZ_SCALE_LUT_SHIFT 0
6601+
6602+
6603+#define MRV_MRSZ_SCALE_VC_UP_SHD
6604+#define MRV_MRSZ_SCALE_VC_UP_SHD_MASK 0x00000080
6605+#define MRV_MRSZ_SCALE_VC_UP_SHD_SHIFT 7
6606+#define MRV_MRSZ_SCALE_VC_UP_SHD_UPSCALE 1
6607+#define MRV_MRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0
6608+#define MRV_MRSZ_SCALE_VY_UP_SHD
6609+#define MRV_MRSZ_SCALE_VY_UP_SHD_MASK 0x00000040
6610+#define MRV_MRSZ_SCALE_VY_UP_SHD_SHIFT 6
6611+#define MRV_MRSZ_SCALE_VY_UP_SHD_UPSCALE 1
6612+#define MRV_MRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0
6613+#define MRV_MRSZ_SCALE_HC_UP_SHD
6614+#define MRV_MRSZ_SCALE_HC_UP_SHD_MASK 0x00000020
6615+#define MRV_MRSZ_SCALE_HC_UP_SHD_SHIFT 5
6616+#define MRV_MRSZ_SCALE_HC_UP_SHD_UPSCALE 1
6617+#define MRV_MRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0
6618+#define MRV_MRSZ_SCALE_HY_UP_SHD
6619+#define MRV_MRSZ_SCALE_HY_UP_SHD_MASK 0x00000010
6620+#define MRV_MRSZ_SCALE_HY_UP_SHD_SHIFT 4
6621+#define MRV_MRSZ_SCALE_HY_UP_SHD_UPSCALE 1
6622+#define MRV_MRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0
6623+#define MRV_MRSZ_SCALE_VC_ENABLE_SHD
6624+#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008
6625+#define MRV_MRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3
6626+#define MRV_MRSZ_SCALE_VY_ENABLE_SHD
6627+#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004
6628+#define MRV_MRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2
6629+#define MRV_MRSZ_SCALE_HC_ENABLE_SHD
6630+#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002
6631+#define MRV_MRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1
6632+#define MRV_MRSZ_SCALE_HY_ENABLE_SHD
6633+#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001
6634+#define MRV_MRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0
6635+
6636+#define MRV_MRSZ_SCALE_HY_SHD
6637+#define MRV_MRSZ_SCALE_HY_SHD_MASK MRV_RSZ_SCALE_MASK
6638+#define MRV_MRSZ_SCALE_HY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6639+
6640+#define MRV_MRSZ_SCALE_HCB_SHD
6641+#define MRV_MRSZ_SCALE_HCB_SHD_MASK MRV_RSZ_SCALE_MASK
6642+#define MRV_MRSZ_SCALE_HCB_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6643+
6644+#define MRV_MRSZ_SCALE_HCR_SHD
6645+#define MRV_MRSZ_SCALE_HCR_SHD_MASK MRV_RSZ_SCALE_MASK
6646+#define MRV_MRSZ_SCALE_HCR_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6647+
6648+
6649+#define MRV_MRSZ_SCALE_VY_SHD
6650+#define MRV_MRSZ_SCALE_VY_SHD_MASK MRV_RSZ_SCALE_MASK
6651+#define MRV_MRSZ_SCALE_VY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6652+
6653+#define MRV_MRSZ_SCALE_VC_SHD
6654+#define MRV_MRSZ_SCALE_VC_SHD_MASK MRV_RSZ_SCALE_MASK
6655+#define MRV_MRSZ_SCALE_VC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6656+
6657+#define MRV_MRSZ_PHASE_HY_SHD
6658+#define MRV_MRSZ_PHASE_HY_SHD_MASK MRV_RSZ_SCALE_MASK
6659+#define MRV_MRSZ_PHASE_HY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6660+
6661+#define MRV_MRSZ_PHASE_HC_SHD
6662+#define MRV_MRSZ_PHASE_HC_SHD_MASK MRV_RSZ_SCALE_MASK
6663+#define MRV_MRSZ_PHASE_HC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6664+
6665+#define MRV_MRSZ_PHASE_VY_SHD
6666+#define MRV_MRSZ_PHASE_VY_SHD_MASK MRV_RSZ_SCALE_MASK
6667+#define MRV_MRSZ_PHASE_VY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6668+
6669+#define MRV_MRSZ_PHASE_VC_SHD
6670+#define MRV_MRSZ_PHASE_VC_SHD_MASK MRV_RSZ_SCALE_MASK
6671+#define MRV_MRSZ_PHASE_VC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6672+
6673+#define MRV_SRSZ_CFG_UPD
6674+#define MRV_SRSZ_CFG_UPD_MASK 0x00000100
6675+#define MRV_SRSZ_CFG_UPD_SHIFT 8
6676+#define MRV_SRSZ_SCALE_VC_UP
6677+#define MRV_SRSZ_SCALE_VC_UP_MASK 0x00000080
6678+#define MRV_SRSZ_SCALE_VC_UP_SHIFT 7
6679+#define MRV_SRSZ_SCALE_VC_UP_UPSCALE 1
6680+#define MRV_SRSZ_SCALE_VC_UP_DOWNSCALE 0
6681+#define MRV_SRSZ_SCALE_VY_UP
6682+#define MRV_SRSZ_SCALE_VY_UP_MASK 0x00000040
6683+#define MRV_SRSZ_SCALE_VY_UP_SHIFT 6
6684+#define MRV_SRSZ_SCALE_VY_UP_UPSCALE 1
6685+#define MRV_SRSZ_SCALE_VY_UP_DOWNSCALE 0
6686+#define MRV_SRSZ_SCALE_HC_UP
6687+#define MRV_SRSZ_SCALE_HC_UP_MASK 0x00000020
6688+#define MRV_SRSZ_SCALE_HC_UP_SHIFT 5
6689+#define MRV_SRSZ_SCALE_HC_UP_UPSCALE 1
6690+#define MRV_SRSZ_SCALE_HC_UP_DOWNSCALE 0
6691+#define MRV_SRSZ_SCALE_HY_UP
6692+#define MRV_SRSZ_SCALE_HY_UP_MASK 0x00000010
6693+#define MRV_SRSZ_SCALE_HY_UP_SHIFT 4
6694+#define MRV_SRSZ_SCALE_HY_UP_UPSCALE 1
6695+#define MRV_SRSZ_SCALE_HY_UP_DOWNSCALE 0
6696+
6697+#define MRV_SRSZ_SCALE_VC_ENABLE
6698+#define MRV_SRSZ_SCALE_VC_ENABLE_MASK 0x00000008
6699+#define MRV_SRSZ_SCALE_VC_ENABLE_SHIFT 3
6700+#define MRV_SRSZ_SCALE_VY_ENABLE
6701+#define MRV_SRSZ_SCALE_VY_ENABLE_MASK 0x00000004
6702+#define MRV_SRSZ_SCALE_VY_ENABLE_SHIFT 2
6703+#define MRV_SRSZ_SCALE_HC_ENABLE
6704+#define MRV_SRSZ_SCALE_HC_ENABLE_MASK 0x00000002
6705+#define MRV_SRSZ_SCALE_HC_ENABLE_SHIFT 1
6706+#define MRV_SRSZ_SCALE_HY_ENABLE
6707+#define MRV_SRSZ_SCALE_HY_ENABLE_MASK 0x00000001
6708+#define MRV_SRSZ_SCALE_HY_ENABLE_SHIFT 0
6709+
6710+#define MRV_SRSZ_SCALE_HY
6711+#define MRV_SRSZ_SCALE_HY_MASK MRV_RSZ_SCALE_MASK
6712+#define MRV_SRSZ_SCALE_HY_SHIFT MRV_RSZ_SCALE_SHIFT
6713+
6714+#define MRV_SRSZ_SCALE_HCB
6715+#define MRV_SRSZ_SCALE_HCB_MASK MRV_RSZ_SCALE_MASK
6716+#define MRV_SRSZ_SCALE_HCB_SHIFT MRV_RSZ_SCALE_SHIFT
6717+
6718+#define MRV_SRSZ_SCALE_HCR
6719+#define MRV_SRSZ_SCALE_HCR_MASK MRV_RSZ_SCALE_MASK
6720+#define MRV_SRSZ_SCALE_HCR_SHIFT MRV_RSZ_SCALE_SHIFT
6721+
6722+
6723+#define MRV_SRSZ_SCALE_VY
6724+#define MRV_SRSZ_SCALE_VY_MASK MRV_RSZ_SCALE_MASK
6725+#define MRV_SRSZ_SCALE_VY_SHIFT MRV_RSZ_SCALE_SHIFT
6726+
6727+#define MRV_SRSZ_SCALE_VC
6728+#define MRV_SRSZ_SCALE_VC_MASK MRV_RSZ_SCALE_MASK
6729+#define MRV_SRSZ_SCALE_VC_SHIFT MRV_RSZ_SCALE_SHIFT
6730+
6731+#define MRV_SRSZ_PHASE_HY
6732+#define MRV_SRSZ_PHASE_HY_MASK MRV_RSZ_SCALE_MASK
6733+#define MRV_SRSZ_PHASE_HY_SHIFT MRV_RSZ_SCALE_SHIFT
6734+
6735+#define MRV_SRSZ_PHASE_HC
6736+#define MRV_SRSZ_PHASE_HC_MASK MRV_RSZ_SCALE_MASK
6737+#define MRV_SRSZ_PHASE_HC_SHIFT MRV_RSZ_SCALE_SHIFT
6738+
6739+#define MRV_SRSZ_PHASE_VY
6740+#define MRV_SRSZ_PHASE_VY_MASK MRV_RSZ_SCALE_MASK
6741+#define MRV_SRSZ_PHASE_VY_SHIFT MRV_RSZ_SCALE_SHIFT
6742+
6743+#define MRV_SRSZ_PHASE_VC
6744+#define MRV_SRSZ_PHASE_VC_MASK MRV_RSZ_SCALE_MASK
6745+#define MRV_SRSZ_PHASE_VC_SHIFT MRV_RSZ_SCALE_SHIFT
6746+
6747+#define MRV_SRSZ_SCALE_LUT_ADDR
6748+#define MRV_SRSZ_SCALE_LUT_ADDR_MASK 0x0000003F
6749+#define MRV_SRSZ_SCALE_LUT_ADDR_SHIFT 0
6750+
6751+
6752+#define MRV_SRSZ_SCALE_LUT
6753+#define MRV_SRSZ_SCALE_LUT_MASK 0x0000003F
6754+#define MRV_SRSZ_SCALE_LUT_SHIFT 0
6755+
6756+
6757+#define MRV_SRSZ_SCALE_VC_UP_SHD
6758+#define MRV_SRSZ_SCALE_VC_UP_SHD_MASK 0x00000080
6759+#define MRV_SRSZ_SCALE_VC_UP_SHD_SHIFT 7
6760+#define MRV_SRSZ_SCALE_VC_UP_SHD_UPSCALE 1
6761+#define MRV_SRSZ_SCALE_VC_UP_SHD_DOWNSCALE 0
6762+#define MRV_SRSZ_SCALE_VY_UP_SHD
6763+#define MRV_SRSZ_SCALE_VY_UP_SHD_MASK 0x00000040
6764+#define MRV_SRSZ_SCALE_VY_UP_SHD_SHIFT 6
6765+#define MRV_SRSZ_SCALE_VY_UP_SHD_UPSCALE 1
6766+#define MRV_SRSZ_SCALE_VY_UP_SHD_DOWNSCALE 0
6767+#define MRV_SRSZ_SCALE_HC_UP_SHD
6768+#define MRV_SRSZ_SCALE_HC_UP_SHD_MASK 0x00000020
6769+#define MRV_SRSZ_SCALE_HC_UP_SHD_SHIFT 5
6770+#define MRV_SRSZ_SCALE_HC_UP_SHD_UPSCALE 1
6771+#define MRV_SRSZ_SCALE_HC_UP_SHD_DOWNSCALE 0
6772+#define MRV_SRSZ_SCALE_HY_UP_SHD
6773+#define MRV_SRSZ_SCALE_HY_UP_SHD_MASK 0x00000010
6774+#define MRV_SRSZ_SCALE_HY_UP_SHD_SHIFT 4
6775+#define MRV_SRSZ_SCALE_HY_UP_SHD_UPSCALE 1
6776+#define MRV_SRSZ_SCALE_HY_UP_SHD_DOWNSCALE 0
6777+#define MRV_SRSZ_SCALE_VC_ENABLE_SHD
6778+#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_MASK 0x00000008
6779+#define MRV_SRSZ_SCALE_VC_ENABLE_SHD_SHIFT 3
6780+#define MRV_SRSZ_SCALE_VY_ENABLE_SHD
6781+#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_MASK 0x00000004
6782+#define MRV_SRSZ_SCALE_VY_ENABLE_SHD_SHIFT 2
6783+#define MRV_SRSZ_SCALE_HC_ENABLE_SHD
6784+#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_MASK 0x00000002
6785+#define MRV_SRSZ_SCALE_HC_ENABLE_SHD_SHIFT 1
6786+#define MRV_SRSZ_SCALE_HY_ENABLE_SHD
6787+#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_MASK 0x00000001
6788+#define MRV_SRSZ_SCALE_HY_ENABLE_SHD_SHIFT 0
6789+
6790+#define MRV_SRSZ_SCALE_HY_SHD
6791+#define MRV_SRSZ_SCALE_HY_SHD_MASK MRV_RSZ_SCALE_MASK
6792+#define MRV_SRSZ_SCALE_HY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6793+
6794+#define MRV_SRSZ_SCALE_HCB_SHD
6795+#define MRV_SRSZ_SCALE_HCB_SHD_MASK MRV_RSZ_SCALE_MASK
6796+#define MRV_SRSZ_SCALE_HCB_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6797+
6798+#define MRV_SRSZ_SCALE_HCR_SHD
6799+#define MRV_SRSZ_SCALE_HCR_SHD_MASK MRV_RSZ_SCALE_MASK
6800+#define MRV_SRSZ_SCALE_HCR_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6801+
6802+
6803+#define MRV_SRSZ_SCALE_VY_SHD
6804+#define MRV_SRSZ_SCALE_VY_SHD_MASK MRV_RSZ_SCALE_MASK
6805+#define MRV_SRSZ_SCALE_VY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6806+
6807+#define MRV_SRSZ_SCALE_VC_SHD
6808+#define MRV_SRSZ_SCALE_VC_SHD_MASK MRV_RSZ_SCALE_MASK
6809+#define MRV_SRSZ_SCALE_VC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6810+
6811+#define MRV_SRSZ_PHASE_HY_SHD
6812+#define MRV_SRSZ_PHASE_HY_SHD_MASK MRV_RSZ_SCALE_MASK
6813+#define MRV_SRSZ_PHASE_HY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6814+
6815+#define MRV_SRSZ_PHASE_HC_SHD
6816+#define MRV_SRSZ_PHASE_HC_SHD_MASK MRV_RSZ_SCALE_MASK
6817+#define MRV_SRSZ_PHASE_HC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6818+
6819+#define MRV_SRSZ_PHASE_VY_SHD
6820+#define MRV_SRSZ_PHASE_VY_SHD_MASK MRV_RSZ_SCALE_MASK
6821+#define MRV_SRSZ_PHASE_VY_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6822+
6823+#define MRV_SRSZ_PHASE_VC_SHD
6824+#define MRV_SRSZ_PHASE_VC_SHD_MASK MRV_RSZ_SCALE_MASK
6825+#define MRV_SRSZ_PHASE_VC_SHD_SHIFT MRV_RSZ_SCALE_SHIFT
6826+
6827+#define MRV_MI_SP_OUTPUT_FORMAT
6828+#define MRV_MI_SP_OUTPUT_FORMAT_MASK 0x70000000
6829+#define MRV_MI_SP_OUTPUT_FORMAT_SHIFT 28
6830+#define MRV_MI_SP_OUTPUT_FORMAT_RGB888 6
6831+#define MRV_MI_SP_OUTPUT_FORMAT_RGB666 5
6832+#define MRV_MI_SP_OUTPUT_FORMAT_RGB565 4
6833+#define MRV_MI_SP_OUTPUT_FORMAT_YUV444 3
6834+#define MRV_MI_SP_OUTPUT_FORMAT_YUV422 2
6835+#define MRV_MI_SP_OUTPUT_FORMAT_YUV420 1
6836+#define MRV_MI_SP_OUTPUT_FORMAT_YUV400 0
6837+#define MRV_MI_SP_INPUT_FORMAT
6838+#define MRV_MI_SP_INPUT_FORMAT_MASK 0x0C000000
6839+#define MRV_MI_SP_INPUT_FORMAT_SHIFT 26
6840+#define MRV_MI_SP_INPUT_FORMAT_YUV444 3
6841+#define MRV_MI_SP_INPUT_FORMAT_YUV422 2
6842+#define MRV_MI_SP_INPUT_FORMAT_YUV420 1
6843+#define MRV_MI_SP_INPUT_FORMAT_YUV400 0
6844+#define MRV_MI_SP_WRITE_FORMAT
6845+#define MRV_MI_SP_WRITE_FORMAT_MASK 0x03000000
6846+#define MRV_MI_SP_WRITE_FORMAT_SHIFT 24
6847+#define MRV_MI_SP_WRITE_FORMAT_PLANAR 0
6848+#define MRV_MI_SP_WRITE_FORMAT_SEMIPLANAR 1
6849+#define MRV_MI_SP_WRITE_FORMAT_INTERLEAVED 2
6850+#define MRV_MI_MP_WRITE_FORMAT
6851+#define MRV_MI_MP_WRITE_FORMAT_MASK 0x00C00000
6852+#define MRV_MI_MP_WRITE_FORMAT_SHIFT 22
6853+#define MRV_MI_MP_WRITE_FORMAT_PLANAR 0
6854+#define MRV_MI_MP_WRITE_FORMAT_SEMIPLANAR 1
6855+#define MRV_MI_MP_WRITE_FORMAT_INTERLEAVED 2
6856+#define MRV_MI_MP_WRITE_FORMAT_RAW_8 0
6857+#define MRV_MI_MP_WRITE_FORMAT_RAW_12 2
6858+#define MRV_MI_INIT_OFFSET_EN
6859+#define MRV_MI_INIT_OFFSET_EN_MASK 0x00200000
6860+#define MRV_MI_INIT_OFFSET_EN_SHIFT 21
6861+
6862+#define MRV_MI_INIT_BASE_EN
6863+#define MRV_MI_INIT_BASE_EN_MASK 0x00100000
6864+#define MRV_MI_INIT_BASE_EN_SHIFT 20
6865+#define MRV_MI_BURST_LEN_CHROM
6866+#define MRV_MI_BURST_LEN_CHROM_MASK 0x000C0000
6867+#define MRV_MI_BURST_LEN_CHROM_SHIFT 18
6868+#define MRV_MI_BURST_LEN_CHROM_4 0
6869+#define MRV_MI_BURST_LEN_CHROM_8 1
6870+#define MRV_MI_BURST_LEN_CHROM_16 2
6871+
6872+#define MRV_MI_BURST_LEN_LUM
6873+#define MRV_MI_BURST_LEN_LUM_MASK 0x00030000
6874+#define MRV_MI_BURST_LEN_LUM_SHIFT 16
6875+#define MRV_MI_BURST_LEN_LUM_4 0
6876+#define MRV_MI_BURST_LEN_LUM_8 1
6877+#define MRV_MI_BURST_LEN_LUM_16 2
6878+
6879+#define MRV_MI_LAST_PIXEL_SIG_EN
6880+#define MRV_MI_LAST_PIXEL_SIG_EN_MASK 0x00008000
6881+#define MRV_MI_LAST_PIXEL_SIG_EN_SHIFT 15
6882+
6883+ #define MRV_MI_422NONCOSITED
6884+ #define MRV_MI_422NONCOSITED_MASK 0x00000400
6885+ #define MRV_MI_422NONCOSITED_SHIFT 10
6886+ #define MRV_MI_CBCR_FULL_RANGE
6887+ #define MRV_MI_CBCR_FULL_RANGE_MASK 0x00000200
6888+ #define MRV_MI_CBCR_FULL_RANGE_SHIFT 9
6889+ #define MRV_MI_Y_FULL_RANGE
6890+ #define MRV_MI_Y_FULL_RANGE_MASK 0x00000100
6891+ #define MRV_MI_Y_FULL_RANGE_SHIFT 8
6892+#define MRV_MI_BYTE_SWAP
6893+#define MRV_MI_BYTE_SWAP_MASK 0x00000080
6894+#define MRV_MI_BYTE_SWAP_SHIFT 7
6895+#define MRV_MI_ROT
6896+#define MRV_MI_ROT_MASK 0x00000040
6897+#define MRV_MI_ROT_SHIFT 6
6898+#define MRV_MI_V_FLIP
6899+#define MRV_MI_V_FLIP_MASK 0x00000020
6900+#define MRV_MI_V_FLIP_SHIFT 5
6901+
6902+#define MRV_MI_H_FLIP
6903+#define MRV_MI_H_FLIP_MASK 0x00000010
6904+#define MRV_MI_H_FLIP_SHIFT 4
6905+#define MRV_MI_RAW_ENABLE
6906+#define MRV_MI_RAW_ENABLE_MASK 0x00000008
6907+#define MRV_MI_RAW_ENABLE_SHIFT 3
6908+#define MRV_MI_JPEG_ENABLE
6909+#define MRV_MI_JPEG_ENABLE_MASK 0x00000004
6910+#define MRV_MI_JPEG_ENABLE_SHIFT 2
6911+#define MRV_MI_SP_ENABLE
6912+#define MRV_MI_SP_ENABLE_MASK 0x00000002
6913+#define MRV_MI_SP_ENABLE_SHIFT 1
6914+#define MRV_MI_MP_ENABLE
6915+#define MRV_MI_MP_ENABLE_MASK 0x00000001
6916+#define MRV_MI_MP_ENABLE_SHIFT 0
6917+
6918+
6919+#define MRV_MI_ROT_AND_FLIP
6920+#define MRV_MI_ROT_AND_FLIP_MASK \
6921+ (MRV_MI_H_FLIP_MASK | MRV_MI_V_FLIP_MASK | MRV_MI_ROT_MASK)
6922+#define MRV_MI_ROT_AND_FLIP_SHIFT \
6923+ (MRV_MI_H_FLIP_SHIFT)
6924+#define MRV_MI_ROT_AND_FLIP_H_FLIP \
6925+ (MRV_MI_H_FLIP_MASK >> MRV_MI_ROT_AND_FLIP_SHIFT)
6926+#define MRV_MI_ROT_AND_FLIP_V_FLIP \
6927+ (MRV_MI_V_FLIP_MASK >> MRV_MI_ROT_AND_FLIP_SHIFT)
6928+#define MRV_MI_ROT_AND_FLIP_ROTATE \
6929+ (MRV_MI_ROT_MASK >> MRV_MI_ROT_AND_FLIP_SHIFT)
6930+
6931+#define MRV_MI_MI_CFG_UPD
6932+#define MRV_MI_MI_CFG_UPD_MASK 0x00000010
6933+#define MRV_MI_MI_CFG_UPD_SHIFT 4
6934+#define MRV_MI_MI_SKIP
6935+#define MRV_MI_MI_SKIP_MASK 0x00000004
6936+#define MRV_MI_MI_SKIP_SHIFT 2
6937+
6938+#define MRV_MI_MP_Y_BASE_AD_INIT
6939+#define MRV_MI_MP_Y_BASE_AD_INIT_MASK 0xFFFFFFFC
6940+#define MRV_MI_MP_Y_BASE_AD_INIT_SHIFT 0
6941+#define MRV_MI_MP_Y_BASE_AD_INIT_VALID_MASK (MRV_MI_MP_Y_BASE_AD_INIT_MASK &\
6942+ ~0x00000003)
6943+#define MRV_MI_MP_Y_SIZE_INIT
6944+#define MRV_MI_MP_Y_SIZE_INIT_MASK 0x01FFFFFC
6945+#define MRV_MI_MP_Y_SIZE_INIT_SHIFT 0
6946+#define MRV_MI_MP_Y_SIZE_INIT_VALID_MASK (MRV_MI_MP_Y_SIZE_INIT_MASK &\
6947+ ~0x00000003)
6948+#define MRV_MI_MP_Y_OFFS_CNT_INIT
6949+#define MRV_MI_MP_Y_OFFS_CNT_INIT_MASK 0x01FFFFFC
6950+#define MRV_MI_MP_Y_OFFS_CNT_INIT_SHIFT 0
6951+#define MRV_MI_MP_Y_OFFS_CNT_INIT_VALID_MASK \
6952+ (MRV_MI_MP_Y_OFFS_CNT_INIT_MASK & ~0x00000003)
6953+
6954+#define MRV_MI_MP_Y_OFFS_CNT_START
6955+#define MRV_MI_MP_Y_OFFS_CNT_START_MASK 0x01FFFFFC
6956+#define MRV_MI_MP_Y_OFFS_CNT_START_SHIFT 0
6957+#define MRV_MI_MP_Y_OFFS_CNT_START_VALID_MASK \
6958+ (MRV_MI_MP_Y_OFFS_CNT_START_MASK & ~0x00000003)
6959+
6960+#define MRV_MI_MP_Y_IRQ_OFFS_INIT
6961+#define MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK 0x01FFFFFC
6962+#define MRV_MI_MP_Y_IRQ_OFFS_INIT_SHIFT 0
6963+#define MRV_MI_MP_Y_IRQ_OFFS_INIT_VALID_MASK \
6964+ (MRV_MI_MP_Y_IRQ_OFFS_INIT_MASK & ~0x00000003)
6965+#define MRV_MI_MP_CB_BASE_AD_INIT
6966+#define MRV_MI_MP_CB_BASE_AD_INIT_MASK 0xFFFFFFFC
6967+#define MRV_MI_MP_CB_BASE_AD_INIT_SHIFT 0
6968+#define MRV_MI_MP_CB_BASE_AD_INIT_VALID_MASK \
6969+ (MRV_MI_MP_CB_BASE_AD_INIT_MASK & ~0x00000003)
6970+
6971+#define MRV_MI_MP_CB_SIZE_INIT
6972+#define MRV_MI_MP_CB_SIZE_INIT_MASK 0x00FFFFFC
6973+#define MRV_MI_MP_CB_SIZE_INIT_SHIFT 0
6974+#define MRV_MI_MP_CB_SIZE_INIT_VALID_MASK \
6975+ (MRV_MI_MP_CB_SIZE_INIT_MASK & ~0x00000003)
6976+
6977+#define MRV_MI_MP_CB_OFFS_CNT_INIT
6978+#define MRV_MI_MP_CB_OFFS_CNT_INIT_MASK 0x00FFFFFC
6979+#define MRV_MI_MP_CB_OFFS_CNT_INIT_SHIFT 0
6980+#define MRV_MI_MP_CB_OFFS_CNT_INIT_VALID_MASK \
6981+ (MRV_MI_MP_CB_OFFS_CNT_INIT_MASK & ~0x00000003)
6982+
6983+#define MRV_MI_MP_CB_OFFS_CNT_START
6984+#define MRV_MI_MP_CB_OFFS_CNT_START_MASK 0x00FFFFFC
6985+#define MRV_MI_MP_CB_OFFS_CNT_START_SHIFT 0
6986+#define MRV_MI_MP_CB_OFFS_CNT_START_VALID_MASK \
6987+ (MRV_MI_MP_CB_OFFS_CNT_START_MASK & ~0x00000003)
6988+
6989+#define MRV_MI_MP_CR_BASE_AD_INIT
6990+#define MRV_MI_MP_CR_BASE_AD_INIT_MASK 0xFFFFFFFC
6991+#define MRV_MI_MP_CR_BASE_AD_INIT_SHIFT 0
6992+#define MRV_MI_MP_CR_BASE_AD_INIT_VALID_MASK \
6993+ (MRV_MI_MP_CR_BASE_AD_INIT_MASK & ~0x00000003)
6994+
6995+#define MRV_MI_MP_CR_SIZE_INIT
6996+#define MRV_MI_MP_CR_SIZE_INIT_MASK 0x00FFFFFC
6997+#define MRV_MI_MP_CR_SIZE_INIT_SHIFT 0
6998+#define MRV_MI_MP_CR_SIZE_INIT_VALID_MASK \
6999+ (MRV_MI_MP_CR_SIZE_INIT_MASK & ~0x00000003)
7000+
7001+#define MRV_MI_MP_CR_OFFS_CNT_INIT
7002+#define MRV_MI_MP_CR_OFFS_CNT_INIT_MASK 0x00FFFFFC
7003+#define MRV_MI_MP_CR_OFFS_CNT_INIT_SHIFT 0
7004+#define MRV_MI_MP_CR_OFFS_CNT_INIT_VALID_MASK \
7005+ (MRV_MI_MP_CR_OFFS_CNT_INIT_MASK & ~0x00000003)
7006+
7007+#define MRV_MI_MP_CR_OFFS_CNT_START
7008+#define MRV_MI_MP_CR_OFFS_CNT_START_MASK 0x00FFFFFC
7009+#define MRV_MI_MP_CR_OFFS_CNT_START_SHIFT 0
7010+#define MRV_MI_MP_CR_OFFS_CNT_START_VALID_MASK \
7011+ (MRV_MI_MP_CR_OFFS_CNT_START_MASK & ~0x00000003)
7012+
7013+#define MRV_MI_SP_Y_BASE_AD_INIT
7014+#define MRV_MI_SP_Y_BASE_AD_INIT_MASK 0xFFFFFFFC
7015+#define MRV_MI_SP_Y_BASE_AD_INIT_SHIFT 0
7016+#define MRV_MI_SP_Y_BASE_AD_INIT_VALID_MASK \
7017+ (MRV_MI_SP_Y_BASE_AD_INIT_MASK & ~0x00000003)
7018+
7019+#define MRV_MI_SP_Y_SIZE_INIT
7020+#define MRV_MI_SP_Y_SIZE_INIT_MASK 0x01FFFFFC
7021+#define MRV_MI_SP_Y_SIZE_INIT_SHIFT 0
7022+#define MRV_MI_SP_Y_SIZE_INIT_VALID_MASK \
7023+ (MRV_MI_SP_Y_SIZE_INIT_MASK & ~0x00000003)
7024+
7025+#define MRV_MI_SP_Y_OFFS_CNT_INIT
7026+#define MRV_MI_SP_Y_OFFS_CNT_INIT_MASK 0x01FFFFFC
7027+#define MRV_MI_SP_Y_OFFS_CNT_INIT_SHIFT 0
7028+#define MRV_MI_SP_Y_OFFS_CNT_INIT_VALID_MASK \
7029+ (MRV_MI_SP_Y_OFFS_CNT_INIT_MASK & ~0x00000003)
7030+
7031+#define MRV_MI_SP_Y_OFFS_CNT_START
7032+#define MRV_MI_SP_Y_OFFS_CNT_START_MASK 0x01FFFFFC
7033+#define MRV_MI_SP_Y_OFFS_CNT_START_SHIFT 0
7034+#define MRV_MI_SP_Y_OFFS_CNT_START_VALID_MASK \
7035+ (MRV_MI_SP_Y_OFFS_CNT_START_MASK & ~0x00000003)
7036+
7037+#define MRV_MI_SP_Y_LLENGTH
7038+#define MRV_MI_SP_Y_LLENGTH_MASK 0x00001FFF
7039+#define MRV_MI_SP_Y_LLENGTH_SHIFT 0
7040+#define MRV_MI_SP_Y_LLENGTH_VALID_MASK \
7041+ (MRV_MI_SP_Y_LLENGTH_MASK & ~0x00000000)
7042+
7043+#define MRV_MI_SP_CB_BASE_AD_INIT
7044+#define MRV_MI_SP_CB_BASE_AD_INIT_MASK 0xFFFFFFFF
7045+#define MRV_MI_SP_CB_BASE_AD_INIT_SHIFT 0
7046+#define MRV_MI_SP_CB_BASE_AD_INIT_VALID_MASK \
7047+ (MRV_MI_SP_CB_BASE_AD_INIT_MASK & ~0x00000003)
7048+
7049+#define MRV_MI_SP_CB_SIZE_INIT
7050+#define MRV_MI_SP_CB_SIZE_INIT_MASK 0x00FFFFFF
7051+#define MRV_MI_SP_CB_SIZE_INIT_SHIFT 0
7052+#define MRV_MI_SP_CB_SIZE_INIT_VALID_MASK \
7053+ (MRV_MI_SP_CB_SIZE_INIT_MASK & ~0x00000003)
7054+
7055+#define MRV_MI_SP_CB_OFFS_CNT_INIT
7056+#define MRV_MI_SP_CB_OFFS_CNT_INIT_MASK 0x00FFFFFF
7057+#define MRV_MI_SP_CB_OFFS_CNT_INIT_SHIFT 0
7058+#define MRV_MI_SP_CB_OFFS_CNT_INIT_VALID_MASK \
7059+ (MRV_MI_SP_CB_OFFS_CNT_INIT_MASK & ~0x00000003)
7060+
7061+#define MRV_MI_SP_CB_OFFS_CNT_START
7062+#define MRV_MI_SP_CB_OFFS_CNT_START_MASK 0x00FFFFFF
7063+#define MRV_MI_SP_CB_OFFS_CNT_START_SHIFT 0
7064+#define MRV_MI_SP_CB_OFFS_CNT_START_VALID_MASK \
7065+ (MRV_MI_SP_CB_OFFS_CNT_START_MASK & ~0x00000003)
7066+
7067+#define MRV_MI_SP_CR_BASE_AD_INIT
7068+#define MRV_MI_SP_CR_BASE_AD_INIT_MASK 0xFFFFFFFF
7069+#define MRV_MI_SP_CR_BASE_AD_INIT_SHIFT 0
7070+#define MRV_MI_SP_CR_BASE_AD_INIT_VALID_MASK \
7071+ (MRV_MI_SP_CR_BASE_AD_INIT_MASK & ~0x00000003)
7072+
7073+#define MRV_MI_SP_CR_SIZE_INIT
7074+#define MRV_MI_SP_CR_SIZE_INIT_MASK 0x00FFFFFF
7075+#define MRV_MI_SP_CR_SIZE_INIT_SHIFT 0
7076+#define MRV_MI_SP_CR_SIZE_INIT_VALID_MASK \
7077+ (MRV_MI_SP_CR_SIZE_INIT_MASK & ~0x00000003)
7078+
7079+#define MRV_MI_SP_CR_OFFS_CNT_INIT
7080+#define MRV_MI_SP_CR_OFFS_CNT_INIT_MASK 0x00FFFFFF
7081+#define MRV_MI_SP_CR_OFFS_CNT_INIT_SHIFT 0
7082+#define MRV_MI_SP_CR_OFFS_CNT_INIT_VALID_MASK \
7083+ (MRV_MI_SP_CR_OFFS_CNT_INIT_MASK & ~0x00000003)
7084+
7085+#define MRV_MI_SP_CR_OFFS_CNT_START
7086+#define MRV_MI_SP_CR_OFFS_CNT_START_MASK 0x00FFFFFF
7087+#define MRV_MI_SP_CR_OFFS_CNT_START_SHIFT 0
7088+#define MRV_MI_SP_CR_OFFS_CNT_START_VALID_MASK \
7089+ (MRV_MI_SP_CR_OFFS_CNT_START_MASK & ~0x00000003)
7090+
7091+#define MRV_MI_BYTE_CNT
7092+#define MRV_MI_BYTE_CNT_MASK 0x01FFFFFF
7093+#define MRV_MI_BYTE_CNT_SHIFT 0
7094+
7095+#define MRV_MI_RAW_ENABLE_OUT
7096+#define MRV_MI_RAW_ENABLE_OUT_MASK 0x00080000
7097+#define MRV_MI_RAW_ENABLE_OUT_SHIFT 19
7098+#define MRV_MI_JPEG_ENABLE_OUT
7099+#define MRV_MI_JPEG_ENABLE_OUT_MASK 0x00040000
7100+#define MRV_MI_JPEG_ENABLE_OUT_SHIFT 18
7101+#define MRV_MI_SP_ENABLE_OUT
7102+#define MRV_MI_SP_ENABLE_OUT_MASK 0x00020000
7103+#define MRV_MI_SP_ENABLE_OUT_SHIFT 17
7104+#define MRV_MI_MP_ENABLE_OUT
7105+#define MRV_MI_MP_ENABLE_OUT_MASK 0x00010000
7106+#define MRV_MI_MP_ENABLE_OUT_SHIFT 16
7107+#define MRV_MI_RAW_ENABLE_IN
7108+#define MRV_MI_RAW_ENABLE_IN_MASK 0x00000020
7109+#define MRV_MI_RAW_ENABLE_IN_SHIFT 5
7110+#define MRV_MI_JPEG_ENABLE_IN
7111+#define MRV_MI_JPEG_ENABLE_IN_MASK 0x00000010
7112+#define MRV_MI_JPEG_ENABLE_IN_SHIFT 4
7113+#define MRV_MI_SP_ENABLE_IN
7114+#define MRV_MI_SP_ENABLE_IN_MASK 0x00000004
7115+#define MRV_MI_SP_ENABLE_IN_SHIFT 2
7116+#define MRV_MI_MP_ENABLE_IN
7117+#define MRV_MI_MP_ENABLE_IN_MASK 0x00000001
7118+#define MRV_MI_MP_ENABLE_IN_SHIFT 0
7119+
7120+#define MRV_MI_MP_Y_BASE_AD
7121+#define MRV_MI_MP_Y_BASE_AD_MASK 0xFFFFFFFC
7122+#define MRV_MI_MP_Y_BASE_AD_SHIFT 0
7123+#define MRV_MI_MP_Y_BASE_AD_VALID_MASK \
7124+ (MRV_MI_MP_Y_BASE_AD_MASK & ~0x00000003)
7125+
7126+#define MRV_MI_MP_Y_SIZE
7127+#define MRV_MI_MP_Y_SIZE_MASK 0x01FFFFFC
7128+#define MRV_MI_MP_Y_SIZE_SHIFT 0
7129+#define MRV_MI_MP_Y_SIZE_VALID_MASK (MRV_MI_MP_Y_SIZE_MASK & ~0x00000003)
7130+
7131+#define MRV_MI_MP_Y_OFFS_CNT
7132+#define MRV_MI_MP_Y_OFFS_CNT_MASK 0x01FFFFFC
7133+#define MRV_MI_MP_Y_OFFS_CNT_SHIFT 0
7134+#define MRV_MI_MP_Y_OFFS_CNT_VALID_MASK \
7135+ (MRV_MI_MP_Y_OFFS_CNT_MASK & ~0x00000003)
7136+
7137+#define MRV_MI_MP_Y_IRQ_OFFS
7138+#define MRV_MI_MP_Y_IRQ_OFFS_MASK 0x01FFFFFC
7139+#define MRV_MI_MP_Y_IRQ_OFFS_SHIFT 0
7140+#define MRV_MI_MP_Y_IRQ_OFFS_VALID_MASK \
7141+ (MRV_MI_MP_Y_IRQ_OFFS_MASK & ~0x00000003)
7142+
7143+#define MRV_MI_MP_CB_BASE_AD
7144+#define MRV_MI_MP_CB_BASE_AD_MASK 0xFFFFFFFF
7145+#define MRV_MI_MP_CB_BASE_AD_SHIFT 0
7146+#define MRV_MI_MP_CB_BASE_AD_VALID_MASK \
7147+ (MRV_MI_MP_CB_BASE_AD_MASK & ~0x00000003)
7148+
7149+#define MRV_MI_MP_CB_SIZE
7150+#define MRV_MI_MP_CB_SIZE_MASK 0x00FFFFFF
7151+#define MRV_MI_MP_CB_SIZE_SHIFT 0
7152+#define MRV_MI_MP_CB_SIZE_VALID_MASK (MRV_MI_MP_CB_SIZE_MASK & ~0x00000003)
7153+
7154+#define MRV_MI_MP_CB_OFFS_CNT
7155+#define MRV_MI_MP_CB_OFFS_CNT_MASK 0x00FFFFFF
7156+#define MRV_MI_MP_CB_OFFS_CNT_SHIFT 0
7157+#define MRV_MI_MP_CB_OFFS_CNT_VALID_MASK \
7158+ (MRV_MI_MP_CB_OFFS_CNT_MASK & ~0x00000003)
7159+
7160+#define MRV_MI_MP_CR_BASE_AD
7161+#define MRV_MI_MP_CR_BASE_AD_MASK 0xFFFFFFFF
7162+#define MRV_MI_MP_CR_BASE_AD_SHIFT 0
7163+#define MRV_MI_MP_CR_BASE_AD_VALID_MASK \
7164+ (MRV_MI_MP_CR_BASE_AD_MASK & ~0x00000003)
7165+
7166+#define MRV_MI_MP_CR_SIZE
7167+#define MRV_MI_MP_CR_SIZE_MASK 0x00FFFFFF
7168+#define MRV_MI_MP_CR_SIZE_SHIFT 0
7169+#define MRV_MI_MP_CR_SIZE_VALID_MASK (MRV_MI_MP_CR_SIZE_MASK & ~0x00000003)
7170+
7171+#define MRV_MI_MP_CR_OFFS_CNT
7172+#define MRV_MI_MP_CR_OFFS_CNT_MASK 0x00FFFFFF
7173+#define MRV_MI_MP_CR_OFFS_CNT_SHIFT 0
7174+#define MRV_MI_MP_CR_OFFS_CNT_VALID_MASK \
7175+ (MRV_MI_MP_CR_OFFS_CNT_MASK & ~0x00000003)
7176+
7177+#define MRV_MI_SP_Y_BASE_AD
7178+#define MRV_MI_SP_Y_BASE_AD_MASK 0xFFFFFFFF
7179+#define MRV_MI_SP_Y_BASE_AD_SHIFT 0
7180+#define MRV_MI_SP_Y_BASE_AD_VALID_MASK \
7181+ (MRV_MI_SP_Y_BASE_AD_MASK & ~0x00000003)
7182+
7183+#define MRV_MI_SP_Y_SIZE
7184+#define MRV_MI_SP_Y_SIZE_MASK 0x01FFFFFC
7185+#define MRV_MI_SP_Y_SIZE_SHIFT 0
7186+#define MRV_MI_SP_Y_SIZE_VALID_MASK (MRV_MI_SP_Y_SIZE_MASK & ~0x00000003)
7187+
7188+#define MRV_MI_SP_Y_OFFS_CNT
7189+#define MRV_MI_SP_Y_OFFS_CNT_MASK 0x01FFFFFC
7190+#define MRV_MI_SP_Y_OFFS_CNT_SHIFT 0
7191+#define MRV_MI_SP_Y_OFFS_CNT_VALID_MASK \
7192+ (MRV_MI_SP_Y_OFFS_CNT_MASK & ~0x00000003)
7193+
7194+#define MRV_MI_SP_CB_BASE_AD
7195+#define MRV_MI_SP_CB_BASE_AD_MASK 0xFFFFFFFF
7196+#define MRV_MI_SP_CB_BASE_AD_SHIFT 0
7197+#define MRV_MI_SP_CB_BASE_AD_VALID_MASK \
7198+ (MRV_MI_SP_CB_BASE_AD_MASK & ~0x00000003)
7199+
7200+#define MRV_MI_SP_CB_SIZE
7201+#define MRV_MI_SP_CB_SIZE_MASK 0x00FFFFFF
7202+#define MRV_MI_SP_CB_SIZE_SHIFT 0
7203+#define MRV_MI_SP_CB_SIZE_VALID_MASK (MRV_MI_SP_CB_SIZE_MASK & ~0x00000003)
7204+
7205+#define MRV_MI_SP_CB_OFFS_CNT
7206+#define MRV_MI_SP_CB_OFFS_CNT_MASK 0x00FFFFFF
7207+#define MRV_MI_SP_CB_OFFS_CNT_SHIFT 0
7208+#define MRV_MI_SP_CB_OFFS_CNT_VALID_MASK \
7209+ (MRV_MI_SP_CB_OFFS_CNT_MASK & ~0x00000003)
7210+
7211+#define MRV_MI_SP_CR_BASE_AD
7212+#define MRV_MI_SP_CR_BASE_AD_MASK 0xFFFFFFFF
7213+#define MRV_MI_SP_CR_BASE_AD_SHIFT 0
7214+#define MRV_MI_SP_CR_BASE_AD_VALID_MASK \
7215+ (MRV_MI_SP_CR_BASE_AD_MASK & ~0x00000003)
7216+
7217+#define MRV_MI_SP_CR_SIZE
7218+#define MRV_MI_SP_CR_SIZE_MASK 0x00FFFFFF
7219+#define MRV_MI_SP_CR_SIZE_SHIFT 0
7220+#define MRV_MI_SP_CR_SIZE_VALID_MASK (MRV_MI_SP_CR_SIZE_MASK & ~0x00000003)
7221+
7222+#define MRV_MI_SP_CR_OFFS_CNT
7223+#define MRV_MI_SP_CR_OFFS_CNT_MASK 0x00FFFFFF
7224+#define MRV_MI_SP_CR_OFFS_CNT_SHIFT 0
7225+#define MRV_MI_SP_CR_OFFS_CNT_VALID_MASK \
7226+ (MRV_MI_SP_CR_OFFS_CNT_MASK & ~0x00000003)
7227+
7228+
7229+#define MRV_MI_DMA_Y_PIC_START_AD
7230+#define MRV_MI_DMA_Y_PIC_START_AD_MASK 0xFFFFFFFF
7231+#define MRV_MI_DMA_Y_PIC_START_AD_SHIFT 0
7232+
7233+#define MRV_MI_DMA_Y_PIC_WIDTH
7234+#define MRV_MI_DMA_Y_PIC_WIDTH_MASK 0x00001FFF
7235+#define MRV_MI_DMA_Y_PIC_WIDTH_SHIFT 0
7236+
7237+#define MRV_MI_DMA_Y_LLENGTH
7238+#define MRV_MI_DMA_Y_LLENGTH_MASK 0x00001FFF
7239+#define MRV_MI_DMA_Y_LLENGTH_SHIFT 0
7240+
7241+#define MRV_MI_DMA_Y_PIC_SIZE
7242+#define MRV_MI_DMA_Y_PIC_SIZE_MASK 0x00FFFFFF
7243+#define MRV_MI_DMA_Y_PIC_SIZE_SHIFT 0
7244+
7245+#define MRV_MI_DMA_CB_PIC_START_AD
7246+#define MRV_MI_DMA_CB_PIC_START_AD_MASK 0xFFFFFFFF
7247+#define MRV_MI_DMA_CB_PIC_START_AD_SHIFT 0
7248+
7249+
7250+#define MRV_MI_DMA_CR_PIC_START_AD
7251+#define MRV_MI_DMA_CR_PIC_START_AD_MASK 0xFFFFFFFF
7252+#define MRV_MI_DMA_CR_PIC_START_AD_SHIFT 0
7253+
7254+
7255+#define MRV_MI_DMA_READY
7256+#define MRV_MI_DMA_READY_MASK 0x00000800
7257+#define MRV_MI_DMA_READY_SHIFT 11
7258+
7259+#define MRV_MI_AHB_ERROR
7260+
7261+#define MRV_MI_AHB_ERROR_MASK 0x00000400
7262+#define MRV_MI_AHB_ERROR_SHIFT 10
7263+#define MRV_MI_WRAP_SP_CR
7264+
7265+#define MRV_MI_WRAP_SP_CR_MASK 0x00000200
7266+#define MRV_MI_WRAP_SP_CR_SHIFT 9
7267+#define MRV_MI_WRAP_SP_CB
7268+
7269+#define MRV_MI_WRAP_SP_CB_MASK 0x00000100
7270+#define MRV_MI_WRAP_SP_CB_SHIFT 8
7271+#define MRV_MI_WRAP_SP_Y
7272+
7273+#define MRV_MI_WRAP_SP_Y_MASK 0x00000080
7274+#define MRV_MI_WRAP_SP_Y_SHIFT 7
7275+#define MRV_MI_WRAP_MP_CR
7276+
7277+#define MRV_MI_WRAP_MP_CR_MASK 0x00000040
7278+#define MRV_MI_WRAP_MP_CR_SHIFT 6
7279+#define MRV_MI_WRAP_MP_CB
7280+
7281+#define MRV_MI_WRAP_MP_CB_MASK 0x00000020
7282+#define MRV_MI_WRAP_MP_CB_SHIFT 5
7283+#define MRV_MI_WRAP_MP_Y
7284+
7285+#define MRV_MI_WRAP_MP_Y_MASK 0x00000010
7286+#define MRV_MI_WRAP_MP_Y_SHIFT 4
7287+#define MRV_MI_FILL_MP_Y
7288+
7289+#define MRV_MI_FILL_MP_Y_MASK 0x00000008
7290+#define MRV_MI_FILL_MP_Y_SHIFT 3
7291+#define MRV_MI_MBLK_LINE
7292+
7293+#define MRV_MI_MBLK_LINE_MASK 0x00000004
7294+#define MRV_MI_MBLK_LINE_SHIFT 2
7295+#define MRV_MI_SP_FRAME_END
7296+#define MRV_MI_SP_FRAME_END_MASK 0x00000002
7297+#define MRV_MI_SP_FRAME_END_SHIFT 1
7298+
7299+#define MRV_MI_MP_FRAME_END
7300+#define MRV_MI_MP_FRAME_END_MASK 0x00000001
7301+#define MRV_MI_MP_FRAME_END_SHIFT 0
7302+
7303+#ifndef MRV_MI_SP_FRAME_END
7304+#define MRV_MI_SP_FRAME_END_MASK 0
7305+#endif
7306+#ifndef MRV_MI_DMA_FRAME_END
7307+#define MRV_MI_DMA_FRAME_END_MASK 0
7308+#endif
7309+
7310+
7311+#define MRV_MI_ALLIRQS
7312+#define MRV_MI_ALLIRQS_MASK \
7313+(0 \
7314+| MRV_MI_DMA_READY_MASK \
7315+| MRV_MI_AHB_ERROR_MASK \
7316+| MRV_MI_WRAP_SP_CR_MASK \
7317+| MRV_MI_WRAP_SP_CB_MASK \
7318+| MRV_MI_WRAP_SP_Y_MASK \
7319+| MRV_MI_WRAP_MP_CR_MASK \
7320+| MRV_MI_WRAP_MP_CB_MASK \
7321+| MRV_MI_WRAP_MP_Y_MASK \
7322+| MRV_MI_FILL_MP_Y_MASK \
7323+| MRV_MI_MBLK_LINE_MASK \
7324+| MRV_MI_SP_FRAME_END_MASK \
7325+| MRV_MI_DMA_FRAME_END_MASK \
7326+| MRV_MI_MP_FRAME_END_MASK \
7327+)
7328+#define MRV_MI_ALLIRQS_SHIFT 0
7329+
7330+#define MRV_MI_AHB_READ_ERROR
7331+#define MRV_MI_AHB_READ_ERROR_MASK 0x00000200
7332+#define MRV_MI_AHB_READ_ERROR_SHIFT 9
7333+#define MRV_MI_AHB_WRITE_ERROR
7334+#define MRV_MI_AHB_WRITE_ERROR_MASK 0x00000100
7335+#define MRV_MI_AHB_WRITE_ERROR_SHIFT 8
7336+#define MRV_MI_SP_CR_FIFO_FULL
7337+#define MRV_MI_SP_CR_FIFO_FULL_MASK 0x00000040
7338+#define MRV_MI_SP_CR_FIFO_FULL_SHIFT 6
7339+#define MRV_MI_SP_CB_FIFO_FULL
7340+#define MRV_MI_SP_CB_FIFO_FULL_MASK 0x00000020
7341+#define MRV_MI_SP_CB_FIFO_FULL_SHIFT 5
7342+#define MRV_MI_SP_Y_FIFO_FULL
7343+#define MRV_MI_SP_Y_FIFO_FULL_MASK 0x00000010
7344+#define MRV_MI_SP_Y_FIFO_FULL_SHIFT 4
7345+#define MRV_MI_MP_CR_FIFO_FULL
7346+#define MRV_MI_MP_CR_FIFO_FULL_MASK 0x00000004
7347+#define MRV_MI_MP_CR_FIFO_FULL_SHIFT 2
7348+#define MRV_MI_MP_CB_FIFO_FULL
7349+#define MRV_MI_MP_CB_FIFO_FULL_MASK 0x00000002
7350+#define MRV_MI_MP_CB_FIFO_FULL_SHIFT 1
7351+#define MRV_MI_MP_Y_FIFO_FULL
7352+#define MRV_MI_MP_Y_FIFO_FULL_MASK 0x00000001
7353+#define MRV_MI_MP_Y_FIFO_FULL_SHIFT 0
7354+
7355+
7356+#define MRV_MI_ALL_STAT
7357+#define MRV_MI_ALL_STAT_MASK \
7358+(0 \
7359+| MRV_MI_AHB_READ_ERROR_MASK \
7360+| MRV_MI_AHB_WRITE_ERROR_MASK \
7361+| MRV_MI_SP_CR_FIFO_FULL_MASK \
7362+| MRV_MI_SP_CB_FIFO_FULL_MASK \
7363+| MRV_MI_SP_Y_FIFO_FULL_MASK \
7364+| MRV_MI_MP_CR_FIFO_FULL_MASK \
7365+| MRV_MI_MP_CB_FIFO_FULL_MASK \
7366+| MRV_MI_MP_Y_FIFO_FULL_MASK \
7367+)
7368+#define MRV_MI_ALL_STAT_SHIFT 0
7369+
7370+
7371+
7372+#define MRV_MI_SP_Y_PIC_WIDTH
7373+#define MRV_MI_SP_Y_PIC_WIDTH_MASK 0x00000FFF
7374+#define MRV_MI_SP_Y_PIC_WIDTH_SHIFT 0
7375+
7376+#define MRV_MI_SP_Y_PIC_HEIGHT
7377+#define MRV_MI_SP_Y_PIC_HEIGHT_MASK 0x00000FFF
7378+#define MRV_MI_SP_Y_PIC_HEIGHT_SHIFT 0
7379+
7380+#define MRV_MI_SP_Y_PIC_SIZE
7381+#define MRV_MI_SP_Y_PIC_SIZE_MASK 0x01FFFFFF
7382+#define MRV_MI_SP_Y_PIC_SIZE_SHIFT 0
7383+
7384+
7385+
7386+
7387+#define MRV_MI_DMA_FRAME_END_DISABLE
7388+#define MRV_MI_DMA_FRAME_END_DISABLE_MASK 0x00000400
7389+#define MRV_MI_DMA_FRAME_END_DISABLE_SHIFT 10
7390+#define MRV_MI_DMA_CONTINUOUS_EN
7391+#define MRV_MI_DMA_CONTINUOUS_EN_MASK 0x00000200
7392+#define MRV_MI_DMA_CONTINUOUS_EN_SHIFT 9
7393+#define MRV_MI_DMA_BYTE_SWAP
7394+#define MRV_MI_DMA_BYTE_SWAP_MASK 0x00000100
7395+#define MRV_MI_DMA_BYTE_SWAP_SHIFT 8
7396+#define MRV_MI_DMA_INOUT_FORMAT
7397+#define MRV_MI_DMA_INOUT_FORMAT_MASK 0x000000C0
7398+#define MRV_MI_DMA_INOUT_FORMAT_SHIFT 6
7399+#define MRV_MI_DMA_INOUT_FORMAT_YUV444 3
7400+#define MRV_MI_DMA_INOUT_FORMAT_YUV422 2
7401+#define MRV_MI_DMA_INOUT_FORMAT_YUV420 1
7402+#define MRV_MI_DMA_INOUT_FORMAT_YUV400 0
7403+#define MRV_MI_DMA_READ_FORMAT
7404+#define MRV_MI_DMA_READ_FORMAT_MASK 0x00000030
7405+#define MRV_MI_DMA_READ_FORMAT_SHIFT 4
7406+#define MRV_MI_DMA_READ_FORMAT_PLANAR 0
7407+#define MRV_MI_DMA_READ_FORMAT_SEMIPLANAR 1
7408+#define MRV_MI_DMA_READ_FORMAT_INTERLEAVED 2
7409+#define MRV_MI_DMA_BURST_LEN_CHROM
7410+#define MRV_MI_DMA_BURST_LEN_CHROM_MASK 0x0000000C
7411+#define MRV_MI_DMA_BURST_LEN_CHROM_SHIFT 2
7412+#define MRV_MI_DMA_BURST_LEN_CHROM_4 0
7413+#define MRV_MI_DMA_BURST_LEN_CHROM_8 1
7414+#define MRV_MI_DMA_BURST_LEN_CHROM_16 2
7415+#define MRV_MI_DMA_BURST_LEN_LUM
7416+#define MRV_MI_DMA_BURST_LEN_LUM_MASK 0x00000003
7417+#define MRV_MI_DMA_BURST_LEN_LUM_SHIFT 0
7418+#define MRV_MI_DMA_BURST_LEN_LUM_4 0
7419+#define MRV_MI_DMA_BURST_LEN_LUM_8 1
7420+#define MRV_MI_DMA_BURST_LEN_LUM_16 2
7421+
7422+
7423+
7424+#define MRV_MI_DMA_START
7425+#define MRV_MI_DMA_START_MASK 0x00000001
7426+#define MRV_MI_DMA_START_SHIFT 0
7427+
7428+
7429+#define MRV_MI_DMA_ACTIVE
7430+#define MRV_MI_DMA_ACTIVE_MASK 0x00000001
7431+#define MRV_MI_DMA_ACTIVE_SHIFT 0
7432+
7433+
7434+
7435+#define MRV_JPE_GEN_HEADER
7436+#define MRV_JPE_GEN_HEADER_MASK 0x00000001
7437+#define MRV_JPE_GEN_HEADER_SHIFT 0
7438+
7439+
7440+#define MRV_JPE_CONT_MODE
7441+#define MRV_JPE_CONT_MODE_MASK 0x00000030
7442+#define MRV_JPE_CONT_MODE_SHIFT 4
7443+#define MRV_JPE_CONT_MODE_STOP 0
7444+#define MRV_JPE_CONT_MODE_NEXT 1
7445+#define MRV_JPE_CONT_MODE_HEADER 3
7446+#define MRV_JPE_ENCODE
7447+#define MRV_JPE_ENCODE_MASK 0x00000001
7448+#define MRV_JPE_ENCODE_SHIFT 0
7449+
7450+
7451+#define MRV_JPE_JP_INIT
7452+#define MRV_JPE_JP_INIT_MASK 0x00000001
7453+#define MRV_JPE_JP_INIT_SHIFT 0
7454+
7455+
7456+#define MRV_JPE_Y_SCALE_EN
7457+#define MRV_JPE_Y_SCALE_EN_MASK 0x00000001
7458+#define MRV_JPE_Y_SCALE_EN_SHIFT 0
7459+
7460+
7461+#define MRV_JPE_CBCR_SCALE_EN
7462+#define MRV_JPE_CBCR_SCALE_EN_MASK 0x00000001
7463+#define MRV_JPE_CBCR_SCALE_EN_SHIFT 0
7464+
7465+#define MRV_JPE_TABLE_FLUSH
7466+#define MRV_JPE_TABLE_FLUSH_MASK 0x00000001
7467+#define MRV_JPE_TABLE_FLUSH_SHIFT 0
7468+
7469+
7470+#define MRV_JPE_ENC_HSIZE
7471+
7472+#define MRV_JPE_ENC_HSIZE_MASK 0x00001FFF
7473+
7474+#define MRV_JPE_ENC_HSIZE_SHIFT 0
7475+
7476+#define MRV_JPE_ENC_VSIZE
7477+
7478+#define MRV_JPE_ENC_VSIZE_MASK 0x00000FFF
7479+
7480+#define MRV_JPE_ENC_VSIZE_SHIFT 0
7481+
7482+
7483+#define MRV_JPE_ENC_PIC_FORMAT
7484+#define MRV_JPE_ENC_PIC_FORMAT_MASK 0x00000007
7485+#define MRV_JPE_ENC_PIC_FORMAT_SHIFT 0
7486+#define MRV_JPE_ENC_PIC_FORMAT_422 1
7487+#define MRV_JPE_ENC_PIC_FORMAT_400 4
7488+
7489+#define MRV_JPE_RESTART_INTERVAL
7490+#define MRV_JPE_RESTART_INTERVAL_MASK 0x0000FFFF
7491+#define MRV_JPE_RESTART_INTERVAL_SHIFT 0
7492+
7493+#define MRV_JPE_TQ0_SELECT
7494+#define MRV_JPE_TQ0_SELECT_MASK 0x00000003
7495+#define MRV_JPE_TQ0_SELECT_SHIFT 0
7496+#define MRV_JPE_TQ1_SELECT
7497+#define MRV_JPE_TQ1_SELECT_MASK 0x00000003
7498+#define MRV_JPE_TQ1_SELECT_SHIFT 0
7499+
7500+
7501+#define MRV_JPE_TQ2_SELECT
7502+#define MRV_JPE_TQ2_SELECT_MASK 0x00000003
7503+#define MRV_JPE_TQ2_SELECT_SHIFT 0
7504+
7505+#define MRV_JPE_TQ_SELECT_TAB3 3
7506+#define MRV_JPE_TQ_SELECT_TAB2 2
7507+#define MRV_JPE_TQ_SELECT_TAB1 1
7508+#define MRV_JPE_TQ_SELECT_TAB0 0
7509+
7510+
7511+#define MRV_JPE_DC_TABLE_SELECT_Y
7512+#define MRV_JPE_DC_TABLE_SELECT_Y_MASK 0x00000001
7513+#define MRV_JPE_DC_TABLE_SELECT_Y_SHIFT 0
7514+#define MRV_JPE_DC_TABLE_SELECT_U
7515+#define MRV_JPE_DC_TABLE_SELECT_U_MASK 0x00000002
7516+#define MRV_JPE_DC_TABLE_SELECT_U_SHIFT 1
7517+#define MRV_JPE_DC_TABLE_SELECT_V
7518+#define MRV_JPE_DC_TABLE_SELECT_V_MASK 0x00000004
7519+#define MRV_JPE_DC_TABLE_SELECT_V_SHIFT 2
7520+
7521+
7522+#define MRV_JPE_AC_TABLE_SELECT_Y
7523+#define MRV_JPE_AC_TABLE_SELECT_Y_MASK 0x00000001
7524+#define MRV_JPE_AC_TABLE_SELECT_Y_SHIFT 0
7525+#define MRV_JPE_AC_TABLE_SELECT_U
7526+#define MRV_JPE_AC_TABLE_SELECT_U_MASK 0x00000002
7527+#define MRV_JPE_AC_TABLE_SELECT_U_SHIFT 1
7528+#define MRV_JPE_AC_TABLE_SELECT_V
7529+#define MRV_JPE_AC_TABLE_SELECT_V_MASK 0x00000004
7530+#define MRV_JPE_AC_TABLE_SELECT_V_SHIFT 2
7531+
7532+
7533+#define MRV_JPE_TABLE_WDATA_H
7534+#define MRV_JPE_TABLE_WDATA_H_MASK 0x0000FF00
7535+#define MRV_JPE_TABLE_WDATA_H_SHIFT 8
7536+#define MRV_JPE_TABLE_WDATA_L
7537+#define MRV_JPE_TABLE_WDATA_L_MASK 0x000000FF
7538+#define MRV_JPE_TABLE_WDATA_L_SHIFT 0
7539+
7540+
7541+#define MRV_JPE_TABLE_ID
7542+#define MRV_JPE_TABLE_ID_MASK 0x0000000F
7543+#define MRV_JPE_TABLE_ID_SHIFT 0
7544+#define MRV_JPE_TABLE_ID_QUANT0 0
7545+#define MRV_JPE_TABLE_ID_QUANT1 1
7546+#define MRV_JPE_TABLE_ID_QUANT2 2
7547+#define MRV_JPE_TABLE_ID_QUANT3 3
7548+#define MRV_JPE_TABLE_ID_VLC_DC0 4
7549+#define MRV_JPE_TABLE_ID_VLC_AC0 5
7550+#define MRV_JPE_TABLE_ID_VLC_DC1 6
7551+#define MRV_JPE_TABLE_ID_VLC_AC1 7
7552+
7553+#define MRV_JPE_TAC0_LEN
7554+#define MRV_JPE_TAC0_LEN_MASK 0x000000FF
7555+#define MRV_JPE_TAC0_LEN_SHIFT 0
7556+
7557+#define MRV_JPE_TDC0_LEN
7558+#define MRV_JPE_TDC0_LEN_MASK 0x000000FF
7559+#define MRV_JPE_TDC0_LEN_SHIFT 0
7560+
7561+#define MRV_JPE_TAC1_LEN
7562+#define MRV_JPE_TAC1_LEN_MASK 0x000000FF
7563+#define MRV_JPE_TAC1_LEN_SHIFT 0
7564+
7565+#define MRV_JPE_TDC1_LEN
7566+#define MRV_JPE_TDC1_LEN_MASK 0x000000FF
7567+#define MRV_JPE_TDC1_LEN_SHIFT 0
7568+
7569+
7570+#define MRV_JPE_CODEC_BUSY
7571+#define MRV_JPE_CODEC_BUSY_MASK 0x00000001
7572+#define MRV_JPE_CODEC_BUSY_SHIFT 0
7573+
7574+
7575+#define MRV_JPE_HEADER_MODE
7576+#define MRV_JPE_HEADER_MODE_MASK 0x00000003
7577+#define MRV_JPE_HEADER_MODE_SHIFT 0
7578+#define MRV_JPE_HEADER_MODE_NO 0
7579+#define MRV_JPE_HEADER_MODE_JFIF 2
7580+
7581+#define MRV_JPE_ENCODE_MODE
7582+#define MRV_JPE_ENCODE_MODE_MASK 0x00000001
7583+#define MRV_JPE_ENCODE_MODE_SHIFT 0
7584+
7585+#define MRV_JPE_DEB_BAD_TABLE_ACCESS
7586+#define MRV_JPE_DEB_BAD_TABLE_ACCESS_MASK 0x00000100
7587+#define MRV_JPE_DEB_BAD_TABLE_ACCESS_SHIFT 8
7588+#define MRV_JPE_DEB_VLC_TABLE_BUSY
7589+#define MRV_JPE_DEB_VLC_TABLE_BUSY_MASK 0x00000020
7590+#define MRV_JPE_DEB_VLC_TABLE_BUSY_SHIFT 5
7591+#define MRV_JPE_DEB_R2B_MEMORY_FULL
7592+#define MRV_JPE_DEB_R2B_MEMORY_FULL_MASK 0x00000010
7593+#define MRV_JPE_DEB_R2B_MEMORY_FULL_SHIFT 4
7594+#define MRV_JPE_DEB_VLC_ENCODE_BUSY
7595+#define MRV_JPE_DEB_VLC_ENCODE_BUSY_MASK 0x00000008
7596+#define MRV_JPE_DEB_VLC_ENCODE_BUSY_SHIFT 3
7597+#define MRV_JPE_DEB_QIQ_TABLE_ACC
7598+#define MRV_JPE_DEB_QIQ_TABLE_ACC_MASK 0x00000004
7599+#define MRV_JPE_DEB_QIQ_TABLE_ACC_SHIFT 2
7600+
7601+#define MRV_JPE_VLC_TABLE_ERR
7602+#define MRV_JPE_VLC_TABLE_ERR_MASK 0x00000400
7603+#define MRV_JPE_VLC_TABLE_ERR_SHIFT 10
7604+#define MRV_JPE_R2B_IMG_SIZE_ERR
7605+#define MRV_JPE_R2B_IMG_SIZE_ERR_MASK 0x00000200
7606+#define MRV_JPE_R2B_IMG_SIZE_ERR_SHIFT 9
7607+#define MRV_JPE_DCT_ERR
7608+#define MRV_JPE_DCT_ERR_MASK 0x00000080
7609+#define MRV_JPE_DCT_ERR_SHIFT 7
7610+#define MRV_JPE_VLC_SYMBOL_ERR
7611+#define MRV_JPE_VLC_SYMBOL_ERR_MASK 0x00000010
7612+#define MRV_JPE_VLC_SYMBOL_ERR_SHIFT 4
7613+
7614+
7615+#define MRV_JPE_ALL_ERR
7616+#define MRV_JPE_ALL_ERR_MASK \
7617+(0 \
7618+| MRV_JPE_VLC_TABLE_ERR_MASK \
7619+| MRV_JPE_R2B_IMG_SIZE_ERR_MASK \
7620+| MRV_JPE_DCT_ERR_MASK \
7621+| MRV_JPE_VLC_SYMBOL_ERR_MASK \
7622+)
7623+#define MRV_JPE_ALL_ERR_SHIFT 0
7624+
7625+#define MRV_JPE_GEN_HEADER_DONE
7626+#define MRV_JPE_GEN_HEADER_DONE_MASK 0x00000020
7627+#define MRV_JPE_GEN_HEADER_DONE_SHIFT 5
7628+#define MRV_JPE_ENCODE_DONE
7629+#define MRV_JPE_ENCODE_DONE_MASK 0x00000010
7630+#define MRV_JPE_ENCODE_DONE_SHIFT 4
7631+
7632+/* FIXME | MRV_JPE_GEN_HEADER_DONE_MASK \ */
7633+
7634+#define MRV_JPE_ALL_STAT
7635+#define MRV_JPE_ALL_STAT_MASK \
7636+(0 \
7637+| MRV_JPE_ENCODE_DONE_MASK \
7638+)
7639+#define MRV_JPE_ALL_STAT_SHIFT 0
7640+
7641+
7642+#define MRV_SMIA_DMA_CHANNEL_SEL
7643+#define MRV_SMIA_DMA_CHANNEL_SEL_MASK 0x00000700
7644+#define MRV_SMIA_DMA_CHANNEL_SEL_SHIFT 8
7645+#define MRV_SMIA_SHUTDOWN_LANE
7646+#define MRV_SMIA_SHUTDOWN_LANE_MASK 0x00000008
7647+#define MRV_SMIA_SHUTDOWN_LANE_SHIFT 3
7648+
7649+#define MRV_SMIA_FLUSH_FIFO
7650+#define MRV_SMIA_FLUSH_FIFO_MASK 0x00000002
7651+#define MRV_SMIA_FLUSH_FIFO_SHIFT 1
7652+
7653+#define MRV_SMIA_OUTPUT_ENA
7654+#define MRV_SMIA_OUTPUT_ENA_MASK 0x00000001
7655+#define MRV_SMIA_OUTPUT_ENA_SHIFT 0
7656+
7657+#define MRV_SMIA_DMA_CHANNEL
7658+#define MRV_SMIA_DMA_CHANNEL_MASK 0x00000700
7659+#define MRV_SMIA_DMA_CHANNEL_SHIFT 8
7660+#define MRV_SMIA_EMB_DATA_AVAIL
7661+#define MRV_SMIA_EMB_DATA_AVAIL_MASK 0x00000001
7662+#define MRV_SMIA_EMB_DATA_AVAIL_SHIFT 0
7663+
7664+#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL
7665+#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK 0x00000020
7666+#define MRV_SMIA_IMSC_FIFO_FILL_LEVEL_SHIFT 5
7667+
7668+#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW
7669+#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK 0x00000010
7670+#define MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_SHIFT 4
7671+#define MRV_SMIA_IMSC_ERR_CS
7672+#define MRV_SMIA_IMSC_ERR_CS_MASK 0x00000008
7673+#define MRV_SMIA_IMSC_ERR_CS_SHIFT 3
7674+#define MRV_SMIA_IMSC_ERR_PROTOCOL
7675+#define MRV_SMIA_IMSC_ERR_PROTOCOL_MASK 0x00000004
7676+#define MRV_SMIA_IMSC_ERR_PROTOCOL_SHIFT 2
7677+
7678+#define MRV_SMIA_IMSC_EMB_DATA_OVFLW
7679+#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK 0x00000002
7680+#define MRV_SMIA_IMSC_EMB_DATA_OVFLW_SHIFT 1
7681+#define MRV_SMIA_IMSC_FRAME_END
7682+#define MRV_SMIA_IMSC_FRAME_END_MASK 0x00000001
7683+#define MRV_SMIA_IMSC_FRAME_END_SHIFT 0
7684+
7685+#define MRV_SMIA_IMSC_ALL_IRQS
7686+#define MRV_SMIA_IMSC_ALL_IRQS_MASK \
7687+(0 \
7688+| MRV_SMIA_IMSC_FIFO_FILL_LEVEL_MASK \
7689+| MRV_SMIA_IMSC_SYNC_FIFO_OVFLW_MASK \
7690+| MRV_SMIA_IMSC_ERR_CS_MASK \
7691+| MRV_SMIA_IMSC_ERR_PROTOCOL_MASK \
7692+| MRV_SMIA_IMSC_EMB_DATA_OVFLW_MASK \
7693+| MRV_SMIA_IMSC_FRAME_END_MASK \
7694+)
7695+#define MRV_SMIA_IMSC_ALL_IRQS_SHIFT 0
7696+
7697+#define MRV_SMIA_RIS_FIFO_FILL_LEVEL
7698+#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK 0x00000020
7699+#define MRV_SMIA_RIS_FIFO_FILL_LEVEL_SHIFT 5
7700+#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW
7701+#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK 0x00000010
7702+#define MRV_SMIA_RIS_SYNC_FIFO_OVFLW_SHIFT 4
7703+#define MRV_SMIA_RIS_ERR_CS
7704+#define MRV_SMIA_RIS_ERR_CS_MASK 0x00000008
7705+#define MRV_SMIA_RIS_ERR_CS_SHIFT 3
7706+#define MRV_SMIA_RIS_ERR_PROTOCOL
7707+#define MRV_SMIA_RIS_ERR_PROTOCOL_MASK 0x00000004
7708+#define MRV_SMIA_RIS_ERR_PROTOCOL_SHIFT 2
7709+
7710+#define MRV_SMIA_RIS_EMB_DATA_OVFLW
7711+#define MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK 0x00000002
7712+#define MRV_SMIA_RIS_EMB_DATA_OVFLW_SHIFT 1
7713+#define MRV_SMIA_RIS_FRAME_END
7714+#define MRV_SMIA_RIS_FRAME_END_MASK 0x00000001
7715+#define MRV_SMIA_RIS_FRAME_END_SHIFT 0
7716+
7717+#define MRV_SMIA_RIS_ALL_IRQS
7718+#define MRV_SMIA_RIS_ALL_IRQS_MASK \
7719+(0 \
7720+| MRV_SMIA_RIS_FIFO_FILL_LEVEL_MASK \
7721+| MRV_SMIA_RIS_SYNC_FIFO_OVFLW_MASK \
7722+| MRV_SMIA_RIS_ERR_CS_MASK \
7723+| MRV_SMIA_RIS_ERR_PROTOCOL_MASK \
7724+| MRV_SMIA_RIS_EMB_DATA_OVFLW_MASK \
7725+| MRV_SMIA_RIS_FRAME_END_MASK \
7726+)
7727+#define MRV_SMIA_RIS_ALL_IRQS_SHIFT 0
7728+
7729+#define MRV_SMIA_MIS_FIFO_FILL_LEVEL
7730+#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK 0x00000020
7731+#define MRV_SMIA_MIS_FIFO_FILL_LEVEL_SHIFT 5
7732+#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW
7733+#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK 0x00000010
7734+#define MRV_SMIA_MIS_SYNC_FIFO_OVFLW_SHIFT 4
7735+#define MRV_SMIA_MIS_ERR_CS
7736+#define MRV_SMIA_MIS_ERR_CS_MASK 0x00000008
7737+#define MRV_SMIA_MIS_ERR_CS_SHIFT 3
7738+#define MRV_SMIA_MIS_ERR_PROTOCOL
7739+#define MRV_SMIA_MIS_ERR_PROTOCOL_MASK 0x00000004
7740+#define MRV_SMIA_MIS_ERR_PROTOCOL_SHIFT 2
7741+
7742+#define MRV_SMIA_MIS_EMB_DATA_OVFLW
7743+#define MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK 0x00000002
7744+#define MRV_SMIA_MIS_EMB_DATA_OVFLW_SHIFT 1
7745+#define MRV_SMIA_MIS_FRAME_END
7746+#define MRV_SMIA_MIS_FRAME_END_MASK 0x00000001
7747+#define MRV_SMIA_MIS_FRAME_END_SHIFT 0
7748+
7749+#define MRV_SMIA_MIS_ALL_IRQS
7750+#define MRV_SMIA_MIS_ALL_IRQS_MASK \
7751+(0 \
7752+| MRV_SMIA_MIS_FIFO_FILL_LEVEL_MASK \
7753+| MRV_SMIA_MIS_SYNC_FIFO_OVFLW_MASK \
7754+| MRV_SMIA_MIS_ERR_CS_MASK \
7755+| MRV_SMIA_MIS_ERR_PROTOCOL_MASK \
7756+| MRV_SMIA_MIS_EMB_DATA_OVFLW_MASK \
7757+| MRV_SMIA_MIS_FRAME_END_MASK \
7758+)
7759+#define MRV_SMIA_MIS_ALL_IRQS_SHIFT 0
7760+
7761+
7762+#define MRV_SMIA_ICR_FIFO_FILL_LEVEL
7763+#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK 0x00000020
7764+#define MRV_SMIA_ICR_FIFO_FILL_LEVEL_SHIFT 5
7765+#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW
7766+#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK 0x00000010
7767+#define MRV_SMIA_ICR_SYNC_FIFO_OVFLW_SHIFT 4
7768+#define MRV_SMIA_ICR_ERR_CS
7769+#define MRV_SMIA_ICR_ERR_CS_MASK 0x00000008
7770+#define MRV_SMIA_ICR_ERR_CS_SHIFT 3
7771+#define MRV_SMIA_ICR_ERR_PROTOCOL
7772+#define MRV_SMIA_ICR_ERR_PROTOCOL_MASK 0x00000004
7773+#define MRV_SMIA_ICR_ERR_PROTOCOL_SHIFT 2
7774+
7775+#define MRV_SMIA_ICR_EMB_DATA_OVFLW
7776+#define MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK 0x00000002
7777+#define MRV_SMIA_ICR_EMB_DATA_OVFLW_SHIFT 1
7778+#define MRV_SMIA_ICR_FRAME_END
7779+#define MRV_SMIA_ICR_FRAME_END_MASK 0x00000001
7780+#define MRV_SMIA_ICR_FRAME_END_SHIFT 0
7781+
7782+#define MRV_SMIA_ICR_ALL_IRQS
7783+#define MRV_SMIA_ICR_ALL_IRQS_MASK \
7784+(0 \
7785+| MRV_SMIA_ICR_FIFO_FILL_LEVEL_MASK \
7786+| MRV_SMIA_ICR_SYNC_FIFO_OVFLW_MASK \
7787+| MRV_SMIA_ICR_ERR_CS_MASK \
7788+| MRV_SMIA_ICR_ERR_PROTOCOL_MASK \
7789+| MRV_SMIA_ICR_EMB_DATA_OVFLW_MASK \
7790+| MRV_SMIA_ICR_FRAME_END_MASK \
7791+)
7792+#define MRV_SMIA_ICR_ALL_IRQS_SHIFT 0
7793+
7794+
7795+#define MRV_SMIA_ISR_FIFO_FILL_LEVEL
7796+#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK 0x00000020
7797+#define MRV_SMIA_ISR_FIFO_FILL_LEVEL_SHIFT 5
7798+#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW
7799+#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK 0x00000010
7800+#define MRV_SMIA_ISR_SYNC_FIFO_OVFLW_SHIFT 4
7801+#define MRV_SMIA_ISR_ERR_CS
7802+#define MRV_SMIA_ISR_ERR_CS_MASK 0x00000008
7803+#define MRV_SMIA_ISR_ERR_CS_SHIFT 3
7804+#define MRV_SMIA_ISR_ERR_PROTOCOL
7805+#define MRV_SMIA_ISR_ERR_PROTOCOL_MASK 0x00000004
7806+#define MRV_SMIA_ISR_ERR_PROTOCOL_SHIFT 2
7807+
7808+#define MRV_SMIA_ISR_EMB_DATA_OVFLW
7809+#define MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK 0x00000002
7810+#define MRV_SMIA_ISR_EMB_DATA_OVFLW_SHIFT 1
7811+#define MRV_SMIA_ISR_FRAME_END
7812+#define MRV_SMIA_ISR_FRAME_END_MASK 0x00000001
7813+#define MRV_SMIA_ISR_FRAME_END_SHIFT 0
7814+
7815+#define MRV_SMIA_ISR_ALL_IRQS
7816+#define MRV_SMIA_ISR_ALL_IRQS_MASK \
7817+(0 \
7818+| MRV_SMIA_ISR_FIFO_FILL_LEVEL_MASK \
7819+| MRV_SMIA_ISR_SYNC_FIFO_OVFLW_MASK \
7820+| MRV_SMIA_ISR_ERR_CS_MASK \
7821+| MRV_SMIA_ISR_ERR_PROTOCOL_MASK \
7822+| MRV_SMIA_ISR_EMB_DATA_OVFLW_MASK \
7823+| MRV_SMIA_ISR_FRAME_END_MASK \
7824+)
7825+#define MRV_SMIA_ISR_ALL_IRQS_SHIFT 0
7826+
7827+#define MRV_SMIA_DATA_FORMAT_SEL
7828+#define MRV_SMIA_DATA_FORMAT_SEL_MASK 0x0000000F
7829+#define MRV_SMIA_DATA_FORMAT_SEL_SHIFT 0
7830+#define MRV_SMIA_DATA_FORMAT_SEL_YUV422 0
7831+#define MRV_SMIA_DATA_FORMAT_SEL_YUV420 1
7832+#define MRV_SMIA_DATA_FORMAT_SEL_RGB444 4
7833+#define MRV_SMIA_DATA_FORMAT_SEL_RGB565 5
7834+#define MRV_SMIA_DATA_FORMAT_SEL_RGB888 6
7835+#define MRV_SMIA_DATA_FORMAT_SEL_RAW6 8
7836+#define MRV_SMIA_DATA_FORMAT_SEL_RAW7 9
7837+#define MRV_SMIA_DATA_FORMAT_SEL_RAW8 10
7838+#define MRV_SMIA_DATA_FORMAT_SEL_RAW10 11
7839+#define MRV_SMIA_DATA_FORMAT_SEL_RAW12 12
7840+#define MRV_SMIA_DATA_FORMAT_SEL_RAW8TO10 13
7841+#define MRV_SMIA_DATA_FORMAT_SEL_COMPRESSED 15
7842+
7843+
7844+#define MRV_SMIA_SOF_EMB_DATA_LINES
7845+#define MRV_SMIA_SOF_EMB_DATA_LINES_MASK 0x00000007
7846+#define MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT 0
7847+#define MRV_SMIA_SOF_EMB_DATA_LINES_MIN 0
7848+#define MRV_SMIA_SOF_EMB_DATA_LINES_MAX \
7849+ (MRV_SMIA_SOF_EMB_DATA_LINES_MASK >> MRV_SMIA_SOF_EMB_DATA_LINES_SHIFT)
7850+#define MRV_SMIA_EMB_HSTART
7851+#define MRV_SMIA_EMB_HSTART_MASK 0x00003FFF
7852+#define MRV_SMIA_EMB_HSTART_SHIFT 0
7853+#define MRV_SMIA_EMB_HSTART_VALID_MASK (MRV_SMIA_EMB_HSTART_MASK & ~0x00000003)
7854+
7855+#define MRV_SMIA_EMB_HSIZE
7856+#define MRV_SMIA_EMB_HSIZE_MASK 0x00003FFF
7857+#define MRV_SMIA_EMB_HSIZE_SHIFT 0
7858+#define MRV_SMIA_EMB_HSIZE_VALID_MASK (MRV_SMIA_EMB_HSIZE_MASK & ~0x00000003)
7859+
7860+#define MRV_SMIA_EMB_VSTART
7861+#define MRV_SMIA_EMB_VSTART_MASK 0x00000FFF
7862+#define MRV_SMIA_EMB_VSTART_SHIFT 0
7863+
7864+#define MRV_SMIA_NUM_LINES
7865+#define MRV_SMIA_NUM_LINES_MASK 0x00000FFF
7866+
7867+#define MRV_SMIA_NUM_LINES_SHIFT 0
7868+#define MRV_SMIA_NUM_LINES_MIN 1
7869+#define MRV_SMIA_NUM_LINES_MAX \
7870+ (MRV_SMIA_NUM_LINES_MASK >> MRV_SMIA_NUM_LINES_SHIFT)
7871+
7872+#define MRV_SMIA_EMB_DATA_FIFO
7873+#define MRV_SMIA_EMB_DATA_FIFO_MASK 0xFFFFFFFF
7874+#define MRV_SMIA_EMB_DATA_FIFO_SHIFT 0
7875+
7876+#define MRV_SMIA_FIFO_FILL_LEVEL
7877+#define MRV_SMIA_FIFO_FILL_LEVEL_MASK 0x000003FF
7878+#define MRV_SMIA_FIFO_FILL_LEVEL_SHIFT 0
7879+#define MRV_SMIA_FIFO_FILL_LEVEL_VALID_MASK \
7880+ (MRV_SMIA_FIFO_FILL_LEVEL_MASK & ~0x00000003)
7881+
7882+#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP
7883+#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_MASK 0x00020000
7884+#define MRV_MIPI_ERR_SOT_SYNC_HS_SKIP_SHIFT 17
7885+#define MRV_MIPI_ERR_SOT_HS_SKIP
7886+#define MRV_MIPI_ERR_SOT_HS_SKIP_MASK 0x00010000
7887+#define MRV_MIPI_ERR_SOT_HS_SKIP_SHIFT 16
7888+
7889+#define MRV_MIPI_NUM_LANES
7890+#define MRV_MIPI_NUM_LANES_MASK 0x00003000
7891+#define MRV_MIPI_NUM_LANES_SHIFT 12
7892+#define MRV_MIPI_SHUTDOWN_LANE
7893+#define MRV_MIPI_SHUTDOWN_LANE_MASK 0x00000F00
7894+#define MRV_MIPI_SHUTDOWN_LANE_SHIFT 8
7895+#define MRV_MIPI_FLUSH_FIFO
7896+#define MRV_MIPI_FLUSH_FIFO_MASK 0x00000002
7897+#define MRV_MIPI_FLUSH_FIFO_SHIFT 1
7898+#define MRV_MIPI_OUTPUT_ENA
7899+#define MRV_MIPI_OUTPUT_ENA_MASK 0x00000001
7900+#define MRV_MIPI_OUTPUT_ENA_SHIFT 0
7901+
7902+#define MRV_MIPI_STOPSTATE
7903+#define MRV_MIPI_STOPSTATE_MASK 0x00000F00
7904+#define MRV_MIPI_STOPSTATE_SHIFT 8
7905+#define MRV_MIPI_ADD_DATA_AVAIL
7906+#define MRV_MIPI_ADD_DATA_AVAIL_MASK 0x00000001
7907+#define MRV_MIPI_ADD_DATA_AVAIL_SHIFT 0
7908+
7909+#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL
7910+#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK 0x04000000
7911+#define MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_SHIFT 26
7912+#define MRV_MIPI_IMSC_ADD_DATA_OVFLW
7913+#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK 0x02000000
7914+#define MRV_MIPI_IMSC_ADD_DATA_OVFLW_SHIFT 25
7915+#define MRV_MIPI_IMSC_FRAME_END
7916+#define MRV_MIPI_IMSC_FRAME_END_MASK 0x01000000
7917+#define MRV_MIPI_IMSC_FRAME_END_SHIFT 24
7918+#define MRV_MIPI_IMSC_ERR_CS
7919+#define MRV_MIPI_IMSC_ERR_CS_MASK 0x00800000
7920+#define MRV_MIPI_IMSC_ERR_CS_SHIFT 23
7921+#define MRV_MIPI_IMSC_ERR_ECC1
7922+#define MRV_MIPI_IMSC_ERR_ECC1_MASK 0x00400000
7923+#define MRV_MIPI_IMSC_ERR_ECC1_SHIFT 22
7924+#define MRV_MIPI_IMSC_ERR_ECC2
7925+#define MRV_MIPI_IMSC_ERR_ECC2_MASK 0x00200000
7926+#define MRV_MIPI_IMSC_ERR_ECC2_SHIFT 21
7927+#define MRV_MIPI_IMSC_ERR_PROTOCOL
7928+#define MRV_MIPI_IMSC_ERR_PROTOCOL_MASK 0x00100000
7929+#define MRV_MIPI_IMSC_ERR_PROTOCOL_SHIFT 20
7930+#define MRV_MIPI_IMSC_ERR_CONTROL
7931+#define MRV_MIPI_IMSC_ERR_CONTROL_MASK 0x000F0000
7932+#define MRV_MIPI_IMSC_ERR_CONTROL_SHIFT 16
7933+
7934+#define MRV_MIPI_IMSC_ERR_EOT_SYNC
7935+#define MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK 0x0000F000
7936+#define MRV_MIPI_IMSC_ERR_EOT_SYNC_SHIFT 12
7937+#define MRV_MIPI_IMSC_ERR_SOT_SYNC
7938+#define MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK 0x00000F00
7939+#define MRV_MIPI_IMSC_ERR_SOT_SYNC_SHIFT 8
7940+#define MRV_MIPI_IMSC_ERR_SOT
7941+#define MRV_MIPI_IMSC_ERR_SOT_MASK 0x000000F0
7942+#define MRV_MIPI_IMSC_ERR_SOT_SHIFT 4
7943+#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW
7944+#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK 0x0000000F
7945+#define MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_SHIFT 0
7946+
7947+#define MRV_MIPI_IMSC_ALL_IRQS
7948+#define MRV_MIPI_IMSC_ALL_IRQS_MASK \
7949+(0 \
7950+| MRV_MIPI_IMSC_ADD_DATA_FILL_LEVEL_MASK \
7951+| MRV_MIPI_IMSC_ADD_DATA_OVFLW_MASK \
7952+| MRV_MIPI_IMSC_FRAME_END_MASK \
7953+| MRV_MIPI_IMSC_ERR_CS_MASK \
7954+| MRV_MIPI_IMSC_ERR_ECC1_MASK \
7955+| MRV_MIPI_IMSC_ERR_ECC2_MASK \
7956+| MRV_MIPI_IMSC_ERR_PROTOCOL_MASK \
7957+| MRV_MIPI_IMSC_ERR_CONTROL_MASK \
7958+| MRV_MIPI_IMSC_ERR_EOT_SYNC_MASK \
7959+| MRV_MIPI_IMSC_ERR_SOT_SYNC_MASK \
7960+| MRV_MIPI_IMSC_ERR_SOT_MASK \
7961+| MRV_MIPI_IMSC_SYNC_FIFO_OVFLW_MASK \
7962+)
7963+#define MRV_MIPI_IMSC_ALL_IRQS_SHIFT 0
7964+
7965+#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL
7966+#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000
7967+#define MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_SHIFT 26
7968+#define MRV_MIPI_RIS_ADD_DATA_OVFLW
7969+#define MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK 0x02000000
7970+#define MRV_MIPI_RIS_ADD_DATA_OVFLW_SHIFT 25
7971+#define MRV_MIPI_RIS_FRAME_END
7972+#define MRV_MIPI_RIS_FRAME_END_MASK 0x01000000
7973+#define MRV_MIPI_RIS_FRAME_END_SHIFT 24
7974+#define MRV_MIPI_RIS_ERR_CS
7975+#define MRV_MIPI_RIS_ERR_CS_MASK 0x00800000
7976+#define MRV_MIPI_RIS_ERR_CS_SHIFT 23
7977+#define MRV_MIPI_RIS_ERR_ECC1
7978+#define MRV_MIPI_RIS_ERR_ECC1_MASK 0x00400000
7979+#define MRV_MIPI_RIS_ERR_ECC1_SHIFT 22
7980+#define MRV_MIPI_RIS_ERR_ECC2
7981+#define MRV_MIPI_RIS_ERR_ECC2_MASK 0x00200000
7982+#define MRV_MIPI_RIS_ERR_ECC2_SHIFT 21
7983+#define MRV_MIPI_RIS_ERR_PROTOCOL
7984+#define MRV_MIPI_RIS_ERR_PROTOCOL_MASK 0x00100000
7985+#define MRV_MIPI_RIS_ERR_PROTOCOL_SHIFT 20
7986+#define MRV_MIPI_RIS_ERR_CONTROL
7987+#define MRV_MIPI_RIS_ERR_CONTROL_MASK 0x000F0000
7988+#define MRV_MIPI_RIS_ERR_CONTROL_SHIFT 16
7989+#define MRV_MIPI_RIS_ERR_EOT_SYNC
7990+#define MRV_MIPI_RIS_ERR_EOT_SYNC_MASK 0x0000F000
7991+#define MRV_MIPI_RIS_ERR_EOT_SYNC_SHIFT 12
7992+#define MRV_MIPI_RIS_ERR_SOT_SYNC
7993+#define MRV_MIPI_RIS_ERR_SOT_SYNC_MASK 0x00000F00
7994+#define MRV_MIPI_RIS_ERR_SOT_SYNC_SHIFT 8
7995+#define MRV_MIPI_RIS_ERR_SOT
7996+#define MRV_MIPI_RIS_ERR_SOT_MASK 0x000000F0
7997+#define MRV_MIPI_RIS_ERR_SOT_SHIFT 4
7998+#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW
7999+#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK 0x0000000F
8000+#define MRV_MIPI_RIS_SYNC_FIFO_OVFLW_SHIFT 0
8001+
8002+#define MRV_MIPI_RIS_ALL_IRQS
8003+#define MRV_MIPI_RIS_ALL_IRQS_MASK \
8004+(0 \
8005+| MRV_MIPI_RIS_ADD_DATA_FILL_LEVEL_MASK \
8006+| MRV_MIPI_RIS_ADD_DATA_OVFLW_MASK \
8007+| MRV_MIPI_RIS_FRAME_END_MASK \
8008+| MRV_MIPI_RIS_ERR_CS_MASK \
8009+| MRV_MIPI_RIS_ERR_ECC1_MASK \
8010+| MRV_MIPI_RIS_ERR_ECC2_MASK \
8011+| MRV_MIPI_RIS_ERR_PROTOCOL_MASK \
8012+| MRV_MIPI_RIS_ERR_CONTROL_MASK \
8013+| MRV_MIPI_RIS_ERR_EOT_SYNC_MASK \
8014+| MRV_MIPI_RIS_ERR_SOT_SYNC_MASK \
8015+| MRV_MIPI_RIS_ERR_SOT_MASK \
8016+| MRV_MIPI_RIS_SYNC_FIFO_OVFLW_MASK \
8017+)
8018+#define MRV_MIPI_RIS_ALL_IRQS_SHIFT 0
8019+
8020+#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL
8021+#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK 0x04000000
8022+#define MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_SHIFT 26
8023+#define MRV_MIPI_MIS_ADD_DATA_OVFLW
8024+#define MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK 0x02000000
8025+#define MRV_MIPI_MIS_ADD_DATA_OVFLW_SHIFT 25
8026+#define MRV_MIPI_MIS_FRAME_END
8027+#define MRV_MIPI_MIS_FRAME_END_MASK 0x01000000
8028+#define MRV_MIPI_MIS_FRAME_END_SHIFT 24
8029+#define MRV_MIPI_MIS_ERR_CS
8030+#define MRV_MIPI_MIS_ERR_CS_MASK 0x00800000
8031+#define MRV_MIPI_MIS_ERR_CS_SHIFT 23
8032+#define MRV_MIPI_MIS_ERR_ECC1
8033+#define MRV_MIPI_MIS_ERR_ECC1_MASK 0x00400000
8034+#define MRV_MIPI_MIS_ERR_ECC1_SHIFT 22
8035+#define MRV_MIPI_MIS_ERR_ECC2
8036+#define MRV_MIPI_MIS_ERR_ECC2_MASK 0x00200000
8037+#define MRV_MIPI_MIS_ERR_ECC2_SHIFT 21
8038+#define MRV_MIPI_MIS_ERR_PROTOCOL
8039+#define MRV_MIPI_MIS_ERR_PROTOCOL_MASK 0x00100000
8040+#define MRV_MIPI_MIS_ERR_PROTOCOL_SHIFT 20
8041+#define MRV_MIPI_MIS_ERR_CONTROL
8042+#define MRV_MIPI_MIS_ERR_CONTROL_MASK 0x000F0000
8043+#define MRV_MIPI_MIS_ERR_CONTROL_SHIFT 16
8044+#define MRV_MIPI_MIS_ERR_EOT_SYNC
8045+#define MRV_MIPI_MIS_ERR_EOT_SYNC_MASK 0x0000F000
8046+#define MRV_MIPI_MIS_ERR_EOT_SYNC_SHIFT 12
8047+#define MRV_MIPI_MIS_ERR_SOT_SYNC
8048+#define MRV_MIPI_MIS_ERR_SOT_SYNC_MASK 0x00000F00
8049+#define MRV_MIPI_MIS_ERR_SOT_SYNC_SHIFT 8
8050+#define MRV_MIPI_MIS_ERR_SOT
8051+#define MRV_MIPI_MIS_ERR_SOT_MASK 0x000000F0
8052+#define MRV_MIPI_MIS_ERR_SOT_SHIFT 4
8053+#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW
8054+#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK 0x0000000F
8055+#define MRV_MIPI_MIS_SYNC_FIFO_OVFLW_SHIFT 0
8056+
8057+#define MRV_MIPI_MIS_ALL_IRQS
8058+#define MRV_MIPI_MIS_ALL_IRQS_MASK \
8059+(0 \
8060+| MRV_MIPI_MIS_ADD_DATA_FILL_LEVEL_MASK \
8061+| MRV_MIPI_MIS_ADD_DATA_OVFLW_MASK \
8062+| MRV_MIPI_MIS_FRAME_END_MASK \
8063+| MRV_MIPI_MIS_ERR_CS_MASK \
8064+| MRV_MIPI_MIS_ERR_ECC1_MASK \
8065+| MRV_MIPI_MIS_ERR_ECC2_MASK \
8066+| MRV_MIPI_MIS_ERR_PROTOCOL_MASK \
8067+| MRV_MIPI_MIS_ERR_CONTROL_MASK \
8068+| MRV_MIPI_MIS_ERR_EOT_SYNC_MASK \
8069+| MRV_MIPI_MIS_ERR_SOT_SYNC_MASK \
8070+| MRV_MIPI_MIS_ERR_SOT_MASK \
8071+| MRV_MIPI_MIS_SYNC_FIFO_OVFLW_MASK \
8072+)
8073+#define MRV_MIPI_MIS_ALL_IRQS_SHIFT 0
8074+
8075+#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL
8076+#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK 0x04000000
8077+#define MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_SHIFT 26
8078+#define MRV_MIPI_ICR_ADD_DATA_OVFLW
8079+#define MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK 0x02000000
8080+#define MRV_MIPI_ICR_ADD_DATA_OVFLW_SHIFT 25
8081+#define MRV_MIPI_ICR_FRAME_END
8082+#define MRV_MIPI_ICR_FRAME_END_MASK 0x01000000
8083+#define MRV_MIPI_ICR_FRAME_END_SHIFT 24
8084+#define MRV_MIPI_ICR_ERR_CS
8085+#define MRV_MIPI_ICR_ERR_CS_MASK 0x00800000
8086+#define MRV_MIPI_ICR_ERR_CS_SHIFT 23
8087+#define MRV_MIPI_ICR_ERR_ECC1
8088+#define MRV_MIPI_ICR_ERR_ECC1_MASK 0x00400000
8089+#define MRV_MIPI_ICR_ERR_ECC1_SHIFT 22
8090+#define MRV_MIPI_ICR_ERR_ECC2
8091+#define MRV_MIPI_ICR_ERR_ECC2_MASK 0x00200000
8092+#define MRV_MIPI_ICR_ERR_ECC2_SHIFT 21
8093+#define MRV_MIPI_ICR_ERR_PROTOCOL
8094+#define MRV_MIPI_ICR_ERR_PROTOCOL_MASK 0x00100000
8095+#define MRV_MIPI_ICR_ERR_PROTOCOL_SHIFT 20
8096+#define MRV_MIPI_ICR_ERR_CONTROL
8097+#define MRV_MIPI_ICR_ERR_CONTROL_MASK 0x000F0000
8098+#define MRV_MIPI_ICR_ERR_CONTROL_SHIFT 16
8099+#define MRV_MIPI_ICR_ERR_EOT_SYNC
8100+#define MRV_MIPI_ICR_ERR_EOT_SYNC_MASK 0x0000F000
8101+#define MRV_MIPI_ICR_ERR_EOT_SYNC_SHIFT 12
8102+#define MRV_MIPI_ICR_ERR_SOT_SYNC
8103+#define MRV_MIPI_ICR_ERR_SOT_SYNC_MASK 0x00000F00
8104+#define MRV_MIPI_ICR_ERR_SOT_SYNC_SHIFT 8
8105+#define MRV_MIPI_ICR_ERR_SOT
8106+#define MRV_MIPI_ICR_ERR_SOT_MASK 0x000000F0
8107+#define MRV_MIPI_ICR_ERR_SOT_SHIFT 4
8108+#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW
8109+#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK 0x0000000F
8110+#define MRV_MIPI_ICR_SYNC_FIFO_OVFLW_SHIFT 0
8111+
8112+#define MRV_MIPI_ICR_ALL_IRQS
8113+#define MRV_MIPI_ICR_ALL_IRQS_MASK \
8114+(0 \
8115+| MRV_MIPI_ICR_ADD_DATA_FILL_LEVEL_MASK \
8116+| MRV_MIPI_ICR_ADD_DATA_OVFLW_MASK \
8117+| MRV_MIPI_ICR_FRAME_END_MASK \
8118+| MRV_MIPI_ICR_ERR_CS_MASK \
8119+| MRV_MIPI_ICR_ERR_ECC1_MASK \
8120+| MRV_MIPI_ICR_ERR_ECC2_MASK \
8121+| MRV_MIPI_ICR_ERR_PROTOCOL_MASK \
8122+| MRV_MIPI_ICR_ERR_CONTROL_MASK \
8123+| MRV_MIPI_ICR_ERR_EOT_SYNC_MASK \
8124+| MRV_MIPI_ICR_ERR_SOT_SYNC_MASK \
8125+| MRV_MIPI_ICR_ERR_SOT_MASK \
8126+| MRV_MIPI_ICR_SYNC_FIFO_OVFLW_MASK \
8127+)
8128+#define MRV_MIPI_ICR_ALL_IRQS_SHIFT 0
8129+
8130+
8131+#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL
8132+#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK 0x04000000
8133+#define MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_SHIFT 26
8134+#define MRV_MIPI_ISR_ADD_DATA_OVFLW
8135+#define MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK 0x02000000
8136+#define MRV_MIPI_ISR_ADD_DATA_OVFLW_SHIFT 25
8137+#define MRV_MIPI_ISR_FRAME_END
8138+#define MRV_MIPI_ISR_FRAME_END_MASK 0x01000000
8139+#define MRV_MIPI_ISR_FRAME_END_SHIFT 24
8140+#define MRV_MIPI_ISR_ERR_CS
8141+#define MRV_MIPI_ISR_ERR_CS_MASK 0x00800000
8142+#define MRV_MIPI_ISR_ERR_CS_SHIFT 23
8143+#define MRV_MIPI_ISR_ERR_ECC1
8144+#define MRV_MIPI_ISR_ERR_ECC1_MASK 0x00400000
8145+#define MRV_MIPI_ISR_ERR_ECC1_SHIFT 22
8146+#define MRV_MIPI_ISR_ERR_ECC2
8147+#define MRV_MIPI_ISR_ERR_ECC2_MASK 0x00200000
8148+#define MRV_MIPI_ISR_ERR_ECC2_SHIFT 21
8149+#define MRV_MIPI_ISR_ERR_PROTOCOL
8150+#define MRV_MIPI_ISR_ERR_PROTOCOL_MASK 0x00100000
8151+#define MRV_MIPI_ISR_ERR_PROTOCOL_SHIFT 20
8152+#define MRV_MIPI_ISR_ERR_CONTROL
8153+#define MRV_MIPI_ISR_ERR_CONTROL_MASK 0x000F0000
8154+#define MRV_MIPI_ISR_ERR_CONTROL_SHIFT 16
8155+#define MRV_MIPI_ISR_ERR_EOT_SYNC
8156+#define MRV_MIPI_ISR_ERR_EOT_SYNC_MASK 0x0000F000
8157+#define MRV_MIPI_ISR_ERR_EOT_SYNC_SHIFT 12
8158+#define MRV_MIPI_ISR_ERR_SOT_SYNC
8159+#define MRV_MIPI_ISR_ERR_SOT_SYNC_MASK 0x00000F00
8160+#define MRV_MIPI_ISR_ERR_SOT_SYNC_SHIFT 8
8161+#define MRV_MIPI_ISR_ERR_SOT
8162+#define MRV_MIPI_ISR_ERR_SOT_MASK 0x000000F0
8163+#define MRV_MIPI_ISR_ERR_SOT_SHIFT 4
8164+#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW
8165+#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK 0x0000000F
8166+#define MRV_MIPI_ISR_SYNC_FIFO_OVFLW_SHIFT 0
8167+
8168+#define MRV_MIPI_ISR_ALL_IRQS
8169+#define MRV_MIPI_ISR_ALL_IRQS_MASK \
8170+(0 \
8171+| MRV_MIPI_ISR_ADD_DATA_FILL_LEVEL_MASK \
8172+| MRV_MIPI_ISR_ADD_DATA_OVFLW_MASK \
8173+| MRV_MIPI_ISR_FRAME_END_MASK \
8174+| MRV_MIPI_ISR_ERR_CS_MASK \
8175+| MRV_MIPI_ISR_ERR_ECC1_MASK \
8176+| MRV_MIPI_ISR_ERR_ECC2_MASK \
8177+| MRV_MIPI_ISR_ERR_PROTOCOL_MASK \
8178+| MRV_MIPI_ISR_ERR_CONTROL_MASK \
8179+| MRV_MIPI_ISR_ERR_EOT_SYNC_MASK \
8180+| MRV_MIPI_ISR_ERR_SOT_SYNC_MASK \
8181+| MRV_MIPI_ISR_ERR_SOT_MASK \
8182+| MRV_MIPI_ISR_SYNC_FIFO_OVFLW_MASK \
8183+)
8184+#define MRV_MIPI_ISR_ALL_IRQS_SHIFT 0
8185+
8186+
8187+#define MRV_MIPI_VIRTUAL_CHANNEL
8188+#define MRV_MIPI_VIRTUAL_CHANNEL_MASK 0x000000C0
8189+#define MRV_MIPI_VIRTUAL_CHANNEL_SHIFT 6
8190+
8191+#define MRV_MIPI_VIRTUAL_CHANNEL_MAX \
8192+ (MRV_MIPI_VIRTUAL_CHANNEL_MASK >> MRV_MIPI_VIRTUAL_CHANNEL_SHIFT)
8193+#define MRV_MIPI_DATA_TYPE
8194+#define MRV_MIPI_DATA_TYPE_MASK 0x0000003F
8195+#define MRV_MIPI_DATA_TYPE_SHIFT 0
8196+
8197+#define MRV_MIPI_DATA_TYPE_MAX \
8198+ (MRV_MIPI_DATA_TYPE_MASK >> MRV_MIPI_DATA_TYPE_SHIFT)
8199+
8200+
8201+#define MRV_MIPI_VIRTUAL_CHANNEL_SEL
8202+#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_MASK 0x000000C0
8203+#define MRV_MIPI_VIRTUAL_CHANNEL_SEL_SHIFT 6
8204+#define MRV_MIPI_DATA_TYPE_SEL
8205+#define MRV_MIPI_DATA_TYPE_SEL_MASK 0x0000003F
8206+#define MRV_MIPI_DATA_TYPE_SEL_SHIFT 0
8207+#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT 24
8208+#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT 25
8209+#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_LEGACY 26
8210+#define MRV_MIPI_DATA_TYPE_SEL_YUV420_8BIT_CSPS 28
8211+#define MRV_MIPI_DATA_TYPE_SEL_YUV420_10BIT_CSPS 29
8212+#define MRV_MIPI_DATA_TYPE_SEL_YUV422_8BIT 30
8213+#define MRV_MIPI_DATA_TYPE_SEL_YUV422_10BIT 31
8214+#define MRV_MIPI_DATA_TYPE_SEL_RGB444 32
8215+#define MRV_MIPI_DATA_TYPE_SEL_RGB555 33
8216+#define MRV_MIPI_DATA_TYPE_SEL_RGB565 34
8217+#define MRV_MIPI_DATA_TYPE_SEL_RGB666 35
8218+#define MRV_MIPI_DATA_TYPE_SEL_RGB888 36
8219+#define MRV_MIPI_DATA_TYPE_SEL_RAW6 40
8220+#define MRV_MIPI_DATA_TYPE_SEL_RAW7 41
8221+#define MRV_MIPI_DATA_TYPE_SEL_RAW8 42
8222+#define MRV_MIPI_DATA_TYPE_SEL_RAW10 43
8223+#define MRV_MIPI_DATA_TYPE_SEL_RAW12 44
8224+#define MRV_MIPI_DATA_TYPE_SEL_USER1 48
8225+#define MRV_MIPI_DATA_TYPE_SEL_USER2 49
8226+#define MRV_MIPI_DATA_TYPE_SEL_USER3 50
8227+#define MRV_MIPI_DATA_TYPE_SEL_USER4 51
8228+
8229+
8230+#define MRV_MIPI_ADD_DATA_VC_1
8231+#define MRV_MIPI_ADD_DATA_VC_1_MASK 0x000000C0
8232+#define MRV_MIPI_ADD_DATA_VC_1_SHIFT 6
8233+#define MRV_MIPI_ADD_DATA_TYPE_1
8234+#define MRV_MIPI_ADD_DATA_TYPE_1_MASK 0x0000003F
8235+#define MRV_MIPI_ADD_DATA_TYPE_1_SHIFT 0
8236+
8237+
8238+#define MRV_MIPI_ADD_DATA_VC_2
8239+#define MRV_MIPI_ADD_DATA_VC_2_MASK 0x000000C0
8240+#define MRV_MIPI_ADD_DATA_VC_2_SHIFT 6
8241+#define MRV_MIPI_ADD_DATA_TYPE_2
8242+#define MRV_MIPI_ADD_DATA_TYPE_2_MASK 0x0000003F
8243+#define MRV_MIPI_ADD_DATA_TYPE_2_SHIFT 0
8244+
8245+
8246+#define MRV_MIPI_ADD_DATA_VC_3
8247+#define MRV_MIPI_ADD_DATA_VC_3_MASK 0x000000C0
8248+#define MRV_MIPI_ADD_DATA_VC_3_SHIFT 6
8249+#define MRV_MIPI_ADD_DATA_TYPE_3
8250+#define MRV_MIPI_ADD_DATA_TYPE_3_MASK 0x0000003F
8251+#define MRV_MIPI_ADD_DATA_TYPE_3_SHIFT 0
8252+
8253+
8254+#define MRV_MIPI_ADD_DATA_VC_4
8255+#define MRV_MIPI_ADD_DATA_VC_4_MASK 0x000000C0
8256+#define MRV_MIPI_ADD_DATA_VC_4_SHIFT 6
8257+#define MRV_MIPI_ADD_DATA_TYPE_4
8258+#define MRV_MIPI_ADD_DATA_TYPE_4_MASK 0x0000003F
8259+#define MRV_MIPI_ADD_DATA_TYPE_4_SHIFT 0
8260+
8261+#define MRV_MIPI_ADD_DATA_FIFO
8262+#define MRV_MIPI_ADD_DATA_FIFO_MASK 0xFFFFFFFF
8263+#define MRV_MIPI_ADD_DATA_FIFO_SHIFT 0
8264+
8265+#define MRV_MIPI_ADD_DATA_FILL_LEVEL
8266+#define MRV_MIPI_ADD_DATA_FILL_LEVEL_MASK 0x00001FFC
8267+#define MRV_MIPI_ADD_DATA_FILL_LEVEL_SHIFT 0
8268+#define MRV_MIPI_ADD_DATA_FILL_LEVEL_MAX 0x00001FFC
8269+
8270+#define MRV_AFM_AFM_EN
8271+#define MRV_AFM_AFM_EN_MASK 0x00000001
8272+#define MRV_AFM_AFM_EN_SHIFT 0
8273+
8274+#define MRV_AFM_A_H_L
8275+#define MRV_AFM_A_H_L_MASK 0x0FFF0000
8276+#define MRV_AFM_A_H_L_SHIFT 16
8277+#define MRV_AFM_A_H_L_MIN 5
8278+#define MRV_AFM_A_H_L_MAX (MRV_AFM_A_H_L_MASK >> MRV_AFM_A_H_L_SHIFT)
8279+#define MRV_AFM_A_V_T
8280+#define MRV_AFM_A_V_T_MASK 0x00000FFF
8281+#define MRV_AFM_A_V_T_SHIFT 0
8282+#define MRV_AFM_A_V_T_MIN 2
8283+#define MRV_AFM_A_V_T_MAX (MRV_AFM_A_V_T_MASK >> MRV_AFM_A_V_T_SHIFT)
8284+
8285+
8286+#define MRV_AFM_A_H_R
8287+#define MRV_AFM_A_H_R_MASK 0x0FFF0000
8288+#define MRV_AFM_A_H_R_SHIFT 16
8289+#define MRV_AFM_A_H_R_MIN 5
8290+#define MRV_AFM_A_H_R_MAX (MRV_AFM_A_H_R_MASK >> MRV_AFM_A_H_R_SHIFT)
8291+#define MRV_AFM_A_V_B
8292+#define MRV_AFM_A_V_B_MASK 0x00000FFF
8293+#define MRV_AFM_A_V_B_SHIFT 0
8294+#define MRV_AFM_A_V_B_MIN 2
8295+#define MRV_AFM_A_V_B_MAX (MRV_AFM_A_V_B_MASK >> MRV_AFM_A_V_B_SHIFT)
8296+
8297+
8298+#define MRV_AFM_B_H_L
8299+#define MRV_AFM_B_H_L_MASK 0x0FFF0000
8300+#define MRV_AFM_B_H_L_SHIFT 16
8301+#define MRV_AFM_B_H_L_MIN 5
8302+#define MRV_AFM_B_H_L_MAX (MRV_AFM_B_H_L_MASK >> MRV_AFM_B_H_L_SHIFT)
8303+#define MRV_AFM_B_V_T
8304+#define MRV_AFM_B_V_T_MASK 0x00000FFF
8305+#define MRV_AFM_B_V_T_SHIFT 0
8306+#define MRV_AFM_B_V_T_MIN 2
8307+#define MRV_AFM_B_V_T_MAX (MRV_AFM_B_V_T_MASK >> MRV_AFM_B_V_T_SHIFT)
8308+
8309+
8310+#define MRV_AFM_B_H_R
8311+#define MRV_AFM_B_H_R_MASK 0x0FFF0000
8312+#define MRV_AFM_B_H_R_SHIFT 16
8313+#define MRV_AFM_B_H_R_MIN 5
8314+#define MRV_AFM_B_H_R_MAX (MRV_AFM_B_H_R_MASK >> MRV_AFM_B_H_R_SHIFT)
8315+#define MRV_AFM_B_V_B
8316+#define MRV_AFM_B_V_B_MASK 0x00000FFF
8317+#define MRV_AFM_B_V_B_SHIFT 0
8318+#define MRV_AFM_B_V_B_MIN 2
8319+#define MRV_AFM_B_V_B_MAX (MRV_AFM_B_V_B_MASK >> MRV_AFM_B_V_B_SHIFT)
8320+
8321+
8322+#define MRV_AFM_C_H_L
8323+#define MRV_AFM_C_H_L_MASK 0x0FFF0000
8324+#define MRV_AFM_C_H_L_SHIFT 16
8325+#define MRV_AFM_C_H_L_MIN 5
8326+#define MRV_AFM_C_H_L_MAX (MRV_AFM_C_H_L_MASK >> MRV_AFM_C_H_L_SHIFT)
8327+#define MRV_AFM_C_V_T
8328+#define MRV_AFM_C_V_T_MASK 0x00000FFF
8329+#define MRV_AFM_C_V_T_SHIFT 0
8330+#define MRV_AFM_C_V_T_MIN 2
8331+#define MRV_AFM_C_V_T_MAX (MRV_AFM_C_V_T_MASK >> MRV_AFM_C_V_T_SHIFT)
8332+
8333+
8334+#define MRV_AFM_C_H_R
8335+#define MRV_AFM_C_H_R_MASK 0x0FFF0000
8336+#define MRV_AFM_C_H_R_SHIFT 16
8337+#define MRV_AFM_C_H_R_MIN 5
8338+#define MRV_AFM_C_H_R_MAX (MRV_AFM_C_H_R_MASK >> MRV_AFM_C_H_R_SHIFT)
8339+#define MRV_AFM_C_V_B
8340+#define MRV_AFM_C_V_B_MASK 0x00000FFF
8341+#define MRV_AFM_C_V_B_SHIFT 0
8342+#define MRV_AFM_C_V_B_MIN 2
8343+#define MRV_AFM_C_V_B_MAX (MRV_AFM_C_V_B_MASK >> MRV_AFM_C_V_B_SHIFT)
8344+
8345+#define MRV_AFM_AFM_THRES
8346+#define MRV_AFM_AFM_THRES_MASK 0x0000FFFF
8347+#define MRV_AFM_AFM_THRES_SHIFT 0
8348+
8349+#define MRV_AFM_LUM_VAR_SHIFT
8350+#define MRV_AFM_LUM_VAR_SHIFT_MASK 0x00070000
8351+#define MRV_AFM_LUM_VAR_SHIFT_SHIFT 16
8352+#define MRV_AFM_AFM_VAR_SHIFT
8353+#define MRV_AFM_AFM_VAR_SHIFT_MASK 0x00000007
8354+#define MRV_AFM_AFM_VAR_SHIFT_SHIFT 0
8355+
8356+#define MRV_AFM_AFM_SUM_A
8357+#define MRV_AFM_AFM_SUM_A_MASK 0xFFFFFFFF
8358+#define MRV_AFM_AFM_SUM_A_SHIFT 0
8359+
8360+#define MRV_AFM_AFM_SUM_B
8361+#define MRV_AFM_AFM_SUM_B_MASK 0xFFFFFFFF
8362+#define MRV_AFM_AFM_SUM_B_SHIFT 0
8363+
8364+#define MRV_AFM_AFM_SUM_C
8365+#define MRV_AFM_AFM_SUM_C_MASK 0xFFFFFFFF
8366+#define MRV_AFM_AFM_SUM_C_SHIFT 0
8367+
8368+#define MRV_AFM_AFM_LUM_A
8369+#define MRV_AFM_AFM_LUM_A_MASK 0x00FFFFFF
8370+#define MRV_AFM_AFM_LUM_A_SHIFT 0
8371+
8372+#define MRV_AFM_AFM_LUM_B
8373+#define MRV_AFM_AFM_LUM_B_MASK 0x00FFFFFF
8374+#define MRV_AFM_AFM_LUM_B_SHIFT 0
8375+
8376+#define MRV_AFM_AFM_LUM_C
8377+#define MRV_AFM_AFM_LUM_C_MASK 0x00FFFFFF
8378+#define MRV_AFM_AFM_LUM_C_SHIFT 0
8379+
8380+
8381+#define MRV_BP_COR_TYPE
8382+#define MRV_BP_COR_TYPE_MASK 0x00000010
8383+#define MRV_BP_COR_TYPE_SHIFT 4
8384+#define MRV_BP_COR_TYPE_TABLE 0
8385+#define MRV_BP_COR_TYPE_DIRECT 1
8386+#define MRV_BP_REP_APPR
8387+#define MRV_BP_REP_APPR_MASK 0x00000008
8388+#define MRV_BP_REP_APPR_SHIFT 3
8389+#define MRV_BP_REP_APPR_NEAREST 0
8390+#define MRV_BP_REP_APPR_INTERPOL 1
8391+#define MRV_BP_DEAD_COR_EN
8392+#define MRV_BP_DEAD_COR_EN_MASK 0x00000004
8393+#define MRV_BP_DEAD_COR_EN_SHIFT 2
8394+#define MRV_BP_HOT_COR_EN
8395+#define MRV_BP_HOT_COR_EN_MASK 0x00000002
8396+#define MRV_BP_HOT_COR_EN_SHIFT 1
8397+#define MRV_BP_BP_DET_EN
8398+#define MRV_BP_BP_DET_EN_MASK 0x00000001
8399+#define MRV_BP_BP_DET_EN_SHIFT 0
8400+
8401+
8402+
8403+#define MRV_BP_HOT_THRES
8404+#define MRV_BP_HOT_THRES_MASK 0x0FFF0000
8405+#define MRV_BP_HOT_THRES_SHIFT 16
8406+#define MRV_BP_DEAD_THRES
8407+#define MRV_BP_DEAD_THRES_MASK 0x00000FFF
8408+#define MRV_BP_DEAD_THRES_SHIFT 0
8409+
8410+
8411+
8412+#define MRV_BP_DEV_HOT_THRES
8413+#define MRV_BP_DEV_HOT_THRES_MASK 0x0FFF0000
8414+#define MRV_BP_DEV_HOT_THRES_SHIFT 16
8415+#define MRV_BP_DEV_DEAD_THRES
8416+#define MRV_BP_DEV_DEAD_THRES_MASK 0x00000FFF
8417+#define MRV_BP_DEV_DEAD_THRES_SHIFT 0
8418+
8419+
8420+#define MRV_BP_BP_NUMBER
8421+
8422+#define MRV_BP_BP_NUMBER_MASK 0x00000FFF
8423+#define MRV_BP_BP_NUMBER_SHIFT 0
8424+
8425+#define MRV_BP_BP_TABLE_ADDR
8426+#define MRV_BP_BP_TABLE_ADDR_MASK 0x000007FF
8427+
8428+#define MRV_BP_BP_TABLE_ADDR_SHIFT 0
8429+#define MRV_BP_BP_TABLE_ADDR_MAX MRV_BP_BP_TABLE_ADDR_MASK
8430+
8431+
8432+#define MRV_BP_PIX_TYPE
8433+#define MRV_BP_PIX_TYPE_MASK 0x80000000
8434+#define MRV_BP_PIX_TYPE_SHIFT 31
8435+#define MRV_BP_PIX_TYPE_DEAD 0u
8436+#define MRV_BP_PIX_TYPE_HOT 1u
8437+#define MRV_BP_V_ADDR
8438+
8439+#define MRV_BP_V_ADDR_MASK 0x0FFF0000
8440+
8441+#define MRV_BP_V_ADDR_SHIFT 16
8442+#define MRV_BP_H_ADDR
8443+#define MRV_BP_H_ADDR_MASK 0x00000FFF
8444+#define MRV_BP_H_ADDR_SHIFT 0
8445+
8446+
8447+#define MRV_BP_BP_NEW_NUMBER
8448+#define MRV_BP_BP_NEW_NUMBER_MASK 0x0000000F
8449+#define MRV_BP_BP_NEW_NUMBER_SHIFT 0
8450+
8451+
8452+#define MRV_BP_NEW_VALUE
8453+
8454+#define MRV_BP_NEW_VALUE_MASK 0xF8000000
8455+#define MRV_BP_NEW_VALUE_SHIFT 27
8456+#define MRV_BP_NEW_V_ADDR
8457+
8458+#define MRV_BP_NEW_V_ADDR_MASK 0x07FF0000
8459+#define MRV_BP_NEW_V_ADDR_SHIFT 16
8460+#define MRV_BP_NEW_H_ADDR
8461+#define MRV_BP_NEW_H_ADDR_MASK 0x00000FFF
8462+#define MRV_BP_NEW_H_ADDR_SHIFT 0
8463+
8464+
8465+
8466+#define MRV_LSC_LSC_EN
8467+#define MRV_LSC_LSC_EN_MASK 0x00000001
8468+#define MRV_LSC_LSC_EN_SHIFT 0
8469+
8470+#define MRV_LSC_R_RAM_ADDR
8471+#define MRV_LSC_R_RAM_ADDR_MASK 0x000000FF
8472+#define MRV_LSC_R_RAM_ADDR_SHIFT 0
8473+#define MRV_LSC_R_RAM_ADDR_MIN 0x00000000
8474+#define MRV_LSC_R_RAM_ADDR_MAX 0x00000098
8475+
8476+#define MRV_LSC_G_RAM_ADDR
8477+#define MRV_LSC_G_RAM_ADDR_MASK 0x000000FF
8478+#define MRV_LSC_G_RAM_ADDR_SHIFT 0
8479+#define MRV_LSC_G_RAM_ADDR_MIN 0x00000000
8480+#define MRV_LSC_G_RAM_ADDR_MAX 0x00000098
8481+
8482+#define MRV_LSC_B_RAM_ADDR
8483+#define MRV_LSC_B_RAM_ADDR_MASK 0x000000FF
8484+#define MRV_LSC_B_RAM_ADDR_SHIFT 0
8485+#define MRV_LSC_B_RAM_ADDR_MIN 0x00000000
8486+#define MRV_LSC_B_RAM_ADDR_MAX 0x00000098
8487+
8488+#define MRV_LSC_R_SAMPLE_1
8489+#define MRV_LSC_R_SAMPLE_1_MASK 0x00FFF000
8490+#define MRV_LSC_R_SAMPLE_1_SHIFT 12
8491+#define MRV_LSC_R_SAMPLE_0
8492+#define MRV_LSC_R_SAMPLE_0_MASK 0x00000FFF
8493+#define MRV_LSC_R_SAMPLE_0_SHIFT 0
8494+
8495+
8496+#define MRV_LSC_G_SAMPLE_1
8497+#define MRV_LSC_G_SAMPLE_1_MASK 0x00FFF000
8498+#define MRV_LSC_G_SAMPLE_1_SHIFT 12
8499+#define MRV_LSC_G_SAMPLE_0
8500+#define MRV_LSC_G_SAMPLE_0_MASK 0x00000FFF
8501+#define MRV_LSC_G_SAMPLE_0_SHIFT 0
8502+
8503+
8504+#define MRV_LSC_B_SAMPLE_1
8505+#define MRV_LSC_B_SAMPLE_1_MASK 0x00FFF000
8506+#define MRV_LSC_B_SAMPLE_1_SHIFT 12
8507+#define MRV_LSC_B_SAMPLE_0
8508+#define MRV_LSC_B_SAMPLE_0_MASK 0x00000FFF
8509+#define MRV_LSC_B_SAMPLE_0_SHIFT 0
8510+
8511+#define MRV_LSC_XGRAD_1
8512+#define MRV_LSC_XGRAD_1_MASK 0x0FFF0000
8513+#define MRV_LSC_XGRAD_1_SHIFT 16
8514+#define MRV_LSC_XGRAD_0
8515+#define MRV_LSC_XGRAD_0_MASK 0x00000FFF
8516+#define MRV_LSC_XGRAD_0_SHIFT 0
8517+
8518+#define MRV_LSC_XGRAD_3
8519+#define MRV_LSC_XGRAD_3_MASK 0x0FFF0000
8520+#define MRV_LSC_XGRAD_3_SHIFT 16
8521+#define MRV_LSC_XGRAD_2
8522+#define MRV_LSC_XGRAD_2_MASK 0x00000FFF
8523+#define MRV_LSC_XGRAD_2_SHIFT 0
8524+
8525+#define MRV_LSC_XGRAD_5
8526+#define MRV_LSC_XGRAD_5_MASK 0x0FFF0000
8527+#define MRV_LSC_XGRAD_5_SHIFT 16
8528+
8529+#define MRV_LSC_XGRAD_4
8530+#define MRV_LSC_XGRAD_4_MASK 0x00000FFF
8531+#define MRV_LSC_XGRAD_4_SHIFT 0
8532+
8533+
8534+#define MRV_LSC_XGRAD_7
8535+#define MRV_LSC_XGRAD_7_MASK 0x0FFF0000
8536+#define MRV_LSC_XGRAD_7_SHIFT 16
8537+
8538+#define MRV_LSC_XGRAD_6
8539+#define MRV_LSC_XGRAD_6_MASK 0x00000FFF
8540+#define MRV_LSC_XGRAD_6_SHIFT 0
8541+
8542+
8543+#define MRV_LSC_YGRAD_1
8544+#define MRV_LSC_YGRAD_1_MASK 0x0FFF0000
8545+#define MRV_LSC_YGRAD_1_SHIFT 16
8546+#define MRV_LSC_YGRAD_0
8547+#define MRV_LSC_YGRAD_0_MASK 0x00000FFF
8548+#define MRV_LSC_YGRAD_0_SHIFT 0
8549+
8550+
8551+#define MRV_LSC_YGRAD_3
8552+#define MRV_LSC_YGRAD_3_MASK 0x0FFF0000
8553+#define MRV_LSC_YGRAD_3_SHIFT 16
8554+
8555+#define MRV_LSC_YGRAD_2
8556+#define MRV_LSC_YGRAD_2_MASK 0x00000FFF
8557+#define MRV_LSC_YGRAD_2_SHIFT 0
8558+
8559+
8560+#define MRV_LSC_YGRAD_5
8561+#define MRV_LSC_YGRAD_5_MASK 0x0FFF0000
8562+#define MRV_LSC_YGRAD_5_SHIFT 16
8563+
8564+#define MRV_LSC_YGRAD_4
8565+#define MRV_LSC_YGRAD_4_MASK 0x00000FFF
8566+#define MRV_LSC_YGRAD_4_SHIFT 0
8567+
8568+
8569+#define MRV_LSC_YGRAD_7
8570+#define MRV_LSC_YGRAD_7_MASK 0x0FFF0000
8571+#define MRV_LSC_YGRAD_7_SHIFT 16
8572+
8573+#define MRV_LSC_YGRAD_6
8574+#define MRV_LSC_YGRAD_6_MASK 0x00000FFF
8575+#define MRV_LSC_YGRAD_6_SHIFT 0
8576+
8577+
8578+#define MRV_LSC_X_SECT_SIZE_1
8579+#define MRV_LSC_X_SECT_SIZE_1_MASK 0x03FF0000
8580+#define MRV_LSC_X_SECT_SIZE_1_SHIFT 16
8581+
8582+#define MRV_LSC_X_SECT_SIZE_0
8583+#define MRV_LSC_X_SECT_SIZE_0_MASK 0x000003FF
8584+#define MRV_LSC_X_SECT_SIZE_0_SHIFT 0
8585+
8586+
8587+#define MRV_LSC_X_SECT_SIZE_3
8588+#define MRV_LSC_X_SECT_SIZE_3_MASK 0x03FF0000
8589+#define MRV_LSC_X_SECT_SIZE_3_SHIFT 16
8590+
8591+#define MRV_LSC_X_SECT_SIZE_2
8592+#define MRV_LSC_X_SECT_SIZE_2_MASK 0x000003FF
8593+#define MRV_LSC_X_SECT_SIZE_2_SHIFT 0
8594+
8595+
8596+#define MRV_LSC_X_SECT_SIZE_5
8597+#define MRV_LSC_X_SECT_SIZE_5_MASK 0x03FF0000
8598+#define MRV_LSC_X_SECT_SIZE_5_SHIFT 16
8599+
8600+#define MRV_LSC_X_SECT_SIZE_4
8601+#define MRV_LSC_X_SECT_SIZE_4_MASK 0x000003FF
8602+#define MRV_LSC_X_SECT_SIZE_4_SHIFT 0
8603+
8604+
8605+#define MRV_LSC_X_SECT_SIZE_7
8606+#define MRV_LSC_X_SECT_SIZE_7_MASK 0x03FF0000
8607+#define MRV_LSC_X_SECT_SIZE_7_SHIFT 16
8608+
8609+#define MRV_LSC_X_SECT_SIZE_6
8610+#define MRV_LSC_X_SECT_SIZE_6_MASK 0x000003FF
8611+#define MRV_LSC_X_SECT_SIZE_6_SHIFT 0
8612+
8613+
8614+#define MRV_LSC_Y_SECT_SIZE_1
8615+#define MRV_LSC_Y_SECT_SIZE_1_MASK 0x03FF0000
8616+#define MRV_LSC_Y_SECT_SIZE_1_SHIFT 16
8617+#define MRV_LSC_Y_SECT_SIZE_0
8618+#define MRV_LSC_Y_SECT_SIZE_0_MASK 0x000003FF
8619+#define MRV_LSC_Y_SECT_SIZE_0_SHIFT 0
8620+
8621+
8622+#define MRV_LSC_Y_SECT_SIZE_3
8623+#define MRV_LSC_Y_SECT_SIZE_3_MASK 0x03FF0000
8624+#define MRV_LSC_Y_SECT_SIZE_3_SHIFT 16
8625+#define MRV_LSC_Y_SECT_SIZE_2
8626+#define MRV_LSC_Y_SECT_SIZE_2_MASK 0x000003FF
8627+#define MRV_LSC_Y_SECT_SIZE_2_SHIFT 0
8628+
8629+
8630+#define MRV_LSC_Y_SECT_SIZE_5
8631+#define MRV_LSC_Y_SECT_SIZE_5_MASK 0x03FF0000
8632+#define MRV_LSC_Y_SECT_SIZE_5_SHIFT 16
8633+#define MRV_LSC_Y_SECT_SIZE_4
8634+#define MRV_LSC_Y_SECT_SIZE_4_MASK 0x000003FF
8635+#define MRV_LSC_Y_SECT_SIZE_4_SHIFT 0
8636+
8637+
8638+#define MRV_LSC_Y_SECT_SIZE_7
8639+#define MRV_LSC_Y_SECT_SIZE_7_MASK 0x03FF0000
8640+#define MRV_LSC_Y_SECT_SIZE_7_SHIFT 16
8641+#define MRV_LSC_Y_SECT_SIZE_6
8642+#define MRV_LSC_Y_SECT_SIZE_6_MASK 0x000003FF
8643+#define MRV_LSC_Y_SECT_SIZE_6_SHIFT 0
8644+
8645+
8646+#define MRV_IS_IS_EN
8647+#define MRV_IS_IS_EN_MASK 0x00000001
8648+#define MRV_IS_IS_EN_SHIFT 0
8649+
8650+
8651+#define MRV_IS_IS_RECENTER
8652+#define MRV_IS_IS_RECENTER_MASK 0x00000007
8653+#define MRV_IS_IS_RECENTER_SHIFT 0
8654+#define MRV_IS_IS_RECENTER_MAX \
8655+ (MRV_IS_IS_RECENTER_MASK >> MRV_IS_IS_RECENTER_SHIFT)
8656+
8657+
8658+#define MRV_IS_IS_H_OFFS
8659+#define MRV_IS_IS_H_OFFS_MASK 0x00001FFF
8660+#define MRV_IS_IS_H_OFFS_SHIFT 0
8661+
8662+
8663+#define MRV_IS_IS_V_OFFS
8664+#define MRV_IS_IS_V_OFFS_MASK 0x00000FFF
8665+#define MRV_IS_IS_V_OFFS_SHIFT 0
8666+
8667+#define MRV_IS_IS_H_SIZE
8668+#define MRV_IS_IS_H_SIZE_MASK 0x00003FFF
8669+#define MRV_IS_IS_H_SIZE_SHIFT 0
8670+
8671+#define MRV_IS_IS_V_SIZE
8672+#define MRV_IS_IS_V_SIZE_MASK 0x00000FFF
8673+#define MRV_IS_IS_V_SIZE_SHIFT 0
8674+
8675+#define MRV_IS_IS_MAX_DX
8676+#define MRV_IS_IS_MAX_DX_MASK 0x00000FFF
8677+#define MRV_IS_IS_MAX_DX_SHIFT 0
8678+#define MRV_IS_IS_MAX_DX_MAX (MRV_IS_IS_MAX_DX_MASK >> MRV_IS_IS_MAX_DX_SHIFT)
8679+
8680+
8681+
8682+#define MRV_IS_IS_MAX_DY
8683+#define MRV_IS_IS_MAX_DY_MASK 0x00000FFF
8684+#define MRV_IS_IS_MAX_DY_SHIFT 0
8685+#define MRV_IS_IS_MAX_DY_MAX (MRV_IS_IS_MAX_DY_MASK >> MRV_IS_IS_MAX_DY_SHIFT)
8686+#define MRV_IS_DY
8687+#define MRV_IS_DY_MASK 0x0FFF0000
8688+#define MRV_IS_DY_SHIFT 16
8689+#define MRV_IS_DY_MAX 0x000007FF
8690+#define MRV_IS_DY_MIN (~MRV_IS_DY_MAX)
8691+#define MRV_IS_DX
8692+#define MRV_IS_DX_MASK 0x00000FFF
8693+#define MRV_IS_DX_SHIFT 0
8694+#define MRV_IS_DX_MAX 0x000007FF
8695+#define MRV_IS_DX_MIN (~MRV_IS_DX_MAX)
8696+
8697+
8698+#define MRV_IS_IS_H_OFFS_SHD
8699+#define MRV_IS_IS_H_OFFS_SHD_MASK 0x00001FFF
8700+#define MRV_IS_IS_H_OFFS_SHD_SHIFT 0
8701+
8702+
8703+#define MRV_IS_IS_V_OFFS_SHD
8704+#define MRV_IS_IS_V_OFFS_SHD_MASK 0x00000FFF
8705+#define MRV_IS_IS_V_OFFS_SHD_SHIFT 0
8706+
8707+
8708+#define MRV_IS_ISP_H_SIZE_SHD
8709+#define MRV_IS_ISP_H_SIZE_SHD_MASK 0x00001FFF
8710+#define MRV_IS_ISP_H_SIZE_SHD_SHIFT 0
8711+
8712+
8713+#define MRV_IS_ISP_V_SIZE_SHD
8714+#define MRV_IS_ISP_V_SIZE_SHD_MASK 0x00000FFF
8715+#define MRV_IS_ISP_V_SIZE_SHD_SHIFT 0
8716+
8717+
8718+#define MRV_HIST_HIST_PDIV
8719+#define MRV_HIST_HIST_PDIV_MASK 0x000007F8
8720+#define MRV_HIST_HIST_PDIV_SHIFT 3
8721+#define MRV_HIST_HIST_PDIV_MIN 0x00000003
8722+#define MRV_HIST_HIST_PDIV_MAX 0x000000FF
8723+#define MRV_HIST_HIST_MODE
8724+#define MRV_HIST_HIST_MODE_MASK 0x00000007
8725+#define MRV_HIST_HIST_MODE_SHIFT 0
8726+#define MRV_HIST_HIST_MODE_MAX 5
8727+#define MRV_HIST_HIST_MODE_LUM 5
8728+#define MRV_HIST_HIST_MODE_B 4
8729+#define MRV_HIST_HIST_MODE_G 3
8730+#define MRV_HIST_HIST_MODE_R 2
8731+#define MRV_HIST_HIST_MODE_RGB 1
8732+#define MRV_HIST_HIST_MODE_NONE 0
8733+
8734+#define MRV_HIST_HIST_H_OFFS
8735+#define MRV_HIST_HIST_H_OFFS_MASK 0x00000FFF
8736+#define MRV_HIST_HIST_H_OFFS_SHIFT 0
8737+#define MRV_HIST_HIST_H_OFFS_MAX \
8738+ (MRV_HIST_HIST_H_OFFS_MASK >> MRV_HIST_HIST_H_OFFS_SHIFT)
8739+
8740+#define MRV_HIST_HIST_V_OFFS
8741+#define MRV_HIST_HIST_V_OFFS_MASK 0x00000FFF
8742+#define MRV_HIST_HIST_V_OFFS_SHIFT 0
8743+#define MRV_HIST_HIST_V_OFFS_MAX \
8744+ (MRV_HIST_HIST_V_OFFS_MASK >> MRV_HIST_HIST_V_OFFS_SHIFT)
8745+
8746+#define MRV_HIST_HIST_H_SIZE
8747+#define MRV_HIST_HIST_H_SIZE_MASK 0x00000FFF
8748+#define MRV_HIST_HIST_H_SIZE_SHIFT 0
8749+#define MRV_HIST_HIST_H_SIZE_MAX \
8750+ (MRV_HIST_HIST_H_SIZE_MASK >> MRV_HIST_HIST_H_SIZE_SHIFT)
8751+
8752+#define MRV_HIST_HIST_V_SIZE
8753+#define MRV_HIST_HIST_V_SIZE_MASK 0x00000FFF
8754+#define MRV_HIST_HIST_V_SIZE_SHIFT 0
8755+#define MRV_HIST_HIST_V_SIZE_MAX \
8756+ (MRV_HIST_HIST_V_SIZE_MASK >> MRV_HIST_HIST_V_SIZE_SHIFT)
8757+
8758+
8759+#define MRV_HIST_HIST_BIN_N
8760+#define MRV_HIST_HIST_BIN_N_MASK 0x000000FF
8761+#define MRV_HIST_HIST_BIN_N_SHIFT 0
8762+#define MRV_HIST_HIST_BIN_N_MAX \
8763+ (MRV_HIST_HIST_BIN_N_MASK >> MRV_HIST_HIST_BIN_N_SHIFT)
8764+
8765+
8766+
8767+#define MRV_FILT_STAGE1_SELECT
8768+#define MRV_FILT_STAGE1_SELECT_MASK 0x00000F00
8769+#define MRV_FILT_STAGE1_SELECT_SHIFT 8
8770+#define MRV_FILT_STAGE1_SELECT_MAX_BLUR 0
8771+#define MRV_FILT_STAGE1_SELECT_DEFAULT 4
8772+#define MRV_FILT_STAGE1_SELECT_MIN_BLUR 7
8773+#define MRV_FILT_STAGE1_SELECT_BYPASS 8
8774+#define MRV_FILT_FILT_CHR_H_MODE
8775+#define MRV_FILT_FILT_CHR_H_MODE_MASK 0x000000C0
8776+#define MRV_FILT_FILT_CHR_H_MODE_SHIFT 6
8777+#define MRV_FILT_FILT_CHR_H_MODE_BYPASS 0
8778+#define MRV_FILT_FILT_CHR_H_MODE_STATIC 1
8779+#define MRV_FILT_FILT_CHR_H_MODE_DYN_1 2
8780+#define MRV_FILT_FILT_CHR_H_MODE_DYN_2 3
8781+#define MRV_FILT_FILT_CHR_V_MODE
8782+#define MRV_FILT_FILT_CHR_V_MODE_MASK 0x00000030
8783+#define MRV_FILT_FILT_CHR_V_MODE_SHIFT 4
8784+#define MRV_FILT_FILT_CHR_V_MODE_BYPASS 0
8785+#define MRV_FILT_FILT_CHR_V_MODE_STATIC8 1
8786+#define MRV_FILT_FILT_CHR_V_MODE_STATIC10 2
8787+#define MRV_FILT_FILT_CHR_V_MODE_STATIC12 3
8788+
8789+#define MRV_FILT_FILT_MODE
8790+#define MRV_FILT_FILT_MODE_MASK 0x00000002
8791+#define MRV_FILT_FILT_MODE_SHIFT 1
8792+#define MRV_FILT_FILT_MODE_STATIC 0
8793+#define MRV_FILT_FILT_MODE_DYNAMIC 1
8794+
8795+#define MRV_FILT_FILT_ENABLE
8796+#define MRV_FILT_FILT_ENABLE_MASK 0x00000001
8797+#define MRV_FILT_FILT_ENABLE_SHIFT 0
8798+
8799+
8800+#define MRV_FILT_FILT_THRESH_BL0
8801+#define MRV_FILT_FILT_THRESH_BL0_MASK 0x000003FF
8802+#define MRV_FILT_FILT_THRESH_BL0_SHIFT 0
8803+
8804+
8805+#define MRV_FILT_FILT_THRESH_BL1
8806+#define MRV_FILT_FILT_THRESH_BL1_MASK 0x000003FF
8807+#define MRV_FILT_FILT_THRESH_BL1_SHIFT 0
8808+
8809+
8810+#define MRV_FILT_FILT_THRESH_SH0
8811+#define MRV_FILT_FILT_THRESH_SH0_MASK 0x000003FF
8812+#define MRV_FILT_FILT_THRESH_SH0_SHIFT 0
8813+
8814+
8815+#define MRV_FILT_FILT_THRESH_SH1
8816+#define MRV_FILT_FILT_THRESH_SH1_MASK 0x000003FF
8817+#define MRV_FILT_FILT_THRESH_SH1_SHIFT 0
8818+
8819+
8820+#define MRV_FILT_LUM_WEIGHT_GAIN
8821+#define MRV_FILT_LUM_WEIGHT_GAIN_MASK 0x00070000
8822+#define MRV_FILT_LUM_WEIGHT_GAIN_SHIFT 16
8823+#define MRV_FILT_LUM_WEIGHT_KINK
8824+#define MRV_FILT_LUM_WEIGHT_KINK_MASK 0x0000FF00
8825+#define MRV_FILT_LUM_WEIGHT_KINK_SHIFT 8
8826+#define MRV_FILT_LUM_WEIGHT_MIN
8827+#define MRV_FILT_LUM_WEIGHT_MIN_MASK 0x000000FF
8828+#define MRV_FILT_LUM_WEIGHT_MIN_SHIFT 0
8829+
8830+
8831+#define MRV_FILT_FILT_FAC_SH1
8832+#define MRV_FILT_FILT_FAC_SH1_MASK 0x0000003F
8833+#define MRV_FILT_FILT_FAC_SH1_SHIFT 0
8834+
8835+
8836+#define MRV_FILT_FILT_FAC_SH0
8837+#define MRV_FILT_FILT_FAC_SH0_MASK 0x0000003F
8838+#define MRV_FILT_FILT_FAC_SH0_SHIFT 0
8839+
8840+
8841+#define MRV_FILT_FILT_FAC_MID
8842+#define MRV_FILT_FILT_FAC_MID_MASK 0x0000003F
8843+#define MRV_FILT_FILT_FAC_MID_SHIFT 0
8844+
8845+
8846+#define MRV_FILT_FILT_FAC_BL0
8847+#define MRV_FILT_FILT_FAC_BL0_MASK 0x0000003F
8848+#define MRV_FILT_FILT_FAC_BL0_SHIFT 0
8849+
8850+
8851+#define MRV_FILT_FILT_FAC_BL1
8852+#define MRV_FILT_FILT_FAC_BL1_MASK 0x0000003F
8853+#define MRV_FILT_FILT_FAC_BL1_SHIFT 0
8854+
8855+
8856+
8857+
8858+ #define MRV_AE_EXP_MEAS_MODE
8859+ #define MRV_AE_EXP_MEAS_MODE_MASK 0x80000000
8860+ #define MRV_AE_EXP_MEAS_MODE_SHIFT 31
8861+
8862+#define MRV_AE_AUTOSTOP
8863+#define MRV_AE_AUTOSTOP_MASK 0x00000002
8864+#define MRV_AE_AUTOSTOP_SHIFT 1
8865+
8866+#define MRV_AE_EXP_START
8867+#define MRV_AE_EXP_START_MASK 0x00000001
8868+#define MRV_AE_EXP_START_SHIFT 0
8869+
8870+
8871+
8872+
8873+
8874+#define MRV_AE_ISP_EXP_H_OFFSET
8875+#define MRV_AE_ISP_EXP_H_OFFSET_MASK 0x00000FFF
8876+#define MRV_AE_ISP_EXP_H_OFFSET_SHIFT 0
8877+#define MRV_AE_ISP_EXP_H_OFFSET_MIN 0x00000000
8878+#define MRV_AE_ISP_EXP_H_OFFSET_MAX 0x00000F50
8879+
8880+
8881+
8882+#define MRV_AE_ISP_EXP_V_OFFSET
8883+#define MRV_AE_ISP_EXP_V_OFFSET_MASK 0x00000FFF
8884+#define MRV_AE_ISP_EXP_V_OFFSET_SHIFT 0
8885+#define MRV_AE_ISP_EXP_V_OFFSET_MIN 0x00000000
8886+#define MRV_AE_ISP_EXP_V_OFFSET_MAX 0x00000B74
8887+
8888+
8889+#define MRV_AE_ISP_EXP_H_SIZE
8890+#define MRV_AE_ISP_EXP_H_SIZE_MASK 0x000003FF
8891+#define MRV_AE_ISP_EXP_H_SIZE_SHIFT 0
8892+#define MRV_AE_ISP_EXP_H_SIZE_MIN 0x00000023
8893+#define MRV_AE_ISP_EXP_H_SIZE_MAX 0x00000333
8894+
8895+
8896+#define MRV_AE_ISP_EXP_V_SIZE
8897+#define MRV_AE_ISP_EXP_V_SIZE_MASK 0x000003FE
8898+#define MRV_AE_ISP_EXP_V_SIZE_SHIFT 0
8899+#define MRV_AE_ISP_EXP_V_SIZE_VALID_MASK \
8900+ (MRV_AE_ISP_EXP_V_SIZE_MASK & ~0x00000001)
8901+#define MRV_AE_ISP_EXP_V_SIZE_MIN 0x0000001C
8902+#define MRV_AE_ISP_EXP_V_SIZE_MAX 0x00000266
8903+
8904+#define MRV_AE_ISP_EXP_MEAN_ARR_SIZE1 5
8905+#define MRV_AE_ISP_EXP_MEAN_ARR_SIZE2 5
8906+#define MRV_AE_ISP_EXP_MEAN_ARR_OFS1 1
8907+#define MRV_AE_ISP_EXP_MEAN_ARR_OFS2 MRV_AE_ISP_EXP_MEAN_ARR_SIZE1
8908+#define MRV_AE_ISP_EXP_MEAN
8909+#define MRV_AE_ISP_EXP_MEAN_MASK 0x000000FF
8910+#define MRV_AE_ISP_EXP_MEAN_SHIFT 0
8911+
8912+
8913+#define MRV_AE_ISP_EXP_MEAN_00
8914+#define MRV_AE_ISP_EXP_MEAN_00_MASK 0x000000FF
8915+#define MRV_AE_ISP_EXP_MEAN_00_SHIFT 0
8916+
8917+#define MRV_AE_ISP_EXP_MEAN_10
8918+#define MRV_AE_ISP_EXP_MEAN_10_MASK 0x000000FF
8919+#define MRV_AE_ISP_EXP_MEAN_10_SHIFT 0
8920+
8921+
8922+#define MRV_AE_ISP_EXP_MEAN_20
8923+#define MRV_AE_ISP_EXP_MEAN_20_MASK 0x000000FF
8924+#define MRV_AE_ISP_EXP_MEAN_20_SHIFT 0
8925+
8926+
8927+#define MRV_AE_ISP_EXP_MEAN_30
8928+#define MRV_AE_ISP_EXP_MEAN_30_MASK 0x000000FF
8929+#define MRV_AE_ISP_EXP_MEAN_30_SHIFT 0
8930+
8931+
8932+#define MRV_AE_ISP_EXP_MEAN_40
8933+#define MRV_AE_ISP_EXP_MEAN_40_MASK 0x000000FF
8934+#define MRV_AE_ISP_EXP_MEAN_40_SHIFT 0
8935+
8936+
8937+#define MRV_AE_ISP_EXP_MEAN_01
8938+#define MRV_AE_ISP_EXP_MEAN_01_MASK 0x000000FF
8939+#define MRV_AE_ISP_EXP_MEAN_01_SHIFT 0
8940+
8941+
8942+#define MRV_AE_ISP_EXP_MEAN_11
8943+#define MRV_AE_ISP_EXP_MEAN_11_MASK 0x000000FF
8944+#define MRV_AE_ISP_EXP_MEAN_11_SHIFT 0
8945+
8946+
8947+#define MRV_AE_ISP_EXP_MEAN_21
8948+#define MRV_AE_ISP_EXP_MEAN_21_MASK 0x000000FF
8949+#define MRV_AE_ISP_EXP_MEAN_21_SHIFT 0
8950+
8951+
8952+#define MRV_AE_ISP_EXP_MEAN_31
8953+#define MRV_AE_ISP_EXP_MEAN_31_MASK 0x000000FF
8954+#define MRV_AE_ISP_EXP_MEAN_31_SHIFT 0
8955+
8956+
8957+#define MRV_AE_ISP_EXP_MEAN_41
8958+#define MRV_AE_ISP_EXP_MEAN_41_MASK 0x000000FF
8959+#define MRV_AE_ISP_EXP_MEAN_41_SHIFT 0
8960+
8961+
8962+#define MRV_AE_ISP_EXP_MEAN_02
8963+#define MRV_AE_ISP_EXP_MEAN_02_MASK 0x000000FF
8964+#define MRV_AE_ISP_EXP_MEAN_02_SHIFT 0
8965+
8966+
8967+
8968+#define MRV_AE_ISP_EXP_MEAN_12
8969+#define MRV_AE_ISP_EXP_MEAN_12_MASK 0x000000FF
8970+#define MRV_AE_ISP_EXP_MEAN_12_SHIFT 0
8971+
8972+
8973+#define MRV_AE_ISP_EXP_MEAN_22
8974+#define MRV_AE_ISP_EXP_MEAN_22_MASK 0x000000FF
8975+#define MRV_AE_ISP_EXP_MEAN_22_SHIFT 0
8976+
8977+
8978+#define MRV_AE_ISP_EXP_MEAN_32
8979+#define MRV_AE_ISP_EXP_MEAN_32_MASK 0x000000FF
8980+#define MRV_AE_ISP_EXP_MEAN_32_SHIFT 0
8981+
8982+
8983+#define MRV_AE_ISP_EXP_MEAN_42
8984+#define MRV_AE_ISP_EXP_MEAN_42_MASK 0x000000FF
8985+#define MRV_AE_ISP_EXP_MEAN_42_SHIFT 0
8986+
8987+
8988+#define MRV_AE_ISP_EXP_MEAN_03
8989+#define MRV_AE_ISP_EXP_MEAN_03_MASK 0x000000FF
8990+#define MRV_AE_ISP_EXP_MEAN_03_SHIFT 0
8991+
8992+
8993+#define MRV_AE_ISP_EXP_MEAN_13
8994+#define MRV_AE_ISP_EXP_MEAN_13_MASK 0x000000FF
8995+#define MRV_AE_ISP_EXP_MEAN_13_SHIFT 0
8996+
8997+
8998+#define MRV_AE_ISP_EXP_MEAN_23
8999+#define MRV_AE_ISP_EXP_MEAN_23_MASK 0x000000FF
9000+#define MRV_AE_ISP_EXP_MEAN_23_SHIFT 0
9001+
9002+
9003+#define MRV_AE_ISP_EXP_MEAN_33
9004+#define MRV_AE_ISP_EXP_MEAN_33_MASK 0x000000FF
9005+#define MRV_AE_ISP_EXP_MEAN_33_SHIFT 0
9006+
9007+
9008+#define MRV_AE_ISP_EXP_MEAN_43
9009+#define MRV_AE_ISP_EXP_MEAN_43_MASK 0x000000FF
9010+#define MRV_AE_ISP_EXP_MEAN_43_SHIFT 0
9011+
9012+
9013+#define MRV_AE_ISP_EXP_MEAN_04
9014+#define MRV_AE_ISP_EXP_MEAN_04_MASK 0x000000FF
9015+#define MRV_AE_ISP_EXP_MEAN_04_SHIFT 0
9016+
9017+
9018+#define MRV_AE_ISP_EXP_MEAN_14
9019+#define MRV_AE_ISP_EXP_MEAN_14_MASK 0x000000FF
9020+#define MRV_AE_ISP_EXP_MEAN_14_SHIFT 0
9021+
9022+
9023+#define MRV_AE_ISP_EXP_MEAN_24
9024+#define MRV_AE_ISP_EXP_MEAN_24_MASK 0x000000FF
9025+#define MRV_AE_ISP_EXP_MEAN_24_SHIFT 0
9026+
9027+
9028+#define MRV_AE_ISP_EXP_MEAN_34
9029+#define MRV_AE_ISP_EXP_MEAN_34_MASK 0x000000FF
9030+#define MRV_AE_ISP_EXP_MEAN_34_SHIFT 0
9031+
9032+
9033+#define MRV_AE_ISP_EXP_MEAN_44
9034+#define MRV_AE_ISP_EXP_MEAN_44_MASK 0x000000FF
9035+#define MRV_AE_ISP_EXP_MEAN_44_SHIFT 0
9036+
9037+
9038+
9039+#define MRV_BLS_WINDOW_ENABLE
9040+#define MRV_BLS_WINDOW_ENABLE_MASK 0x0000000C
9041+#define MRV_BLS_WINDOW_ENABLE_SHIFT 2
9042+#define MRV_BLS_WINDOW_ENABLE_NONE 0
9043+#define MRV_BLS_WINDOW_ENABLE_WND1 1
9044+#define MRV_BLS_WINDOW_ENABLE_WND2 2
9045+#define MRV_BLS_WINDOW_ENABLE_BOTH 3
9046+
9047+#define MRV_BLS_BLS_MODE
9048+#define MRV_BLS_BLS_MODE_MASK 0x00000002
9049+#define MRV_BLS_BLS_MODE_SHIFT 1
9050+#define MRV_BLS_BLS_MODE_MEAS 1
9051+#define MRV_BLS_BLS_MODE_FIX 0
9052+
9053+#define MRV_BLS_BLS_ENABLE
9054+#define MRV_BLS_BLS_ENABLE_MASK 0x00000001
9055+#define MRV_BLS_BLS_ENABLE_SHIFT 0
9056+
9057+
9058+#define MRV_BLS_BLS_SAMPLES
9059+#define MRV_BLS_BLS_SAMPLES_MASK 0x0000001F
9060+#define MRV_BLS_BLS_SAMPLES_SHIFT 0
9061+
9062+#define MRV_BLS_BLS_SAMPLES_MAX (0x00000014)
9063+
9064+
9065+#define MRV_BLS_BLS_H1_START
9066+#define MRV_BLS_BLS_H1_START_MASK 0x00000FFF
9067+#define MRV_BLS_BLS_H1_START_SHIFT 0
9068+#define MRV_BLS_BLS_H1_START_MAX \
9069+ (MRV_BLS_BLS_H1_START_MASK >> MRV_BLS_BLS_H1_START_SHIFT)
9070+
9071+
9072+#define MRV_BLS_BLS_H1_STOP
9073+#define MRV_BLS_BLS_H1_STOP_MASK 0x00001FFF
9074+#define MRV_BLS_BLS_H1_STOP_SHIFT 0
9075+#define MRV_BLS_BLS_H1_STOP_MAX \
9076+ (MRV_BLS_BLS_H1_STOP_MASK >> MRV_BLS_BLS_H1_STOP_SHIFT)
9077+
9078+
9079+#define MRV_BLS_BLS_V1_START
9080+#define MRV_BLS_BLS_V1_START_MASK 0x00001FFF
9081+#define MRV_BLS_BLS_V1_START_SHIFT 0
9082+#define MRV_BLS_BLS_V1_START_MAX \
9083+ (MRV_BLS_BLS_V1_START_MASK >> MRV_BLS_BLS_V1_START_SHIFT)
9084+
9085+#define MRV_BLS_BLS_V1_STOP
9086+#define MRV_BLS_BLS_V1_STOP_MASK 0x00001FFF
9087+#define MRV_BLS_BLS_V1_STOP_SHIFT 0
9088+#define MRV_BLS_BLS_V1_STOP_MAX \
9089+ (MRV_BLS_BLS_V1_STOP_MASK >> MRV_BLS_BLS_V1_STOP_SHIFT)
9090+
9091+#define MRV_BLS_BLS_H2_START
9092+#define MRV_BLS_BLS_H2_START_MASK 0x00001FFF
9093+#define MRV_BLS_BLS_H2_START_SHIFT 0
9094+#define MRV_BLS_BLS_H2_START_MAX \
9095+ (MRV_BLS_BLS_H2_START_MASK >> MRV_BLS_BLS_H2_START_SHIFT)
9096+
9097+
9098+#define MRV_BLS_BLS_H2_STOP
9099+#define MRV_BLS_BLS_H2_STOP_MASK 0x00001FFF
9100+#define MRV_BLS_BLS_H2_STOP_SHIFT 0
9101+#define MRV_BLS_BLS_H2_STOP_MAX \
9102+ (MRV_BLS_BLS_H2_STOP_MASK >> MRV_BLS_BLS_H2_STOP_SHIFT)
9103+
9104+
9105+#define MRV_BLS_BLS_V2_START
9106+#define MRV_BLS_BLS_V2_START_MASK 0x00001FFF
9107+#define MRV_BLS_BLS_V2_START_SHIFT 0
9108+#define MRV_BLS_BLS_V2_START_MAX \
9109+ (MRV_BLS_BLS_V2_START_MASK >> MRV_BLS_BLS_V2_START_SHIFT)
9110+
9111+
9112+#define MRV_BLS_BLS_V2_STOP
9113+#define MRV_BLS_BLS_V2_STOP_MASK 0x00001FFF
9114+#define MRV_BLS_BLS_V2_STOP_SHIFT 0
9115+#define MRV_BLS_BLS_V2_STOP_MAX \
9116+ (MRV_BLS_BLS_V2_STOP_MASK >> MRV_BLS_BLS_V2_STOP_SHIFT)
9117+
9118+#define MRV_ISP_BLS_FIX_SUB_MIN (0xFFFFF001)
9119+#define MRV_ISP_BLS_FIX_SUB_MAX (0x00000FFF)
9120+#define MRV_ISP_BLS_FIX_MASK (0x00001FFF)
9121+#define MRV_ISP_BLS_FIX_SHIFT_A (0)
9122+#define MRV_ISP_BLS_FIX_SHIFT_B (0)
9123+#define MRV_ISP_BLS_FIX_SHIFT_C (0)
9124+#define MRV_ISP_BLS_FIX_SHIFT_D (0)
9125+#define MRV_ISP_BLS_MEAN_MASK (0x00000FFF)
9126+#define MRV_ISP_BLS_MEAN_SHIFT_A (0)
9127+#define MRV_ISP_BLS_MEAN_SHIFT_B (0)
9128+#define MRV_ISP_BLS_MEAN_SHIFT_C (0)
9129+#define MRV_ISP_BLS_MEAN_SHIFT_D (0)
9130+
9131+#define MRV_BLS_BLS_A_FIXED
9132+#define MRV_BLS_BLS_A_FIXED_MASK (MRV_ISP_BLS_FIX_MASK <<\
9133+ MRV_ISP_BLS_FIX_SHIFT_A)
9134+#define MRV_BLS_BLS_A_FIXED_SHIFT MRV_ISP_BLS_FIX_SHIFT_A
9135+
9136+#define MRV_BLS_BLS_B_FIXED
9137+#define MRV_BLS_BLS_B_FIXED_MASK (MRV_ISP_BLS_FIX_MASK <<\
9138+ MRV_ISP_BLS_FIX_SHIFT_B)
9139+#define MRV_BLS_BLS_B_FIXED_SHIFT MRV_ISP_BLS_FIX_SHIFT_B
9140+
9141+#define MRV_BLS_BLS_C_FIXED
9142+#define MRV_BLS_BLS_C_FIXED_MASK (MRV_ISP_BLS_FIX_MASK <<\
9143+ MRV_ISP_BLS_FIX_SHIFT_C)
9144+#define MRV_BLS_BLS_C_FIXED_SHIFT MRV_ISP_BLS_FIX_SHIFT_C
9145+
9146+#define MRV_BLS_BLS_D_FIXED
9147+#define MRV_BLS_BLS_D_FIXED_MASK (MRV_ISP_BLS_FIX_MASK <<\
9148+ MRV_ISP_BLS_FIX_SHIFT_D)
9149+#define MRV_BLS_BLS_D_FIXED_SHIFT MRV_ISP_BLS_FIX_SHIFT_D
9150+
9151+
9152+#define MRV_BLS_BLS_A_MEASURED
9153+#define MRV_BLS_BLS_A_MEASURED_MASK (MRV_ISP_BLS_MEAN_MASK <<\
9154+ MRV_ISP_BLS_MEAN_SHIFT_A)
9155+#define MRV_BLS_BLS_A_MEASURED_SHIFT MRV_ISP_BLS_MEAN_SHIFT_A
9156+
9157+
9158+#define MRV_BLS_BLS_B_MEASURED
9159+#define MRV_BLS_BLS_B_MEASURED_MASK (MRV_ISP_BLS_MEAN_MASK <<\
9160+ MRV_ISP_BLS_MEAN_SHIFT_B)
9161+#define MRV_BLS_BLS_B_MEASURED_SHIFT MRV_ISP_BLS_MEAN_SHIFT_B
9162+
9163+
9164+#define MRV_BLS_BLS_C_MEASURED
9165+#define MRV_BLS_BLS_C_MEASURED_MASK (MRV_ISP_BLS_MEAN_MASK <<\
9166+ MRV_ISP_BLS_MEAN_SHIFT_C)
9167+#define MRV_BLS_BLS_C_MEASURED_SHIFT MRV_ISP_BLS_MEAN_SHIFT_C
9168+
9169+
9170+#define MRV_BLS_BLS_D_MEASURED
9171+#define MRV_BLS_BLS_D_MEASURED_MASK (MRV_ISP_BLS_MEAN_MASK <<\
9172+ MRV_ISP_BLS_MEAN_SHIFT_D)
9173+#define MRV_BLS_BLS_D_MEASURED_SHIFT MRV_ISP_BLS_MEAN_SHIFT_D
9174+
9175+#define CI_ISP_DELAY_AFTER_RESET 15
9176+
9177+#define IRQ_ISP_ERROR -1
9178+#define IRQ_JPE_ERROR 0
9179+#define IRQ_JPE_SUCCESS 1
9180+#define IRQ_MI_SUCCESS 2
9181+#define IRQ_MI_SP_SUCCESS 3
9182+#define IRQ 1
9183+
9184+#endif
9185--- /dev/null
9186+++ b/drivers/media/video/mrstci/mrstisp/include/mrstisp_stdinc.h
9187@@ -0,0 +1,119 @@
9188+/*
9189+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
9190+ *
9191+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
9192+ *
9193+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
9194+ *
9195+ * This program is free software; you can redistribute it and/or
9196+ * modify it under the terms of the GNU General Public License version
9197+ * 2 as published by the Free Software Foundation.
9198+ *
9199+ * This program is distributed in the hope that it will be useful,
9200+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9201+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9202+ * GNU General Public License for more details.
9203+ *
9204+ * You should have received a copy of the GNU General Public License
9205+ * along with this program; if not, write to the Free Software
9206+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
9207+ * 02110-1301, USA.
9208+ *
9209+ *
9210+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
9211+ */
9212+
9213+#ifndef _MRSTISP_STDINC_H
9214+#define _MRSTISP_STDINC_H
9215+
9216+#ifdef __KERNEL__
9217+#include <linux/module.h>
9218+#include <linux/version.h>
9219+#include <linux/moduleparam.h>
9220+#include <linux/init.h>
9221+#include <linux/fs.h>
9222+
9223+#include <linux/proc_fs.h>
9224+#include <linux/ctype.h>
9225+#include <linux/pagemap.h>
9226+#include <linux/delay.h>
9227+#include <linux/io.h>
9228+
9229+#include <linux/uaccess.h>
9230+#include <linux/videodev2.h>
9231+#include <media/v4l2-common.h>
9232+#include <media/v4l2-ioctl.h>
9233+
9234+#include <linux/mutex.h>
9235+#include <linux/list.h>
9236+#include <linux/string.h>
9237+#include <linux/slab.h>
9238+#include <linux/vmalloc.h>
9239+#include <linux/types.h>
9240+#include <linux/errno.h>
9241+#include <linux/sched.h>
9242+#include <linux/moduleparam.h>
9243+#include <linux/smp_lock.h>
9244+#include <asm/kmap_types.h>
9245+#include <linux/delay.h>
9246+#include <linux/pci.h>
9247+#include <linux/interrupt.h>
9248+#include <linux/timer.h>
9249+#include <asm/system.h>
9250+#include <asm/page.h>
9251+#include <asm/pgtable.h>
9252+#include <linux/time.h>
9253+#include <linux/syscalls.h>
9254+
9255+#include <linux/i2c.h>
9256+#include <linux/gpio.h>
9257+#include <linux/dma-mapping.h>
9258+#include <media/videobuf-core.h>
9259+#include <media/videobuf-dma-contig.h>
9260+/* #include <media/v4l2-i2c-drv.h> */
9261+
9262+#ifdef CONFIG_KMOD
9263+#include <linux/kmod.h>
9264+#endif
9265+
9266+#include "project_settings_mrv.h"
9267+
9268+#include "ci_sensor_common.h"
9269+#include "ci_isp_common.h"
9270+#include "ci_va.h"
9271+#include "v4l2_jpg_review.h"
9272+
9273+#include "def.h"
9274+#include "mrstisp_reg.h"
9275+#include "mrstisp.h"
9276+#include "mrstisp_isp.h"
9277+#include "mrstisp_hw.h"
9278+#include "mrstisp_jpe.h"
9279+#include "mrstisp_dp.h"
9280+/* #include "mrstisp_mif.h" */
9281+
9282+extern unsigned char *mrst_isp_regs;
9283+#define MEM_CSC_REG_BASE (0x08500000)
9284+#define MEM_MRV_REG_BASE (mrst_isp_regs)
9285+#define ALIGN_TO_4(f) (((f) + 3) & ~3)
9286+
9287+/* for debug */
9288+extern int mrstisp_debug;
9289+#define dprintk(level, fmt, arg...) do { \
9290+ if (mrstisp_debug >= level) \
9291+ printk(KERN_DEBUG "mrstisp@%s: " fmt "\n", \
9292+ __func__, ## arg); } \
9293+ while (0)
9294+
9295+#define eprintk(fmt, arg...) \
9296+ printk(KERN_ERR "mrstisp@%s" fmt "\n", \
9297+ __func__, ## arg);
9298+
9299+#define DBG_entering dprintk(1, "entering");
9300+#define DBG_leaving dprintk(1, "leaving");
9301+#define DBG_line dprintk(1, " line: %d", __LINE__);
9302+
9303+#include "reg_access.h"
9304+
9305+#endif
9306+#endif
9307--- /dev/null
9308+++ b/drivers/media/video/mrstci/mrstisp/include/project_settings_mrv.h
9309@@ -0,0 +1,622 @@
9310+/*
9311+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
9312+ *
9313+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
9314+ *
9315+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
9316+ *
9317+ * This program is free software; you can redistribute it and/or
9318+ * modify it under the terms of the GNU General Public License version
9319+ * 2 as published by the Free Software Foundation.
9320+ *
9321+ * This program is distributed in the hope that it will be useful,
9322+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9323+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9324+ * GNU General Public License for more details.
9325+ *
9326+ * You should have received a copy of the GNU General Public License
9327+ * along with this program; if not, write to the Free Software
9328+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
9329+ * 02110-1301, USA.
9330+ *
9331+ *
9332+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
9333+ */
9334+
9335+
9336+#ifndef _PROJECT_SETTTINGS_MRV_H
9337+#define _PROJECT_SETTTINGS_MRV_H
9338+
9339+/* !< information mask */
9340+#define DBG_INFO 0x00000001
9341+/* !< warning mask */
9342+#define DBG_WARN 0x00000002
9343+/* !< error mask */
9344+#define DBG_ERR 0x00000004
9345+/* !< assert mask */
9346+#define DBG_ASSERT 0x00000008
9347+/* !< mask to get all categories */
9348+#define DBG_CAT_ALL 0x000000FF
9349+
9350+/* !< currly used category mask */
9351+#define DBG_CAT_FILTER (DBG_CAT_ALL)
9352+
9353+/* !< application mask */
9354+#define DBG_APP 0x00002000
9355+/* !< MARVIN driver mask */
9356+#define DBG_MRV 0x00001000
9357+/* !< mipi driver mask */
9358+#define DBG_MIPI 0x00040000
9359+
9360+#define CAMERA_VB6850 11
9361+#define CAMERA_HW CAMERA_VB6850
9362+/*
9363+ * \name MARVIN_HW
9364+ * select which MARVIN hardware is used.
9365+ */
9366+
9367+/* MARVIN 3, basically MARVIN 1 with more resolution */
9368+#define MARVIN_3 2
9369+/* Codename: "ISP upgrade" */
9370+#define MARVIN_3_V2 3
9371+/* MARVIN_3_V2 upgrade */
9372+#define MARVIN_3_V22 11
9373+/* MARVIN_3_V2 upgrade + MI patch from 12/2006 */
9374+#define MARVIN_3_V22X 13
9375+/* MARVIN_3_V2 upgrade + MI patch from 12/2006 (package tag 15.01.07) */
9376+#define MARVIN_3_V22X2 15
9377+/* just a quick-made test version for AF, other features see below */
9378+#define MARVIN_3_V2B 5
9379+/* Codename: "M3plus" */
9380+#define MARVIN_3_V3 4
9381+/* Codename: "Autofocus/bad pixel" */
9382+#define MARVIN_3_V4 6
9383+/* MARVIN_3_V4 upgrade */
9384+#define MARVIN_3_V42 12
9385+/* MARVIN_3_V4 upgrade + MI patch from 12/2006 */
9386+#define MARVIN_3_V42X 14
9387+/* MARVIN_3_V4 upgrade + MI patch from 12/2006 + (package tag 15.01.07) */
9388+#define MARVIN_3_V42X2 16
9389+/* Codename: "EMP" */
9390+#define MARVIN_3_V5 7
9391+/* successor of MARVIN_3_V5 */
9392+#define MARVIN_5_V5 18
9393+
9394+/*
9395+ * FPGA Bitstream ID 12 (Marvin5 tag 27.02.06), used for USA roadshow in
9396+ * 03/2006
9397+ */
9398+#define MARVIN_5_BS12 10
9399+/* MARVIN 5 (product) */
9400+#define MARVIN_5_V1 9
9401+/* MARVIN 5 (product with new isp filter) */
9402+#define MARVIN_5_V2 20
9403+/* MARVIN 5 (product with Chromatic Aberration) */
9404+#define MARVIN_5_V3 21
9405+/* MARVIN 5 (with 16 beat burst) */
9406+#define MARVIN_5_V4 22
9407+/* MARVIN XF */
9408+#define MARVIN_5_XF 17
9409+/* MARVIN XF */
9410+#define MARVIN_5_XF_TMP 19
9411+
9412+/* MARVIN 12MP */
9413+#define MARVIN_12_V1 23
9414+
9415+/* MARVIN 5 (with 16 beat burst) */
9416+#define MARVIN_5_V4_R20 30
9417+
9418+
9419+/* Currently used MARVIN version */
9420+#define MARVIN_HW MARVIN_5_V4_R20
9421+
9422+/*
9423+ * MRV_SUPPORT_xxx
9424+ * Some compile-time-configurable features of the MARVIN driver.
9425+ * Set the certain defines to a non-zero value to enable the feature
9426+ */
9427+
9428+/*
9429+ * routines to convert state and configuration enums into human readable
9430+ * text. (useful in e.g. debug outputs)
9431+ */
9432+#define MRV_SUPPORT_STATE2STRING 1
9433+
9434+/*
9435+ * routines to read, write and dump the register set of the MARVIN module
9436+ */
9437+#define MRV_SUPPORT_REGDUMP 1
9438+
9439+/*
9440+ * second level support routines for e.g. exposure control, auto focus
9441+ * and white balance. Second level support routines are
9442+ * those using the plain routines of mrv.h to implement a kind of
9443+ * "helper" to program/access/use the MARVIN with a bit more
9444+ * abstraction.
9445+ */
9446+#define MRV_SUPPORT_SL 1
9447+
9448+/*
9449+ * \mainpage MARVIN SOFTWARE
9450+ * \b File: project_settings_mrv.h
9451+ *
9452+ * <!-- \section Global Descriptions and Informations
9453+ * (settings, definitions, software changes) -->
9454+ *
9455+ * For global descriptions and informations see under "Modules"
9456+ *
9457+ */
9458+
9459+/*
9460+ * \addtogroup MARVIN_DEFINES_00 MARVIN Features
9461+ * \b File: project_settings_mrv.h
9462+ *
9463+ * \par MARVIN Features
9464+ * Depends on the used MARVIN_HW. Direct usage of MARVIN_HW should be
9465+ * avoided wherever possible.
9466+ * This makes it VERY MUCH easier to adapt the driver to new MARVIN
9467+ * versions with a feature set suited to a certain customer.
9468+ *
9469+ * \par MARVIN_FEATURE_CHIP_ID (integer)
9470+ * ID value contained in the chip. This is to be able to identify
9471+ * the chip derivative during runtime of the software
9472+ *
9473+ * \par MARVIN_FEATURE_CAMBUSWIDTH: (integer)
9474+ * How many bits can be captured from the image sensor?
9475+ * MARVIN_FEATURE_8BITS = sensor bus width is 8 bits
9476+ * MARVIN_FEATURE_10BITS = sensor bus width is 10 bits
9477+ * MARVIN_FEATURE_12BITS = sensor bus width is 12 bits
9478+ *
9479+ * \par MARVIN_FEATURE_XTALK: (integer)
9480+ * separate crosstalk matrix. without this feature, the crosstalk
9481+ * coefficients have to be combined with the color conversion matrix
9482+ * MARVIN_FEATURE_XTALK_9BITS = coefficient range -2.0 ... +1.992 ( 9 Bit)
9483+ * MARVIN_FEATURE_XTALK_10BITS = coefficient range -4.0 ... +3.992 (10 Bit)
9484+ * MARVIN_FEATURE_XTALK_11BITS = coefficient range -8.0 ... +7.992 (11 Bit)
9485+ * MARVIN_FEATURE_EXIST_NOT = no separate xtalk matrix
9486+ *
9487+ * \par MARVIN_FEATURE_XTALK_OFFSET: (boolean)
9488+ * add a offset to the crosstalk matrix output
9489+ *
9490+ * \par MARVIN_FEATURE_GAMMAOUT: (boolean)
9491+ * gamma correction for luminance channel at the output of the
9492+ * ISP block.
9493+ *
9494+ * \par MARVIN_FEATURE_FRAMESIZE: (integer)
9495+ * Maximum frame size (at sensor input) MARVIN can handle.
9496+ * MARVIN_FEATURE_1M9 = 1.9 megapixels
9497+ * MARVIN_FEATURE_3M1 = 3.1 megapixels
9498+ * MARVIN_FEATURE_5M3 = 5.3 megapixels
9499+ *
9500+ * \par MARVIN_FEATURE_SSCALE: (boolean)
9501+ * Selfpath feature, and therefore selfpath scaler feautel also. If set to
9502+ * MARVIN_FEATURE_EXIST_NOT, the whole self data path is not present.
9503+ *
9504+ * \par MARVIN_FEATURE_SSCALE_UP: (boolean)
9505+ * Upscale capability of the self path scaler. This feature enables
9506+ * the scaler to do upscaling up to the factor of 5
9507+ *
9508+ * \par MARVIN_FEATURE_SSCALE_FACTORCALC: (integer)
9509+ * Specifies the strategy to calculate the scale factors for the self scaler.
9510+ * Note that this define is the successor of the MARVIN_FEATURE_SSCALE_LANES,
9511+ * which does not longer reflect the 'true' implementations of the scaler
9512+ * hardware and therefore has been removed.
9513+ * MARVIN_FEATURE_SCALEFACTOR_COMBINED_UV = 'traditional' behaviour: The
9514+ * scaler handles the U and V chroma components as if they were two joined
9515+ * pixels. Thus, when YUV422 subsampled input data is to be processed and
9516+ * no further subsampling is required, the scale facrors of luma and chroma
9517+ * pathes must be identical.
9518+ * MARVIN_FEATURE_SCALEFACTOR_SEPARATED_UV = 'new style' behaviour: The
9519+ * scaler handles the U and V chroma components as if they belong to
9520+ * totally different picture planes. Thus, when YUV422 subsampled input
9521+ * data is to be processed and no further subsampling is required, the
9522+ * scale facrors of the chroma path must be calculated like those of the
9523+ * luma path, but with only half of the image width.
9524+ *
9525+ * \par MARVIN_FEATURE_MSCALE_UP: (boolean)
9526+ * Upscale capability of the main path scaler. This feature enables
9527+ * the scaler to do upscaling up to the factor of 5
9528+ *
9529+ * \par MARVIN_FEATURE_MSCALE_FACTORCALC: (integer)
9530+ * Specifies the strategy to calculate the scale factors for the main scaler.
9531+ * MARVIN_FEATURE_SCALEFACTOR_COMBINED_UV = 'traditional' behaviour: The
9532+ * scaler handles the U and V chroma components as if they were two joined
9533+ * pixels. Thus, when YUV422 subsampled input data is to be processed and
9534+ * no further subsampling is required, the scale facrors of luma and chroma
9535+ * pathes must be identical.
9536+ * MARVIN_FEATURE_SCALEFACTOR_SEPARATED_UV = 'new style' behaviour: The
9537+ * scaler handles the U and V chroma components as if they belong to
9538+ * totally different picture planes. Thus, when YUV422 subsampled input
9539+ * data is to be processed and no further subsampling is required, the
9540+ * scale facrors of the chroma path must be calculated like those of the
9541+ * luma path, but with only half of the image width.
9542+ *
9543+ * \par MARVIN_FEATURE_SCALE_FACTORWIDTH: (integer)
9544+ * Width of the scalefactors for both main and self scaler
9545+ * MARVIN_FEATURE_12BITS = 12 bits precision
9546+ * MARVIN_FEATURE_14BITS = 14 bits precision
9547+ * MARVIN_FEATURE_16BITS = 16 bits precision
9548+ *
9549+ * \par MARVIN_FEATURE_AF_MEASURE: (boolean)
9550+ * Autofocus measurement block (attached to the demosaicing block)
9551+ *
9552+ * \par MARVIN_FEATURE_BAD_PIXEL: (boolean)
9553+ * Bad pixel detection/correction block
9554+ *
9555+ * \par MARVIN_FEATURE_BAD_PIXEL_WIDTH: (integer)
9556+ * Bad pixel detection/correction block register size
9557+ * MARVIN_FEATURE_10BITS = 10 bits precision
9558+ * MARVIN_FEATURE_12BITS = 12 bits precision
9559+ * MARVIN_FEATURE_EXIST_NOT = no bad pixel detection/correction block
9560+ *
9561+ * \par MARVIN_FEATURE_BAD_PIXEL_RAM: (integer)
9562+ * Bad pixel table ram address size
9563+ * MARVIN_FEATURE_7BITS = 128 entries
9564+ * MARVIN_FEATURE_11BITS = 2048 entries
9565+ * MARVIN_FEATURE_EXIST_NOT = no bad pixel ram block
9566+ *
9567+ * \par MARVIN_FEATURE_SUPERIMPOSE: (boolean)
9568+ * Superimpose block, used to combine camera picture with a static
9569+ * one coming from the system memory (chroma keying)
9570+ *
9571+ * \par MARVIN_FEATURE_CHROM_ABERRATION: (boolean)
9572+ * Chromatic aberration block corrects color fringing
9573+ *
9574+ * \par MARVIN_FEATURE_IMAGE_EFFECTS: (boolean)
9575+ * Image effects block, various modes like grayscale, sepia, emboss
9576+ * sketch, etc.
9577+ *
9578+ * \par MARVIN_FEATURE_LENS_SHADING: (boolean)
9579+ * Lens shading compensation block
9580+ *
9581+ * \par MARVIN_FEATURE_ISP_ERRORFLAGS: (boolean)
9582+ * Some registers containing more detailed error flags of the ISP.
9583+ * These may help during system integration.
9584+ *
9585+ * \par MARVIN_FEATURE_FRAMECOUNTER: (boolean)
9586+ * Frame counter register
9587+ *
9588+ * \par MARVIN_FEATURE_FLASH_LIGHT: (boolean)
9589+ * Support for frame-synchronized triggering of a LED or xenon based
9590+ * flashlight
9591+ *
9592+ * \par MARVIN_FEATURE_SHUTTER: (boolean)
9593+ * Support for driving an external mechanical shutter
9594+ *
9595+ * \par MARVIN_FEATURE_IMG_STABILIZATION: (integer)
9596+ * Support for digital image stabilization (=compensation against
9597+ * small movements)
9598+ * MARVIN_FEATURE_IMG_STABILIZATION_V1 = represents second output formatter
9599+ * at ISP output, no image
9600+ * stabilization functionality, located
9601+ * in the ISP bayer path only.
9602+ * MARVIN_FEATURE_IMG_STABILIZATION_V2 = represents image stabilization
9603+ * including output formatter, located
9604+ * in both bayer and YCbCr paths, but
9605+ * not in the raw data path.
9606+ * MARVIN_FEATURE_EXIST_NOT = there is no output image stabilization
9607+ *
9608+ * \par MARVIN_FEATURE_ISP_HISTOGRAM: (boolean)
9609+ * Histogram measurement block
9610+ *
9611+ * \par MARVIN_FEATURE_ISP_FILTER: (boolean)
9612+ * Additional burring/sharpness filer
9613+ *
9614+ * \par MARVIN_FEATURE_SMIA: (integer)
9615+ * SMIA camera protocol version switch
9616+ * MARVIN_FEATURE_SMIA_MIPI_EMP = EMP version that contains just the the
9617+ * SMIA and MIPI application protocol
9618+ * with two embedded data areas
9619+ * MARVIN_FEATURE_SMIA_EM = EMP version that contains just the the SMIA
9620+ * application protocol
9621+ * MARVIN_FEATURE_SMIA_COMPLETE= SMIA module that contains the complete SMIA
9622+ * functionality.
9623+ * MARVIN_FEATURE_EXIST_NOT = there is no SMIA module
9624+ *
9625+ * \par MARVIN_FEATURE_AUTO_EXPOSURE: (integer)
9626+ * measurement unit for automatic exposure control
9627+ * MARVIN_FEATURE_AUTO_EXPOSURE_V1 = First implemented auto-exposure
9628+ * algorithm version
9629+ * MARVIN_FEATURE_AUTO_EXPOSURE_V2 = Second implemented auto-exposure
9630+ * algorithm version
9631+ *
9632+ * \par MARVIN_FEATURE_MI_STATUSFLAGS: (boolean)
9633+ * MI status flags needed for debugging purposes
9634+ *
9635+ * \par MARVIN_FEATURE_MIPI: (boolean)
9636+ * MIPI camera protocol block
9637+ *
9638+ * \par MARVIN_FEATURE_SMALL_OUTUNIT: (boolean)
9639+ * A small output unit instead of MI module
9640+ *
9641+ * \par MARVIN_FEATURE_CLOCK_DOMAINS: (integer)
9642+ * MARVIN_CLOCK_DOMAINS_1 = One clock domain for the complete MARVIN.
9643+ * MARVIN_CLOCK_DOMAINS_2 = Two clock domains (Camera data clock and AHB
9644+ * clock)
9645+ *
9646+ * \par MARVIN_FEATURE_WB: (integer)
9647+ * measurement and correction unit for white balance
9648+ * MARVIN_FEATURE_WB_V1 = basic white balance block
9649+ * MARVIN_FEATURE_WB_V2 = like version 1, but Y_max added
9650+ * MARVIN_FEATURE_WB_V3 = like version 2, but green_diff_gain added
9651+ * MARVIN_FEATURE_WB_V4 = version 4of the white balance block. Extended gain
9652+ * range 0..4, resolution 10 bit, separated green
9653+ * gains for red and blue rows of bayer pattern.
9654+ *
9655+ * \par MARVIN_FEATURE_OUTPUT_FORMATTER: (integer)
9656+ * position of the output formatter
9657+ * MARVIN_FEATURE_OUTPUT_FORMATTER_V1 = exists at ISP output (old style)
9658+ * MARVIN_FEATURE_OUTPUT_FORMATTER_V2 = exists at ISP input
9659+ * MARVIN_FEATURE_EXIST_NOT = there is no output formatter, as
9660+ * the image stabilization contains
9661+ * already this functionality
9662+ *
9663+ * \par MARVIN_FEATURE_MI: (integer)
9664+ * MARVIN_FEATURE_MI_V1 = basic version
9665+ * MARVIN_FEATURE_MI_V2 = introducing self-path DMA read
9666+ * MARVIN_FEATURE_MI_V3 = self path DMA read, rotation, line stripe, 8
9667+ * beat burst
9668+ *
9669+ * \par MARVIN_FEATURE_DMA_READ: (integer)
9670+ * MARVIN_FEATURE_DMA_READ_V1 = version 1
9671+ * MARVIN_FEATURE_DMA_READ_V2 = version 2
9672+ * MARVIN_FEATURE_DMA_READ_V3 = version 3
9673+ * MARVIN_FEATURE_DMA_READ_V4 = version 4
9674+ * MARVIN_FEATURE_EXIST_NOT = there is no DMA read feature
9675+ *
9676+ * \par MARVIN_FEATURE_JPE_SIZE: (integer)
9677+ * MARVIN_FEATURE_JPE_SIZE_11BITS =11 Bits for JPE_HSIZE and JPE_VSIZE, only
9678+ * Marvin1.
9679+ * MARVIN_FEATURE_JPE_SIZE_12BITS =12 Bits for JPE_HSIZE and JPE_VSIZE, all
9680+ * MARVIN3.
9681+ * MARVIN_FEATURE_JPE_SIZE_13BITS = 13 Bits for JPE_HSIZE and JPE_VSIZE, all
9682+ * MARVIN5.
9683+ *
9684+ * \par MARVIN_FEATURE_BLACK_LEVEL: (integer)
9685+ * MARVIN_FEATURE_EXIST_NOT = there is no BLS module
9686+ * MARVIN_FEATURE_BLACK_LEVEL_V1 = version 1; basic version with 8 Bit
9687+ * registers
9688+ * MARVIN_FEATURE_BLACK_LEVEL_V2 = version 2; extended version with 10 Bit
9689+ * registers
9690+ * MARVIN_FEATURE_BLACK_LEVEL_V3 = version 3; extended version with 12 Bit
9691+ * registers
9692+ * MARVIN_FEATURE_BLACK_LEVEL_V4 = version 4; advanced version with 2
9693+ * independent measurement windows
9694+ * and signed values; 10 Bit
9695+ * registers
9696+ * MARVIN_FEATURE_BLACK_LEVEL_V5 = version 5; like version 4
9697+ * with 12 Bit registers
9698+ *
9699+ * \par MARVIN_FEATURE_DPMUX_YCSPLIT: (integer)
9700+ * MARVIN_FEATURE_YCS_V1 = traditional datapath setup; separate datapath for
9701+ * raw data, y/c splitter does not support self path
9702+ * only mode
9703+ * MARVIN_FEATURE_YCS_V2 = version 2, raw data routed through main path,
9704+ * y/c splitter supports self path only mode.
9705+ *
9706+ * \par MARVIN_FEATURE_DPMUX_MAINPATH: (integer)
9707+ * MARVIN_FEATURE_DPMUX_MAIN_V1 = Traditional mainpath muxer. No direct path
9708+ * from DMA-read to JPEG encoder, explicit RAW
9709+ * datapath to MI
9710+ * MARVIN_FEATURE_DPMUX_MAIN_V2 = new DPCL register settings,
9711+ * possibility to feed
9712+ * JPEG encoder directly via DMA-Read
9713+ *
9714+ * \par MARVIN_FEATURE_INPUT_AQUISITION: (integer)
9715+ * MARVIN_FEATURE_IAQU_V1 = Traditional version, supports following modes:
9716+ * raw data mode,
9717+ * raw picture according to ITU-R BT.601,
9718+ * RGB Bayer according to ITU-R BT.601,
9719+ * ITU-R BT601 (YCbCr data),
9720+ * ITU-R BT656 (YCbCr data)
9721+ * MARVIN_FEATURE_IAQU_V2 = Additional modes:
9722+ * RGB Bayer according to ITU-R BT.656, raw
9723+ * picture according to ITU-R BT.656
9724+ *
9725+ * \par MARVIN_FEATURE_JPE: (integer)
9726+ * MARVIN_FEATURE_JPE_V1 = Basic version
9727+ * MARVIN_FEATURE_JPE_V2 = Enable bit frame synchronization
9728+ * MARVIN_FEATURE_JPE_V3 = flags for Motion JPEG
9729+ *
9730+ * \par MARVIN_FEATURE_EXT_YCBCR_RANGE: (boolean)
9731+ * ???
9732+ *
9733+ * \par MARVIN_FEATURE_SP_DMA: (boolean)
9734+ * ???
9735+ * \par MARVIN_FEATURE_MI_BURST_16: (boolean)
9736+ * MARVIN_FEATURE_EXIST = AHB 16 beat burst
9737+ * MARVIN_FEATURE_EXIST_NOT = AHB burst to 8 or 4 is possible
9738+ * \par MARVIN_FEATURE_MI_LAST_PIXEL: (boolean)
9739+ * last pixel signalization
9740+ */
9741+
9742+/* \name Values for all boolean features */
9743+#define MARVIN_FEATURE_EXIST_NOT (0)
9744+#define MARVIN_FEATURE_EXIST (1)
9745+
9746+/*
9747+ * \name Values for MARVIN_FEATURE_FRAMESIZE and
9748+ * MARVIN_FEATURE_MI_FRAMESIZE
9749+ */
9750+#define MARVIN_FEATURE_1M9 1
9751+#define MARVIN_FEATURE_3M1 2
9752+#define MARVIN_FEATURE_5M3 3
9753+#define MARVIN_FEATURE_12M6 4
9754+
9755+/* \name Values for MARVIN_FEATURE_CAMBUSWIDTH and
9756+ * MARVIN_FEATURE_SCALE_FACTORWIDTH
9757+ */
9758+#define MARVIN_FEATURE_7BITS 7
9759+#define MARVIN_FEATURE_8BITS 8
9760+#define MARVIN_FEATURE_9BITS 9
9761+#define MARVIN_FEATURE_10BITS 10
9762+#define MARVIN_FEATURE_11BITS 11
9763+#define MARVIN_FEATURE_12BITS 12
9764+#define MARVIN_FEATURE_14BITS 14
9765+#define MARVIN_FEATURE_16BITS 16
9766+
9767+/* \name Values for MARVIN_FEATURE_SMIA */
9768+#define MARVIN_FEATURE_SMIA_COMPLETE 1
9769+#define MARVIN_FEATURE_SMIA_EMP 2
9770+#define MARVIN_FEATURE_SMIA_MIPI_EMP 3
9771+
9772+/* \name Values for MARVIN_FEATURE_AUTO_EXPOSURE */
9773+#define MARVIN_FEATURE_AUTO_EXPOSURE_V1 1
9774+#define MARVIN_FEATURE_AUTO_EXPOSURE_V2 2
9775+#define MARVIN_FEATURE_AUTO_EXPOSURE_V3 3
9776+
9777+/* \name Values for MARVIN_FEATURE_CLOCK_DOMAINS */
9778+#define MARVIN_CLOCK_DOMAINS_1 1
9779+#define MARVIN_CLOCK_DOMAINS_2 2
9780+
9781+/* \name Values for MARVIN_FEATURE_WB: (integer) */
9782+#define MARVIN_FEATURE_WB_V4 4
9783+#define MARVIN_FEATURE_WB_V5 5
9784+
9785+/* \name Values for MARVIN_FEATURE_XTALK: (integer) */
9786+/* coefficient range -2.0 ... +1.992 ( 9 Bit) */
9787+#define MARVIN_FEATURE_XTALK_9BITS 2
9788+/* coefficient range -4.0 ... +3.992 (10 Bit) */
9789+#define MARVIN_FEATURE_XTALK_10BITS 3
9790+/* coefficient range -8.0 ... +7.992 (11 Bit) */
9791+#define MARVIN_FEATURE_XTALK_11BITS 4
9792+
9793+#define MARVIN_FEATURE_GAMMAIN_10BITS 1
9794+#define MARVIN_FEATURE_GAMMAIN_12BITS 2
9795+/* \name Values for MARVIN_FEATURE_OUTPUT_FORMATTER: (integer) */
9796+#define MARVIN_FEATURE_OUTPUT_FORMATTER_V1 (2)
9797+#define MARVIN_FEATURE_OUTPUT_FORMATTER_V2 (3)
9798+
9799+/* \name Values for MARVIN_FEATURE_IMG_STABILIZATION: (integer) */
9800+#define MARVIN_FEATURE_IMG_STABILIZATION_V1 (2)
9801+#define MARVIN_FEATURE_IMG_STABILIZATION_V2 (3)
9802+
9803+/*
9804+ * \name Values for MARVIN_FEATURE_SSCALE_FACTORCALC and
9805+ * MARVIN_FEATURE_MSCALE_FACTORCALC: (integer)
9806+ */
9807+#define MARVIN_FEATURE_SCALEFACTOR_COMBINED_UV (2)
9808+#define MARVIN_FEATURE_SCALEFACTOR_SEPARATED_UV (3)
9809+
9810+/* \name Values for MARVIN_FEATURE_MI: (integer) */
9811+#define MARVIN_FEATURE_MI_V1 (2)
9812+#define MARVIN_FEATURE_MI_V2 (3)
9813+#define MARVIN_FEATURE_MI_V3 (4)
9814+#define MARVIN_FEATURE_MI_V4 (5)
9815+
9816+/* \name Values for MARVIN_FEATURE_DMA_READ: (integer) */
9817+#define MARVIN_FEATURE_DMA_READ_V1 (2)
9818+#define MARVIN_FEATURE_DMA_READ_V2 (3)
9819+#define MARVIN_FEATURE_DMA_READ_V3 (4)
9820+#define MARVIN_FEATURE_DMA_READ_V4 (5)
9821+
9822+/* \name Values for MARVIN_FEATURE_JPE_SIZE: (integer) */
9823+#define MARVIN_FEATURE_JPE_SIZE_11BITS 1
9824+#define MARVIN_FEATURE_JPE_SIZE_12BITS 2
9825+#define MARVIN_FEATURE_JPE_SIZE_13BITS 3
9826+
9827+/* \name Values for MARVIN_FEATURE_BLACK_LEVEL: (integer) */
9828+#define MARVIN_FEATURE_BLACK_LEVEL_V1 (2)
9829+#define MARVIN_FEATURE_BLACK_LEVEL_V2 (3)
9830+#define MARVIN_FEATURE_BLACK_LEVEL_V3 (4)
9831+#define MARVIN_FEATURE_BLACK_LEVEL_V4 (5)
9832+#define MARVIN_FEATURE_BLACK_LEVEL_V5 (6)
9833+
9834+/* \name Values for MARVIN_FEATURE_DPMUX_YCSPLIT: (integer) */
9835+#define MARVIN_FEATURE_YCS_V1 1
9836+#define MARVIN_FEATURE_YCS_V2 2
9837+
9838+/* \name Values for MARVIN_FEATURE_DPMUX_MAINPATH: (integer) */
9839+#define MARVIN_FEATURE_DPMUX_MAIN_V1 1
9840+#define MARVIN_FEATURE_DPMUX_MAIN_V2 2
9841+
9842+/* \name Values for MARVIN_FEATURE_INPUT_AQUISITION: (integer) */
9843+#define MARVIN_FEATURE_IAQU_V1 1
9844+#define MARVIN_FEATURE_IAQU_V2 2
9845+
9846+/* \name Values for MARVIN_FEATURE_JPE: (integer) */
9847+#define MARVIN_FEATURE_JPE_V1 (2)
9848+#define MARVIN_FEATURE_JPE_V2 (3)
9849+#define MARVIN_FEATURE_JPE_V3 (4)
9850+
9851+/* \name Values for MARVIN_FEATURE_JPE_CFG: (integer) */
9852+#define MARVIN_FEATURE_JPE_CFG_V1 (2)
9853+#define MARVIN_FEATURE_JPE_CFG_V2 (3)
9854+
9855+
9856+/* \name Values for MARVIN_FEATURE_ISP_FILTER: (integer) */
9857+#define MARVIN_FEATURE_ISP_FILTER_V1 1
9858+#define MARVIN_FEATURE_ISP_FILTER_V2 2
9859+
9860+/* \name Values for MARVIN_FEATURE_LENS_SHADING: (integer) */
9861+#define MARVIN_FEATURE_LSC_V1 1
9862+#define MARVIN_FEATURE_LSC_V2 2
9863+
9864+/* \name Values for MARVIN_FEATURE_HISTOGRAM: (integer) */
9865+#define MARVIN_FEATURE_HIST_V1 1
9866+#define MARVIN_FEATURE_HIST_V2 2
9867+#define MARVIN_FEATURE_HIST_V3 3
9868+
9869+#define MARVIN_FEATURE_IE_V1 (2)
9870+#define MARVIN_FEATURE_IE_V2 (3)
9871+#define MARVIN_FEATURE_IE_V3 (4)
9872+
9873+#if (MARVIN_HW == MARVIN_5_V4_R20)
9874+#define MARVIN_FEATURE_CHIP_ID 0x20453010
9875+#define MARVIN_FEATURE_CAMBUSWIDTH MARVIN_FEATURE_12BITS
9876+#define MARVIN_FEATURE_XTALK MARVIN_FEATURE_XTALK_11BITS
9877+ #define MARVIN_FEATURE_GAMMAIN MARVIN_FEATURE_GAMMAIN_12BITS
9878+#define MARVIN_FEATURE_GAMMAOUT MARVIN_FEATURE_EXIST
9879+#define MARVIN_FEATURE_FRAMESIZE MARVIN_FEATURE_5M3
9880+#define MARVIN_FEATURE_SP_DMA MARVIN_FEATURE_EXIST
9881+#define MARVIN_FEATURE_SSCALE MARVIN_FEATURE_EXIST
9882+#define MARVIN_FEATURE_SSCALE_UP MARVIN_FEATURE_EXIST
9883+#define MARVIN_FEATURE_SSCALE_FACTORCALC \
9884+ MARVIN_FEATURE_SCALEFACTOR_SEPARATED_UV
9885+#define MARVIN_FEATURE_MSCALE_UP MARVIN_FEATURE_EXIST
9886+#define MARVIN_FEATURE_MSCALE_FACTORCALC \
9887+ MARVIN_FEATURE_SCALEFACTOR_SEPARATED_UV
9888+#define MARVIN_FEATURE_SCALE_FACTORWIDTH MARVIN_FEATURE_14BITS
9889+#define MARVIN_FEATURE_AF_MEASURE MARVIN_FEATURE_EXIST
9890+#define MARVIN_FEATURE_BAD_PIXEL MARVIN_FEATURE_EXIST
9891+#define MARVIN_FEATURE_BAD_PIXEL_WIDTH MARVIN_FEATURE_12BITS
9892+#define MARVIN_FEATURE_BAD_PIXEL_RAM MARVIN_FEATURE_11BITS
9893+#define MARVIN_FEATURE_SUPERIMPOSE MARVIN_FEATURE_EXIST
9894+#define MARVIN_FEATURE_IMAGE_EFFECTS MARVIN_FEATURE_IE_V1
9895+#define MARVIN_FEATURE_LENS_SHADING MARVIN_FEATURE_LSC_V2
9896+#define MARVIN_FEATURE_ISP_ERRORFLAGS MARVIN_FEATURE_EXIST
9897+#define MARVIN_FEATURE_FRAMECOUNTER MARVIN_FEATURE_EXIST
9898+#define MARVIN_FEATURE_FLASH_LIGHT MARVIN_FEATURE_EXIST
9899+#define MARVIN_FEATURE_EXT_YCBCR_RANGE MARVIN_FEATURE_EXIST
9900+#define MARVIN_FEATURE_SHUTTER MARVIN_FEATURE_EXIST
9901+#define MARVIN_FEATURE_IMG_STABILIZATION MARVIN_FEATURE_IMG_STABILIZATION_V2
9902+#define MARVIN_FEATURE_ISP_HISTOGRAM MARVIN_FEATURE_HIST_V2
9903+#define MARVIN_FEATURE_ISP_CSM MARVIN_FEATURE_EXIST
9904+#define MARVIN_FEATURE_ISP_FILTER MARVIN_FEATURE_ISP_FILTER_V2
9905+#define MARVIN_FEATURE_SMIA MARVIN_FEATURE_SMIA_COMPLETE
9906+#define MARVIN_FEATURE_AUTO_EXPOSURE MARVIN_FEATURE_AUTO_EXPOSURE_V3
9907+#define MARVIN_FEATURE_MI_STATUSFLAGS MARVIN_FEATURE_EXIST
9908+#define MARVIN_FEATURE_MIPI MARVIN_FEATURE_EXIST
9909+#define MARVIN_FEATURE_SMALL_OUTUNIT MARVIN_FEATURE_EXIST_NOT
9910+#define MARVIN_FEATURE_CLOCK_DOMAINS MARVIN_CLOCK_DOMAINS_1
9911+#define MARVIN_FEATURE_WB MARVIN_FEATURE_WB_V5
9912+#define MARVIN_FEATURE_OUTPUT_FORMATTER MARVIN_FEATURE_OUTPUT_FORMATTER_V2
9913+#define MARVIN_FEATURE_MI MARVIN_FEATURE_MI_V4
9914+#define MARVIN_FEATURE_DMA_READ MARVIN_FEATURE_DMA_READ_V3
9915+#define MARVIN_FEATURE_JPE_SIZE MARVIN_FEATURE_JPE_SIZE_13BITS
9916+#define MARVIN_FEATURE_BLACK_LEVEL MARVIN_FEATURE_BLACK_LEVEL_V5
9917+#define MARVIN_FEATURE_DPMUX_YCSPLIT MARVIN_FEATURE_YCS_V2
9918+#define MARVIN_FEATURE_DPMUX_MAINPATH MARVIN_FEATURE_DPMUX_MAIN_V2
9919+#define MARVIN_FEATURE_INPUT_AQUISITION MARVIN_FEATURE_IAQU_V2
9920+#define MARVIN_FEATURE_JPE MARVIN_FEATURE_JPE_V3
9921+#define MARVIN_FEATURE_JPE_CFG MARVIN_FEATURE_JPE_CFG_V1
9922+#define MARVIN_FEATURE_XTALK_OFFSET MARVIN_FEATURE_EXIST
9923+#define MARVIN_FEATURE_CHROM_ABERRATION MARVIN_FEATURE_EXIST_NOT
9924+#define MARVIN_FEATURE_MI_BURST_16 MARVIN_FEATURE_EXIST
9925+#define MARVIN_FEATURE_MI_LAST_PIXEL MARVIN_FEATURE_EXIST
9926+#define MARVIN_FEATURE_MI_FRAMESIZE MARVIN_FEATURE_12M6
9927+#define MARVIN_FEATURE_BAYER_RGB MARVIN_FEATURE_EXIST
9928+
9929+#endif /* MARVIN_HW */
9930+
9931+#endif
9932--- /dev/null
9933+++ b/drivers/media/video/mrstci/mrstisp/include/reg_access.h
9934@@ -0,0 +1,233 @@
9935+/*
9936+ * Support for Moorestown Langwell Camera Imaging ISP subsystem.
9937+ *
9938+ * Copyright (c) 2009 Intel Corporation. All Rights Reserved.
9939+ *
9940+ * Copyright (c) Silicon Image 2008 www.siliconimage.com
9941+ *
9942+ * This program is free software; you can redistribute it and/or
9943+ * modify it under the terms of the GNU General Public License version
9944+ * 2 as published by the Free Software Foundation.
9945+ *
9946+ * This program is distributed in the hope that it will be useful,
9947+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
9948+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9949+ * GNU General Public License for more details.
9950+ *
9951+ * You should have received a copy of the GNU General Public License
9952+ * along with this program; if not, write to the Free Software
9953+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
9954+ * 02110-1301, USA.
9955+ *
9956+ *
9957+ * Xiaolin Zhang <xiaolin.zhang@intel.com>
9958+ */
9959+
9960+#ifndef _REG_ACCESS_H
9961+#define _REG_ACCESS_H
9962+
9963+/*
9964+ * Notes:
9965+ *
9966+ * registers:
9967+ * - use these macros to allow a central way e.g. to print out debug
9968+ * information on register access
9969+ *
9970+ * slices:
9971+ * - "parameter" \a reg could be a hardware register or a (32bit) variable,
9972+ * but not a pointer!
9973+ * - each slice (specified as "parameter" \a name) requires two \#defines:
9974+ * \b \<name\>_MASK : defines the mask to use on register side
9975+ * \b \<name\>_SHIFT : defines the shift value to use (left on write, right
9976+ * on read)
9977+ *
9978+ * arrays:
9979+ * - "parameter" \a areg could be an (32bit) array or a pointer to the
9980+ * first array element
9981+ * - each one-dimensional array (specified as "parameter" \a name) requires
9982+ * one \#define
9983+ * - <tt> \<name\>_ARR_SIZE </tt>: number of elements
9984+ * - each two-dimensional array (specified as "parameter" <name>) requires
9985+ * four \#defines:
9986+ * - <tt> \<name\>_ARR_SIZE1 </tt>: number of elements in first dimension
9987+ * - <tt> \<name\>_ARR_SIZE2 </tt>: number of elements in second dimension
9988+ * - <tt> \<name\>_ARR_OFS1 </tt>: offset between two consecutive elements
9989+ * in first dimension
9990+ * - <tt> \<name\>_ARR_OFS2 </tt>: offset between two consecutive elements
9991+ * in second dimension
9992+ */
9993+
9994+/*
9995+ * reads and returns the complete value of register \a reg
9996+ * \note Use these macro to allow a central way e.g. to print out debug
9997+ * information on register access.
9998+ */
9999+
10000+/* helper function to let REG_READ return the value */
10001+
10002+#define DBG_DD(x) \
10003+ do { \
10004+ if (mrstisp_debug >= 4) { \
10005+ printk(KERN_INFO "mrstisp@%s ", __func__); \
10006+ printk x; \
10007+ } \
10008+ } while (0)
10009+
10010+static inline u32 _reg_read(u32 reg, const char *text)
10011+{
10012+ u32 variable = reg;
10013+ DBG_DD((text, variable));
10014+ return variable;
10015+}
10016+
10017+#define REG_READ(reg) \
10018+_reg_read((reg), "REG_READ(" VAL2STR(reg) "): 0x%08X\n")
10019+
10020+static inline u32 _reg_read_ex(u32 reg, const char *text)
10021+{
10022+ u32 variable = reg;
10023+ DBG_DD((text, variable));
10024+ return variable;
10025+}
10026+
10027+#define REG_READ_EX(reg) \
10028+_reg_read_ex((reg), "REG_READ_EX(" VAL2STR(reg) "): 0x%08X\n")
10029+/*
10030+ * writes the complete value \a value into register \a reg
10031+ * \note Use these macro to allow a central way e.g. to print out debug
10032+ * information on register access.
10033+ */
10034+#define REG_WRITE(reg, value) \
10035+{ \
10036+ dprintk(4, \
10037+ "REG_WRITE(" VAL2STR(reg) ", " VAL2STR(value) "): 0x%08X", (value)); \
10038+ (reg) = (value); \
10039+}
10040+
10041+#define REG_WRITE_EX(reg, value) \
10042+{ \
10043+ (reg) = (value); \
10044+}
10045+
10046+
10047+/*
10048+ * returns the value of slice \a name from register or variable \a reg
10049+ * \note "parameter" \a reg could be a hardware register or a (32bit)
10050+ * variable, but not a pointer! \n
10051+ * each slice (specified as "parameter" \a name) requires two \#defines: \n
10052+ * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
10053+ * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write,
10054+ * right on read)
10055+ */
10056+
10057+static inline u32 _reg_get_slice(const char *text, u32 val)
10058+{
10059+ u32 variable = val;
10060+ DBG_DD((text, variable));
10061+ return val;
10062+}
10063+
10064+#define REG_GET_SLICE_EX(reg, name) \
10065+ (((reg) & (name##_MASK)) >> (name##_SHIFT))
10066+
10067+#define REG_GET_SLICE(reg, name) \
10068+ _reg_get_slice("REG_GET_SLICE(" VAL2STR(reg) ", " VAL2STR(name) \
10069+ "): 0x%08X\n" , \
10070+ (((reg) & (name##_MASK)) >> (name##_SHIFT)))
10071+
10072+/*
10073+ * writes the value \a value into slice \a name of register or variable \a reg
10074+ * \note "parameter" \a reg could be a hardware register or a (32bit) variable,
10075+ * but not a pointer! \n
10076+ * each slice (specified as "parameter" \a name) requires two \#defines: \n
10077+ * - <tt>\<name\>_MASK </tt>: defines the mask to use on register side
10078+ * - <tt>\<name\>_SHIFT </tt>: defines the shift value to use (left on write,
10079+ * right on read)
10080+ */
10081+#define REG_SET_SLICE(reg, name, value) \
10082+{ \
10083+ dprintk(4, \
10084+ "REG_SET_SLICE(" VAL2STR(reg) ", " VAL2STR(name) \
10085+ ", " VAL2STR(value) "): 0x%08X", \
10086+ (value)); \
10087+ ((reg) = (((reg) & ~(name##_MASK)) | \
10088+ (((value) << (name##_SHIFT)) & (name##_MASK)))); \
10089+}
10090+
10091+#define REG_SET_SLICE_EX(reg, name, value) \
10092+{ \
10093+ ((reg) = (((reg) & ~(name##_MASK)) | \
10094+ (((value) << (name##_SHIFT)) & (name##_MASK)))); \
10095+}
10096+
10097+/*
10098+ * returns the value of element \a idx from register array or array variable \a
10099+ * areg
10100+ * \note "parameter" \a areg could be an (32bit) array or a pointer to the first
10101+ * array element \n
10102+ * each one-dimensional array (specified as "parameter" \a name) requires one
10103+ * \#define: \n
10104+ * - <tt>\<name\>_ARR_SIZE </tt>: number of elements
10105+ */
10106+#define REG_GET_ARRAY_ELEM1(areg, name, idx) \
10107+((idx < name##_ARR_SIZE) \
10108+? areg[idx] \
10109+: 0)
10110+
10111+
10112+/*
10113+ * writes the value \a value into element \a idx of register array or array
10114+ * variable \a areg
10115+ * \note "parameter" \a areg could be an (32bit) array or a pointer to the
10116+ * first array element \n
10117+ * each one-dimensional array (specified as "parameter" \a name) requires
10118+ * one \#define: \n
10119+ * - <tt>\<name\>_ARR_SIZE </tt>: number of elements
10120+ */
10121+#define REG_SET_ARRAY_ELEM1(areg, name, idx, value) \
10122+((idx < name##_ARR_SIZE) \
10123+? areg[idx] = value \
10124+: 0)
10125+
10126+
10127+/*
10128+ * returns the value of element \a idx1, \a idx2 from two-dimensional register
10129+ * array or array variable \a areg
10130+ * \note "parameter" \a areg could be an (32bit) array or a pointer to the
10131+ * first array element \n
10132+ * each two-dimensional array (specified as "parameter" \a name) requires
10133+ * four \#defines:
10134+ * - <tt>\<name\>_ARR_SIZE1 </tt>: number of elements in first dimension
10135+ * - <tt>\<name\>_ARR_SIZE2 </tt>: number of elements in second dimension
10136+ * - <tt>\<name\>_ARR_OFS1 </tt>: offset between two consecutive
10137+ * elements in first dimension
10138+ * - <tt>\<name\>_ARR_OFS2 </tt>: offset between two consecutive
10139+ * elements in second dimension
10140+ */
10141+#define REG_GET_ARRAY_ELEM2(areg, name, idx1, idx2) \
10142+(((idx1 < name##_ARR_SIZE1) && (idx2 < name##_ARR_SIZE2)) \
10143+? areg[(idx1 * name##_ARR_OFS1) + (idx2 * name##_ARR_OFS2)] \
10144+: 0)
10145+
10146+
10147+/*
10148+ * writes the value \a value into element \a idx1, \a idx2 of two-dimensional
10149+ * register array or array variable \a areg
10150+ * \note "parameter" \a areg could be an (32bit) array or a pointer to the
10151+ * first array element \n
10152+ * each two-dimensional array (specified as "parameter" \a name) requires
10153+ * four \#defines:
10154+ * - <tt>\<name\>_ARR_SIZE1 </tt>: number of elements in first dimension
10155+ * - <tt>\<name\>_ARR_SIZE2 </tt>: number of elements in second dimension
10156+ * - <tt>\<name\>_ARR_OFS1 </tt>: offset between two consecutive
10157+ * elements in first dimension
10158+ * - <tt>\<name\>_ARR_OFS2 </tt>: offset between two consecutive
10159+ * elements in second dimension
10160+ */
10161+#define REG_SET_ARRAY_ELEM2(areg, name, idx1, idx2, value) \
10162+(((idx1 < name##_ARR_SIZE1) && (idx2 < name##_ARR_SIZE2)) \
10163+? areg[(idx1 * name##_ARR_OFS1) + (idx2 * name##_ARR_OFS2)] = value \
10164+: 0)
10165+
10166+/* _REG_ACCESS_H */
10167+#endif
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