summaryrefslogtreecommitdiffstats
path: root/meta/recipes-devtools/binutils
diff options
context:
space:
mode:
authorRichard Purdie <richard.purdie@linuxfoundation.org>2021-12-09 17:22:55 +0000
committerRichard Purdie <richard.purdie@linuxfoundation.org>2021-12-12 11:27:23 +0000
commitd4f4ed77b15496d882e2142f1e7132dd82cea038 (patch)
tree63e7fa0f8b3a7b1670c1eb7a7e90a2c672ee79d0 /meta/recipes-devtools/binutils
parentfb8f1924f51ae4546eba9edf3dff81b4ff79afb0 (diff)
downloadpoky-d4f4ed77b15496d882e2142f1e7132dd82cea038.tar.gz
binutils: Drop mips XLP support patch
The kernel has dropped this as of 5.16 and we don't want to carry such patches without active maintainers for such targets. It isn't clear who would even have such hardware and it isn't something we can support. It would be best maintained as a separate layer by those who can test it if needed. (From OE-Core rev: 5cd5075412639c0be9506cf1101737b12894fc5f) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-devtools/binutils')
-rw-r--r--meta/recipes-devtools/binutils/binutils-2.37.inc1
-rw-r--r--meta/recipes-devtools/binutils/binutils/0010-Add-support-for-Netlogic-XLP.patch415
2 files changed, 0 insertions, 416 deletions
diff --git a/meta/recipes-devtools/binutils/binutils-2.37.inc b/meta/recipes-devtools/binutils/binutils-2.37.inc
index 8c6e659e73..5ac17c4a65 100644
--- a/meta/recipes-devtools/binutils/binutils-2.37.inc
+++ b/meta/recipes-devtools/binutils/binutils-2.37.inc
@@ -26,7 +26,6 @@ SRC_URI = "\
26 file://0006-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch \ 26 file://0006-Only-generate-an-RPATH-entry-if-LD_RUN_PATH-is-not-e.patch \
27 file://0007-don-t-let-the-distro-compiler-point-to-the-wrong-ins.patch \ 27 file://0007-don-t-let-the-distro-compiler-point-to-the-wrong-ins.patch \
28 file://0008-warn-for-uses-of-system-directories-when-cross-linki.patch \ 28 file://0008-warn-for-uses-of-system-directories-when-cross-linki.patch \
29 file://0010-Add-support-for-Netlogic-XLP.patch \
30 file://0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch \ 29 file://0011-fix-the-incorrect-assembling-for-ppc-wait-mnemonic.patch \
31 file://0013-Use-libtool-2.4.patch \ 30 file://0013-Use-libtool-2.4.patch \
32 file://0014-Fix-rpath-in-libtool-when-sysroot-is-enabled.patch \ 31 file://0014-Fix-rpath-in-libtool-when-sysroot-is-enabled.patch \
diff --git a/meta/recipes-devtools/binutils/binutils/0010-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0010-Add-support-for-Netlogic-XLP.patch
deleted file mode 100644
index b2f7448a28..0000000000
--- a/meta/recipes-devtools/binutils/binutils/0010-Add-support-for-Netlogic-XLP.patch
+++ /dev/null
@@ -1,415 +0,0 @@
1From 21920b7a3d10a7dae4c1f18a4bb185de78048e3f Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Sun, 14 Feb 2016 17:06:19 +0000
4Subject: [PATCH] Add support for Netlogic XLP
5
6Patch From: Nebu Philips <nphilips@netlogicmicro.com>
7
8Using the mipsisa64r2nlm target, add support for XLP from
9Netlogic. Also, update vendor name to NLM wherever applicable.
10
11Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
12assigned to INSN_OCTEON3
13
14Upstream-Status: Pending
15
16Signed-off-by: Khem Raj <raj.khem@gmail.com>
17Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
18Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
19---
20 bfd/aoutx.h | 1 +
21 bfd/archures.c | 1 +
22 bfd/bfd-in2.h | 1 +
23 bfd/config.bfd | 5 +++++
24 bfd/cpu-mips.c | 6 ++++--
25 bfd/elfxx-mips.c | 8 ++++++++
26 binutils/readelf.c | 1 +
27 gas/config/tc-mips.c | 4 +++-
28 gas/configure | 3 +++
29 gas/configure.ac | 3 +++
30 include/elf/mips.h | 1 +
31 include/opcode/mips.h | 8 +++++++-
32 ld/configure.tgt | 3 +++
33 opcodes/mips-dis.c | 12 +++++-------
34 opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
35 15 files changed, 66 insertions(+), 22 deletions(-)
36
37diff --git a/bfd/aoutx.h b/bfd/aoutx.h
38index 17560bd8f54..10b1cad74e6 100644
39--- a/bfd/aoutx.h
40+++ b/bfd/aoutx.h
41@@ -810,6 +810,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
42 case bfd_mach_mipsisa64r6:
43 case bfd_mach_mips_sb1:
44 case bfd_mach_mips_xlr:
45+ case bfd_mach_mips_xlp:
46 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
47 arch_flags = M_MIPS2;
48 break;
49diff --git a/bfd/archures.c b/bfd/archures.c
50index 390691bfba1..b0b7a5fa7a0 100644
51--- a/bfd/archures.c
52+++ b/bfd/archures.c
53@@ -185,6 +185,7 @@ DESCRIPTION
54 .#define bfd_mach_mips_octeon3 6503
55 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *}
56 .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *}
57+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP'. *}
58 .#define bfd_mach_mipsisa32 32
59 .#define bfd_mach_mipsisa32r2 33
60 .#define bfd_mach_mipsisa32r3 34
61diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
62index 57b3c453649..a00b0d44359 100644
63--- a/bfd/bfd-in2.h
64+++ b/bfd/bfd-in2.h
65@@ -1562,6 +1562,7 @@ enum bfd_architecture
66 #define bfd_mach_mips_octeon3 6503
67 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */
68 #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */
69+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP'. */
70 #define bfd_mach_mipsisa32 32
71 #define bfd_mach_mipsisa32r2 33
72 #define bfd_mach_mipsisa32r3 34
73diff --git a/bfd/config.bfd b/bfd/config.bfd
74index 1896e11790c..8270fd2708d 100644
75--- a/bfd/config.bfd
76+++ b/bfd/config.bfd
77@@ -874,6 +874,11 @@ case "${targ}" in
78 targ_defvec=mips_elf32_le_vec
79 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
80 ;;
81+ mipsisa64*-*-elf*)
82+ targ_defvec=mips_elf32_trad_be_vec
83+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
84+ want64=true
85+ ;;
86 mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
87 targ_defvec=mips_elf32_be_vec
88 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
89diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
90index 76b507e3c77..c1563cf4319 100644
91--- a/bfd/cpu-mips.c
92+++ b/bfd/cpu-mips.c
93@@ -108,7 +108,8 @@ enum
94 I_mipsocteon3,
95 I_xlr,
96 I_interaptiv_mr2,
97- I_micromips
98+ I_micromips,
99+ I_xlp
100 };
101
102 #define NN(index) (&arch_info_struct[(index) + 1])
103@@ -163,7 +164,8 @@ static const bfd_arch_info_type arch_info_struct[] =
104 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", false, NN(I_xlr)),
105 N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", false,
106 NN(I_interaptiv_mr2)),
107- N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NULL)
108+ N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NN(I_micromips)),
109+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", false, NULL)
110 };
111
112 /* The default architecture is mips:3000, but with a machine number of
113diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
114index e4827fd17de..fa8c2512837 100644
115--- a/bfd/elfxx-mips.c
116+++ b/bfd/elfxx-mips.c
117@@ -6980,6 +6980,9 @@ _bfd_elf_mips_mach (flagword flags)
118 case E_MIPS_MACH_IAMR2:
119 return bfd_mach_mips_interaptiv_mr2;
120
121+ case E_MIPS_MACH_XLP:
122+ return bfd_mach_mips_xlp;
123+
124 default:
125 switch (flags & EF_MIPS_ARCH)
126 {
127@@ -12339,6 +12342,10 @@ mips_set_isa_flags (bfd *abfd)
128 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
129 break;
130
131+ case bfd_mach_mips_xlp:
132+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
133+ break;
134+
135 case bfd_mach_mipsisa32:
136 val = E_MIPS_ARCH_32;
137 break;
138@@ -14428,6 +14435,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
139 { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
140 { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
141 { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
142+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
143
144 /* MIPS64 extensions. */
145 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
146diff --git a/binutils/readelf.c b/binutils/readelf.c
147index a6073f7ec80..2f2448b5eba 100644
148--- a/binutils/readelf.c
149+++ b/binutils/readelf.c
150@@ -3613,6 +3613,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
151 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
152 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
153 case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
154+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
155 case 0:
156 /* We simply ignore the field in this case to avoid confusion:
157 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
158diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
159index 0201f816814..a3cfcdbe982 100644
160--- a/gas/config/tc-mips.c
161+++ b/gas/config/tc-mips.c
162@@ -570,6 +570,7 @@ static int mips_32bitmode = 0;
163 || mips_opts.arch == CPU_RM7000 \
164 || mips_opts.arch == CPU_VR5500 \
165 || mips_opts.micromips \
166+ || mips_opts.arch == CPU_XLP \
167 )
168
169 /* Whether the processor uses hardware interlocks to protect reads
170@@ -599,6 +600,7 @@ static int mips_32bitmode = 0;
171 && mips_opts.isa != ISA_MIPS3) \
172 || mips_opts.arch == CPU_R4300 \
173 || mips_opts.micromips \
174+ || mips_opts.arch == CPU_XLP \
175 )
176
177 /* Whether the processor uses hardware interlocks to protect reads
178@@ -20157,7 +20159,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
179 /* Broadcom XLP.
180 XLP is mostly like XLR, with the prominent exception that it is
181 MIPS64R2 rather than MIPS64. */
182- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
183+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
184
185 /* MIPS 64 Release 6. */
186 { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
187diff --git a/gas/configure b/gas/configure
188index 110d707f079..789d1b38b33 100755
189--- a/gas/configure
190+++ b/gas/configure
191@@ -12083,6 +12083,9 @@ _ACEOF
192 mipsisa64r6 | mipsisa64r6el)
193 mips_cpu=mips64r6
194 ;;
195+ mipsisa64r2nlm | mipsisa64r2nlmel)
196+ mips_cpu=xlp
197+ ;;
198 mipstx39 | mipstx39el)
199 mips_cpu=r3900
200 ;;
201diff --git a/gas/configure.ac b/gas/configure.ac
202index 78efba88e23..c1b4ef6b3b0 100644
203--- a/gas/configure.ac
204+++ b/gas/configure.ac
205@@ -331,6 +331,9 @@ changequote([,])dnl
206 mipsisa64r6 | mipsisa64r6el)
207 mips_cpu=mips64r6
208 ;;
209+ mipsisa64r2nlm | mipsisa64r2nlmel)
210+ mips_cpu=xlp
211+ ;;
212 mipstx39 | mipstx39el)
213 mips_cpu=r3900
214 ;;
215diff --git a/include/elf/mips.h b/include/elf/mips.h
216index 4bd86307120..2d7df22abf2 100644
217--- a/include/elf/mips.h
218+++ b/include/elf/mips.h
219@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
220 #define E_MIPS_MACH_SB1 0x008a0000
221 #define E_MIPS_MACH_OCTEON 0x008b0000
222 #define E_MIPS_MACH_XLR 0x008c0000
223+#define E_MIPS_MACH_XLP 0x008f0000
224 #define E_MIPS_MACH_OCTEON2 0x008d0000
225 #define E_MIPS_MACH_OCTEON3 0x008e0000
226 #define E_MIPS_MACH_5400 0x00910000
227diff --git a/include/opcode/mips.h b/include/opcode/mips.h
228index 9add3c9d5bf..a99c53f652f 100644
229--- a/include/opcode/mips.h
230+++ b/include/opcode/mips.h
231@@ -1157,7 +1157,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
232 #define INSN_ISA32R3 8
233 #define INSN_ISA32R5 9
234 #define INSN_ISA32R6 10
235-#define INSN_ISA64 11
236+#define INSN_ISA64 11
237 #define INSN_ISA64R2 12
238 #define INSN_ISA64R3 13
239 #define INSN_ISA64R5 14
240@@ -1265,6 +1265,8 @@ static const unsigned int mips_isa_table[] = {
241 #define INSN_XLR 0x00000020
242 /* Imagination interAptiv MR2. */
243 #define INSN_INTERAPTIV_MR2 0x04000000
244+/* Netlogic XlP instruction */
245+#define INSN_XLP 0x00000080
246
247 /* DSP ASE */
248 #define ASE_DSP 0x00000001
249@@ -1389,6 +1391,7 @@ static const unsigned int mips_isa_table[] = {
250 #define CPU_OCTEON3 6503
251 #define CPU_XLR 887682 /* decimal 'XLR' */
252 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
253+#define CPU_XLP 887680 /* decimal 'XLP' */
254
255 /* Return true if the given CPU is included in INSN_* mask MASK. */
256
257@@ -1459,6 +1462,9 @@ cpu_is_member (int cpu, unsigned int mask)
258 case CPU_INTERAPTIV_MR2:
259 return (mask & INSN_INTERAPTIV_MR2) != 0;
260
261+ case CPU_XLP:
262+ return (mask & INSN_XLP) != 0;
263+
264 default:
265 return false;
266 }
267diff --git a/ld/configure.tgt b/ld/configure.tgt
268index c08533658e5..7abf32215c2 100644
269--- a/ld/configure.tgt
270+++ b/ld/configure.tgt
271@@ -509,6 +509,9 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
272 targ_emul=elf32btsmip
273 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip"
274 ;;
275+mipsisa64*-*-elf*) targ_emul=elf32btsmip
276+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip"
277+ ;;
278 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
279 targ_extra_emuls="elf32lr5900"
280 targ_extra_libpath=$targ_extra_emuls
281diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
282index 591caf11e28..00120afed47 100644
283--- a/opcodes/mips-dis.c
284+++ b/opcodes/mips-dis.c
285@@ -698,13 +698,11 @@ const struct mips_arch_choice mips_arch_choices[] =
286 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
287 mips_cp1_names_mips3264, mips_hwr_names_numeric },
288
289- /* XLP is mostly like XLR, with the prominent exception it is being
290- MIPS64R2. */
291- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
292- ISA_MIPS64R2 | INSN_XLR, 0,
293- mips_cp0_names_xlr,
294- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
295- mips_cp1_names_mips3264, mips_hwr_names_numeric },
296+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
297+ ISA_MIPS64R2 | INSN_XLP, 0,
298+ mips_cp0_names_mips3264r2,
299+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
300+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
301
302 /* This entry, mips16, is here only for ISA/processor selection; do
303 not print its name. */
304diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
305index db72c039bfd..ff2fa614de1 100644
306--- a/opcodes/mips-opc.c
307+++ b/opcodes/mips-opc.c
308@@ -329,6 +329,7 @@ decode_mips_operand (const char *p)
309 #define IOCT3 INSN_OCTEON3
310 #define XLR INSN_XLR
311 #define IAMR2 INSN_INTERAPTIV_MR2
312+#define XLP INSN_XLP
313 #define IVIRT ASE_VIRT
314 #define IVIRT64 ASE_VIRT64
315
316@@ -991,6 +992,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
317 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
318 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
319 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
320+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
321 /* ctc0 is at the bottom of the table. */
322 {"ctc1", "t,g", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
323 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
324@@ -1023,12 +1025,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
325 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
326 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
327 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
328-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
329+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
330 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
331 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
332 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
333 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
334 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
335+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
336 /* dctr and dctw are used on the r5000. */
337 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
338 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
339@@ -1100,6 +1103,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
340 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
341 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
342 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
343+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
344 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
345 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
346 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
347@@ -1113,6 +1117,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
348 /* dmfc2 is at the bottom of the table. */
349 /* dmtc2 is at the bottom of the table. */
350 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
351+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
352+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
353 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
354 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
355 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
356@@ -1266,9 +1272,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
357 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
358 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
359 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
360-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
361-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
362-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
363+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
364+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
365+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
366 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
367 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
368 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
369@@ -1437,7 +1443,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
370 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
371 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
372 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
373-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
374+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
375 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
376 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
377 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
378@@ -1482,10 +1488,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
379 /* move is at the top of the table. */
380 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
381 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
382+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
383 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
384 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
385-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
386-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
387+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
388+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
389+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
390+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
391 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
392 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
393 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
394@@ -1535,7 +1544,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
395 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
396 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
397 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
398-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
399+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
400 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
401 {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
402 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
403@@ -1977,9 +1986,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
404 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
405 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
406 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
407-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
408-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
409-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
410+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
411+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
412+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
413 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, I2 },
414 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, I2 },
415 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-25 21:43:11 +0000