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authorKhem Raj <raj.khem@gmail.com>2020-02-20 09:13:40 -0800
committerRichard Purdie <richard.purdie@linuxfoundation.org>2020-02-22 23:57:27 +0000
commitfd0e3e1708393cf4b59802843c2c6c917798145c (patch)
tree6cdcbf2d50b78b0e1cc24571bc4eea4a5735e833 /meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
parent746f277acc908c75a1578c018b5dd03fb88bcb1a (diff)
downloadpoky-fd0e3e1708393cf4b59802843c2c6c917798145c.tar.gz
binutils: Upgrade to 2.34 release
Details of changelog [1] Removing bfd/ld patch to enable PE targets, instead use specific emulations via --enable-targets for x86_64 Re-arrange/forward-port patches and upgrade libctf configure to libtool 2.4 patch rpaths are no longer emitted into elfedit/readelf therefore no need of chrpath anymore Instead of pre-generating configure scripts and house them in libtool patch, generate them during configure. This also ensures that we do not patch configure directly but rather the sources which generate it Package newly added libctf library [1] https://lists.gnu.org/archive/html/info-gnu/2020-02/msg00000.html (From OE-Core rev: 82f7d5cfc2ab02f39b69c0f8697d660936422d4a) Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Christopher Clark <christopher.clark6@baesystems.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch')
-rw-r--r--meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch406
1 files changed, 406 insertions, 0 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
new file mode 100644
index 0000000000..c32867a238
--- /dev/null
+++ b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
@@ -0,0 +1,406 @@
1From a0237ec2d1e58bd35c236df39dd5a06504c6d2ed Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com>
3Date: Sun, 14 Feb 2016 17:06:19 +0000
4Subject: [PATCH] Add support for Netlogic XLP
5
6Patch From: Nebu Philips <nphilips@netlogicmicro.com>
7
8Using the mipsisa64r2nlm target, add support for XLP from
9Netlogic. Also, update vendor name to NLM wherever applicable.
10
11Use 0x00000080 for INSN_XLP, the value 0x00000040 has already been
12assigned to INSN_OCTEON3
13
14Upstream-Status: Pending
15
16Signed-off-by: Khem Raj <raj.khem@gmail.com>
17Signed-off-by: Baoshan Pang <baoshan.pang@windriver.com>
18Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
19---
20 bfd/aoutx.h | 1 +
21 bfd/archures.c | 1 +
22 bfd/bfd-in2.h | 1 +
23 bfd/config.bfd | 5 +++++
24 bfd/cpu-mips.c | 6 ++++--
25 bfd/elfxx-mips.c | 8 ++++++++
26 binutils/readelf.c | 1 +
27 gas/config/tc-mips.c | 4 +++-
28 gas/configure | 3 +++
29 gas/configure.ac | 3 +++
30 include/elf/mips.h | 1 +
31 include/opcode/mips.h | 6 ++++++
32 ld/configure.tgt | 3 +++
33 opcodes/mips-dis.c | 12 +++++-------
34 opcodes/mips-opc.c | 31 ++++++++++++++++++++-----------
35 15 files changed, 65 insertions(+), 21 deletions(-)
36
37diff --git a/bfd/aoutx.h b/bfd/aoutx.h
38index fa3a9746b6..5078024fd5 100644
39--- a/bfd/aoutx.h
40+++ b/bfd/aoutx.h
41@@ -799,6 +799,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
42 case bfd_mach_mipsisa64r6:
43 case bfd_mach_mips_sb1:
44 case bfd_mach_mips_xlr:
45+ case bfd_mach_mips_xlp:
46 /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */
47 arch_flags = M_MIPS2;
48 break;
49diff --git a/bfd/archures.c b/bfd/archures.c
50index 232103817c..b2b3b8c124 100644
51--- a/bfd/archures.c
52+++ b/bfd/archures.c
53@@ -185,6 +185,7 @@ DESCRIPTION
54 .#define bfd_mach_mips_octeon3 6503
55 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *}
56 .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *}
57+.#define bfd_mach_mips_xlp 887680 {* decimal 'XLP'. *}
58 .#define bfd_mach_mipsisa32 32
59 .#define bfd_mach_mipsisa32r2 33
60 .#define bfd_mach_mipsisa32r3 34
61diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
62index 7c13bc8c91..2e453c50c1 100644
63--- a/bfd/bfd-in2.h
64+++ b/bfd/bfd-in2.h
65@@ -1568,6 +1568,7 @@ enum bfd_architecture
66 #define bfd_mach_mips_octeon3 6503
67 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */
68 #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */
69+#define bfd_mach_mips_xlp 887680 /* decimal 'XLP'. */
70 #define bfd_mach_mipsisa32 32
71 #define bfd_mach_mipsisa32r2 33
72 #define bfd_mach_mipsisa32r3 34
73diff --git a/bfd/config.bfd b/bfd/config.bfd
74index 847f9f0ba9..a12707f827 100644
75--- a/bfd/config.bfd
76+++ b/bfd/config.bfd
77@@ -894,6 +894,11 @@ case "${targ}" in
78 targ_defvec=mips_elf32_le_vec
79 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
80 ;;
81+ mipsisa64*-*-elf*)
82+ targ_defvec=mips_elf32_trad_be_vec
83+ targ_selvecs="mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec"
84+ want64=true
85+ ;;
86 mips*-*-elf* | mips*-*-rtems* | mips*-*-windiss | mips*-*-none)
87 targ_defvec=mips_elf32_be_vec
88 targ_selvecs="mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec"
89diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
90index 802acb45f1..fd9ec4c0ad 100644
91--- a/bfd/cpu-mips.c
92+++ b/bfd/cpu-mips.c
93@@ -108,7 +108,8 @@ enum
94 I_mipsocteon3,
95 I_xlr,
96 I_interaptiv_mr2,
97- I_micromips
98+ I_micromips,
99+ I_xlp
100 };
101
102 #define NN(index) (&arch_info_struct[(index) + 1])
103@@ -163,7 +164,8 @@ static const bfd_arch_info_type arch_info_struct[] =
104 N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
105 N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", FALSE,
106 NN(I_interaptiv_mr2)),
107- N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NULL)
108+ N (64, 64, bfd_mach_mips_micromips, "mips:micromips", FALSE, NN(I_micromips)),
109+ N (64, 64, bfd_mach_mips_xlp, "mips:xlp", FALSE, NULL)
110 };
111
112 /* The default architecture is mips:3000, but with a machine number of
113diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
114index d7e3aed3b6..7baeee9ee3 100644
115--- a/bfd/elfxx-mips.c
116+++ b/bfd/elfxx-mips.c
117@@ -6999,6 +6999,9 @@ _bfd_elf_mips_mach (flagword flags)
118 case E_MIPS_MACH_IAMR2:
119 return bfd_mach_mips_interaptiv_mr2;
120
121+ case E_MIPS_MACH_XLP:
122+ return bfd_mach_mips_xlp;
123+
124 default:
125 switch (flags & EF_MIPS_ARCH)
126 {
127@@ -12355,6 +12358,10 @@ mips_set_isa_flags (bfd *abfd)
128 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
129 break;
130
131+ case bfd_mach_mips_xlp:
132+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_XLP;
133+ break;
134+
135 case bfd_mach_mipsisa32:
136 val = E_MIPS_ARCH_32;
137 break;
138@@ -14379,6 +14386,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
139 { bfd_mach_mips_gs264e, bfd_mach_mips_gs464e },
140 { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
141 { bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
142+ { bfd_mach_mips_xlp, bfd_mach_mipsisa64r2 },
143
144 /* MIPS64 extensions. */
145 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
146diff --git a/binutils/readelf.c b/binutils/readelf.c
147index 6b5bebe743..d15a7828db 100644
148--- a/binutils/readelf.c
149+++ b/binutils/readelf.c
150@@ -3440,6 +3440,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
151 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
152 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
153 case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
154+ case E_MIPS_MACH_XLP: strcat (buf, ", xlp"); break;
155 case 0:
156 /* We simply ignore the field in this case to avoid confusion:
157 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
158diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
159index fc6898834e..2c7151ccdb 100644
160--- a/gas/config/tc-mips.c
161+++ b/gas/config/tc-mips.c
162@@ -568,6 +568,7 @@ static int mips_32bitmode = 0;
163 || mips_opts.arch == CPU_RM7000 \
164 || mips_opts.arch == CPU_VR5500 \
165 || mips_opts.micromips \
166+ || mips_opts.arch == CPU_XLP \
167 )
168
169 /* Whether the processor uses hardware interlocks to protect reads
170@@ -597,6 +598,7 @@ static int mips_32bitmode = 0;
171 && mips_opts.isa != ISA_MIPS3) \
172 || mips_opts.arch == CPU_R4300 \
173 || mips_opts.micromips \
174+ || mips_opts.arch == CPU_XLP \
175 )
176
177 /* Whether the processor uses hardware interlocks to protect reads
178@@ -20135,7 +20137,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
179 /* Broadcom XLP.
180 XLP is mostly like XLR, with the prominent exception that it is
181 MIPS64R2 rather than MIPS64. */
182- { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
183+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLP },
184
185 /* MIPS 64 Release 6. */
186 { "i6400", 0, ASE_VIRT | ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
187diff --git a/gas/configure b/gas/configure
188index 60c1a055ae..59d6d11215 100755
189--- a/gas/configure
190+++ b/gas/configure
191@@ -12722,6 +12722,9 @@ _ACEOF
192 mipsisa64r6 | mipsisa64r6el)
193 mips_cpu=mips64r6
194 ;;
195+ mipsisa64r2nlm | mipsisa64r2nlmel)
196+ mips_cpu=xlp
197+ ;;
198 mipstx39 | mipstx39el)
199 mips_cpu=r3900
200 ;;
201diff --git a/gas/configure.ac b/gas/configure.ac
202index 6f32e55a1a..11c2e0d273 100644
203--- a/gas/configure.ac
204+++ b/gas/configure.ac
205@@ -325,6 +325,9 @@ changequote([,])dnl
206 mipsisa64r6 | mipsisa64r6el)
207 mips_cpu=mips64r6
208 ;;
209+ mipsisa64r2nlm | mipsisa64r2nlmel)
210+ mips_cpu=xlp
211+ ;;
212 mipstx39 | mipstx39el)
213 mips_cpu=r3900
214 ;;
215diff --git a/include/elf/mips.h b/include/elf/mips.h
216index d116b036b6..dceeb3f156 100644
217--- a/include/elf/mips.h
218+++ b/include/elf/mips.h
219@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
220 #define E_MIPS_MACH_SB1 0x008a0000
221 #define E_MIPS_MACH_OCTEON 0x008b0000
222 #define E_MIPS_MACH_XLR 0x008c0000
223+#define E_MIPS_MACH_XLP 0x008f0000
224 #define E_MIPS_MACH_OCTEON2 0x008d0000
225 #define E_MIPS_MACH_OCTEON3 0x008e0000
226 #define E_MIPS_MACH_5400 0x00910000
227diff --git a/include/opcode/mips.h b/include/opcode/mips.h
228index fd031f3758..a96a44df84 100644
229--- a/include/opcode/mips.h
230+++ b/include/opcode/mips.h
231@@ -1260,6 +1260,8 @@ static const unsigned int mips_isa_table[] = {
232 #define INSN_XLR 0x00000020
233 /* Imagination interAptiv MR2. */
234 #define INSN_INTERAPTIV_MR2 0x04000000
235+/* Netlogic XlP instruction */
236+#define INSN_XLP 0x00000080
237
238 /* DSP ASE */
239 #define ASE_DSP 0x00000001
240@@ -1384,6 +1386,7 @@ static const unsigned int mips_isa_table[] = {
241 #define CPU_OCTEON3 6503
242 #define CPU_XLR 887682 /* decimal 'XLR' */
243 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
244+#define CPU_XLP 887680 /* decimal 'XLP' */
245
246 /* Return true if the given CPU is included in INSN_* mask MASK. */
247
248@@ -1461,6 +1464,9 @@ cpu_is_member (int cpu, unsigned int mask)
249 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
250 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
251
252+ case CPU_XLP:
253+ return (mask & INSN_XLP) != 0;
254+
255 default:
256 return FALSE;
257 }
258diff --git a/ld/configure.tgt b/ld/configure.tgt
259index f4f0eaf9b2..0da3eca19c 100644
260--- a/ld/configure.tgt
261+++ b/ld/configure.tgt
262@@ -520,6 +520,9 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
263 targ_emul=elf32btsmip
264 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip"
265 ;;
266+mipsisa64*-*-elf*) targ_emul=elf32btsmip
267+ targ_extra_emuls="elf32ltsmip elf64btsmip elf64ltsmip"
268+ ;;
269 mips64*el-ps2-elf*) targ_emul=elf32lr5900n32
270 targ_extra_emuls="elf32lr5900"
271 targ_extra_libpath=$targ_extra_emuls
272diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
273index 755bbe294b..ce22ef683a 100644
274--- a/opcodes/mips-dis.c
275+++ b/opcodes/mips-dis.c
276@@ -674,13 +674,11 @@ const struct mips_arch_choice mips_arch_choices[] =
277 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
278 mips_cp1_names_mips3264, mips_hwr_names_numeric },
279
280- /* XLP is mostly like XLR, with the prominent exception it is being
281- MIPS64R2. */
282- { "xlp", 1, bfd_mach_mips_xlr, CPU_XLR,
283- ISA_MIPS64R2 | INSN_XLR, 0,
284- mips_cp0_names_xlr,
285- mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
286- mips_cp1_names_mips3264, mips_hwr_names_numeric },
287+ { "xlp", 1, bfd_mach_mips_xlp, CPU_XLP,
288+ ISA_MIPS64R2 | INSN_XLP, 0,
289+ mips_cp0_names_mips3264r2,
290+ mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
291+ mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
292
293 /* This entry, mips16, is here only for ISA/processor selection; do
294 not print its name. */
295diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
296index 5270aeefa8..d17dc78cd7 100644
297--- a/opcodes/mips-opc.c
298+++ b/opcodes/mips-opc.c
299@@ -328,6 +328,7 @@ decode_mips_operand (const char *p)
300 #define IOCT3 INSN_OCTEON3
301 #define XLR INSN_XLR
302 #define IAMR2 INSN_INTERAPTIV_MR2
303+#define XLP INSN_XLP
304 #define IVIRT ASE_VIRT
305 #define IVIRT64 ASE_VIRT64
306
307@@ -990,6 +991,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
308 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
309 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
310 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
311+{"crc", "d,s,t", 0x7000001c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
312 /* ctc0 is at the bottom of the table. */
313 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
314 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
315@@ -1022,12 +1024,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
316 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
317 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
318 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
319-{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
320+{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR|XLP, 0, 0 },
321 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
322 {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
323 {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
324 {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
325 {"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
326+{"dcrc", "d,s,t", 0x7000001d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
327 /* dctr and dctw are used on the r5000. */
328 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
329 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
330@@ -1099,6 +1102,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
331 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
332 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
333 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
334+{"dmfur", "t,d", 0x7000001e, 0xffe007ff, WR_1, 0, XLP, 0, 0 },
335 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
336 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
337 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
338@@ -1114,6 +1118,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
339 /* dmfc3 is at the bottom of the table. */
340 /* dmtc3 is at the bottom of the table. */
341 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
342+{"dmtur", "t,d", 0x7000001f, 0xffe007ff, RD_1, 0, XLP, 0, 0 },
343+{"dmul", "d,s,t", 0x70000006, 0xfc0007ff, WR_1|RD_2|RD_3, 0, XLP, 0, 0 },
344 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
345 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
346 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
347@@ -1267,9 +1273,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
348 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
349 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
350 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
351-{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
352-{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
353-{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
354+{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
355+{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
356+{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
357 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
358 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
359 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
360@@ -1438,7 +1444,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
361 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
362 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
363 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
364-{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 },
365+{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR|XLP, 0, 0 },
366 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
367 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
368 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
369@@ -1483,10 +1489,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
370 /* move is at the top of the table. */
371 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
372 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
373+{"msgsnds", "d,t", 0x4a000001, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
374 {"msgld", "", 0, (int) M_MSGLD, INSN_MACRO, 0, XLR, 0, 0 },
375 {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 },
376-{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 },
377-{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 },
378+{"msglds", "d,t", 0x4a000002, 0xffe007ff, WR_1|RD_2|RD_C0|WR_C0, 0, XLP, 0, 0 },
379+{"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR|XLP, 0, 0 },
380+{"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR|XLP, 0, 0 },
381+{"msgsync", "", 0x4a000004, 0xffffffff,0, 0, XLP, 0, 0 },
382 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
383 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
384 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
385@@ -1536,7 +1545,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
386 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
387 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
388 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
389-{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 },
390+{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR|XLP, 0, 0 },
391 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
392 {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
393 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
394@@ -1978,9 +1987,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
395 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
396 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
397 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
398-{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
399-{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
400-{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
401+{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
402+{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
403+{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR|XLP, 0, 0 },
404 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
405 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
406 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-28 21:08:53 +0000