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authorKhem Raj <raj.khem@gmail.com>2018-07-17 00:41:04 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2018-07-26 13:16:40 +0100
commit26810bc160bd78924a7f1fddac31afb4981f5b6b (patch)
treed47c36cb8ff424c8e88b14cb92198e80de9c5e32 /meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
parent9245162e8bfc346c97d8e6c2ee5b77fc2c4bde92 (diff)
downloadpoky-26810bc160bd78924a7f1fddac31afb4981f5b6b.tar.gz
binutils: Upgrade to 2.31 release branch
(From OE-Core rev: 7eeec2ad91eca6ba44ea7b761d47082f4ebb04cc) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Ross Burton <ross.burton@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch')
-rw-r--r--meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch80
1 files changed, 40 insertions, 40 deletions
diff --git a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
index 1fefb680f8..4d64bd53f8 100644
--- a/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
+++ b/meta/recipes-devtools/binutils/binutils/0012-Add-support-for-Netlogic-XLP.patch
@@ -1,4 +1,4 @@
1From 3b40bf584615f794b85fd50d4d0a5c0a1d2ee7bf Mon Sep 17 00:00:00 2001 1From 96ff7570c29f792c466a933529fefda9b8e97994 Mon Sep 17 00:00:00 2001
2From: Khem Raj <raj.khem@gmail.com> 2From: Khem Raj <raj.khem@gmail.com>
3Date: Sun, 14 Feb 2016 17:06:19 +0000 3Date: Sun, 14 Feb 2016 17:06:19 +0000
4Subject: [PATCH 12/15] Add support for Netlogic XLP 4Subject: [PATCH 12/15] Add support for Netlogic XLP
@@ -34,10 +34,10 @@ Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
34 14 files changed, 61 insertions(+), 21 deletions(-) 34 14 files changed, 61 insertions(+), 21 deletions(-)
35 35
36diff --git a/bfd/aoutx.h b/bfd/aoutx.h 36diff --git a/bfd/aoutx.h b/bfd/aoutx.h
37index eec9c4ad2a..3bf0a71e63 100644 37index 023843b0be..46246fec2d 100644
38--- a/bfd/aoutx.h 38--- a/bfd/aoutx.h
39+++ b/bfd/aoutx.h 39+++ b/bfd/aoutx.h
40@@ -814,6 +814,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch, 40@@ -798,6 +798,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
41 case bfd_mach_mipsisa64r6: 41 case bfd_mach_mipsisa64r6:
42 case bfd_mach_mips_sb1: 42 case bfd_mach_mips_sb1:
43 case bfd_mach_mips_xlr: 43 case bfd_mach_mips_xlr:
@@ -46,10 +46,10 @@ index eec9c4ad2a..3bf0a71e63 100644
46 arch_flags = M_MIPS2; 46 arch_flags = M_MIPS2;
47 break; 47 break;
48diff --git a/bfd/archures.c b/bfd/archures.c 48diff --git a/bfd/archures.c b/bfd/archures.c
49index e83c57a2f3..3016ea1bae 100644 49index 282e983086..b38b05d132 100644
50--- a/bfd/archures.c 50--- a/bfd/archures.c
51+++ b/bfd/archures.c 51+++ b/bfd/archures.c
52@@ -201,6 +201,7 @@ DESCRIPTION 52@@ -183,6 +183,7 @@ DESCRIPTION
53 .#define bfd_mach_mips_octeon3 6503 53 .#define bfd_mach_mips_octeon3 6503
54 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *} 54 .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR'. *}
55 .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *} 55 .#define bfd_mach_mips_interaptiv_mr2 736550 {* decimal 'IA2'. *}
@@ -58,10 +58,10 @@ index e83c57a2f3..3016ea1bae 100644
58 .#define bfd_mach_mipsisa32r2 33 58 .#define bfd_mach_mipsisa32r2 33
59 .#define bfd_mach_mipsisa32r3 34 59 .#define bfd_mach_mipsisa32r3 34
60diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h 60diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
61index 42991e7848..27abc5d5a8 100644 61index 93745bd3fd..326e9e49ed 100644
62--- a/bfd/bfd-in2.h 62--- a/bfd/bfd-in2.h
63+++ b/bfd/bfd-in2.h 63+++ b/bfd/bfd-in2.h
64@@ -2062,6 +2062,7 @@ enum bfd_architecture 64@@ -2054,6 +2054,7 @@ enum bfd_architecture
65 #define bfd_mach_mips_octeon3 6503 65 #define bfd_mach_mips_octeon3 6503
66 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */ 66 #define bfd_mach_mips_xlr 887682 /* decimal 'XLR'. */
67 #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */ 67 #define bfd_mach_mips_interaptiv_mr2 736550 /* decimal 'IA2'. */
@@ -70,10 +70,10 @@ index 42991e7848..27abc5d5a8 100644
70 #define bfd_mach_mipsisa32r2 33 70 #define bfd_mach_mipsisa32r2 33
71 #define bfd_mach_mipsisa32r3 34 71 #define bfd_mach_mipsisa32r3 34
72diff --git a/bfd/config.bfd b/bfd/config.bfd 72diff --git a/bfd/config.bfd b/bfd/config.bfd
73index 8777f96bd2..7b80bda8c9 100644 73index 8a11c0680a..c882421343 100644
74--- a/bfd/config.bfd 74--- a/bfd/config.bfd
75+++ b/bfd/config.bfd 75+++ b/bfd/config.bfd
76@@ -1172,6 +1172,11 @@ case "${targ}" in 76@@ -896,6 +896,11 @@ case "${targ}" in
77 targ_defvec=mips_elf32_le_vec 77 targ_defvec=mips_elf32_le_vec
78 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec" 78 targ_selvecs="mips_elf32_be_vec mips_elf64_be_vec mips_elf64_le_vec"
79 ;; 79 ;;
@@ -110,10 +110,10 @@ index cb50c64371..2b9d1d6ecf 100644
110 110
111 /* The default architecture is mips:3000, but with a machine number of 111 /* The default architecture is mips:3000, but with a machine number of
112diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c 112diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
113index 285401367d..14ebb5f175 100644 113index d91942301c..5d1bd3f0b1 100644
114--- a/bfd/elfxx-mips.c 114--- a/bfd/elfxx-mips.c
115+++ b/bfd/elfxx-mips.c 115+++ b/bfd/elfxx-mips.c
116@@ -6806,6 +6806,9 @@ _bfd_elf_mips_mach (flagword flags) 116@@ -6805,6 +6805,9 @@ _bfd_elf_mips_mach (flagword flags)
117 case E_MIPS_MACH_IAMR2: 117 case E_MIPS_MACH_IAMR2:
118 return bfd_mach_mips_interaptiv_mr2; 118 return bfd_mach_mips_interaptiv_mr2;
119 119
@@ -123,7 +123,7 @@ index 285401367d..14ebb5f175 100644
123 default: 123 default:
124 switch (flags & EF_MIPS_ARCH) 124 switch (flags & EF_MIPS_ARCH)
125 { 125 {
126@@ -11963,6 +11966,10 @@ mips_set_isa_flags (bfd *abfd) 126@@ -12003,6 +12006,10 @@ mips_set_isa_flags (bfd *abfd)
127 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; 127 val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
128 break; 128 break;
129 129
@@ -134,7 +134,7 @@ index 285401367d..14ebb5f175 100644
134 case bfd_mach_mipsisa32: 134 case bfd_mach_mipsisa32:
135 val = E_MIPS_ARCH_32; 135 val = E_MIPS_ARCH_32;
136 break; 136 break;
137@@ -13936,6 +13943,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = 137@@ -13992,6 +13999,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
138 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, 138 { bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
139 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, 139 { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
140 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, 140 { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
@@ -143,10 +143,10 @@ index 285401367d..14ebb5f175 100644
143 /* MIPS64 extensions. */ 143 /* MIPS64 extensions. */
144 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, 144 { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
145diff --git a/binutils/readelf.c b/binutils/readelf.c 145diff --git a/binutils/readelf.c b/binutils/readelf.c
146index ae1cda9a7b..fed0387a94 100644 146index 2b78db219b..7a7178925f 100644
147--- a/binutils/readelf.c 147--- a/binutils/readelf.c
148+++ b/binutils/readelf.c 148+++ b/binutils/readelf.c
149@@ -3370,6 +3370,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) 149@@ -3403,6 +3403,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
150 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; 150 case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
151 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; 151 case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
152 case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break; 152 case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
@@ -155,7 +155,7 @@ index ae1cda9a7b..fed0387a94 100644
155 /* We simply ignore the field in this case to avoid confusion: 155 /* We simply ignore the field in this case to avoid confusion:
156 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU 156 MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
157diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c 157diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
158index c135131b59..d8fbda8e31 100644 158index 59df787155..48537226c0 100644
159--- a/gas/config/tc-mips.c 159--- a/gas/config/tc-mips.c
160+++ b/gas/config/tc-mips.c 160+++ b/gas/config/tc-mips.c
161@@ -552,6 +552,7 @@ static int mips_32bitmode = 0; 161@@ -552,6 +552,7 @@ static int mips_32bitmode = 0;
@@ -174,7 +174,7 @@ index c135131b59..d8fbda8e31 100644
174 ) 174 )
175 175
176 /* Whether the processor uses hardware interlocks to protect reads 176 /* Whether the processor uses hardware interlocks to protect reads
177@@ -19737,7 +19739,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = 177@@ -19778,7 +19780,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
178 /* Broadcom XLP. 178 /* Broadcom XLP.
179 XLP is mostly like XLR, with the prominent exception that it is 179 XLP is mostly like XLR, with the prominent exception that it is
180 MIPS64R2 rather than MIPS64. */ 180 MIPS64R2 rather than MIPS64. */
@@ -184,10 +184,10 @@ index c135131b59..d8fbda8e31 100644
184 /* MIPS 64 Release 6 */ 184 /* MIPS 64 Release 6 */
185 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6}, 185 { "i6400", 0, ASE_MSA, ISA_MIPS64R6, CPU_MIPS64R6},
186diff --git a/gas/configure b/gas/configure 186diff --git a/gas/configure b/gas/configure
187index a40ac2144f..65a6995243 100755 187index 134278fa25..2fdca147a1 100755
188--- a/gas/configure 188--- a/gas/configure
189+++ b/gas/configure 189+++ b/gas/configure
190@@ -12989,6 +12989,9 @@ _ACEOF 190@@ -13336,6 +13336,9 @@ _ACEOF
191 mipsisa64r6 | mipsisa64r6el) 191 mipsisa64r6 | mipsisa64r6el)
192 mips_cpu=mips64r6 192 mips_cpu=mips64r6
193 ;; 193 ;;
@@ -198,7 +198,7 @@ index a40ac2144f..65a6995243 100755
198 mips_cpu=r3900 198 mips_cpu=r3900
199 ;; 199 ;;
200diff --git a/include/elf/mips.h b/include/elf/mips.h 200diff --git a/include/elf/mips.h b/include/elf/mips.h
201index 9de0b4e175..74fc4f7e55 100644 201index 4e2cde3279..c329f38929 100644
202--- a/include/elf/mips.h 202--- a/include/elf/mips.h
203+++ b/include/elf/mips.h 203+++ b/include/elf/mips.h
204@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) 204@@ -290,6 +290,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
@@ -210,10 +210,10 @@ index 9de0b4e175..74fc4f7e55 100644
210 #define E_MIPS_MACH_OCTEON3 0x008e0000 210 #define E_MIPS_MACH_OCTEON3 0x008e0000
211 #define E_MIPS_MACH_5400 0x00910000 211 #define E_MIPS_MACH_5400 0x00910000
212diff --git a/include/opcode/mips.h b/include/opcode/mips.h 212diff --git a/include/opcode/mips.h b/include/opcode/mips.h
213index 5eea72f139..90f6d57e15 100644 213index 1ab1780567..74f457b579 100644
214--- a/include/opcode/mips.h 214--- a/include/opcode/mips.h
215+++ b/include/opcode/mips.h 215+++ b/include/opcode/mips.h
216@@ -1259,6 +1259,8 @@ static const unsigned int mips_isa_table[] = { 216@@ -1262,6 +1262,8 @@ static const unsigned int mips_isa_table[] = {
217 #define INSN_XLR 0x00000020 217 #define INSN_XLR 0x00000020
218 /* Imagination interAptiv MR2. */ 218 /* Imagination interAptiv MR2. */
219 #define INSN_INTERAPTIV_MR2 0x04000000 219 #define INSN_INTERAPTIV_MR2 0x04000000
@@ -222,7 +222,7 @@ index 5eea72f139..90f6d57e15 100644
222 222
223 /* DSP ASE */ 223 /* DSP ASE */
224 #define ASE_DSP 0x00000001 224 #define ASE_DSP 0x00000001
225@@ -1365,6 +1367,7 @@ static const unsigned int mips_isa_table[] = { 225@@ -1373,6 +1375,7 @@ static const unsigned int mips_isa_table[] = {
226 #define CPU_OCTEON3 6503 226 #define CPU_OCTEON3 6503
227 #define CPU_XLR 887682 /* decimal 'XLR' */ 227 #define CPU_XLR 887682 /* decimal 'XLR' */
228 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ 228 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
@@ -230,7 +230,7 @@ index 5eea72f139..90f6d57e15 100644
230 230
231 /* Return true if the given CPU is included in INSN_* mask MASK. */ 231 /* Return true if the given CPU is included in INSN_* mask MASK. */
232 232
233@@ -1445,6 +1448,9 @@ cpu_is_member (int cpu, unsigned int mask) 233@@ -1453,6 +1456,9 @@ cpu_is_member (int cpu, unsigned int mask)
234 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) 234 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
235 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); 235 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
236 236
@@ -241,10 +241,10 @@ index 5eea72f139..90f6d57e15 100644
241 return FALSE; 241 return FALSE;
242 } 242 }
243diff --git a/ld/configure.tgt b/ld/configure.tgt 243diff --git a/ld/configure.tgt b/ld/configure.tgt
244index 1d78465590..307e787b64 100644 244index 7fb2168503..a1db7adfe2 100644
245--- a/ld/configure.tgt 245--- a/ld/configure.tgt
246+++ b/ld/configure.tgt 246+++ b/ld/configure.tgt
247@@ -521,6 +521,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*) 247@@ -450,6 +450,8 @@ mips*el-sde-elf* | mips*el-mti-elf* | mips*el-img-elf*)
248 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) 248 mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*)
249 targ_emul=elf32btsmip 249 targ_emul=elf32btsmip
250 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; 250 targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;;
@@ -254,10 +254,10 @@ index 1d78465590..307e787b64 100644
254 targ_extra_emuls="elf32lr5900" 254 targ_extra_emuls="elf32lr5900"
255 targ_extra_libpath=$targ_extra_emuls ;; 255 targ_extra_libpath=$targ_extra_emuls ;;
256diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c 256diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
257index 984fcbb802..95b107d216 100644 257index bbf21328e8..38e487c16f 100644
258--- a/opcodes/mips-dis.c 258--- a/opcodes/mips-dis.c
259+++ b/opcodes/mips-dis.c 259+++ b/opcodes/mips-dis.c
260@@ -655,13 +655,11 @@ const struct mips_arch_choice mips_arch_choices[] = 260@@ -656,13 +656,11 @@ const struct mips_arch_choice mips_arch_choices[] =
261 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), 261 mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
262 mips_cp1_names_mips3264, mips_hwr_names_numeric }, 262 mips_cp1_names_mips3264, mips_hwr_names_numeric },
263 263
@@ -277,10 +277,10 @@ index 984fcbb802..95b107d216 100644
277 /* This entry, mips16, is here only for ISA/processor selection; do 277 /* This entry, mips16, is here only for ISA/processor selection; do
278 not print its name. */ 278 not print its name. */
279diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c 279diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
280index 180d613c93..65b7b8cc23 100644 280index 1cbcbc6abc..e1fbdc89de 100644
281--- a/opcodes/mips-opc.c 281--- a/opcodes/mips-opc.c
282+++ b/opcodes/mips-opc.c 282+++ b/opcodes/mips-opc.c
283@@ -328,6 +328,7 @@ decode_mips_operand (const char *p) 283@@ -329,6 +329,7 @@ decode_mips_operand (const char *p)
284 #define IOCT3 INSN_OCTEON3 284 #define IOCT3 INSN_OCTEON3
285 #define XLR INSN_XLR 285 #define XLR INSN_XLR
286 #define IAMR2 INSN_INTERAPTIV_MR2 286 #define IAMR2 INSN_INTERAPTIV_MR2
@@ -288,7 +288,7 @@ index 180d613c93..65b7b8cc23 100644
288 #define IVIRT ASE_VIRT 288 #define IVIRT ASE_VIRT
289 #define IVIRT64 ASE_VIRT64 289 #define IVIRT64 ASE_VIRT64
290 290
291@@ -966,6 +967,7 @@ const struct mips_opcode mips_builtin_opcodes[] = 291@@ -974,6 +975,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
292 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, 292 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
293 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, 293 {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
294 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, 294 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
@@ -296,7 +296,7 @@ index 180d613c93..65b7b8cc23 100644
296 /* ctc0 is at the bottom of the table. */ 296 /* ctc0 is at the bottom of the table. */
297 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, 297 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
298 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, 298 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
299@@ -998,12 +1000,13 @@ const struct mips_opcode mips_builtin_opcodes[] = 299@@ -1006,12 +1008,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
300 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, 300 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
301 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, 301 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
302 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, 302 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
@@ -311,7 +311,7 @@ index 180d613c93..65b7b8cc23 100644
311 /* dctr and dctw are used on the r5000. */ 311 /* dctr and dctw are used on the r5000. */
312 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, 312 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
313 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, 313 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
314@@ -1075,6 +1078,7 @@ const struct mips_opcode mips_builtin_opcodes[] = 314@@ -1083,6 +1086,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
315 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 }, 315 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
316 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 316 {"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
317 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 }, 317 {"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
@@ -319,7 +319,7 @@ index 180d613c93..65b7b8cc23 100644
319 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, 319 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
320 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, 320 {"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
321 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE }, 321 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
322@@ -1090,6 +1094,8 @@ const struct mips_opcode mips_builtin_opcodes[] = 322@@ -1098,6 +1102,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
323 /* dmfc3 is at the bottom of the table. */ 323 /* dmfc3 is at the bottom of the table. */
324 /* dmtc3 is at the bottom of the table. */ 324 /* dmtc3 is at the bottom of the table. */
325 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, 325 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
@@ -328,7 +328,7 @@ index 180d613c93..65b7b8cc23 100644
328 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, 328 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
329 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, 329 {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
330 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, 330 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
331@@ -1243,9 +1249,9 @@ const struct mips_opcode mips_builtin_opcodes[] = 331@@ -1251,9 +1257,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
332 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 }, 332 {"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
333 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, 333 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
334 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, 334 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
@@ -341,7 +341,7 @@ index 180d613c93..65b7b8cc23 100644
341 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, 341 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
342 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, 342 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
343 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, 343 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
344@@ -1410,7 +1416,7 @@ const struct mips_opcode mips_builtin_opcodes[] = 344@@ -1418,7 +1424,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
345 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, 345 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 },
346 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, 346 {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 },
347 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, 347 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 },
@@ -350,7 +350,7 @@ index 180d613c93..65b7b8cc23 100644
350 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, 350 {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 },
351 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, 351 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
352 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, 352 {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
353@@ -1455,10 +1461,13 @@ const struct mips_opcode mips_builtin_opcodes[] = 353@@ -1463,10 +1469,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
354 /* move is at the top of the table. */ 354 /* move is at the top of the table. */
355 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, 355 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
356 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 }, 356 {"msgsnd", "t", 0, (int) M_MSGSND, INSN_MACRO, 0, XLR, 0, 0 },
@@ -366,7 +366,7 @@ index 180d613c93..65b7b8cc23 100644
366 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, 366 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 },
367 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, 367 {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
368 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, 368 {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 },
369@@ -1508,7 +1517,7 @@ const struct mips_opcode mips_builtin_opcodes[] = 369@@ -1516,7 +1525,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
370 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, 370 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 },
371 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, 371 {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 },
372 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, 372 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 },
@@ -375,7 +375,7 @@ index 180d613c93..65b7b8cc23 100644
375 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, 375 {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
376 {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, 376 {"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 },
377 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, 377 {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 },
378@@ -1945,9 +1954,9 @@ const struct mips_opcode mips_builtin_opcodes[] = 378@@ -1953,9 +1962,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
379 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, 379 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37},
380 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, 380 {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
381 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, 381 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 },
@@ -389,5 +389,5 @@ index 180d613c93..65b7b8cc23 100644
389 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, 389 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 },
390 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, 390 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
391-- 391--
3922.16.1 3922.18.0
393 393