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authorXiaotian Wu <wuxiaotian@loongson.cn>2023-02-03 07:16:13 +0000
committerRichard Purdie <richard.purdie@linuxfoundation.org>2023-02-04 17:02:10 +0000
commitf3889273f5d736d30e901c651ea81260af701003 (patch)
treedd17e706873ff77cbc1def2c82acec8d457c640e /meta/classes-recipe/kernel-arch.bbclass
parent324b03e15fb8623690a5c5c64006602fdc7027a2 (diff)
downloadpoky-f3889273f5d736d30e901c651ea81260af701003.tar.gz
linux: add loongarch64 support
(From OE-Core rev: 103993845bb8efa3a17df4585b248d775795ac4f) Signed-off-by: Xiaotian Wu <wuxiaotian@loongson.cn> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/classes-recipe/kernel-arch.bbclass')
-rw-r--r--meta/classes-recipe/kernel-arch.bbclass2
1 files changed, 2 insertions, 0 deletions
diff --git a/meta/classes-recipe/kernel-arch.bbclass b/meta/classes-recipe/kernel-arch.bbclass
index 1531ae6cd5..777f900241 100644
--- a/meta/classes-recipe/kernel-arch.bbclass
+++ b/meta/classes-recipe/kernel-arch.bbclass
@@ -19,6 +19,7 @@ valid_archs = "alpha cris ia64 \
19 sh sh64 um h8300 \ 19 sh sh64 um h8300 \
20 parisc s390 v850 \ 20 parisc s390 v850 \
21 avr32 blackfin \ 21 avr32 blackfin \
22 loongarch64 \
22 microblaze \ 23 microblaze \
23 nios2 arc riscv xtensa" 24 nios2 arc riscv xtensa"
24 25
@@ -34,6 +35,7 @@ def map_kernel_arch(a, d):
34 elif re.match('aarch64_be$', a): return 'arm64' 35 elif re.match('aarch64_be$', a): return 'arm64'
35 elif re.match('aarch64_ilp32$', a): return 'arm64' 36 elif re.match('aarch64_ilp32$', a): return 'arm64'
36 elif re.match('aarch64_be_ilp32$', a): return 'arm64' 37 elif re.match('aarch64_be_ilp32$', a): return 'arm64'
38 elif re.match('loongarch(32|64|)$', a): return 'loongarch'
37 elif re.match('mips(isa|)(32|64|)(r6|)(el|)$', a): return 'mips' 39 elif re.match('mips(isa|)(32|64|)(r6|)(el|)$', a): return 'mips'
38 elif re.match('mcf', a): return 'm68k' 40 elif re.match('mcf', a): return 'm68k'
39 elif re.match('riscv(32|64|)(eb|)$', a): return 'riscv' 41 elif re.match('riscv(32|64|)(eb|)$', a): return 'riscv'