ReferenceGuide: Remove SDK section

- remove the recommendation to reserve huge pages at boot time
- The order of the chapters is weird, since we mention DPDK and OVS
  in the virtualization chapter, change the order to:  DPDK first, then
  OVS/OVS-DPDK, then the virtualization chapter.
- remove 7.1 chapter, together with BIOS seetings

Change-Id: Iad11c534f4855a41e3812db0b212b1c7ffd1efbf
Signed-off-by: Sona Sarmadi <sona.sarmadi@enea.com>

4 files changed, 12 insertions, 164 deletions

diff --git a/doc/book-enea-nfv-access-reference-guide-intel/doc/benchmarks.xml b/doc/book-enea-nfv-access-reference-guide-intel/doc/benchmarks.xml
index 2571f34..3fae2ba 100644
--- a/doc/book-enea-nfv-access-reference-guide-intel/doc/benchmarks.xml
+++ b/doc/book-enea-nfv-access-reference-guide-intel/doc/benchmarks.xml
@@ -82,156 +82,7 @@
     </itemizedlist>
   </section>
 
-  <section id="bios">
-    <title>BIOS Settings</title>
-
-    <para>The table below details the BIOS settings for which the default
-    values were changed when doing performance measurements.</para>
-
-    <table>
-      <title>BIOS Settings</title>
-
-      <tgroup cols="4">
-        <colspec align="left" />
-
-        <thead>
-          <row>
-            <entry align="center">Menu Path</entry>
-
-            <entry align="center">Setting Name</entry>
-
-            <entry align="center">Enea NFV Access value</entry>
-
-            <entry align="center">BIOS Default value</entry>
-          </row>
-        </thead>
-
-        <tbody>
-          <row>
-            <entry align="left">CPU Configuration</entry>
-
-            <entry align="left">Direct Cache Access (DCA)</entry>
-
-            <entry>Enable</entry>
-
-            <entry>Auto</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management
-            Configuration</entry>
-
-            <entry align="left">EIST (P-States)</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management Configuration
-            / CPU C State Control</entry>
-
-            <entry align="left">CPU C State</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management Configuration
-            / CPU Advanced PM Turning / Energy Perf BIAS</entry>
-
-            <entry align="left">Energy Performance Tuning</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management Configuration
-            / CPU Advanced PM Turning / Energy Perf BIAS</entry>
-
-            <entry align="left">Energy Performance BIAS Setting</entry>
-
-            <entry>Performance</entry>
-
-            <entry>Balanced Performance</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management Configuration
-            / CPU Advanced PM Turning / Energy Perf BIAS</entry>
-
-            <entry align="left">Power/Performance Switch</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>CPU Configuration / Advanced Power Management Configuration
-            / CPU Advanced PM Turning / Program PowerCTL _MSR</entry>
-
-            <entry align="left">Energy Efficient Turbo</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>Chipset Configuration / North Bridge / IIO
-            Configuration</entry>
-
-            <entry align="left">EV DFX Features</entry>
-
-            <entry>Enable</entry>
-
-            <entry>Disable</entry>
-          </row>
-
-          <row>
-            <entry>Chipset Configuration / North Bridge / Memory
-            Configuration</entry>
-
-            <entry align="left">Enforce POR</entry>
-
-            <entry>Disable</entry>
-
-            <entry>Enable</entry>
-          </row>
-
-          <row>
-            <entry>Chipset Configuration / North Bridge / Memory
-            Configuration</entry>
-
-            <entry align="left">Memory Frequency</entry>
-
-            <entry>2400</entry>
-
-            <entry>Auto</entry>
-          </row>
-
-          <row>
-            <entry>Chipset Configuration / North Bridge / Memory
-            Configuration</entry>
-
-            <entry align="left">DRAM RAPL Baseline</entry>
-
-            <entry>Disable</entry>
-
-            <entry>DRAM RAPL Mode 1</entry>
-          </row>
-        </tbody>
-      </tgroup>
-    </table>
-  </section>
-
-  <section id="use-cases" condition="hidden">
+  <section condition="hidden" id="use-cases">
     <title>Use Cases</title>
 
     <section id="docker-benchmarks">
diff --git a/doc/book-enea-nfv-access-reference-guide-intel/doc/book.xml b/doc/book-enea-nfv-access-reference-guide-intel/doc/book.xml
index ad26c6e..cec06b6 100644
--- a/doc/book-enea-nfv-access-reference-guide-intel/doc/book.xml
+++ b/doc/book-enea-nfv-access-reference-guide-intel/doc/book.xml
@@ -13,18 +13,18 @@
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
         <xi:include href="overview.xml"
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
+        <xi:include href="dpdk.xml"
+                xmlns:xi="http://www.w3.org/2001/XInclude" />
+        <xi:include href="ovs.xml"
+                xmlns:xi="http://www.w3.org/2001/XInclude" />
         <xi:include href="hypervisor_virtualization.xml"
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
         <xi:include href="container_virtualization.xml"
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
-        <xi:include href="ovs.xml"
-                xmlns:xi="http://www.w3.org/2001/XInclude" />
-        <xi:include href="dpdk.xml"
-                xmlns:xi="http://www.w3.org/2001/XInclude" />
         <xi:include href="ostree.xml"
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
         <xi:include href="benchmarks.xml"
                 xmlns:xi="http://www.w3.org/2001/XInclude" />
-        <xi:include href="using_nfv_access_sdks.xml"
-                xmlns:xi="http://www.w3.org/2001/XInclude" />
+        <!--    <xi:include href="using_nfv_access_sdks.xml"
+                xmlns:xi="http://www.w3.org/2001/XInclude" />-->
 </book>
diff --git a/doc/book-enea-nfv-access-reference-guide-intel/doc/dpdk.xml b/doc/book-enea-nfv-access-reference-guide-intel/doc/dpdk.xml
index 5c5cb9f..523a2d5 100644
--- a/doc/book-enea-nfv-access-reference-guide-intel/doc/dpdk.xml
+++ b/doc/book-enea-nfv-access-reference-guide-intel/doc/dpdk.xml
@@ -13,11 +13,7 @@
 
   <para>In order to take advantage of DPDK, Linux <ulink
   url="https://www.kernel.org/doc/Documentation/vm/hugetlbpage.txt">huge
-  pages</ulink> must be enabled in the system. The allocation of huge pages
-  should preferably be done at boot time by passing parameters on the kernel
-  command line. Add the following to the kernel boot parameters:</para>
-
-  <programlisting>default_hugepagesz=1GB hugepagesz=1GB hugepages=8 hugepagesz=2M hugepages=2048</programlisting>
+  pages</ulink> must be enabled in the system.</para>
 
   <para>For DPDK documentation, see <ulink
   url="http://dpdk.org/doc/guides-18.02/index.html">http://dpdk.org/doc/guides-18.02/index.html</ulink></para>
diff --git a/doc/book-enea-nfv-access-reference-guide-intel/doc/overview.xml b/doc/book-enea-nfv-access-reference-guide-intel/doc/overview.xml
index 800abe4..3439937 100644
--- a/doc/book-enea-nfv-access-reference-guide-intel/doc/overview.xml
+++ b/doc/book-enea-nfv-access-reference-guide-intel/doc/overview.xml
@@ -4,9 +4,10 @@
 <chapter id="overview">
   <title>Overview</title>
 
-  <para>The Enea NFV Access Reference Guide available with this release of the Enea NFV
-  Access seeks to provide further information that will help all intended
-  users make the most out of the virtualization features.</para>
+  <para>The Enea NFV Access Reference Guide seeks to provide further
+   information that will help users understand the high-level architecture
+   and features of the Enea NFV Access Platform. Focus is placed
+   on data-path and virtualization components.</para>
 
   <section id="description">
     <title>Enea NFV Access Description</title>