1 files changed, 10 insertions, 0 deletions

diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb
index d4157d16..4d268c2e 100644
--- a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb
@@ -28,11 +28,21 @@ EXTRA_OECMAKE += " \
                 -DCMAKE_BUILD_TYPE=Release \
                 -DCMAKE_EXPORT_COMPILE_COMANDS=ON \
                 "
+
+# For vck190 kind of devices
 PACKAGE_ARCH:versal-ai-core = "${SOC_VARIANT_ARCH}"
 EXTRA_OECMAKE:append:versal-ai-core = " -DXRT_AIE_BUILD=true"
 TARGET_CXXFLAGS:append:versal-ai-core = " -DXRT_ENABLE_AIE"
 DEPENDS:append:versal-ai-core = " libmetal-xlnx libxaiengine aiefal"
 RDEPENDS:${PN}:append:versal-ai-core = " libxaiengine aiefal"
+
+# For vek280 kind of devices
+PACKAGE_ARCH:versal-ai-edge = "${SOC_VARIANT_ARCH}"
+EXTRA_OECMAKE:append:versal-ai-edge = " -DXRT_AIE_BUILD=true"
+TARGET_CXXFLAGS:append:versal-ai-edge = " -DXRT_ENABLE_AIE"
+DEPENDS:append:versal-ai-edge = " libmetal libxaiengine aiefal"
+RDEPENDS:${PN}:append:versal-ai-edge = " libxaiengine aiefal"
+
 EXTRA_OECMAKE:append:versal = " -DXRT_LIBDFX=true"
 EXTRA_OECMAKE:append:zynqmp = " -DXRT_LIBDFX=true"
 DEPENDS:append:versal = " libdfx"