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Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch')
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch | 120 |
1 files changed, 120 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..cbf64d97 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch | |||
@@ -0,0 +1,120 @@ | |||
1 | From 45deb5bd3ae8c3db360ef181c9873e37d2288848 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Wed, 18 Jan 2017 12:14:51 +0530 | ||
4 | Subject: [PATCH 31/63] [Patch, microblaze]: Add new bit-field instructions | ||
5 | This patches adds new bsefi and bsifi instructions. BSEFI- The instruction | ||
6 | shall extract a bit field from a register and place it right-adjusted in the | ||
7 | destination register. The other bits in the destination register shall be set | ||
8 | to zero BSIFI- The instruction shall insert a right-adjusted bit field from a | ||
9 | register at another position in the destination register. The rest of the | ||
10 | bits in the destination register shall be unchanged | ||
11 | |||
12 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | ||
13 | |||
14 | ChangeLog: | ||
15 | 2016-02-03 Nagaraju Mekala <nmekala@xilix.com> | ||
16 | |||
17 | *microblaze.md (Update): Added new patterns | ||
18 | --- | ||
19 | gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++ | ||
20 | 1 file changed, 73 insertions(+) | ||
21 | |||
22 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
23 | index b7c16ac..67b298a 100644 | ||
24 | --- a/gcc/config/microblaze/microblaze.md | ||
25 | +++ b/gcc/config/microblaze/microblaze.md | ||
26 | @@ -982,6 +982,8 @@ | ||
27 | (set_attr "mode" "DI") | ||
28 | (set_attr "length" "20,20,20")]) | ||
29 | |||
30 | + | ||
31 | + | ||
32 | ;;---------------------------------------------------------------- | ||
33 | ;; Data movement | ||
34 | ;;---------------------------------------------------------------- | ||
35 | @@ -1776,6 +1778,7 @@ | ||
36 | (set_attr "length" "28")] | ||
37 | ) | ||
38 | |||
39 | + | ||
40 | ;;---------------------------------------------------------------- | ||
41 | ;; Setting a register from an integer comparison. | ||
42 | ;;---------------------------------------------------------------- | ||
43 | @@ -2489,4 +2492,74 @@ | ||
44 | DONE; | ||
45 | }") | ||
46 | |||
47 | +(define_expand "extvsi" | ||
48 | + [(set (match_operand:SI 0 "register_operand" "r") | ||
49 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
50 | + (match_operand:SI 2 "immediate_operand" "I") | ||
51 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
52 | +"TARGET_HAS_BITFIELD" | ||
53 | +" | ||
54 | +{ | ||
55 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); | ||
56 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); | ||
57 | + | ||
58 | + if ((len == 0) || (pos + len > 32) ) | ||
59 | + FAIL; | ||
60 | + | ||
61 | + ;;if (!register_operand (operands[1], VOIDmode)) | ||
62 | + ;; FAIL; | ||
63 | + if (operands[0] == operands[1]) | ||
64 | + FAIL; | ||
65 | + if (GET_CODE (operands[1]) == ASHIFT) | ||
66 | + FAIL; | ||
67 | +;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); | ||
68 | + emit_insn (gen_extv_32 (operands[0], operands[1], | ||
69 | + operands[2], operands[3])); | ||
70 | + DONE; | ||
71 | +}") | ||
72 | + | ||
73 | +(define_insn "extv_32" | ||
74 | + [(set (match_operand:SI 0 "register_operand" "=r") | ||
75 | + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | ||
76 | + (match_operand:SI 2 "immediate_operand" "I") | ||
77 | + (match_operand:SI 3 "immediate_operand" "I")))] | ||
78 | + "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0) | ||
79 | + && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)" | ||
80 | + "bsefi %0,%1,%2,%3" | ||
81 | + [(set_attr "type" "bshift") | ||
82 | + (set_attr "length" "4")]) | ||
83 | + | ||
84 | +(define_expand "insvsi" | ||
85 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
86 | + (match_operand:SI 1 "immediate_operand" "I") | ||
87 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
88 | + (match_operand:SI 3 "register_operand" "r"))] | ||
89 | + "TARGET_HAS_BITFIELD" | ||
90 | + " | ||
91 | +{ | ||
92 | + unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); | ||
93 | + unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); | ||
94 | + | ||
95 | + if (len <= 0 || pos + len > 32) | ||
96 | + FAIL; | ||
97 | + | ||
98 | + ;;if (!register_operand (operands[0], VOIDmode)) | ||
99 | + ;; FAIL; | ||
100 | + | ||
101 | + emit_insn (gen_insv_32 (operands[0], operands[1], | ||
102 | + operands[2], operands[3])); | ||
103 | + DONE; | ||
104 | +}") | ||
105 | + | ||
106 | +(define_insn "insv_32" | ||
107 | + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | ||
108 | + (match_operand:SI 1 "immediate_operand" "I") | ||
109 | + (match_operand:SI 2 "immediate_operand" "I")) | ||
110 | + (match_operand:SI 3 "register_operand" "r"))] | ||
111 | + "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0 | ||
112 | + && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32" | ||
113 | + "bsifi %0, %3, %1, %2" | ||
114 | + [(set_attr "type" "bshift") | ||
115 | + (set_attr "length" "4")]) | ||
116 | + | ||
117 | (include "sync.md") | ||
118 | -- | ||
119 | 2.7.4 | ||
120 | |||