diff options
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch')
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch new file mode 100644 index 00000000..de35f286 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0018-Patch-microblaze-Add-optimized-lshrsi3.patch | |||
@@ -0,0 +1,81 @@ | |||
1 | From 6db9d068e32a424ac04c27e963d1e58cb3ef8bdf Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Tue, 17 Jan 2017 15:23:57 +0530 | ||
4 | Subject: [PATCH 18/63] [Patch, microblaze]: Add optimized lshrsi3 When barrel | ||
5 | shifter is not present, the immediate value is greater than #5 and | ||
6 | optimization is -OS, the compiler will generate shift operation using loop. | ||
7 | |||
8 | Changelog | ||
9 | |||
10 | 2013-11-26 David Holsgrove <david.holsgrove@xilinx.com> | ||
11 | |||
12 | * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn | ||
13 | |||
14 | ChangeLog/testsuite | ||
15 | |||
16 | 2014-02-12 David Holsgrove <david.holsgrove@xilinx.com> | ||
17 | |||
18 | * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. | ||
19 | |||
20 | Signed-off-by:Nagaraju <nmekala@xilix.com> | ||
21 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | ||
22 | --- | ||
23 | gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ | ||
24 | .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++ | ||
25 | 2 files changed, 34 insertions(+) | ||
26 | create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c | ||
27 | |||
28 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
29 | index 3d2636e..aa2eda3 100644 | ||
30 | --- a/gcc/config/microblaze/microblaze.md | ||
31 | +++ b/gcc/config/microblaze/microblaze.md | ||
32 | @@ -1618,6 +1618,27 @@ | ||
33 | (set_attr "length" "4,4")] | ||
34 | ) | ||
35 | |||
36 | +(define_insn "*lshrsi3_with_size_opt" | ||
37 | + [(set (match_operand:SI 0 "register_operand" "=&d") | ||
38 | + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
39 | + (match_operand:SI 2 "immediate_operand" "I")))] | ||
40 | + "(INTVAL (operands[2]) > 5 && optimize_size)" | ||
41 | + { | ||
42 | + operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); | ||
43 | + | ||
44 | + output_asm_insn ("ori\t%3,r0,%2", operands); | ||
45 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
46 | + output_asm_insn ("addk\t%0,%1,r0", operands); | ||
47 | + | ||
48 | + output_asm_insn ("addik\t%3,%3,-1", operands); | ||
49 | + output_asm_insn ("bneid\t%3,.-4", operands); | ||
50 | + return "srl\t%0,%0"; | ||
51 | + } | ||
52 | + [(set_attr "type" "multi") | ||
53 | + (set_attr "mode" "SI") | ||
54 | + (set_attr "length" "20")] | ||
55 | +) | ||
56 | + | ||
57 | (define_insn "*lshrsi_inline" | ||
58 | [(set (match_operand:SI 0 "register_operand" "=&d") | ||
59 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
60 | diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c | ||
61 | new file mode 100644 | ||
62 | index 0000000..32a3be7 | ||
63 | --- /dev/null | ||
64 | +++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c | ||
65 | @@ -0,0 +1,13 @@ | ||
66 | +/* { dg-options "-Os -mno-xl-barrel-shift" } */ | ||
67 | + | ||
68 | +void testfunc(void) | ||
69 | +{ | ||
70 | + unsigned volatile int z = 8192; | ||
71 | + z >>= 8; | ||
72 | +} | ||
73 | +/* { dg-final { scan-assembler-not "\bsrli" } } */ | ||
74 | +/* { dg-final { scan-assembler "\ori\tr18,r0" } } */ | ||
75 | +/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */ | ||
76 | +/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */ | ||
77 | +/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ | ||
78 | +/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ | ||
79 | -- | ||
80 | 2.7.4 | ||
81 | |||