6 files changed, 21 insertions, 25 deletions

diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch
deleted file mode 100644
index 9575539e..00000000
--- a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/riscv-multilib-generator-python.patch
+++ /dev/null
@@ -1,14 +0,0 @@
-Use python3 instead of python when calling the mutlib-generator
-
-Upstream-Status: Backport
-
-Signed-off-by: Mark Hatle <mark.hatle@amd.com>
-
---- gcc-12.2.0/gcc/config/riscv/multilib-generator.orig 2024-02-22 19:23:07.166805418 -0700
-+++ gcc-12.2.0/gcc/config/riscv/multilib-generator      2024-02-22 19:18:12.803798625 -0700
-@@ -1,4 +1,4 @@
--#!/usr/bin/env python
-+#!/usr/bin/env python3
- 
- # RISC-V multilib list generator.
- # Copyright (C) 2011-2022 Free Software Foundation, Inc.
diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch
index e035b8a6..e035b8a6 100644
--- a/meta-vitis-tc/recipes-devtools/gcc/gcc-12/additional-microblaze-multilibs.patch
+++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/additional-microblaze-multilibs.patch
diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-13/riscv-multilib-generator-python.patch b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/riscv-multilib-generator-python.patch
new file mode 100644
index 00000000..ba08945c
--- /dev/null
+++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-13/riscv-multilib-generator-python.patch
@@ -0,0 +1,16 @@
+Use python3 instead of python when calling the mutlib-generator
+
+Upstream-Status: Pending
+
+Signed-off-by: Mark Hatle <mark.hatle@amd.com>
+
+Index: gcc-13.3.0/gcc/config/riscv/multilib-generator
+===================================================================
+--- gcc-13.3.0.orig/gcc/config/riscv/multilib-generator
++++ gcc-13.3.0/gcc/config/riscv/multilib-generator
+@@ -1,4 +1,4 @@
+-#!/usr/bin/env python
++#!/usr/bin/env python3
+ 
+ # RISC-V multilib list generator.
+ # Copyright (C) 2011-2023 Free Software Foundation, Inc.
diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend b/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend
index a439407d..e38dd8b3 100644
--- a/meta-vitis-tc/recipes-devtools/gcc/gcc-source_12.%.bbappend
+++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-source_13.%.bbappend
@@ -1,5 +1,4 @@
-# Add MicroBlaze Patches (only when using MicroBlaze)
-FILESEXTRAPATHS:append := ":${THISDIR}/gcc-12"
+FILESEXTRAPATHS:append := ":${THISDIR}/gcc-13"
 SRC_URI += " \
         file://additional-microblaze-multilibs.patch \
         file://riscv-multilib-generator-python.patch \
diff --git a/meta-vitis-tc/recipes-devtools/gcc/gcc-xilinx-standalone-multilib.inc b/meta-vitis-tc/recipes-devtools/gcc/gcc-xilinx-standalone-multilib.inc
index f69ac4d8..c69e0745 100644
--- a/meta-vitis-tc/recipes-devtools/gcc/gcc-xilinx-standalone-multilib.inc
+++ b/meta-vitis-tc/recipes-devtools/gcc/gcc-xilinx-standalone-multilib.inc
@@ -9,11 +9,10 @@ EXTRA_OECONF:append:xilinx-standalone:arm:baremetal-multilib-tc = " \
 
 # RISC V configuration
 RISCV_MULTILIB = "\
-rv32i-ilp32--;rv32if-ilp32f--;rv32ic-ilp32--;rv32ifc-ilp32f--;\
-rv32im-ilp32--;rv32imf-ilp32f--;rv32imc-ilp32--;rv32imfc-ilp32f--;\
-rv64i-lp64--;rv64if-lp64f--;rv64ic-lp64--;rv64ifc-lp64f--;\
-rv64im-lp64--;rv64imf-lp64f--;rv64imc-lp64--;rv64imfc-lp64f--;\
-rv32imfdc-ilp32d--;rv64imfdc-lp64d--\
+rv32i-ilp32--;rv32ic-ilp32--;rv32im-ilp32--;rv32imc-ilp32--;rv32imac-ilp32--;rv32e-ilp32e--;\
+rv32imf-ilp32f--;rv32imfc-ilp32f--;rv32imafc-ilp32f--;rv32imfdc-ilp32d--;\
+rv64i-lp64--;rv64ic-lp64--;rv64im-lp64--;rv64imc-lp64--;rv64imac-lp64--;\
+rv64imf-lp64f--;rv64imfc-lp64f--;rv64imafc-lp64f--;rv64imfdc-lp64d--\
 "
 
 EXTRA_OECONF:append:xilinx-standalone:riscv32:baremetal-multilib-tc = " \
diff --git a/meta-vitis-tc/recipes-devtools/gcc/libgcc_14.1.bbappend b/meta-vitis-tc/recipes-devtools/gcc/libgcc_14.1.bbappend
deleted file mode 100644
index 2490c419..00000000
--- a/meta-vitis-tc/recipes-devtools/gcc/libgcc_14.1.bbappend
+++ /dev/null
@@ -1,4 +0,0 @@
-# There are some configurations that can result in addition spec files being written
-FILES:${PN}-dev:append:xilinx-standalone:class-target:baremetal-multilib-tc = "\
-   ${libdir}/*.specs \
-"