57 files changed, 465 insertions, 710 deletions

diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
index e0f7b12e..9750cee8 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -1,7 +1,7 @@
-From e3f148dff6d6d926d1f39802f54abd59bd9e887c Mon Sep 17 00:00:00 2001
+From 89825e41d91ef04532a7a53d72f4eb33ad40d1d9 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 13:13:57 +0530
-Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
+Subject: [PATCH 01/53] LOCAL]: Testsuite - builtins tests require fpic
  Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 
 Conflicts:
@@ -12,7 +12,7 @@ Conflicts:
  1 file changed, 8 insertions(+)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 594c9297958..8350d9401d2 100644
+index baec137d9a3..ad62a7348bc 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 @@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
index 431dc7ef..bfb98bcd 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -1,7 +1,7 @@
-From bef1a4116efded9972e693ded5152f1d8670862e Mon Sep 17 00:00:00 2001
+From 997e53fc324c3414d09a883a7bff28e1e346c847 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 14:31:10 +0530
-Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
+Subject: [PATCH 02/53] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
  particular testcase fails with a timeout. Instead, fail it at compile-time
  for microblaze. This speeds up the testsuite without removing it from the
  FAIL reports.
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
index a2dc7ccc..6a4b907a 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -1,7 +1,7 @@
-From a063597f875142af49003e2f28b6c0f56e3b914d Mon Sep 17 00:00:00 2001
+From 66fb54b40c49c86e8cefa94523a3f65a6779d6f2 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:46:28 +0530
-Subject: [PATCH 03/54] [LOCAL]: For dejagnu static testing on qemu, suppress
+Subject: [PATCH 03/53] [LOCAL]: For dejagnu static testing on qemu, suppress
  warnings about multiple definitions from the test function and libc in line
  with method used by powerpc. Dynamic linking and using a qemu binary which
  understands sysroot resolves all test failures with builtins
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 4 deletions(-)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 8350d9401d2..d7c9b281d01 100644
+index ad62a7348bc..3a38fb1de91 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 @@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
index 661417d7..0d907474 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -1,7 +1,7 @@
-From c1028bcb40ccd8d61afc1ab798198948fbf74aa0 Mon Sep 17 00:00:00 2001
+From dd488cfaf9f909462290c85a1e30665f6252cbf1 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 15:50:35 +0530
-Subject: [PATCH 04/54] [Patch, testsuite]: Add MicroBlaze to target-supports
+Subject: [PATCH 04/53] [Patch, testsuite]: Add MicroBlaze to target-supports
  for atomic buil. .tin tests
 
 MicroBlaze added to supported targets for atomic builtin tests.
@@ -19,17 +19,17 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 0dfe3ae0651..86caf6db9a9 100644
+index 411e559f508..9e6a1480e8f 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
-@@ -7468,6 +7468,7 @@ proc check_effective_target_sync_int_long { } {
+@@ -7958,6 +7958,7 @@ proc check_effective_target_sync_int_long { } {
                  && [check_effective_target_arm_acq_rel])
              || [istarget bfin*-*linux*]
              || [istarget hppa*-*linux*]
 +            || [istarget microblaze*-*linux*]
              || [istarget s390*-*-*] 
              || [istarget powerpc*-*-*]
-             || [istarget crisv32-*-*] || [istarget cris-*-*]
+             || [istarget cris-*-*]
 -- 
 2.17.1
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
index d34988c5..1714c142 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -1,7 +1,7 @@
-From ae5ce07a67df89dabba61414ba7dabbdabc1ee1b Mon Sep 17 00:00:00 2001
+From 5576c4ca7641833a91b19b36d105a6b852c1a0cc Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 16:20:01 +0530
-Subject: [PATCH 05/54] [Patch, testsuite]: Update MicroBlaze strings test for
+Subject: [PATCH 05/53] [Patch, testsuite]: Update MicroBlaze strings test for
  new scan-assembly output resulting in use of $LC label
 
 ChangeLog/testsuite
@@ -13,15 +13,16 @@ ChangeLog/testsuite
 
 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 ---
- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
+ gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++
+ 1 file changed, 4 insertions(+)
 
 diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-index 7a63faf79f2..0403b7bdca9 100644
+index efaf3c660ea..347872360d3 100644
 --- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
 +++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-@@ -1,13 +1,15 @@
- /* { dg-options "-O3" } */
+@@ -3,6 +3,10 @@
+ /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
+ /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
  
 +/* { dg-final { scan-assembler "\.rodata*" } } */
 +/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
@@ -29,15 +30,7 @@ index 7a63faf79f2..0403b7bdca9 100644
 +
  #include <string.h>
  
--/* { dg-final { scan-assembler "\.rodata*" } } */
  extern void somefunc (char *);
- int testfunc ()
- {
-     char string2[80];
--/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
-     strcpy (string2, "hello");
-     somefunc (string2);
- }
 -- 
 2.17.1
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
index 4b45fcf1..def6e95e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -1,7 +1,7 @@
-From 49cf9cd3fedce80a63e9d03d42482dd4596c27a7 Mon Sep 17 00:00:00 2001
+From ea6a9f11d6a866fe20cca13d06c7386754543e6c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:14:15 +0530
-Subject: [PATCH 06/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
+Subject: [PATCH 06/53] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
  in regex match Extend regex pattern to include optional ext at the end of
  .weak to match the MicroBlaze weak label .weakext
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
index 8fa324ad..5f72ecd2 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -1,7 +1,7 @@
-From dc6cbb4e18a3f31441403146b8f159554c329897 Mon Sep 17 00:00:00 2001
+From fe007d78e220606b220dfc452fe9564ebfecd57a Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:34:27 +0530
-Subject: [PATCH 07/54] [Patch, testsuite]: Add MicroBlaze to
+Subject: [PATCH 07/53] [Patch, testsuite]: Add MicroBlaze to
  check_profiling_available Testsuite, add microblaze*-*-* target in
  check_profiling_available inline with other archs setting
  profiling_available_saved to 0
@@ -12,10 +12,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 1 insertion(+)
 
 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 86caf6db9a9..cbd9024ece9 100644
+index 9e6a1480e8f..7e9d0889f76 100644
 --- a/gcc/testsuite/lib/target-supports.exp
 +++ b/gcc/testsuite/lib/target-supports.exp
-@@ -707,6 +707,7 @@ proc check_profiling_available { test_what } {
+@@ -727,6 +727,7 @@ proc check_profiling_available { test_what } {
              || [istarget m68k-*-elf]
              || [istarget m68k-*-uclinux*]
              || [istarget mips*-*-elf*]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch
index 1fa55729..78dc5dcd 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0008-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -1,7 +1,7 @@
-From 602713d07d2e1b3a33a7f097baff270266aa4254 Mon Sep 17 00:00:00 2001
+From 63b07793addb119dfc3ec0a30225e767d8f48706 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:41:43 +0530
-Subject: [PATCH 08/54] [Patch, microblaze]: Fix atomic side effects. In
+Subject: [PATCH 08/53] [Patch, microblaze]: Fix atomic side effects. In
  atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
  during optimization. Previously, the outputs were considered unused; this
  generated assembly code with undefined side effects after invocation of the
@@ -18,7 +18,7 @@ Conflicts:
  2 files changed, 16 insertions(+), 8 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7049acd1dcd..eba2776ae56 100644
+index 472ef4c1d8d..b02034c9f1e 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -43,6 +43,9 @@
@@ -32,7 +32,7 @@ index 7049acd1dcd..eba2776ae56 100644
  
  (define_c_enum "unspec" [
 diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 76f530b9d3b..24cd67e1fdb 100644
+index 23e0f1c52e2..3b0fba1d3cf 100644
 --- a/gcc/config/microblaze/sync.md
 +++ b/gcc/config/microblaze/sync.md
 @@ -18,14 +18,19 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
index 666d344f..824b031c 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -1,7 +1,7 @@
-From d3d065c9645d795e03dab6db827c08231e011a1f Mon Sep 17 00:00:00 2001
+From 0aa9647936673e3ff1ac0082144b196309916ddb Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:45:45 +0530
-Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic boolean return value.
+Subject: [PATCH 09/53] [Patch, microblaze]: Fix atomic boolean return value.
  In atomic_compare_and_swapsi, fix boolean return value. Previously, it
  contained zero if successful and non-zero if unsuccessful.
 
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 4 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 24cd67e1fdb..76c3616c992 100644
+index 3b0fba1d3cf..d08400af4bb 100644
 --- a/gcc/config/microblaze/sync.md
 +++ b/gcc/config/microblaze/sync.md
 @@ -34,15 +34,16 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
index 22bf521d..a1896298 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -1,7 +1,7 @@
-From 8d9d1f457e1e270250d8a6700d4a1e1fa09465df Mon Sep 17 00:00:00 2001
+From a950e2d4fb15e9ebabe11a5606f24a510f297d6d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:50:17 +0530
-Subject: [PATCH 10/54] [Patch, microblaze]: Fix the Microblaze crash with
+Subject: [PATCH 10/53] [Patch, microblaze]: Fix the Microblaze crash with
  msmall-divides flag Compiler is crashing when we use msmall-divides and
  mxl-barrel-shift flag. This is because when use above flags
  microblaze_expand_divide function will be called for division operation. In
@@ -15,7 +15,7 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
  1 file changed, 1 insertion(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a0f81b71391..0186171c04c 100644
+index b444db17719..45405fa2160 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3709,8 +3709,7 @@ microblaze_expand_divide (rtx operands[])
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
index cce812bb..597e4e6e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -1,7 +1,7 @@
-From 03429c91d1db134e1deda4c8e58bc0939d5fedf9 Mon Sep 17 00:00:00 2001
+From 3c984648f42e5fcf586c4327f108486fb8630f0d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 16:52:56 +0530
-Subject: [PATCH 11/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
+Subject: [PATCH 11/53] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
  ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
  optimization is used. lshrsi3_with_size_opt is being removed as it has
  conflicts with unsigned int variables
@@ -12,7 +12,7 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
  1 file changed, 21 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index eba2776ae56..187ad522dcc 100644
+index b02034c9f1e..55477fd0a69 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1508,6 +1508,27 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
index e393f0fe..917b6d70 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -1,7 +1,7 @@
-From 6803fbc540db39865037994daa122cf10c0eb33a Mon Sep 17 00:00:00 2001
+From fa6e9e4317f9adb0748ade5029cbe3a10504ab54 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 10:57:19 +0530
-Subject: [PATCH 12/54] [Patch, microblaze]: Use bralid for profiler calls
+Subject: [PATCH 12/53] [Patch, microblaze]: Use bralid for profiler calls
  Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 12/54] [Patch, microblaze]: Use bralid for profiler calls
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index dc112f5301f..8aa3f155790 100644
+index 2ecec750526..e32ce7dbb51 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -486,7 +486,7 @@ typedef struct microblaze_args
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch
index b601c98a..0891750a 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0013-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -1,10 +1,13 @@
-From 5de3888c460a341667150d569548b3309188e7e8 Mon Sep 17 00:00:00 2001
+From a5b58621655fa306c37157dfe3092547adce0aab Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Thu, 12 Jan 2017 17:36:16 +0530
-Subject: [PATCH 13/54] [Patch, microblaze]: Removed moddi3 routinue Using the
+Subject: [PATCH 13/53] [Patch, microblaze]: Removed moddi3 routinue Using the
  default moddi3 function as the existing implementation has many bugs
 
 Signed-off-by:Nagaraju <nmekala@xilix.com>
+
+Conflicts:
+        libgcc/config/microblaze/moddi3.S
 ---
  libgcc/config/microblaze/moddi3.S     | 121 --------------------------
  libgcc/config/microblaze/t-microblaze |   3 +-
@@ -13,13 +16,13 @@ Signed-off-by:Nagaraju <nmekala@xilix.com>
 
 diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
 deleted file mode 100644
-index d0e24fdb89d..00000000000
+index 4bac960107e..00000000000
 --- a/libgcc/config/microblaze/moddi3.S
 +++ /dev/null
 @@ -1,121 +0,0 @@
 -###################################
 -# 
--#  Copyright (C) 2009-2020 Free Software Foundation, Inc.
+-#  Copyright (C) 2009-2021 Free Software Foundation, Inc.
 -#
 -#  Contributed by Michael Eager <eager@eagercon.com>.
 -#
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
index 3bd6efd5..cbee1692 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -1,7 +1,7 @@
-From b9a9e8f9d0994c76819ec605a0b7cd113f3b2cf0 Mon Sep 17 00:00:00 2001
+From a9abf680767f4294177d716cd95a9bec5c7916a7 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 14:41:58 +0530
-Subject: [PATCH 14/54] [Patch, microblaze]: Add INIT_PRIORITY support Added
+Subject: [PATCH 14/53] [Patch, microblaze]: Add INIT_PRIORITY support Added
  TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
 
 These macros allows users to control the order of initialization
@@ -26,7 +26,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 53 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0186171c04c..9eae5515c60 100644
+index 45405fa2160..62630aab64e 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2634,6 +2634,53 @@ print_operand_address (FILE * file, rtx addr)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
index ba20cf07..42d836cb 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -1,7 +1,7 @@
-From f448485f5e0507a7ab8be7f83c08f807200a3501 Mon Sep 17 00:00:00 2001
+From fe3572f4b0cc033db305b0d67abb88632bf13887 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 15:23:57 +0530
-Subject: [PATCH 15/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel
+Subject: [PATCH 15/53] [Patch, microblaze]: Add optimized lshrsi3 When barrel
  shifter is not present, the immediate value is greater than #5 and
  optimization is -OS, the compiler will generate shift operation using loop.
 
@@ -26,7 +26,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 187ad522dcc..8f9baec826b 100644
+index 55477fd0a69..f85d8fcac8a 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1618,6 +1618,27 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
index 0c865224..3ee98b39 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -1,7 +1,7 @@
-From 386b8dcef2d774e9138515814be0fd579ade5af5 Mon Sep 17 00:00:00 2001
+From 3ace42f94961162022e9e7baf3e3509fc1a1bfa4 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:04:37 +0530
-Subject: [PATCH 16/54] [Patch, microblaze]: Add cbranchsi4_reg This patch
+Subject: [PATCH 16/53] [Patch, microblaze]: Add cbranchsi4_reg This patch
  optimizes the generation of  pcmpne/pcmpeq instruction if the compare
  instruction has no immediate values.For the immediate values the xor
  instruction is generated
@@ -30,7 +30,7 @@ Conflicts:
  7 files changed, 18 insertions(+), 18 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 982b2abd2d4..c2f88813a8d 100644
+index 54c26969fbd..3a5f439703c 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
 @@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
index 504083f3..dcc8b6af 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -1,7 +1,7 @@
-From b6298861681965533c9b6dac5e26fbd62b52839d Mon Sep 17 00:00:00 2001
+From 2c68b0e5e0307019207e54d1f2d1565053f2e50f Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 17:11:04 +0530
-Subject: [PATCH 17/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
+Subject: [PATCH 17/53] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
  The changes are made in the patch for the inline expansion of the fsqrt
  builtin with fqrt instruction. The sqrt math function takes double as
  argument and return double as argument. The pattern is selected while
@@ -29,7 +29,7 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
  1 file changed, 14 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8f9baec826b..986d9c3aa25 100644
+index f85d8fcac8a..254221482af 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -451,6 +451,20 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
index 14095d83..4aa51cc9 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -1,7 +1,7 @@
-From a8c6c13cc322ecc300bb2cdf22e3d6f1680e56be Mon Sep 17 00:00:00 2001
+From 9eb2e41cedc278eb16e20383b6c8caad2ce22138 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:07:24 +0530
-Subject: [PATCH 18/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
+Subject: [PATCH 18/53] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
  insn definitions Change adddi3 to handle DI immediates as the second operand,
  this requires modification to the output template however reduces the need to
  specify seperate templates for 16-bit positive/negative immediate operands.
@@ -23,7 +23,7 @@ Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
  1 file changed, 6 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 986d9c3aa25..efd2c34e0b7 100644
+index 254221482af..d86a049355a 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -502,17 +502,16 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
index 4a490119..b67d8424 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -1,7 +1,7 @@
-From 3a9ee185eb462f880ceb4ddd125d4a98e0759873 Mon Sep 17 00:00:00 2001
+From abef7f4d2ad2869c37c4fb2666b52ed700384877 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 17 Jan 2017 18:18:41 +0530
-Subject: [PATCH 19/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns
+Subject: [PATCH 19/53] [Patch, microblaze]: Update ashlsi3 & movsf patterns
  This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
  of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
  patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
@@ -27,7 +27,7 @@ ChangeLog:
  2 files changed, 9 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 9eae5515c60..0a4619eec0c 100644
+index 62630aab64e..16f3120e415 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2468,7 +2468,7 @@ print_operand (FILE * file, rtx op, int letter)
@@ -40,7 +40,7 @@ index 9eae5515c60..0a4619eec0c 100644
        else
         {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index efd2c34e0b7..be8bbda2bfb 100644
+index d86a049355a..986c78f592a 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1368,7 +1368,10 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
index 07cf635d..3e19f449 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -1,7 +1,7 @@
-From bfdb38133201f7df01d09dc7e7ee3043a35c1d3e Mon Sep 17 00:00:00 2001
+From 39d009f82d0fc316b633a717f173b6195316c8ed Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 9 Nov 2020 19:54:39 +0530
-Subject: [PATCH 20/54] [Patch, microblaze]: 8-stage pipeline for microblaze
+Subject: [PATCH 20/53] [Patch, microblaze]: 8-stage pipeline for microblaze
 
 This patch adds the support for the 8-stage pipeline. The new 8-stage
 pipeline reduces the latencies of float & integer division drastically
@@ -15,7 +15,7 @@ Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
  4 files changed, 94 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0a4619eec0c..0dc96e481b7 100644
+index 16f3120e415..c730faa9814 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -1840,6 +1840,17 @@ microblaze_option_override (void)
@@ -37,7 +37,7 @@ index 0a4619eec0c..0dc96e481b7 100644
    if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
      error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8aa3f155790..8a668278337 100644
+index e32ce7dbb51..21560ec1618 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -27,7 +27,8 @@
@@ -51,7 +51,7 @@ index 8aa3f155790..8a668278337 100644
  
  #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index be8bbda2bfb..c407a81c51e 100644
+index 986c78f592a..ce72acb9ee0 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -35,6 +35,7 @@
@@ -162,7 +162,7 @@ index be8bbda2bfb..c407a81c51e 100644
    (set_attr "length"    "4")])
  
 diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index 725c2fab52a..a29c6f8df90 100644
+index 8dfb134b315..2a72566372b 100644
 --- a/gcc/config/microblaze/microblaze.opt
 +++ b/gcc/config/microblaze/microblaze.opt
 @@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
index f362cea8..4ef976b7 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -1,7 +1,7 @@
-From af01da22797795408d45dcf03076dc8153c7029e Mon Sep 17 00:00:00 2001
+From 1c93b2ce88766f74f1f6d7e0235ffff0b7ca7b81 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 9 Nov 2020 21:14:54 +0530
-Subject: [PATCH 21/54] [Patch, microblaze]: Correct the const high double
+Subject: [PATCH 21/53] [Patch, microblaze]: Correct the const high double
  immediate value with this patch the loading of the DI mode immediate values
  will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
  functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
@@ -16,7 +16,7 @@ Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
  create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0dc96e481b7..5d395f047f7 100644
+index c730faa9814..3b1e992fa28 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2452,14 +2452,16 @@ print_operand (FILE * file, rtx op, int letter)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
index 3faef052..58c4a146 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -1,7 +1,7 @@
-From 7349def8102c09fd09e735daa9fc890bee323e79 Mon Sep 17 00:00:00 2001
+From 808c5fecf0eab33e4cb66fb5170b9bf114dbc320 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 11:49:58 +0530
-Subject: [PATCH 22/54] [Fix, microblaze]: Fix internal compiler error with
+Subject: [PATCH 22/53] [Fix, microblaze]: Fix internal compiler error with
  msmall-divides This patch will fix the internal error
  microblaze_expand_divide function which comes because of rtx PLUS where the
  mem_rtx is of type SI and the operand is of type QImode. This patch modifies
@@ -19,7 +19,7 @@ ChangeLog:
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 5d395f047f7..29b2f6b016b 100644
+index 3b1e992fa28..94aaeaa3a67 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3767,7 +3767,7 @@ microblaze_expand_divide (rtx operands[])
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
index 1c4f8ca9..62f8f5e5 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -1,7 +1,7 @@
-From ad3d0a29a4895351008ce959138c13b8f5924464 Mon Sep 17 00:00:00 2001
+From e6f5b2ba1c03ac3d0521291beb64d64a125e1481 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 18 Jan 2017 12:03:39 +0530
-Subject: [PATCH 23/54] [patch,microblaze]: Fix the calculation of high word in
+Subject: [PATCH 23/53] [patch,microblaze]: Fix the calculation of high word in
  a long long 6. .4-bit
 
 This patch will change the calculation of high word in a long long 64-bit.
@@ -27,7 +27,7 @@ ChangeLog:
  1 file changed, 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 29b2f6b016b..4710def18cf 100644
+index 94aaeaa3a67..84e17fc4520 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2468,9 +2468,6 @@ print_operand (FILE * file, rtx op, int letter)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-MicroBlaze-this-patch-has.patch
index da24f113..c5c9f416 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-MicroBlaze-this-patch-has.patch
@@ -1,21 +1,30 @@
-From cb67b2e64c0d5bd32d36cb32def5f889122fc37a Mon Sep 17 00:00:00 2001
+From 5b81fec66287856abfe7def27e245fe73e60fe5e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:42:10 +0530
-Subject: [PATCH 25/54] [Patch, microblaze]: Fix bug in MB version calculation
- This patch fixes the bug in microblaze_version_to_int function. Earlier the
- conversion of vXX.YY.Z to int has a bug which is fixed now.
+Date: Tue, 26 Oct 2021 21:11:21 +0530
+Subject: [PATCH 24/53] [Patch,MicroBlaze] : this patch has 1.Fixed the bug in
+ version calculation. 2.Add new bitfield instructions.
 
-Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
-                Nagaraju Mekala <nmekala@xilix.com>
 ---
- gcc/config/microblaze/microblaze.c | 147 ++++++++++++++---------------
- 1 file changed, 70 insertions(+), 77 deletions(-)
+ gcc/config/microblaze/microblaze.c  | 154 ++++++++++++++--------------
+ gcc/config/microblaze/microblaze.h  |   2 +
+ gcc/config/microblaze/microblaze.md |  69 +++++++++++++
+ 3 files changed, 147 insertions(+), 78 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 14c652325a8..451db9c79b0 100644
+index 84e17fc4520..9f94d015597 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
-@@ -242,6 +242,63 @@ section *sdata2_section;
+@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn.  */
+ int microblaze_has_clz = 0;
+ 
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
+    version having only a particular type of pipeline. There can still be 
+    options on the CPU to scale pipeline features up or down. :( 
+@@ -239,6 +242,63 @@ section *sdata2_section;
  #define TARGET_HAVE_TLS true
  #endif
  
@@ -79,7 +88,7 @@ index 14c652325a8..451db9c79b0 100644
  /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
  static bool
  microblaze_const_double_ok (rtx op, machine_mode mode)
-@@ -1341,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+@@ -1338,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
        {
         if (TARGET_BARREL_SHIFT)
           {
@@ -89,7 +98,7 @@ index 14c652325a8..451db9c79b0 100644
               *total = COSTS_N_INSNS (1);
             else
               *total = COSTS_N_INSNS (2);
-@@ -1403,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+@@ -1400,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
           }
         else if (!TARGET_SOFT_MUL)
           {
@@ -99,7 +108,7 @@ index 14c652325a8..451db9c79b0 100644
               *total = COSTS_N_INSNS (1);
             else
               *total = COSTS_N_INSNS (3);
-@@ -1677,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
+@@ -1674,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
    return 0;
  }
  
@@ -173,7 +182,7 @@ index 14c652325a8..451db9c79b0 100644
  
    microblaze_section_threshold = (global_options_set.x_g_switch_value
                                   ? g_switch_value
-@@ -1763,13 +1759,13 @@ microblaze_option_override (void)
+@@ -1760,13 +1759,13 @@ microblaze_option_override (void)
    /* Check the MicroBlaze CPU version for any special action to be done.  */
    if (microblaze_select_cpu == NULL)
      microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
@@ -190,7 +199,7 @@ index 14c652325a8..451db9c79b0 100644
    if (ver < 0)
      {
        /* No hardware exceptions in earlier versions. So no worries.  */
-@@ -1780,8 +1776,7 @@ microblaze_option_override (void)
+@@ -1777,8 +1776,7 @@ microblaze_option_override (void)
        microblaze_pipe = MICROBLAZE_PIPE_3;
      }
    else if (ver == 0
@@ -200,7 +209,7 @@ index 14c652325a8..451db9c79b0 100644
      {
  #if 0
        microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
-@@ -1798,11 +1793,9 @@ microblaze_option_override (void)
+@@ -1795,11 +1793,9 @@ microblaze_option_override (void)
  #endif
        microblaze_no_unsafe_delay = 0;
        microblaze_pipe = MICROBLAZE_PIPE_5;
@@ -215,7 +224,7 @@ index 14c652325a8..451db9c79b0 100644
         {
           /* Pattern compares are to be turned on by default only when 
              compiling for MB v5.00.'z'.  */
-@@ -1810,7 +1803,7 @@ microblaze_option_override (void)
+@@ -1807,7 +1803,7 @@ microblaze_option_override (void)
         }
      }
  
@@ -224,7 +233,7 @@ index 14c652325a8..451db9c79b0 100644
    if (ver < 0)
      {
        if (TARGET_MULTIPLY_HIGH)
-@@ -1819,7 +1812,7 @@ microblaze_option_override (void)
+@@ -1816,7 +1812,7 @@ microblaze_option_override (void)
                  "%<-mcpu=v6.00.a%> or greater");
      }
  
@@ -233,7 +242,7 @@ index 14c652325a8..451db9c79b0 100644
    microblaze_has_clz = 1;
    if (ver < 0)
      {
-@@ -1828,7 +1821,7 @@ microblaze_option_override (void)
+@@ -1825,7 +1821,7 @@ microblaze_option_override (void)
      }
  
    /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
@@ -242,6 +251,122 @@ index 14c652325a8..451db9c79b0 100644
    if (ver < 0)
      {
          if (TARGET_REORDER == 1)
+@@ -1840,7 +1836,7 @@ microblaze_option_override (void)
+                   "%<-mcpu=v8.30.a%>");
+         TARGET_REORDER = 0;
+     }
+-  ver = microblaze_version_to_int("v10.0");
++  ver = ver_int - microblaze_version_to_int("v10.0");
+   if (ver < 0)
+     {
+         if (TARGET_AREA_OPTIMIZED_2)
+@@ -1850,6 +1846,8 @@ microblaze_option_override (void)
+     {
+         if (TARGET_AREA_OPTIMIZED_2)
+           microblaze_pipe = MICROBLAZE_PIPE_8;
++        if (TARGET_BARREL_SHIFT)
++          microblaze_has_bitfield = 1;
+     }
+ 
+   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 21560ec1618..6aac8a6cc2a 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
+ 
+ extern int microblaze_no_unsafe_delay;
+ extern int microblaze_has_clz;
++extern int microblaze_has_bitfield;
+ extern enum pipeline_type microblaze_pipe;
+ 
+ #define OBJECT_FORMAT_ELF
+@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe;
+ /* Do we have CLZ?  */
+ #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
+ 
++#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
+ /* The default is to support PIC.  */
+ #define TARGET_SUPPORTS_PIC 1
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index ce72acb9ee0..fc3326b2314 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2489,4 +2489,73 @@
+   DONE;
+ }")
+ 
++(define_expand "extvsi"
++  [(set (match_operand:SI 0 "register_operand" "r")
++       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++                        (match_operand:SI 2 "immediate_operand" "I")
++                        (match_operand:SI 3 "immediate_operand" "I")))]
++"TARGET_HAS_BITFIELD"
++"
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++  if ((len == 0) || (pos + len > 32) )
++    FAIL;
++
++  ;;if (!register_operand (operands[1], VOIDmode))
++  ;;  FAIL;
++  if (operands[0] == operands[1])
++  FAIL;
++  if (GET_CODE (operands[1]) == ASHIFT)
++  FAIL;
++;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++                         operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "extv_32"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++                        (match_operand:SI 2 "immediate_operand" "I")
++                        (match_operand:SI 3 "immediate_operand" "I")))]
++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
++   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
++  "bsefi %0,%1,%2,%3"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
++(define_expand "insvsi"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++                        (match_operand:SI 1 "immediate_operand" "I")
++                        (match_operand:SI 2 "immediate_operand" "I"))
++       (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD"
++  "
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++  if (len <= 0 || pos + len > 32)
++    FAIL;
++
++  ;;if (!register_operand (operands[0], VOIDmode))
++  ;;  FAIL;
++  emit_insn (gen_insv_32 (operands[0], operands[1],
++                         operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "insv_32"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++                        (match_operand:SI 1 "immediate_operand" "I")
++                        (match_operand:SI 2 "immediate_operand" "I"))
++       (match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
++   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
++  "bsifi %0, %3, %1, %2"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
+ (include "sync.md")
 -- 
 2.17.1
 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
deleted file mode 100644
index 590cb38c..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
+++ /dev/null
@@ -1,162 +0,0 @@
-From 50f5f8341ba39f2e12eef4a149e59f71f032f7d3 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 10 Nov 2020 09:51:24 +0530
-Subject: [PATCH 24/54] [Patch, microblaze]: Add new bit-field instructions
-
-This patches adds new bsefi and bsifi instructions.
-BSEFI- The instruction shall extract a bit field from a
-register and place it right-adjusted in the destination register.
-The other bits in the destination register shall be set to zero
-BSIFI- The instruction shall insert a right-adjusted bit field
-from a register at another position in the destination register.
-The rest of the bits in the destination register shall be unchanged
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c  |  5 ++
- gcc/config/microblaze/microblaze.h  |  2 +
- gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++
- 3 files changed, 80 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 4710def18cf..14c652325a8 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
- /* Set to one if the targeted core has the CLZ insn.  */
- int microblaze_has_clz = 0;
- 
-+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
-+int microblaze_has_bitfield = 0;
-+
- /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
-    version having only a particular type of pipeline. There can still be 
-    options on the CPU to scale pipeline features up or down. :( 
-@@ -1850,6 +1853,8 @@ microblaze_option_override (void)
-     {
-         if (TARGET_AREA_OPTIMIZED_2)
-           microblaze_pipe = MICROBLAZE_PIPE_8;
-+        if (TARGET_BARREL_SHIFT)
-+          microblaze_has_bitfield = 1;
-     }
- 
-   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8a668278337..857cb1cd9d0 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
- 
- extern int microblaze_no_unsafe_delay;
- extern int microblaze_has_clz;
-+extern int microblaze_has_bitfield;
- extern enum pipeline_type microblaze_pipe;
- 
- #define OBJECT_FORMAT_ELF
-@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe;
- /* Do we have CLZ?  */
- #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
- 
-+#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
- /* The default is to support PIC.  */
- #define TARGET_SUPPORTS_PIC 1
- 
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index c407a81c51e..3e6e2b9276d 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -982,6 +982,8 @@
-   (set_attr "mode"     "DI")
-   (set_attr "length"   "20,20,20")])
- 
-+
-+
- ;;----------------------------------------------------------------
- ;; Data movement
- ;;----------------------------------------------------------------
-@@ -1776,6 +1778,7 @@
-   (set_attr "length"   "28")]
- )
- 
-+
- ;;----------------------------------------------------------------
- ;; Setting a register from an integer comparison. 
- ;;----------------------------------------------------------------
-@@ -2489,4 +2492,74 @@
-   DONE;
- }")
- 
-+(define_expand "extvsi"
-+  [(set (match_operand:SI 0 "register_operand" "r")
-+       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+                        (match_operand:SI 2 "immediate_operand" "I")
-+                        (match_operand:SI 3 "immediate_operand" "I")))]
-+""
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+                         operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "extv_32"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+       (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+                        (match_operand:SI 2 "immediate_operand" "I")
-+                        (match_operand:SI 3 "immediate_operand" "I")))]
-+ "TARGET_BARREL_SHIFT && (UINTVAL (operands[2]) > 0)
-+   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
-+  "bsefi %0,%1,%2,%3"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
-+(define_expand "insvsi"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+                        (match_operand:SI 1 "immediate_operand" "I")
-+                        (match_operand:SI 2 "immediate_operand" "I"))
-+       (match_operand:SI 3 "register_operand" "r"))]
-+ ""
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+                         operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "insv_32"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+                        (match_operand:SI 1 "immediate_operand" "I")
-+                        (match_operand:SI 2 "immediate_operand" "I"))
-+       (match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_BARREL_SHIFT && UINTVAL (operands[1]) > 0
-+   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
-+  "bsifi %0, %3, %1, %2"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
- (include "sync.md")
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Fixing-the-issue-with-the-builtin_alloc.patch
index c0719f6e..f8c438c2 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Fixing-the-issue-with-the-builtin_alloc.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0025-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -1,7 +1,7 @@
-From fdb2f23a69182da516c7bf89a9e0011e55120f94 Mon Sep 17 00:00:00 2001
+From 18f970e2dd79c67cefeeaa6634f959be19d1a6ad Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 23 Feb 2017 17:09:04 +0530
-Subject: [PATCH 26/54] Fixing the issue with the builtin_alloc. register r18
+Subject: [PATCH 25/53] Fixing the issue with the builtin_alloc. register r18
  was not properly handling the stack pattern which was resolved by using free
  available register
 
@@ -11,10 +11,10 @@ signed-off-by:nagaraju mekala <nmekala@xilinx.com>
  1 file changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 3e6e2b9276d..d938efcd762 100644
+index fc3326b2314..0b3dbdd4a70 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2078,10 +2078,10 @@
+@@ -2075,10 +2075,10 @@
    ""
    { 
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
@@ -27,7 +27,7 @@ index 3e6e2b9276d..d938efcd762 100644
      if (GET_CODE (operands[1]) != CONST_INT)
      {
          neg_op0 = gen_reg_rtx (Pmode);
-@@ -2090,9 +2090,9 @@
+@@ -2087,9 +2087,9 @@
          neg_op0 = GEN_INT (- INTVAL (operands[1]));
  
      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
index f12cea24..e895ddbd 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -1,7 +1,7 @@
-From e4f5435e6e77afe0150bf36ec9d3d055cf25a089 Mon Sep 17 00:00:00 2001
+From 45f4d3915c2194183a87ca54bd9ecf68eeccba4d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 4 Jun 2018 10:10:18 +0530
-Subject: [PATCH 28/54] [Patch,Microblaze] : Removed fsqrt generation for
+Subject: [PATCH 26/53] [Patch,Microblaze] : Removed fsqrt generation for
  double values.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 28/54] [Patch,Microblaze] : Removed fsqrt generation for
  1 file changed, 14 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 63ad94b972f..7695b105baa 100644
+index 0b3dbdd4a70..9dd12d1011b 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -526,20 +526,6 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
index d9603721..140332aa 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
@@ -1,20 +1,22 @@
-From 1a7fda96cb247bad0a4df61cd8fd3e65c0e6f35d Mon Sep 17 00:00:00 2001
+From dba8e9e148812774d94f584cdff7b6e0293081b5 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 10 Nov 2020 12:52:54 +0530
-Subject: [PATCH 29/54] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze
+Subject: [PATCH 27/53] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze
 
+Conflicts:
+        gcc/config/microblaze/microblaze.md
 ---
  gcc/config/microblaze/constraints.md      |   6 +
  gcc/config/microblaze/microblaze-protos.h |   1 +
- gcc/config/microblaze/microblaze.c        | 109 ++++--
+ gcc/config/microblaze/microblaze.c        | 109 +++++--
  gcc/config/microblaze/microblaze.h        |   4 +-
- gcc/config/microblaze/microblaze.md       | 395 +++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.md       | 352 +++++++++++++++++++++-
  gcc/config/microblaze/microblaze.opt      |   7 +-
  gcc/config/microblaze/t-microblaze        |   7 +-
- 7 files changed, 492 insertions(+), 37 deletions(-)
+ 7 files changed, 456 insertions(+), 30 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index b9fc6e3fae2..123395717e0 100644
+index b4d7ee329b8..95b21d58f88 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -52,6 +52,12 @@
@@ -31,7 +33,7 @@ index b9fc6e3fae2..123395717e0 100644
  
  (define_constraint "G"
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index c2f88813a8d..460feac4ac5 100644
+index 3a5f439703c..302f6bbda2e 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
 @@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
@@ -43,7 +45,7 @@ index c2f88813a8d..460feac4ac5 100644
  extern void print_operand (FILE *, rtx, int);
  extern void print_operand_address (FILE *, rtx);
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 451db9c79b0..99a1cd5c0be 100644
+index 9f94d015597..58d7397945e 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3432,11 +3432,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
@@ -234,7 +236,7 @@ index 451db9c79b0..99a1cd5c0be 100644
  
  static bool
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 857cb1cd9d0..c0358603380 100644
+index 6aac8a6cc2a..22fc3509319 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
@@ -263,7 +265,7 @@ index 857cb1cd9d0..c0358603380 100644
  #define FLOAT_TYPE_SIZE         32
  #define DOUBLE_TYPE_SIZE        64
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7695b105baa..4d8429d9a90 100644
+index 9dd12d1011b..3834725eec1 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -497,7 +497,6 @@
@@ -456,7 +458,7 @@ index 7695b105baa..4d8429d9a90 100644
  ;; Those for integer source operand are ordered
  ;; widest source type first.
  
-@@ -1011,6 +1122,32 @@
+@@ -1009,6 +1120,32 @@
  )
  
  
@@ -489,7 +491,7 @@ index 7695b105baa..4d8429d9a90 100644
  
  (define_insn "*movdi_internal"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
-@@ -1423,6 +1560,36 @@
+@@ -1421,6 +1558,36 @@
    (set_attr "length"   "4,4")]
  )
  
@@ -526,7 +528,7 @@ index 7695b105baa..4d8429d9a90 100644
  ;; The following patterns apply when there is no barrel shifter present
  
  (define_insn "*ashlsi3_with_mul_delay"
-@@ -1548,6 +1715,36 @@
+@@ -1546,6 +1713,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts
  ;;----------------------------------------------------------------
@@ -563,7 +565,7 @@ index 7695b105baa..4d8429d9a90 100644
  (define_expand "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -1657,6 +1854,36 @@
+@@ -1655,6 +1852,36 @@
  ;;----------------------------------------------------------------
  ;; 32-bit right shifts (logical)
  ;;----------------------------------------------------------------
@@ -600,7 +602,7 @@ index 7695b105baa..4d8429d9a90 100644
  
  (define_expand "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
-@@ -1803,6 +2030,8 @@
+@@ -1800,6 +2027,8 @@
    (set_attr "length"   "4")]
  )              
  
@@ -609,7 +611,7 @@ index 7695b105baa..4d8429d9a90 100644
  ;;----------------------------------------------------------------
  ;; Setting a register from an floating point comparison. 
  ;;----------------------------------------------------------------
-@@ -1818,6 +2047,18 @@
+@@ -1815,6 +2044,18 @@
     (set_attr "length"    "4")]
  )
  
@@ -628,7 +630,7 @@ index 7695b105baa..4d8429d9a90 100644
  ;;----------------------------------------------------------------
  ;; Conditional branches
  ;;----------------------------------------------------------------
-@@ -1930,6 +2171,115 @@
+@@ -1927,6 +2168,115 @@
     (set_attr "length"   "12")]
  )
  
@@ -744,71 +746,8 @@ index 7695b105baa..4d8429d9a90 100644
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
-@@ -2478,17 +2828,33 @@
-   DONE;
- }")
- 
--(define_expand "extzvsi"
-+(define_expand "extvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
-        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                         (match_operand:SI 2 "immediate_operand" "I")
-                         (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
--""
--)
--
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+                         operands[2], operands[3]));
-+  DONE;
-+}")
- 
--(define_insn "extzv_32"
-+(define_insn "extv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
-        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                         (match_operand:SI 2 "immediate_operand" "I")
-@@ -2505,8 +2871,21 @@
-                         (match_operand:SI 2 "immediate_operand" "I"))
-        (match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
--""
--)
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+                         operands[2], operands[3]));
-+  DONE;
-+}")
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
 diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index a29c6f8df90..bbe48b06da6 100644
+index 2a72566372b..206899c0384 100644
 --- a/gcc/config/microblaze/microblaze.opt
 +++ b/gcc/config/microblaze/microblaze.opt
 @@ -136,4 +136,9 @@ Target
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
deleted file mode 100644
index 7627b765..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 336d984c580345eccdeb889af8ef8c986afc1dad Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 19 Feb 2018 18:06:16 +0530
-Subject: [PATCH 27/54] [Patch,Microblaze]: update in constraints for bitfield
- insert and extract instructions.
-
-Conflicts:
-        gcc/config/microblaze/microblaze.md
----
- gcc/config/microblaze/microblaze.md | 45 +++++------------------------
- 1 file changed, 8 insertions(+), 37 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index d938efcd762..63ad94b972f 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2492,33 +2492,17 @@
-   DONE;
- }")
- 
--(define_expand "extvsi"
-+(define_expand "extzvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
-        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                         (match_operand:SI 2 "immediate_operand" "I")
-                         (match_operand:SI 3 "immediate_operand" "I")))]
-+"TARGET_HAS_BITFIELD"
- ""
--"
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
--
--  if ((len == 0) || (pos + len > 32) )
--    FAIL;
--
--  ;;if (!register_operand (operands[1], VOIDmode))
--  ;;  FAIL;
--  if (operands[0] == operands[1])
--  FAIL;
--  if (GET_CODE (operands[1]) == ASHIFT)
--  FAIL;
--;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-- emit_insn (gen_extv_32 (operands[0], operands[1],
--                         operands[2], operands[3]));
--  DONE;
--}")
-+)
- 
--(define_insn "extv_32"
-+
-+(define_insn "extzv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
-        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                         (match_operand:SI 2 "immediate_operand" "I")
-@@ -2534,22 +2518,9 @@
-                         (match_operand:SI 1 "immediate_operand" "I")
-                         (match_operand:SI 2 "immediate_operand" "I"))
-        (match_operand:SI 3 "register_operand" "r"))]
-- ""
--  "
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
--
--  if (len <= 0 || pos + len > 32)
--    FAIL;
--
--  ;;if (!register_operand (operands[0], VOIDmode))
--  ;;  FAIL;
--
--  emit_insn (gen_insv_32 (operands[0], operands[1],
--                         operands[2], operands[3]));
--  DONE;
--}")
-+ "TARGET_HAS_BITFIELD"
-+""
-+)
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Intial-commit-for-64bit-MB-sources.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Intial-commit-for-64bit-MB-sources.patch
index 88a0d0ba..9d38091e 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Intial-commit-for-64bit-MB-sources.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0028-Intial-commit-for-64bit-MB-sources.patch
@@ -1,7 +1,7 @@
-From 53799d63bd26a04265a55f68ca57e3462ed6eeb7 Mon Sep 17 00:00:00 2001
+From 211cfd6be4b47e1fecf95d1becb713772fd71091 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 27 Jul 2018 15:23:41 +0530
-Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
+Subject: [PATCH 28/53] Intial commit for 64bit-MB sources. Need to cleanup the
  code later.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
  gcc/config/microblaze/microblaze-c.c    |   6 +
  gcc/config/microblaze/microblaze.c      | 218 ++++++---
  gcc/config/microblaze/microblaze.h      |  63 ++-
- gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++------
+ gcc/config/microblaze/microblaze.md     | 605 ++++++++++++++++++------
  gcc/config/microblaze/t-microblaze      |   3 +-
  libgcc/config/microblaze/crti.S         |   4 +-
  libgcc/config/microblaze/crtn.S         |   4 +-
@@ -20,7 +20,7 @@ Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
  libgcc/config/microblaze/t-microblaze   |  11 +-
  libgcc/config/microblaze/udivdi3.S      | 107 +++++
  libgcc/config/microblaze/umoddi3.S      | 110 +++++
- 15 files changed, 1230 insertions(+), 234 deletions(-)
+ 15 files changed, 1230 insertions(+), 233 deletions(-)
  create mode 100644 libgcc/config/microblaze/divdi3.S
  create mode 100644 libgcc/config/microblaze/divdi3_table.c
  create mode 100644 libgcc/config/microblaze/moddi3.S
@@ -29,7 +29,7 @@ Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
  create mode 100644 libgcc/config/microblaze/umoddi3.S
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 123395717e0..b8ef1650f92 100644
+index 95b21d58f88..0a4d5269314 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -42,7 +42,7 @@ index 123395717e0..b8ef1650f92 100644
  
  ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index d8c88e510e5..dbcd21fc6ee 100644
+index e0b29bcb0b0..2dcb879992c 100644
 --- a/gcc/config/microblaze/microblaze-c.c
 +++ b/gcc/config/microblaze/microblaze-c.c
 @@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
@@ -57,7 +57,7 @@ index d8c88e510e5..dbcd21fc6ee 100644
 +    }
  }  
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 99a1cd5c0be..3c815444574 100644
+index 58d7397945e..f59a71ac072 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
@@ -575,7 +575,7 @@ index 99a1cd5c0be..3c815444574 100644
  #define TARGET_PROMOTE_FUNCTION_MODE   default_promote_function_mode_always_promote
  
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index c0358603380..f6ad4d9fc21 100644
+index 22fc3509319..94ac736221c 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
@@ -744,7 +744,7 @@ index c0358603380..f6ad4d9fc21 100644
  /* Default to -G 8 */
  #ifndef MICROBLAZE_DEFAULT_GVALUE
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 4d8429d9a90..33a8b12ef3b 100644
+index 3834725eec1..7bc91602ca2 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -26,6 +26,7 @@
@@ -1054,7 +1054,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  (define_insn "extendsidi2"
    [(set (match_operand:DI 0 "register_operand" "=d,d,d")
         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-@@ -1090,69 +1135,118 @@
+@@ -1088,69 +1133,118 @@
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
@@ -1209,7 +1209,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    { 
      switch (which_alternative)
      {
-@@ -1184,7 +1278,8 @@
+@@ -1182,7 +1276,8 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1219,7 +1219,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-@@ -1196,12 +1291,22 @@
+@@ -1194,12 +1289,22 @@
    "reload_completed 
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
@@ -1243,7 +1243,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  ;; Unlike most other insns, the move insns can't be split with
  ;; different predicates, because register spilling and other parts of
  ;; the compiler, have memoized the insn number already.
-@@ -1273,6 +1378,8 @@
+@@ -1271,6 +1376,8 @@
    (set_attr "length"   "4,4,8,4,8,4,8")])
  
  
@@ -1252,7 +1252,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  ;; 16-bit Integer moves
  
  ;; Unlike most other insns, the move insns can't be split with
-@@ -1305,8 +1412,8 @@
+@@ -1303,8 +1410,8 @@
    "@
     addik\t%0,r0,%1\t# %X1
     addk\t%0,%1,r0
@@ -1263,7 +1263,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
     sh%i0\t%z1,%0
     sh%i0\t%z1,%0"
    [(set_attr "type"    "arith,move,load,no_delay_load,store,no_delay_store")
-@@ -1349,7 +1456,7 @@
+@@ -1347,7 +1454,7 @@
     lbu%i1\t%0,%1
     lbu%i1\t%0,%1
     sb%i0\t%z1,%0
@@ -1272,7 +1272,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    [(set_attr "type"    "arith,arith,move,load,no_delay_load,store,no_delay_store")
    (set_attr "mode"     "QI")
    (set_attr "length"   "4,4,8,4,8,4,8")])
-@@ -1422,7 +1529,7 @@
+@@ -1420,7 +1527,7 @@
     addik\t%0,r0,%F1
     lw%i1\t%0,%1
     sw%i0\t%z1,%0
@@ -1281,7 +1281,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
    (set_attr "mode"      "SF")
    (set_attr "length"    "4,4,4,4,4,4,4")])
-@@ -1461,6 +1568,33 @@
+@@ -1459,6 +1566,33 @@
  ;; movdf_internal
  ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
  ;;
@@ -1315,7 +1315,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  (define_insn "*movdf_internal"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
          (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
-@@ -1495,7 +1629,8 @@
+@@ -1493,7 +1627,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1325,7 +1325,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
    (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
    "")
-@@ -1506,7 +1641,8 @@
+@@ -1504,7 +1639,8 @@
    "reload_completed
     && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
     && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
@@ -1335,7 +1335,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
    (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
    "")
-@@ -2006,6 +2142,31 @@ else
+@@ -2003,6 +2139,31 @@ else
    "
  )
  
@@ -1367,7 +1367,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  (define_insn "seq_internal_pat" 
    [(set (match_operand:SI 0 "register_operand" "=d")
         (eq:SI 
-@@ -2066,8 +2227,8 @@ else
+@@ -2063,8 +2224,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1378,7 +1378,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
                        (label_ref (match_operand 3 ""))
                        (pc)))]
    ""
-@@ -2079,13 +2240,13 @@ else
+@@ -2076,13 +2237,13 @@ else
  (define_expand "cbranchsi4_reg"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
@@ -1395,7 +1395,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    DONE;
  })
  
-@@ -2110,6 +2271,26 @@ else
+@@ -2107,6 +2268,26 @@ else
                       (label_ref (match_operand 1))
                       (pc)))])
  
@@ -1422,7 +1422,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  (define_insn "branch_zero"
    [(set (pc)
         (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-@@ -2130,6 +2311,47 @@ else
+@@ -2127,6 +2308,47 @@ else
     (set_attr "length"  "4")]
  )
  
@@ -1470,7 +1470,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2313,7 +2535,7 @@ else
+@@ -2310,7 +2532,7 @@ else
  ;; Indirect jumps. Jump to register values. Assuming absolute jumps
  
  (define_insn "indirect_jump_internal1"
@@ -1479,7 +1479,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    "bra%?\t%0"
    [(set_attr "type"    "jump")
-@@ -2326,7 +2548,7 @@ else
+@@ -2323,7 +2545,7 @@ else
    (use (label_ref (match_operand 1 "" "")))]
    ""
    {
@@ -1488,7 +1488,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
  
      if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
        emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-@@ -2338,7 +2560,7 @@ else
+@@ -2335,7 +2557,7 @@ else
  
  (define_insn "tablejump_internal1"
    [(set (pc)
@@ -1497,7 +1497,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2348,9 +2570,9 @@ else
+@@ -2345,9 +2567,9 @@ else
  
  (define_expand "tablejump_internal3"
    [(parallel [(set (pc)
@@ -1510,7 +1510,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    ""
  )
-@@ -2411,7 +2633,7 @@ else
+@@ -2408,7 +2630,7 @@ else
         (minus (reg 1) (match_operand 1 "register_operand" "")))
     (set (reg 1)
         (minus (reg 1) (match_dup 1)))]
@@ -1519,7 +1519,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    { 
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx reg = gen_reg_rtx (Pmode);
-@@ -2436,7 +2658,7 @@ else
+@@ -2433,7 +2655,7 @@ else
  (define_expand "save_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1528,7 +1528,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    {
      emit_move_insn (operands[0], operands[1]);
      DONE;
-@@ -2446,7 +2668,7 @@ else
+@@ -2443,7 +2665,7 @@ else
  (define_expand "restore_stack_block"
    [(match_operand 0 "register_operand" "")
     (match_operand 1 "register_operand" "")]
@@ -1537,7 +1537,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    {
      rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
      rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-@@ -2493,7 +2715,7 @@ else
+@@ -2490,7 +2712,7 @@ else
  
  (define_insn "<optab>_internal"
    [(any_return)
@@ -1546,7 +1546,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    {
      if (microblaze_is_break_handler ())
-@@ -2526,7 +2748,7 @@ else
+@@ -2523,7 +2745,7 @@ else
  (define_expand "call"
    [(parallel [(call (match_operand 0 "memory_operand" "m")
                     (match_operand 1 "" "i"))
@@ -1555,7 +1555,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
               (use (match_operand 2 "" ""))
               (use (match_operand 3 "" ""))])]
    ""
-@@ -2547,12 +2769,12 @@ else
+@@ -2544,12 +2766,12 @@ else
  
      if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
        emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
@@ -1570,7 +1570,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
                                      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
          DONE;
-@@ -2562,7 +2784,7 @@ else
+@@ -2559,7 +2781,7 @@ else
  (define_expand "call_internal0"
    [(parallel [(call (match_operand 0 "" "")
                     (match_operand 1 "" ""))
@@ -1579,7 +1579,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    {
    }
-@@ -2571,18 +2793,34 @@ else
+@@ -2568,18 +2790,34 @@ else
  (define_expand "call_internal_plt0"
    [(parallel [(call (match_operand 0 "" "")
                     (match_operand 1 "" ""))
@@ -1620,7 +1620,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    "flag_pic"
    {
      register rtx target2 = gen_rtx_REG (Pmode, 
-@@ -2594,10 +2832,41 @@ else
+@@ -2591,10 +2829,41 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -1664,7 +1664,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    {
      register rtx target = operands[0];
-@@ -2631,7 +2900,7 @@ else
+@@ -2628,7 +2897,7 @@ else
    [(parallel [(set (match_operand 0 "register_operand" "=d")
                    (call (match_operand 1 "memory_operand" "m")
                          (match_operand 2 "" "i")))
@@ -1673,7 +1673,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
               (use (match_operand 3 "" ""))])] ;; next_arg_reg
    ""
    {
-@@ -2652,13 +2921,13 @@ else
+@@ -2649,13 +2918,13 @@ else
      if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
        emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
                         operands[2],
@@ -1689,7 +1689,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
                                      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
  
      DONE;
-@@ -2670,7 +2939,7 @@ else
+@@ -2667,7 +2936,7 @@ else
    [(parallel [(set (match_operand 0 "" "")
                    (call (match_operand 1 "" "")
                          (match_operand 2 "" "")))
@@ -1698,7 +1698,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
               ])]
    ""
    {}
-@@ -2680,18 +2949,35 @@ else
+@@ -2677,18 +2946,35 @@ else
    [(parallel[(set (match_operand 0 "" "")
                    (call (match_operand 1 "" "")
                          (match_operand 2 "" "")))
@@ -1740,7 +1740,7 @@ index 4d8429d9a90..33a8b12ef3b 100644
    "flag_pic"
    { 
      register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-@@ -2703,11 +2989,46 @@ else
+@@ -2700,11 +2986,46 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -1789,14 +1789,6 @@ index 4d8429d9a90..33a8b12ef3b 100644
    ""
    { 
      register rtx target = operands[1];
-@@ -2881,7 +3202,6 @@ else
- 
-   ;;if (!register_operand (operands[0], VOIDmode))
-   ;;  FAIL;
--
-   emit_insn (gen_insv_32 (operands[0], operands[1],
-                          operands[2], operands[3]));
-   DONE;
 diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
 index e9a1921ae26..9fc80b142ce 100644
 --- a/gcc/config/microblaze/t-microblaze
@@ -1812,7 +1804,7 @@ index e9a1921ae26..9fc80b142ce 100644
  MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
  MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
 diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index d0146083db6..005825f1ec5 100644
+index f9bafaf3aa5..bc69d890370 100644
 --- a/libgcc/config/microblaze/crti.S
 +++ b/libgcc/config/microblaze/crti.S
 @@ -40,7 +40,7 @@
@@ -1832,7 +1824,7 @@ index d0146083db6..005825f1ec5 100644
 +    addik   r1, r1, -16
      sw      r15, r0, r1
 diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 2fff5ac04c7..5705eff9a4a 100644
+index 0260e432371..1a1f0a8e0f3 100644
 --- a/libgcc/config/microblaze/crtn.S
 +++ b/libgcc/config/microblaze/crtn.S
 @@ -33,9 +33,9 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-re-arrangement-of-the-compare-branches.patch
index 0113c65d..19605270 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-re-arrangement-of-the-compare-branches.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0029-re-arrangement-of-the-compare-branches.patch
@@ -1,7 +1,7 @@
-From 67d89be9ace8f658354fb1378e986451ef435d60 Mon Sep 17 00:00:00 2001
+From 5b31cd986c75c5f479967b8f9c1b4ac1fc322b1a Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 3 Aug 2018 15:41:39 +0530
-Subject: [PATCH 31/54] re-arrangement of the compare branches
+Subject: [PATCH 29/53] re-arrangement of the compare branches
 
 ---
  gcc/config/microblaze/microblaze.c  |  28 ++----
@@ -9,7 +9,7 @@ Subject: [PATCH 31/54] re-arrangement of the compare branches
  2 files changed, 73 insertions(+), 96 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 3c815444574..046bfd05558 100644
+index f59a71ac072..e33e1bc1482 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3697,11 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
@@ -83,10 +83,10 @@ index 3c815444574..046bfd05558 100644
  
  /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 33a8b12ef3b..cfe9e5312d1 100644
+index 7bc91602ca2..ddf01505bd8 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2271,7 +2271,27 @@ else
+@@ -2268,7 +2268,27 @@ else
                       (label_ref (match_operand 1))
                       (pc)))])
  
@@ -115,7 +115,7 @@ index 33a8b12ef3b..cfe9e5312d1 100644
    [(set (pc)
         (if_then_else (match_operator 0 "ordered_comparison_operator"
                                  [(match_operand 1 "register_operand" "d")
-@@ -2282,9 +2302,9 @@ else
+@@ -2279,9 +2299,9 @@ else
    "TARGET_MB_64"
    {
      if (operands[3] == pc_rtx) 
@@ -127,7 +127,7 @@ index 33a8b12ef3b..cfe9e5312d1 100644
    }
    [(set_attr "type"    "branch")
     (set_attr "mode"    "none")
-@@ -2313,9 +2333,9 @@ else
+@@ -2310,9 +2330,9 @@ else
  
  (define_insn "branch_compare64"
    [(set (pc)
@@ -140,7 +140,7 @@ index 33a8b12ef3b..cfe9e5312d1 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2352,6 +2372,47 @@ else
+@@ -2349,6 +2369,47 @@ else
     (set_attr "length"   "12")]
  )
  
@@ -188,7 +188,7 @@ index 33a8b12ef3b..cfe9e5312d1 100644
  (define_insn "branch_compare"
    [(set (pc)
          (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2434,74 +2495,6 @@ else
+@@ -2431,74 +2492,6 @@ else
  
  })
  
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch
index b74c79ec..528fef0c 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -1,7 +1,7 @@
-From 410348f4fd9b641afa24e6c6b6a62a4c74d18862 Mon Sep 17 00:00:00 2001
+From 37af05f1ea7dc8476057580944a236f135babaf8 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 8 Aug 2018 17:37:26 +0530
-Subject: [PATCH 32/54] [Patch,Microblaze] :  previous commit broke the
+Subject: [PATCH 30/53] [Patch,Microblaze] :  previous commit broke the
  handling of SI Branch compare for Microblaze 32-bit..
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 32/54] [Patch,Microblaze] :  previous commit broke the
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index cfe9e5312d1..592757baf2f 100644
+index ddf01505bd8..87158066562 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2227,8 +2227,8 @@ else
+@@ -2224,8 +2224,8 @@ else
  (define_expand "cbranchsi4"
    [(set (pc)
          (if_then_else (match_operator 0 "ordered_comparison_operator"
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch
index 353bfa90..c247120b 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -1,7 +1,7 @@
-From 802c136f1a41ebfed3b25419e48331038f284e2b Mon Sep 17 00:00:00 2001
+From 397a532bd80e21682ca3b5e230949f66c5b9ad30 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 11 Sep 2018 13:43:48 +0530
-Subject: [PATCH 33/54] [Patch, Microblaze] : Support of multilibs with m64 ...
+Subject: [PATCH 31/53] [Patch, Microblaze] : Support of multilibs with m64 ...
 
 ---
  gcc/config/microblaze/microblaze-c.c  |  1 +
@@ -10,7 +10,7 @@ Subject: [PATCH 33/54] [Patch, Microblaze] : Support of multilibs with m64 ...
  3 files changed, 10 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index dbcd21fc6ee..db543edcbe5 100644
+index 2dcb879992c..50d01feb670 100644
 --- a/gcc/config/microblaze/microblaze-c.c
 +++ b/gcc/config/microblaze/microblaze-c.c
 @@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Fixed-issues-like.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Fixed-issues-like.patch
index c508b158..9f5381af 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Fixed-issues-like.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0032-Fixed-issues-like.patch
@@ -1,7 +1,7 @@
-From 2b2c6e96c3aefc86c880be05d93685a4ce97c9f1 Mon Sep 17 00:00:00 2001
+From c03a994475d8894ae0913dd3534e72bfb389aa28 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 11 Sep 2018 14:58:00 +0530
-Subject: [PATCH 34/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
+Subject: [PATCH 32/53] Fixed issues like: 1 Interrupt alignment issue 2 Sign
  extension issue
 
 ---
@@ -10,7 +10,7 @@ Subject: [PATCH 34/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
  2 files changed, 11 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 046bfd05558..498c8ca191f 100644
+index e33e1bc1482..64b948d6cfc 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2177,9 +2177,14 @@ compute_frame_size (HOST_WIDE_INT size)
@@ -53,7 +53,7 @@ index 046bfd05558..498c8ca191f 100644
    else if (code == CONST_DOUBLE)
      {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 592757baf2f..e7c7cf3e8b5 100644
+index 87158066562..b154d15c34c 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1096,7 +1096,7 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-below-issues.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Fixed-below-issues.patch
index 61d35261..3a4b2037 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-below-issues.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0033-Fixed-below-issues.patch
@@ -1,7 +1,7 @@
-From 051d744c06ed3f11f603e37768eece57784c2583 Mon Sep 17 00:00:00 2001
+From 844daa118a8f376e5a53040fc953c86e70d34140 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 26 Nov 2019 17:26:15 +0530
-Subject: [PATCH 35/54] Fixed below issues:
+Subject: [PATCH 33/53] Fixed below issues:
 
 - Floating point print issues in 64bit mode
 - Dejagnu Jump related issues
@@ -18,7 +18,7 @@ Conflicts:
  5 files changed, 125 insertions(+), 17 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 498c8ca191f..e32de46fa62 100644
+index 64b948d6cfc..b2cd89a310a 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2473,7 +2473,12 @@ print_operand (FILE * file, rtx op, int letter)
@@ -48,7 +48,7 @@ index 498c8ca191f..e32de46fa62 100644
    LABEL_NUSES (div_end_label) = 1; 
    emit_barrier ();
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index f6ad4d9fc21..60c552958b8 100644
+index 94ac736221c..17bf470c95b 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -888,10 +888,17 @@ do {                                                                       \
@@ -70,7 +70,7 @@ index f6ad4d9fc21..60c552958b8 100644
  /* We need to group -lm as well, since some Newlib math functions 
     reference __errno!  */
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index e7c7cf3e8b5..74bb30cb9e8 100644
+index b154d15c34c..7d6cf263eb6 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -527,6 +527,15 @@
@@ -89,7 +89,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
  (define_insn "fix_truncsfsi2"
    [(set (match_operand:SI 0 "register_operand" "=d")
          (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-@@ -1301,7 +1310,7 @@
+@@ -1299,7 +1308,7 @@
  (define_insn "movdi_long_int"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
         (match_operand:DI 1 "general_operand"      "i"))]
@@ -98,7 +98,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
    "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
    [(set_attr "type"    "no_delay_arith")
    (set_attr "mode"     "DI")
-@@ -1584,7 +1593,7 @@
+@@ -1582,7 +1591,7 @@
            return "ll%i1\t%0,%1";
        case 3:
        {
@@ -107,7 +107,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
        }
        case 5:
         return "sl%i0\t%1,%0";
-@@ -2374,9 +2383,9 @@ else
+@@ -2371,9 +2380,9 @@ else
  
  (define_insn "long_branch_compare"
    [(set (pc)
@@ -120,7 +120,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
                                           ])
                        (label_ref (match_operand 3))
                        (pc)))
-@@ -2498,6 +2507,20 @@ else
+@@ -2495,6 +2504,20 @@ else
  ;;----------------------------------------------------------------
  ;; Unconditional branches
  ;;----------------------------------------------------------------
@@ -141,7 +141,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
  (define_insn "jump"
    [(set (pc)
         (label_ref (match_operand 0 "" "")))]
-@@ -2543,17 +2566,25 @@ else
+@@ -2540,17 +2563,25 @@ else
    {
      //gcc_assert (GET_MODE (operands[0]) == Pmode);
  
@@ -172,7 +172,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
    (use (label_ref (match_operand 1 "" "")))]
    ""
    "bra%?\t%0 "
-@@ -2561,11 +2592,21 @@ else
+@@ -2558,11 +2589,21 @@ else
    (set_attr "mode"     "none")
    (set_attr "length"   "4")])
  
@@ -197,7 +197,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
    ""
    ""
  )
-@@ -2596,6 +2637,23 @@ else
+@@ -2593,6 +2634,23 @@ else
    ""
  )
  
@@ -221,7 +221,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
  ;;----------------------------------------------------------------
  ;; Function prologue/epilogue and stack allocation
  ;;----------------------------------------------------------------
-@@ -3102,7 +3160,7 @@ else
+@@ -3099,7 +3157,7 @@ else
  ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
  ;; between "mfs" and "addik" instructions.
  (define_insn "set_got"
@@ -231,7 +231,7 @@ index e7c7cf3e8b5..74bb30cb9e8 100644
    ""
    "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
 diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 005825f1ec5..b7436c7131f 100644
+index bc69d890370..7400eeb2e3b 100644
 --- a/libgcc/config/microblaze/crti.S
 +++ b/libgcc/config/microblaze/crti.S
 @@ -33,11 +33,32 @@
@@ -274,7 +274,7 @@ index 005825f1ec5..b7436c7131f 100644
      sw      r15, r0, r1
 +#endif
 diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 5705eff9a4a..f1148ffebe4 100644
+index 1a1f0a8e0f3..14d9a084e3e 100644
 --- a/libgcc/config/microblaze/crtn.S
 +++ b/libgcc/config/microblaze/crtn.S
 @@ -29,7 +29,19 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Added-double-arith-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Added-double-arith-instructions.patch
index 3f52e879..293c9f90 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Added-double-arith-instructions.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0034-Added-double-arith-instructions.patch
@@ -1,7 +1,7 @@
-From 2bb5cef1a85d63ebf155bcb0070492b0ad298dd8 Mon Sep 17 00:00:00 2001
+From 93874549e864b39689060edda456c897ea0fac4e Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 9 Oct 2018 10:07:08 +0530
-Subject: [PATCH 36/54] -Added double arith instructions -Fixed prologue stack
+Subject: [PATCH 34/53] -Added double arith instructions -Fixed prologue stack
  pointer decrement issue
 
 ---
@@ -10,7 +10,7 @@ Subject: [PATCH 36/54] -Added double arith instructions -Fixed prologue stack
  2 files changed, 76 insertions(+), 9 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 74bb30cb9e8..1401d6b77ff 100644
+index 7d6cf263eb6..943037336f1 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -527,6 +527,66 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
index 2253b759..6135b952 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -1,7 +1,7 @@
-From 2feba7c8902be8d5c4cc99feca0581472c16de0c Mon Sep 17 00:00:00 2001
+From 8c359136e4b5ca105946b259212ed4bac0a69a9e Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 12 Oct 2018 16:07:36 +0530
-Subject: [PATCH 37/54] Fixed the issue in the delay slot with swap
+Subject: [PATCH 35/53] Fixed the issue in the delay slot with swap
  instructions
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 37/54] Fixed the issue in the delay slot with swap
  1 file changed, 6 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 1401d6b77ff..a91108cf0e5 100644
+index 943037336f1..162c6231a86 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -443,6 +443,9 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
index 57905e66..23b640a6 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -1,7 +1,7 @@
-From 10d59c50195cff30c4e74959ef4cebc9065808a4 Mon Sep 17 00:00:00 2001
+From 08ca1c1550145a8bddbd03a594620db13a259238 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Sat, 13 Oct 2018 21:12:43 +0530
-Subject: [PATCH 38/54] Fixed the load store issue with the 32bit arith
+Subject: [PATCH 36/53] Fixed the load store issue with the 32bit arith
  libraries
 
 ---
@@ -13,7 +13,7 @@ Subject: [PATCH 38/54] Fixed the load store issue with the 32bit arith
  5 files changed, 98 insertions(+), 4 deletions(-)
 
 diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index bb047094e2f..104243e35fe 100644
+index 886a4f2bb36..3a7fc4d6122 100644
 --- a/libgcc/config/microblaze/divsi3.S
 +++ b/libgcc/config/microblaze/divsi3.S
 @@ -41,6 +41,17 @@
@@ -70,7 +70,7 @@ index bb047094e2f..104243e35fe 100644
         .size   __divsi3, . - __divsi3
  
 diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 9692ff310ff..9500d64bdc0 100644
+index 2c4f39a045f..3e405ea6267 100644
 --- a/libgcc/config/microblaze/modsi3.S
 +++ b/libgcc/config/microblaze/modsi3.S
 @@ -41,6 +41,17 @@
@@ -128,7 +128,7 @@ index 9692ff310ff..9500d64bdc0 100644
         .size   __modsi3, . - __modsi3
  
 diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index cb3b6b8321f..2044399db4a 100644
+index c50a380177a..0329fa3037a 100644
 --- a/libgcc/config/microblaze/mulsi3.S
 +++ b/libgcc/config/microblaze/mulsi3.S
 @@ -41,6 +41,9 @@
@@ -142,7 +142,7 @@ index cb3b6b8321f..2044399db4a 100644
         .frame  r1,0,r15
         add     r3,r0,r0
 diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index ee2bdd0950d..d2332bcfe62 100644
+index 1bf73265b98..7bdcd8873e5 100644
 --- a/libgcc/config/microblaze/udivsi3.S
 +++ b/libgcc/config/microblaze/udivsi3.S
 @@ -41,6 +41,16 @@
@@ -197,7 +197,7 @@ index ee2bdd0950d..d2332bcfe62 100644
          .end __udivsi3
         .size   __udivsi3, . - __udivsi3
 diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 12c082f6417..30bd8c20b58 100644
+index 2bc0909605f..7d1e4484a53 100644
 --- a/libgcc/config/microblaze/umodsi3.S
 +++ b/libgcc/config/microblaze/umodsi3.S
 @@ -41,6 +41,16 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch
index 8f46859a..3f0ec920 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -1,14 +1,14 @@
-From e51fb2d87f412d1f7045050c5c2df664766de706 Mon Sep 17 00:00:00 2001
+From 3fbf3d7049cccb5ddec02e3360f1b4da0eb5a177 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Mon, 15 Oct 2018 12:00:10 +0530
-Subject: [PATCH 39/54] extending the Dwarf support to 64bit Microblaze
+Subject: [PATCH 37/53] extending the Dwarf support to 64bit Microblaze
 
 ---
  gcc/config/microblaze/microblaze.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 60c552958b8..747adcc7a70 100644
+index 17bf470c95b..b0c44c4fd50 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-fixing-the-typo-errors-in-umodsi3-file.patch
index e7e581e3..0f91a572 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-fixing-the-typo-errors-in-umodsi3-file.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0038-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -1,14 +1,14 @@
-From 61be4b342d470aeb7ad1c0cc5e90f5afdc906c00 Mon Sep 17 00:00:00 2001
+From 23c8d1d396c7ae5e478c793b72fddcec80dfd083 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Tue, 16 Oct 2018 07:55:46 +0530
-Subject: [PATCH 40/54] fixing the typo errors in umodsi3 file
+Subject: [PATCH 38/53] fixing the typo errors in umodsi3 file
 
 ---
  libgcc/config/microblaze/umodsi3.S | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
 
 diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 30bd8c20b58..2dd72aef68e 100644
+index 7d1e4484a53..63ab1c2a357 100644
 --- a/libgcc/config/microblaze/umodsi3.S
 +++ b/libgcc/config/microblaze/umodsi3.S
 @@ -47,9 +47,9 @@ __umodsi3:
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch
index 9f9afdb9..6aa6937f 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -1,14 +1,14 @@
-From b1eb7b1f6c33246ded3501364279a5f002cd8de0 Mon Sep 17 00:00:00 2001
+From cc2c7e5255edc97064d29880f156d603d3ec740a Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 41/54] fixing the 32bit LTO related issue9(1014024)
+Subject: [PATCH 39/53] fixing the 32bit LTO related issue9(1014024)
 
 ---
  gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
  1 file changed, 14 insertions(+), 10 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 747adcc7a70..bfa7bc9a01c 100644
+index b0c44c4fd50..c6c3a9baa5a 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
index fb31d663..e086a851 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -1,7 +1,7 @@
-From e0820fe8c8d9b7504595794fe6e65151d22e2acf Mon Sep 17 00:00:00 2001
+From 7d245c4d22c5c845666f33f19d23c075dcae2af6 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 19 Oct 2018 14:26:25 +0530
-Subject: [PATCH 42/54] Fixed the missing stack adjustment in prologue of
+Subject: [PATCH 40/53] Fixed the missing stack adjustment in prologue of
  modsi3 function
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 42/54] Fixed the missing stack adjustment in prologue of
  1 file changed, 1 insertion(+)
 
 diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 9500d64bdc0..4dbb25900d9 100644
+index 3e405ea6267..c98442c01c2 100644
 --- a/libgcc/config/microblaze/modsi3.S
 +++ b/libgcc/config/microblaze/modsi3.S
 @@ -119,6 +119,7 @@ $LaRETURN_HERE:
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
index ce8b1384..b3b04ae7 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -1,7 +1,7 @@
-From 1f288ec920d938accb084dc0d1d6f6115950c014 Mon Sep 17 00:00:00 2001
+From 4de570fde0740cbcfea443aea24c2cfc9df5a876 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 24 Oct 2018 18:31:04 +0530
-Subject: [PATCH 43/54] [Patch,Microblaze] : corrected SPN for dlong
+Subject: [PATCH 41/53] [Patch,Microblaze] : corrected SPN for dlong
  instruction mapping.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 43/54] [Patch,Microblaze] : corrected SPN for dlong
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a91108cf0e5..19801f8edcc 100644
+index 162c6231a86..f62ad28130b 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -602,9 +602,9 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch
index fec0a2af..29e8d753 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -1,7 +1,7 @@
-From eed2bf4db9bdfc0da1c3f77ce746fb5bfa460b3c Mon Sep 17 00:00:00 2001
+From b2d05f4ad5c66fb8cec37064a77d21194db9dd32 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Thu, 29 Nov 2018 17:55:08 +0530
-Subject: [PATCH 44/54] fixing the long & long long mingw toolchain issue
+Subject: [PATCH 42/53] fixing the long & long long mingw toolchain issue
 
 ---
  gcc/config/microblaze/constraints.md | 2 +-
@@ -9,7 +9,7 @@ Subject: [PATCH 44/54] fixing the long & long long mingw toolchain issue
  2 files changed, 5 insertions(+), 5 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index b8ef1650f92..89db511c453 100644
+index 0a4d5269314..e3f89491fb4 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -55,7 +55,7 @@
@@ -22,7 +22,7 @@ index b8ef1650f92..89db511c453 100644
  
  ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 19801f8edcc..8f0ae901b77 100644
+index f62ad28130b..74be0728e75 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -648,8 +648,8 @@
@@ -36,7 +36,7 @@ index 19801f8edcc..8f0ae901b77 100644
        FAIL;
     }
  })
-@@ -1266,7 +1266,7 @@
+@@ -1264,7 +1264,7 @@
         (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
    "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
             (GET_CODE (operands[1]) == CONST_INT && 
@@ -45,7 +45,7 @@ index 19801f8edcc..8f0ae901b77 100644
    "@
     addlk\t%0,r0,r0\t
     addlik\t%0,r0,%1\t #N1 %X1
-@@ -1300,7 +1300,7 @@
+@@ -1298,7 +1298,7 @@
       case 1:
       case 2:
          if (GET_CODE (operands[1]) == CONST_INT && 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch
index 15acc1cb..4fcf90c8 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -1,17 +1,17 @@
-From 682f65fa3a6b37c207b0d727dd22b6f8cc5d8d3d Mon Sep 17 00:00:00 2001
+From 3691860b698107ce5338468cbef932c63d195961 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 14 Mar 2019 18:11:04 +0530
-Subject: [PATCH 45/54] Fix the MB-64 bug of handling QI objects
+Subject: [PATCH 43/53] Fix the MB-64 bug of handling QI objects
 
 ---
  gcc/config/microblaze/microblaze.md | 14 +++++++-------
  1 file changed, 7 insertions(+), 7 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8f0ae901b77..207d2bf1b55 100644
+index 74be0728e75..fed6f5e0234 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -2348,11 +2348,11 @@ else
+@@ -2345,11 +2345,11 @@ else
  
  (define_insn "branch_zero_64"
    [(set (pc)
@@ -26,7 +26,7 @@ index 8f0ae901b77..207d2bf1b55 100644
    ]
    "TARGET_MB_64"
    {
-@@ -2368,11 +2368,11 @@ else
+@@ -2365,11 +2365,11 @@ else
  
  (define_insn "long_branch_zero"
    [(set (pc)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
index eebf6ee7..43c13b31 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -1,7 +1,7 @@
-From 444a09859149f8d21777a1c859ef2305ff86b211 Mon Sep 17 00:00:00 2001
+From b26f11b38406605f1601626f9ee8267f85b4857c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Fri, 29 Mar 2019 12:08:39 +0530
-Subject: [PATCH 46/54] [Patch,Microblaze] : We will check the possibility of
+Subject: [PATCH 44/53] [Patch,Microblaze] : We will check the possibility of
  peephole2 optimization,if we can then we will fix the compiler issue.
 
 ---
@@ -9,7 +9,7 @@ Subject: [PATCH 46/54] [Patch,Microblaze] : We will check the possibility of
  1 file changed, 38 insertions(+), 25 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 207d2bf1b55..9b88666c0a6 100644
+index fed6f5e0234..1490a522a4c 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -882,31 +882,44 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
index 34378812..3edef57a 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -1,7 +1,7 @@
-From 7cc6db7ad5bf2fac80a81711c70ac1147ab87b2c Mon Sep 17 00:00:00 2001
+From db8016ae6874865f57c6841ecabf9d9cdf785ece Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 17 Apr 2019 12:36:16 +0530
-Subject: [PATCH 47/54] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+Subject: [PATCH 45/53] [Patch,MicroBlaze]: fixed typos in mul,div and mod
  assembly files.
 
 ---
@@ -13,7 +13,7 @@ Subject: [PATCH 47/54] [Patch,MicroBlaze]: fixed typos in mul,div and mod
  5 files changed, 212 insertions(+), 20 deletions(-)
 
 diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index 104243e35fe..5755e29fbb6 100644
+index 3a7fc4d6122..0fd275c8702 100644
 --- a/libgcc/config/microblaze/divsi3.S
 +++ b/libgcc/config/microblaze/divsi3.S
 @@ -46,7 +46,7 @@
@@ -107,7 +107,7 @@ index 104243e35fe..5755e29fbb6 100644
  $LaDiv_By_Zero:
  $LaResult_Is_Zero:
 diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 4dbb25900d9..b6129f5e822 100644
+index c98442c01c2..28775d71ba0 100644
 --- a/libgcc/config/microblaze/modsi3.S
 +++ b/libgcc/config/microblaze/modsi3.S
 @@ -62,40 +62,72 @@ __modsi3:
@@ -196,7 +196,7 @@ index 4dbb25900d9..b6129f5e822 100644
         nop
  #else
 diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index 2044399db4a..95709d5bb01 100644
+index 0329fa3037a..7557368bc1c 100644
 --- a/libgcc/config/microblaze/mulsi3.S
 +++ b/libgcc/config/microblaze/mulsi3.S
 @@ -43,7 +43,37 @@
@@ -246,7 +246,7 @@ index 2044399db4a..95709d5bb01 100644
         .end __mulsi3
         .size   __mulsi3, . - __mulsi3
 diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index d2332bcfe62..687d5588801 100644
+index 7bdcd8873e5..feff14664fb 100644
 --- a/libgcc/config/microblaze/udivsi3.S
 +++ b/libgcc/config/microblaze/udivsi3.S
 @@ -59,52 +59,96 @@ __udivsi3:
@@ -360,7 +360,7 @@ index d2332bcfe62..687d5588801 100644
         NOP
  #else
 diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 2dd72aef68e..59646ce437f 100644
+index 63ab1c2a357..f5bbb6f2d10 100644
 --- a/libgcc/config/microblaze/umodsi3.S
 +++ b/libgcc/config/microblaze/umodsi3.S
 @@ -46,7 +46,7 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Author-Nagaraju-nmekala-xilinx.com.patch
index 94be6aff..456c5a48 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Author-Nagaraju-nmekala-xilinx.com.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0046-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -1,7 +1,7 @@
-From f6b896effc198b8d9d1e6f33889f029da5e5d96c Mon Sep 17 00:00:00 2001
+From 45fcd0217edf07fcb6473812cfc4ccacc8e95aac Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 18 Apr 2019 16:00:37 +0530
-Subject: [PATCH 48/54] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+Subject: [PATCH 46/53] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
  17 14:11:00 2019 +0530
 
     [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
@@ -16,7 +16,7 @@ Subject: [PATCH 48/54] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
  2 files changed, 252 insertions(+), 19 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index e32de46fa62..7b48c011550 100644
+index b2cd89a310a..d1257032bfb 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3870,7 +3870,7 @@ microblaze_expand_divide (rtx operands[])
@@ -29,7 +29,7 @@ index e32de46fa62..7b48c011550 100644
      }
    else  {
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 9b88666c0a6..60afd9be288 100644
+index 1490a522a4c..40328b0d39d 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -547,7 +547,7 @@
@@ -95,7 +95,7 @@ index 9b88666c0a6..60afd9be288 100644
    "dlong\t%0,%1"
    [(set_attr "type"     "fcvt")
    (set_attr "mode"      "DI")
-@@ -1301,6 +1301,34 @@
+@@ -1299,6 +1299,34 @@
    (set_attr "mode"     "DI")
    (set_attr "length"   "4")])
  
@@ -130,7 +130,7 @@ index 9b88666c0a6..60afd9be288 100644
  (define_insn "*movdi_internal2"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
         (match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-@@ -1314,7 +1342,15 @@
+@@ -1312,7 +1340,15 @@
       case 2:
          if (GET_CODE (operands[1]) == CONST_INT && 
             (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
@@ -147,7 +147,7 @@ index 9b88666c0a6..60afd9be288 100644
          else   
           return "addlik\t%0,r0,%1";
       case 3:
-@@ -1389,7 +1425,7 @@
+@@ -1387,7 +1423,7 @@
  (define_insn "movdi_long_int"
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
         (match_operand:DI 1 "general_operand"      "i"))]
@@ -156,7 +156,7 @@ index 9b88666c0a6..60afd9be288 100644
    "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
    [(set_attr "type"    "no_delay_arith")
    (set_attr "mode"     "DI")
-@@ -1656,6 +1692,33 @@
+@@ -1654,6 +1690,33 @@
  ;; movdf_internal
  ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
  ;;
@@ -190,7 +190,7 @@ index 9b88666c0a6..60afd9be288 100644
  (define_insn "*movdf_internal_64"
    [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
          (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-@@ -1672,7 +1735,13 @@
+@@ -1670,7 +1733,13 @@
            return "ll%i1\t%0,%1";
        case 3:
        {
@@ -205,7 +205,7 @@ index 9b88666c0a6..60afd9be288 100644
        }
        case 5:
         return "sl%i0\t%1,%0";
-@@ -1792,11 +1861,21 @@
+@@ -1790,11 +1859,21 @@
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -228,7 +228,7 @@ index 9b88666c0a6..60afd9be288 100644
  else
    FAIL;
  }    
-@@ -1806,7 +1885,7 @@ else
+@@ -1804,7 +1883,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -237,7 +237,7 @@ index 9b88666c0a6..60afd9be288 100644
    "@
    bsllli\t%0,%1,%2
    bslll\t%0,%1,%2"
-@@ -1814,6 +1893,51 @@ else
+@@ -1812,6 +1891,51 @@ else
    (set_attr "mode"     "DI,DI")
    (set_attr "length"   "4,4")]
  )
@@ -289,7 +289,7 @@ index 9b88666c0a6..60afd9be288 100644
  ;; The following patterns apply when there is no barrel shifter present
  
  (define_insn "*ashlsi3_with_mul_delay"
-@@ -1947,11 +2071,21 @@ else
+@@ -1945,11 +2069,21 @@ else
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -312,7 +312,7 @@ index 9b88666c0a6..60afd9be288 100644
  else
    FAIL;
  }    
-@@ -1961,7 +2095,7 @@ else
+@@ -1959,7 +2093,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -321,7 +321,7 @@ index 9b88666c0a6..60afd9be288 100644
    "@
     bslrai\t%0,%1,%2
     bslra\t%0,%1,%2"
-@@ -1969,6 +2103,51 @@ else
+@@ -1967,6 +2101,51 @@ else
    (set_attr "mode"     "DI,DI")
    (set_attr "length"   "4,4")]
    )
@@ -373,7 +373,7 @@ index 9b88666c0a6..60afd9be288 100644
  (define_expand "ashrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2086,11 +2265,21 @@ else
+@@ -2084,11 +2263,21 @@ else
  "TARGET_MB_64"
  {
  ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
@@ -396,7 +396,7 @@ index 9b88666c0a6..60afd9be288 100644
  else
    FAIL;
  }    
-@@ -2100,7 +2289,7 @@ else
+@@ -2098,7 +2287,7 @@ else
    [(set (match_operand:DI 0 "register_operand" "=d,d")
         (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
                     (match_operand:DI 2 "arith_operand"    "I,d")))]
@@ -405,7 +405,7 @@ index 9b88666c0a6..60afd9be288 100644
    "@
     bslrli\t%0,%1,%2
     bslrl\t%0,%1,%2"
-@@ -2109,6 +2298,50 @@ else
+@@ -2107,6 +2296,50 @@ else
    (set_attr "length"   "4,4")]
    )
  
@@ -456,7 +456,7 @@ index 9b88666c0a6..60afd9be288 100644
  (define_expand "lshrsi3"
    [(set (match_operand:SI 0 "register_operand" "=&d")
         (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2236,7 +2469,7 @@ else
+@@ -2233,7 +2466,7 @@ else
         (eq:DI 
                (match_operand:DI 1 "register_operand" "d")
                (match_operand:DI 2 "register_operand" "d")))]
@@ -465,7 +465,7 @@ index 9b88666c0a6..60afd9be288 100644
    "pcmpleq\t%0,%1,%2"
    [(set_attr "type"    "arith")
     (set_attr "mode"    "DI")
-@@ -2248,7 +2481,7 @@ else
+@@ -2245,7 +2478,7 @@ else
         (ne:DI 
                (match_operand:DI 1 "register_operand" "d")
                (match_operand:DI 2 "register_operand" "d")))]
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch
index 81ecbf8e..98183053 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -1,14 +1,14 @@
-From adb1b8d8cc2a8fb99f474d9166db9f68b8f3f8b4 Mon Sep 17 00:00:00 2001
+From 688fcf782b7eca82cb2e2ab6589dee843983a5d6 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Fri, 23 Aug 2019 16:16:53 +0530
-Subject: [PATCH 49/54] Added new MB-64 single register arithmetic instructions
+Subject: [PATCH 47/53] Added new MB-64 single register arithmetic instructions
 
 ---
  gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++
  1 file changed, 56 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 60afd9be288..1ad139cbd44 100644
+index 40328b0d39d..6bd042747bf 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -654,6 +654,18 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
index d452b988..29291154 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -1,7 +1,7 @@
-From 797697692635d4c536181cb007b3b0d63d2431c1 Mon Sep 17 00:00:00 2001
+From 9098a760a10f09fefbdf438daf63b9e36576c9b2 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 26 Aug 2019 15:55:22 +0530
-Subject: [PATCH 50/54] [Patch,MicroBlaze] : Added support for 64 bit Immediate
+Subject: [PATCH 48/53] [Patch,MicroBlaze] : Added support for 64 bit Immediate
  values.
 
 ---
@@ -10,7 +10,7 @@ Subject: [PATCH 50/54] [Patch,MicroBlaze] : Added support for 64 bit Immediate
  2 files changed, 3 insertions(+), 4 deletions(-)
 
 diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 89db511c453..9ad2b099310 100644
+index e3f89491fb4..ef3001764c0 100644
 --- a/gcc/config/microblaze/constraints.md
 +++ b/gcc/config/microblaze/constraints.md
 @@ -53,9 +53,9 @@
@@ -26,10 +26,10 @@ index 89db511c453..9ad2b099310 100644
  
  ;; Define floating point constraints
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 1ad139cbd44..93de8d831fd 100644
+index 6bd042747bf..b89a4276c7c 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
-@@ -1334,8 +1334,7 @@
+@@ -1332,8 +1332,7 @@
    [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
         (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
    "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
index 3e0c483b..163d4925 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
@@ -1,7 +1,7 @@
-From 697db2e2c2519f27011fbd1960cd8860133aaa84 Mon Sep 17 00:00:00 2001
+From 2673e0dc2d75769c7cc36ca94e4e07caa28b8ef7 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Thu, 9 Jan 2020 12:30:41 +0530
-Subject: [PATCH 51/54] [Patch, microblaze]: Fix Compiler crash with
+Subject: [PATCH 49/53] [Patch, microblaze]: Fix Compiler crash with
  -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
  struct values in registers. Currently we are only handling SImode With this
  patch all other modes are handled properly
@@ -23,7 +23,7 @@ ChangeLog:
  2 files changed, 10 insertions(+), 20 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 7b48c011550..1bba77dab6d 100644
+index d1257032bfb..5afac2ba8d1 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -3908,7 +3908,16 @@ microblaze_function_value (const_tree valtype,
@@ -45,7 +45,7 @@ index 7b48c011550..1bba77dab6d 100644
  
  /* Implement TARGET_SCHED_ADJUST_COST.  */
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index bfa7bc9a01c..d467a7ee65d 100644
+index c6c3a9baa5a..2581d52d17a 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
index 91c7c026..37945b65 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -1,7 +1,7 @@
-From d7d6835bd839150e864cbb0d9c9c7a497e93bbb8 Mon Sep 17 00:00:00 2001
+From 009fc9cbb72f50ac73b7f58153d0d90db46b48b8 Mon Sep 17 00:00:00 2001
 From: Nagaraju <nmekala@xilinx.com>
 Date: Wed, 8 May 2019 14:12:03 +0530
-Subject: [PATCH 52/54] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+Subject: [PATCH 50/53] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
  disable fivopts by default
 
 Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
@@ -18,7 +18,7 @@ Conflicts:
  1 file changed, 11 insertions(+)
 
 diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 4391f939626..cf2db8afe36 100644
+index 1e4abb34027..d3a74fcc99e 100644
 --- a/gcc/common/config/microblaze/microblaze-common.c
 +++ b/gcc/common/config/microblaze/microblaze-common.c
 @@ -24,7 +24,18 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
index 377154d7..73b170c1 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -1,7 +1,7 @@
-From e146b21e18e51ab6ce77af2c39cdf3375606c1eb Mon Sep 17 00:00:00 2001
+From f52258e89f2ea416f418b6c55fef15552a081e18 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 24 Nov 2020 12:26:32 +0530
-Subject: [PATCH 53/54] [Patch, microblaze]: Reducing Stack space for arguments
+Subject: [PATCH 51/53] [Patch, microblaze]: Reducing Stack space for arguments
 
 Currently in Microblaze target stack space for arguments in register is being
 allocated even if there are no arguments in the function.
@@ -16,7 +16,7 @@ Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
  3 files changed, 134 insertions(+), 3 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 460feac4ac5..b8a3321dbdf 100644
+index 302f6bbda2e..87a7093e369 100644
 --- a/gcc/config/microblaze/microblaze-protos.h
 +++ b/gcc/config/microblaze/microblaze-protos.h
 @@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx);
@@ -28,7 +28,7 @@ index 460feac4ac5..b8a3321dbdf 100644
  
  /* Declare functions in microblaze-c.c.  */
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 1bba77dab6d..dac0596bc7d 100644
+index 5afac2ba8d1..6914eb8380c 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2080,6 +2080,136 @@ microblaze_must_save_register (int regno)
@@ -178,7 +178,7 @@ index 1bba77dab6d..dac0596bc7d 100644
    shorten_branches (insn);
    assemble_start_function (thunk_fndecl, fnname);
 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index d467a7ee65d..be6c798c889 100644
+index 2581d52d17a..9c48978d2ca 100644
 --- a/gcc/config/microblaze/microblaze.h
 +++ b/gcc/config/microblaze/microblaze.h
 @@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info;
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0055-Patch-MicroBlaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-MicroBlaze.patch
index 4d6cbae6..293a7486 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0055-Patch-MicroBlaze.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0052-Patch-MicroBlaze.patch
@@ -1,17 +1,18 @@
-From db280c2d72bb043215b2fdfe7cf959fb50d3ce80 Mon Sep 17 00:00:00 2001
+From b0ea0d18d1b353421ef7e18d496fd505cb1d5f7d Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 28 Apr 2021 16:49:18 +0530
-Subject: [PATCH 55] [Patch,MicroBlaze] : If we use break_handler attribute then
- interrupt vector call happened to break_handler instead of interrupt_handler.
- this fix will resolve the issue CR-1081780 This fix will not change the
- behavior of compiler unless there is a usage of break_handler attribute.
+Subject: [PATCH 52/53] [Patch,MicroBlaze] : If we use break_handler attribute
+ then interrupt vector call happened to break_handler instead of
+ interrupt_handler. this fix will resolve the issue CR-1081780 This fix will
+ not change the behavior of compiler unless there is a usage of break_handler
+ attribute.
 
 ---
  gcc/config/microblaze/microblaze.c | 13 +++++--------
  1 file changed, 5 insertions(+), 8 deletions(-)
 
 diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index d72eb7d5898..e47eb1cd0fe 100644
+index 6914eb8380c..d0546a164d7 100644
 --- a/gcc/config/microblaze/microblaze.c
 +++ b/gcc/config/microblaze/microblaze.c
 @@ -2019,7 +2019,7 @@ microblaze_save_volatiles (tree func)
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-patch-microblaze64-Add-Zero_extended-instructions.patch
index 949e6346..76148d15 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0056-patch-microblaze64-Add-Zero_extended-instructions.patch
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-11/0053-patch-microblaze64-Add-Zero_extended-instructions.patch
@@ -1,7 +1,7 @@
-From 4096da3ea3765ec9484af719a16074789b8946ee Mon Sep 17 00:00:00 2001
+From 7c9402f1dc641a1fe4110e92cd16a33ed4bd35cf Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilinx.com>
 Date: Mon, 30 Aug 2021 12:13:45 +0530
-Subject: [PATCH] [patch, microblaze64]: Add Zero_extended instructions
+Subject: [PATCH 53/53] [patch, microblaze64]: Add Zero_extended instructions
 
 Due to latest changes in GCC-10.2 MB64 perforamance has reduced
 We have added zero_extended instructions to get rid of left shift
@@ -15,7 +15,7 @@ Signed-off-by: Nagaraju Mekala<nmekala@xilinx.com>
  1 file changed, 27 insertions(+)
 
 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 71ac46dfb6c..51c2751e6be 100644
+index b89a4276c7c..ee078b0152a 100644
 --- a/gcc/config/microblaze/microblaze.md
 +++ b/gcc/config/microblaze/microblaze.md
 @@ -1191,6 +1191,33 @@
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-11/0054-Patch-MicroBlaze-Typo-in-the-previous-commits.bsefi-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-11/0054-Patch-MicroBlaze-Typo-in-the-previous-commits.bsefi-.patch
deleted file mode 100644
index 2d53e4b2..00000000
--- a/meta-microblaze/recipes-devtools/gcc/gcc-11/0054-Patch-MicroBlaze-Typo-in-the-previous-commits.bsefi-.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 54aa2bf8d84820071de2670504d2e87cc8231c1e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 31 Mar 2021 17:18:56 +0530
-Subject: [PATCH] [Patch,MicroBlaze] : Typo in the previous commits.bsefi/bsifi
- should be generated only if mcpu is >= 10.0
-
----
- gcc/config/microblaze/microblaze.c  | 2 +-
- gcc/config/microblaze/microblaze.md | 4 ++--
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index dac0596bc7d..d72eb7d5898 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -1850,7 +1850,7 @@ microblaze_option_override (void)
-                   "%<-mcpu=v8.30.a%>");
-         TARGET_REORDER = 0;
-     }
--  ver = microblaze_version_to_int("v10.0");
-+  ver = ver_int - microblaze_version_to_int("v10.0");
-   if (ver < 0)
-     {
-         if (TARGET_AREA_OPTIMIZED_2)
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 93de8d831fd..71ac46dfb6c 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -3598,7 +3598,7 @@ else
-        (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-                         (match_operand:SI 2 "immediate_operand" "I")
-                         (match_operand:SI 3 "immediate_operand" "I")))]
-- "TARGET_BARREL_SHIFT && (UINTVAL (operands[2]) > 0)
-+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
-    && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
-   "bsefi %0,%1,%2,%3"
-   [(set_attr "type" "bshift")
-@@ -3630,7 +3630,7 @@ else
-                         (match_operand:SI 1 "immediate_operand" "I")
-                         (match_operand:SI 2 "immediate_operand" "I"))
-        (match_operand:SI 3 "register_operand" "r"))]
-- "TARGET_BARREL_SHIFT && UINTVAL (operands[1]) > 0
-+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
-    && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
-   "bsifi %0, %3, %1, %2"
-   [(set_attr "type" "bshift")
--- 
-2.17.1
-
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend b/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend
index e7d453a4..ab3a1c47 100644
--- a/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-source_11.%.bbappend
@@ -25,38 +25,35 @@ SRC_URI:append:microblaze = " \
     file://0021-Patch-microblaze-Correct-the-const-high-double-immed.patch \
     file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
     file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
-    file://0024-Patch-microblaze-Add-new-bit-field-instructions.patch \
-    file://0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
-    file://0026-Fixing-the-issue-with-the-builtin_alloc.patch \
-    file://0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
-    file://0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
-    file://0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \
-    file://0030-Intial-commit-for-64bit-MB-sources.patch \
-    file://0031-re-arrangement-of-the-compare-branches.patch \
-    file://0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
-    file://0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
-    file://0034-Fixed-issues-like.patch \
-    file://0035-Fixed-below-issues.patch \
-    file://0036-Added-double-arith-instructions.patch \
-    file://0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
-    file://0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
-    file://0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
-    file://0040-fixing-the-typo-errors-in-umodsi3-file.patch \
-    file://0041-fixing-the-32bit-LTO-related-issue9-1014024.patch \
-    file://0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
-    file://0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
-    file://0044-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-    file://0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
-    file://0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
-    file://0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
-    file://0048-Author-Nagaraju-nmekala-xilinx.com.patch \
-    file://0049-Added-new-MB-64-single-register-arithmetic-instructi.patch \
-    file://0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
-    file://0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
-    file://0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
-    file://0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
-    file://0054-Patch-MicroBlaze-Typo-in-the-previous-commits.bsefi-.patch \
-    file://0055-Patch-MicroBlaze.patch \
-    file://0056-patch-microblaze64-Add-Zero_extended-instructions.patch \
+    file://0024-Patch-MicroBlaze-this-patch-has.patch \
+    file://0025-Fixing-the-issue-with-the-builtin_alloc.patch \
+    file://0026-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
+    file://0027-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \
+    file://0028-Intial-commit-for-64bit-MB-sources.patch \
+    file://0029-re-arrangement-of-the-compare-branches.patch \
+    file://0030-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
+    file://0031-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
+    file://0032-Fixed-issues-like.patch \
+    file://0033-Fixed-below-issues.patch \
+    file://0034-Added-double-arith-instructions.patch \
+    file://0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
+    file://0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
+    file://0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
+    file://0038-fixing-the-typo-errors-in-umodsi3-file.patch \
+    file://0039-fixing-the-32bit-LTO-related-issue9-1014024.patch \
+    file://0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
+    file://0041-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
+    file://0042-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+    file://0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
+    file://0044-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
+    file://0045-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
+    file://0046-Author-Nagaraju-nmekala-xilinx.com.patch \
+    file://0047-Added-new-MB-64-single-register-arithmetic-instructi.patch \
+    file://0048-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
+    file://0049-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
+    file://0050-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
+    file://0051-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
+    file://0052-Patch-MicroBlaze.patch \
+    file://0053-patch-microblaze64-Add-Zero_extended-instructions.patch \
     file://microblaze-mulitlib-hack.patch \
 "