diff options
Diffstat (limited to 'meta-microblaze/recipes-microblaze/gdb/gdb/0010-Add-new-bit-field-instructions.patch')
-rw-r--r-- | meta-microblaze/recipes-microblaze/gdb/gdb/0010-Add-new-bit-field-instructions.patch | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-microblaze/gdb/gdb/0010-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-microblaze/gdb/gdb/0010-Add-new-bit-field-instructions.patch new file mode 100644 index 00000000..11d45a23 --- /dev/null +++ b/meta-microblaze/recipes-microblaze/gdb/gdb/0010-Add-new-bit-field-instructions.patch | |||
@@ -0,0 +1,139 @@ | |||
1 | From 55acba095458b872b500e978af946733a9f33021 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju Mekala <nmekala@xilix.com> | ||
3 | Date: Mon, 18 Jul 2016 12:24:28 +0530 | ||
4 | Subject: [PATCH 10/43] Add new bit-field instructions | ||
5 | |||
6 | This patches adds new bsefi and bsifi instructions. | ||
7 | BSEFI- The instruction shall extract a bit field from a | ||
8 | register and place it right-adjusted in the destination register. | ||
9 | The other bits in the destination register shall be set to zero | ||
10 | BSIFI- The instruction shall insert a right-adjusted bit field | ||
11 | from a register at another position in the destination register. | ||
12 | The rest of the bits in the destination register shall be unchanged | ||
13 | |||
14 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | ||
15 | --- | ||
16 | opcodes/microblaze-dis.c | 16 +++++++++ | ||
17 | opcodes/microblaze-opc.h | 12 ++++++- | ||
18 | opcodes/microblaze-opcm.h | 6 +++- | ||
19 | 4 files changed, 102 insertions(+), 3 deletions(-) | ||
20 | |||
21 | diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c | ||
22 | index f691740dfd..f8aaf27873 100644 | ||
23 | --- a/opcodes/microblaze-dis.c | ||
24 | +++ b/opcodes/microblaze-dis.c | ||
25 | @@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr) | ||
26 | return(strdup(tmpstr)); | ||
27 | } | ||
28 | |||
29 | +static char * | ||
30 | +get_field_imm5width (long instr) | ||
31 | +{ | ||
32 | + char tmpstr[25]; | ||
33 | + | ||
34 | + if (instr & 0x00004000) | ||
35 | + sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ | ||
36 | + else | ||
37 | + sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ | ||
38 | + return (strdup (tmpstr)); | ||
39 | +} | ||
40 | + | ||
41 | static char * | ||
42 | get_field_rfsl (long instr) | ||
43 | { | ||
44 | @@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) | ||
45 | /* For mbar 16 or sleep insn. */ | ||
46 | case INST_TYPE_NONE: | ||
47 | break; | ||
48 | + /* For bit field insns. */ | ||
49 | + case INST_TYPE_RD_R1_IMM5_IMM5: | ||
50 | + print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst)); | ||
51 | + break; | ||
52 | /* For tuqula instruction */ | ||
53 | case INST_TYPE_RD: | ||
54 | print_func (stream, "\t%s", get_field_rd (inst)); | ||
55 | diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h | ||
56 | index 2a6b841232..ce8ac351b5 100644 | ||
57 | --- a/opcodes/microblaze-opc.h | ||
58 | +++ b/opcodes/microblaze-opc.h | ||
59 | @@ -59,6 +59,9 @@ | ||
60 | /* For mbar. */ | ||
61 | #define INST_TYPE_IMM5 20 | ||
62 | |||
63 | +/* For bsefi and bsifi */ | ||
64 | +#define INST_TYPE_RD_R1_IMM5_IMM5 21 | ||
65 | + | ||
66 | #define INST_TYPE_NONE 25 | ||
67 | |||
68 | |||
69 | @@ -89,7 +92,9 @@ | ||
70 | #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ | ||
71 | #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ | ||
72 | #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ | ||
73 | +#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */ | ||
74 | #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ | ||
75 | +#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */ | ||
76 | #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ | ||
77 | #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ | ||
78 | #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ | ||
79 | @@ -102,7 +107,7 @@ | ||
80 | #define DELAY_SLOT 1 | ||
81 | #define NO_DELAY_SLOT 0 | ||
82 | |||
83 | -#define MAX_OPCODES 299 | ||
84 | +#define MAX_OPCODES 301 | ||
85 | |||
86 | struct op_code_struct | ||
87 | { | ||
88 | @@ -159,6 +164,8 @@ struct op_code_struct | ||
89 | {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, | ||
90 | {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, | ||
91 | {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, | ||
92 | + {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, | ||
93 | + {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, | ||
94 | {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, | ||
95 | {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, | ||
96 | {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, | ||
97 | @@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr"; | ||
98 | #define MIN_IMM5 ((int) 0x00000000) | ||
99 | #define MAX_IMM5 ((int) 0x0000001f) | ||
100 | |||
101 | +#define MIN_IMM_WIDTH ((int) 0x00000001) | ||
102 | +#define MAX_IMM_WIDTH ((int) 0x00000020) | ||
103 | + | ||
104 | #endif /* MICROBLAZE_OPC */ | ||
105 | |||
106 | diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h | ||
107 | index 1c39dbf50b..28662694cd 100644 | ||
108 | --- a/opcodes/microblaze-opcm.h | ||
109 | +++ b/opcodes/microblaze-opcm.h | ||
110 | @@ -29,7 +29,7 @@ enum microblaze_instr | ||
111 | addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, | ||
112 | mulh, mulhu, mulhsu,swapb,swaph, | ||
113 | idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, | ||
114 | - ncget, ncput, muli, bslli, bsrai, bsrli, mului, | ||
115 | + ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, | ||
116 | /* 'or/and/xor' are C++ keywords. */ | ||
117 | microblaze_or, microblaze_and, microblaze_xor, | ||
118 | andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, | ||
119 | @@ -129,6 +129,7 @@ enum microblaze_instr_type | ||
120 | #define RB_LOW 11 /* Low bit for RB. */ | ||
121 | #define IMM_LOW 0 /* Low bit for immediate. */ | ||
122 | #define IMM_MBAR 21 /* low bit for mbar instruction. */ | ||
123 | +#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ | ||
124 | |||
125 | #define RD_MASK 0x03E00000 | ||
126 | #define RA_MASK 0x001F0000 | ||
127 | @@ -141,6 +142,9 @@ enum microblaze_instr_type | ||
128 | /* Imm mask for mbar. */ | ||
129 | #define IMM5_MBAR_MASK 0x03E00000 | ||
130 | |||
131 | +/* Imm mask for extract/insert width. */ | ||
132 | +#define IMM5_WIDTH_MASK 0x000007C0 | ||
133 | + | ||
134 | /* FSL imm mask for get, put instructions. */ | ||
135 | #define RFSL_MASK 0x000000F | ||
136 | |||
137 | -- | ||
138 | 2.17.1 | ||
139 | |||