1 files changed, 110 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch
new file mode 100644
index 00000000..03d8e0b8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch
@@ -0,0 +1,110 @@
+From d3fd5a77fa218f8f6c296337758d45cab61483fe Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 2 Nov 2021 17:28:24 +0530
+Subject: [PATCH 26/53] [Patch,MicroBlaze : Adding new relocation to support
+ 64bit rodata.
+Signed-off-by: Aayush Misra <aayushm@amd.com>
+---
+ gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++----
+ 1 file changed, 45 insertions(+), 4 deletions(-)
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 544732649a5..c9757796ae8 100644
+--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
+@@ -1090,6 +1090,13 @@ md_assemble (char * str)
+            as_fatal (_("smi pseudo instruction should not use a label in imm field"));
+           if(streq (name, "lli") || streq (name, "sli"))
+             opc = str_microblaze_64;
+          else if ((microblaze_arch_size == 64) && ((streq (name, "lbui")
+                       || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi")
+                       || streq (name, "shi") || streq (name, "swi"))))
+           {
+              opc = str_microblaze_64;
+             subtype = opcode->inst_offset_type;
+           }
+          else if (reg2 == REG_ROSDP)
+            opc = str_microblaze_ro_anchor;
+          else if (reg2 == REG_RWSDP)
+@@ -1157,7 +1164,10 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+        }
+-      else if (streq (name, "lli") || streq (name, "sli"))
+      else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64)
+               && ((streq (name, "lbui")) || streq (name, "lhui")
+               || streq (name, "lwi") || streq (name, "sbi")
+                || streq (name, "shi") || streq (name, "swi"))))
+         {
+           temp = immed & 0xFFFFFF8000;
+           if (temp != 0 && temp != 0xFFFFFF8000)
+@@ -1773,6 +1783,11 @@ md_assemble (char * str)
+ 
+          if (exp.X_md != 0)
+            subtype = get_imm_otype(exp.X_md);
+          else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+            {
+              opc = str_microblaze_64;
+             subtype = opcode->inst_offset_type;
+           }
+          else
+            subtype = opcode->inst_offset_type;
+ 
+@@ -1790,6 +1805,31 @@ md_assemble (char * str)
+           output = frag_more (isize);
+           immed = exp.X_add_number;
+         }
+      if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+        {
+          temp = immed & 0xFFFFFF8000;
+          if (temp != 0 && temp != 0xFFFFFF8000)
+            {
+              /* Needs an immediate inst.  */
+              opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+              if (opcode1 == NULL)
+                {
+                  as_bad (_("unknown opcode \"%s\""), "imml");
+                  return;
+                }
+              inst1 = opcode1->bit_sequence;
+             inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+              output[0] = INST_BYTE0 (inst1);
+              output[1] = INST_BYTE1 (inst1);
+              output[2] = INST_BYTE2 (inst1);
+              output[3] = INST_BYTE3 (inst1);
+              output = frag_more (isize);
+            }
+         inst |= (reg1 << RD_LOW) & RD_MASK;
+          inst |= (immed << IMM_LOW) & IMM_MASK;
+         }
+       else 
+        {
+ 
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+@@ -1815,6 +1855,7 @@ md_assemble (char * str)
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (immed << IMM_LOW) & IMM_MASK;
+        }
+       break;
+ 
+     case INST_TYPE_R2:
+@@ -3060,10 +3101,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          /*if (microblaze_arch_size == 64)
+-            r = BFD_RELOC_32;
+-          else*/
+          if (microblaze_arch_size == 64)
+             r = BFD_RELOC_MICROBLAZE_EA64;
+          else
+            r = BFD_RELOC_64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+-- 
+2.34.1

diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch new file mode 100644 index 00000000..03d8e0b8 --- /dev/null +++ b/meta-microblaze/recipes-devtools/binutils/binutils/0026-Patch-MicroBlaze-Adding-new-relocation-to-support-64.patch
@@ -0,0 +1,110 @@
	1	From d3fd5a77fa218f8f6c296337758d45cab61483fe Mon Sep 17 00:00:00 2001
	2	From: Mahesh Bodapati <mbodapat@xilinx.com>
	3	Date: Tue, 2 Nov 2021 17:28:24 +0530
	4	Subject: [PATCH 26/53] [Patch,MicroBlaze : Adding new relocation to support
	5	64bit rodata.
	6
	7	Signed-off-by: Aayush Misra <aayushm@amd.com>
	8	---
	9	gas/config/tc-microblaze.c \| 49 ++++++++++++++++++++++++++++++++++----
	10	1 file changed, 45 insertions(+), 4 deletions(-)
	11
	12	diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
	13	index 544732649a5..c9757796ae8 100644
	14	--- a/gas/config/tc-microblaze.c
	15	+++ b/gas/config/tc-microblaze.c
	16	@@ -1090,6 +1090,13 @@ md_assemble (char * str)
	17	as_fatal (_("smi pseudo instruction should not use a label in imm field"));
	18	if(streq (name, "lli") \|\| streq (name, "sli"))
	19	opc = str_microblaze_64;
	20	+ else if ((microblaze_arch_size == 64) && ((streq (name, "lbui")
	21	+ \|\| streq (name, "lhui") \|\| streq (name, "lwi") \|\| streq (name, "sbi")
	22	+ \|\| streq (name, "shi") \|\| streq (name, "swi"))))
	23	+ {
	24	+ opc = str_microblaze_64;
	25	+ subtype = opcode->inst_offset_type;
	26	+ }
	27	else if (reg2 == REG_ROSDP)
	28	opc = str_microblaze_ro_anchor;
	29	else if (reg2 == REG_RWSDP)
	30	@@ -1157,7 +1164,10 @@ md_assemble (char * str)
	31	inst \|= (immed << IMM_LOW) & IMM_MASK;
	32	}
	33	}
	34	- else if (streq (name, "lli") \|\| streq (name, "sli"))
	35	+ else if (streq (name, "lli") \|\| streq (name, "sli") \|\| ((microblaze_arch_size == 64)
	36	+ && ((streq (name, "lbui")) \|\| streq (name, "lhui")
	37	+ \|\| streq (name, "lwi") \|\| streq (name, "sbi")
	38	+ \|\| streq (name, "shi") \|\| streq (name, "swi"))))
	39	{
	40	temp = immed & 0xFFFFFF8000;
	41	if (temp != 0 && temp != 0xFFFFFF8000)
	42	@@ -1773,6 +1783,11 @@ md_assemble (char * str)
	43
	44	if (exp.X_md != 0)
	45	subtype = get_imm_otype(exp.X_md);
	46	+ else if (streq (name, "brealid") \|\| streq (name, "breaid") \|\| streq (name, "breai"))
	47	+ {
	48	+ opc = str_microblaze_64;
	49	+ subtype = opcode->inst_offset_type;
	50	+ }
	51	else
	52	subtype = opcode->inst_offset_type;
	53
	54	@@ -1790,6 +1805,31 @@ md_assemble (char * str)
	55	output = frag_more (isize);
	56	immed = exp.X_add_number;
	57	}
	58	+ if (streq (name, "brealid") \|\| streq (name, "breaid") \|\| streq (name, "breai"))
	59	+ {
	60	+ temp = immed & 0xFFFFFF8000;
	61	+ if (temp != 0 && temp != 0xFFFFFF8000)
	62	+ {
	63	+ /* Needs an immediate inst. */
	64	+ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
	65	+ if (opcode1 == NULL)
	66	+ {
	67	+ as_bad (_("unknown opcode \"%s\""), "imml");
	68	+ return;
	69	+ }
	70	+ inst1 = opcode1->bit_sequence;
	71	+ inst1 \|= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
	72	+ output[0] = INST_BYTE0 (inst1);
	73	+ output[1] = INST_BYTE1 (inst1);
	74	+ output[2] = INST_BYTE2 (inst1);
	75	+ output[3] = INST_BYTE3 (inst1);
	76	+ output = frag_more (isize);
	77	+ }
	78	+ inst \|= (reg1 << RD_LOW) & RD_MASK;
	79	+ inst \|= (immed << IMM_LOW) & IMM_MASK;
	80	+ }
	81	+ else
	82	+ {
	83
	84	temp = immed & 0xFFFF8000;
	85	if ((temp != 0) && (temp != 0xFFFF8000))
	86	@@ -1815,6 +1855,7 @@ md_assemble (char * str)
	87
	88	inst \|= (reg1 << RD_LOW) & RD_MASK;
	89	inst \|= (immed << IMM_LOW) & IMM_MASK;
	90	+ }
	91	break;
	92
	93	case INST_TYPE_R2:
	94	@@ -3060,10 +3101,10 @@ cons_fix_new_microblaze (fragS * frag,
	95	r = BFD_RELOC_32;
	96	break;
	97	case 8:
	98	- /*if (microblaze_arch_size == 64)
	99	- r = BFD_RELOC_32;
	100	- else*/
	101	+ if (microblaze_arch_size == 64)
	102	r = BFD_RELOC_MICROBLAZE_EA64;
	103	+ else
	104	+ r = BFD_RELOC_64;
	105	break;
	106	default:
	107	as_bad (_("unsupported BFD relocation size %u"), size);
	108	--
	109	2.34.1
	110