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-rw-r--r--meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch373
1 files changed, 0 insertions, 373 deletions
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch
deleted file mode 100644
index 74b0f42a..00000000
--- a/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch
+++ /dev/null
@@ -1,373 +0,0 @@
1From 3c197b12c4b680a230e8350ecd9a523be804fe3c Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Fri, 23 Aug 2019 16:18:43 +0530
4Subject: [PATCH 23/34] Added support to new arithmetic single register
5 instructions
6
7Conflicts:
8 opcodes/microblaze-dis.c
9
10Conflicts:
11 gas/config/tc-microblaze.c
12 opcodes/microblaze-dis.c
13
14Conflicts:
15 gas/config/tc-microblaze.c
16signed-off-by:Nagaraju <nmekala@xilinx.com>
17 Mahesh <mbodapat@xilinx.com>
18Upstream-Status: Pending
19
20Signed-off-by: Mark Hatle <mark.hatle@amd.com>
21
22---
23 gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
24 opcodes/microblaze-dis.c | 11 +++
25 opcodes/microblaze-opc.h | 43 ++++++++++-
26 opcodes/microblaze-opcm.h | 5 +-
27 4 files changed, 200 insertions(+), 6 deletions(-)
28
29diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
30index a1fb6ccbd44..27544b60ea3 100644
31--- a/gas/config/tc-microblaze.c
32+++ b/gas/config/tc-microblaze.c
33@@ -423,12 +423,33 @@ void
34 md_begin (void)
35 {
36 const struct op_code_struct * opcode;
37+ const char *prev_name = "";
38
39 opcode_hash_control = str_htab_create ();
40
41 /* Insert unique names into hash table. */
42- for (opcode = microblaze_opcodes; opcode->name; opcode ++)
43- str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
44+ for (opcode = (struct microblaze_opcodes *)microblaze_opcodes; opcode->name; opcode ++)
45+ {
46+ if (strcmp (prev_name, opcode->name))
47+ {
48+ prev_name = (char *) opcode->name;
49+ str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
50+ }
51+ }
52+}
53+
54+static int
55+is_reg (char * s)
56+{
57+ int is_reg = 0;
58+ /* Strip leading whitespace. */
59+ while (ISSPACE (* s))
60+ ++ s;
61+ if (TOLOWER (s[0]) == 'r')
62+ {
63+ is_reg =1;
64+ }
65+ return is_reg;
66 }
67
68 /* Try to parse a reg name. */
69@@ -986,6 +1007,7 @@ md_assemble (char * str)
70 {
71 char * op_start;
72 char * op_end;
73+ char * temp_op_end;
74 struct op_code_struct * opcode, *opcode1;
75 char * output = NULL;
76 int nlen = 0;
77@@ -996,9 +1018,10 @@ md_assemble (char * str)
78 unsigned reg3;
79 unsigned isize;
80 unsigned long immed = 0, immed2 = 0, temp;
81- expressionS exp;
82+ expressionS exp,exp1;
83 char name[20];
84 long immedl;
85+ int reg=0;
86
87 /* Drop leading whitespace. */
88 while (ISSPACE (* str))
89@@ -1029,7 +1052,78 @@ md_assemble (char * str)
90 as_bad (_("unknown opcode \"%s\""), name);
91 return;
92 }
93-
94+
95+ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
96+ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli")
97+ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc")
98+ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli")
99+ || streq (name, "xorli")))
100+ {
101+ temp_op_end = op_end;
102+ if (strcmp (temp_op_end, ""))
103+ temp_op_end = parse_reg (temp_op_end + 1, &reg1); /* Get rd. */
104+ if (strcmp (temp_op_end, ""))
105+ reg = is_reg (temp_op_end + 1);
106+ if (reg)
107+ {
108+
109+ opcode->inst_type=INST_TYPE_RD_R1_IMML;
110+ opcode->inst_offset_type = OPCODE_MASK_H;
111+ if (streq (name, "addli"))
112+ opcode->bit_sequence = ADDLI_MASK;
113+ else if (streq (name, "addlic"))
114+ opcode->bit_sequence = ADDLIC_MASK;
115+ else if (streq (name, "addlik"))
116+ opcode->bit_sequence = ADDLIK_MASK;
117+ else if (streq (name, "addlikc"))
118+ opcode->bit_sequence = ADDLIKC_MASK;
119+ else if (streq (name, "rsubli"))
120+ opcode->bit_sequence = RSUBLI_MASK;
121+ else if (streq (name, "rsublic"))
122+ opcode->bit_sequence = RSUBLIC_MASK;
123+ else if (streq (name, "rsublik"))
124+ opcode->bit_sequence = RSUBLIK_MASK;
125+ else if (streq (name, "rsublikc"))
126+ opcode->bit_sequence = RSUBLIKC_MASK;
127+ else if (streq (name, "andli"))
128+ opcode->bit_sequence = ANDLI_MASK;
129+ else if (streq (name, "andnli"))
130+ opcode->bit_sequence = ANDLNI_MASK;
131+ else if (streq (name, "orli"))
132+ opcode->bit_sequence = ORLI_MASK;
133+ else if (streq (name, "xorli"))
134+ opcode->bit_sequence = XORLI_MASK;
135+ }
136+ else
137+ {
138+ opcode->inst_type=INST_TYPE_RD_IMML;
139+ opcode->inst_offset_type = OPCODE_MASK_LIMM;
140+ if (streq (name, "addli"))
141+ opcode->bit_sequence = ADDLI_ONE_REG_MASK;
142+ else if (streq (name, "addlic"))
143+ opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
144+ else if (streq (name, "addlik"))
145+ opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
146+ else if (streq (name, "addlikc"))
147+ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
148+ else if (streq (name, "rsubli"))
149+ opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
150+ else if (streq (name, "rsublic"))
151+ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
152+ else if (streq (name, "rsublik"))
153+ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
154+ else if (streq (name, "rsublikc"))
155+ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
156+ else if (streq (name, "andli"))
157+ opcode->bit_sequence = ANDLI_ONE_REG_MASK;
158+ else if (streq (name, "andnli"))
159+ opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
160+ else if (streq (name, "orli"))
161+ opcode->bit_sequence = ORLI_ONE_REG_MASK;
162+ else if (streq (name, "xorli"))
163+ opcode->bit_sequence = XORLI_ONE_REG_MASK;
164+ }
165+ }
166 inst = opcode->bit_sequence;
167 isize = 4;
168
169@@ -1486,6 +1580,51 @@ md_assemble (char * str)
170 inst |= (immed << IMM_LOW) & IMM15_MASK;
171 break;
172
173+ case INST_TYPE_RD_IMML:
174+ if (strcmp (op_end, ""))
175+ op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
176+ else
177+ {
178+ as_fatal (_("Error in statement syntax"));
179+ reg1 = 0;
180+ }
181+
182+ if (strcmp (op_end, ""))
183+ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
184+ else
185+ as_fatal (_("Error in statement syntax"));
186+
187+ /* Check for spl registers. */
188+ if (check_spl_reg (&reg1))
189+ as_fatal (_("Cannot use special register with this instruction"));
190+ if (exp.X_op != O_constant)
191+ {
192+ char *opc = NULL;
193+ relax_substateT subtype;
194+
195+ if (exp.X_md != 0)
196+ subtype = get_imm_otype(exp.X_md);
197+ else
198+ subtype = opcode->inst_offset_type;
199+
200+ output = frag_var (rs_machine_dependent,
201+ isize * 2,
202+ isize * 2,
203+ subtype,
204+ exp.X_add_symbol,
205+ exp.X_add_number,
206+ (char *) opc);
207+ immedl = 0L;
208+ }
209+ else
210+ {
211+ output = frag_more (isize);
212+ immed = exp.X_add_number;
213+ }
214+ inst |= (reg1 << RD_LOW) & RD_MASK;
215+ inst |= (immed << IMM_LOW) & IMM16_MASK;
216+ break;
217+
218 case INST_TYPE_R1_RFSL:
219 if (strcmp (op_end, ""))
220 op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */
221diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
222index d837ebb38e2..b5a78dcfe09 100644
223--- a/opcodes/microblaze-dis.c
224+++ b/opcodes/microblaze-dis.c
225@@ -130,6 +130,14 @@ get_field_imm15 (struct string_buf *buf, long instr)
226 return p;
227 }
228
229+get_field_imm16 (struct string_buf *buf, long instr)
230+{
231+ char *p = strbuf (buf);
232+
233+ sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
234+ return p;
235+}
236+
237 static char *
238 get_field_special (struct string_buf *buf, long instr,
239 const struct op_code_struct *op)
240@@ -457,6 +465,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
241 /* For mbar 16 or sleep insn. */
242 case INST_TYPE_NONE:
243 break;
244+ case INST_TYPE_RD_IMML:
245+ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
246+ break;
247 /* For bit field insns. */
248 case INST_TYPE_RD_R1_IMMW_IMMS:
249 print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
250diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
251index 6b25d12dace..82da7f1179a 100644
252--- a/opcodes/microblaze-opc.h
253+++ b/opcodes/microblaze-opc.h
254@@ -69,6 +69,7 @@
255 #define INST_TYPE_RD_R1_IMMW_IMMS 21
256
257 #define INST_TYPE_NONE 25
258+#define INST_TYPE_RD_IMML 26
259
260
261
262@@ -84,6 +85,7 @@
263 #define IMMVAL_MASK_MFS 0x0000
264
265 #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
266+#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
267 #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
268 #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
269 #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
270@@ -106,6 +108,33 @@
271 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
272 #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
273
274+/*Defines to identify 64-bit single reg instructions */
275+#define ADDLI_ONE_REG_MASK 0x68000000
276+#define ADDLIC_ONE_REG_MASK 0x68020000
277+#define ADDLIK_ONE_REG_MASK 0x68040000
278+#define ADDLIKC_ONE_REG_MASK 0x68060000
279+#define RSUBLI_ONE_REG_MASK 0x68010000
280+#define RSUBLIC_ONE_REG_MASK 0x68030000
281+#define RSUBLIK_ONE_REG_MASK 0x68050000
282+#define RSUBLIKC_ONE_REG_MASK 0x68070000
283+#define ORLI_ONE_REG_MASK 0x68100000
284+#define ANDLI_ONE_REG_MASK 0x68110000
285+#define XORLI_ONE_REG_MASK 0x68120000
286+#define ANDLNI_ONE_REG_MASK 0x68130000
287+#define ADDLI_MASK 0x20000000
288+#define ADDLIC_MASK 0x28000000
289+#define ADDLIK_MASK 0x30000000
290+#define ADDLIKC_MASK 0x38000000
291+#define RSUBLI_MASK 0x24000000
292+#define RSUBLIC_MASK 0x2C000000
293+#define RSUBLIK_MASK 0x34000000
294+#define RSUBLIKC_MASK 0x3C000000
295+#define ANDLI_MASK 0xA4000000
296+#define ANDLNI_MASK 0xAC000000
297+#define ORLI_MASK 0xA0000000
298+#define XORLI_MASK 0xA8000000
299+
300+
301 /* New Mask for msrset, msrclr insns. */
302 #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
303 /* Mask for mbar insn. */
304@@ -114,7 +143,7 @@
305 #define DELAY_SLOT 1
306 #define NO_DELAY_SLOT 0
307
308-#define MAX_OPCODES 412
309+#define MAX_OPCODES 424
310
311 const struct op_code_struct
312 {
313@@ -444,13 +473,21 @@ const struct op_code_struct
314 {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
315 {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
316 {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
317+ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
318 {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
319+ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
320 {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
321+ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
322 {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
323+ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
324 {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
325+ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
326 {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
327+ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
328 {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
329+ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
330 {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
331+ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
332 {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
333 {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
334 {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
335@@ -501,9 +538,13 @@ const struct op_code_struct
336 {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
337 {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
338 {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
339+ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
340 {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
341+ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
342 {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
343+ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
344 {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
345+ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
346 {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
347 {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
348 {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
349diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
350index b242ea73c7b..5c44a5ff0ac 100644
351--- a/opcodes/microblaze-opcm.h
352+++ b/opcodes/microblaze-opcm.h
353@@ -62,7 +62,9 @@ enum microblaze_instr
354 eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
355
356 /* 64-bit instructions */
357- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
358+ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
359+ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
360+ andli, andnli, orli, xorli,
361 bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
362 andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
363 brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
364@@ -167,5 +169,6 @@ enum microblaze_instr_type
365
366 /* Imm mask for msrset, msrclr instructions. */
367 #define IMM15_MASK 0x00007FFF
368+#define IMM16_MASK 0x0000FFFF
369
370 #endif /* MICROBLAZE-OPCM */
371--
3722.37.1 (Apple Git-137.1)
373
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-18 02:47:37 +0000