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-rw-r--r--meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch369
1 files changed, 369 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 00000000..0b8c83cd
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0023-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,369 @@
1From 3c197b12c4b680a230e8350ecd9a523be804fe3c Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Fri, 23 Aug 2019 16:18:43 +0530
4Subject: [PATCH 23/34] Added support to new arithmetic single register
5 instructions
6
7Conflicts:
8 opcodes/microblaze-dis.c
9
10Conflicts:
11 gas/config/tc-microblaze.c
12 opcodes/microblaze-dis.c
13
14Conflicts:
15 gas/config/tc-microblaze.c
16signed-off-by:Nagaraju <nmekala@xilinx.com>
17 Mahesh <mbodapat@xilinx.com>
18---
19 gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
20 opcodes/microblaze-dis.c | 11 +++
21 opcodes/microblaze-opc.h | 43 ++++++++++-
22 opcodes/microblaze-opcm.h | 5 +-
23 4 files changed, 200 insertions(+), 6 deletions(-)
24
25diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
26index a1fb6ccbd44..27544b60ea3 100644
27--- a/gas/config/tc-microblaze.c
28+++ b/gas/config/tc-microblaze.c
29@@ -423,12 +423,33 @@ void
30 md_begin (void)
31 {
32 const struct op_code_struct * opcode;
33+ const char *prev_name = "";
34
35 opcode_hash_control = str_htab_create ();
36
37 /* Insert unique names into hash table. */
38- for (opcode = microblaze_opcodes; opcode->name; opcode ++)
39- str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
40+ for (opcode = (struct microblaze_opcodes *)microblaze_opcodes; opcode->name; opcode ++)
41+ {
42+ if (strcmp (prev_name, opcode->name))
43+ {
44+ prev_name = (char *) opcode->name;
45+ str_hash_insert (opcode_hash_control, opcode->name, opcode, 0);
46+ }
47+ }
48+}
49+
50+static int
51+is_reg (char * s)
52+{
53+ int is_reg = 0;
54+ /* Strip leading whitespace. */
55+ while (ISSPACE (* s))
56+ ++ s;
57+ if (TOLOWER (s[0]) == 'r')
58+ {
59+ is_reg =1;
60+ }
61+ return is_reg;
62 }
63
64 /* Try to parse a reg name. */
65@@ -986,6 +1007,7 @@ md_assemble (char * str)
66 {
67 char * op_start;
68 char * op_end;
69+ char * temp_op_end;
70 struct op_code_struct * opcode, *opcode1;
71 char * output = NULL;
72 int nlen = 0;
73@@ -996,9 +1018,10 @@ md_assemble (char * str)
74 unsigned reg3;
75 unsigned isize;
76 unsigned long immed = 0, immed2 = 0, temp;
77- expressionS exp;
78+ expressionS exp,exp1;
79 char name[20];
80 long immedl;
81+ int reg=0;
82
83 /* Drop leading whitespace. */
84 while (ISSPACE (* str))
85@@ -1029,7 +1052,78 @@ md_assemble (char * str)
86 as_bad (_("unknown opcode \"%s\""), name);
87 return;
88 }
89-
90+
91+ if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
92+ streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli")
93+ || streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc")
94+ || streq (name, "andli") || streq (name, "andnli") || streq (name, "orli")
95+ || streq (name, "xorli")))
96+ {
97+ temp_op_end = op_end;
98+ if (strcmp (temp_op_end, ""))
99+ temp_op_end = parse_reg (temp_op_end + 1, &reg1); /* Get rd. */
100+ if (strcmp (temp_op_end, ""))
101+ reg = is_reg (temp_op_end + 1);
102+ if (reg)
103+ {
104+
105+ opcode->inst_type=INST_TYPE_RD_R1_IMML;
106+ opcode->inst_offset_type = OPCODE_MASK_H;
107+ if (streq (name, "addli"))
108+ opcode->bit_sequence = ADDLI_MASK;
109+ else if (streq (name, "addlic"))
110+ opcode->bit_sequence = ADDLIC_MASK;
111+ else if (streq (name, "addlik"))
112+ opcode->bit_sequence = ADDLIK_MASK;
113+ else if (streq (name, "addlikc"))
114+ opcode->bit_sequence = ADDLIKC_MASK;
115+ else if (streq (name, "rsubli"))
116+ opcode->bit_sequence = RSUBLI_MASK;
117+ else if (streq (name, "rsublic"))
118+ opcode->bit_sequence = RSUBLIC_MASK;
119+ else if (streq (name, "rsublik"))
120+ opcode->bit_sequence = RSUBLIK_MASK;
121+ else if (streq (name, "rsublikc"))
122+ opcode->bit_sequence = RSUBLIKC_MASK;
123+ else if (streq (name, "andli"))
124+ opcode->bit_sequence = ANDLI_MASK;
125+ else if (streq (name, "andnli"))
126+ opcode->bit_sequence = ANDLNI_MASK;
127+ else if (streq (name, "orli"))
128+ opcode->bit_sequence = ORLI_MASK;
129+ else if (streq (name, "xorli"))
130+ opcode->bit_sequence = XORLI_MASK;
131+ }
132+ else
133+ {
134+ opcode->inst_type=INST_TYPE_RD_IMML;
135+ opcode->inst_offset_type = OPCODE_MASK_LIMM;
136+ if (streq (name, "addli"))
137+ opcode->bit_sequence = ADDLI_ONE_REG_MASK;
138+ else if (streq (name, "addlic"))
139+ opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
140+ else if (streq (name, "addlik"))
141+ opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
142+ else if (streq (name, "addlikc"))
143+ opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
144+ else if (streq (name, "rsubli"))
145+ opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
146+ else if (streq (name, "rsublic"))
147+ opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
148+ else if (streq (name, "rsublik"))
149+ opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
150+ else if (streq (name, "rsublikc"))
151+ opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
152+ else if (streq (name, "andli"))
153+ opcode->bit_sequence = ANDLI_ONE_REG_MASK;
154+ else if (streq (name, "andnli"))
155+ opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
156+ else if (streq (name, "orli"))
157+ opcode->bit_sequence = ORLI_ONE_REG_MASK;
158+ else if (streq (name, "xorli"))
159+ opcode->bit_sequence = XORLI_ONE_REG_MASK;
160+ }
161+ }
162 inst = opcode->bit_sequence;
163 isize = 4;
164
165@@ -1486,6 +1580,51 @@ md_assemble (char * str)
166 inst |= (immed << IMM_LOW) & IMM15_MASK;
167 break;
168
169+ case INST_TYPE_RD_IMML:
170+ if (strcmp (op_end, ""))
171+ op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
172+ else
173+ {
174+ as_fatal (_("Error in statement syntax"));
175+ reg1 = 0;
176+ }
177+
178+ if (strcmp (op_end, ""))
179+ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
180+ else
181+ as_fatal (_("Error in statement syntax"));
182+
183+ /* Check for spl registers. */
184+ if (check_spl_reg (&reg1))
185+ as_fatal (_("Cannot use special register with this instruction"));
186+ if (exp.X_op != O_constant)
187+ {
188+ char *opc = NULL;
189+ relax_substateT subtype;
190+
191+ if (exp.X_md != 0)
192+ subtype = get_imm_otype(exp.X_md);
193+ else
194+ subtype = opcode->inst_offset_type;
195+
196+ output = frag_var (rs_machine_dependent,
197+ isize * 2,
198+ isize * 2,
199+ subtype,
200+ exp.X_add_symbol,
201+ exp.X_add_number,
202+ (char *) opc);
203+ immedl = 0L;
204+ }
205+ else
206+ {
207+ output = frag_more (isize);
208+ immed = exp.X_add_number;
209+ }
210+ inst |= (reg1 << RD_LOW) & RD_MASK;
211+ inst |= (immed << IMM_LOW) & IMM16_MASK;
212+ break;
213+
214 case INST_TYPE_R1_RFSL:
215 if (strcmp (op_end, ""))
216 op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */
217diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
218index d837ebb38e2..b5a78dcfe09 100644
219--- a/opcodes/microblaze-dis.c
220+++ b/opcodes/microblaze-dis.c
221@@ -130,6 +130,14 @@ get_field_imm15 (struct string_buf *buf, long instr)
222 return p;
223 }
224
225+get_field_imm16 (struct string_buf *buf, long instr)
226+{
227+ char *p = strbuf (buf);
228+
229+ sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
230+ return p;
231+}
232+
233 static char *
234 get_field_special (struct string_buf *buf, long instr,
235 const struct op_code_struct *op)
236@@ -457,6 +465,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
237 /* For mbar 16 or sleep insn. */
238 case INST_TYPE_NONE:
239 break;
240+ case INST_TYPE_RD_IMML:
241+ print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
242+ break;
243 /* For bit field insns. */
244 case INST_TYPE_RD_R1_IMMW_IMMS:
245 print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
246diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
247index 6b25d12dace..82da7f1179a 100644
248--- a/opcodes/microblaze-opc.h
249+++ b/opcodes/microblaze-opc.h
250@@ -69,6 +69,7 @@
251 #define INST_TYPE_RD_R1_IMMW_IMMS 21
252
253 #define INST_TYPE_NONE 25
254+#define INST_TYPE_RD_IMML 26
255
256
257
258@@ -84,6 +85,7 @@
259 #define IMMVAL_MASK_MFS 0x0000
260
261 #define OPCODE_MASK_H 0xFC000000 /* High 6 bits only. */
262+#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
263 #define OPCODE_MASK_H1 0xFFE00000 /* High 11 bits. */
264 #define OPCODE_MASK_H2 0xFC1F0000 /* High 6 and bits 20-16. */
265 #define OPCODE_MASK_H12 0xFFFF0000 /* High 16. */
266@@ -106,6 +108,33 @@
267 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
268 #define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */
269
270+/*Defines to identify 64-bit single reg instructions */
271+#define ADDLI_ONE_REG_MASK 0x68000000
272+#define ADDLIC_ONE_REG_MASK 0x68020000
273+#define ADDLIK_ONE_REG_MASK 0x68040000
274+#define ADDLIKC_ONE_REG_MASK 0x68060000
275+#define RSUBLI_ONE_REG_MASK 0x68010000
276+#define RSUBLIC_ONE_REG_MASK 0x68030000
277+#define RSUBLIK_ONE_REG_MASK 0x68050000
278+#define RSUBLIKC_ONE_REG_MASK 0x68070000
279+#define ORLI_ONE_REG_MASK 0x68100000
280+#define ANDLI_ONE_REG_MASK 0x68110000
281+#define XORLI_ONE_REG_MASK 0x68120000
282+#define ANDLNI_ONE_REG_MASK 0x68130000
283+#define ADDLI_MASK 0x20000000
284+#define ADDLIC_MASK 0x28000000
285+#define ADDLIK_MASK 0x30000000
286+#define ADDLIKC_MASK 0x38000000
287+#define RSUBLI_MASK 0x24000000
288+#define RSUBLIC_MASK 0x2C000000
289+#define RSUBLIK_MASK 0x34000000
290+#define RSUBLIKC_MASK 0x3C000000
291+#define ANDLI_MASK 0xA4000000
292+#define ANDLNI_MASK 0xAC000000
293+#define ORLI_MASK 0xA0000000
294+#define XORLI_MASK 0xA8000000
295+
296+
297 /* New Mask for msrset, msrclr insns. */
298 #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */
299 /* Mask for mbar insn. */
300@@ -114,7 +143,7 @@
301 #define DELAY_SLOT 1
302 #define NO_DELAY_SLOT 0
303
304-#define MAX_OPCODES 412
305+#define MAX_OPCODES 424
306
307 const struct op_code_struct
308 {
309@@ -444,13 +473,21 @@ const struct op_code_struct
310 {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
311 {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
312 {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
313+ {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
314 {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
315+ {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
316 {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
317+ {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
318 {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
319+ {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
320 {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
321+ {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
322 {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
323+ {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
324 {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
325+ {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
326 {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */
327+ {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
328 {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
329 {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
330 {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
331@@ -501,9 +538,13 @@ const struct op_code_struct
332 {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
333 {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
334 {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
335+ {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
336 {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
337+ {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
338 {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
339+ {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
340 {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */
341+ {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
342 {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
343 {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
344 {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
345diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
346index b242ea73c7b..5c44a5ff0ac 100644
347--- a/opcodes/microblaze-opcm.h
348+++ b/opcodes/microblaze-opcm.h
349@@ -62,7 +62,9 @@ enum microblaze_instr
350 eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
351
352 /* 64-bit instructions */
353- addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
354+ addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
355+ addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
356+ andli, andnli, orli, xorli,
357 bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
358 andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
359 brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
360@@ -167,5 +169,6 @@ enum microblaze_instr_type
361
362 /* Imm mask for msrset, msrclr instructions. */
363 #define IMM15_MASK 0x00007FFF
364+#define IMM16_MASK 0x0000FFFF
365
366 #endif /* MICROBLAZE-OPCM */
367--
3682.37.1 (Apple Git-137.1)
369
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-09 13:05:20 +0000