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-rw-r--r--meta-microblaze/recipes-devtools/binutils/binutils/0008-Add-new-bit-field-instructions.patch241
1 files changed, 241 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/binutils/binutils/0008-Add-new-bit-field-instructions.patch b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..3966566d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/binutils/binutils/0008-Add-new-bit-field-instructions.patch
@@ -0,0 +1,241 @@
1From c02813b6a27e6eed281609e5d696bb67ac74c804 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Mon, 18 Jul 2016 12:24:28 +0530
4Subject: [PATCH 08/34] Add new bit-field instructions
5
6This patches adds new bsefi and bsifi instructions.
7BSEFI- The instruction shall extract a bit field from a
8register and place it right-adjusted in the destination register.
9The other bits in the destination register shall be set to zero
10BSIFI- The instruction shall insert a right-adjusted bit field
11from a register at another position in the destination register.
12The rest of the bits in the destination register shall be unchanged
13
14Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
15
16Conflicts:
17 opcodes/microblaze-dis.c
18
19Conflicts:
20 gas/config/tc-microblaze.c
21 opcodes/microblaze-opc.h
22---
23 gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
24 opcodes/microblaze-dis.c | 20 +++++++++--
25 opcodes/microblaze-opc.h | 12 ++++++-
26 opcodes/microblaze-opcm.h | 6 +++-
27 4 files changed, 104 insertions(+), 5 deletions(-)
28
29diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
30index 8018d1f5686..1cb9b2519c3 100644
31--- a/gas/config/tc-microblaze.c
32+++ b/gas/config/tc-microblaze.c
33@@ -917,7 +917,7 @@ md_assemble (char * str)
34 unsigned reg2;
35 unsigned reg3;
36 unsigned isize;
37- unsigned int immed = 0, temp;
38+ unsigned int immed = 0, immed2 = 0, temp;
39 expressionS exp;
40 char name[20];
41
42@@ -1178,7 +1178,76 @@ md_assemble (char * str)
43 inst |= (reg2 << RA_LOW) & RA_MASK;
44 inst |= (immed << IMM_LOW) & IMM5_MASK;
45 break;
46+ case INST_TYPE_RD_R1_IMM5_IMM5:
47+ if (strcmp (op_end, ""))
48+ op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
49+ else
50+ {
51+ as_fatal (_("Error in statement syntax"));
52+ reg1 = 0;
53+ }
54+ if (strcmp (op_end, ""))
55+ op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
56+ else
57+ {
58+ as_fatal (_("Error in statement syntax"));
59+ reg2 = 0;
60+ }
61+
62+ /* Check for spl registers. */
63+ if (check_spl_reg (&reg1))
64+ as_fatal (_("Cannot use special register with this instruction"));
65+ if (check_spl_reg (&reg2))
66+ as_fatal (_("Cannot use special register with this instruction"));
67
68+ /* Width immediate value. */
69+ if (strcmp (op_end, ""))
70+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
71+ else
72+ as_fatal (_("Error in statement syntax"));
73+ if (exp.X_op != O_constant)
74+ {
75+ as_warn (_("Symbol used as immediate width value for bit field instruction"));
76+ immed = 1;
77+ }
78+ else
79+ immed = exp.X_add_number;
80+ if (opcode->instr == bsefi && immed > 31)
81+ as_fatal (_("Width value must be less than 32"));
82+
83+ /* Shift immediate value. */
84+ if (strcmp (op_end, ""))
85+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
86+ else
87+ as_fatal (_("Error in statement syntax"));
88+ if (exp.X_op != O_constant)
89+ {
90+ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
91+ immed2 = 0;
92+ }
93+ else
94+ {
95+ output = frag_more (isize);
96+ immed2 = exp.X_add_number;
97+ }
98+ if (immed2 != (immed2 % 32))
99+ {
100+ as_warn (_("Shift value greater than 32. using <value %% 32>"));
101+ immed2 = immed2 % 32;
102+ }
103+
104+ /* Check combined value. */
105+ if (immed + immed2 > 32)
106+ as_fatal (_("Width value + shift value must not be greater than 32"));
107+
108+ inst |= (reg1 << RD_LOW) & RD_MASK;
109+ inst |= (reg2 << RA_LOW) & RA_MASK;
110+ if (opcode->instr == bsefi)
111+ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
112+ else
113+ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
114+ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
115+ break;
116 case INST_TYPE_R1_R2:
117 if (strcmp (op_end, ""))
118 op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */
119diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
120index b057492ba93..f57b98fc9f7 100644
121--- a/opcodes/microblaze-dis.c
122+++ b/opcodes/microblaze-dis.c
123@@ -91,7 +91,19 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
124 }
125
126 static char *
127-get_field_rfsl (struct string_buf *buf, long instr)
128+get_field_imm5width (struct string_buf *buf, long instr)
129+{
130+ char *p = strbuf (buf);
131+
132+ if (instr & 0x00004000)
133+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
134+ else
135+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
136+ return p;
137+}
138+
139+static char *
140+get_field_rfsl (struct string_buf *buf,long instr)
141 {
142 char *p = strbuf (buf);
143
144@@ -427,7 +439,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
145 /* For mbar 16 or sleep insn. */
146 case INST_TYPE_NONE:
147 break;
148- /* For tuqula instruction */
149+ /* For bit field insns. */
150+ case INST_TYPE_RD_R1_IMM5_IMM5:
151+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
152+ break;
153+ /* For tuqula instruction */
154 case INST_TYPE_RD:
155 print_func (stream, "\t%s", get_field_rd (&buf, inst));
156 break;
157diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
158index d3f8e36199e..825c639a41e 100644
159--- a/opcodes/microblaze-opc.h
160+++ b/opcodes/microblaze-opc.h
161@@ -59,6 +59,9 @@
162 /* For mbar. */
163 #define INST_TYPE_IMM5 20
164
165+/* For bsefi and bsifi */
166+#define INST_TYPE_RD_R1_IMM5_IMM5 21
167+
168 #define INST_TYPE_NONE 25
169
170
171@@ -89,7 +92,9 @@
172 #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
173 #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
174 #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
175+#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
176 #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
177+#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
178 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
179 #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
180 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
181@@ -102,7 +107,7 @@
182 #define DELAY_SLOT 1
183 #define NO_DELAY_SLOT 0
184
185-#define MAX_OPCODES 291
186+#define MAX_OPCODES 301
187
188 const struct op_code_struct
189 {
190@@ -159,6 +164,8 @@ const struct op_code_struct
191 {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
192 {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
193 {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
194+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
195+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
196 {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
197 {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
198 {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
199@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
200 #define MIN_IMM5 ((int) 0x00000000)
201 #define MAX_IMM5 ((int) 0x0000001f)
202
203+#define MIN_IMM_WIDTH ((int) 0x00000001)
204+#define MAX_IMM_WIDTH ((int) 0x00000020)
205+
206 #endif /* MICROBLAZE_OPC */
207
208diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
209index ad964560c17..aa3401610d9 100644
210--- a/opcodes/microblaze-opcm.h
211+++ b/opcodes/microblaze-opcm.h
212@@ -29,7 +29,7 @@ enum microblaze_instr
213 addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
214 mulh, mulhu, mulhsu,swapb,swaph,
215 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
216- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
217+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
218 /* 'or/and/xor' are C++ keywords. */
219 microblaze_or, microblaze_and, microblaze_xor,
220 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
221@@ -130,6 +130,7 @@ enum microblaze_instr_type
222 #define RB_LOW 11 /* Low bit for RB. */
223 #define IMM_LOW 0 /* Low bit for immediate. */
224 #define IMM_MBAR 21 /* low bit for mbar instruction. */
225+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
226
227 #define RD_MASK 0x03E00000
228 #define RA_MASK 0x001F0000
229@@ -142,6 +143,9 @@ enum microblaze_instr_type
230 /* Imm mask for mbar. */
231 #define IMM5_MBAR_MASK 0x03E00000
232
233+/* Imm mask for extract/insert width. */
234+#define IMM5_WIDTH_MASK 0x000007C0
235+
236 /* FSL imm mask for get, put instructions. */
237 #define RFSL_MASK 0x000000F
238
239--
2402.37.1 (Apple Git-137.1)
241
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-09 06:56:00 +0000