diff options
author | Nathan Rossi <nathan.rossi@xilinx.com> | 2014-04-09 10:43:56 +1000 |
---|---|---|
committer | Nathan Rossi <nathan.rossi@xilinx.com> | 2014-04-09 11:19:16 +1000 |
commit | becbfa08d248cd64e970d369661946767dda225c (patch) | |
tree | aa9b0f769069bfe7068d78e81427418457bbb10a /recipes-devtools | |
parent | 0c3b0e951c702a24eaf271b769b816b7c5305a00 (diff) | |
download | meta-xilinx-becbfa08d248cd64e970d369661946767dda225c.tar.gz |
qemu: Add patch to resolve MicroBlaze ethernet phy issues
* Add patch to resolve phy soft reset functionality which is relied on
by newer kernel versions
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Diffstat (limited to 'recipes-devtools')
-rw-r--r-- | recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch | 29 | ||||
-rw-r--r-- | recipes-devtools/qemu/qemu_1.7.0.bbappend | 1 |
2 files changed, 30 insertions, 0 deletions
diff --git a/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch b/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch new file mode 100644 index 00000000..9bc7a564 --- /dev/null +++ b/recipes-devtools/qemu/files/hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch | |||
@@ -0,0 +1,29 @@ | |||
1 | From 425580f9241098c9ef554a33b80153624b1e0318 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nathan Rossi <nathan.rossi@xilinx.com> | ||
3 | Date: Wed, 9 Apr 2014 11:15:25 +1000 | ||
4 | Subject: [PATCH] hw/net/xilinx_axienet.c: Add phy soft reset bit clearing | ||
5 | |||
6 | * Clear the BMCR Reset when writing to registers. | ||
7 | |||
8 | Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> | ||
9 | --- | ||
10 | hw/net/xilinx_axienet.c | 3 +++ | ||
11 | 1 file changed, 3 insertions(+) | ||
12 | |||
13 | diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c | ||
14 | index 3eb7715..d9c15df 100644 | ||
15 | --- a/hw/net/xilinx_axienet.c | ||
16 | +++ b/hw/net/xilinx_axienet.c | ||
17 | @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int data) | ||
18 | phy->regs[regnum] = data; | ||
19 | break; | ||
20 | } | ||
21 | + | ||
22 | + /* Unconditionally clear regs[BMCR][BMCR_RESET] */ | ||
23 | + phy->regs[0] &= ~0x8000; | ||
24 | } | ||
25 | |||
26 | static void | ||
27 | -- | ||
28 | 1.9.0 | ||
29 | |||
diff --git a/recipes-devtools/qemu/qemu_1.7.0.bbappend b/recipes-devtools/qemu/qemu_1.7.0.bbappend index 4637cf0d..a06eefef 100644 --- a/recipes-devtools/qemu/qemu_1.7.0.bbappend +++ b/recipes-devtools/qemu/qemu_1.7.0.bbappend | |||
@@ -5,4 +5,5 @@ SRC_URI_append += " \ | |||
5 | file://HACK_target-arm_Harcode_the_SCU_offset.patch \ | 5 | file://HACK_target-arm_Harcode_the_SCU_offset.patch \ |
6 | file://HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch \ | 6 | file://HACK_zynq_slcr_Bring_SLCR_out_of_reset_in_kernel_state.patch \ |
7 | file://qom_object_c_Split_out_object_and_class_caches.patch \ | 7 | file://qom_object_c_Split_out_object_and_class_caches.patch \ |
8 | file://hw-net-xilinx_axienet.c-Add-phy-soft-reset-bit-clear.patch \ | ||
8 | " | 9 | " |