qemu_zynqmp: Update SRCREV and Patches

* Update SRCREV to point to newest master
* Update patches based on patches that are on qemu-devel at v4

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>

21 files changed, 529 insertions, 475 deletions

diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch
index 779e8c42..f759f27b 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch
@@ -1,7 +1,10 @@
-From 17c53bfa9ce6bb75f9ff55722bc02e4050a148c1 Mon Sep 17 00:00:00 2001
+From 56489633015d2ac71d680bdd27accbd6f87b4fe3 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:38 -0800
+Date: Mon, 23 Mar 2015 04:05:11 -0700
 Subject: [PATCH 01/15] target-arm: cpu64: Factor out ARM cortex init
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
 In preparation for support for Cortex a53. Use "axx" to describe the
 shareable features. Some of the CP15 registers (such as ACTLR) are
@@ -13,13 +16,14 @@ The cache sizes and geometeries, the L1 I-cache policy and the physical
 address range differ between A53 and A57 so those particulars are left
 as A57 specific. The rest are moved to the generalisation.
 
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- target-arm/cpu64.c | 32 +++++++++++++++++++-------------
- 1 file changed, 19 insertions(+), 13 deletions(-)
+ target-arm/cpu64.c |   34 ++++++++++++++++++++--------------
+ 1 file changed, 20 insertions(+), 14 deletions(-)
 
 diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
-index 823c739..5cf3121 100644
+index 270bc2f..3eb58c6 100644
 --- a/target-arm/cpu64.c
 +++ b/target-arm/cpu64.c
 @@ -38,22 +38,22 @@ static inline void unset_feature(CPUARMState *env, int feature)
@@ -49,7 +53,7 @@ index 823c739..5cf3121 100644
        .writefn = arm_cp_write_ignore },
  #endif
      { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
-@@ -92,10 +92,8 @@ static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
+@@ -92,11 +92,8 @@ static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
      REGINFO_SENTINEL
  };
  
@@ -58,10 +62,11 @@ index 823c739..5cf3121 100644
  {
 -    ARMCPU *cpu = ARM_CPU(obj);
 -
+-    cpu->dtb_compatible = "arm,cortex-a57";
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_VFP4);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
-@@ -107,13 +105,10 @@ static void aarch64_a57_initfn(Object *obj)
+@@ -108,13 +105,10 @@ static void aarch64_a57_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
      set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
      set_feature(&cpu->env, ARM_FEATURE_CRC);
@@ -75,7 +80,7 @@ index 823c739..5cf3121 100644
      cpu->reset_sctlr = 0x00c50838;
      cpu->id_pfr0 = 0x00000131;
      cpu->id_pfr1 = 0x00011011;
-@@ -132,14 +127,25 @@ static void aarch64_a57_initfn(Object *obj)
+@@ -133,14 +127,26 @@ static void aarch64_a57_initfn(Object *obj)
      cpu->id_aa64pfr0 = 0x00002222;
      cpu->id_aa64dfr0 = 0x10305106;
      cpu->id_aa64isar0 = 0x00011120;
@@ -92,6 +97,7 @@ index 823c739..5cf3121 100644
 +
 +    aarch64_axx_initfn(cpu);
 +
++    cpu->dtb_compatible = "arm,cortex-a57";
 +    cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
 +    cpu->midr = 0x411fd070;
 +    cpu->ctr = 0x8444c004; /* L1Ip = PIPT */
@@ -105,5 +111,5 @@ index 823c739..5cf3121 100644
  
  #ifdef CONFIG_USER_ONLY
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
index 4723bd2b..290f2870 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
@@ -1,23 +1,27 @@
-From 2390e80ace413722b0d41500c1927d78b2a0154b Mon Sep 17 00:00:00 2001
+From a69dfd5611a5671ff6163d3368d3628152251b04 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:39 -0800
+Date: Mon, 23 Mar 2015 04:05:11 -0700
 Subject: [PATCH 02/15] target-arm: cpu64: Add support for cortex-a53
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
 Similar to a53, but with different L1 I cache policy, phys addr size and
 different cache geometries. The cache sizes is implementation
 configurable, but use these values (from Xilinx MPSoC) as a default
 until cache size configurability is added.
 
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- target-arm/cpu64.c | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
+ target-arm/cpu64.c |   16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
 
 diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
-index 5cf3121..0b9728e 100644
+index 3eb58c6..728d9a7 100644
 --- a/target-arm/cpu64.c
 +++ b/target-arm/cpu64.c
-@@ -148,6 +148,20 @@ static void aarch64_a57_initfn(Object *obj)
+@@ -149,6 +149,21 @@ static void aarch64_a57_initfn(Object *obj)
      cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
  }
  
@@ -27,6 +31,7 @@ index 5cf3121..0b9728e 100644
 +
 +    aarch64_axx_initfn(cpu);
 +
++    cpu->dtb_compatible = "arm,cortex-a53";
 +    cpu->midr = 0x410fd034;
 +    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
 +    cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
@@ -38,7 +43,7 @@ index 5cf3121..0b9728e 100644
  #ifdef CONFIG_USER_ONLY
  static void aarch64_any_initfn(Object *obj)
  {
-@@ -175,6 +189,7 @@ typedef struct ARMCPUInfo {
+@@ -176,6 +191,7 @@ typedef struct ARMCPUInfo {
  
  static const ARMCPUInfo aarch64_cpus[] = {
      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
@@ -47,5 +52,5 @@ index 5cf3121..0b9728e 100644
      { .name = "any",         .initfn = aarch64_any_initfn },
  #endif
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-Zynq-MPSoC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch
index fdff7c17..eb5740e0 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-Zynq-MPSoC.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch
@@ -1,22 +1,23 @@
-From 37b74b0626d6403da8d9b946d77d29296bc47bcc Mon Sep 17 00:00:00 2001
+From 7f403cd27dbef216c77faa32d015965dfa5fe34e Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:42 -0800
-Subject: [PATCH 03/15] arm: Introduce Xilinx Zynq MPSoC
+Date: Mon, 23 Mar 2015 04:05:13 -0700
+Subject: [PATCH 03/15] arm: Introduce Xilinx ZynqMP SoC
 
 With quad Cortex-A53 CPUs.
 
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 ---
- default-configs/aarch64-softmmu.mak |  2 +-
- hw/arm/Makefile.objs                |  1 +
- hw/arm/xlnx-zynq-mp.c               | 71 +++++++++++++++++++++++++++++++++++++
- include/hw/arm/xlnx-zynq-mp.h       | 21 +++++++++++
- 4 files changed, 94 insertions(+), 1 deletion(-)
- create mode 100644 hw/arm/xlnx-zynq-mp.c
- create mode 100644 include/hw/arm/xlnx-zynq-mp.h
+ default-configs/aarch64-softmmu.mak |    2 +-
+ hw/arm/Makefile.objs                |    1 +
+ hw/arm/xlnx-zynqmp.c                |   72 +++++++++++++++++++++++++++++++++++
+ include/hw/arm/xlnx-zynqmp.h        |   21 ++++++++++
+ 4 files changed, 95 insertions(+), 1 deletion(-)
+ create mode 100644 hw/arm/xlnx-zynqmp.c
+ create mode 100644 include/hw/arm/xlnx-zynqmp.h
 
 diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
-index 6d3b5c7..a8011e0 100644
+index 6d3b5c7..96dd994 100644
 --- a/default-configs/aarch64-softmmu.mak
 +++ b/default-configs/aarch64-softmmu.mak
 @@ -3,4 +3,4 @@
@@ -24,22 +25,22 @@ index 6d3b5c7..a8011e0 100644
  include arm-softmmu.mak
  
 -# Currently no 64-bit specific config requirements
-+CONFIG_XLNX_ZYNQ_MP=y
++CONFIG_XLNX_ZYNQMP=y
 diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
-index 6088e53..9bf072b 100644
+index 2577f68..d7cd5f4 100644
 --- a/hw/arm/Makefile.objs
 +++ b/hw/arm/Makefile.objs
-@@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
- obj-$(CONFIG_DIGIC) += digic.o
+@@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
  obj-y += omap1.o omap2.o strongarm.o
  obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
-+obj-$(CONFIG_XLNX_ZYNQ_MP) += xlnx-zynq-mp.o
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
+ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
++obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
 new file mode 100644
-index 0000000..d553fb0
+index 0000000..41c207a
 --- /dev/null
-+++ b/hw/arm/xlnx-zynq-mp.c
-@@ -0,0 +1,71 @@
++++ b/hw/arm/xlnx-zynqmp.c
+@@ -0,0 +1,72 @@
 +/*
 + * Xilinx Zynq MPSoC emulation
 + *
@@ -57,17 +58,18 @@ index 0000000..d553fb0
 + * for more details.
 + */
 +
-+#include "hw/arm/xlnx-zynq-mp.h"
++#include "hw/arm/xlnx-zynqmp.h"
 +
-+static void xlnx_zynq_mp_init(Object *obj)
++static void xlnx_zynqmp_init(Object *obj)
 +{
-+    XlnxZynqMPState *s = XLNX_ZYNQ_MP(obj);
++    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
 +    int i;
 +
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_CPUS; i++) {
++    for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
 +        object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
 +                          "cortex-a53-" TYPE_ARM_CPU);
-+        object_property_add_child(obj, "cpu", OBJECT(&s->cpu[i]), NULL);
++        object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
++                                  &error_abort);
 +    }
 +}
 +
@@ -78,66 +80,66 @@ index 0000000..d553fb0
 +    } \
 +} while (0)
 +
-+static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
++static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 +{
-+    XlnxZynqMPState *s = XLNX_ZYNQ_MP(dev);
++    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
 +    uint8_t i;
 +    Error *err = NULL;
 +
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_CPUS; i++) {
++    for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
 +        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
 +        ERR_PROP_CHECK_RETURN(err, errp);
 +    }
 +}
 +
-+static void xlnx_zynq_mp_class_init(ObjectClass *oc, void *data)
++static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
-+    dc->realize = xlnx_zynq_mp_realize;
++    dc->realize = xlnx_zynqmp_realize;
 +}
 +
-+static const TypeInfo xlnx_zynq_mp_type_info = {
-+    .name = TYPE_XLNX_ZYNQ_MP,
++static const TypeInfo xlnx_zynqmp_type_info = {
++    .name = TYPE_XLNX_ZYNQMP,
 +    .parent = TYPE_DEVICE,
 +    .instance_size = sizeof(XlnxZynqMPState),
-+    .instance_init = xlnx_zynq_mp_init,
-+    .class_init = xlnx_zynq_mp_class_init,
++    .instance_init = xlnx_zynqmp_init,
++    .class_init = xlnx_zynqmp_class_init,
 +};
 +
-+static void xlnx_zynq_mp_register_types(void)
++static void xlnx_zynqmp_register_types(void)
 +{
-+    type_register_static(&xlnx_zynq_mp_type_info);
++    type_register_static(&xlnx_zynqmp_type_info);
 +}
 +
-+type_init(xlnx_zynq_mp_register_types)
-diff --git a/include/hw/arm/xlnx-zynq-mp.h b/include/hw/arm/xlnx-zynq-mp.h
++type_init(xlnx_zynqmp_register_types)
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
 new file mode 100644
-index 0000000..f7410dc
+index 0000000..d6b3b92
 --- /dev/null
-+++ b/include/hw/arm/xlnx-zynq-mp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
 @@ -0,0 +1,21 @@
-+#ifndef XLNX_ZYNQ_MP_H_
++#ifndef XLNX_ZYNQMP_H_
 +
 +#include "qemu-common.h"
 +#include "hw/arm/arm.h"
 +
-+#define TYPE_XLNX_ZYNQ_MP "xlnx,zynq-mp"
-+#define XLNX_ZYNQ_MP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
-+                                       TYPE_XLNX_ZYNQ_MP)
++#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
++#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
++                                       TYPE_XLNX_ZYNQMP)
 +
-+#define XLNX_ZYNQ_MP_NUM_CPUS 4
++#define XLNX_ZYNQMP_NUM_CPUS 4
 +
 +typedef struct XlnxZynqMPState {
 +    /*< private >*/
 +    DeviceState parent_obj;
 +    /*< public >*/
 +
-+    ARMCPU cpu[XLNX_ZYNQ_MP_NUM_CPUS];
++    ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
 +}  XlnxZynqMPState;
 +
-+#define XLNX_ZYNQ_MP_H_
++#define XLNX_ZYNQMP_H_
 +#endif
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynq-mp-Add-GIC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch
index 518ca702..c9cc17c3 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynq-mp-Add-GIC.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch
@@ -1,35 +1,36 @@
-From 307b6f846c7cc878f399a34a29a9db48f32e3432 Mon Sep 17 00:00:00 2001
+From c10adfae330dababc9752d02431e8e7b098f3ce2 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:43 -0800
-Subject: [PATCH 04/15] arm: xlnx-zynq-mp: Add GIC
+Date: Mon, 23 Mar 2015 04:05:13 -0700
+Subject: [PATCH 04/15] arm: xlnx-zynqmp: Add GIC
 
 And connect IRQ outputs to the CPUs.
 
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/arm/xlnx-zynq-mp.c         | 19 +++++++++++++++++++
- include/hw/arm/xlnx-zynq-mp.h |  2 ++
+ hw/arm/xlnx-zynqmp.c         |   19 +++++++++++++++++++
+ include/hw/arm/xlnx-zynqmp.h |    2 ++
  2 files changed, 21 insertions(+)
 
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
-index d553fb0..9cdff13 100644
---- a/hw/arm/xlnx-zynq-mp.c
-+++ b/hw/arm/xlnx-zynq-mp.c
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index 41c207a..9465185 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
 @@ -17,6 +17,11 @@
  
- #include "hw/arm/xlnx-zynq-mp.h"
+ #include "hw/arm/xlnx-zynqmp.h"
  
 +#define GIC_NUM_SPI_INTR 128
 +
 +#define GIC_DIST_ADDR       0xf9010000
 +#define GIC_CPU_ADDR        0xf9020000
 +
- static void xlnx_zynq_mp_init(Object *obj)
+ static void xlnx_zynqmp_init(Object *obj)
  {
-     XlnxZynqMPState *s = XLNX_ZYNQ_MP(obj);
-@@ -27,6 +32,9 @@ static void xlnx_zynq_mp_init(Object *obj)
-                           "cortex-a53-" TYPE_ARM_CPU);
-         object_property_add_child(obj, "cpu", OBJECT(&s->cpu[i]), NULL);
+     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
+@@ -28,6 +33,9 @@ static void xlnx_zynqmp_init(Object *obj)
+         object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
+                                   &error_abort);
      }
 +
 +    object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
@@ -37,19 +38,19 @@ index d553fb0..9cdff13 100644
  }
  
  #define ERR_PROP_CHECK_RETURN(err, errp) do { \
-@@ -42,9 +50,20 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
+@@ -43,9 +51,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
      uint8_t i;
      Error *err = NULL;
  
 +    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
 +    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
-+    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQ_MP_NUM_CPUS);
++    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
 +    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
 +    ERR_PROP_CHECK_RETURN(err, errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, GIC_DIST_ADDR);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
 +
-     for (i = 0; i < XLNX_ZYNQ_MP_NUM_CPUS; i++) {
+     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
          object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
          ERR_PROP_CHECK_RETURN(err, errp);
 +
@@ -58,26 +59,26 @@ index d553fb0..9cdff13 100644
      }
  }
  
-diff --git a/include/hw/arm/xlnx-zynq-mp.h b/include/hw/arm/xlnx-zynq-mp.h
-index f7410dc..22b2af0 100644
---- a/include/hw/arm/xlnx-zynq-mp.h
-+++ b/include/hw/arm/xlnx-zynq-mp.h
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index d6b3b92..d29c7de 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
 @@ -2,6 +2,7 @@
  
  #include "qemu-common.h"
  #include "hw/arm/arm.h"
 +#include "hw/intc/arm_gic.h"
  
- #define TYPE_XLNX_ZYNQ_MP "xlnx,zynq-mp"
- #define XLNX_ZYNQ_MP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
+ #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
+ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
 @@ -15,6 +16,7 @@ typedef struct XlnxZynqMPState {
      /*< public >*/
  
-     ARMCPU cpu[XLNX_ZYNQ_MP_NUM_CPUS];
+     ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
 +    GICState gic;
  }  XlnxZynqMPState;
  
- #define XLNX_ZYNQ_MP_H_
+ #define XLNX_ZYNQMP_H_
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynq-mp-Connect-CPU-Timers-to-GIC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch
index 207dbc93..487d722c 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynq-mp-Connect-CPU-Timers-to-GIC.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch
@@ -1,20 +1,20 @@
-From c2c5018da201c9eead0dba39263eb40549064511 Mon Sep 17 00:00:00 2001
+From 6eb0b99419e4f20cef0c0af2847e1635b2dbc04e Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:44 -0800
-Subject: [PATCH 05/15] arm: xlnx-zynq-mp: Connect CPU Timers to GIC
+Date: Mon, 23 Mar 2015 04:05:14 -0700
+Subject: [PATCH 05/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC
 
 Connect the GPIO outputs from the individual CPUs for the timers to the
 GIC.
 
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/arm/xlnx-zynq-mp.c | 16 ++++++++++++++++
+ hw/arm/xlnx-zynqmp.c |   16 ++++++++++++++++
  1 file changed, 16 insertions(+)
 
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
-index 9cdff13..be82a66 100644
---- a/hw/arm/xlnx-zynq-mp.c
-+++ b/hw/arm/xlnx-zynq-mp.c
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index 9465185..29954f5 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
 @@ -19,9 +19,17 @@
  
  #define GIC_NUM_SPI_INTR 128
@@ -30,13 +30,13 @@ index 9cdff13..be82a66 100644
 +    return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
 +}
 +
- static void xlnx_zynq_mp_init(Object *obj)
+ static void xlnx_zynqmp_init(Object *obj)
  {
-     XlnxZynqMPState *s = XLNX_ZYNQ_MP(obj);
-@@ -59,11 +67,19 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
+     XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
+@@ -60,11 +68,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
  
-     for (i = 0; i < XLNX_ZYNQ_MP_NUM_CPUS; i++) {
+     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
 +        qemu_irq irq;
 +
          object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
@@ -54,5 +54,5 @@ index 9cdff13..be82a66 100644
  }
  
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
index c5bf07ef..53453ca9 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
@@ -1,7 +1,10 @@
-From 67513395caa586a2f6bc79e3791e26a129e6ec1c Mon Sep 17 00:00:00 2001
+From 7c37c0a33c598fe0dcb015aa4d48712e33e21a8b Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:45 -0800
+Date: Mon, 23 Mar 2015 04:05:14 -0700
 Subject: [PATCH 06/15] net: cadence_gem: Clean up variable names
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
 
 In preparation for migrating the state struct and type cast macro to a public
 header. The acronym "GEM" on it's own is not specific enough to be used in a
@@ -9,9 +12,11 @@ more global namespace so preface with "cadence". Fix the capitalisation of
 "gem" in the state type while touching the typename. Also preface the
 GEM_MAXREG macro as this will need to migrate to public header.
 
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/net/cadence_gem.c | 70 ++++++++++++++++++++++++++--------------------------
+ hw/net/cadence_gem.c |   70 +++++++++++++++++++++++++-------------------------
  1 file changed, 35 insertions(+), 35 deletions(-)
 
 diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
@@ -260,5 +265,5 @@ index 55b6293..5994306 100644
  };
  
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
index be4b30cf..e468563b 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
@@ -1,16 +1,17 @@
-From 3acfa69c02afc5c8f84c4e5b528a18959ddd8c1b Mon Sep 17 00:00:00 2001
+From 9f9cd8a67975d0973bf5d0dd0bdf6e0bff168774 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:46 -0800
+Date: Mon, 23 Mar 2015 04:05:15 -0700
 Subject: [PATCH 07/15] net: cadence_gem: Split state struct and type into
  header
 
 To allow using the device with modern SoC programming conventions. The
 state struct needs to be visible to embed the device in SoC containers.
 
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/net/cadence_gem.c         | 43 +-------------------------------------
- include/hw/net/cadence_gem.h | 49 ++++++++++++++++++++++++++++++++++++++++++++
+ hw/net/cadence_gem.c         |   43 +-----------------------------------
+ include/hw/net/cadence_gem.h |   49 ++++++++++++++++++++++++++++++++++++++++++
  2 files changed, 50 insertions(+), 42 deletions(-)
  create mode 100644 include/hw/net/cadence_gem.h
 
@@ -84,7 +85,7 @@ index 5994306..dafe914 100644
  
 diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
 new file mode 100644
-index 0000000..e6413ff
+index 0000000..12de820
 --- /dev/null
 +++ b/include/hw/net/cadence_gem.h
 @@ -0,0 +1,49 @@
@@ -101,8 +102,8 @@ index 0000000..e6413ff
 +typedef struct CadenceGEMState {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
-+    /*< public >*/
 +
++    /*< public >*/
 +    MemoryRegion iomem;
 +    NICState *nic;
 +    NICConf conf;
@@ -138,5 +139,5 @@ index 0000000..e6413ff
 +#define CADENCE_GEM_H_
 +#endif
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynq-mp-Add-GEM-support.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch
index 0cb42127..9441f609 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynq-mp-Add-GEM-support.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch
@@ -1,56 +1,56 @@
-From eed690e857579901b4571a250af0259e5051692f Mon Sep 17 00:00:00 2001
+From 5f3d79a3b5ede9d2da63dded227f7cdf44e7d476 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:48 -0800
-Subject: [PATCH 08/15] arm: xilinx-zynq-mp: Add GEM support
+Date: Wed, 18 Feb 2015 18:56:37 -0800
+Subject: [PATCH 08/15] arm: xilinx-zynqmp: Add GEM support
 
-There are 4x Cadence GEMs in Zynq MP. Add them.
+There are 4x Cadence GEMs in ZynqMP. Add them.
 
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/arm/xlnx-zynq-mp.c         | 32 ++++++++++++++++++++++++++++++++
- include/hw/arm/xlnx-zynq-mp.h |  3 +++
+ hw/arm/xlnx-zynqmp.c         |   32 ++++++++++++++++++++++++++++++++
+ include/hw/arm/xlnx-zynqmp.h |    3 +++
  2 files changed, 35 insertions(+)
 
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
-index be82a66..2ef57d9 100644
---- a/hw/arm/xlnx-zynq-mp.c
-+++ b/hw/arm/xlnx-zynq-mp.c
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index 29954f5..d8c648d 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
 @@ -25,6 +25,14 @@
  #define GIC_DIST_ADDR       0xf9010000
  #define GIC_CPU_ADDR        0xf9020000
  
-+static const uint64_t gem_addr[XLNX_ZYNQ_MP_NUM_GEMS] = {
++static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
 +    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
 +};
 +
-+static const int gem_intr[XLNX_ZYNQ_MP_NUM_GEMS] = {
++static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
 +    57, 59, 61, 63,
 +};
 +
  static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
  {
      return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
-@@ -43,6 +51,11 @@ static void xlnx_zynq_mp_init(Object *obj)
+@@ -44,6 +52,11 @@ static void xlnx_zynqmp_init(Object *obj)
  
      object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
      qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
 +
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_GEMS; i++) {
++    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 +        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
 +        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
 +    }
  }
  
  #define ERR_PROP_CHECK_RETURN(err, errp) do { \
-@@ -56,6 +69,7 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
+@@ -57,6 +70,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
  {
-     XlnxZynqMPState *s = XLNX_ZYNQ_MP(dev);
+     XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
      uint8_t i;
 +    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
      Error *err = NULL;
  
      qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
-@@ -81,6 +95,24 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
+@@ -82,6 +96,24 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
                                 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
          qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
      }
@@ -59,7 +59,7 @@ index be82a66..2ef57d9 100644
 +        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
 +    }
 +
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_GEMS; i++) {
++    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
 +        NICInfo *nd = &nd_table[i];
 +
 +        if (nd->used) {
@@ -74,34 +74,34 @@ index be82a66..2ef57d9 100644
 +    }
  }
  
- static void xlnx_zynq_mp_class_init(ObjectClass *oc, void *data)
-diff --git a/include/hw/arm/xlnx-zynq-mp.h b/include/hw/arm/xlnx-zynq-mp.h
-index 22b2af0..470503c 100644
---- a/include/hw/arm/xlnx-zynq-mp.h
-+++ b/include/hw/arm/xlnx-zynq-mp.h
+ static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index d29c7de..12a1be1 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
 @@ -3,12 +3,14 @@
  #include "qemu-common.h"
  #include "hw/arm/arm.h"
  #include "hw/intc/arm_gic.h"
 +#include "hw/net/cadence_gem.h"
  
- #define TYPE_XLNX_ZYNQ_MP "xlnx,zynq-mp"
- #define XLNX_ZYNQ_MP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
-                                        TYPE_XLNX_ZYNQ_MP)
+ #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
+ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
+                                        TYPE_XLNX_ZYNQMP)
  
- #define XLNX_ZYNQ_MP_NUM_CPUS 4
-+#define XLNX_ZYNQ_MP_NUM_GEMS 4
+ #define XLNX_ZYNQMP_NUM_CPUS 4
++#define XLNX_ZYNQMP_NUM_GEMS 4
  
  typedef struct XlnxZynqMPState {
      /*< private >*/
 @@ -17,6 +19,7 @@ typedef struct XlnxZynqMPState {
  
-     ARMCPU cpu[XLNX_ZYNQ_MP_NUM_CPUS];
+     ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
      GICState gic;
-+    CadenceGEMState gem[XLNX_ZYNQ_MP_NUM_GEMS];
++    CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  }  XlnxZynqMPState;
  
- #define XLNX_ZYNQ_MP_H_
+ #define XLNX_ZYNQMP_H_
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch
index b864f470..d94b23ad 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch
@@ -1,6 +1,6 @@
-From 246128b68939e7cede11cf60cffbbc194e7643ed Mon Sep 17 00:00:00 2001
+From 7f5e56c8f0a8393b9cb930883059d873802338c6 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:49 -0800
+Date: Mon, 23 Mar 2015 04:05:16 -0700
 Subject: [PATCH 09/15] char: cadence_uart: Clean up variable names
 
 In preparation for migrating the state struct and type cast macro to a public
@@ -10,13 +10,14 @@ more global namespace so preface with "cadence". Fix the capitalisation of
 used by the state struct itself with CADENCE_UART so they don't conflict
 in namespace either.
 
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/char/cadence_uart.c | 100 ++++++++++++++++++++++++++-----------------------
- 1 file changed, 53 insertions(+), 47 deletions(-)
+ hw/char/cadence_uart.c |  102 +++++++++++++++++++++++++-----------------------
+ 1 file changed, 54 insertions(+), 48 deletions(-)
 
 diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
-index 7044b35..23f548d 100644
+index d145378..4a4d3eb 100644
 --- a/hw/char/cadence_uart.c
 +++ b/hw/char/cadence_uart.c
 @@ -85,8 +85,8 @@
@@ -271,14 +272,23 @@ index 7044b35..23f548d 100644
      s->r[R_IMR] = 0;
 @@ -478,7 +482,7 @@ static void cadence_uart_reset(DeviceState *dev)
  
- static int cadence_uart_init(SysBusDevice *dev)
+ static void cadence_uart_realize(DeviceState *dev, Error **errp)
  {
 -    UartState *s = CADENCE_UART(dev);
 +    CadenceUARTState *s = CADENCE_UART(dev);
  
-     memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
-     sysbus_init_mmio(dev, &s->iomem);
-@@ -501,7 +505,7 @@ static int cadence_uart_init(SysBusDevice *dev)
+     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+                                           fifo_trigger_update, s);
+@@ -495,7 +499,7 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
+ static void cadence_uart_init(Object *obj)
+ {
+     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+-    UartState *s = CADENCE_UART(obj);
++    CadenceUARTState *s = CADENCE_UART(obj);
+ 
+     memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
+     sysbus_init_mmio(sbd, &s->iomem);
+@@ -506,7 +510,7 @@ static void cadence_uart_init(Object *obj)
  
  static int cadence_uart_post_load(void *opaque, int version_id)
  {
@@ -287,7 +297,7 @@ index 7044b35..23f548d 100644
  
      uart_parameters_setup(s);
      uart_update_status(s);
-@@ -514,13 +518,15 @@ static const VMStateDescription vmstate_cadence_uart = {
+@@ -519,13 +523,15 @@ static const VMStateDescription vmstate_cadence_uart = {
      .minimum_version_id = 2,
      .post_load = cadence_uart_post_load,
      .fields = (VMStateField[]) {
@@ -310,15 +320,15 @@ index 7044b35..23f548d 100644
          VMSTATE_END_OF_LIST()
      }
  };
-@@ -538,7 +544,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data)
+@@ -544,7 +550,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data)
  static const TypeInfo cadence_uart_info = {
      .name          = TYPE_CADENCE_UART,
      .parent        = TYPE_SYS_BUS_DEVICE,
 -    .instance_size = sizeof(UartState),
 +    .instance_size = sizeof(CadenceUARTState),
+     .instance_init = cadence_uart_init,
      .class_init    = cadence_uart_class_init,
  };
- 
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch
index 6fe3f98a..e56aed88 100644
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch
@@ -1,21 +1,22 @@
-From 33e66004378aa203562e5b051282c1a7ffb8ee3b Mon Sep 17 00:00:00 2001
+From f50fc4d6e1ee32e47f0f9cd6b8b98aa754ced588 Mon Sep 17 00:00:00 2001
 From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:50 -0800
+Date: Mon, 23 Mar 2015 04:05:16 -0700
 Subject: [PATCH 10/15] char: cadence_uart: Split state struct and type into
  header
 
 To allow using the device with modern SoC programming conventions. The
 state struct needs to be visible to embed the device in SoC containers.
 
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
 Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
 ---
- hw/char/cadence_uart.c         | 29 +----------------------------
- include/hw/char/cadence_uart.h | 35 +++++++++++++++++++++++++++++++++++
+ hw/char/cadence_uart.c         |   29 +----------------------------
+ include/hw/char/cadence_uart.h |   35 +++++++++++++++++++++++++++++++++++
  2 files changed, 36 insertions(+), 28 deletions(-)
  create mode 100644 include/hw/char/cadence_uart.h
 
 diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
-index 23f548d..4509e01 100644
+index 4a4d3eb..9d379e5 100644
 --- a/hw/char/cadence_uart.c
 +++ b/hw/char/cadence_uart.c
 @@ -16,9 +16,7 @@
@@ -70,7 +71,7 @@ index 23f548d..4509e01 100644
  {
 diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
 new file mode 100644
-index 0000000..0404785
+index 0000000..3456d4c
 --- /dev/null
 +++ b/include/hw/char/cadence_uart.h
 @@ -0,0 +1,35 @@
@@ -92,8 +93,8 @@ index 0000000..0404785
 +typedef struct {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
-+    /*< public >*/
 +
++    /*< public >*/
 +    MemoryRegion iomem;
 +    uint32_t r[CADENCE_UART_R_MAX];
 +    uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
@@ -110,5 +111,5 @@ index 0000000..0404785
 +#define CADENCE_UART_H_
 +#endif
 -- 
-2.1.1
+1.7.10.4
 
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynq-mp-Add-UART-support.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynq-mp-Add-UART-support.patch
deleted file mode 100644
index 166aa129..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynq-mp-Add-UART-support.patch
+++ /dev/null
@@ -1,90 +0,0 @@
-From ef634b1cf1766a5798868d1299a9a4ae2e87bcc9 Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:51 -0800
-Subject: [PATCH 11/15] arm: xilinx-zynq-mp: Add UART support
-
-There are 2x Cadence UARTSs in Zynq MP. Add them.
-
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/arm/xlnx-zynq-mp.c         | 21 +++++++++++++++++++++
- include/hw/arm/xlnx-zynq-mp.h |  3 +++
- 2 files changed, 24 insertions(+)
-
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
-index 2ef57d9..9d7e834 100644
---- a/hw/arm/xlnx-zynq-mp.c
-+++ b/hw/arm/xlnx-zynq-mp.c
-@@ -33,6 +33,14 @@ static const int gem_intr[XLNX_ZYNQ_MP_NUM_GEMS] = {
-     57, 59, 61, 63,
- };
- 
-+static const uint64_t uart_addr[XLNX_ZYNQ_MP_NUM_UARTS] = {
-+    0xFF000000, 0xFF010000,
-+};
-+
-+static const int uart_intr[XLNX_ZYNQ_MP_NUM_UARTS] = {
-+    21, 22,
-+};
-+
- static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
- {
-     return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
-@@ -56,6 +64,11 @@ static void xlnx_zynq_mp_init(Object *obj)
-         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
-         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
-     }
-+
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_UARTS; i++) {
-+        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
-+        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
-+    }
- }
- 
- #define ERR_PROP_CHECK_RETURN(err, errp) do { \
-@@ -113,6 +126,14 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
-         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
-                            gic_spi[gem_intr[i]]);
-     }
-+
-+    for (i = 0; i < XLNX_ZYNQ_MP_NUM_UARTS; i++) {
-+        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
-+        ERR_PROP_CHECK_RETURN(err, errp);
-+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
-+                           gic_spi[uart_intr[i]]);
-+    }
- }
- 
- static void xlnx_zynq_mp_class_init(ObjectClass *oc, void *data)
-diff --git a/include/hw/arm/xlnx-zynq-mp.h b/include/hw/arm/xlnx-zynq-mp.h
-index 470503c..c4ee658 100644
---- a/include/hw/arm/xlnx-zynq-mp.h
-+++ b/include/hw/arm/xlnx-zynq-mp.h
-@@ -4,6 +4,7 @@
- #include "hw/arm/arm.h"
- #include "hw/intc/arm_gic.h"
- #include "hw/net/cadence_gem.h"
-+#include "hw/char/cadence_uart.h"
- 
- #define TYPE_XLNX_ZYNQ_MP "xlnx,zynq-mp"
- #define XLNX_ZYNQ_MP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
-@@ -11,6 +12,7 @@
- 
- #define XLNX_ZYNQ_MP_NUM_CPUS 4
- #define XLNX_ZYNQ_MP_NUM_GEMS 4
-+#define XLNX_ZYNQ_MP_NUM_UARTS 2
- 
- typedef struct XlnxZynqMPState {
-     /*< private >*/
-@@ -20,6 +22,7 @@ typedef struct XlnxZynqMPState {
-     ARMCPU cpu[XLNX_ZYNQ_MP_NUM_CPUS];
-     GICState gic;
-     CadenceGEMState gem[XLNX_ZYNQ_MP_NUM_GEMS];
-+    CadenceUARTState uart[XLNX_ZYNQ_MP_NUM_UARTS];
- }  XlnxZynqMPState;
- 
- #define XLNX_ZYNQ_MP_H_
--- 
-2.1.1
-
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch
new file mode 100644
index 00000000..ccf86cf7
--- /dev/null
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch
@@ -0,0 +1,91 @@
+From d35149eea398ca20d0c1ec382e9fce5e2c229ce0 Mon Sep 17 00:00:00 2001
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Wed, 18 Feb 2015 18:56:37 -0800
+Subject: [PATCH 11/15] arm: xilinx-zynqmp: Add UART support
+
+There are 2x Cadence UARTs in Zynq MP. Add them.
+
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+ hw/arm/xlnx-zynqmp.c         |   21 +++++++++++++++++++++
+ include/hw/arm/xlnx-zynqmp.h |    3 +++
+ 2 files changed, 24 insertions(+)
+
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index d8c648d..e015025 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
+@@ -33,6 +33,14 @@ static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
+     57, 59, 61, 63,
+ };
+ 
++static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
++    0xFF000000, 0xFF010000,
++};
++
++static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
++    21, 22,
++};
++
+ static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
+ {
+     return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
+@@ -57,6 +65,11 @@ static void xlnx_zynqmp_init(Object *obj)
+         object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
+         qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
+     }
++
++    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
++        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
++        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
++    }
+ }
+ 
+ #define ERR_PROP_CHECK_RETURN(err, errp) do { \
+@@ -114,6 +127,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
+                            gic_spi[gem_intr[i]]);
+     }
++
++    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
++        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
++        ERR_PROP_CHECK_RETURN(err, errp);
++        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
++        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
++                           gic_spi[uart_intr[i]]);
++    }
+ }
+ 
+ static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index 12a1be1..62d8d3f 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
+@@ -4,6 +4,7 @@
+ #include "hw/arm/arm.h"
+ #include "hw/intc/arm_gic.h"
+ #include "hw/net/cadence_gem.h"
++#include "hw/char/cadence_uart.h"
+ 
+ #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
+ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
+@@ -11,6 +12,7 @@
+ 
+ #define XLNX_ZYNQMP_NUM_CPUS 4
+ #define XLNX_ZYNQMP_NUM_GEMS 4
++#define XLNX_ZYNQMP_NUM_UARTS 2
+ 
+ typedef struct XlnxZynqMPState {
+     /*< private >*/
+@@ -20,6 +22,7 @@ typedef struct XlnxZynqMPState {
+     ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
+     GICState gic;
+     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
++    CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ }  XlnxZynqMPState;
+ 
+ #define XLNX_ZYNQMP_H_
+-- 
+1.7.10.4
+
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xilinx-zynq-mp-generic-machine.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xilinx-zynq-mp-generic-machine.patch
deleted file mode 100644
index 4dbcc495..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xilinx-zynq-mp-generic-machine.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 48860a59e9fe23da638dde9c47a3665466ceefae Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:52 -0800
-Subject: [PATCH 12/15] arm: Add xilinx-zynq-mp-generic machine
-
-Add a generic machine for the Xilinx Zynq MP SoC. This is a minimal
-machine that exposes the capabilities of the raw SoC as a usable
-machine.
-
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/arm/Makefile.objs          |  2 +-
- hw/arm/xlnx-zynq-mp-generic.c | 52 +++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 53 insertions(+), 1 deletion(-)
- create mode 100644 hw/arm/xlnx-zynq-mp-generic.c
-
-diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
-index 9bf072b..776fbe3 100644
---- a/hw/arm/Makefile.objs
-+++ b/hw/arm/Makefile.objs
-@@ -8,4 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
- obj-$(CONFIG_DIGIC) += digic.o
- obj-y += omap1.o omap2.o strongarm.o
- obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
--obj-$(CONFIG_XLNX_ZYNQ_MP) += xlnx-zynq-mp.o
-+obj-$(CONFIG_XLNX_ZYNQ_MP) += xlnx-zynq-mp.o xlnx-zynq-mp-generic.o
-diff --git a/hw/arm/xlnx-zynq-mp-generic.c b/hw/arm/xlnx-zynq-mp-generic.c
-new file mode 100644
-index 0000000..ff69b07
---- /dev/null
-+++ b/hw/arm/xlnx-zynq-mp-generic.c
-@@ -0,0 +1,52 @@
-+#/*
-+ * Xilinx Zynq MPSoC emulation
-+ *
-+ * Copyright (C) 2015 Xilinx Inc
-+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-+ * for more details.
-+ */
-+
-+#include "hw/arm/xlnx-zynq-mp.h"
-+#include "hw/boards.h"
-+#include "qemu/error-report.h"
-+
-+typedef struct XlnxZynqMPGeneric {
-+    XlnxZynqMPState soc;
-+} XlnxZynqMPGeneric;
-+
-+static void xlnx_zynq_mp_generic_init(MachineState *machine)
-+{
-+    XlnxZynqMPGeneric *s = g_new0(XlnxZynqMPGeneric, 1);
-+    Error *err = NULL;
-+
-+    object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQ_MP);
-+    object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), NULL);
-+
-+    object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
-+    if (err) {
-+        error_report("%s", error_get_pretty(err));
-+        exit(1);
-+    }
-+}
-+
-+static QEMUMachine xlnx_zynq_mp_generic_machine = {
-+    .name = "xlnx-zynq-mp-generic",
-+    .desc = "Xilinx Zynq MP SoC generic machine",
-+    .init = xlnx_zynq_mp_generic_init,
-+};
-+
-+static void xlnx_zynq_mp_generic_machine_init(void)
-+{
-+    qemu_register_machine(&xlnx_zynq_mp_generic_machine);
-+}
-+
-+machine_init(xlnx_zynq_mp_generic_machine_init);
--- 
-2.1.1
-
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch
new file mode 100644
index 00000000..4c7d05aa
--- /dev/null
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch
@@ -0,0 +1,87 @@
+From 0b9dbaa31007d9d7ef8bafcdcb756ffdcc591e03 Mon Sep 17 00:00:00 2001
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Mon, 23 Mar 2015 04:05:17 -0700
+Subject: [PATCH 12/15] arm: Add xlnx-ep108 machine
+
+Add a machine model for the Xilinx ZynqMP SoC EP108 board.
+
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+---
+ hw/arm/Makefile.objs |    2 +-
+ hw/arm/xlnx-ep108.c  |   53 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 54 insertions(+), 1 deletion(-)
+ create mode 100644 hw/arm/xlnx-ep108.c
+
+diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
+index d7cd5f4..a75a182 100644
+--- a/hw/arm/Makefile.objs
++++ b/hw/arm/Makefile.objs
+@@ -10,4 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
+ obj-y += omap1.o omap2.o strongarm.o
+ obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
+ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
+-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o
++obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
+diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
+new file mode 100644
+index 0000000..81704bb
+--- /dev/null
++++ b/hw/arm/xlnx-ep108.c
+@@ -0,0 +1,53 @@
++/*
++ * Xilinx ZynqMP EP108 board
++ *
++ * Copyright (C) 2015 Xilinx Inc
++ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include "hw/arm/xlnx-zynqmp.h"
++#include "hw/boards.h"
++#include "qemu/error-report.h"
++
++typedef struct XlnxEP108 {
++    XlnxZynqMPState soc;
++} XlnxEP108;
++
++static void xlnx_ep108_init(MachineState *machine)
++{
++    XlnxEP108 *s = g_new0(XlnxEP108, 1);
++    Error *err = NULL;
++
++    object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
++    object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
++                              &error_abort);
++
++    object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
++    if (err) {
++        error_report("%s", error_get_pretty(err));
++        exit(1);
++    }
++}
++
++static QEMUMachine xlnx_ep108_machine = {
++    .name = "xlnx-ep108",
++    .desc = "Xilinx ZynqMP EP108 board",
++    .init = xlnx_ep108_init,
++};
++
++static void xlnx_ep108_machine_init(void)
++{
++    qemu_register_machine(&xlnx_ep108_machine);
++}
++
++machine_init(xlnx_ep108_machine_init);
+-- 
+1.7.10.4
+
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch
new file mode 100644
index 00000000..2030048e
--- /dev/null
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch
@@ -0,0 +1,60 @@
+From 7c16af47e2ec33043ca0ef924232c9eef9dc60c4 Mon Sep 17 00:00:00 2001
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Mon, 23 Mar 2015 04:05:18 -0700
+Subject: [PATCH 13/15] arm: xilinx-ep108: Add external RAM
+
+Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
+
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+---
+ hw/arm/xlnx-ep108.c |   21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
+index 81704bb..6e89456 100644
+--- a/hw/arm/xlnx-ep108.c
++++ b/hw/arm/xlnx-ep108.c
+@@ -18,11 +18,16 @@
+ #include "hw/arm/xlnx-zynqmp.h"
+ #include "hw/boards.h"
+ #include "qemu/error-report.h"
++#include "exec/address-spaces.h"
+ 
+ typedef struct XlnxEP108 {
+     XlnxZynqMPState soc;
++    MemoryRegion ddr_ram;
+ } XlnxEP108;
+ 
++/* Max 2GB RAM */
++#define EP108_MAX_RAM_SIZE 0x80000000ull
++
+ static void xlnx_ep108_init(MachineState *machine)
+ {
+     XlnxEP108 *s = g_new0(XlnxEP108, 1);
+@@ -37,6 +42,22 @@ static void xlnx_ep108_init(MachineState *machine)
+         error_report("%s", error_get_pretty(err));
+         exit(1);
+     }
++
++    if (machine->ram_size > EP108_MAX_RAM_SIZE) {
++        error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
++                     "reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
++        machine->ram_size = EP108_MAX_RAM_SIZE;
++    }
++
++    if (machine->ram_size <= 0x08000000) {
++        error_report("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108\n",
++                     machine->ram_size);
++    }
++
++    memory_region_init_ram(&s->ddr_ram, NULL, "ddr-ram", machine->ram_size,
++                           &error_abort);
++    vmstate_register_ram_global(&s->ddr_ram);
++    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
+ }
+ 
+ static QEMUMachine xlnx_ep108_machine = {
+-- 
+1.7.10.4
+
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-zynq-mp-generic-Add-external-RAM.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-zynq-mp-generic-Add-external-RAM.patch
deleted file mode 100644
index 0af560de..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-zynq-mp-generic-Add-external-RAM.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 0b155ff9a1e19f2b4ed4324e822285d3a667f02a Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:53 -0800
-Subject: [PATCH 13/15] arm: xilinx-zynq-mp-generic: Add external RAM
-
-Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
-
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/arm/xlnx-zynq-mp-generic.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/hw/arm/xlnx-zynq-mp-generic.c b/hw/arm/xlnx-zynq-mp-generic.c
-index ff69b07..7394e82 100644
---- a/hw/arm/xlnx-zynq-mp-generic.c
-+++ b/hw/arm/xlnx-zynq-mp-generic.c
-@@ -18,9 +18,11 @@
- #include "hw/arm/xlnx-zynq-mp.h"
- #include "hw/boards.h"
- #include "qemu/error-report.h"
-+#include "exec/address-spaces.h"
- 
- typedef struct XlnxZynqMPGeneric {
-     XlnxZynqMPState soc;
-+    MemoryRegion ddr_ram;
- } XlnxZynqMPGeneric;
- 
- static void xlnx_zynq_mp_generic_init(MachineState *machine)
-@@ -36,6 +38,11 @@ static void xlnx_zynq_mp_generic_init(MachineState *machine)
-         error_report("%s", error_get_pretty(err));
-         exit(1);
-     }
-+
-+    memory_region_init_ram(&s->ddr_ram, NULL, "ddr-ram", machine->ram_size,
-+                           &error_abort);
-+    vmstate_register_ram_global(&s->ddr_ram);
-+    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
- }
- 
- static QEMUMachine xlnx_zynq_mp_generic_machine = {
--- 
-2.1.1
-
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch
new file mode 100644
index 00000000..1a9a8a8f
--- /dev/null
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch
@@ -0,0 +1,42 @@
+From 409477e2655e2169c5dd38de8cec00c863869670 Mon Sep 17 00:00:00 2001
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Mon, 23 Mar 2015 04:05:18 -0700
+Subject: [PATCH 14/15] arm: xilinx-ep108: Add bootloading
+
+Using standard ARM bootloader.
+
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+---
+ hw/arm/xlnx-ep108.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
+index 6e89456..a86f595 100644
+--- a/hw/arm/xlnx-ep108.c
++++ b/hw/arm/xlnx-ep108.c
+@@ -28,6 +28,8 @@ typedef struct XlnxEP108 {
+ /* Max 2GB RAM */
+ #define EP108_MAX_RAM_SIZE 0x80000000ull
+ 
++static struct arm_boot_info xlnx_ep108_binfo;
++
+ static void xlnx_ep108_init(MachineState *machine)
+ {
+     XlnxEP108 *s = g_new0(XlnxEP108, 1);
+@@ -58,6 +60,12 @@ static void xlnx_ep108_init(MachineState *machine)
+                            &error_abort);
+     vmstate_register_ram_global(&s->ddr_ram);
+     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
++
++    xlnx_ep108_binfo.ram_size = machine->ram_size;
++    xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
++    xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
++    xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
++    arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
+ }
+ 
+ static QEMUMachine xlnx_ep108_machine = {
+-- 
+1.7.10.4
+
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-zynq-mp-generic-Add-bootloading.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-zynq-mp-generic-Add-bootloading.patch
deleted file mode 100644
index 9c551bff..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-zynq-mp-generic-Add-bootloading.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 8ef4b6e8f95d99dcee6ae1bae92f24cd05d1ff3a Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:54 -0800
-Subject: [PATCH 14/15] arm: xilinx-zynq-mp-generic: Add bootloading
-
-Using standard ARM bootloader.
-
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/arm/xlnx-zynq-mp-generic.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/hw/arm/xlnx-zynq-mp-generic.c b/hw/arm/xlnx-zynq-mp-generic.c
-index 7394e82..a86f10d 100644
---- a/hw/arm/xlnx-zynq-mp-generic.c
-+++ b/hw/arm/xlnx-zynq-mp-generic.c
-@@ -25,6 +25,8 @@ typedef struct XlnxZynqMPGeneric {
-     MemoryRegion ddr_ram;
- } XlnxZynqMPGeneric;
- 
-+static struct arm_boot_info xlnx_zynq_mp_generic_binfo;
-+
- static void xlnx_zynq_mp_generic_init(MachineState *machine)
- {
-     XlnxZynqMPGeneric *s = g_new0(XlnxZynqMPGeneric, 1);
-@@ -43,6 +45,12 @@ static void xlnx_zynq_mp_generic_init(MachineState *machine)
-                            &error_abort);
-     vmstate_register_ram_global(&s->ddr_ram);
-     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
-+
-+    xlnx_zynq_mp_generic_binfo.ram_size = machine->ram_size;
-+    xlnx_zynq_mp_generic_binfo.kernel_filename = machine->kernel_filename;
-+    xlnx_zynq_mp_generic_binfo.kernel_cmdline = machine->kernel_cmdline;
-+    xlnx_zynq_mp_generic_binfo.initrd_filename = machine->initrd_filename;
-+    arm_load_kernel(&s->soc.cpu[0], &xlnx_zynq_mp_generic_binfo);
- }
- 
- static QEMUMachine xlnx_zynq_mp_generic_machine = {
--- 
-2.1.1
-
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynq-mp-Add-PSCI-setup.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynq-mp-Add-PSCI-setup.patch
deleted file mode 100644
index e145e4b4..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynq-mp-Add-PSCI-setup.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 97287cf7c4f7550d298c0ef11dde88ee91c209a3 Mon Sep 17 00:00:00 2001
-From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
-Date: Mon, 23 Feb 2015 15:04:55 -0800
-Subject: [PATCH 15/15] arm: xlnx-zynq-mp: Add PSCI setup
-
-Use SMC PSCI, with the standard policy of secondaries starting in
-power-off.
-
-Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
----
- hw/arm/xlnx-zynq-mp.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/hw/arm/xlnx-zynq-mp.c b/hw/arm/xlnx-zynq-mp.c
-index 9d7e834..0952221 100644
---- a/hw/arm/xlnx-zynq-mp.c
-+++ b/hw/arm/xlnx-zynq-mp.c
-@@ -96,6 +96,14 @@ static void xlnx_zynq_mp_realize(DeviceState *dev, Error **errp)
-     for (i = 0; i < XLNX_ZYNQ_MP_NUM_CPUS; i++) {
-         qemu_irq irq;
- 
-+        object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
-+                                "psci-conduit", NULL);
-+        if (i > 0) {
-+            /* Secondary CPUs start in PSCI powered-down state */
-+            object_property_set_bool(OBJECT(&s->cpu[i]), true,
-+                                     "start-powered-off", NULL);
-+        }
-+
-         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
-         ERR_PROP_CHECK_RETURN(err, errp);
- 
--- 
-2.1.1
-
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch
new file mode 100644
index 00000000..20b9b827
--- /dev/null
+++ b/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch
@@ -0,0 +1,36 @@
+From 5c6a101203322028e91586736b4f6e3c5ecc7d09 Mon Sep 17 00:00:00 2001
+From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+Date: Mon, 23 Mar 2015 04:05:19 -0700
+Subject: [PATCH 15/15] arm: xlnx-zynqmp: Add PSCI setup
+
+Use SMC PSCI, with the standard policy of secondaries starting in
+power-off.
+
+Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
+Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
+---
+ hw/arm/xlnx-zynqmp.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index e015025..0265fba 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
+@@ -97,6 +97,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+     for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+         qemu_irq irq;
+ 
++        object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
++                                "psci-conduit", &error_abort);
++        if (i > 0) {
++            /* Secondary CPUs start in PSCI powered-down state */
++            object_property_set_bool(OBJECT(&s->cpu[i]), true,
++                                     "start-powered-off", &error_abort);
++        }
++
+         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+         ERR_PROP_CHECK_RETURN(err, errp);
+ 
+-- 
+1.7.10.4
+
diff --git a/recipes-devtools/qemu/qemu_zynqmp.bb b/recipes-devtools/qemu/qemu_zynqmp.bb
index 040147ec..679fc755 100644
--- a/recipes-devtools/qemu/qemu_zynqmp.bb
+++ b/recipes-devtools/qemu/qemu_zynqmp.bb
@@ -1,5 +1,8 @@
 require recipes-devtools/qemu/qemu.inc
 
+# glx no longer valid config option
+PACKAGECONFIG[glx] = ""
+
 DEFAULT_PREFERENCE = "-1"
 
 LIC_FILES_CHKSUM = " \
@@ -7,7 +10,7 @@ LIC_FILES_CHKSUM = " \
                 file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \
                 "
 
-SRCREV = "cd2d5541271f1934345d8ca42f5fafff1744eee7"
+SRCREV = "f2a581010cb8e3a2564a45a2863a33a732cc2fc7"
 
 PV = "2.2.0+master+zynqmp+git${SRCPV}"
 
@@ -22,18 +25,18 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/qemu-zynqmp-mainline:"
 SRC_URI_append += " \
                 file://0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch \
                 file://0002-target-arm-cpu64-Add-support-for-cortex-a53.patch \
-                file://0003-arm-Introduce-Xilinx-Zynq-MPSoC.patch \
-                file://0004-arm-xlnx-zynq-mp-Add-GIC.patch \
-                file://0005-arm-xlnx-zynq-mp-Connect-CPU-Timers-to-GIC.patch \
+                file://0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch \
+                file://0004-arm-xlnx-zynqmp-Add-GIC.patch \
+                file://0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch \
                 file://0006-net-cadence_gem-Clean-up-variable-names.patch \
                 file://0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch \
-                file://0008-arm-xilinx-zynq-mp-Add-GEM-support.patch \
+                file://0008-arm-xilinx-zynqmp-Add-GEM-support.patch \
                 file://0009-char-cadence_uart-Clean-up-variable-names.patch \
                 file://0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch \
-                file://0011-arm-xilinx-zynq-mp-Add-UART-support.patch \
-                file://0012-arm-Add-xilinx-zynq-mp-generic-machine.patch \
-                file://0013-arm-xilinx-zynq-mp-generic-Add-external-RAM.patch \
-                file://0014-arm-xilinx-zynq-mp-generic-Add-bootloading.patch \
-                file://0015-arm-xlnx-zynq-mp-Add-PSCI-setup.patch \
+                file://0011-arm-xilinx-zynqmp-Add-UART-support.patch \
+                file://0012-arm-Add-xlnx-ep108-machine.patch \
+                file://0013-arm-xilinx-ep108-Add-external-RAM.patch \
+                file://0014-arm-xilinx-ep108-Add-bootloading.patch \
+                file://0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch \
                 "