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authorNathan Rossi <nathan@nathanrossi.com>2015-07-23 21:24:37 +1000
committerNathan Rossi <nathan@nathanrossi.com>2015-07-23 23:59:13 +1000
commit2e14dd1dd6e6544c87aea39cc37f88bedaace738 (patch)
treedcc2ecfa60924aaf910ad917db2e12d41d0c5674 /recipes-devtools
parent9ab92ee087dba5efe56a0782573cec2ffaa4d615 (diff)
downloadmeta-xilinx-2e14dd1dd6e6544c87aea39cc37f88bedaace738.tar.gz
qemu_zynqmp: Remove custom QEMU recipe for ZynqMP
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Diffstat (limited to 'recipes-devtools')
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch115
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch56
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch145
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch84
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch58
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch269
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch143
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch107
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch334
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch115
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch91
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch87
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch60
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch42
-rw-r--r--recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch36
-rw-r--r--recipes-devtools/qemu/qemu_zynqmp.bb42
16 files changed, 0 insertions, 1784 deletions
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch
deleted file mode 100644
index f759f27b..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch
+++ /dev/null
@@ -1,115 +0,0 @@
1From 56489633015d2ac71d680bdd27accbd6f87b4fe3 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:11 -0700
4Subject: [PATCH 01/15] target-arm: cpu64: Factor out ARM cortex init
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9In preparation for support for Cortex a53. Use "axx" to describe the
10shareable features. Some of the CP15 registers (such as ACTLR) are
11specific to implementation, but we currently just RAZ them so continue
12with that as the policy for all cortex A processors under a shared
13definition.
14
15The cache sizes and geometeries, the L1 I-cache policy and the physical
16address range differ between A53 and A57 so those particulars are left
17as A57 specific. The rest are moved to the generalisation.
18
19Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
20Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
21---
22 target-arm/cpu64.c | 34 ++++++++++++++++++++--------------
23 1 file changed, 20 insertions(+), 14 deletions(-)
24
25diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
26index 270bc2f..3eb58c6 100644
27--- a/target-arm/cpu64.c
28+++ b/target-arm/cpu64.c
29@@ -38,22 +38,22 @@ static inline void unset_feature(CPUARMState *env, int feature)
30 }
31
32 #ifndef CONFIG_USER_ONLY
33-static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
34+static uint64_t axx_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
35 {
36 /* Number of processors is in [25:24]; otherwise we RAZ */
37 return (smp_cpus - 1) << 24;
38 }
39 #endif
40
41-static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
42+static const ARMCPRegInfo cortexaxx_cp_reginfo[] = {
43 #ifndef CONFIG_USER_ONLY
44 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
45 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
46- .access = PL1_RW, .readfn = a57_l2ctlr_read,
47+ .access = PL1_RW, .readfn = axx_l2ctlr_read,
48 .writefn = arm_cp_write_ignore },
49 { .name = "L2CTLR",
50 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
51- .access = PL1_RW, .readfn = a57_l2ctlr_read,
52+ .access = PL1_RW, .readfn = axx_l2ctlr_read,
53 .writefn = arm_cp_write_ignore },
54 #endif
55 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
56@@ -92,11 +92,8 @@ static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
57 REGINFO_SENTINEL
58 };
59
60-static void aarch64_a57_initfn(Object *obj)
61+static void aarch64_axx_initfn(ARMCPU *cpu)
62 {
63- ARMCPU *cpu = ARM_CPU(obj);
64-
65- cpu->dtb_compatible = "arm,cortex-a57";
66 set_feature(&cpu->env, ARM_FEATURE_V8);
67 set_feature(&cpu->env, ARM_FEATURE_VFP4);
68 set_feature(&cpu->env, ARM_FEATURE_NEON);
69@@ -108,13 +105,10 @@ static void aarch64_a57_initfn(Object *obj)
70 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
71 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
72 set_feature(&cpu->env, ARM_FEATURE_CRC);
73- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
74- cpu->midr = 0x411fd070;
75 cpu->reset_fpsid = 0x41034070;
76 cpu->mvfr0 = 0x10110222;
77 cpu->mvfr1 = 0x12111111;
78 cpu->mvfr2 = 0x00000043;
79- cpu->ctr = 0x8444c004;
80 cpu->reset_sctlr = 0x00c50838;
81 cpu->id_pfr0 = 0x00000131;
82 cpu->id_pfr1 = 0x00011011;
83@@ -133,14 +127,26 @@ static void aarch64_a57_initfn(Object *obj)
84 cpu->id_aa64pfr0 = 0x00002222;
85 cpu->id_aa64dfr0 = 0x10305106;
86 cpu->id_aa64isar0 = 0x00011120;
87- cpu->id_aa64mmfr0 = 0x00001124;
88 cpu->dbgdidr = 0x3516d000;
89 cpu->clidr = 0x0a200023;
90+ cpu->dcz_blocksize = 4; /* 64 bytes */
91+ define_arm_cp_regs(cpu, cortexaxx_cp_reginfo);
92+}
93+
94+static void aarch64_a57_initfn(Object *obj)
95+{
96+ ARMCPU *cpu = ARM_CPU(obj);
97+
98+ aarch64_axx_initfn(cpu);
99+
100+ cpu->dtb_compatible = "arm,cortex-a57";
101+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
102+ cpu->midr = 0x411fd070;
103+ cpu->ctr = 0x8444c004; /* L1Ip = PIPT */
104+ cpu->id_aa64mmfr0 = 0x00001124; /* 44 bit physical addr */
105 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
106 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
107 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
108- cpu->dcz_blocksize = 4; /* 64 bytes */
109- define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
110 }
111
112 #ifdef CONFIG_USER_ONLY
113--
1141.7.10.4
115
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
deleted file mode 100644
index 290f2870..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0002-target-arm-cpu64-Add-support-for-cortex-a53.patch
+++ /dev/null
@@ -1,56 +0,0 @@
1From a69dfd5611a5671ff6163d3368d3628152251b04 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:11 -0700
4Subject: [PATCH 02/15] target-arm: cpu64: Add support for cortex-a53
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9Similar to a53, but with different L1 I cache policy, phys addr size and
10different cache geometries. The cache sizes is implementation
11configurable, but use these values (from Xilinx MPSoC) as a default
12until cache size configurability is added.
13
14Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
16---
17 target-arm/cpu64.c | 16 ++++++++++++++++
18 1 file changed, 16 insertions(+)
19
20diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
21index 3eb58c6..728d9a7 100644
22--- a/target-arm/cpu64.c
23+++ b/target-arm/cpu64.c
24@@ -149,6 +149,21 @@ static void aarch64_a57_initfn(Object *obj)
25 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
26 }
27
28+static void aarch64_a53_initfn(Object *obj)
29+{
30+ ARMCPU *cpu = ARM_CPU(obj);
31+
32+ aarch64_axx_initfn(cpu);
33+
34+ cpu->dtb_compatible = "arm,cortex-a53";
35+ cpu->midr = 0x410fd034;
36+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
37+ cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
38+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
39+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
40+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
41+}
42+
43 #ifdef CONFIG_USER_ONLY
44 static void aarch64_any_initfn(Object *obj)
45 {
46@@ -176,6 +191,7 @@ typedef struct ARMCPUInfo {
47
48 static const ARMCPUInfo aarch64_cpus[] = {
49 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
50+ { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
51 #ifdef CONFIG_USER_ONLY
52 { .name = "any", .initfn = aarch64_any_initfn },
53 #endif
54--
551.7.10.4
56
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch
deleted file mode 100644
index eb5740e0..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch
+++ /dev/null
@@ -1,145 +0,0 @@
1From 7f403cd27dbef216c77faa32d015965dfa5fe34e Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:13 -0700
4Subject: [PATCH 03/15] arm: Introduce Xilinx ZynqMP SoC
5
6With quad Cortex-A53 CPUs.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10---
11 default-configs/aarch64-softmmu.mak | 2 +-
12 hw/arm/Makefile.objs | 1 +
13 hw/arm/xlnx-zynqmp.c | 72 +++++++++++++++++++++++++++++++++++
14 include/hw/arm/xlnx-zynqmp.h | 21 ++++++++++
15 4 files changed, 95 insertions(+), 1 deletion(-)
16 create mode 100644 hw/arm/xlnx-zynqmp.c
17 create mode 100644 include/hw/arm/xlnx-zynqmp.h
18
19diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak
20index 6d3b5c7..96dd994 100644
21--- a/default-configs/aarch64-softmmu.mak
22+++ b/default-configs/aarch64-softmmu.mak
23@@ -3,4 +3,4 @@
24 # We support all the 32 bit boards so need all their config
25 include arm-softmmu.mak
26
27-# Currently no 64-bit specific config requirements
28+CONFIG_XLNX_ZYNQMP=y
29diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
30index 2577f68..d7cd5f4 100644
31--- a/hw/arm/Makefile.objs
32+++ b/hw/arm/Makefile.objs
33@@ -10,3 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
34 obj-y += omap1.o omap2.o strongarm.o
35 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
36 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
37+obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o
38diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
39new file mode 100644
40index 0000000..41c207a
41--- /dev/null
42+++ b/hw/arm/xlnx-zynqmp.c
43@@ -0,0 +1,72 @@
44+/*
45+ * Xilinx Zynq MPSoC emulation
46+ *
47+ * Copyright (C) 2015 Xilinx Inc
48+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
49+ *
50+ * This program is free software; you can redistribute it and/or modify it
51+ * under the terms of the GNU General Public License as published by the
52+ * Free Software Foundation; either version 2 of the License, or
53+ * (at your option) any later version.
54+ *
55+ * This program is distributed in the hope that it will be useful, but WITHOUT
56+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
57+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
58+ * for more details.
59+ */
60+
61+#include "hw/arm/xlnx-zynqmp.h"
62+
63+static void xlnx_zynqmp_init(Object *obj)
64+{
65+ XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
66+ int i;
67+
68+ for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
69+ object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
70+ "cortex-a53-" TYPE_ARM_CPU);
71+ object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
72+ &error_abort);
73+ }
74+}
75+
76+#define ERR_PROP_CHECK_RETURN(err, errp) do { \
77+ if (err) { \
78+ error_propagate((errp), (err)); \
79+ return; \
80+ } \
81+} while (0)
82+
83+static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
84+{
85+ XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
86+ uint8_t i;
87+ Error *err = NULL;
88+
89+ for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
90+ object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
91+ ERR_PROP_CHECK_RETURN(err, errp);
92+ }
93+}
94+
95+static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
96+{
97+ DeviceClass *dc = DEVICE_CLASS(oc);
98+
99+ dc->realize = xlnx_zynqmp_realize;
100+}
101+
102+static const TypeInfo xlnx_zynqmp_type_info = {
103+ .name = TYPE_XLNX_ZYNQMP,
104+ .parent = TYPE_DEVICE,
105+ .instance_size = sizeof(XlnxZynqMPState),
106+ .instance_init = xlnx_zynqmp_init,
107+ .class_init = xlnx_zynqmp_class_init,
108+};
109+
110+static void xlnx_zynqmp_register_types(void)
111+{
112+ type_register_static(&xlnx_zynqmp_type_info);
113+}
114+
115+type_init(xlnx_zynqmp_register_types)
116diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
117new file mode 100644
118index 0000000..d6b3b92
119--- /dev/null
120+++ b/include/hw/arm/xlnx-zynqmp.h
121@@ -0,0 +1,21 @@
122+#ifndef XLNX_ZYNQMP_H_
123+
124+#include "qemu-common.h"
125+#include "hw/arm/arm.h"
126+
127+#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
128+#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
129+ TYPE_XLNX_ZYNQMP)
130+
131+#define XLNX_ZYNQMP_NUM_CPUS 4
132+
133+typedef struct XlnxZynqMPState {
134+ /*< private >*/
135+ DeviceState parent_obj;
136+ /*< public >*/
137+
138+ ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
139+} XlnxZynqMPState;
140+
141+#define XLNX_ZYNQMP_H_
142+#endif
143--
1441.7.10.4
145
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch
deleted file mode 100644
index c9cc17c3..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0004-arm-xlnx-zynqmp-Add-GIC.patch
+++ /dev/null
@@ -1,84 +0,0 @@
1From c10adfae330dababc9752d02431e8e7b098f3ce2 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:13 -0700
4Subject: [PATCH 04/15] arm: xlnx-zynqmp: Add GIC
5
6And connect IRQ outputs to the CPUs.
7
8Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
10---
11 hw/arm/xlnx-zynqmp.c | 19 +++++++++++++++++++
12 include/hw/arm/xlnx-zynqmp.h | 2 ++
13 2 files changed, 21 insertions(+)
14
15diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16index 41c207a..9465185 100644
17--- a/hw/arm/xlnx-zynqmp.c
18+++ b/hw/arm/xlnx-zynqmp.c
19@@ -17,6 +17,11 @@
20
21 #include "hw/arm/xlnx-zynqmp.h"
22
23+#define GIC_NUM_SPI_INTR 128
24+
25+#define GIC_DIST_ADDR 0xf9010000
26+#define GIC_CPU_ADDR 0xf9020000
27+
28 static void xlnx_zynqmp_init(Object *obj)
29 {
30 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
31@@ -28,6 +33,9 @@ static void xlnx_zynqmp_init(Object *obj)
32 object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
33 &error_abort);
34 }
35+
36+ object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
37+ qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
38 }
39
40 #define ERR_PROP_CHECK_RETURN(err, errp) do { \
41@@ -43,9 +51,20 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
42 uint8_t i;
43 Error *err = NULL;
44
45+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
46+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
47+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_CPUS);
48+ object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
49+ ERR_PROP_CHECK_RETURN(err, errp);
50+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, GIC_DIST_ADDR);
51+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
52+
53 for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
54 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
55 ERR_PROP_CHECK_RETURN(err, errp);
56+
57+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
58+ qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
59 }
60 }
61
62diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
63index d6b3b92..d29c7de 100644
64--- a/include/hw/arm/xlnx-zynqmp.h
65+++ b/include/hw/arm/xlnx-zynqmp.h
66@@ -2,6 +2,7 @@
67
68 #include "qemu-common.h"
69 #include "hw/arm/arm.h"
70+#include "hw/intc/arm_gic.h"
71
72 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
73 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
74@@ -15,6 +16,7 @@ typedef struct XlnxZynqMPState {
75 /*< public >*/
76
77 ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
78+ GICState gic;
79 } XlnxZynqMPState;
80
81 #define XLNX_ZYNQMP_H_
82--
831.7.10.4
84
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch
deleted file mode 100644
index 487d722c..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch
+++ /dev/null
@@ -1,58 +0,0 @@
1From 6eb0b99419e4f20cef0c0af2847e1635b2dbc04e Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:14 -0700
4Subject: [PATCH 05/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC
5
6Connect the GPIO outputs from the individual CPUs for the timers to the
7GIC.
8
9Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
10---
11 hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
12 1 file changed, 16 insertions(+)
13
14diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
15index 9465185..29954f5 100644
16--- a/hw/arm/xlnx-zynqmp.c
17+++ b/hw/arm/xlnx-zynqmp.c
18@@ -19,9 +19,17 @@
19
20 #define GIC_NUM_SPI_INTR 128
21
22+#define ARM_PHYS_TIMER_PPI 30
23+#define ARM_VIRT_TIMER_PPI 27
24+
25 #define GIC_DIST_ADDR 0xf9010000
26 #define GIC_CPU_ADDR 0xf9020000
27
28+static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
29+{
30+ return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
31+}
32+
33 static void xlnx_zynqmp_init(Object *obj)
34 {
35 XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
36@@ -60,11 +68,19 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
37 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, GIC_CPU_ADDR);
38
39 for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
40+ qemu_irq irq;
41+
42 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
43 ERR_PROP_CHECK_RETURN(err, errp);
44
45 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
46 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
47+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
48+ arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
49+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
50+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
51+ arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
52+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
53 }
54 }
55
56--
571.7.10.4
58
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
deleted file mode 100644
index 53453ca9..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0006-net-cadence_gem-Clean-up-variable-names.patch
+++ /dev/null
@@ -1,269 +0,0 @@
1From 7c37c0a33c598fe0dcb015aa4d48712e33e21a8b Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:14 -0700
4Subject: [PATCH 06/15] net: cadence_gem: Clean up variable names
5MIME-Version: 1.0
6Content-Type: text/plain; charset=UTF-8
7Content-Transfer-Encoding: 8bit
8
9In preparation for migrating the state struct and type cast macro to a public
10header. The acronym "GEM" on it's own is not specific enough to be used in a
11more global namespace so preface with "cadence". Fix the capitalisation of
12"gem" in the state type while touching the typename. Also preface the
13GEM_MAXREG macro as this will need to migrate to public header.
14
15Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
16Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
18---
19 hw/net/cadence_gem.c | 70 +++++++++++++++++++++++++-------------------------
20 1 file changed, 35 insertions(+), 35 deletions(-)
21
22diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
23index 55b6293..5994306 100644
24--- a/hw/net/cadence_gem.c
25+++ b/hw/net/cadence_gem.c
26@@ -141,7 +141,7 @@
27 #define GEM_DESCONF6 (0x00000294/4)
28 #define GEM_DESCONF7 (0x00000298/4)
29
30-#define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
31+#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
32
33 /*****************************************/
34 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
35@@ -350,9 +350,9 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
36 }
37
38 #define TYPE_CADENCE_GEM "cadence_gem"
39-#define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM)
40+#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
41
42-typedef struct GemState {
43+typedef struct CadenceGEMState {
44 SysBusDevice parent_obj;
45
46 MemoryRegion iomem;
47@@ -361,15 +361,15 @@ typedef struct GemState {
48 qemu_irq irq;
49
50 /* GEM registers backing store */
51- uint32_t regs[GEM_MAXREG];
52+ uint32_t regs[CADENCE_GEM_MAXREG];
53 /* Mask of register bits which are write only */
54- uint32_t regs_wo[GEM_MAXREG];
55+ uint32_t regs_wo[CADENCE_GEM_MAXREG];
56 /* Mask of register bits which are read only */
57- uint32_t regs_ro[GEM_MAXREG];
58+ uint32_t regs_ro[CADENCE_GEM_MAXREG];
59 /* Mask of register bits which are clear on read */
60- uint32_t regs_rtc[GEM_MAXREG];
61+ uint32_t regs_rtc[CADENCE_GEM_MAXREG];
62 /* Mask of register bits which are write 1 to clear */
63- uint32_t regs_w1c[GEM_MAXREG];
64+ uint32_t regs_w1c[CADENCE_GEM_MAXREG];
65
66 /* PHY registers backing store */
67 uint16_t phy_regs[32];
68@@ -385,7 +385,7 @@ typedef struct GemState {
69 unsigned rx_desc[2];
70
71 bool sar_active[4];
72-} GemState;
73+} CadenceGEMState;
74
75 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
76 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
77@@ -395,7 +395,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
78 * One time initialization.
79 * Set masks to identify which register bits have magical clear properties
80 */
81-static void gem_init_register_masks(GemState *s)
82+static void gem_init_register_masks(CadenceGEMState *s)
83 {
84 /* Mask of register bits which are read only */
85 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
86@@ -430,7 +430,7 @@ static void gem_init_register_masks(GemState *s)
87 * phy_update_link:
88 * Make the emulated PHY link state match the QEMU "interface" state.
89 */
90-static void phy_update_link(GemState *s)
91+static void phy_update_link(CadenceGEMState *s)
92 {
93 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
94
95@@ -450,7 +450,7 @@ static void phy_update_link(GemState *s)
96
97 static int gem_can_receive(NetClientState *nc)
98 {
99- GemState *s;
100+ CadenceGEMState *s;
101
102 s = qemu_get_nic_opaque(nc);
103
104@@ -483,7 +483,7 @@ static int gem_can_receive(NetClientState *nc)
105 * gem_update_int_status:
106 * Raise or lower interrupt based on current status.
107 */
108-static void gem_update_int_status(GemState *s)
109+static void gem_update_int_status(CadenceGEMState *s)
110 {
111 if (s->regs[GEM_ISR]) {
112 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]);
113@@ -495,7 +495,7 @@ static void gem_update_int_status(GemState *s)
114 * gem_receive_updatestats:
115 * Increment receive statistics.
116 */
117-static void gem_receive_updatestats(GemState *s, const uint8_t *packet,
118+static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
119 unsigned bytes)
120 {
121 uint64_t octets;
122@@ -586,7 +586,7 @@ static unsigned calc_mac_hash(const uint8_t *mac)
123 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
124 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
125 */
126-static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
127+static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
128 {
129 uint8_t *gem_spaddr;
130 int i;
131@@ -636,7 +636,7 @@ static int gem_mac_address_filter(GemState *s, const uint8_t *packet)
132 return GEM_RX_REJECT;
133 }
134
135-static void gem_get_rx_desc(GemState *s)
136+static void gem_get_rx_desc(CadenceGEMState *s)
137 {
138 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr);
139 /* read current descriptor */
140@@ -660,7 +660,7 @@ static void gem_get_rx_desc(GemState *s)
141 */
142 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
143 {
144- GemState *s;
145+ CadenceGEMState *s;
146 unsigned rxbufsize, bytes_to_copy;
147 unsigned rxbuf_offset;
148 uint8_t rxbuf[2048];
149@@ -810,7 +810,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
150 * gem_transmit_updatestats:
151 * Increment transmit statistics.
152 */
153-static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
154+static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
155 unsigned bytes)
156 {
157 uint64_t octets;
158@@ -856,7 +856,7 @@ static void gem_transmit_updatestats(GemState *s, const uint8_t *packet,
159 * gem_transmit:
160 * Fish packets out of the descriptor ring and feed them to QEMU
161 */
162-static void gem_transmit(GemState *s)
163+static void gem_transmit(CadenceGEMState *s)
164 {
165 unsigned desc[2];
166 hwaddr packet_desc_addr;
167@@ -976,7 +976,7 @@ static void gem_transmit(GemState *s)
168 }
169 }
170
171-static void gem_phy_reset(GemState *s)
172+static void gem_phy_reset(CadenceGEMState *s)
173 {
174 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
175 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
176@@ -1004,7 +1004,7 @@ static void gem_phy_reset(GemState *s)
177 static void gem_reset(DeviceState *d)
178 {
179 int i;
180- GemState *s = GEM(d);
181+ CadenceGEMState *s = CADENCE_GEM(d);
182
183 DB_PRINT("\n");
184
185@@ -1032,13 +1032,13 @@ static void gem_reset(DeviceState *d)
186 gem_update_int_status(s);
187 }
188
189-static uint16_t gem_phy_read(GemState *s, unsigned reg_num)
190+static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
191 {
192 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
193 return s->phy_regs[reg_num];
194 }
195
196-static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
197+static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
198 {
199 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
200
201@@ -1072,10 +1072,10 @@ static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val)
202 */
203 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
204 {
205- GemState *s;
206+ CadenceGEMState *s;
207 uint32_t retval;
208
209- s = (GemState *)opaque;
210+ s = (CadenceGEMState *)opaque;
211
212 offset >>= 2;
213 retval = s->regs[offset];
214@@ -1120,7 +1120,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
215 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
216 unsigned size)
217 {
218- GemState *s = (GemState *)opaque;
219+ CadenceGEMState *s = (CadenceGEMState *)opaque;
220 uint32_t readonly;
221
222 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
223@@ -1226,7 +1226,7 @@ static NetClientInfo net_gem_info = {
224 static int gem_init(SysBusDevice *sbd)
225 {
226 DeviceState *dev = DEVICE(sbd);
227- GemState *s = GEM(dev);
228+ CadenceGEMState *s = CADENCE_GEM(dev);
229
230 DB_PRINT("\n");
231
232@@ -1248,18 +1248,18 @@ static const VMStateDescription vmstate_cadence_gem = {
233 .version_id = 2,
234 .minimum_version_id = 2,
235 .fields = (VMStateField[]) {
236- VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG),
237- VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32),
238- VMSTATE_UINT8(phy_loop, GemState),
239- VMSTATE_UINT32(rx_desc_addr, GemState),
240- VMSTATE_UINT32(tx_desc_addr, GemState),
241- VMSTATE_BOOL_ARRAY(sar_active, GemState, 4),
242+ VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
243+ VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
244+ VMSTATE_UINT8(phy_loop, CadenceGEMState),
245+ VMSTATE_UINT32(rx_desc_addr, CadenceGEMState),
246+ VMSTATE_UINT32(tx_desc_addr, CadenceGEMState),
247+ VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
248 VMSTATE_END_OF_LIST(),
249 }
250 };
251
252 static Property gem_properties[] = {
253- DEFINE_NIC_PROPERTIES(GemState, conf),
254+ DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
255 DEFINE_PROP_END_OF_LIST(),
256 };
257
258@@ -1277,7 +1277,7 @@ static void gem_class_init(ObjectClass *klass, void *data)
259 static const TypeInfo gem_info = {
260 .name = TYPE_CADENCE_GEM,
261 .parent = TYPE_SYS_BUS_DEVICE,
262- .instance_size = sizeof(GemState),
263+ .instance_size = sizeof(CadenceGEMState),
264 .class_init = gem_class_init,
265 };
266
267--
2681.7.10.4
269
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
deleted file mode 100644
index e468563b..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch
+++ /dev/null
@@ -1,143 +0,0 @@
1From 9f9cd8a67975d0973bf5d0dd0bdf6e0bff168774 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:15 -0700
4Subject: [PATCH 07/15] net: cadence_gem: Split state struct and type into
5 header
6
7To allow using the device with modern SoC programming conventions. The
8state struct needs to be visible to embed the device in SoC containers.
9
10Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
12---
13 hw/net/cadence_gem.c | 43 +-----------------------------------
14 include/hw/net/cadence_gem.h | 49 ++++++++++++++++++++++++++++++++++++++++++
15 2 files changed, 50 insertions(+), 42 deletions(-)
16 create mode 100644 include/hw/net/cadence_gem.h
17
18diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
19index 5994306..dafe914 100644
20--- a/hw/net/cadence_gem.c
21+++ b/hw/net/cadence_gem.c
22@@ -24,8 +24,7 @@
23
24 #include <zlib.h> /* For crc32 */
25
26-#include "hw/sysbus.h"
27-#include "net/net.h"
28+#include "hw/net/cadence_gem.h"
29 #include "net/checksum.h"
30
31 #ifdef CADENCE_GEM_ERR_DEBUG
32@@ -141,8 +140,6 @@
33 #define GEM_DESCONF6 (0x00000294/4)
34 #define GEM_DESCONF7 (0x00000298/4)
35
36-#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
37-
38 /*****************************************/
39 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
40 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
41@@ -349,44 +346,6 @@ static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
42 desc[1] |= R_DESC_1_RX_SAR_MATCH;
43 }
44
45-#define TYPE_CADENCE_GEM "cadence_gem"
46-#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
47-
48-typedef struct CadenceGEMState {
49- SysBusDevice parent_obj;
50-
51- MemoryRegion iomem;
52- NICState *nic;
53- NICConf conf;
54- qemu_irq irq;
55-
56- /* GEM registers backing store */
57- uint32_t regs[CADENCE_GEM_MAXREG];
58- /* Mask of register bits which are write only */
59- uint32_t regs_wo[CADENCE_GEM_MAXREG];
60- /* Mask of register bits which are read only */
61- uint32_t regs_ro[CADENCE_GEM_MAXREG];
62- /* Mask of register bits which are clear on read */
63- uint32_t regs_rtc[CADENCE_GEM_MAXREG];
64- /* Mask of register bits which are write 1 to clear */
65- uint32_t regs_w1c[CADENCE_GEM_MAXREG];
66-
67- /* PHY registers backing store */
68- uint16_t phy_regs[32];
69-
70- uint8_t phy_loop; /* Are we in phy loopback? */
71-
72- /* The current DMA descriptor pointers */
73- uint32_t rx_desc_addr;
74- uint32_t tx_desc_addr;
75-
76- uint8_t can_rx_state; /* Debug only */
77-
78- unsigned rx_desc[2];
79-
80- bool sar_active[4];
81-} CadenceGEMState;
82-
83 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
84 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
85
86diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
87new file mode 100644
88index 0000000..12de820
89--- /dev/null
90+++ b/include/hw/net/cadence_gem.h
91@@ -0,0 +1,49 @@
92+#ifndef CADENCE_GEM_H_
93+
94+#define TYPE_CADENCE_GEM "cadence_gem"
95+#define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
96+
97+#include "net/net.h"
98+#include "hw/sysbus.h"
99+
100+#define CADENCE_GEM_MAXREG (0x00000640/4) /* Last valid GEM address */
101+
102+typedef struct CadenceGEMState {
103+ /*< private >*/
104+ SysBusDevice parent_obj;
105+
106+ /*< public >*/
107+ MemoryRegion iomem;
108+ NICState *nic;
109+ NICConf conf;
110+ qemu_irq irq;
111+
112+ /* GEM registers backing store */
113+ uint32_t regs[CADENCE_GEM_MAXREG];
114+ /* Mask of register bits which are write only */
115+ uint32_t regs_wo[CADENCE_GEM_MAXREG];
116+ /* Mask of register bits which are read only */
117+ uint32_t regs_ro[CADENCE_GEM_MAXREG];
118+ /* Mask of register bits which are clear on read */
119+ uint32_t regs_rtc[CADENCE_GEM_MAXREG];
120+ /* Mask of register bits which are write 1 to clear */
121+ uint32_t regs_w1c[CADENCE_GEM_MAXREG];
122+
123+ /* PHY registers backing store */
124+ uint16_t phy_regs[32];
125+
126+ uint8_t phy_loop; /* Are we in phy loopback? */
127+
128+ /* The current DMA descriptor pointers */
129+ uint32_t rx_desc_addr;
130+ uint32_t tx_desc_addr;
131+
132+ uint8_t can_rx_state; /* Debug only */
133+
134+ unsigned rx_desc[2];
135+
136+ bool sar_active[4];
137+} CadenceGEMState;
138+
139+#define CADENCE_GEM_H_
140+#endif
141--
1421.7.10.4
143
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch
deleted file mode 100644
index 9441f609..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0008-arm-xilinx-zynqmp-Add-GEM-support.patch
+++ /dev/null
@@ -1,107 +0,0 @@
1From 5f3d79a3b5ede9d2da63dded227f7cdf44e7d476 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Wed, 18 Feb 2015 18:56:37 -0800
4Subject: [PATCH 08/15] arm: xilinx-zynqmp: Add GEM support
5
6There are 4x Cadence GEMs in ZynqMP. Add them.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9---
10 hw/arm/xlnx-zynqmp.c | 32 ++++++++++++++++++++++++++++++++
11 include/hw/arm/xlnx-zynqmp.h | 3 +++
12 2 files changed, 35 insertions(+)
13
14diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
15index 29954f5..d8c648d 100644
16--- a/hw/arm/xlnx-zynqmp.c
17+++ b/hw/arm/xlnx-zynqmp.c
18@@ -25,6 +25,14 @@
19 #define GIC_DIST_ADDR 0xf9010000
20 #define GIC_CPU_ADDR 0xf9020000
21
22+static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
23+ 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
24+};
25+
26+static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
27+ 57, 59, 61, 63,
28+};
29+
30 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
31 {
32 return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
33@@ -44,6 +52,11 @@ static void xlnx_zynqmp_init(Object *obj)
34
35 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
36 qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
37+
38+ for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
39+ object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
40+ qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
41+ }
42 }
43
44 #define ERR_PROP_CHECK_RETURN(err, errp) do { \
45@@ -57,6 +70,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
46 {
47 XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
48 uint8_t i;
49+ qemu_irq gic_spi[GIC_NUM_SPI_INTR];
50 Error *err = NULL;
51
52 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
53@@ -82,6 +96,24 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
54 arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
55 qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
56 }
57+
58+ for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
59+ gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
60+ }
61+
62+ for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
63+ NICInfo *nd = &nd_table[i];
64+
65+ if (nd->used) {
66+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
67+ qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
68+ }
69+ object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
70+ ERR_PROP_CHECK_RETURN(err, errp);
71+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
72+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
73+ gic_spi[gem_intr[i]]);
74+ }
75 }
76
77 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
78diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
79index d29c7de..12a1be1 100644
80--- a/include/hw/arm/xlnx-zynqmp.h
81+++ b/include/hw/arm/xlnx-zynqmp.h
82@@ -3,12 +3,14 @@
83 #include "qemu-common.h"
84 #include "hw/arm/arm.h"
85 #include "hw/intc/arm_gic.h"
86+#include "hw/net/cadence_gem.h"
87
88 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
89 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
90 TYPE_XLNX_ZYNQMP)
91
92 #define XLNX_ZYNQMP_NUM_CPUS 4
93+#define XLNX_ZYNQMP_NUM_GEMS 4
94
95 typedef struct XlnxZynqMPState {
96 /*< private >*/
97@@ -17,6 +19,7 @@ typedef struct XlnxZynqMPState {
98
99 ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
100 GICState gic;
101+ CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
102 } XlnxZynqMPState;
103
104 #define XLNX_ZYNQMP_H_
105--
1061.7.10.4
107
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch
deleted file mode 100644
index d94b23ad..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0009-char-cadence_uart-Clean-up-variable-names.patch
+++ /dev/null
@@ -1,334 +0,0 @@
1From 7f5e56c8f0a8393b9cb930883059d873802338c6 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:16 -0700
4Subject: [PATCH 09/15] char: cadence_uart: Clean up variable names
5
6In preparation for migrating the state struct and type cast macro to a public
7header. The acronym "UART" on it's own is not specific enough to be used in a
8more global namespace so preface with "cadence". Fix the capitalisation of
9"uart" in the state type while touching the typename. Preface macros
10used by the state struct itself with CADENCE_UART so they don't conflict
11in namespace either.
12
13Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
14Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
15---
16 hw/char/cadence_uart.c | 102 +++++++++++++++++++++++++-----------------------
17 1 file changed, 54 insertions(+), 48 deletions(-)
18
19diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
20index d145378..4a4d3eb 100644
21--- a/hw/char/cadence_uart.c
22+++ b/hw/char/cadence_uart.c
23@@ -85,8 +85,8 @@
24 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
25 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
26
27-#define RX_FIFO_SIZE 16
28-#define TX_FIFO_SIZE 16
29+#define CADENCE_UART_RX_FIFO_SIZE 16
30+#define CADENCE_UART_TX_FIFO_SIZE 16
31 #define UART_INPUT_CLK 50000000
32
33 #define R_CR (0x00/4)
34@@ -108,10 +108,11 @@
35 #define R_PWID (0x40/4)
36 #define R_TTRIG (0x44/4)
37
38-#define R_MAX (R_TTRIG + 1)
39+#define CADENCE_UART_R_MAX (0x48/4)
40
41 #define TYPE_CADENCE_UART "cadence_uart"
42-#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
43+#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
44+ TYPE_CADENCE_UART)
45
46 typedef struct {
47 /*< private >*/
48@@ -119,9 +120,9 @@ typedef struct {
49 /*< public >*/
50
51 MemoryRegion iomem;
52- uint32_t r[R_MAX];
53- uint8_t rx_fifo[RX_FIFO_SIZE];
54- uint8_t tx_fifo[TX_FIFO_SIZE];
55+ uint32_t r[CADENCE_UART_R_MAX];
56+ uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
57+ uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
58 uint32_t rx_wpos;
59 uint32_t rx_count;
60 uint32_t tx_count;
61@@ -129,17 +130,19 @@ typedef struct {
62 CharDriverState *chr;
63 qemu_irq irq;
64 QEMUTimer *fifo_trigger_handle;
65-} UartState;
66+} CadenceUARTState;
67
68-static void uart_update_status(UartState *s)
69+static void uart_update_status(CadenceUARTState *s)
70 {
71 s->r[R_SR] = 0;
72
73- s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
74+ s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
75+ : 0;
76 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
77 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
78
79- s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
80+ s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
81+ : 0;
82 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
83 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
84
85@@ -150,14 +153,14 @@ static void uart_update_status(UartState *s)
86
87 static void fifo_trigger_update(void *opaque)
88 {
89- UartState *s = (UartState *)opaque;
90+ CadenceUARTState *s = opaque;
91
92 s->r[R_CISR] |= UART_INTR_TIMEOUT;
93
94 uart_update_status(s);
95 }
96
97-static void uart_rx_reset(UartState *s)
98+static void uart_rx_reset(CadenceUARTState *s)
99 {
100 s->rx_wpos = 0;
101 s->rx_count = 0;
102@@ -166,12 +169,12 @@ static void uart_rx_reset(UartState *s)
103 }
104 }
105
106-static void uart_tx_reset(UartState *s)
107+static void uart_tx_reset(CadenceUARTState *s)
108 {
109 s->tx_count = 0;
110 }
111
112-static void uart_send_breaks(UartState *s)
113+static void uart_send_breaks(CadenceUARTState *s)
114 {
115 int break_enabled = 1;
116
117@@ -181,7 +184,7 @@ static void uart_send_breaks(UartState *s)
118 }
119 }
120
121-static void uart_parameters_setup(UartState *s)
122+static void uart_parameters_setup(CadenceUARTState *s)
123 {
124 QEMUSerialSetParams ssp;
125 unsigned int baud_rate, packet_size;
126@@ -236,20 +239,20 @@ static void uart_parameters_setup(UartState *s)
127
128 static int uart_can_receive(void *opaque)
129 {
130- UartState *s = (UartState *)opaque;
131- int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE);
132+ CadenceUARTState *s = opaque;
133+ int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
134 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
135
136 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
137- ret = MIN(ret, RX_FIFO_SIZE - s->rx_count);
138+ ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
139 }
140 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
141- ret = MIN(ret, TX_FIFO_SIZE - s->tx_count);
142+ ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
143 }
144 return ret;
145 }
146
147-static void uart_ctrl_update(UartState *s)
148+static void uart_ctrl_update(CadenceUARTState *s)
149 {
150 if (s->r[R_CR] & UART_CR_TXRST) {
151 uart_tx_reset(s);
152@@ -268,7 +271,7 @@ static void uart_ctrl_update(UartState *s)
153
154 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
155 {
156- UartState *s = (UartState *)opaque;
157+ CadenceUARTState *s = opaque;
158 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
159 int i;
160
161@@ -276,12 +279,12 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
162 return;
163 }
164
165- if (s->rx_count == RX_FIFO_SIZE) {
166+ if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
167 s->r[R_CISR] |= UART_INTR_ROVR;
168 } else {
169 for (i = 0; i < size; i++) {
170 s->rx_fifo[s->rx_wpos] = buf[i];
171- s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
172+ s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
173 s->rx_count++;
174 }
175 timer_mod(s->fifo_trigger_handle, new_rx_time +
176@@ -293,7 +296,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
177 static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
178 void *opaque)
179 {
180- UartState *s = opaque;
181+ CadenceUARTState *s = opaque;
182 int ret;
183
184 /* instant drain the fifo when there's no back-end */
185@@ -320,14 +323,15 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
186 return FALSE;
187 }
188
189-static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
190+static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
191+ int size)
192 {
193 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
194 return;
195 }
196
197- if (size > TX_FIFO_SIZE - s->tx_count) {
198- size = TX_FIFO_SIZE - s->tx_count;
199+ if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
200+ size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
201 /*
202 * This can only be a guest error via a bad tx fifo register push,
203 * as can_receive() should stop remote loop and echo modes ever getting
204@@ -345,7 +349,7 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
205
206 static void uart_receive(void *opaque, const uint8_t *buf, int size)
207 {
208- UartState *s = (UartState *)opaque;
209+ CadenceUARTState *s = opaque;
210 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
211
212 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
213@@ -358,7 +362,7 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
214
215 static void uart_event(void *opaque, int event)
216 {
217- UartState *s = (UartState *)opaque;
218+ CadenceUARTState *s = opaque;
219 uint8_t buf = '\0';
220
221 if (event == CHR_EVENT_BREAK) {
222@@ -368,15 +372,15 @@ static void uart_event(void *opaque, int event)
223 uart_update_status(s);
224 }
225
226-static void uart_read_rx_fifo(UartState *s, uint32_t *c)
227+static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
228 {
229 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
230 return;
231 }
232
233 if (s->rx_count) {
234- uint32_t rx_rpos =
235- (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
236+ uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
237+ s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
238 *c = s->rx_fifo[rx_rpos];
239 s->rx_count--;
240
241@@ -393,7 +397,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
242 static void uart_write(void *opaque, hwaddr offset,
243 uint64_t value, unsigned size)
244 {
245- UartState *s = (UartState *)opaque;
246+ CadenceUARTState *s = opaque;
247
248 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
249 offset >>= 2;
250@@ -437,11 +441,11 @@ static void uart_write(void *opaque, hwaddr offset,
251 static uint64_t uart_read(void *opaque, hwaddr offset,
252 unsigned size)
253 {
254- UartState *s = (UartState *)opaque;
255+ CadenceUARTState *s = opaque;
256 uint32_t c = 0;
257
258 offset >>= 2;
259- if (offset >= R_MAX) {
260+ if (offset >= CADENCE_UART_R_MAX) {
261 c = 0;
262 } else if (offset == R_TX_RX) {
263 uart_read_rx_fifo(s, &c);
264@@ -461,7 +465,7 @@ static const MemoryRegionOps uart_ops = {
265
266 static void cadence_uart_reset(DeviceState *dev)
267 {
268- UartState *s = CADENCE_UART(dev);
269+ CadenceUARTState *s = CADENCE_UART(dev);
270
271 s->r[R_CR] = 0x00000128;
272 s->r[R_IMR] = 0;
273@@ -478,7 +482,7 @@ static void cadence_uart_reset(DeviceState *dev)
274
275 static void cadence_uart_realize(DeviceState *dev, Error **errp)
276 {
277- UartState *s = CADENCE_UART(dev);
278+ CadenceUARTState *s = CADENCE_UART(dev);
279
280 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
281 fifo_trigger_update, s);
282@@ -495,7 +499,7 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
283 static void cadence_uart_init(Object *obj)
284 {
285 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
286- UartState *s = CADENCE_UART(obj);
287+ CadenceUARTState *s = CADENCE_UART(obj);
288
289 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
290 sysbus_init_mmio(sbd, &s->iomem);
291@@ -506,7 +510,7 @@ static void cadence_uart_init(Object *obj)
292
293 static int cadence_uart_post_load(void *opaque, int version_id)
294 {
295- UartState *s = opaque;
296+ CadenceUARTState *s = opaque;
297
298 uart_parameters_setup(s);
299 uart_update_status(s);
300@@ -519,13 +523,15 @@ static const VMStateDescription vmstate_cadence_uart = {
301 .minimum_version_id = 2,
302 .post_load = cadence_uart_post_load,
303 .fields = (VMStateField[]) {
304- VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
305- VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
306- VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
307- VMSTATE_UINT32(rx_count, UartState),
308- VMSTATE_UINT32(tx_count, UartState),
309- VMSTATE_UINT32(rx_wpos, UartState),
310- VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState),
311+ VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
312+ VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
313+ CADENCE_UART_RX_FIFO_SIZE),
314+ VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
315+ CADENCE_UART_TX_FIFO_SIZE),
316+ VMSTATE_UINT32(rx_count, CadenceUARTState),
317+ VMSTATE_UINT32(tx_count, CadenceUARTState),
318+ VMSTATE_UINT32(rx_wpos, CadenceUARTState),
319+ VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
320 VMSTATE_END_OF_LIST()
321 }
322 };
323@@ -544,7 +550,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data)
324 static const TypeInfo cadence_uart_info = {
325 .name = TYPE_CADENCE_UART,
326 .parent = TYPE_SYS_BUS_DEVICE,
327- .instance_size = sizeof(UartState),
328+ .instance_size = sizeof(CadenceUARTState),
329 .instance_init = cadence_uart_init,
330 .class_init = cadence_uart_class_init,
331 };
332--
3331.7.10.4
334
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch
deleted file mode 100644
index e56aed88..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch
+++ /dev/null
@@ -1,115 +0,0 @@
1From f50fc4d6e1ee32e47f0f9cd6b8b98aa754ced588 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:16 -0700
4Subject: [PATCH 10/15] char: cadence_uart: Split state struct and type into
5 header
6
7To allow using the device with modern SoC programming conventions. The
8state struct needs to be visible to embed the device in SoC containers.
9
10Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
12---
13 hw/char/cadence_uart.c | 29 +----------------------------
14 include/hw/char/cadence_uart.h | 35 +++++++++++++++++++++++++++++++++++
15 2 files changed, 36 insertions(+), 28 deletions(-)
16 create mode 100644 include/hw/char/cadence_uart.h
17
18diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
19index 4a4d3eb..9d379e5 100644
20--- a/hw/char/cadence_uart.c
21+++ b/hw/char/cadence_uart.c
22@@ -16,9 +16,7 @@
23 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 */
25
26-#include "hw/sysbus.h"
27-#include "sysemu/char.h"
28-#include "qemu/timer.h"
29+#include "hw/char/cadence_uart.h"
30
31 #ifdef CADENCE_UART_ERR_DEBUG
32 #define DB_PRINT(...) do { \
33@@ -85,8 +83,6 @@
34 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
35 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
36
37-#define CADENCE_UART_RX_FIFO_SIZE 16
38-#define CADENCE_UART_TX_FIFO_SIZE 16
39 #define UART_INPUT_CLK 50000000
40
41 #define R_CR (0x00/4)
42@@ -108,29 +104,6 @@
43 #define R_PWID (0x40/4)
44 #define R_TTRIG (0x44/4)
45
46-#define CADENCE_UART_R_MAX (0x48/4)
47-
48-#define TYPE_CADENCE_UART "cadence_uart"
49-#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
50- TYPE_CADENCE_UART)
51-
52-typedef struct {
53- /*< private >*/
54- SysBusDevice parent_obj;
55- /*< public >*/
56-
57- MemoryRegion iomem;
58- uint32_t r[CADENCE_UART_R_MAX];
59- uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
60- uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
61- uint32_t rx_wpos;
62- uint32_t rx_count;
63- uint32_t tx_count;
64- uint64_t char_tx_time;
65- CharDriverState *chr;
66- qemu_irq irq;
67- QEMUTimer *fifo_trigger_handle;
68-} CadenceUARTState;
69
70 static void uart_update_status(CadenceUARTState *s)
71 {
72diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
73new file mode 100644
74index 0000000..3456d4c
75--- /dev/null
76+++ b/include/hw/char/cadence_uart.h
77@@ -0,0 +1,35 @@
78+#ifndef CADENCE_UART_H_
79+
80+#include "hw/sysbus.h"
81+#include "sysemu/char.h"
82+#include "qemu/timer.h"
83+
84+#define CADENCE_UART_RX_FIFO_SIZE 16
85+#define CADENCE_UART_TX_FIFO_SIZE 16
86+
87+#define CADENCE_UART_R_MAX (0x48/4)
88+
89+#define TYPE_CADENCE_UART "cadence_uart"
90+#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
91+ TYPE_CADENCE_UART)
92+
93+typedef struct {
94+ /*< private >*/
95+ SysBusDevice parent_obj;
96+
97+ /*< public >*/
98+ MemoryRegion iomem;
99+ uint32_t r[CADENCE_UART_R_MAX];
100+ uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
101+ uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
102+ uint32_t rx_wpos;
103+ uint32_t rx_count;
104+ uint32_t tx_count;
105+ uint64_t char_tx_time;
106+ CharDriverState *chr;
107+ qemu_irq irq;
108+ QEMUTimer *fifo_trigger_handle;
109+} CadenceUARTState;
110+
111+#define CADENCE_UART_H_
112+#endif
113--
1141.7.10.4
115
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch
deleted file mode 100644
index ccf86cf7..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0011-arm-xilinx-zynqmp-Add-UART-support.patch
+++ /dev/null
@@ -1,91 +0,0 @@
1From d35149eea398ca20d0c1ec382e9fce5e2c229ce0 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Wed, 18 Feb 2015 18:56:37 -0800
4Subject: [PATCH 11/15] arm: xilinx-zynqmp: Add UART support
5
6There are 2x Cadence UARTs in Zynq MP. Add them.
7
8Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
9Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
10---
11 hw/arm/xlnx-zynqmp.c | 21 +++++++++++++++++++++
12 include/hw/arm/xlnx-zynqmp.h | 3 +++
13 2 files changed, 24 insertions(+)
14
15diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16index d8c648d..e015025 100644
17--- a/hw/arm/xlnx-zynqmp.c
18+++ b/hw/arm/xlnx-zynqmp.c
19@@ -33,6 +33,14 @@ static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
20 57, 59, 61, 63,
21 };
22
23+static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
24+ 0xFF000000, 0xFF010000,
25+};
26+
27+static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
28+ 21, 22,
29+};
30+
31 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
32 {
33 return GIC_NUM_SPI_INTR + cpu_nr * 32 + ppi_index;
34@@ -57,6 +65,11 @@ static void xlnx_zynqmp_init(Object *obj)
35 object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
36 qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
37 }
38+
39+ for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
40+ object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
41+ qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
42+ }
43 }
44
45 #define ERR_PROP_CHECK_RETURN(err, errp) do { \
46@@ -114,6 +127,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
47 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
48 gic_spi[gem_intr[i]]);
49 }
50+
51+ for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
52+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
53+ ERR_PROP_CHECK_RETURN(err, errp);
54+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
55+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
56+ gic_spi[uart_intr[i]]);
57+ }
58 }
59
60 static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
61diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
62index 12a1be1..62d8d3f 100644
63--- a/include/hw/arm/xlnx-zynqmp.h
64+++ b/include/hw/arm/xlnx-zynqmp.h
65@@ -4,6 +4,7 @@
66 #include "hw/arm/arm.h"
67 #include "hw/intc/arm_gic.h"
68 #include "hw/net/cadence_gem.h"
69+#include "hw/char/cadence_uart.h"
70
71 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
72 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
73@@ -11,6 +12,7 @@
74
75 #define XLNX_ZYNQMP_NUM_CPUS 4
76 #define XLNX_ZYNQMP_NUM_GEMS 4
77+#define XLNX_ZYNQMP_NUM_UARTS 2
78
79 typedef struct XlnxZynqMPState {
80 /*< private >*/
81@@ -20,6 +22,7 @@ typedef struct XlnxZynqMPState {
82 ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS];
83 GICState gic;
84 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
85+ CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
86 } XlnxZynqMPState;
87
88 #define XLNX_ZYNQMP_H_
89--
901.7.10.4
91
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch
deleted file mode 100644
index 4c7d05aa..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0012-arm-Add-xlnx-ep108-machine.patch
+++ /dev/null
@@ -1,87 +0,0 @@
1From 0b9dbaa31007d9d7ef8bafcdcb756ffdcc591e03 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:17 -0700
4Subject: [PATCH 12/15] arm: Add xlnx-ep108 machine
5
6Add a machine model for the Xilinx ZynqMP SoC EP108 board.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10---
11 hw/arm/Makefile.objs | 2 +-
12 hw/arm/xlnx-ep108.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++
13 2 files changed, 54 insertions(+), 1 deletion(-)
14 create mode 100644 hw/arm/xlnx-ep108.c
15
16diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17index d7cd5f4..a75a182 100644
18--- a/hw/arm/Makefile.objs
19+++ b/hw/arm/Makefile.objs
20@@ -10,4 +10,4 @@ obj-$(CONFIG_DIGIC) += digic.o
21 obj-y += omap1.o omap2.o strongarm.o
22 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
23 obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
24-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o
25+obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
26diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
27new file mode 100644
28index 0000000..81704bb
29--- /dev/null
30+++ b/hw/arm/xlnx-ep108.c
31@@ -0,0 +1,53 @@
32+/*
33+ * Xilinx ZynqMP EP108 board
34+ *
35+ * Copyright (C) 2015 Xilinx Inc
36+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
37+ *
38+ * This program is free software; you can redistribute it and/or modify it
39+ * under the terms of the GNU General Public License as published by the
40+ * Free Software Foundation; either version 2 of the License, or
41+ * (at your option) any later version.
42+ *
43+ * This program is distributed in the hope that it will be useful, but WITHOUT
44+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
45+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
46+ * for more details.
47+ */
48+
49+#include "hw/arm/xlnx-zynqmp.h"
50+#include "hw/boards.h"
51+#include "qemu/error-report.h"
52+
53+typedef struct XlnxEP108 {
54+ XlnxZynqMPState soc;
55+} XlnxEP108;
56+
57+static void xlnx_ep108_init(MachineState *machine)
58+{
59+ XlnxEP108 *s = g_new0(XlnxEP108, 1);
60+ Error *err = NULL;
61+
62+ object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
63+ object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
64+ &error_abort);
65+
66+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
67+ if (err) {
68+ error_report("%s", error_get_pretty(err));
69+ exit(1);
70+ }
71+}
72+
73+static QEMUMachine xlnx_ep108_machine = {
74+ .name = "xlnx-ep108",
75+ .desc = "Xilinx ZynqMP EP108 board",
76+ .init = xlnx_ep108_init,
77+};
78+
79+static void xlnx_ep108_machine_init(void)
80+{
81+ qemu_register_machine(&xlnx_ep108_machine);
82+}
83+
84+machine_init(xlnx_ep108_machine_init);
85--
861.7.10.4
87
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch
deleted file mode 100644
index 2030048e..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0013-arm-xilinx-ep108-Add-external-RAM.patch
+++ /dev/null
@@ -1,60 +0,0 @@
1From 7c16af47e2ec33043ca0ef924232c9eef9dc60c4 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:18 -0700
4Subject: [PATCH 13/15] arm: xilinx-ep108: Add external RAM
5
6Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10---
11 hw/arm/xlnx-ep108.c | 21 +++++++++++++++++++++
12 1 file changed, 21 insertions(+)
13
14diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
15index 81704bb..6e89456 100644
16--- a/hw/arm/xlnx-ep108.c
17+++ b/hw/arm/xlnx-ep108.c
18@@ -18,11 +18,16 @@
19 #include "hw/arm/xlnx-zynqmp.h"
20 #include "hw/boards.h"
21 #include "qemu/error-report.h"
22+#include "exec/address-spaces.h"
23
24 typedef struct XlnxEP108 {
25 XlnxZynqMPState soc;
26+ MemoryRegion ddr_ram;
27 } XlnxEP108;
28
29+/* Max 2GB RAM */
30+#define EP108_MAX_RAM_SIZE 0x80000000ull
31+
32 static void xlnx_ep108_init(MachineState *machine)
33 {
34 XlnxEP108 *s = g_new0(XlnxEP108, 1);
35@@ -37,6 +42,22 @@ static void xlnx_ep108_init(MachineState *machine)
36 error_report("%s", error_get_pretty(err));
37 exit(1);
38 }
39+
40+ if (machine->ram_size > EP108_MAX_RAM_SIZE) {
41+ error_report("WARNING: RAM size " RAM_ADDR_FMT " above max supported, "
42+ "reduced to %llx", machine->ram_size, EP108_MAX_RAM_SIZE);
43+ machine->ram_size = EP108_MAX_RAM_SIZE;
44+ }
45+
46+ if (machine->ram_size <= 0x08000000) {
47+ error_report("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108\n",
48+ machine->ram_size);
49+ }
50+
51+ memory_region_init_ram(&s->ddr_ram, NULL, "ddr-ram", machine->ram_size,
52+ &error_abort);
53+ vmstate_register_ram_global(&s->ddr_ram);
54+ memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
55 }
56
57 static QEMUMachine xlnx_ep108_machine = {
58--
591.7.10.4
60
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch
deleted file mode 100644
index 1a9a8a8f..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0014-arm-xilinx-ep108-Add-bootloading.patch
+++ /dev/null
@@ -1,42 +0,0 @@
1From 409477e2655e2169c5dd38de8cec00c863869670 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:18 -0700
4Subject: [PATCH 14/15] arm: xilinx-ep108: Add bootloading
5
6Using standard ARM bootloader.
7
8Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10---
11 hw/arm/xlnx-ep108.c | 8 ++++++++
12 1 file changed, 8 insertions(+)
13
14diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
15index 6e89456..a86f595 100644
16--- a/hw/arm/xlnx-ep108.c
17+++ b/hw/arm/xlnx-ep108.c
18@@ -28,6 +28,8 @@ typedef struct XlnxEP108 {
19 /* Max 2GB RAM */
20 #define EP108_MAX_RAM_SIZE 0x80000000ull
21
22+static struct arm_boot_info xlnx_ep108_binfo;
23+
24 static void xlnx_ep108_init(MachineState *machine)
25 {
26 XlnxEP108 *s = g_new0(XlnxEP108, 1);
27@@ -58,6 +60,12 @@ static void xlnx_ep108_init(MachineState *machine)
28 &error_abort);
29 vmstate_register_ram_global(&s->ddr_ram);
30 memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
31+
32+ xlnx_ep108_binfo.ram_size = machine->ram_size;
33+ xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
34+ xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
35+ xlnx_ep108_binfo.initrd_filename = machine->initrd_filename;
36+ arm_load_kernel(&s->soc.cpu[0], &xlnx_ep108_binfo);
37 }
38
39 static QEMUMachine xlnx_ep108_machine = {
40--
411.7.10.4
42
diff --git a/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch b/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch
deleted file mode 100644
index 20b9b827..00000000
--- a/recipes-devtools/qemu/qemu-zynqmp-mainline/0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch
+++ /dev/null
@@ -1,36 +0,0 @@
1From 5c6a101203322028e91586736b4f6e3c5ecc7d09 Mon Sep 17 00:00:00 2001
2From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
3Date: Mon, 23 Mar 2015 04:05:19 -0700
4Subject: [PATCH 15/15] arm: xlnx-zynqmp: Add PSCI setup
5
6Use SMC PSCI, with the standard policy of secondaries starting in
7power-off.
8
9Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
10Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
11---
12 hw/arm/xlnx-zynqmp.c | 8 ++++++++
13 1 file changed, 8 insertions(+)
14
15diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
16index e015025..0265fba 100644
17--- a/hw/arm/xlnx-zynqmp.c
18+++ b/hw/arm/xlnx-zynqmp.c
19@@ -97,6 +97,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
20 for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
21 qemu_irq irq;
22
23+ object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
24+ "psci-conduit", &error_abort);
25+ if (i > 0) {
26+ /* Secondary CPUs start in PSCI powered-down state */
27+ object_property_set_bool(OBJECT(&s->cpu[i]), true,
28+ "start-powered-off", &error_abort);
29+ }
30+
31 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
32 ERR_PROP_CHECK_RETURN(err, errp);
33
34--
351.7.10.4
36
diff --git a/recipes-devtools/qemu/qemu_zynqmp.bb b/recipes-devtools/qemu/qemu_zynqmp.bb
deleted file mode 100644
index 679fc755..00000000
--- a/recipes-devtools/qemu/qemu_zynqmp.bb
+++ /dev/null
@@ -1,42 +0,0 @@
1require recipes-devtools/qemu/qemu.inc
2
3# glx no longer valid config option
4PACKAGECONFIG[glx] = ""
5
6DEFAULT_PREFERENCE = "-1"
7
8LIC_FILES_CHKSUM = " \
9 file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \
10 file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \
11 "
12
13SRCREV = "f2a581010cb8e3a2564a45a2863a33a732cc2fc7"
14
15PV = "2.2.0+master+zynqmp+git${SRCPV}"
16
17SRC_URI_prepend = "git://git.qemu.org/qemu.git"
18S = "${WORKDIR}/git"
19
20# for base patches
21FILESEXTRAPATHS_prepend := "${COREBASE}/meta/recipes-devtools/qemu/files:"
22FILESEXTRAPATHS_prepend := "${COREBASE}/meta/recipes-devtools/qemu/qemu:"
23
24FILESEXTRAPATHS_prepend := "${THISDIR}/qemu-zynqmp-mainline:"
25SRC_URI_append += " \
26 file://0001-target-arm-cpu64-Factor-out-ARM-cortex-init.patch \
27 file://0002-target-arm-cpu64-Add-support-for-cortex-a53.patch \
28 file://0003-arm-Introduce-Xilinx-ZynqMP-SoC.patch \
29 file://0004-arm-xlnx-zynqmp-Add-GIC.patch \
30 file://0005-arm-xlnx-zynqmp-Connect-CPU-Timers-to-GIC.patch \
31 file://0006-net-cadence_gem-Clean-up-variable-names.patch \
32 file://0007-net-cadence_gem-Split-state-struct-and-type-into-hea.patch \
33 file://0008-arm-xilinx-zynqmp-Add-GEM-support.patch \
34 file://0009-char-cadence_uart-Clean-up-variable-names.patch \
35 file://0010-char-cadence_uart-Split-state-struct-and-type-into-h.patch \
36 file://0011-arm-xilinx-zynqmp-Add-UART-support.patch \
37 file://0012-arm-Add-xlnx-ep108-machine.patch \
38 file://0013-arm-xilinx-ep108-Add-external-RAM.patch \
39 file://0014-arm-xilinx-ep108-Add-bootloading.patch \
40 file://0015-arm-xlnx-zynqmp-Add-PSCI-setup.patch \
41 "
42
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-03 04:31:07 +0000