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| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-08-18 12:52:10 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-08-18 15:17:10 +0530 |
| commit | fdb9cb07d1675295fe1dcb361dc703f89544abd3 (patch) | |
| tree | 3bfea5cd802c64b76442a604512083a3b33907c7 /meta-xilinx-standalone/classes | |
| parent | 268bec019aeae450d1c488d3c4d7c1225a40b9db (diff) | |
| download | meta-xilinx-fdb9cb07d1675295fe1dcb361dc703f89544abd3.tar.gz | |
embeddedsw : Updated SRCREV for 2023.2_7635
versal_psmfw: update usage of XPsmFw_Write32 and XPsmFw_RMW32
xilpm: versal: server: Check state of DDRMC in self-refresh operations
qspipsu: src: Fix code format issues with checkpatch tool
qspipsu: examples: Add status check for XQspiPsu_SetClkPrescaler API
qspipsu: Add support for feedback clock
lib: sw_apps: openamp: sdt: Ensure parity in build process for OpenAMP apps in VitisNG
ThirdParty: sw_services: OpenAMP: sdt: Enable BSP for A72, R52 Proxy information
ThirdParty: sw_services: OpenAMP: sdt: Enable BSP build in one-shot
lib: sw_apps: libmetal demo: sdt: Add parity with Vitis Classic
ThirdParty: sw_services: Libmetal: SDT: Enable BSP support for A53, A72, A78, R52
scripts: pyesw: open-amp: Pass OS to application
bram: Fix interrupt example compilation errors in sdt flow
Xilsecure: Error out disallowed CPU modes
sw_apps: versal_psmfw: Update PSMFW release version
sdps: Add description for Adma2_DescrTbl32/64
Revert "uartns550: Add support for peripheral test for uartns550 in SDT flow"
Revert "uartpsv: Add support for peripheral test for uartpsv in SDT flow"
Revert "iicps: Add support for peripheral test for iicps in SDT flow"
Revert "iic: Add support for peripheral test for iic in SDT flow"
Revert "uartlite: Add support for peripheral test for uartlite in SDT flow"
Revert "uartps: Add support for peripheral tests in SDT flow"
Revert "gpio: Disable peripheral test for gpio in SDT flow"
Revert "sw_apps: zynq_fsbl: fixed addresses issue in SDT flow"
drivers: emacps: Fix the order of clock parameters in _g.c
mipicsiss:Updated dependencies.props Updated dependencies.props with rc21008adrv file names
scripts: pyesw: create_bsp: Fix the family variable value for microblaze platform
axidma: Fix selftest example in yaml file for SDT flow
xilpm: versal: server: Update AIE1 memory zeroization routine
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
Diffstat (limited to 'meta-xilinx-standalone/classes')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 55fad44c..70fab2fc 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" | |||
| 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
| 9 | 9 | ||
| 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
| 11 | ESW_REV[2023.2] = "f17f0ceebe99fb75eea5a04c951bad7027bd9370" | 11 | ESW_REV[2023.2] = "75c7c3382a2e2b7ae42f9d8e017ca388b1fe2358" |
| 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 13 | 13 | ||
| 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |