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| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-08-17 12:51:27 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-08-17 14:37:11 +0530 |
| commit | 517ea2b99abdd164bd6a4d18c67a97dbaded6f6e (patch) | |
| tree | a33facfefc7a834f2c16c30b9a493657273e2b81 /meta-xilinx-standalone/classes | |
| parent | 615327fe45ce4c393b16cb040ed8451c557cfc5a (diff) | |
| download | meta-xilinx-517ea2b99abdd164bd6a4d18c67a97dbaded6f6e.tar.gz | |
embeddedsw : Updated SRCREV for 2023.2_9835
versal:psmfw: Integrate PSM interrupt injection STL
axivdma: Add selftest example in yaml file
xilpm: Fix for DDR modeling implementation gaps for versal-net
xilpm: versal_net: Synchronize init node functions with Versal
xilpm: versal_common: Copy xpm_node.h and xpm_nodeid.h generated by the latest versal-topology repo
sw_apps: zynqmp_fsbl: Added protection macro for the prints at handoff
bsp: standalone: Do not assign coresight as stdout/stdin for non ARM based processors.
xilpm: versal_net: server: Remove redundant workaround
BSP:ARMv8:32bit: Fix Cortexa53 32 bit BSP compilation failure
trngpsv: Doxygen fixes
xilpdi: Doxygen fixes
xilloader: Doxygen fixes
sw_apps: zynq_fsbl: fixed addresses issue in SDT flow
uartns550: Add support for peripheral test for uartns550 in SDT flow
uartpsv: Add support for peripheral test for uartpsv in SDT flow
iicps: Add support for peripheral test for iicps in SDT flow
iic: Add support for peripheral test for iic in SDT flow
uartlite: Add support for peripheral test for uartlite in SDT flow
uartps: Add support for peripheral tests in SDT flow
gpio: Disable peripheral test for gpio in SDT flow
sw_services:xilnvm: Add redundnacy for XNvm_EfusePgmAndVerifyBit
sw_services:xilnvm:Removed XNvm_EfuseReadCacheRange
sw_services:xilnvm: Assign key clear status only when status is XST_SUCCESS
sw_services:xilnvm: Add missing else check in XNvm_EfuseReadPpkHash
sw_services:xilnvm: Clear AES keys
sw_apps: zynqmp_fsbl: Add forward declaration for config object
xilpm: Add forward declaration for config object
uartlite: Use Canonical form for base address in uartlite examples
scugic: Support PL to PS interrupts for VERSAL NET
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
Diffstat (limited to 'meta-xilinx-standalone/classes')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index ef33d2a4..55fad44c 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "xlnx_rel_v2023.2-next" | |||
| 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | 8 | BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" |
| 9 | 9 | ||
| 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" | 10 | ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" |
| 11 | ESW_REV[2023.2] = "92e375271e6ff5f4c75822a8b9a647dc1f3bdc71" | 11 | ESW_REV[2023.2] = "f17f0ceebe99fb75eea5a04c951bad7027bd9370" |
| 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 12 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 13 | 13 | ||
| 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 14 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |