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| author | Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> | 2023-01-16 13:02:57 +0530 |
|---|---|---|
| committer | Mark Hatle <mark.hatle@amd.com> | 2023-01-17 10:39:04 -0600 |
| commit | c3feb4c16ed3043f732c6d6c2d9f55f29316bc24 (patch) | |
| tree | 0589318eb72f0e61a58009fa561001c5c2e2648d /meta-xilinx-core | |
| parent | 17a13ad81fe8e3625d9ffd0f7da8a0986fc257ee (diff) | |
| download | meta-xilinx-c3feb4c16ed3043f732c6d6c2d9f55f29316bc24.tar.gz | |
fpgamanager_custom: Generate .bit.bin when .dtsi found in source directory
Validating SRC_URI for .dtsi failing when it points to git url.
Check .dtsi file exists or not in S directory and generate .bin.bin if
found.
Signed-off-by: Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-core')
| -rw-r--r-- | meta-xilinx-core/classes/fpgamanager_custom.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/classes/fpgamanager_custom.bbclass b/meta-xilinx-core/classes/fpgamanager_custom.bbclass index 8e7e86c3..466c615b 100644 --- a/meta-xilinx-core/classes/fpgamanager_custom.bbclass +++ b/meta-xilinx-core/classes/fpgamanager_custom.bbclass | |||
| @@ -97,7 +97,7 @@ python devicetree_do_compile:append() { | |||
| 97 | # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit or | 97 | # In case of dtbo as input, bbclass doesn't know if firmware-name is .bit or |
| 98 | # .bit.bin format and corresponding file name. Hence we are not doing | 98 | # .bit.bin format and corresponding file name. Hence we are not doing |
| 99 | # bit.bin conversion. | 99 | # bit.bin conversion. |
| 100 | if soc_family != 'versal' and '.dtsi' in d.getVar("SRC_URI"): | 100 | if soc_family != 'versal' and glob.glob(d.getVar('S') + '/*.dtsi'): |
| 101 | pn = d.getVar('PN') | 101 | pn = d.getVar('PN') |
| 102 | biffile = pn + '.bif' | 102 | biffile = pn + '.bif' |
| 103 | 103 | ||