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authorMark Hatle <mark.hatle@amd.com>2023-10-22 10:43:49 -0600
committerMark Hatle <mark.hatle@amd.com>2023-10-22 10:43:49 -0600
commitff2eaf78e304228cfb57fa178955fae6d929bc9e (patch)
tree1508cf56424e406f027630f2f0cb68fe8bb20721 /meta-xilinx-contrib
parentfb1c237ca640796788d55def59f6dc60ca57702a (diff)
parent05911e19d85fd98c42054238392afe95a5125265 (diff)
downloadmeta-xilinx-ff2eaf78e304228cfb57fa178955fae6d929bc9e.tar.gz
Merge remote-tracking branch 'origin/rel-v2023.2' into langdale
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-contrib')
-rw-r--r--meta-xilinx-contrib/conf/layer.conf17
-rw-r--r--meta-xilinx-contrib/dynamic-layers/meta-xilinx-tools/recipes-bsp/bitstream/bitstream-extraction_%.bbappend2
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch305
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch607
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch54
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg33
-rw-r--r--meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend12
7 files changed, 1026 insertions, 4 deletions
diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf
index eb056957..f3d6c6e4 100644
--- a/meta-xilinx-contrib/conf/layer.conf
+++ b/meta-xilinx-contrib/conf/layer.conf
@@ -2,14 +2,23 @@
2BBPATH .= ":${LAYERDIR}" 2BBPATH .= ":${LAYERDIR}"
3 3
4# We have a packages directory, add to BBFILES 4# We have a packages directory, add to BBFILES
5BBFILES += "${LAYERDIR}/recipes-*/*/*.bb" 5BBFILES += " \
6BBFILES += "${LAYERDIR}/recipes-*/*/*.bbappend" 6 ${LAYERDIR}/recipes-*/*/*.bb \
7 ${LAYERDIR}/recipes-*/*/*.bbappend \
8 "
9
10BBFILES_DYNAMIC += " \
11 xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bb \
12 xilinx-tools:${LAYERDIR}/dynamic-layers/meta-xilinx-tools/recipes-*/*/*.bbappend \
13 "
7 14
8BBFILE_COLLECTIONS += "xilinx-contrib" 15BBFILE_COLLECTIONS += "xilinx-contrib"
9BBFILE_PATTERN_xilinx-contrib = "^${LAYERDIR}/" 16BBFILE_PATTERN_xilinx-contrib = "^${LAYERDIR}/"
10BBFILE_PRIORITY_xilinx-contrib = "5" 17BBFILE_PRIORITY_xilinx-contrib = "5"
11 18
12LAYERDEPENDS_xilinx-contrib = "core" 19LAYERDEPENDS_xilinx-contrib = " \
13LAYERDEPENDS_xilinx-contrib = "xilinx" 20 core \
21 xilinx \
22 "
14 23
15LAYERSERIES_COMPAT_xilinx-contrib = "langdale" 24LAYERSERIES_COMPAT_xilinx-contrib = "langdale"
diff --git a/meta-xilinx-contrib/dynamic-layers/meta-xilinx-tools/recipes-bsp/bitstream/bitstream-extraction_%.bbappend b/meta-xilinx-contrib/dynamic-layers/meta-xilinx-tools/recipes-bsp/bitstream/bitstream-extraction_%.bbappend
new file mode 100644
index 00000000..4653c93a
--- /dev/null
+++ b/meta-xilinx-contrib/dynamic-layers/meta-xilinx-tools/recipes-bsp/bitstream/bitstream-extraction_%.bbappend
@@ -0,0 +1,2 @@
1COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = "^$"
2
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
new file mode 100644
index 00000000..660bc218
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
@@ -0,0 +1,305 @@
1From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:14:13 +1000
4Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
5
6Add the dglnt_encoder driver that enables DRM support for the VGA and
7HDMI output ports found on many Digilent boards.
8
9Upstream-Status: Pending
10
11Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
12Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
13---
14 .../bindings/drm/xilinx/dglnt_encoder.txt | 23 +++
15 drivers/gpu/drm/xilinx/Kconfig | 6 +
16 drivers/gpu/drm/xilinx/Makefile | 1 +
17 drivers/gpu/drm/xilinx/dglnt_encoder.c | 217 +++++++++++++++++++++
18 4 files changed, 247 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
20 create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
21
22diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
23new file mode 100644
24index 0000000..242b24e
25--- /dev/null
26+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
27@@ -0,0 +1,23 @@
28+Device-Tree bindings for Digilent DRM Encoder Slave
29+
30+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
31+The VGA or HDMI port must be connected to a Xilinx display pipeline via an
32+axi2vid IP core.
33+
34+Required properties:
35+ - compatible: Should be "digilent,drm-encoder".
36+
37+Optional properties:
38+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
39+ connector. This is used to obtain the supported resolutions
40+ of an attached monitor. If not defined, then a default
41+ set of resolutions is used and the display will initialize
42+ to 720p. Note most VGA connectors on Digilent boards do
43+ not have the DDC bus routed out.
44+
45+Example:
46+
47+ encoder_0: digilent_encoder {
48+ compatible = "digilent,drm-encoder";
49+ dglnt,edid-i2c = <&i2c1>;
50+ };
51diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
52index 57e18a9..d9ecff2 100644
53--- a/drivers/gpu/drm/xilinx/Kconfig
54+++ b/drivers/gpu/drm/xilinx/Kconfig
55@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB
56 help
57 DRM driver for Xilinx Display Port Subsystem.
58
59+config DRM_DIGILENT_ENCODER
60+ tristate "Digilent VGA/HDMI DRM Encoder Driver"
61+ depends on DRM_XILINX
62+ help
63+ DRM slave encoder for Video-out on Digilent boards.
64+
65 config DRM_XILINX_DP_SUB_DEBUG_FS
66 bool "Xilinx DRM DPSUB debugfs"
67 depends on DEBUG_FS && DRM_XILINX_DP_SUB
68diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
69index 19bc154..c2717e40 100644
70--- a/drivers/gpu/drm/xilinx/Makefile
71+++ b/drivers/gpu/drm/xilinx/Makefile
72@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \
73 xilinx_drm_plane.o
74 xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
75
76+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
77 obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
78 obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
79 obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
80diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
81new file mode 100644
82index 0000000..cb9fc7d
83--- /dev/null
84+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
85@@ -0,0 +1,217 @@
86+/*
87+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
88+ *
89+ * Copyright (C) 2015 Digilent
90+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
91+ *
92+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
93+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
94+ *
95+ * This software is licensed under the terms of the GNU General Public
96+ * License version 2, as published by the Free Software Foundation, and
97+ * may be copied, distributed, and modified under those terms.
98+ *
99+ * This program is distributed in the hope that it will be useful,
100+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
101+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
102+ * GNU General Public License for more details.
103+ */
104+
105+#include <drm/drmP.h>
106+#include <drm/drm_edid.h>
107+#include <drm/drm_encoder_slave.h>
108+
109+#include <linux/device.h>
110+#include <linux/module.h>
111+#include <linux/err.h>
112+#include <linux/i2c.h>
113+#include <linux/of.h>
114+#include <linux/of_platform.h>
115+#include <linux/platform_device.h>
116+
117+#define DGLNT_ENC_MAX_FREQ 150000
118+#define DGLNT_ENC_MAX_H 1920
119+#define DGLNT_ENC_MAX_V 1080
120+#define DGLNT_ENC_PREF_H 1280
121+#define DGLNT_ENC_PREF_V 720
122+
123+struct dglnt_encoder {
124+ struct drm_encoder *encoder;
125+ struct i2c_adapter *i2c_bus;
126+ bool i2c_present;
127+};
128+
129+static inline struct dglnt_encoder *to_dglnt_encoder(
130+ struct drm_encoder *encoder)
131+{
132+ return to_encoder_slave(encoder)->slave_priv;
133+}
134+
135+static bool dglnt_mode_fixup(struct drm_encoder *encoder,
136+ const struct drm_display_mode *mode,
137+ struct drm_display_mode *adjusted_mode)
138+{
139+ return true;
140+}
141+
142+static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
143+ struct drm_display_mode *mode,
144+ struct drm_display_mode *adjusted_mode)
145+{
146+}
147+
148+static void
149+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
150+{
151+}
152+
153+static void dglnt_encoder_save(struct drm_encoder *encoder)
154+{
155+}
156+
157+static void dglnt_encoder_restore(struct drm_encoder *encoder)
158+{
159+}
160+
161+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
162+ struct drm_display_mode *mode)
163+{
164+ if (mode &&
165+ !(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
166+ DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
167+ (mode->clock <= DGLNT_ENC_MAX_FREQ) &&
168+ (mode->hdisplay <= DGLNT_ENC_MAX_H) &&
169+ (mode->vdisplay <= DGLNT_ENC_MAX_V))
170+ return MODE_OK;
171+ return MODE_BAD;
172+}
173+
174+static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
175+ struct drm_connector *connector)
176+{
177+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
178+ struct edid *edid;
179+ int num_modes = 0;
180+
181+ if (dglnt->i2c_present) {
182+ edid = drm_get_edid(connector, dglnt->i2c_bus);
183+ drm_connector_update_edid_property(connector, edid);
184+ if (edid) {
185+ num_modes = drm_add_edid_modes(connector, edid);
186+ kfree(edid);
187+ }
188+ } else {
189+ num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
190+ DGLNT_ENC_MAX_V);
191+ drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
192+ DGLNT_ENC_PREF_V);
193+ }
194+ return num_modes;
195+}
196+
197+static enum drm_connector_status dglnt_encoder_detect(
198+ struct drm_encoder *encoder,
199+ struct drm_connector *connector)
200+{
201+ struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
202+
203+ if (dglnt->i2c_present) {
204+ if (drm_probe_ddc(dglnt->i2c_bus))
205+ return connector_status_connected;
206+ return connector_status_disconnected;
207+ } else
208+ return connector_status_unknown;
209+}
210+
211+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
212+ .dpms = dglnt_encoder_dpms,
213+ .save = dglnt_encoder_save,
214+ .restore = dglnt_encoder_restore,
215+ .mode_fixup = dglnt_mode_fixup,
216+ .mode_valid = dglnt_encoder_mode_valid,
217+ .mode_set = dglnt_encoder_mode_set,
218+ .detect = dglnt_encoder_detect,
219+ .get_modes = dglnt_encoder_get_modes,
220+};
221+
222+static int dglnt_encoder_encoder_init(struct platform_device *pdev,
223+ struct drm_device *dev,
224+ struct drm_encoder_slave *encoder)
225+{
226+ struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
227+ struct device_node *sub_node;
228+
229+ encoder->slave_priv = dglnt;
230+ encoder->slave_funcs = &dglnt_encoder_slave_funcs;
231+
232+ dglnt->encoder = &encoder->base;
233+
234+ /* get i2c adapter for edid */
235+ dglnt->i2c_present = false;
236+ sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
237+ if (sub_node) {
238+ dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
239+ if (!dglnt->i2c_bus)
240+ DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
241+ else
242+ dglnt->i2c_present = true;
243+ of_node_put(sub_node);
244+ }
245+
246+ return 0;
247+}
248+
249+static int dglnt_encoder_probe(struct platform_device *pdev)
250+{
251+ struct dglnt_encoder *dglnt;
252+
253+ dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
254+ if (!dglnt)
255+ return -ENOMEM;
256+
257+ platform_set_drvdata(pdev, dglnt);
258+
259+ return 0;
260+}
261+
262+static int dglnt_encoder_remove(struct platform_device *pdev)
263+{
264+ return 0;
265+}
266+
267+static const struct of_device_id dglnt_encoder_of_match[] = {
268+ { .compatible = "digilent,drm-encoder", },
269+ { /* end of table */ },
270+};
271+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
272+
273+static struct drm_platform_encoder_driver dglnt_encoder_driver = {
274+ .platform_driver = {
275+ .probe = dglnt_encoder_probe,
276+ .remove = dglnt_encoder_remove,
277+ .driver = {
278+ .owner = THIS_MODULE,
279+ .name = "dglnt-drm-enc",
280+ .of_match_table = dglnt_encoder_of_match,
281+ },
282+ },
283+
284+ .encoder_init = dglnt_encoder_encoder_init,
285+};
286+
287+static int __init dglnt_encoder_init(void)
288+{
289+ return platform_driver_register(&dglnt_encoder_driver.platform_driver);
290+}
291+
292+static void __exit dglnt_encoder_exit(void)
293+{
294+ platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
295+}
296+
297+module_init(dglnt_encoder_init);
298+module_exit(dglnt_encoder_exit);
299+
300+MODULE_AUTHOR("Digilent, Inc.");
301+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
302+MODULE_LICENSE("GPL v2");
303--
3042.7.4
305
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
new file mode 100644
index 00000000..9b6229db
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
@@ -0,0 +1,607 @@
1From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001
2From: Jason Wu <jason.wu.misc@gmail.com>
3Date: Sun, 10 Apr 2016 13:16:06 +1000
4Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
5
6Add support for the axi_dynclk IP Core available from Digilent. This IP
7core dynamically configures the clock resources inside a Xilinx FPGA to
8generate a clock with a software programmable frequency.
9
10Upstream-Status: Pending
11
12Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
13Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
14---
15 drivers/clk/Kconfig | 8 +
16 drivers/clk/Makefile | 1 +
17 drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 556 insertions(+)
19 create mode 100644 drivers/clk/clk-dglnt-dynclk.c
20
21diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
22index dccb111100..7fe65a702b 100644
23--- a/drivers/clk/Kconfig
24+++ b/drivers/clk/Kconfig
25@@ -148,6 +148,14 @@ config CLK_QORIQ
26 This adds the clock driver support for Freescale QorIQ platforms
27 using common clock framework.
28
29+config COMMON_CLK_DGLNT_DYNCLK
30+ tristate "Digilent axi_dynclk Driver"
31+ depends on ARCH_ZYNQ || MICROBLAZE
32+ help
33+ ---help---
34+ Support for the Digilent AXI Dynamic Clock core for Xilinx
35+ FPGAs.
36+
37 config COMMON_CLK_XGENE
38 bool "Clock driver for APM XGene SoC"
39 default y
40diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
41index 0760449dde..45ce97d053 100644
42--- a/drivers/clk/Makefile
43+++ b/drivers/clk/Makefile
44@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o
45 obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
46 obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
47 obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
48+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK) += clk-dglnt-dynclk.o
49 obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
50 obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
51 obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
52diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
53new file mode 100644
54index 0000000000..496ad5fc90
55--- /dev/null
56+++ b/drivers/clk/clk-dglnt-dynclk.c
57@@ -0,0 +1,547 @@
58+/*
59+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
60+ *
61+ * Copyright (C) 2015 Digilent
62+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
63+ *
64+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
65+ *
66+ * This software is licensed under the terms of the GNU General Public
67+ * License version 2, as published by the Free Software Foundation, and
68+ * may be copied, distributed, and modified under those terms.
69+ *
70+ * This program is distributed in the hope that it will be useful,
71+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
72+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
73+ * GNU General Public License for more details.
74+ */
75+
76+#include <linux/platform_device.h>
77+#include <linux/clk-provider.h>
78+#include <linux/clk.h>
79+#include <linux/slab.h>
80+#include <linux/io.h>
81+#include <linux/of.h>
82+#include <linux/module.h>
83+#include <linux/err.h>
84+#include <linux/kernel.h>
85+
86+#define CLK_BIT_WEDGE 13
87+#define CLK_BIT_NOCOUNT 12
88+
89+/* This value is used to signal an error */
90+#define ERR_CLKCOUNTCALC 0xFFFFFFFF
91+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
92+
93+#define DYNCLK_DIV_1_REGMASK 0x1041
94+/* 25 MHz (125 KHz / 5) */
95+#define DYNCLK_DEFAULT_FREQ 125000
96+
97+#define MMCM_FREQ_VCOMIN 600000
98+#define MMCM_FREQ_VCOMAX 1200000
99+#define MMCM_FREQ_PFDMIN 10000
100+#define MMCM_FREQ_PFDMAX 450000
101+#define MMCM_FREQ_OUTMIN 4000
102+#define MMCM_FREQ_OUTMAX 800000
103+#define MMCM_DIV_MAX 106
104+#define MMCM_FB_MIN 2
105+#define MMCM_FB_MAX 64
106+#define MMCM_CLKDIV_MAX 128
107+#define MMCM_CLKDIV_MIN 1
108+
109+#define OFST_DISPLAY_CTRL 0x0
110+#define OFST_DISPLAY_STATUS 0x4
111+#define OFST_DISPLAY_CLK_L 0x8
112+#define OFST_DISPLAY_FB_L 0x0C
113+#define OFST_DISPLAY_FB_H_CLK_H 0x10
114+#define OFST_DISPLAY_DIV 0x14
115+#define OFST_DISPLAY_LOCK_L 0x18
116+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
117+
118+static const u64 lock_lookup[64] = {
119+ 0b0011000110111110100011111010010000000001,
120+ 0b0011000110111110100011111010010000000001,
121+ 0b0100001000111110100011111010010000000001,
122+ 0b0101101011111110100011111010010000000001,
123+ 0b0111001110111110100011111010010000000001,
124+ 0b1000110001111110100011111010010000000001,
125+ 0b1001110011111110100011111010010000000001,
126+ 0b1011010110111110100011111010010000000001,
127+ 0b1100111001111110100011111010010000000001,
128+ 0b1110011100111110100011111010010000000001,
129+ 0b1111111111111000010011111010010000000001,
130+ 0b1111111111110011100111111010010000000001,
131+ 0b1111111111101110111011111010010000000001,
132+ 0b1111111111101011110011111010010000000001,
133+ 0b1111111111101000101011111010010000000001,
134+ 0b1111111111100111000111111010010000000001,
135+ 0b1111111111100011111111111010010000000001,
136+ 0b1111111111100010011011111010010000000001,
137+ 0b1111111111100000110111111010010000000001,
138+ 0b1111111111011111010011111010010000000001,
139+ 0b1111111111011101101111111010010000000001,
140+ 0b1111111111011100001011111010010000000001,
141+ 0b1111111111011010100111111010010000000001,
142+ 0b1111111111011001000011111010010000000001,
143+ 0b1111111111011001000011111010010000000001,
144+ 0b1111111111010111011111111010010000000001,
145+ 0b1111111111010101111011111010010000000001,
146+ 0b1111111111010101111011111010010000000001,
147+ 0b1111111111010100010111111010010000000001,
148+ 0b1111111111010100010111111010010000000001,
149+ 0b1111111111010010110011111010010000000001,
150+ 0b1111111111010010110011111010010000000001,
151+ 0b1111111111010010110011111010010000000001,
152+ 0b1111111111010001001111111010010000000001,
153+ 0b1111111111010001001111111010010000000001,
154+ 0b1111111111010001001111111010010000000001,
155+ 0b1111111111001111101011111010010000000001,
156+ 0b1111111111001111101011111010010000000001,
157+ 0b1111111111001111101011111010010000000001,
158+ 0b1111111111001111101011111010010000000001,
159+ 0b1111111111001111101011111010010000000001,
160+ 0b1111111111001111101011111010010000000001,
161+ 0b1111111111001111101011111010010000000001,
162+ 0b1111111111001111101011111010010000000001,
163+ 0b1111111111001111101011111010010000000001,
164+ 0b1111111111001111101011111010010000000001,
165+ 0b1111111111001111101011111010010000000001,
166+ 0b1111111111001111101011111010010000000001,
167+ 0b1111111111001111101011111010010000000001,
168+ 0b1111111111001111101011111010010000000001,
169+ 0b1111111111001111101011111010010000000001,
170+ 0b1111111111001111101011111010010000000001,
171+ 0b1111111111001111101011111010010000000001,
172+ 0b1111111111001111101011111010010000000001,
173+ 0b1111111111001111101011111010010000000001,
174+ 0b1111111111001111101011111010010000000001,
175+ 0b1111111111001111101011111010010000000001,
176+ 0b1111111111001111101011111010010000000001,
177+ 0b1111111111001111101011111010010000000001,
178+ 0b1111111111001111101011111010010000000001,
179+ 0b1111111111001111101011111010010000000001,
180+ 0b1111111111001111101011111010010000000001,
181+ 0b1111111111001111101011111010010000000001,
182+ 0b1111111111001111101011111010010000000001
183+};
184+
185+static const u32 filter_lookup_low[64] = {
186+ 0b0001011111,
187+ 0b0001010111,
188+ 0b0001111011,
189+ 0b0001011011,
190+ 0b0001101011,
191+ 0b0001110011,
192+ 0b0001110011,
193+ 0b0001110011,
194+ 0b0001110011,
195+ 0b0001001011,
196+ 0b0001001011,
197+ 0b0001001011,
198+ 0b0010110011,
199+ 0b0001010011,
200+ 0b0001010011,
201+ 0b0001010011,
202+ 0b0001010011,
203+ 0b0001010011,
204+ 0b0001010011,
205+ 0b0001010011,
206+ 0b0001010011,
207+ 0b0001010011,
208+ 0b0001010011,
209+ 0b0001100011,
210+ 0b0001100011,
211+ 0b0001100011,
212+ 0b0001100011,
213+ 0b0001100011,
214+ 0b0001100011,
215+ 0b0001100011,
216+ 0b0001100011,
217+ 0b0001100011,
218+ 0b0001100011,
219+ 0b0001100011,
220+ 0b0001100011,
221+ 0b0001100011,
222+ 0b0001100011,
223+ 0b0010010011,
224+ 0b0010010011,
225+ 0b0010010011,
226+ 0b0010010011,
227+ 0b0010010011,
228+ 0b0010010011,
229+ 0b0010010011,
230+ 0b0010010011,
231+ 0b0010010011,
232+ 0b0010010011,
233+ 0b0010100011,
234+ 0b0010100011,
235+ 0b0010100011,
236+ 0b0010100011,
237+ 0b0010100011,
238+ 0b0010100011,
239+ 0b0010100011,
240+ 0b0010100011,
241+ 0b0010100011,
242+ 0b0010100011,
243+ 0b0010100011,
244+ 0b0010100011,
245+ 0b0010100011,
246+ 0b0010100011,
247+ 0b0010100011,
248+ 0b0010100011,
249+ 0b0010100011
250+};
251+
252+struct dglnt_dynclk_reg;
253+struct dglnt_dynclk_mode;
254+struct dglnt_dynclk;
255+
256+struct dglnt_dynclk_reg {
257+ u32 clk0L;
258+ u32 clkFBL;
259+ u32 clkFBH_clk0H;
260+ u32 divclk;
261+ u32 lockL;
262+ u32 fltr_lockH;
263+};
264+
265+struct dglnt_dynclk_mode {
266+ u32 freq;
267+ u32 fbmult;
268+ u32 clkdiv;
269+ u32 maindiv;
270+};
271+
272+struct dglnt_dynclk {
273+ void __iomem *base;
274+ struct clk_hw clk_hw;
275+ unsigned long freq;
276+};
277+
278+u32 dglnt_dynclk_divider(u32 divide)
279+{
280+ u32 output = 0;
281+ u32 highTime = 0;
282+ u32 lowTime = 0;
283+
284+ if ((divide < 1) || (divide > 128))
285+ return ERR_CLKDIVIDER;
286+
287+ if (divide == 1)
288+ return DYNCLK_DIV_1_REGMASK;
289+
290+ highTime = divide / 2;
291+ /* if divide is odd */
292+ if (divide & 0x1) {
293+ lowTime = highTime + 1;
294+ output = 1 << CLK_BIT_WEDGE;
295+ } else {
296+ lowTime = highTime;
297+ }
298+
299+ output |= 0x03F & lowTime;
300+ output |= 0xFC0 & (highTime << 6);
301+ return output;
302+}
303+
304+u32 dglnt_dynclk_count_calc(u32 divide)
305+{
306+ u32 output = 0;
307+ u32 divCalc = 0;
308+
309+ divCalc = dglnt_dynclk_divider(divide);
310+ if (divCalc == ERR_CLKDIVIDER)
311+ output = ERR_CLKCOUNTCALC;
312+ else
313+ output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
314+ return output;
315+}
316+
317+
318+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
319+ struct dglnt_dynclk_mode *clkParams)
320+{
321+ if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
322+ return -EINVAL;
323+
324+ regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
325+ if (regValues->clk0L == ERR_CLKCOUNTCALC)
326+ return -EINVAL;
327+
328+ regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
329+ if (regValues->clkFBL == ERR_CLKCOUNTCALC)
330+ return -EINVAL;
331+
332+ regValues->clkFBH_clk0H = 0;
333+
334+ regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
335+ if (regValues->divclk == ERR_CLKDIVIDER)
336+ return -EINVAL;
337+
338+ regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
339+ 0xFFFFFFFF);
340+
341+ regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
342+ 32) & 0x000000FF);
343+ regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
344+ 16) & 0x03FF0000);
345+
346+ return 0;
347+}
348+
349+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
350+ void __iomem *baseaddr)
351+{
352+ writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
353+ writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
354+ writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
355+ writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
356+ writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
357+ writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
358+}
359+
360+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
361+ struct dglnt_dynclk_mode *bestPick)
362+{
363+ u32 bestError = MMCM_FREQ_OUTMAX;
364+ u32 curError;
365+ u32 curClkMult;
366+ u32 curFreq;
367+ u32 divVal;
368+ u32 curFb, curClkDiv;
369+ u32 minFb = 0;
370+ u32 maxFb = 0;
371+ u32 curDiv = 1;
372+ u32 maxDiv;
373+ bool freq_found = false;
374+
375+ bestPick->freq = 0;
376+ if (parentFreq == 0)
377+ return 0;
378+
379+ /* minimum frequency is actually dictated by VCOmin */
380+ if (freq < MMCM_FREQ_OUTMIN)
381+ freq = MMCM_FREQ_OUTMIN;
382+ if (freq > MMCM_FREQ_OUTMAX)
383+ freq = MMCM_FREQ_OUTMAX;
384+
385+ if (parentFreq > MMCM_FREQ_PFDMAX)
386+ curDiv = 2;
387+ maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
388+ if (maxDiv > MMCM_DIV_MAX)
389+ maxDiv = MMCM_DIV_MAX;
390+
391+ while (curDiv <= maxDiv && !freq_found) {
392+ minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
393+ maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
394+ if (maxFb > MMCM_FB_MAX)
395+ maxFb = MMCM_FB_MAX;
396+ if (minFb < MMCM_FB_MIN)
397+ minFb = MMCM_FB_MIN;
398+
399+ divVal = curDiv * freq;
400+ /*
401+ * This multiplier is used to find the best clkDiv value for
402+ * each FB value
403+ */
404+ curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
405+
406+ curFb = minFb;
407+ while (curFb <= maxFb && !freq_found) {
408+ curClkDiv = ((curClkMult * curFb) + 500) / 1000;
409+ if (curClkDiv > MMCM_CLKDIV_MAX)
410+ curClkDiv = MMCM_CLKDIV_MAX;
411+ if (curClkDiv < MMCM_CLKDIV_MIN)
412+ curClkDiv = MMCM_CLKDIV_MIN;
413+ curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
414+ if (curFreq >= freq)
415+ curError = curFreq - freq;
416+ else
417+ curError = freq - curFreq;
418+ if (curError < bestError) {
419+ bestError = curError;
420+ bestPick->clkdiv = curClkDiv;
421+ bestPick->fbmult = curFb;
422+ bestPick->maindiv = curDiv;
423+ bestPick->freq = curFreq;
424+ }
425+ if (!curError)
426+ freq_found = true;
427+ curFb++;
428+ }
429+ curDiv++;
430+ }
431+ return bestPick->freq;
432+}
433+
434+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
435+{
436+ return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
437+}
438+
439+
440+static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
441+{
442+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
443+ unsigned int clock_state;
444+
445+ if (dglnt_dynclk->freq) {
446+ writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
447+ do {
448+ clock_state = readl(dglnt_dynclk->base +
449+ OFST_DISPLAY_STATUS);
450+ } while (!clock_state);
451+ }
452+ return 0;
453+}
454+
455+static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
456+{
457+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
458+
459+ writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
460+}
461+
462+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
463+ unsigned long rate, unsigned long parent_rate)
464+{
465+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
466+ struct dglnt_dynclk_reg clkReg;
467+ struct dglnt_dynclk_mode clkMode;
468+
469+ if (parent_rate == 0 || rate == 0)
470+ return -EINVAL;
471+ if (rate == dglnt_dynclk->freq)
472+ return 0;
473+
474+ /*
475+ * Convert from Hz to KHz, then multiply by five to account for
476+ * BUFR division
477+ */
478+ rate = (rate + 100) / 200;
479+ /* convert from Hz to KHz */
480+ parent_rate = (parent_rate + 500) / 1000;
481+ if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
482+ return -EINVAL;
483+
484+ /*
485+ * Write to the PLL dynamic configuration registers to configure it
486+ * with the calculated parameters.
487+ */
488+ dglnt_dynclk_find_reg(&clkReg, &clkMode);
489+ dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
490+ dglnt_dynclk->freq = clkMode.freq * 200;
491+ dglnt_dynclk_disable(clk_hw);
492+ dglnt_dynclk_enable(clk_hw);
493+
494+ return 0;
495+}
496+
497+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
498+ unsigned long *parent_rate)
499+{
500+ struct dglnt_dynclk_mode clkMode;
501+
502+ dglnt_dynclk_find_mode(((rate + 100) / 200),
503+ ((*parent_rate) + 500) / 1000, &clkMode);
504+
505+ return (clkMode.freq * 200);
506+}
507+
508+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
509+ unsigned long parent_rate)
510+{
511+ struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
512+
513+ return dglnt_dynclk->freq;
514+}
515+
516+
517+static const struct clk_ops dglnt_dynclk_ops = {
518+ .recalc_rate = dglnt_dynclk_recalc_rate,
519+ .round_rate = dglnt_dynclk_round_rate,
520+ .set_rate = dglnt_dynclk_set_rate,
521+ .enable = dglnt_dynclk_enable,
522+ .disable = dglnt_dynclk_disable,
523+};
524+
525+static const struct of_device_id dglnt_dynclk_ids[] = {
526+ { .compatible = "digilent,axi-dynclk", },
527+ { },
528+};
529+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
530+
531+static int dglnt_dynclk_probe(struct platform_device *pdev)
532+{
533+ const struct of_device_id *id;
534+ struct dglnt_dynclk *dglnt_dynclk;
535+ struct clk_init_data init;
536+ const char *parent_name;
537+ const char *clk_name;
538+ struct resource *mem;
539+ struct clk *clk;
540+
541+ if (!pdev->dev.of_node)
542+ return -ENODEV;
543+
544+ id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
545+ if (!id)
546+ return -ENODEV;
547+
548+ dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
549+ GFP_KERNEL);
550+ if (!dglnt_dynclk)
551+ return -ENOMEM;
552+
553+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
554+ dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
555+ if (IS_ERR(dglnt_dynclk->base))
556+ return PTR_ERR(dglnt_dynclk->base);
557+
558+ parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
559+ if (!parent_name)
560+ return -EINVAL;
561+
562+ clk_name = pdev->dev.of_node->name;
563+ of_property_read_string(pdev->dev.of_node, "clock-output-names",
564+ &clk_name);
565+
566+ init.name = clk_name;
567+ init.ops = &dglnt_dynclk_ops;
568+ init.flags = 0;
569+ init.parent_names = &parent_name;
570+ init.num_parents = 1;
571+
572+ dglnt_dynclk->freq = 0;
573+ dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
574+
575+ dglnt_dynclk->clk_hw.init = &init;
576+ clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
577+ if (IS_ERR(clk))
578+ return PTR_ERR(clk);
579+
580+ return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
581+ clk);
582+}
583+
584+static int dglnt_dynclk_remove(struct platform_device *pdev)
585+{
586+ of_clk_del_provider(pdev->dev.of_node);
587+
588+ return 0;
589+}
590+
591+static struct platform_driver dglnt_dynclk_driver = {
592+ .driver = {
593+ .name = "dglnt-dynclk",
594+ .owner = THIS_MODULE,
595+ .of_match_table = dglnt_dynclk_ids,
596+ },
597+ .probe = dglnt_dynclk_probe,
598+ .remove = dglnt_dynclk_remove,
599+};
600+module_platform_driver(dglnt_dynclk_driver);
601+
602+MODULE_LICENSE("GPL v2");
603+MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
604+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
605--
6062.14.2
607
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
new file mode 100644
index 00000000..a98d84c5
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
@@ -0,0 +1,54 @@
1From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 2 May 2016 23:46:42 +1000
4Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
5
6Fix the issues where the VTC is reset (losing its timing config).
7
8Also fix the issue where the plane destroys its DMA descriptors and
9marks the DMA channels as inactive but never recreates the descriptors
10and never updates the active state when turning DPMS back on.
11
12Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
13Upstream-Status: Pending [This is a workaround]
14---
15 drivers/gpu/drm/xilinx/xilinx_drm_crtc.c | 1 -
16 drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
17 2 files changed, 2 insertions(+), 2 deletions(-)
18
19diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
20index 631d35b921..93dbd4b58a 100644
21--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
22+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
23@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
24 default:
25 if (crtc->vtc) {
26 xilinx_vtc_disable(crtc->vtc);
27- xilinx_vtc_reset(crtc->vtc);
28 }
29 if (crtc->cresample) {
30 xilinx_cresample_disable(crtc->cresample);
31diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
32index 6a248b72d4..d2518a4bdf 100644
33--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
34+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
35@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
36 for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
37 struct xilinx_drm_plane_dma *dma = &plane->dma[i];
38
39- if (dma->chan && dma->is_active) {
40+ if (dma->chan) {
41 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
42 desc = dmaengine_prep_interleaved_dma(dma->chan,
43 &dma->xt,
44@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
45 dmaengine_submit(desc);
46
47 dma_async_issue_pending(dma->chan);
48+ dma->is_active = true;
49 }
50 }
51 }
52--
532.14.2
54
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg
new file mode 100644
index 00000000..f71e53ab
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2023.2/0004-minized-wifi-bluetooth.cfg
@@ -0,0 +1,33 @@
1#
2# Bluetooth config
3#
4CONFIG_BT=y
5CONFIG_BT_BREDR=y
6CONFIG_BT_HS=y
7CONFIG_BT_LE=y
8CONFIG_BT_BCM=y
9CONFIG_BT_HCIUART=y
10CONFIG_BT_HCIUART_H4=y
11CONFIG_BT_HCIUART_BCM=y
12CONFIG_BT_HIDP=y
13CONFIG_CFG80211=y
14CONFIG_CFG80211_DEFAULT_PS=y
15CONFIG_CFG80211_CRDA_SUPPORT=y
16CONFIG_BRCMUTIL=y
17CONFIG_BRCMFMAC=y
18CONFIG_BRCMFMAC_PROTO_BCDC=y
19CONFIG_BRCMFMAC_SDIO=y
20CONFIG_CRYPTO_BLKCIPHER=y
21CONFIG_CRYPTO_MANAGER=y
22CONFIG_CRYPTO_ECB=y
23CONFIG_CRYPTO_CMAC=y
24CONFIG_CRYPTO_SHA256=y
25
26#
27# Regulator config
28#
29CONFIG_REGMAP_IRQ=y
30CONFIG_I2C_XILINX=y
31CONFIG_MFD_DA9062=y
32CONFIG_REGULATOR_DA9062=y
33
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend
new file mode 100644
index 00000000..c789c7a9
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2023.2.bbappend
@@ -0,0 +1,12 @@
1FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx/v${@bb.parse.vars_from_file(d.getVar('FILE', False),d)[1] or ''}:"
2
3# Note: These patches are very old and doesn't apply on top of 5.x
4# kernel. For more details refer README.md file.
5
6#SRC_URI:append:zybo-linux-bd-zynq7 = " \
7# file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
8# file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
9# file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
10# "
11
12SRC_URI:append:minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg"
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-06-30 07:43:25 +0000