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authorManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2017-12-21 14:51:41 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-01-31 13:33:02 -0800
commitc45906f006e8168d00d864526fb04941d0e34126 (patch)
tree866bec4d7151b4a30be2c11c69906e7c6a61fe40 /meta-xilinx-bsp
parent2c6ad569ab39c611c01dabe42c2791a23507539d (diff)
downloadmeta-xilinx-c45906f006e8168d00d864526fb04941d0e34126.tar.gz
u-boot-xlnx_2017.3.bb: Add support to build kc705-microblazeel
Add the wiring in u-boot-xlnx to compile kc705-microblazeel machine. Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp')
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch1181
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb2
2 files changed, 1183 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch
new file mode 100644
index 00000000..99e2a648
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2017.3/microblaze-kc705-Convert-microblaze-generic-to-k.patch
@@ -0,0 +1,1181 @@
1From cb4350d00089c0e133ef18d2b662e18ab82a14c6 Mon Sep 17 00:00:00 2001
2From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
3Date: Tue, 8 Aug 2017 10:34:28 -0700
4Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to kc705-microblazeel
5
6This is an update to earlier kc705-trd patch done by Nathan Rossi. Starting
7from v2016.1, KC705 will no longer refer to deprecated KC705 TRD application.
8
9Change the microblaze-generic board to match the kc705-microblazeel. This patch
10is not intended for upstream and serves as an intermediate solution
11until OF support in upstream u-boot allows for easy support for custom
12microblaze boards.
13
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
16---
17 arch/microblaze/dts/microblaze-generic.dts | 570 ++++++++++++++++++++++++++++-
18 board/xilinx/microblaze-generic/config.mk | 30 +-
19 configs/microblaze-generic_defconfig | 27 +-
20 include/configs/microblaze-generic.h | 470 +++++++++---------------
21 4 files changed, 754 insertions(+), 343 deletions(-)
22
23diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
24index 08a1396..879bacd 100644
25--- a/arch/microblaze/dts/microblaze-generic.dts
26+++ b/arch/microblaze/dts/microblaze-generic.dts
27@@ -1,9 +1,567 @@
28 /dts-v1/;
29+
30 / {
31- #address-cells = <1>;
32- #size-cells = <1>;
33- aliases {
34- } ;
35+ #address-cells = <0x1>;
36+ #size-cells = <0x1>;
37+ compatible = "xlnx,microblaze";
38+ model = "Xilinx MicroBlaze";
39+ hard-reset-gpios = <0x1 0x0 0x1>;
40+
41+ cpus {
42+ #address-cells = <0x1>;
43+ #cpus = <0x1>;
44+ #size-cells = <0x0>;
45+
46+ cpu@0 {
47+ bus-handle = <0x2>;
48+ clock-frequency = <0xbebc200>;
49+ clocks = <0x3>;
50+ compatible = "xlnx,microblaze-10.0";
51+ d-cache-baseaddr = <0x80000000>;
52+ d-cache-highaddr = <0xbfffffff>;
53+ d-cache-line-size = <0x20>;
54+ d-cache-size = <0x4000>;
55+ device_type = "cpu";
56+ i-cache-baseaddr = <0x80000000>;
57+ i-cache-highaddr = <0xbfffffff>;
58+ i-cache-line-size = <0x10>;
59+ i-cache-size = <0x4000>;
60+ interrupt-handle = <0x4>;
61+ model = "microblaze,10.0";
62+ timebase-frequency = <0xbebc200>;
63+ xlnx,addr-size = <0x20>;
64+ xlnx,addr-tag-bits = <0x10>;
65+ xlnx,allow-dcache-wr = <0x1>;
66+ xlnx,allow-icache-wr = <0x1>;
67+ xlnx,area-optimized = <0x0>;
68+ xlnx,async-interrupt = <0x1>;
69+ xlnx,async-wakeup = <0x3>;
70+ xlnx,avoid-primitives = <0x0>;
71+ xlnx,base-vectors = <0x0>;
72+ xlnx,branch-target-cache-size = <0x0>;
73+ xlnx,cache-byte-size = <0x4000>;
74+ xlnx,d-axi = <0x1>;
75+ xlnx,d-lmb = <0x1>;
76+ xlnx,d-lmb-mon = <0x0>;
77+ xlnx,daddr-size = <0x20>;
78+ xlnx,data-size = <0x20>;
79+ xlnx,dc-axi-mon = <0x0>;
80+ xlnx,dcache-addr-tag = <0x10>;
81+ xlnx,dcache-always-used = <0x1>;
82+ xlnx,dcache-byte-size = <0x4000>;
83+ xlnx,dcache-data-width = <0x0>;
84+ xlnx,dcache-force-tag-lutram = <0x0>;
85+ xlnx,dcache-line-len = <0x8>;
86+ xlnx,dcache-use-writeback = <0x0>;
87+ xlnx,dcache-victims = <0x0>;
88+ xlnx,debug-counter-width = <0x20>;
89+ xlnx,debug-enabled = <0x1>;
90+ xlnx,debug-event-counters = <0x5>;
91+ xlnx,debug-external-trace = <0x0>;
92+ xlnx,debug-interface = <0x0>;
93+ xlnx,debug-latency-counters = <0x1>;
94+ xlnx,debug-profile-size = <0x0>;
95+ xlnx,debug-trace-async-reset = <0x0>;
96+ xlnx,debug-trace-size = <0x2000>;
97+ xlnx,div-zero-exception = <0x1>;
98+ xlnx,dp-axi-mon = <0x0>;
99+ xlnx,dynamic-bus-sizing = <0x0>;
100+ xlnx,ecc-use-ce-exception = <0x0>;
101+ xlnx,edge-is-positive = <0x1>;
102+ xlnx,enable-discrete-ports = <0x0>;
103+ xlnx,endianness = <0x1>;
104+ xlnx,fault-tolerant = <0x0>;
105+ xlnx,fpu-exception = <0x0>;
106+ xlnx,freq = <0xbebc200>;
107+ xlnx,fsl-exception = <0x0>;
108+ xlnx,fsl-links = <0x0>;
109+ xlnx,i-axi = <0x0>;
110+ xlnx,i-lmb = <0x1>;
111+ xlnx,i-lmb-mon = <0x0>;
112+ xlnx,iaddr-size = <0x20>;
113+ xlnx,ic-axi-mon = <0x0>;
114+ xlnx,icache-always-used = <0x1>;
115+ xlnx,icache-data-width = <0x0>;
116+ xlnx,icache-force-tag-lutram = <0x0>;
117+ xlnx,icache-line-len = <0x4>;
118+ xlnx,icache-streams = <0x1>;
119+ xlnx,icache-victims = <0x8>;
120+ xlnx,ill-opcode-exception = <0x1>;
121+ xlnx,imprecise-exceptions = <0x0>;
122+ xlnx,instr-size = <0x20>;
123+ xlnx,interconnect = <0x2>;
124+ xlnx,interrupt-is-edge = <0x0>;
125+ xlnx,interrupt-mon = <0x0>;
126+ xlnx,ip-axi-mon = <0x0>;
127+ xlnx,lockstep-master = <0x0>;
128+ xlnx,lockstep-select = <0x0>;
129+ xlnx,lockstep-slave = <0x0>;
130+ xlnx,mmu-dtlb-size = <0x4>;
131+ xlnx,mmu-itlb-size = <0x2>;
132+ xlnx,mmu-privileged-instr = <0x0>;
133+ xlnx,mmu-tlb-access = <0x3>;
134+ xlnx,mmu-zones = <0x2>;
135+ xlnx,num-sync-ff-clk = <0x2>;
136+ xlnx,num-sync-ff-clk-debug = <0x2>;
137+ xlnx,num-sync-ff-clk-irq = <0x1>;
138+ xlnx,num-sync-ff-dbg-clk = <0x1>;
139+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
140+ xlnx,number-of-pc-brk = <0x1>;
141+ xlnx,number-of-rd-addr-brk = <0x0>;
142+ xlnx,number-of-wr-addr-brk = <0x0>;
143+ xlnx,opcode-0x0-illegal = <0x1>;
144+ xlnx,optimization = <0x0>;
145+ xlnx,pc-width = <0x20>;
146+ xlnx,piaddr-size = <0x20>;
147+ xlnx,pvr = <0x2>;
148+ xlnx,pvr-user1 = <0x0>;
149+ xlnx,pvr-user2 = <0x0>;
150+ xlnx,reset-msr = <0x0>;
151+ xlnx,reset-msr-bip = <0x0>;
152+ xlnx,reset-msr-dce = <0x0>;
153+ xlnx,reset-msr-ee = <0x0>;
154+ xlnx,reset-msr-eip = <0x0>;
155+ xlnx,reset-msr-ice = <0x0>;
156+ xlnx,reset-msr-ie = <0x0>;
157+ xlnx,sco = <0x0>;
158+ xlnx,trace = <0x0>;
159+ xlnx,unaligned-exceptions = <0x1>;
160+ xlnx,use-barrel = <0x1>;
161+ xlnx,use-branch-target-cache = <0x0>;
162+ xlnx,use-config-reset = <0x0>;
163+ xlnx,use-dcache = <0x1>;
164+ xlnx,use-div = <0x1>;
165+ xlnx,use-ext-brk = <0x0>;
166+ xlnx,use-ext-nm-brk = <0x0>;
167+ xlnx,use-extended-fsl-instr = <0x0>;
168+ xlnx,use-fpu = <0x0>;
169+ xlnx,use-hw-mul = <0x2>;
170+ xlnx,use-icache = <0x1>;
171+ xlnx,use-interrupt = <0x2>;
172+ xlnx,use-mmu = <0x3>;
173+ xlnx,use-msr-instr = <0x1>;
174+ xlnx,use-non-secure = <0x0>;
175+ xlnx,use-pcmp-instr = <0x1>;
176+ xlnx,use-reorder-instr = <0x1>;
177+ xlnx,use-stack-protection = <0x0>;
178+ };
179+ };
180+
181+ clocks {
182+ #address-cells = <0x1>;
183+ #size-cells = <0x0>;
184+
185+ clk_cpu@0 {
186+ #clock-cells = <0x0>;
187+ clock-frequency = <0xbebc200>;
188+ clock-output-names = "clk_cpu";
189+ compatible = "fixed-clock";
190+ reg = <0x0>;
191+ linux,phandle = <0x3>;
192+ phandle = <0x3>;
193+ };
194+
195+ clk_bus_0@1 {
196+ #clock-cells = <0x0>;
197+ clock-frequency = <0xbebc200>;
198+ clock-output-names = "clk_bus_0";
199+ compatible = "fixed-clock";
200+ reg = <0x1>;
201+ linux,phandle = <0x8>;
202+ phandle = <0x8>;
203+ };
204+ };
205+
206+ amba_pl {
207+ #address-cells = <0x1>;
208+ #size-cells = <0x1>;
209+ compatible = "simple-bus";
210+ ranges;
211+ linux,phandle = <0x2>;
212+ phandle = <0x2>;
213+
214+ ethernet@40c00000 {
215+ axistream-connected = <0x5>;
216+ axistream-control-connected = <0x5>;
217+ clock-frequency = <0x5f5e100>;
218+ compatible = "xlnx,axi-ethernet-1.00.a";
219+ device_type = "network";
220+ interrupt-parent = <0x4>;
221+ interrupts = <0x4 0x2>;
222+ phy-mode = "gmii";
223+ reg = <0x40c00000 0x40000>;
224+ xlnx = <0x0>;
225+ xlnx,axiliteclkrate = <0x0>;
226+ xlnx,axisclkrate = <0x0>;
227+ xlnx,clockselection = <0x0>;
228+ xlnx,enableasyncsgmii = <0x0>;
229+ xlnx,gt-type = <0x0>;
230+ xlnx,gtinex = <0x0>;
231+ xlnx,gtlocation = <0x0>;
232+ xlnx,gtrefclksrc = <0x0>;
233+ xlnx,include-dre;
234+ xlnx,instantiatebitslice0 = <0x0>;
235+ xlnx,phy-type = <0x1>;
236+ xlnx,phyaddr = <0x1>;
237+ xlnx,rable = <0x0>;
238+ xlnx,rxcsum = <0x0>;
239+ xlnx,rxlane0-placement = <0x0>;
240+ xlnx,rxlane1-placement = <0x0>;
241+ xlnx,rxmem = <0x1000>;
242+ xlnx,rxnibblebitslice0used = <0x0>;
243+ xlnx,tx-in-upper-nibble = <0x1>;
244+ xlnx,txcsum = <0x0>;
245+ xlnx,txlane0-placement = <0x0>;
246+ xlnx,txlane1-placement = <0x0>;
247+ phy-handle = <0x6>;
248+ local-mac-address = [00 0a 35 00 22 01];
249+ linux,phandle = <0x7>;
250+ phandle = <0x7>;
251+
252+ mdio {
253+ #address-cells = <0x1>;
254+ #size-cells = <0x0>;
255+
256+ phy@7 {
257+ device_type = "ethernet-phy";
258+ reg = <0x7>;
259+ linux,phandle = <0x6>;
260+ phandle = <0x6>;
261+ };
262+ };
263+ };
264+
265+ dma@41e00000 {
266+ #dma-cells = <0x1>;
267+ axistream-connected = <0x7>;
268+ axistream-control-connected = <0x7>;
269+ clock-frequency = <0xbebc200>;
270+ clock-names = "s_axi_lite_aclk";
271+ clocks = <0x8>;
272+ compatible = "xlnx,eth-dma";
273+ interrupt-parent = <0x4>;
274+ interrupts = <0x3 0x2 0x2 0x2>;
275+ reg = <0x41e00000 0x10000>;
276+ xlnx,include-dre;
277+ linux,phandle = <0x5>;
278+ phandle = <0x5>;
279+ };
280+
281+ timer@41c00000 {
282+ clock-frequency = <0xbebc200>;
283+ clocks = <0x8>;
284+ compatible = "xlnx,xps-timer-1.00.a";
285+ interrupt-parent = <0x4>;
286+ interrupts = <0x5 0x2>;
287+ reg = <0x41c00000 0x10000>;
288+ xlnx,count-width = <0x20>;
289+ xlnx,gen0-assert = <0x1>;
290+ xlnx,gen1-assert = <0x1>;
291+ xlnx,one-timer-only = <0x0>;
292+ xlnx,trig0-assert = <0x1>;
293+ xlnx,trig1-assert = <0x1>;
294+ };
295+
296+ gpio@40010000 {
297+ #gpio-cells = <0x2>;
298+ compatible = "xlnx,xps-gpio-1.00.a";
299+ gpio-controller;
300+ reg = <0x40010000 0x10000>;
301+ xlnx,all-inputs = <0x1>;
302+ xlnx,all-inputs-2 = <0x0>;
303+ xlnx,all-outputs = <0x0>;
304+ xlnx,all-outputs-2 = <0x0>;
305+ xlnx,dout-default = <0x0>;
306+ xlnx,dout-default-2 = <0x0>;
307+ xlnx,gpio-width = <0x1>;
308+ xlnx,gpio2-width = <0x20>;
309+ xlnx,interrupt-present = <0x0>;
310+ xlnx,is-dual = <0x0>;
311+ xlnx,tri-default = <0xffffffff>;
312+ xlnx,tri-default-2 = <0xffffffff>;
313+ };
314+
315+ gpio@40020000 {
316+ #gpio-cells = <0x2>;
317+ compatible = "xlnx,xps-gpio-1.00.a";
318+ gpio-controller;
319+ reg = <0x40020000 0x10000>;
320+ xlnx,all-inputs = <0x1>;
321+ xlnx,all-inputs-2 = <0x0>;
322+ xlnx,all-outputs = <0x0>;
323+ xlnx,all-outputs-2 = <0x0>;
324+ xlnx,dout-default = <0x0>;
325+ xlnx,dout-default-2 = <0x0>;
326+ xlnx,gpio-width = <0x4>;
327+ xlnx,gpio2-width = <0x20>;
328+ xlnx,interrupt-present = <0x0>;
329+ xlnx,is-dual = <0x0>;
330+ xlnx,tri-default = <0xffffffff>;
331+ xlnx,tri-default-2 = <0xffffffff>;
332+ };
333+
334+ i2c@40800000 {
335+ #address-cells = <0x1>;
336+ #size-cells = <0x0>;
337+ clock-frequency = <0xbebc200>;
338+ clocks = <0x8>;
339+ compatible = "xlnx,xps-iic-2.00.a";
340+ interrupt-parent = <0x4>;
341+ interrupts = <0x1 0x2>;
342+ reg = <0x40800000 0x10000>;
343+
344+ i2cswitch@74 {
345+ compatible = "nxp,pca9548";
346+ #address-cells = <0x1>;
347+ #size-cells = <0x0>;
348+ reg = <0x74>;
349+
350+ i2c@0 {
351+ #address-cells = <0x1>;
352+ #size-cells = <0x0>;
353+ reg = <0x0>;
354+
355+ clock-generator@5d {
356+ #clock-cells = <0x0>;
357+ compatible = "silabs,si570";
358+ temperature-stability = <0x32>;
359+ reg = <0x5d>;
360+ factory-fout = <0x9502f90>;
361+ clock-frequency = <0x8d9ee20>;
362+ };
363+ };
364+
365+ i2c@3 {
366+ #address-cells = <0x1>;
367+ #size-cells = <0x0>;
368+ reg = <0x3>;
369+
370+ eeprom@54 {
371+ compatible = "at,24c08";
372+ reg = <0x54>;
373+ };
374+ };
375+ };
376+ };
377+
378+ gpio@40030000 {
379+ #gpio-cells = <0x2>;
380+ compatible = "xlnx,xps-gpio-1.00.a";
381+ gpio-controller;
382+ reg = <0x40030000 0x10000>;
383+ xlnx,all-inputs = <0x0>;
384+ xlnx,all-inputs-2 = <0x0>;
385+ xlnx,all-outputs = <0x1>;
386+ xlnx,all-outputs-2 = <0x0>;
387+ xlnx,dout-default = <0x0>;
388+ xlnx,dout-default-2 = <0x0>;
389+ xlnx,gpio-width = <0x8>;
390+ xlnx,gpio2-width = <0x20>;
391+ xlnx,interrupt-present = <0x0>;
392+ xlnx,is-dual = <0x0>;
393+ xlnx,tri-default = <0xffffffff>;
394+ xlnx,tri-default-2 = <0xffffffff>;
395+ };
396+
397+ flash@60000000 {
398+ bank-width = <0x2>;
399+ compatible = "cfi-flash";
400+ reg = <0x60000000 0x8000000>;
401+ xlnx,axi-clk-period-ps = <0x1388>;
402+ xlnx,include-datawidth-matching-0 = <0x1>;
403+ xlnx,include-datawidth-matching-1 = <0x1>;
404+ xlnx,include-datawidth-matching-2 = <0x1>;
405+ xlnx,include-datawidth-matching-3 = <0x1>;
406+ xlnx,include-negedge-ioregs = <0x0>;
407+ xlnx,lflash-period-ps = <0x1388>;
408+ xlnx,linear-flash-sync-burst = <0x0>;
409+ xlnx,max-mem-width = <0x10>;
410+ xlnx,mem-a-lsb = <0x0>;
411+ xlnx,mem-a-msb = <0x1f>;
412+ xlnx,mem0-type = <0x2>;
413+ xlnx,mem0-width = <0x10>;
414+ xlnx,mem1-type = <0x0>;
415+ xlnx,mem1-width = <0x10>;
416+ xlnx,mem2-type = <0x0>;
417+ xlnx,mem2-width = <0x10>;
418+ xlnx,mem3-type = <0x0>;
419+ xlnx,mem3-width = <0x10>;
420+ xlnx,num-banks-mem = <0x1>;
421+ xlnx,page-size = <0x10>;
422+ xlnx,parity-type-mem-0 = <0x0>;
423+ xlnx,parity-type-mem-1 = <0x0>;
424+ xlnx,parity-type-mem-2 = <0x0>;
425+ xlnx,parity-type-mem-3 = <0x0>;
426+ xlnx,port-diff = <0x0>;
427+ xlnx,s-axi-en-reg = <0x0>;
428+ xlnx,s-axi-mem-addr-width = <0x20>;
429+ xlnx,s-axi-mem-data-width = <0x20>;
430+ xlnx,s-axi-mem-id-width = <0x1>;
431+ xlnx,s-axi-reg-addr-width = <0x5>;
432+ xlnx,s-axi-reg-data-width = <0x20>;
433+ xlnx,synch-pipedelay-0 = <0x1>;
434+ xlnx,synch-pipedelay-1 = <0x1>;
435+ xlnx,synch-pipedelay-2 = <0x1>;
436+ xlnx,synch-pipedelay-3 = <0x1>;
437+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
438+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
439+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
440+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
441+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
442+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
443+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
444+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
445+ xlnx,thzce-ps-mem-0 = <0x88b8>;
446+ xlnx,thzce-ps-mem-1 = <0x1b58>;
447+ xlnx,thzce-ps-mem-2 = <0x1b58>;
448+ xlnx,thzce-ps-mem-3 = <0x1b58>;
449+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
450+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
451+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
452+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
453+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
454+ xlnx,tlzwe-ps-mem-1 = <0x0>;
455+ xlnx,tlzwe-ps-mem-2 = <0x0>;
456+ xlnx,tlzwe-ps-mem-3 = <0x0>;
457+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
458+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
459+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
460+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
461+ xlnx,twc-ps-mem-0 = <0x11170>;
462+ xlnx,twc-ps-mem-1 = <0x3a98>;
463+ xlnx,twc-ps-mem-2 = <0x3a98>;
464+ xlnx,twc-ps-mem-3 = <0x3a98>;
465+ xlnx,twp-ps-mem-0 = <0x13880>;
466+ xlnx,twp-ps-mem-1 = <0x2ee0>;
467+ xlnx,twp-ps-mem-2 = <0x2ee0>;
468+ xlnx,twp-ps-mem-3 = <0x2ee0>;
469+ xlnx,twph-ps-mem-0 = <0x13880>;
470+ xlnx,twph-ps-mem-1 = <0x2ee0>;
471+ xlnx,twph-ps-mem-2 = <0x2ee0>;
472+ xlnx,twph-ps-mem-3 = <0x2ee0>;
473+ xlnx,use-startup = <0x0>;
474+ xlnx,use-startup-int = <0x0>;
475+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
476+ xlnx,wr-rec-time-mem-1 = <0x6978>;
477+ xlnx,wr-rec-time-mem-2 = <0x6978>;
478+ xlnx,wr-rec-time-mem-3 = <0x6978>;
479+ #address-cells = <0x1>;
480+ #size-cells = <0x1>;
481+
482+ partition@0x00000000 {
483+ label = "fpga";
484+ reg = <0x0 0xb00000>;
485+ };
486+
487+ partition@0x00b00000 {
488+ label = "boot";
489+ reg = <0xb00000 0x80000>;
490+ };
491+
492+ partition@0x00b80000 {
493+ label = "bootenv";
494+ reg = <0xb80000 0x20000>;
495+ };
496+
497+ partition@0x00ba0000 {
498+ label = "kernel";
499+ reg = <0xba0000 0xc00000>;
500+ };
501+
502+ partition@0x017a0000 {
503+ label = "spare";
504+ reg = <0x17a0000 0x0>;
505+ };
506+ };
507+
508+ interrupt-controller@41200000 {
509+ #interrupt-cells = <0x2>;
510+ compatible = "xlnx,xps-intc-1.00.a";
511+ interrupt-controller;
512+ reg = <0x41200000 0x10000>;
513+ xlnx,kind-of-intr = <0x0>;
514+ xlnx,num-intr-inputs = <0x6>;
515+ linux,phandle = <0x4>;
516+ phandle = <0x4>;
517+ };
518+
519+ gpio@40040000 {
520+ #gpio-cells = <0x2>;
521+ compatible = "xlnx,xps-gpio-1.00.a";
522+ gpio-controller;
523+ reg = <0x40040000 0x10000>;
524+ xlnx,all-inputs = <0x1>;
525+ xlnx,all-inputs-2 = <0x0>;
526+ xlnx,all-outputs = <0x0>;
527+ xlnx,all-outputs-2 = <0x0>;
528+ xlnx,dout-default = <0x0>;
529+ xlnx,dout-default-2 = <0x0>;
530+ xlnx,gpio-width = <0x5>;
531+ xlnx,gpio2-width = <0x20>;
532+ xlnx,interrupt-present = <0x0>;
533+ xlnx,is-dual = <0x0>;
534+ xlnx,tri-default = <0xffffffff>;
535+ xlnx,tri-default-2 = <0xffffffff>;
536+ };
537+
538+ gpio@40000000 {
539+ #gpio-cells = <0x2>;
540+ compatible = "xlnx,xps-gpio-1.00.a";
541+ gpio-controller;
542+ reg = <0x40000000 0x10000>;
543+ xlnx,all-inputs = <0x0>;
544+ xlnx,all-inputs-2 = <0x0>;
545+ xlnx,all-outputs = <0x1>;
546+ xlnx,all-outputs-2 = <0x0>;
547+ xlnx,dout-default = <0x0>;
548+ xlnx,dout-default-2 = <0x0>;
549+ xlnx,gpio-width = <0x1>;
550+ xlnx,gpio2-width = <0x20>;
551+ xlnx,interrupt-present = <0x0>;
552+ xlnx,is-dual = <0x0>;
553+ xlnx,tri-default = <0xffffffff>;
554+ xlnx,tri-default-2 = <0xffffffff>;
555+ linux,phandle = <0x1>;
556+ phandle = <0x1>;
557+ };
558+
559+ serial@44a00000 {
560+ clock-frequency = <0xbebc200>;
561+ clocks = <0x8>;
562+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
563+ current-speed = <0x1c200>;
564+ device_type = "serial";
565+ interrupt-parent = <0x4>;
566+ interrupts = <0x0 0x2>;
567+ port-number = <0x0>;
568+ reg = <0x44a00000 0x10000>;
569+ reg-offset = <0x1000>;
570+ reg-shift = <0x2>;
571+ xlnx,external-xin-clk-hz = <0x17d7840>;
572+ xlnx,external-xin-clk-hz-d = <0x19>;
573+ xlnx,has-external-rclk = <0x0>;
574+ xlnx,has-external-xin = <0x0>;
575+ xlnx,is-a-16550 = <0x1>;
576+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
577+ xlnx,use-modem-ports = <0x1>;
578+ xlnx,use-user-ports = <0x1>;
579+ };
580+ };
581+
582 chosen {
583- } ;
584-} ;
585+ bootargs = "console=ttyS0,115200 earlyprintk";
586+ stdout-path = "serial0:115200n8";
587+ };
588+
589+ aliases {
590+ ethernet0 = "/amba_pl/ethernet@40c00000";
591+ i2c0 = "/amba_pl/i2c@40800000";
592+ serial0 = "/amba_pl/serial@44a00000";
593+ };
594+
595+ memory {
596+ device_type = "memory";
597+ reg = <0x80000000 0x40000000>;
598+ };
599+};
600+
601diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
602index 1dee2d6..cb75fde 100644
603--- a/board/xilinx/microblaze-generic/config.mk
604+++ b/board/xilinx/microblaze-generic/config.mk
605@@ -1,20 +1,10 @@
606-#
607-# (C) Copyright 2007 - 2016 Michal Simek
608-#
609-# Michal SIMEK <monstr@monstr.eu>
610-#
611-# SPDX-License-Identifier: GPL-2.0+
612-#
613-
614-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
615-
616-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
617-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
618-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
619-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
620-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
621-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
622-
623-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
624-
625-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
626+TEXT_BASE = 0x80400000
627+CONFIG_SYS_TEXT_BASE = 0x80400000
628+
629+PLATFORM_CPPFLAGS += -mxl-barrel-shift
630+PLATFORM_CPPFLAGS += -mno-xl-soft-div
631+PLATFORM_CPPFLAGS += -mxl-pattern-compare
632+PLATFORM_CPPFLAGS += -mxl-multiply-high
633+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
634+PLATFORM_CPPFLAGS += -mcpu=v10.0
635+PLATFORM_CPPFLAGS += -fgnu89-inline
636diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
637index 5d13d21..1458ce6 100644
638--- a/configs/microblaze-generic_defconfig
639+++ b/configs/microblaze-generic_defconfig
640@@ -7,32 +7,35 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
641 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
642 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
643 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
644-CONFIG_SYS_TEXT_BASE=0x29000000
645+CONFIG_SYS_TEXT_BASE=0x80400000
646 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
647 CONFIG_FIT=y
648 CONFIG_FIT_VERBOSE=y
649-CONFIG_BOOTDELAY=-1
650+CONFIG_BOOTDELAY=4
651 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
652-CONFIG_SPL=y
653-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
654 CONFIG_SPL_NOR_SUPPORT=y
655 CONFIG_SPL_OS_BOOT=y
656 CONFIG_SYS_OS_BASE=0x2c060000
657 CONFIG_HUSH_PARSER=y
658-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
659+CONFIG_SYS_PROMPT="U-Boot> "
660 CONFIG_CMD_ASKENV=y
661-CONFIG_CMD_GPIO=y
662 # CONFIG_CMD_SETEXPR is not set
663-CONFIG_CMD_TFTPPUT=y
664+CONFIG_SYS_ENET=y
665+CONFIG_NET=y
666+CONFIG_NETDEVICES=y
667+CONFIG_CMD_NET=y
668 CONFIG_CMD_DHCP=y
669+CONFIG_CMD_NFS=y
670 CONFIG_CMD_MII=y
671 CONFIG_CMD_PING=y
672-CONFIG_SPL_OF_CONTROL=y
673 CONFIG_OF_EMBED=y
674-CONFIG_NETCONSOLE=y
675-CONFIG_SPL_DM=y
676 CONFIG_DM_ETH=y
677+CONFIG_SYS_MALLOC_F=y
678+CONFIG_SYS_GENERIC_BOARD=y
679 CONFIG_XILINX_AXIEMAC=y
680-CONFIG_XILINX_EMACLITE=y
681 CONFIG_SYS_NS16550=y
682-CONFIG_XILINX_UARTLITE=y
683+CONFIG_CMD_FLASH=y
684+CONFIG_CMD_IMLS=y
685+CONFIG_CMD_GPIO=y
686+CONFIG_CMD_TFTPPUT=y
687+CONFIG_NETCONSOLE=y
688diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
689index 36b0a0e..1227c95 100644
690--- a/include/configs/microblaze-generic.h
691+++ b/include/configs/microblaze-generic.h
692@@ -1,319 +1,183 @@
693-/*
694- * (C) Copyright 2007-2010 Michal Simek
695- *
696- * Michal SIMEK <monstr@monstr.eu>
697- *
698- * SPDX-License-Identifier: GPL-2.0+
699- */
700-
701 #ifndef __CONFIG_H
702 #define __CONFIG_H
703
704-#include "../board/xilinx/microblaze-generic/xparameters.h"
705-
706-/* MicroBlaze CPU */
707-#define MICROBLAZE_V5 1
708-
709-/* linear and spi flash memory */
710-#ifdef XILINX_FLASH_START
711-#define FLASH
712-#undef SPIFLASH
713-#undef RAMENV /* hold environment in flash */
714-#else
715-#ifdef XILINX_SPI_FLASH_BASEADDR
716-#undef FLASH
717-#define SPIFLASH
718-#undef RAMENV /* hold environment in flash */
719-#else
720-#undef FLASH
721-#undef SPIFLASH
722-#define RAMENV /* hold environment in RAM */
723-#endif
724-#endif
725-
726-/* uart */
727-# define CONFIG_BAUDRATE 115200
728-/* The following table includes the supported baudrates */
729-# define CONFIG_SYS_BAUDRATE_TABLE \
730- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
731-
732-/* setting reset address */
733-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
734+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
735
736-/* gpio */
737-#ifdef XILINX_GPIO_BASEADDR
738-# define CONFIG_XILINX_GPIO
739-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
740-#endif
741-#define CONFIG_BOARD_LATE_INIT
742-
743-/* watchdog */
744-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
745-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
746-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
747-# ifndef CONFIG_SPL_BUILD
748-# define CONFIG_HW_WATCHDOG
749-# define CONFIG_XILINX_TB_WATCHDOG
750-# endif
751-#endif
752-
753-#define CONFIG_SYS_MALLOC_LEN 0xC0000
754-
755-/* Stack location before relocation */
756-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
757- CONFIG_SYS_MALLOC_F_LEN)
758-
759-/*
760- * CFI flash memory layout - Example
761- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
762- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
763- *
764- * SECT_SIZE = 0x20000; 128kB is one sector
765- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
766- *
767- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
768- * FREE 256kB
769- * 0x2204_0000 CONFIG_ENV_ADDR
770- * ENV_AREA 128kB
771- * 0x2206_0000
772- * FREE
773- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
774- *
775- */
776-
777-#ifdef FLASH
778-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
779-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
780-# define CONFIG_SYS_FLASH_CFI 1
781-# define CONFIG_FLASH_CFI_DRIVER 1
782-/* ?empty sector */
783-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
784-/* max number of memory banks */
785-# define CONFIG_SYS_MAX_FLASH_BANKS 1
786-/* max number of sectors on one chip */
787-# define CONFIG_SYS_MAX_FLASH_SECT 512
788-/* hardware flash protection */
789-# define CONFIG_SYS_FLASH_PROTECTION
790-/* use buffered writes (20x faster) */
791-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
792-# ifdef RAMENV
793-# define CONFIG_ENV_IS_NOWHERE 1
794-# define CONFIG_ENV_SIZE 0x1000
795-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
796-
797-# else /* FLASH && !RAMENV */
798-# define CONFIG_ENV_IS_IN_FLASH 1
799-/* 128K(one sector) for env */
800-# define CONFIG_ENV_SECT_SIZE 0x20000
801-# define CONFIG_ENV_ADDR \
802- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
803-# define CONFIG_ENV_SIZE 0x20000
804-# endif /* FLASH && !RAMBOOT */
805-#else /* !FLASH */
806-
807-#ifdef SPIFLASH
808-# define CONFIG_SYS_NO_FLASH 1
809-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
810-# define CONFIG_SPI 1
811-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
812-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
813-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
814-
815-# ifdef RAMENV
816-# define CONFIG_ENV_IS_NOWHERE 1
817-# define CONFIG_ENV_SIZE 0x1000
818-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
819-
820-# else /* SPIFLASH && !RAMENV */
821-# define CONFIG_ENV_IS_IN_SPI_FLASH 1
822-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
823-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
824-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
825-/* 128K(two sectors) for env */
826-# define CONFIG_ENV_SECT_SIZE 0x10000
827-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
828-/* Warning: adjust the offset in respect of other flash content and size */
829-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
830-# endif /* SPIFLASH && !RAMBOOT */
831-#else /* !SPIFLASH */
832-
833-/* ENV in RAM */
834-# define CONFIG_SYS_NO_FLASH 1
835-# define CONFIG_ENV_IS_NOWHERE 1
836-# define CONFIG_ENV_SIZE 0x1000
837-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
838-#endif /* !SPIFLASH */
839-#endif /* !FLASH */
840-
841-#if defined(XILINX_USE_ICACHE)
842-# define CONFIG_ICACHE
843-#else
844-# undef CONFIG_ICACHE
845-#endif
846-
847-#if defined(XILINX_USE_DCACHE)
848-# define CONFIG_DCACHE
849-#else
850-# undef CONFIG_DCACHE
851-#endif
852+/* use serial multi for all serial devices */
853+#define CONFIG_SERIAL_MULTI
854+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
855
856-#ifndef XILINX_DCACHE_BYTE_SIZE
857-#define XILINX_DCACHE_BYTE_SIZE 32768
858-#endif
859+/* Board name */
860
861-/*
862- * BOOTP options
863- */
864+/* processor - microblaze_0 */
865+#define XILINX_USE_MSR_INSTR 1
866+#define XILINX_USE_ICACHE 1
867+#define XILINX_USE_DCACHE 1
868+#define XILINX_DCACHE_BYTE_SIZE 16384
869+#define XILINX_PVR 2
870+#define MICROBLAZE_V5
871+#define CONFIG_CMD_IRQ
872+#define CONFIG_DCACHE
873+#define CONFIG_ICACHE
874+
875+/* main_memory - ddr3_sdram */
876+
877+
878+/* uart - rs232_uart */
879+#define CONFIG_CONS_INDEX 1
880+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
881+#define CONFIG_SYS_NS16550_REG_SIZE -4
882+#define CONSOLE_ARG "console=console=ttyS0,115200\0"
883+#define CONFIG_SYS_NS16550_SERIAL
884+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
885+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
886+#define CONFIG_SYS_NS16550_CLK 200000000
887+#define CONFIG_BAUDRATE 115200
888+
889+/* ethernet - axi_ethernet */
890+#define CONFIG_PHY_XILINX
891+#define CONFIG_MII
892+#define CONFIG_PHY_GIGE
893+#define CONFIG_PHY_MARVELL
894+#define CONFIG_PHY_NATSEMI
895+#define CONFIG_NET_MULTI
896+#define CONFIG_NETCONSOLE 1
897+#define CONFIG_SERVERIP 172.25.229.115
898+#define CONFIG_IPADDR
899+
900+/* nor_flash - linear_flash */
901+#define CONFIG_SYS_FLASH_BASE 0x60000000
902+#define CONFIG_FLASH_END 0x68000000
903+#define CONFIG_SYS_MAX_FLASH_SECT 2048
904+#define CONFIG_SYS_FLASH_PROTECTION
905+#define CONFIG_SYS_FLASH_EMPTY_INFO
906+#define CONFIG_SYS_FLASH_CFI
907+#define CONFIG_FLASH_CFI_DRIVER
908+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
909+#define CONFIG_SYS_MAX_FLASH_BANKS 1
910+
911+/* timer - axi_timer_0 */
912+
913+/* gpio - reset_gpio */
914+#define XILINX_GPIO_BASEADDR 0x40000000
915+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
916+#define CONFIG_XILINX_GPIO
917+
918+/* intc - microblaze_0_axi_intc */
919+
920+/* Make the BOOTM LEN big enough for the compressed image */
921+#define CONFIG_SYS_BOOTM_LEN 0xF000000
922+
923+/* FPGA */
924+
925+/* Memory testing handling */
926+#define CONFIG_SYS_MEMTEST_START 0x80000000
927+#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000)
928+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */
929+
930+/* global pointer options */
931+#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE)
932+
933+/* Size of malloc() pool */
934+#define SIZE 0x100000
935+#define CONFIG_SYS_MALLOC_LEN SIZE
936+#define CONFIG_SYS_MONITOR_LEN SIZE
937+#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
938+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
939+
940+/* stack */
941+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
942+
943+/* No of_control support yet*/
944+
945+/* BOOTP options */
946+#define CONFIG_BOOTP_SERVERIP
947 #define CONFIG_BOOTP_BOOTFILESIZE
948 #define CONFIG_BOOTP_BOOTPATH
949 #define CONFIG_BOOTP_GATEWAY
950 #define CONFIG_BOOTP_HOSTNAME
951+#define CONFIG_BOOTP_MAY_FAIL
952
953-/*
954- * Command line configuration.
955- */
956-#define CONFIG_CMD_IRQ
957-#define CONFIG_CMD_MFSL
958-
959-#if defined(FLASH)
960-# define CONFIG_CMD_JFFS2
961-# undef CONFIG_CMD_UBIFS
962-
963-# if !defined(RAMENV)
964-# define CONFIG_CMD_SAVES
965-# endif
966-
967-#else
968-#if defined(SPIFLASH)
969-
970-# if !defined(RAMENV)
971-# define CONFIG_CMD_SAVES
972-# endif
973-#else
974-# undef CONFIG_CMD_JFFS2
975-# undef CONFIG_CMD_UBIFS
976-#endif
977-#endif
978-
979-#if defined(CONFIG_CMD_JFFS2)
980-# define CONFIG_MTD_PARTITIONS
981-#endif
982-
983-#if defined(CONFIG_CMD_UBIFS)
984-# define CONFIG_LZO
985-#endif
986-
987-#if defined(CONFIG_CMD_UBI)
988-# define CONFIG_MTD_PARTITIONS
989-# define CONFIG_RBTREE
990-#endif
991-
992-#if defined(CONFIG_MTD_PARTITIONS)
993-/* MTD partitions */
994-#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
995-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
996-#define CONFIG_FLASH_CFI_MTD
997-#define MTDIDS_DEFAULT "nor0=flash-0"
998-
999-/* default mtd partition table */
1000-#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
1001- "256k(env),3m(kernel),1m(romfs),"\
1002- "1m(cramfs),-(jffs2)"
1003-#endif
1004-
1005-/* size of console buffer */
1006-#define CONFIG_SYS_CBSIZE 512
1007- /* print buffer size */
1008-#define CONFIG_SYS_PBSIZE \
1009- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1010-/* max number of command args */
1011-#define CONFIG_SYS_MAXARGS 15
1012-#define CONFIG_SYS_LONGHELP
1013-/* default load address */
1014-#define CONFIG_SYS_LOAD_ADDR 0
1015-
1016-#define CONFIG_BOOTARGS "root=romfs"
1017-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
1018-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
1019-
1020-/* architecture dependent code */
1021-#define CONFIG_SYS_USR_EXCEP /* user exception */
1022-
1023-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
1024-
1025-#ifndef CONFIG_EXTRA_ENV_SETTINGS
1026-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
1027- "nor0=flash-0\0"\
1028- "mtdparts=mtdparts=flash-0:"\
1029- "256k(u-boot),256k(env),3m(kernel),"\
1030- "1m(romfs),1m(cramfs),-(jffs2)\0"\
1031- "nc=setenv stdout nc;"\
1032- "setenv stdin nc\0" \
1033- "serial=setenv stdout serial;"\
1034- "setenv stdin serial\0"
1035-#endif
1036-
1037+/*Command line configuration.*/
1038 #define CONFIG_CMDLINE_EDITING
1039+#define CONFIG_CMD_SAVES
1040
1041-/* Enable flat device tree support */
1042-#define CONFIG_LMB 1
1043-
1044-#if defined(CONFIG_XILINX_AXIEMAC)
1045-# define CONFIG_MII 1
1046-# define CONFIG_PHY_GIGE 1
1047-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
1048-# define CONFIG_PHY_ATHEROS 1
1049-# define CONFIG_PHY_BROADCOM 1
1050-# define CONFIG_PHY_DAVICOM 1
1051-# define CONFIG_PHY_LXT 1
1052-# define CONFIG_PHY_MARVELL 1
1053-# define CONFIG_PHY_MICREL 1
1054-# define CONFIG_PHY_MICREL_KSZ9021
1055-# define CONFIG_PHY_NATSEMI 1
1056-# define CONFIG_PHY_REALTEK 1
1057-# define CONFIG_PHY_VITESSE 1
1058-#else
1059-# undef CONFIG_MII
1060-#endif
1061-
1062-/* SPL part */
1063-#define CONFIG_CMD_SPL
1064-#define CONFIG_SPL_FRAMEWORK
1065-#define CONFIG_SPL_BOARD_INIT
1066+/* Miscellaneous configurable options */
1067+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
1068+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1069
1070-#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
1071+/* Boot Argument Buffer Size */
1072+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
1073+#define CONFIG_SYS_LONGHELP
1074+/* architecture dependent code */
1075+#define CONFIG_SYS_USR_EXCEP /* user exception */
1076+#define CONFIG_SYS_HZ 1000
1077+
1078+/* Use the HUSH parser */
1079+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1080+
1081+/* Don't define BOOTARGS, we get it from the DTB chosen fragment */
1082+#undef CONFIG_BOOTARGS
1083+
1084+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
1085+
1086+#define CONFIG_LMB
1087+
1088+/* Initial memory map for Linux */
1089+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
1090+
1091+/* Environment settings*/
1092+#define CONFIG_ENV_IS_IN_FLASH
1093+#define CONFIG_ENV_ADDR 0x60b80000
1094+#define CONFIG_ENV_SIZE 0x20000
1095+#define CONFIG_ENV_SECT_SIZE 0x20000
1096+/* PREBOOT */
1097+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
1098+
1099+/* Extra U-Boot Env settings */
1100+#define CONFIG_EXTRA_ENV_SETTINGS \
1101+ SERIAL_MULTI \
1102+ CONSOLE_ARG \
1103+ ESERIAL0 \
1104+ "nc=setenv stdout nc;setenv stdin nc;\0" \
1105+ "ethaddr=00:0a:35:00:22:01\0" \
1106+ "autoload=no\0" \
1107+ "clobstart=0x81000000\0" \
1108+ "netstart=0x81000000\0" \
1109+ "dtbnetstart=0x82800000\0" \
1110+ "loadaddr=0x81000000\0" \
1111+ "bootsize=0x80000\0" \
1112+ "bootstart=0x60b00000\0" \
1113+ "boot_img=u-boot-s.bin\0" \
1114+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
1115+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
1116+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
1117+ "bootenvsize=0x20000\0" \
1118+ "bootenvstart=0x60b80000\0" \
1119+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
1120+ "kernelsize=0xc00000\0" \
1121+ "kernelstart=0x60ba0000\0" \
1122+ "kernel_img=image.ub\0" \
1123+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
1124+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
1125+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
1126+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
1127+ "fpgasize=0xb00000\0" \
1128+ "fpgastart=0x60000000\0" \
1129+ "fpga_img=system.bit.bin\0" \
1130+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
1131+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
1132+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
1133+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
1134+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
1135+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
1136+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
1137+ "default_bootcmd=bootm ${kernelstart}\0" \
1138+""
1139+
1140+/* BOOTCOMMAND */
1141+#define CONFIG_BOOTCOMMAND "run default_bootcmd"
1142+
1143+#undef CONFIG_SPL_BUILD /* Disable SPL by default*/
1144
1145-#define CONFIG_SPL_RAM_DEVICE
1146-#ifdef CONFIG_SYS_FLASH_BASE
1147-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
1148 #endif
1149-
1150-/* for booting directly linux */
1151-
1152-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
1153- 0x40000)
1154-#define CONFIG_SYS_FDT_SIZE (16<<10)
1155-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
1156- 0x1000000)
1157-
1158-/* SP location before relocation, must use scratch RAM */
1159-/* BRAM start */
1160-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
1161-/* BRAM size - will be generated */
1162-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
1163-
1164-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
1165- CONFIG_SYS_INIT_RAM_SIZE - \
1166- CONFIG_SYS_MALLOC_F_LEN)
1167-
1168-/* Just for sure that there is a space for stack */
1169-#define CONFIG_SPL_STACK_SIZE 0x100
1170-
1171-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1172-
1173-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
1174- CONFIG_SYS_INIT_RAM_ADDR - \
1175- CONFIG_SYS_MALLOC_F_LEN - \
1176- CONFIG_SPL_STACK_SIZE)
1177-
1178-#endif /* __CONFIG_H */
1179--
11802.7.4
1181
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb
index b7817c94..016c0cee 100644
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2017.3.bb
@@ -9,6 +9,8 @@ SRC_URI_append = " \
9 file://arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch \ 9 file://arm64-zynqmp-Setup-partid-for-QEMU-to-match-silicon.patch \
10 " 10 "
11 11
12SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
13
12LICENSE = "GPLv2+" 14LICENSE = "GPLv2+"
13LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" 15LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
14 16
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 18:24:10 +0000