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authorNathan Rossi <nathan@nathanrossi.com>2017-12-13 16:55:40 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-01-12 15:29:38 -0800
commit79056fb533f331e51a74621d5b1574df8ae2cae5 (patch)
tree64b50efbce3fff1aa1a05d82aafeeae8549c1c37 /meta-xilinx-bsp
parentebec5ccd1129e6df5dc43c1cfdb59da70dcc3eac (diff)
downloadmeta-xilinx-79056fb533f331e51a74621d5b1574df8ae2cae5.tar.gz
binutils: Add all Xilinx MicroBlaze binutils 2.29 patches
Add all the Xilinx patches for MicroBlaze, this includes bug fixes, testsuite fixes (and workarounds) as well as additional features. A number of these changes are required to support additional Xilinx patches for MicroBlaze GCC. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp')
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend15
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch67
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch66
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch36
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch78
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch236
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch37
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch106
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch232
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch31
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch36
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch30
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch38
13 files changed, 1008 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
new file mode 100644
index 00000000..17843185
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend
@@ -0,0 +1,15 @@
1FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.29:"
2SRC_URI_append_microblaze = " \
3 file://0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
4 file://0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch \
5 file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
6 file://0004-Fix-relaxation-of-assembler-resolved-references.patch \
7 file://0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch \
8 file://0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch \
9 file://0007-Add-MicroBlaze-address-extension-instructions.patch \
10 file://0008-Add-new-MicroBlaze-bit-field-instructions.patch \
11 file://0009-Fixing-MicroBlaze-IMM-bug.patch \
12 file://0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch \
13 file://0011-Fixing-MicroBlaze-constant-range-check-issue.patch \
14 file://0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch \
15 "
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 00000000..193061a3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,67 @@
1From d2979c539c309347493cebae91dc455fa3368f4f Mon Sep 17 00:00:00 2001
2From: David Holsgrove <david.holsgrove@xilinx.com>
3Date: Mon, 28 Aug 2017 19:53:52 -0700
4Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns
5
6Added two new instructions, wdc.ext.clear and wdc.ext.flush,
7to enable MicroBlaze to flush an external cache, which is
8used with the new coherency support for multiprocessing.
9
10Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
11Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
12Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
13Upstream-Status: Pending
14---
15 opcodes/microblaze-opc.h | 5 ++++-
16 opcodes/microblaze-opcm.h | 4 ++--
17 2 files changed, 6 insertions(+), 3 deletions(-)
18
19diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
20index 3954f927d1..b33178145f 100644
21--- a/opcodes/microblaze-opc.h
22+++ b/opcodes/microblaze-opc.h
23@@ -91,6 +91,7 @@
24 #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
25 #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
26 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
27+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
28 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
29
30 /* New Mask for msrset, msrclr insns. */
31@@ -101,7 +102,7 @@
32 #define DELAY_SLOT 1
33 #define NO_DELAY_SLOT 0
34
35-#define MAX_OPCODES 289
36+#define MAX_OPCODES 291
37
38 struct op_code_struct
39 {
40@@ -174,7 +175,9 @@ struct op_code_struct
41 {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
42 {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
43 {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
44+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
45 {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
46+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
47 {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
48 {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
49 {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
50diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
51index 6b25173442..00dc131302 100644
52--- a/opcodes/microblaze-opcm.h
53+++ b/opcodes/microblaze-opcm.h
54@@ -33,8 +33,8 @@ enum microblaze_instr
55 /* 'or/and/xor' are C++ keywords. */
56 microblaze_or, microblaze_and, microblaze_xor,
57 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
58- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
59- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
60+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
61+ brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
62 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
63 imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
64 brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
65--
662.15.0
67
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 00000000..c8142ca4
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,66 @@
1From 90fa3cca5ce8ca19c9aca521bbc3d47485f02bf1 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:53:53 -0700
4Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags
5
6Added support in gas for mlittle-endian and mbig-endian flags
7as options.
8
9Updated show usage for MicroBlaze specific assembler options
10to include new entries.
11
12Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
13Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Pending
16---
17 gas/config/tc-microblaze.c | 9 +++++++++
18 1 file changed, 9 insertions(+)
19
20diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
21index 0124422168..d47793646b 100644
22--- a/gas/config/tc-microblaze.c
23+++ b/gas/config/tc-microblaze.c
24@@ -37,6 +37,8 @@
25
26 #define OPTION_EB (OPTION_MD_BASE + 0)
27 #define OPTION_EL (OPTION_MD_BASE + 1)
28+#define OPTION_LITTLE (OPTION_MD_BASE + 2)
29+#define OPTION_BIG (OPTION_MD_BASE + 3)
30
31 void microblaze_generate_symbol (char *sym);
32 static bfd_boolean check_spl_reg (unsigned *);
33@@ -1837,6 +1839,8 @@ struct option md_longopts[] =
34 {
35 {"EB", no_argument, NULL, OPTION_EB},
36 {"EL", no_argument, NULL, OPTION_EL},
37+ {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
38+ {"mbig-endian", no_argument, NULL, OPTION_BIG},
39 { NULL, no_argument, NULL, 0}
40 };
41
42@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
43 switch (c)
44 {
45 case OPTION_EB:
46+ case OPTION_BIG:
47 target_big_endian = 1;
48 break;
49 case OPTION_EL:
50+ case OPTION_LITTLE:
51 target_big_endian = 0;
52 break;
53 default:
54@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
55 /* fprintf(stream, _("\
56 MicroBlaze options:\n\
57 -noSmall Data in the comm and data sections do not go into the small data section\n")); */
58+ fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
59+ fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
60+ fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
61 }
62
63
64--
652.15.0
66
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 00000000..55f4ce33
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,36 @@
1From f81026057270346cfcfa16e460dcb04a9fa48511 Mon Sep 17 00:00:00 2001
2From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
3Date: Mon, 28 Aug 2017 19:53:54 -0700
4Subject: [PATCH] Disable the warning message for eh_frame_hdr
5
6Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
7Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
8Upstream-Status: Inappropriate [workaround]
9---
10 bfd/elf-eh-frame.c | 9 ++++++---
11 1 file changed, 6 insertions(+), 3 deletions(-)
12
13diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
14index 52ba9c6213..7ac511dfcb 100644
15--- a/bfd/elf-eh-frame.c
16+++ b/bfd/elf-eh-frame.c
17@@ -1046,10 +1046,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
18 goto success;
19
20 free_no_table:
21- (*info->callbacks->einfo)
22+ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */
23+ if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
24 /* xgettext:c-format */
25- (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
26- abfd, sec);
27+ (*info->callbacks->einfo)
28+ (_("%P: error in %B(%A); no .eh_frame_hdr table will be created.\n"),
29+ abfd, sec);
30+ }
31 hdr_info->u.dwarf.table = FALSE;
32 if (sec_info)
33 free (sec_info);
34--
352.15.0
36
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch
new file mode 100644
index 00000000..c145a746
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0004-Fix-relaxation-of-assembler-resolved-references.patch
@@ -0,0 +1,78 @@
1From 0d5966951c379882b7557befaa229dc5def8dafe Mon Sep 17 00:00:00 2001
2From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
3Date: Mon, 28 Aug 2017 19:53:55 -0700
4Subject: [PATCH] Fix relaxation of assembler resolved references
5
6Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
7Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
8Upstream-Status: Pending
9---
10 bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++
11 gas/config/tc-microblaze.c | 1 +
12 2 files changed, 40 insertions(+)
13
14diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
15index 265773675c..c3dbead48d 100644
16--- a/bfd/elf32-microblaze.c
17+++ b/bfd/elf32-microblaze.c
18@@ -1901,6 +1901,45 @@ microblaze_elf_relax_section (bfd *abfd,
19 irelscanend = irelocs + o->reloc_count;
20 for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
21 {
22+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
23+ {
24+ unsigned int val;
25+
26+ isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
27+
28+ /* This was a PC-relative instruction that was completely resolved. */
29+ if (ocontents == NULL)
30+ {
31+ if (elf_section_data (o)->this_hdr.contents != NULL)
32+ ocontents = elf_section_data (o)->this_hdr.contents;
33+ else
34+ {
35+ /* We always cache the section contents.
36+ Perhaps, if info->keep_memory is FALSE, we
37+ should free them, if we are permitted to. */
38+
39+ if (o->rawsize == 0)
40+ o->rawsize = o->size;
41+ ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
42+ if (ocontents == NULL)
43+ goto error_return;
44+ if (!bfd_get_section_contents (abfd, o, ocontents,
45+ (file_ptr) 0,
46+ o->rawsize))
47+ goto error_return;
48+ elf_section_data (o)->this_hdr.contents = ocontents;
49+ }
50+ }
51+
52+ irelscan->r_addend -= calc_fixup (irelscan->r_addend
53+ + isym->st_value, sec);
54+ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
55+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
56+ irelscan->r_addend);
57+ }
58+ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
59+ fprintf(stderr, "Unhandled NONE 64\n");
60+ }
61 if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
62 {
63 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
64diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
65index d47793646b..1cfd441c19 100644
66--- a/gas/config/tc-microblaze.c
67+++ b/gas/config/tc-microblaze.c
68@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP,
69 else
70 fixP->fx_r_type = BFD_RELOC_NONE;
71 fixP->fx_addsy = section_symbol (absolute_section);
72+ fixP->fx_done = 0;
73 }
74 return;
75 }
76--
772.15.0
78
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
new file mode 100644
index 00000000..9eeb0b28
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch
@@ -0,0 +1,236 @@
1From ef876d5062148e8555353e5e72da87c3a47dea8f Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:53:56 -0700
4Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation
5
6Fixup debug_loc sections after linker relaxation Adds a new reloctype
7R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to
8the linker when the linker manages to fully resolve a local symbol
9reference.
10
11This is a workaround for design flaws in the assembler to
12linker interface with regards to linker relaxation.
13
14Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
15Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
16Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
17Upstream-Status: Pending
18---
19 bfd/bfd-in2.h | 9 +++++++--
20 bfd/elf32-microblaze.c | 42 +++++++++++++++++++++++++++++++++++-------
21 bfd/libbfd.h | 1 +
22 bfd/reloc.c | 6 ++++++
23 binutils/readelf.c | 4 ++++
24 gas/config/tc-microblaze.c | 5 ++++-
25 include/elf/microblaze.h | 1 +
26 7 files changed, 58 insertions(+), 10 deletions(-)
27
28diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
29index 1343780c8c..3456826f83 100644
30--- a/bfd/bfd-in2.h
31+++ b/bfd/bfd-in2.h
32@@ -5809,10 +5809,15 @@ value relative to the read-write small data area anchor */
33 expressions of the form "Symbol Op Symbol" */
34 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
35
36-/* This is a 64 bit reloc that stores the 32 bit pc relative
37+/* This is a 32 bit reloc that stores the 32 bit pc relative
38 value in two words (with an imm instruction). No relocation is
39 done here - only used for relaxing */
40- BFD_RELOC_MICROBLAZE_64_NONE,
41+ BFD_RELOC_MICROBLAZE_32_NONE,
42+
43+/* This is a 64 bit reloc that stores the 32 bit pc relative
44+ * +value in two words (with an imm instruction). No relocation is
45+ * +done here - only used for relaxing */
46+ BFD_RELOC_MICROBLAZE_64_NONE,
47
48 /* This is a 64 bit reloc that stores the 32 bit pc relative
49 value in two words (with an imm instruction). The relocation is
50diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
51index c3dbead48d..1d1f7e210a 100644
52--- a/bfd/elf32-microblaze.c
53+++ b/bfd/elf32-microblaze.c
54@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
55 0x0000ffff, /* Dest Mask. */
56 FALSE), /* PC relative offset? */
57
58+ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */
59+ 0, /* Rightshift. */
60+ 2, /* Size (0 = byte, 1 = short, 2 = long). */
61+ 32, /* Bitsize. */
62+ TRUE, /* PC_relative. */
63+ 0, /* Bitpos. */
64+ complain_overflow_bitfield, /* Complain on overflow. */
65+ NULL, /* Special Function. */
66+ "R_MICROBLAZE_32_NONE",/* Name. */
67+ FALSE, /* Partial Inplace. */
68+ 0, /* Source Mask. */
69+ 0, /* Dest Mask. */
70+ FALSE), /* PC relative offset? */
71+
72 /* This reloc does nothing. Used for relaxation. */
73 HOWTO (R_MICROBLAZE_64_NONE, /* Type. */
74 0, /* Rightshift. */
75@@ -532,6 +546,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
76 case BFD_RELOC_NONE:
77 microblaze_reloc = R_MICROBLAZE_NONE;
78 break;
79+ case BFD_RELOC_MICROBLAZE_32_NONE:
80+ microblaze_reloc = R_MICROBLAZE_32_NONE;
81+ break;
82 case BFD_RELOC_MICROBLAZE_64_NONE:
83 microblaze_reloc = R_MICROBLAZE_64_NONE;
84 break;
85@@ -1846,14 +1863,22 @@ microblaze_elf_relax_section (bfd *abfd,
86 }
87 break;
88 case R_MICROBLAZE_NONE:
89+ case R_MICROBLAZE_32_NONE:
90 {
91 /* This was a PC-relative instruction that was
92 completely resolved. */
93 int sfix, efix;
94+ unsigned int val;
95 bfd_vma target_address;
96 target_address = irel->r_addend + irel->r_offset;
97 sfix = calc_fixup (irel->r_offset, 0, sec);
98 efix = calc_fixup (target_address, 0, sec);
99+
100+ /* Validate the in-band val. */
101+ val = bfd_get_32 (abfd, contents + irel->r_offset);
102+ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
103+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
104+ }
105 irel->r_addend -= (efix - sfix);
106 /* Should use HOWTO. */
107 microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
108@@ -1901,12 +1926,16 @@ microblaze_elf_relax_section (bfd *abfd,
109 irelscanend = irelocs + o->reloc_count;
110 for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
111 {
112- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
113+ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
114 {
115 unsigned int val;
116
117 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
118
119+ /* hax: We only do the following fixup for debug location lists. */
120+ if (strcmp(".debug_loc", o->name))
121+ continue;
122+
123 /* This was a PC-relative instruction that was completely resolved. */
124 if (ocontents == NULL)
125 {
126@@ -1931,15 +1960,14 @@ microblaze_elf_relax_section (bfd *abfd,
127 }
128 }
129
130- irelscan->r_addend -= calc_fixup (irelscan->r_addend
131- + isym->st_value, sec);
132 val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
133+ if (val != irelscan->r_addend) {
134+ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
135+ }
136+ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
137 microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
138 irelscan->r_addend);
139 }
140- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
141- fprintf(stderr, "Unhandled NONE 64\n");
142- }
143 if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
144 {
145 isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
146@@ -1999,7 +2027,7 @@ microblaze_elf_relax_section (bfd *abfd,
147 elf_section_data (o)->this_hdr.contents = ocontents;
148 }
149 }
150- irelscan->r_addend -= calc_fixup (irel->r_addend
151+ irelscan->r_addend -= calc_fixup (irelscan->r_addend
152 + isym->st_value,
153 0,
154 sec);
155diff --git a/bfd/libbfd.h b/bfd/libbfd.h
156index ae9bf76814..2091286c7c 100644
157--- a/bfd/libbfd.h
158+++ b/bfd/libbfd.h
159@@ -2847,6 +2847,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
160 "BFD_RELOC_MICROBLAZE_32_ROSDA",
161 "BFD_RELOC_MICROBLAZE_32_RWSDA",
162 "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
163+ "BFD_RELOC_MICROBLAZE_32_NONE",
164 "BFD_RELOC_MICROBLAZE_64_NONE",
165 "BFD_RELOC_MICROBLAZE_64_GOTPC",
166 "BFD_RELOC_MICROBLAZE_64_GOT",
167diff --git a/bfd/reloc.c b/bfd/reloc.c
168index aa70fa5874..54d7f538ec 100644
169--- a/bfd/reloc.c
170+++ b/bfd/reloc.c
171@@ -6860,6 +6860,12 @@ ENUM
172 ENUMDOC
173 This is a 32 bit reloc for the microblaze to handle
174 expressions of the form "Symbol Op Symbol"
175+ENUM
176+ BFD_RELOC_MICROBLAZE_32_NONE
177+ENUMDOC
178+ This is a 32 bit reloc that stores the 32 bit pc relative
179+ value in two words (with an imm instruction). No relocation is
180+ done here - only used for relaxing
181 ENUM
182 BFD_RELOC_MICROBLAZE_64_NONE
183 ENUMDOC
184diff --git a/binutils/readelf.c b/binutils/readelf.c
185index b2f75c0048..8a3226eba9 100644
186--- a/binutils/readelf.c
187+++ b/binutils/readelf.c
188@@ -12488,6 +12488,10 @@ is_none_reloc (unsigned int reloc_type)
189 || reloc_type == 32 /* R_AVR_DIFF32. */);
190 case EM_METAG:
191 return reloc_type == 3; /* R_METAG_NONE. */
192+ case EM_MICROBLAZE:
193+ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */
194+ || reloc_type == 0 /* R_MICROBLAZE_NONE. */
195+ || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */
196 case EM_NDS32:
197 return (reloc_type == 0 /* R_XTENSA_NONE. */
198 || reloc_type == 204 /* R_NDS32_DIFF8. */
199diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
200index 1cfd441c19..e135547e62 100644
201--- a/gas/config/tc-microblaze.c
202+++ b/gas/config/tc-microblaze.c
203@@ -2179,7 +2179,9 @@ md_apply_fix (fixS * fixP,
204 /* This fixup has been resolved. Create a reloc in case the linker
205 moves code around due to relaxing. */
206 if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
207- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
208+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
209+ else if (fixP->fx_r_type == BFD_RELOC_32)
210+ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
211 else
212 fixP->fx_r_type = BFD_RELOC_NONE;
213 fixP->fx_addsy = section_symbol (absolute_section);
214@@ -2401,6 +2403,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
215 switch (fixp->fx_r_type)
216 {
217 case BFD_RELOC_NONE:
218+ case BFD_RELOC_MICROBLAZE_32_NONE:
219 case BFD_RELOC_MICROBLAZE_64_NONE:
220 case BFD_RELOC_32:
221 case BFD_RELOC_MICROBLAZE_32_LO:
222diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
223index ccb47404c5..abcaea561b 100644
224--- a/include/elf/microblaze.h
225+++ b/include/elf/microblaze.h
226@@ -58,6 +58,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
227 RELOC_NUMBER (R_MICROBLAZE_TLSDTPREL64, 27) /* TLS Offset Within TLS Block */
228 RELOC_NUMBER (R_MICROBLAZE_TLSGOTTPREL32, 28) /* TLS Offset From Thread Pointer */
229 RELOC_NUMBER (R_MICROBLAZE_TLSTPREL32, 29) /* TLS Offset From Thread Pointer */
230+ RELOC_NUMBER (R_MICROBLAZE_32_NONE, 30)
231
232 END_RELOC_NUMBERS (R_MICROBLAZE_max)
233
234--
2352.15.0
236
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
new file mode 100644
index 00000000..de458adb
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch
@@ -0,0 +1,37 @@
1From b55dddad1303aafe249e2ba0ddf20460f8f035f6 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:53:58 -0700
4Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation
5
6Fixed the problem related to the fixup/relocations TLSTPREL.
7When the fixup is applied the addend is not added at the correct offset
8of the instruction. The offset is hard coded considering its big endian
9and it fails for Little endian. This patch allows support for both
10big & little-endian compilers
11
12Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
13Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
14Upstream-Status: Pending
15---
16 bfd/elf32-microblaze.c | 4 ++--
17 1 file changed, 2 insertions(+), 2 deletions(-)
18
19diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
20index 1d1f7e210a..cc6e4b1fd9 100644
21--- a/bfd/elf32-microblaze.c
22+++ b/bfd/elf32-microblaze.c
23@@ -1417,9 +1417,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
24 relocation += addend;
25 relocation -= dtprel_base(info);
26 bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
27- contents + offset + 2);
28+ contents + offset + endian);
29 bfd_put_16 (input_bfd, relocation & 0xffff,
30- contents + offset + 2 + INST_WORD_SIZE);
31+ contents + offset + endian + INST_WORD_SIZE);
32 break;
33 case (int) R_MICROBLAZE_64_PCREL :
34 case (int) R_MICROBLAZE_64:
35--
362.15.0
37
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch
new file mode 100644
index 00000000..ad62345c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0007-Add-MicroBlaze-address-extension-instructions.patch
@@ -0,0 +1,106 @@
1From 82c8eacbceb51422d3da75ac30912f9dedc0e832 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:53:59 -0700
4Subject: [PATCH] Add MicroBlaze address extension instructions
5
6This patch adds the support of new instructions which are required
7for supporting Address extension feature.
8
92016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
10
11 * microblaze-opc.h (op_code_struct): Added new instructions
12 * microblaze-opcm.h (microblaze_instr): Added new instructions
13
14Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
15Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
16Upstream-Status: Pending
17---
18 opcodes/microblaze-opc.h | 13 ++++++++++++-
19 opcodes/microblaze-opcm.h | 10 +++++-----
20 2 files changed, 17 insertions(+), 6 deletions(-)
21
22diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
23index b33178145f..a64f8362da 100644
24--- a/opcodes/microblaze-opc.h
25+++ b/opcodes/microblaze-opc.h
26@@ -102,7 +102,7 @@
27 #define DELAY_SLOT 1
28 #define NO_DELAY_SLOT 0
29
30-#define MAX_OPCODES 291
31+#define MAX_OPCODES 299
32
33 struct op_code_struct
34 {
35@@ -178,8 +178,11 @@ struct op_code_struct
36 {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
37 {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
38 {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
39+ {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
40 {"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
41+ {"mtse", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
42 {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
43+ {"mfse", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
44 {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
45 {"brd", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
46 {"brld", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
47@@ -229,18 +232,24 @@ struct op_code_struct
48 {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
49 {"lbu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
50 {"lbur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
51+ {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
52 {"lhu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
53 {"lhur", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
54+ {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
55 {"lw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
56 {"lwr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
57 {"lwx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
58+ {"lwea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
59 {"sb", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
60 {"sbr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
61+ {"sbea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
62 {"sh", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
63 {"shr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
64+ {"shea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
65 {"sw", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
66 {"swr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
67 {"swx", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
68+ {"swea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
69 {"lbui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
70 {"lhui", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
71 {"lwi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
72@@ -405,6 +414,8 @@ struct op_code_struct
73 {"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
74 {"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
75 {"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
76+ {"hibernate", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 8. */
77+ {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */
78 {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
79 {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
80 {"", 0, 0, 0, 0, 0, 0, 0, 0},
81diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
82index 00dc131302..21a3dc8d76 100644
83--- a/opcodes/microblaze-opcm.h
84+++ b/opcodes/microblaze-opcm.h
85@@ -33,13 +33,13 @@ enum microblaze_instr
86 /* 'or/and/xor' are C++ keywords. */
87 microblaze_or, microblaze_and, microblaze_xor,
88 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
89- wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
90- brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
91- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
92+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
93+ mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
94+ bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
95 imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
96 brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
97- bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
98- shr, sw, swr, swx, lbui, lhui, lwi,
99+ bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
100+ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
101 sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
102 fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
103 fint, fsqrt,
104--
1052.15.0
106
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch
new file mode 100644
index 00000000..0bc01177
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0008-Add-new-MicroBlaze-bit-field-instructions.patch
@@ -0,0 +1,232 @@
1From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:54:01 -0700
4Subject: [PATCH] Add new MicroBlaze bit-field instructions
5
6This patches adds new bsefi and bsifi instructions. BSEFI- The
7instruction shall extract a bit field from a register and place it
8right-adjusted in the destination register. The other bits in the
9destination register shall be set to zero BSIFI- The instruction shall
10insert a right-adjusted bit field from a register at another position in
11the destination register. The rest of the bits in the destination
12register shall be unchanged
13
14Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
15Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
16Upstream-Status: Pending
17---
18 gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++-
19 opcodes/microblaze-dis.c | 16 +++++++++++
20 opcodes/microblaze-opc.h | 12 +++++++-
21 opcodes/microblaze-opcm.h | 6 +++-
22 4 files changed, 102 insertions(+), 3 deletions(-)
23
24diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
25index e135547e62..34cb80fac2 100644
26--- a/gas/config/tc-microblaze.c
27+++ b/gas/config/tc-microblaze.c
28@@ -909,7 +909,7 @@ md_assemble (char * str)
29 unsigned reg2;
30 unsigned reg3;
31 unsigned isize;
32- unsigned int immed, temp;
33+ unsigned int immed, immed2, temp;
34 expressionS exp;
35 char name[20];
36
37@@ -1164,7 +1164,76 @@ md_assemble (char * str)
38 inst |= (reg2 << RA_LOW) & RA_MASK;
39 inst |= (immed << IMM_LOW) & IMM5_MASK;
40 break;
41+ case INST_TYPE_RD_R1_IMM5_IMM5:
42+ if (strcmp (op_end, ""))
43+ op_end = parse_reg (op_end + 1, &reg1); /* Get rd. */
44+ else
45+ {
46+ as_fatal (_("Error in statement syntax"));
47+ reg1 = 0;
48+ }
49+ if (strcmp (op_end, ""))
50+ op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
51+ else
52+ {
53+ as_fatal (_("Error in statement syntax"));
54+ reg2 = 0;
55+ }
56+
57+ /* Check for spl registers. */
58+ if (check_spl_reg (&reg1))
59+ as_fatal (_("Cannot use special register with this instruction"));
60+ if (check_spl_reg (&reg2))
61+ as_fatal (_("Cannot use special register with this instruction"));
62
63+ /* Width immediate value. */
64+ if (strcmp (op_end, ""))
65+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
66+ else
67+ as_fatal (_("Error in statement syntax"));
68+ if (exp.X_op != O_constant)
69+ {
70+ as_warn (_("Symbol used as immediate width value for bit field instruction"));
71+ immed = 1;
72+ }
73+ else
74+ immed = exp.X_add_number;
75+ if (opcode->instr == bsefi && immed > 31)
76+ as_fatal (_("Width value must be less than 32"));
77+
78+ /* Shift immediate value. */
79+ if (strcmp (op_end, ""))
80+ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
81+ else
82+ as_fatal (_("Error in statement syntax"));
83+ if (exp.X_op != O_constant)
84+ {
85+ as_warn (_("Symbol used as immediate shift value for bit field instruction"));
86+ immed2 = 0;
87+ }
88+ else
89+ {
90+ output = frag_more (isize);
91+ immed2 = exp.X_add_number;
92+ }
93+ if (immed2 != (immed2 % 32))
94+ {
95+ as_warn (_("Shift value greater than 32. using <value %% 32>"));
96+ immed2 = immed2 % 32;
97+ }
98+
99+ /* Check combined value. */
100+ if (immed + immed2 > 32)
101+ as_fatal (_("Width value + shift value must not be greater than 32"));
102+
103+ inst |= (reg1 << RD_LOW) & RD_MASK;
104+ inst |= (reg2 << RA_LOW) & RA_MASK;
105+ if (opcode->instr == bsefi)
106+ inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
107+ else
108+ inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
109+ inst |= (immed2 << IMM_LOW) & IMM5_MASK;
110+ break;
111 case INST_TYPE_R1_R2:
112 if (strcmp (op_end, ""))
113 op_end = parse_reg (op_end + 1, &reg1); /* Get r1. */
114diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
115index 6a174b0eb9..80a47ad2fc 100644
116--- a/opcodes/microblaze-dis.c
117+++ b/opcodes/microblaze-dis.c
118@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr)
119 return(strdup(tmpstr));
120 }
121
122+static char *
123+get_field_imm5width (long instr)
124+{
125+ char tmpstr[25];
126+
127+ if (instr & 0x00004000)
128+ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
129+ else
130+ sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
131+ return (strdup (tmpstr));
132+}
133+
134 static char *
135 get_field_rfsl (long instr)
136 {
137@@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
138 /* For mbar 16 or sleep insn. */
139 case INST_TYPE_NONE:
140 break;
141+ /* For bit field insns. */
142+ case INST_TYPE_RD_R1_IMM5_IMM5:
143+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst));
144+ break;
145 /* For tuqula instruction */
146 case INST_TYPE_RD:
147 print_func (stream, "\t%s", get_field_rd (inst));
148diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
149index a64f8362da..afb34989d9 100644
150--- a/opcodes/microblaze-opc.h
151+++ b/opcodes/microblaze-opc.h
152@@ -59,6 +59,9 @@
153 /* For mbar. */
154 #define INST_TYPE_IMM5 20
155
156+/* For bsefi and bsifi */
157+#define INST_TYPE_RD_R1_IMM5_IMM5 21
158+
159 #define INST_TYPE_NONE 25
160
161
162@@ -89,7 +92,9 @@
163 #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
164 #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
165 #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
166+#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
167 #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
168+#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
169 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
170 #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
171 #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
172@@ -102,7 +107,7 @@
173 #define DELAY_SLOT 1
174 #define NO_DELAY_SLOT 0
175
176-#define MAX_OPCODES 299
177+#define MAX_OPCODES 301
178
179 struct op_code_struct
180 {
181@@ -159,6 +164,8 @@ struct op_code_struct
182 {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
183 {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
184 {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
185+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
186+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
187 {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
188 {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
189 {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
190@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
191 #define MIN_IMM5 ((int) 0x00000000)
192 #define MAX_IMM5 ((int) 0x0000001f)
193
194+#define MIN_IMM_WIDTH ((int) 0x00000001)
195+#define MAX_IMM_WIDTH ((int) 0x00000020)
196+
197 #endif /* MICROBLAZE_OPC */
198
199diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
200index 21a3dc8d76..dd6be7f65c 100644
201--- a/opcodes/microblaze-opcm.h
202+++ b/opcodes/microblaze-opcm.h
203@@ -29,7 +29,7 @@ enum microblaze_instr
204 addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
205 mulh, mulhu, mulhsu,swapb,swaph,
206 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
207- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
208+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
209 /* 'or/and/xor' are C++ keywords. */
210 microblaze_or, microblaze_and, microblaze_xor,
211 andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
212@@ -129,6 +129,7 @@ enum microblaze_instr_type
213 #define RB_LOW 11 /* Low bit for RB. */
214 #define IMM_LOW 0 /* Low bit for immediate. */
215 #define IMM_MBAR 21 /* low bit for mbar instruction. */
216+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
217
218 #define RD_MASK 0x03E00000
219 #define RA_MASK 0x001F0000
220@@ -141,6 +142,9 @@ enum microblaze_instr_type
221 /* Imm mask for mbar. */
222 #define IMM5_MBAR_MASK 0x03E00000
223
224+/* Imm mask for extract/insert width. */
225+#define IMM5_WIDTH_MASK 0x000007C0
226+
227 /* FSL imm mask for get, put instructions. */
228 #define RFSL_MASK 0x000000F
229
230--
2312.15.0
232
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch
new file mode 100644
index 00000000..0eef0f0d
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0009-Fixing-MicroBlaze-IMM-bug.patch
@@ -0,0 +1,31 @@
1From cff770a6f73b82db3259e9577e13b08a1bcd14e8 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Mon, 28 Aug 2017 19:54:02 -0700
4Subject: [PATCH] Fixing MicroBlaze IMM bug
5
6Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now.
7
8Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 bfd/elf32-microblaze.c | 3 +--
13 1 file changed, 1 insertion(+), 2 deletions(-)
14
15diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
16index cc6e4b1fd9..6fc475cbcd 100644
17--- a/bfd/elf32-microblaze.c
18+++ b/bfd/elf32-microblaze.c
19@@ -1803,8 +1803,7 @@ microblaze_elf_relax_section (bfd *abfd,
20 else
21 symval += irel->r_addend;
22
23- if ((symval & 0xffff8000) == 0
24- || (symval & 0xffff8000) == 0xffff8000)
25+ if ((symval & 0xffff8000) == 0)
26 {
27 /* We can delete this instruction. */
28 sec->relax[sec->relax_count].addr = irel->r_offset;
29--
302.15.0
31
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
new file mode 100644
index 00000000..e08bedc7
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch
@@ -0,0 +1,36 @@
1From 4449e15997a576761433cc76daf3635742acec62 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 15 Nov 2017 17:45:35 -0800
4Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long
5 0u
6
7Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
8Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
9Upstream-Status: Pending
10---
11 gas/expr.c | 9 +++++++++
12 1 file changed, 9 insertions(+)
13
14diff --git a/gas/expr.c b/gas/expr.c
15index 6fc707b8a5..a54b1f4b76 100644
16--- a/gas/expr.c
17+++ b/gas/expr.c
18@@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
19 break;
20 }
21 }
22+ if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
23+ {
24+ input_line_pointer--;
25+
26+ integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
27+ ? 0 : 10,
28+ expressionP);
29+ break;
30+ }
31 c = *input_line_pointer;
32 switch (c)
33 {
34--
352.15.0
36
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
new file mode 100644
index 00000000..fe940905
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0011-Fixing-MicroBlaze-constant-range-check-issue.patch
@@ -0,0 +1,30 @@
1From 4286d83d6dc58131982247f7017b738595329771 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Wed, 15 Nov 2017 17:45:34 -0800
4Subject: [PATCH] Fixing MicroBlaze constant range check issue
5
6Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
7
8Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 gas/config/tc-microblaze.c | 2 +-
13 1 file changed, 1 insertion(+), 1 deletion(-)
14
15diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
16index 34cb80fac2..7e1233945a 100644
17--- a/gas/config/tc-microblaze.c
18+++ b/gas/config/tc-microblaze.c
19@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
20 if ((e->X_add_number >> 31) == 1)
21 e->X_add_number |= -((addressT) (1U << 31));
22
23- if (e->X_add_number < min || e->X_add_number > max)
24+ if ((int)e->X_add_number < min || (int)e->X_add_number > max)
25 {
26 as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
27 (long) min, (long) max, (long) e->X_add_number);
28--
292.15.0
30
diff --git a/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
new file mode 100644
index 00000000..1028c50a
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.29/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch
@@ -0,0 +1,38 @@
1From a3ce2a329f583a66732b6a435c1bd76a83732dd8 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Sun, 5 Nov 2017 22:17:39 +1000
4Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions
5
6As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have
7bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support
8bit field insert/extract operations. For the bslli/bsrai/bsrli
9instructions these bits must be 0, as such update the opcode mask so
10that the bslli/bsrai/bsrli instructions do not also match the bsefi and
11bsifi instructions.
12
13Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
14Upstream-Status: Pending
15---
16 opcodes/microblaze-opc.h | 6 +++---
17 1 file changed, 3 insertions(+), 3 deletions(-)
18
19diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
20index afb34989d9..68db818d69 100644
21--- a/opcodes/microblaze-opc.h
22+++ b/opcodes/microblaze-opc.h
23@@ -161,9 +161,9 @@ struct op_code_struct
24 {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
25 {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
26 {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
27- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
28- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
29- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
30+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
31+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
32+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
33 {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
34 {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
35 {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
36--
372.15.0
38
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-11-15 11:38:35 +0000