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author | Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> | 2020-06-05 10:27:02 -0700 |
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committer | Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> | 2020-08-11 23:47:26 -0700 |
commit | 034a12cf2ab08a0a9e724ba644667c82556ff09a (patch) | |
tree | eaedda6f78f8bb94e40149cba8ef022d087377be /meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch | |
parent | 1c4692b7e478de2f75541fe26ed7d019e24c889b (diff) | |
download | meta-xilinx-034a12cf2ab08a0a9e724ba644667c82556ff09a.tar.gz |
gcc-9*: Upgrade gcc from 9.2->10.1
Upgrade microblaze recipes to use gcc-10 instead of gcc-9. This patch only
ensures the builds are not broken It doesnt validate the gcc-microblaze
functionality
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch')
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch new file mode 100644 index 00000000..c3822d06 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch | |||
@@ -0,0 +1,58 @@ | |||
1 | From 791d65feae4f3cab47833579bc6f523e54194cbd Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Tue, 17 Jan 2017 17:11:04 +0530 | ||
4 | Subject: [PATCH 22/63] [Patch,microblaze]: Inline Expansion of fsqrt builtin. | ||
5 | The changes are made in the patch for the inline expansion of the fsqrt | ||
6 | builtin with fqrt instruction. The sqrt math function takes double as | ||
7 | argument and return double as argument. The pattern is selected while | ||
8 | expanding the unary op through expand_unop which passes DFmode and the DFmode | ||
9 | pattern was not there returning zero. Thus the sqrt math function is not | ||
10 | inlined and expanded. The pattern with DFmode argument is added. Also the | ||
11 | source and destination argument is not same the DF through two different | ||
12 | consecutive registers with lower 32 bit is the argument passed to sqrt and | ||
13 | the higher 32 bit is zero. If the source and destinations are different the | ||
14 | DFmode 64 bits registers is not set properly giving the problem in runtime. | ||
15 | Such changes are taken care in the implementation of the pattern for DFmode | ||
16 | for inline expansion of the sqrt. | ||
17 | |||
18 | ChangeLog: | ||
19 | 2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> | ||
20 | Nagaraju Mekala <nmekala@xilinx.com> | ||
21 | |||
22 | * config/microblaze/microblaze.md (sqrtdf2): New | ||
23 | pattern. | ||
24 | |||
25 | Signed-off-by:Ajit Agarwal ajitkum@xilinx.com | ||
26 | Nagaraju Mekala nmekala@xilinx.com | ||
27 | --- | ||
28 | gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ | ||
29 | 1 file changed, 14 insertions(+) | ||
30 | |||
31 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
32 | index 3c80760..1fb5582 100644 | ||
33 | --- a/gcc/config/microblaze/microblaze.md | ||
34 | +++ b/gcc/config/microblaze/microblaze.md | ||
35 | @@ -451,6 +451,20 @@ | ||
36 | (set_attr "mode" "SF") | ||
37 | (set_attr "length" "4")]) | ||
38 | |||
39 | +(define_insn "sqrtdf2" | ||
40 | + [(set (match_operand:DF 0 "register_operand" "=d") | ||
41 | + (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] | ||
42 | + "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" | ||
43 | + { | ||
44 | + if (REGNO (operands[0]) == REGNO (operands[1])) | ||
45 | + return "fsqrt\t%0,%1"; | ||
46 | + else | ||
47 | + return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; | ||
48 | + } | ||
49 | + [(set_attr "type" "fsqrt") | ||
50 | + (set_attr "mode" "SF") | ||
51 | + (set_attr "length" "4")]) | ||
52 | + | ||
53 | (define_insn "fix_truncsfsi2" | ||
54 | [(set (match_operand:SI 0 "register_operand" "=d") | ||
55 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] | ||
56 | -- | ||
57 | 2.7.4 | ||
58 | |||