diff options
author | Mark Hatle <mark.hatle@xilinx.com> | 2021-12-15 13:52:16 -0800 |
---|---|---|
committer | Mark Hatle <mark.hatle@xilinx.com> | 2022-01-14 15:37:02 -0800 |
commit | f900c6a0c8908e370689235230094308ec419cf9 (patch) | |
tree | bd9ca83e452c263c7a421b826086048cf8130f34 /meta-xilinx-bsp/recipes-bsp | |
parent | aaddcc3f785404da04af9ea3d005f2f520b4ec9e (diff) | |
download | meta-xilinx-f900c6a0c8908e370689235230094308ec419cf9.tar.gz |
Initial restructure/split of meta-xilinx-bsp
Create a new meta-xilinx-core, move core functionality to the core, keeping
board specific files in the bsp layer.
zynqmp-generic changed from require <board> to include, so if meta-xilinx-bsp
is not available it will not fail.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
Diffstat (limited to 'meta-xilinx-bsp/recipes-bsp')
44 files changed, 0 insertions, 16162 deletions
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc deleted file mode 100644 index 281ce765..00000000 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ /dev/null | |||
@@ -1,103 +0,0 @@ | |||
1 | DESCRIPTION = "ARM Trusted Firmware" | ||
2 | |||
3 | LICENSE = "BSD" | ||
4 | LIC_FILES_CHKSUM ?= "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" | ||
5 | |||
6 | PROVIDES = "virtual/arm-trusted-firmware" | ||
7 | |||
8 | inherit deploy | ||
9 | |||
10 | DEPENDS += "u-boot-mkimage-native" | ||
11 | |||
12 | S = "${WORKDIR}/git" | ||
13 | B = "${WORKDIR}/build" | ||
14 | |||
15 | SYSROOT_DIRS += "/boot" | ||
16 | |||
17 | XILINX_RELEASE_VERSION ?= "" | ||
18 | ATF_VERSION ?= "2.2" | ||
19 | ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" | ||
20 | PV = "${ATF_VERSION}${ATF_VERSION_EXTENSION}+git${SRCPV}" | ||
21 | |||
22 | BRANCH ?= "" | ||
23 | REPO ?= "git://github.com/Xilinx/arm-trusted-firmware.git;protocol=https" | ||
24 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | ||
25 | SRC_URI = "${REPO};${BRANCHARG}" | ||
26 | |||
27 | inherit image-artifact-names | ||
28 | |||
29 | ATF_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}" | ||
30 | |||
31 | # Specify a default in case boardvariant isn't available | ||
32 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
33 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
34 | |||
35 | COMPATIBLE_MACHINE ?= "^$" | ||
36 | COMPATIBLE_MACHINE:zynqmp = ".*" | ||
37 | COMPATIBLE_MACHINE:versal = ".*" | ||
38 | |||
39 | PLATFORM:zynqmp = "zynqmp" | ||
40 | PLATFORM:versal = "versal" | ||
41 | |||
42 | # requires CROSS_COMPILE set by hand as there is no configure script | ||
43 | export CROSS_COMPILE="${TARGET_PREFIX}" | ||
44 | |||
45 | # Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application | ||
46 | CFLAGS[unexport] = "1" | ||
47 | LDFLAGS[unexport] = "1" | ||
48 | AS[unexport] = "1" | ||
49 | LD[unexport] = "1" | ||
50 | |||
51 | ATF_CONSOLE ?= "" | ||
52 | ATF_CONSOLE:zynqmp = "cadence" | ||
53 | ATF_CONSOLE:versal ?= "pl011" | ||
54 | |||
55 | DEBUG_ATF ?= "" | ||
56 | DEBUG_ATF:versal ?= "1" | ||
57 | |||
58 | EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" | ||
59 | EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" | ||
60 | EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}" | ||
61 | |||
62 | OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" | ||
63 | |||
64 | ATF_MEM_BASE ?= "0x1000" | ||
65 | ATF_MEM_SIZE ?= "0x7ffff" | ||
66 | |||
67 | EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" | ||
68 | EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" | ||
69 | |||
70 | EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" | ||
71 | EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" | ||
72 | EXTRA_OEMAKE:append_vc-p-a2197-00-versal =" VERSAL_PLATFORM=silicon" | ||
73 | |||
74 | do_configure() { | ||
75 | oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} | ||
76 | } | ||
77 | |||
78 | do_compile() { | ||
79 | oe_runmake -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} RESET_TO_BL31=1 bl31 | ||
80 | } | ||
81 | |||
82 | do_install() { | ||
83 | install -d ${D}/boot | ||
84 | install -Dm 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${D}/boot/${PN}.elf | ||
85 | } | ||
86 | |||
87 | do_deploy() { | ||
88 | install -d ${DEPLOYDIR} | ||
89 | install -m 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${DEPLOYDIR}/${ATF_BASE_NAME}.elf | ||
90 | ln -sf ${ATF_BASE_NAME}.elf ${DEPLOYDIR}/${PN}.elf | ||
91 | install -m 0644 ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.bin | ||
92 | ln -sf ${ATF_BASE_NAME}.bin ${DEPLOYDIR}/${PN}.bin | ||
93 | |||
94 | # Get the entry point address from the elf. | ||
95 | BL31_BASE_ADDR=$(${READELF} -h ${OUTPUT_DIR}/bl31/bl31.elf | egrep -m 1 -i "entry point.*?0x" | sed -r 's/.*?(0x.*?)/\1/g') | ||
96 | mkimage -A arm64 -O arm-trusted-firmware -T kernel -C none \ | ||
97 | -a $BL31_BASE_ADDR -e $BL31_BASE_ADDR \ | ||
98 | -d ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.ub | ||
99 | ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/${PN}.ub | ||
100 | ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub | ||
101 | } | ||
102 | addtask deploy before do_build after do_compile | ||
103 | FILES:${PN} += "/boot/${PN}.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb deleted file mode 100644 index f69ed50c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | ATF_VERSION = "2.4" | ||
2 | SRCREV = "9188496b9b23a665782bb3d2c2b9e3b29b7fb4e2" | ||
3 | BRANCH = "xlnx_rebase_v2.4" | ||
4 | LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031" | ||
5 | |||
6 | |||
7 | include arm-trusted-firmware.inc | ||
8 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/base-pdi/base-pdi_1.0.bb b/meta-xilinx-bsp/recipes-bsp/base-pdi/base-pdi_1.0.bb deleted file mode 100644 index 4e940642..00000000 --- a/meta-xilinx-bsp/recipes-bsp/base-pdi/base-pdi_1.0.bb +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | DESCRIPTION = "Recipe to deploy base pdi" | ||
2 | |||
3 | LICENSE = "CLOSED" | ||
4 | |||
5 | PROVIDES = "virtual/base-pdi" | ||
6 | |||
7 | COMPATIBLE_MACHINE = "^$" | ||
8 | COMPATIBLE_MACHINE:versal = "versal" | ||
9 | |||
10 | PACKAGE_ARCH ?= "${MACHINE_ARCH}" | ||
11 | |||
12 | do_compile[noexec] = "1" | ||
13 | |||
14 | PDI_PATH ?= "" | ||
15 | SRC_URI += "${@['file://'+d.getVar('PDI_PATH'),''][d.getVar('PDI_PATH') == '']}" | ||
16 | |||
17 | python() { | ||
18 | if d.getVar('PDI_SKIP_CHECK') != "1" and not d.getVar('PDI_PATH'): | ||
19 | raise bb.parse.SkipRecipe("PDI_PATH is not configured with the base design pdi") | ||
20 | } | ||
21 | |||
22 | #base install will just take from PDI_PATH variable | ||
23 | #will need to bbappend to this in meta-xilinx-tools to use xsct to extract pdi from xsa and install | ||
24 | do_install() { | ||
25 | |||
26 | if [ -f ${WORKDIR}/${PDI_PATH} ];then | ||
27 | install -d ${D}/boot | ||
28 | install -m 0644 ${WORKDIR}/${PDI_PATH} ${D}/boot/base-design.pdi | ||
29 | else | ||
30 | bbfatal "No base pdi supplied" | ||
31 | fi | ||
32 | } | ||
33 | SYSROOT_DIRS += "/boot" | ||
34 | |||
35 | FILES:${PN} += "/boot/*" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-versal.inc b/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-versal.inc deleted file mode 100644 index a9c58aa2..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-versal.inc +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | #Extra args for versal | ||
2 | BOOTGEN_EXTRA_ARGS += "-dump bh" | ||
3 | |||
4 | # specify BIF common attribute for FSBL | ||
5 | BIF_COMMON_ATTR ?= "" | ||
6 | |||
7 | # specify BIF partition attributes required for BOOT.bin | ||
8 | BIF_PARTITION_ATTR ?= "base-pdi plmfw psmfw device-tree arm-trusted-firmware u-boot-xlnx" | ||
9 | |||
10 | # specify BIF partition attributes for base-pdi | ||
11 | BIF_PARTITION_ATTR[base-pdi] ?= "type=bootimage" | ||
12 | BIF_PARTITION_IMAGE[base-pdi] ?= "${RECIPE_SYSROOT}/boot/base-design.pdi" | ||
13 | |||
14 | # specify BIF partition attributes for plmfw | ||
15 | BIF_PARTITION_ATTR[plmfw] ?= "type=bootloader" | ||
16 | BIF_PARTITION_IMAGE[plmfw] ?= "${RECIPE_SYSROOT}/boot/plmfw.elf" | ||
17 | |||
18 | # specify BIF partition attributes for psmfw | ||
19 | BIF_PARTITION_ATTR[psmfw] ?= "core=psm" | ||
20 | BIF_PARTITION_IMAGE[psmfw] ?= "${RECIPE_SYSROOT}/boot/psmfw.elf" | ||
21 | |||
22 | # specify BIF partition attributes for device-tree | ||
23 | BIF_PARTITION_ATTR[device-tree] ?= "type=raw, load=0x1000" | ||
24 | BIF_PARTITION_IMAGE[device-tree] ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb" | ||
25 | BIF_PARTITION_ID[device-tree] ?= "0x1c000000" | ||
26 | |||
27 | # specify BIF partition attributes for u-boot | ||
28 | BIF_PARTITION_ATTR[u-boot-xlnx] ?= "core=a72-0, exception_level = el-2" | ||
29 | BIF_PARTITION_IMAGE[u-boot-xlnx] ?= "${RECIPE_SYSROOT}/boot/u-boot.elf" | ||
30 | BIF_PARTITION_ID[u-boot-xlnx] ?= "0x1c000000" | ||
31 | |||
32 | # specify BIF partition attributes for arm-trusted-firmware | ||
33 | BIF_PARTITION_ATTR[arm-trusted-firmware] ?= "core=a72-0, exception_level = el-3, trustzone" | ||
34 | BIF_PARTITION_IMAGE[arm-trusted-firmware] ?= "${RECIPE_SYSROOT}/boot/arm-trusted-firmware.elf" | ||
35 | BIF_PARTITION_ID[arm-trusted-firmware] ?= "0x1c000000" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynq.inc b/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynq.inc deleted file mode 100644 index b8d75c4f..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynq.inc +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | #specify BIF partition attributes required for BOOT.bin | ||
2 | BIF_PARTITION_ATTR ?= "fsbl bitstream u-boot" | ||
3 | |||
4 | #specify BIF partition attributes for FSBL | ||
5 | #bootloader is FSBL. Location where FSBL binary is present and dependency to build FSBL | ||
6 | BIF_PARTITION_ATTR[fsbl] ?= "bootloader" | ||
7 | BIF_PARTITION_IMAGE[fsbl] ?= "${DEPLOY_DIR_IMAGE}/fsbl-${MACHINE}.elf" | ||
8 | BIF_PARTITION_DEPENDS[fsbl] ?= "virtual/fsbl:do_deploy" | ||
9 | |||
10 | #specify BIF partition attributes for u-boot | ||
11 | #Location where u-boot binary is present | ||
12 | BIF_PARTITION_IMAGE[u-boot] ?= "${DEPLOY_DIR_IMAGE}/u-boot-${MACHINE}.elf" | ||
13 | BIF_PARTITION_DEPENDS[u-boot] ?= "virtual/bootloader:do_deploy" | ||
14 | |||
15 | # enable bitstream-Note this is not enabled by default (missing in BIF_PARTITION_ATTR) | ||
16 | BIF_PARTITION_IMAGE[bitstream] ?= "${DEPLOY_DIR_IMAGE}/download-${MACHINE}.bit" | ||
17 | BIF_PARTITION_DEPENDS[bitstream] ?= "virtual/bitstream:do_deploy" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc b/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc deleted file mode 100644 index 4eb404c1..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | # specify BIF common attribute for FSBL | ||
2 | BIF_COMMON_ATTR ?= "" | ||
3 | |||
4 | # specify BIF partition attributes required for BOOT.bin | ||
5 | BIF_PARTITION_ATTR = "fsbl pmufw arm-trusted-firmware device-tree u-boot-xlnx" | ||
6 | |||
7 | # specify BIF partition attributes for FSBL | ||
8 | # bootloader is FSBL. Location where FSBL binary is present and dependency to build FSBL | ||
9 | BIF_PARTITION_ATTR[fsbl] ?= "bootloader, destination_cpu=a53-0" | ||
10 | BIF_PARTITION_IMAGE[fsbl] ?= "${RECIPE_SYSROOT}/boot/fsbl.elf" | ||
11 | |||
12 | # specify BIF partition attributes for PMU Firmware | ||
13 | # destination cpu for PMU. Location where PMU binary is present and dependency to build PMU Firmware | ||
14 | BIF_PARTITION_ATTR[pmufw] ?= "destination_cpu=pmu" | ||
15 | BIF_PARTITION_IMAGE[pmufw] ?= "${RECIPE_SYSROOT}/boot/pmufw.elf" | ||
16 | |||
17 | # specify BIF partition attributes for ATF | ||
18 | # destination cpu for ATF, security levels. Location where ATF binary is present (dependency is not required as ATF is always built for ZU+, see zcu102-zynqmp.conf) | ||
19 | BIF_PARTITION_ATTR[arm-trusted-firmware] ?= "destination_cpu=a53-0,exception_level=el-3,trustzone" | ||
20 | BIF_PARTITION_IMAGE[arm-trusted-firmware] ?= "${RECIPE_SYSROOT}/boot/arm-trusted-firmware.elf" | ||
21 | |||
22 | # specify BIF partition attributes for u-boot | ||
23 | # destination cpu for u-boot, security levels. Location where u-boot binary is present (dependency is not required as u-boot is always built for ZU+, see zcu102-zynqmp.conf) | ||
24 | BIF_PARTITION_ATTR[u-boot-xlnx] ?= "destination_cpu=a53-0,exception_level=el-2" | ||
25 | BIF_PARTITION_IMAGE[u-boot-xlnx] ?= "${RECIPE_SYSROOT}/boot/u-boot.elf" | ||
26 | |||
27 | # specify BIF partition attributes for dtb | ||
28 | BIF_PARTITION_ATTR[device-tree] ?= "destination_cpu=a53-0,load=0x100000" | ||
29 | BIF_PARTITION_IMAGE[device-tree] ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb" | ||
30 | |||
31 | # enable bitstream-Note this is not enabled by default (missing in BIF_PARTITION_ATTR) | ||
32 | BIF_PARTITION_ATTR[bitstream] ?= "destination_device=pl" | ||
33 | BIF_PARTITION_IMAGE[bitstream] ?= "${DEPLOY_DIR_IMAGE}/download-${MACHINE}.bit" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb deleted file mode 100644 index 532da106..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb +++ /dev/null | |||
@@ -1,171 +0,0 @@ | |||
1 | SUMMARY = "Generates boot.bin using bootgen tool" | ||
2 | DESCRIPTION = "Manages task dependencies and creation of boot.bin. Use the \ | ||
3 | BIF_PARTITION_xyz global variables and flags to determine what makes it into \ | ||
4 | the image." | ||
5 | |||
6 | LICENSE = "BSD" | ||
7 | |||
8 | include machine-xilinx-${SOC_FAMILY}.inc | ||
9 | |||
10 | inherit deploy | ||
11 | |||
12 | PROVIDES = "virtual/boot-bin" | ||
13 | |||
14 | DEPENDS += "bootgen-native" | ||
15 | |||
16 | # There is no bitstream recipe, so really depend on virtual/bitstream | ||
17 | DEPENDS += "${@(d.getVar('BIF_PARTITION_ATTR') or "").replace('bitstream', 'virtual/bitstream')}" | ||
18 | |||
19 | # Specify a default in case boardvariant isn't available | ||
20 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
21 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
22 | |||
23 | BIF_FILE_PATH ?= "${B}/bootgen.bif" | ||
24 | |||
25 | LICENSE = "MIT" | ||
26 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" | ||
27 | |||
28 | SRC_URI += "${@('file://' + d.getVar("BIF_FILE_PATH")) if d.getVar("BIF_FILE_PATH") != (d.getVar('B') + '/bootgen.bif') else ''}" | ||
29 | |||
30 | BOOTGEN_EXTRA_ARGS ?= "" | ||
31 | |||
32 | do_patch[noexec] = "1" | ||
33 | |||
34 | def create_bif(config, attrflags, attrimage, ids, common_attr, biffd, d): | ||
35 | import re, os | ||
36 | for cfg in config: | ||
37 | if cfg not in attrflags and common_attr: | ||
38 | error_msg = "%s: invalid ATTRIBUTE" % (cfg) | ||
39 | bb.error("BIF attribute Error: %s " % (error_msg)) | ||
40 | else: | ||
41 | if common_attr: | ||
42 | cfgval = d.expand(attrflags[cfg]).split(',') | ||
43 | cfgstr = "\t [%s] %s\n" % (cfg,', '.join(cfgval)) | ||
44 | else: | ||
45 | if cfg not in attrimage: | ||
46 | error_msg = "%s: invalid or missing elf or image" % (cfg) | ||
47 | bb.error("BIF atrribute Error: %s " % (error_msg)) | ||
48 | imagestr = d.expand(attrimage[cfg]) | ||
49 | if os.stat(imagestr).st_size == 0: | ||
50 | bb.warn("Empty file %s, excluding from bif file" %(imagestr)) | ||
51 | continue | ||
52 | if cfg in attrflags: | ||
53 | cfgval = d.expand(attrflags[cfg]).split(',') | ||
54 | cfgstr = "\t [%s] %s\n" % (', '.join(cfgval), imagestr) | ||
55 | else: | ||
56 | cfgstr = "\t %s\n" % (imagestr) | ||
57 | biffd.write(cfgstr) | ||
58 | |||
59 | return | ||
60 | |||
61 | def create_versal_bif(config, attrflags, attrimage, ids, common_attr, biffd, d): | ||
62 | import re, os | ||
63 | id_dict = {} | ||
64 | for cfg in config: | ||
65 | if cfg not in attrflags and common_attr: | ||
66 | error_msg = "%s: invalid ATTRIBUTE" % (cfg) | ||
67 | bb.error("BIF attribute Error: %s " % (error_msg)) | ||
68 | else: | ||
69 | if common_attr: | ||
70 | cfgval = d.expand(attrflags[cfg]).split(',') | ||
71 | #TODO: Does common attribute syntax change in similar way for versal? | ||
72 | cfgstr = "\t { %s %s }\n" % (cfg,', '.join(cfgval)) | ||
73 | biffd.write(cfgstr) | ||
74 | else: | ||
75 | if cfg not in attrimage: | ||
76 | error_msg = "%s: invalid or missing elf or image" % (cfg) | ||
77 | bb.error("BIF atrribute Error: %s " % (error_msg)) | ||
78 | imagestr = d.expand(attrimage[cfg]) | ||
79 | if os.stat(imagestr).st_size == 0: | ||
80 | bb.warn("Empty file %s, excluding from bif file" %(imagestr)) | ||
81 | continue | ||
82 | if cfg in attrflags: | ||
83 | cfgval = d.expand(attrflags[cfg]).split(',') | ||
84 | try: | ||
85 | id = d.expand(ids[cfg]) | ||
86 | except: | ||
87 | id = '0' | ||
88 | cfgstr = "\t { %s, file=%s }\n" % (', '.join(cfgval), imagestr) | ||
89 | try: | ||
90 | id_dict[id] += cfgstr | ||
91 | except: | ||
92 | id_dict[id] = cfgstr | ||
93 | else: | ||
94 | cfgstr = "\t %s\n" % (imagestr) | ||
95 | for id, string in id_dict.items(): | ||
96 | biffd.write("\timage {\n") | ||
97 | if id != '0': | ||
98 | biffd.write("\t id = " + id + "\n") | ||
99 | biffd.write(string) | ||
100 | biffd.write("\t}\n") | ||
101 | return | ||
102 | |||
103 | python do_configure() { | ||
104 | fp = d.getVar("BIF_FILE_PATH") | ||
105 | if fp == (d.getVar('B') + '/bootgen.bif'): | ||
106 | arch = d.getVar("SOC_FAMILY") | ||
107 | biffunc = {'versal':create_versal_bif, 'zynq':create_bif, 'zynqmp':create_bif} | ||
108 | biffd = open(fp, 'w') | ||
109 | biffd.write("the_ROM_image:\n") | ||
110 | biffd.write("{\n") | ||
111 | |||
112 | bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split() | ||
113 | if bifattr: | ||
114 | attrflags = d.getVarFlags("BIF_COMMON_ATTR") or {} | ||
115 | biffunc[arch](bifattr, attrflags,'','', 1, biffd, d) | ||
116 | |||
117 | bifpartition = (d.getVar("BIF_PARTITION_ATTR") or "").split() | ||
118 | if bifpartition: | ||
119 | attrflags = d.getVarFlags("BIF_PARTITION_ATTR") or {} | ||
120 | attrimage = d.getVarFlags("BIF_PARTITION_IMAGE") or {} | ||
121 | ids = d.getVarFlags("BIF_PARTITION_ID") or {} | ||
122 | biffunc[arch](bifpartition, attrflags, attrimage, ids, 0, biffd, d) | ||
123 | |||
124 | biffd.write("}") | ||
125 | biffd.close() | ||
126 | else: | ||
127 | print("Using custom BIF file: " + d.getVar("BIF_FILE_PATH") ) | ||
128 | } | ||
129 | |||
130 | do_configure[vardeps] += "BIF_PARTITION_ATTR BIF_PARTITION_IMAGE BIF_COMMON_ATTR" | ||
131 | |||
132 | do_compile() { | ||
133 | cd ${WORKDIR} | ||
134 | rm -f ${B}/BOOT.bin | ||
135 | if [ "${BIF_FILE_PATH}" != "${B}/bootgen.bif" ];then | ||
136 | BIF_FILE_PATH="${WORKDIR}${BIF_FILE_PATH}" | ||
137 | fi | ||
138 | bootgen -image ${BIF_FILE_PATH} -arch ${SOC_FAMILY} ${BOOTGEN_EXTRA_ARGS} -w -o ${B}/BOOT.bin | ||
139 | if [ ! -e ${B}/BOOT.bin ]; then | ||
140 | bbfatal "bootgen failed. See log" | ||
141 | fi | ||
142 | } | ||
143 | |||
144 | do_install() { | ||
145 | install -d ${D}/boot | ||
146 | install -m 0644 ${B}/BOOT.bin ${D}/boot/BOOT.bin | ||
147 | } | ||
148 | |||
149 | inherit image-artifact-names | ||
150 | |||
151 | QEMUQSPI_BASE_NAME ?= "QEMU_qspi-${MACHINE}${IMAGE_VERSION_SUFFIX}" | ||
152 | |||
153 | BOOTBIN_BASE_NAME ?= "BOOT-${MACHINE}${IMAGE_VERSION_SUFFIX}" | ||
154 | |||
155 | do_deploy() { | ||
156 | install -d ${DEPLOYDIR} | ||
157 | install -m 0644 ${B}/BOOT.bin ${DEPLOYDIR}/${BOOTBIN_BASE_NAME}.bin | ||
158 | ln -sf ${BOOTBIN_BASE_NAME}.bin ${DEPLOYDIR}/BOOT-${MACHINE}.bin | ||
159 | ln -sf ${BOOTBIN_BASE_NAME}.bin ${DEPLOYDIR}/boot.bin | ||
160 | } | ||
161 | |||
162 | do_deploy:append:versal () { | ||
163 | |||
164 | install -m 0644 ${B}/BOOT_bh.bin ${DEPLOYDIR}/${BOOTBIN_BASE_NAME}_bh.bin | ||
165 | ln -sf ${BOOTBIN_BASE_NAME}_bh.bin ${DEPLOYDIR}/BOOT-${MACHINE}_bh.bin | ||
166 | } | ||
167 | |||
168 | FILES:${PN} += "/boot/BOOT.bin" | ||
169 | SYSROOT_DIRS += "/boot" | ||
170 | |||
171 | addtask do_deploy before do_build after do_compile | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-mcs_1.0.bb b/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-mcs_1.0.bb deleted file mode 100644 index a729c07b..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootbin/xilinx-mcs_1.0.bb +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | SUMMARY = "Generates boot.mcs using vivado" | ||
2 | DESCRIPTION = "Manages task dependencies and creation of boot.mcs for microblaze" | ||
3 | |||
4 | LICENSE = "BSD" | ||
5 | |||
6 | PROVIDES = "virtual/boot-bin" | ||
7 | |||
8 | DEPENDS = "bitstream-microblaze" | ||
9 | |||
10 | PACKAGE_ARCH = "${MACHINE_ARCH}" | ||
11 | |||
12 | COMPATIBLE_MACHINE ?= "^$" | ||
13 | COMPATIBLE_MACHINE:microblaze = ".*" | ||
14 | |||
15 | inherit deploy image-artifact-names | ||
16 | |||
17 | do_fetch[noexec] = "1" | ||
18 | do_unpack[noexec] = "1" | ||
19 | do_patch[noexec] = "1" | ||
20 | |||
21 | PROC ??= "kc705_i/microblaze_0" | ||
22 | PROC_kc705 = "kc705_i/microblaze_0" | ||
23 | |||
24 | FLASH_SIZE ??= "0x80" | ||
25 | FLASH_INTERFACE ??= "BPIx16" | ||
26 | MB_OUT_FORMAT ??= "mcs" | ||
27 | BOOT_EXT = "${@d.getVar('MB_OUT_FORMAT').lower()}" | ||
28 | |||
29 | BITSTREAM_FILE ?= "${RECIPE_SYSROOT}/boot/bitstream/download.bit" | ||
30 | B = "${WORKDIR}/build" | ||
31 | WR_CFGMEM_MISC ?= "-loadbit \" up 0 ${BITSTREAM_FILE}\"" | ||
32 | |||
33 | do_check_for_vivado() { | ||
34 | bbnote "Checking Vivado install path" | ||
35 | which "vivado" 2>/dev/null || { | ||
36 | bbfatal "Vivado not found! Please add \"INHERIT += \"vivado\"\" to your local.conf" | ||
37 | } | ||
38 | } | ||
39 | |||
40 | addtask do_check_for_vivado before do_configure | ||
41 | |||
42 | do_configure() { | ||
43 | echo " write_cfgmem -force -format ${MB_OUT_FORMAT} -size ${FLASH_SIZE} -interface ${FLASH_INTERFACE} ${WR_CFGMEM_MISC} ${B}/BOOT.${BOOT_EXT} " > ${B}/write_cfgmem_boot_mcs.tcl | ||
44 | if [ ! -e ${B}/write_cfgmem_boot_mcs.tcl ]; then | ||
45 | bbfatal "write_cfgmem_boot_mcs.tcl creation failed. See log for details" | ||
46 | fi | ||
47 | } | ||
48 | |||
49 | |||
50 | do_compile() { | ||
51 | vivado -log "${B}/cfgmem_mcs.log" -jou "${B}/cfgmem_mcs.jou" -mode batch -s ${B}/write_cfgmem_boot_mcs.tcl | ||
52 | if [ ! -e ${B}/BOOT.${BOOT_EXT} ]; then | ||
53 | bbfatal "BOOT.${BOOT_EXT} failed. See log" | ||
54 | fi | ||
55 | } | ||
56 | |||
57 | do_install() { | ||
58 | : | ||
59 | } | ||
60 | |||
61 | BOOT_BASE_NAME ?= "BOOT-${MACHINE}${IMAGE_VERSION_SUFFIX}" | ||
62 | |||
63 | do_deploy() { | ||
64 | #install BOOT.mcs | ||
65 | if [ -e ${B}/BOOT.${BOOT_EXT} ]; then | ||
66 | install -Dm 0644 ${B}/BOOT.${BOOT_EXT} ${DEPLOYDIR}/${BOOT_BASE_NAME}.${BOOT_EXT} | ||
67 | ln -sf ${BOOT_BASE_NAME}.${BOOT_EXT} ${DEPLOYDIR}/BOOT-${MACHINE}.${BOOT_EXT} | ||
68 | fi | ||
69 | } | ||
70 | addtask do_deploy before do_build after do_compile | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb deleted file mode 100644 index 236da302..00000000 --- a/meta-xilinx-bsp/recipes-bsp/bootgen/bootgen_1.0.bb +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | SUMMARY = "Building and installing bootgen" | ||
2 | DESCRIPTION = "Building and installing bootgen, a Xilinx tool that lets you stitch binary files together and generate device boot images" | ||
3 | |||
4 | LICENSE = "Apache-2.0" | ||
5 | LIC_FILES_CHKSUM = "file://LICENSE;md5=d526b6d0807bf263b97da1da876f39b1" | ||
6 | |||
7 | S = "${WORKDIR}/git" | ||
8 | |||
9 | DEPENDS += "openssl" | ||
10 | RDEPENDS:${PN} += "openssl" | ||
11 | |||
12 | REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https" | ||
13 | BRANCH ?= "xlnx_rel_v2021.2" | ||
14 | SRCREV = "5b6fe16a2bfd7ced4d90b70b0ba6fbf325e81e97" | ||
15 | |||
16 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | ||
17 | SRC_URI = "${REPO};${BRANCHARG}" | ||
18 | |||
19 | EXTRA_OEMAKE += 'CROSS_COMPILER="${CXX}" -C ${S}' | ||
20 | CXXFLAGS:append = " -std=c++0x" | ||
21 | |||
22 | TARGET_CC_ARCH += "${LDFLAGS}" | ||
23 | |||
24 | do_install() { | ||
25 | install -d ${D}${bindir} | ||
26 | install -Dm 0755 ${S}/bootgen ${D}${bindir} | ||
27 | } | ||
28 | |||
29 | FILES:${PN} = "${bindir}/bootgen" | ||
30 | |||
31 | BBCLASSEXTEND = "native nativesdk" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/cdo/extract-cdo_1.0.bb b/meta-xilinx-bsp/recipes-bsp/cdo/extract-cdo_1.0.bb deleted file mode 100644 index 37c284ad..00000000 --- a/meta-xilinx-bsp/recipes-bsp/cdo/extract-cdo_1.0.bb +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | DESCRIPTION = "Recipe to copy external cdos" | ||
2 | |||
3 | LICENSE = "CLOSED" | ||
4 | |||
5 | inherit deploy | ||
6 | |||
7 | PROVIDES = "virtual/cdo" | ||
8 | |||
9 | DEPENDS += "bootgen-native" | ||
10 | |||
11 | do_compile[depends] += "virtual/boot-bin:do_deploy" | ||
12 | |||
13 | COMPATIBLE_MACHINE = "^$" | ||
14 | COMPATIBLE_MACHINE:versal = "versal" | ||
15 | |||
16 | PACKAGE_ARCH ?= "${MACHINE_ARCH}" | ||
17 | |||
18 | B = "${WORKDIR}/build" | ||
19 | |||
20 | BOOTGEN_CMD ?= "bootgen" | ||
21 | BOOTGEN_ARGS ?= "-arch versal" | ||
22 | BOOTGEN_OUTFILE ?= "${DEPLOY_DIR_IMAGE}/boot.bin" | ||
23 | |||
24 | #The following line creates the pmc_cdo.bin file at the same dir as the boot.bin which is DEPLOY_DIR_IMAGE | ||
25 | do_compile() { | ||
26 | ${BOOTGEN_CMD} ${BOOTGEN_ARGS} -dump ${BOOTGEN_OUTFILE} pmc_cdo | ||
27 | } | ||
28 | |||
29 | do_deploy() { | ||
30 | install -d ${DEPLOYDIR}/CDO | ||
31 | install -m 0644 ${DEPLOY_DIR_IMAGE}/pmc_cdo.bin ${DEPLOYDIR}/CDO/pmc_cdo.bin | ||
32 | } | ||
33 | |||
34 | addtask do_deploy after do_install | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb deleted file mode 100644 index c73e5fb1..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb +++ /dev/null | |||
@@ -1,69 +0,0 @@ | |||
1 | SUMMARY = "Xilinx BSP device trees" | ||
2 | DESCRIPTION = "Xilinx BSP device trees from within layer." | ||
3 | SECTION = "bsp" | ||
4 | |||
5 | # the device trees from within the layer are licensed as MIT, kernel includes are GPL | ||
6 | LICENSE = "MIT & GPLv2" | ||
7 | LIC_FILES_CHKSUM = " \ | ||
8 | file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \ | ||
9 | file://${COMMON_LICENSE_DIR}/GPL-2.0-or-later;md5=fed54355545ffd980b814dab4a3b312c \ | ||
10 | " | ||
11 | |||
12 | inherit devicetree image-artifact-names | ||
13 | |||
14 | #this way of going through SRC_URI is better but if dts is including other dtsis, need to add all of them to SRC_URI.. | ||
15 | #SRC_URI += "file://${SYSTEM_DTFILE}" | ||
16 | #DT_FILES_PATH = "${@d.getVar('WORKDIR')+'/'+os.path.dirname(d.getVar('SYSTEM_DTFILE'))}" | ||
17 | |||
18 | DT_FILES_PATH = "${@os.path.dirname(d.getVar('SYSTEM_DTFILE')) if d.getVar('SYSTEM_DTFILE') else d.getVar('S')}" | ||
19 | |||
20 | COMPATIBLE_MACHINE:zynqmp = ".*" | ||
21 | COMPATIBLE_MACHINE:versal = ".*" | ||
22 | |||
23 | # Device-trees are inherently board specific | ||
24 | BOARD_ARCH ??= "${MACHINE_ARCH}" | ||
25 | PACKAGE_ARCH = "${BOARD_ARCH}" | ||
26 | |||
27 | DEPENDS += "python3-dtc-native" | ||
28 | |||
29 | PROVIDES = "virtual/dtb" | ||
30 | |||
31 | # common zynq include | ||
32 | SRC_URI:append:zynq = " file://zynq-7000-qspi-dummy.dtsi" | ||
33 | |||
34 | # device tree sources for the various machines | ||
35 | COMPATIBLE_MACHINE_picozed-zynq7 = ".*" | ||
36 | SRC_URI:append_picozed-zynq7 = " file://picozed-zynq7.dts" | ||
37 | |||
38 | COMPATIBLE_MACHINE_qemu-zynq7 = ".*" | ||
39 | SRC_URI:append_qemu-zynq7 = " file://qemu-zynq7.dts" | ||
40 | |||
41 | COMPATIBLE_MACHINE_zybo-linux-bd-zynq7 = ".*" | ||
42 | SRC_URI:append_zybo-linux-bd-zynq7 = " \ | ||
43 | file://zybo-linux-bd-zynq7.dts \ | ||
44 | file://pcw.dtsi \ | ||
45 | file://pl.dtsi \ | ||
46 | " | ||
47 | |||
48 | COMPATIBLE_MACHINE_kc705-microblazeel = ".*" | ||
49 | SRC_URI:append_kc705-microblazeel = " \ | ||
50 | file://kc705-microblazeel.dts \ | ||
51 | file://pl.dtsi \ | ||
52 | file://system-conf.dtsi \ | ||
53 | " | ||
54 | |||
55 | DTB_FILE_NAME = "${@os.path.basename(d.getVar('SYSTEM_DTFILE')).replace('.dts', '.dtb') if d.getVar('SYSTEM_DTFILE') else ''}" | ||
56 | DTB_BASE_NAME ?= "${MACHINE}-system${IMAGE_VERSION_SUFFIX}" | ||
57 | |||
58 | devicetree_do_deploy:append() { | ||
59 | if [ -n "${DTB_FILE_NAME}" ]; then | ||
60 | if [ -e "${DEPLOYDIR}/devicetree/${DTB_FILE_NAME}" ]; then | ||
61 | # We need the output to be system.dtb for WIC setup to match XSCT flow | ||
62 | ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/${DTB_BASE_NAME}.dtb | ||
63 | ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/${MACHINE}-system.dtb | ||
64 | ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/system.dtb | ||
65 | else | ||
66 | bberror "Expected filename ${DTB_FILE_NAME} doesn't exist in ${DEPLOYDIR}/devicetree" | ||
67 | fi | ||
68 | fi | ||
69 | } | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts deleted file mode 100644 index 45e488c1..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "pl.dtsi" | ||
3 | /include/ "system-conf.dtsi" | ||
4 | / { | ||
5 | hard-reset-gpios = <&reset_gpio 0 1>; | ||
6 | aliases { | ||
7 | ethernet0 = &axi_ethernet; | ||
8 | i2c0 = &iic_main; | ||
9 | serial0 = &rs232_uart; | ||
10 | }; | ||
11 | memory { | ||
12 | device_type = "memory"; | ||
13 | reg = <0x80000000 0x40000000>; | ||
14 | }; | ||
15 | }; | ||
16 | |||
17 | &iic_main { | ||
18 | i2cswitch@74 { | ||
19 | compatible = "nxp,pca9548"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <0>; | ||
22 | reg = <0x74>; | ||
23 | i2c@0 { | ||
24 | #address-cells = <1>; | ||
25 | #size-cells = <0>; | ||
26 | reg = <0>; | ||
27 | si570: clock-generator@5d { | ||
28 | #clock-cells = <0>; | ||
29 | compatible = "silabs,si570"; | ||
30 | temperature-stability = <50>; | ||
31 | reg = <0x5d>; | ||
32 | factory-fout = <156250000>; | ||
33 | clock-frequency = <148500000>; | ||
34 | }; | ||
35 | }; | ||
36 | i2c@3 { | ||
37 | #address-cells = <1>; | ||
38 | #size-cells = <0>; | ||
39 | reg = <3>; | ||
40 | eeprom@54 { | ||
41 | compatible = "at,24c08"; | ||
42 | reg = <0x54>; | ||
43 | }; | ||
44 | }; | ||
45 | }; | ||
46 | }; | ||
47 | |||
48 | &axi_ethernet { | ||
49 | phy-handle = <&phy0>; | ||
50 | axi_ethernet_mdio: mdio { | ||
51 | phy0: phy@7 { | ||
52 | device_type = "ethernet-phy"; | ||
53 | reg = <7>; | ||
54 | }; | ||
55 | }; | ||
56 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi deleted file mode 100644 index 43bc2ab7..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi +++ /dev/null | |||
@@ -1,445 +0,0 @@ | |||
1 | / { | ||
2 | #address-cells = <1>; | ||
3 | #size-cells = <1>; | ||
4 | compatible = "xlnx,microblaze"; | ||
5 | model = "Xilinx MicroBlaze"; | ||
6 | cpus { | ||
7 | #address-cells = <1>; | ||
8 | #cpus = <1>; | ||
9 | #size-cells = <0>; | ||
10 | microblaze_0: cpu@0 { | ||
11 | bus-handle = <&amba_pl>; | ||
12 | clock-frequency = <200000000>; | ||
13 | clocks = <&clk_cpu>; | ||
14 | compatible = "xlnx,microblaze-10.0"; | ||
15 | d-cache-baseaddr = <0x0000000080000000>; | ||
16 | d-cache-highaddr = <0x00000000bfffffff>; | ||
17 | d-cache-line-size = <0x20>; | ||
18 | d-cache-size = <0x4000>; | ||
19 | device_type = "cpu"; | ||
20 | i-cache-baseaddr = <0x0000000080000000>; | ||
21 | i-cache-highaddr = <0x00000000bfffffff>; | ||
22 | i-cache-line-size = <0x10>; | ||
23 | i-cache-size = <0x4000>; | ||
24 | interrupt-handle = <µblaze_0_axi_intc>; | ||
25 | model = "microblaze,10.0"; | ||
26 | timebase-frequency = <200000000>; | ||
27 | xlnx,addr-size = <0x20>; | ||
28 | xlnx,addr-tag-bits = <0x10>; | ||
29 | xlnx,allow-dcache-wr = <0x1>; | ||
30 | xlnx,allow-icache-wr = <0x1>; | ||
31 | xlnx,area-optimized = <0x0>; | ||
32 | xlnx,async-interrupt = <0x1>; | ||
33 | xlnx,async-wakeup = <0x3>; | ||
34 | xlnx,avoid-primitives = <0x0>; | ||
35 | xlnx,base-vectors = <0x0000000000000000>; | ||
36 | xlnx,branch-target-cache-size = <0x0>; | ||
37 | xlnx,cache-byte-size = <0x4000>; | ||
38 | xlnx,d-axi = <0x1>; | ||
39 | xlnx,d-lmb = <0x1>; | ||
40 | xlnx,d-lmb-mon = <0x0>; | ||
41 | xlnx,daddr-size = <0x20>; | ||
42 | xlnx,data-size = <0x20>; | ||
43 | xlnx,dc-axi-mon = <0x0>; | ||
44 | xlnx,dcache-addr-tag = <0x10>; | ||
45 | xlnx,dcache-always-used = <0x1>; | ||
46 | xlnx,dcache-byte-size = <0x4000>; | ||
47 | xlnx,dcache-data-width = <0x0>; | ||
48 | xlnx,dcache-force-tag-lutram = <0x0>; | ||
49 | xlnx,dcache-line-len = <0x8>; | ||
50 | xlnx,dcache-use-writeback = <0x0>; | ||
51 | xlnx,dcache-victims = <0x0>; | ||
52 | xlnx,debug-counter-width = <0x20>; | ||
53 | xlnx,debug-enabled = <0x1>; | ||
54 | xlnx,debug-event-counters = <0x5>; | ||
55 | xlnx,debug-external-trace = <0x0>; | ||
56 | xlnx,debug-interface = <0x0>; | ||
57 | xlnx,debug-latency-counters = <0x1>; | ||
58 | xlnx,debug-profile-size = <0x0>; | ||
59 | xlnx,debug-trace-async-reset = <0x0>; | ||
60 | xlnx,debug-trace-size = <0x2000>; | ||
61 | xlnx,div-zero-exception = <0x1>; | ||
62 | xlnx,dp-axi-mon = <0x0>; | ||
63 | xlnx,dynamic-bus-sizing = <0x0>; | ||
64 | xlnx,ecc-use-ce-exception = <0x0>; | ||
65 | xlnx,edge-is-positive = <0x1>; | ||
66 | xlnx,enable-discrete-ports = <0x0>; | ||
67 | xlnx,endianness = <0x1>; | ||
68 | xlnx,fault-tolerant = <0x0>; | ||
69 | xlnx,fpu-exception = <0x0>; | ||
70 | xlnx,freq = <0xbebc200>; | ||
71 | xlnx,fsl-exception = <0x0>; | ||
72 | xlnx,fsl-links = <0x0>; | ||
73 | xlnx,i-axi = <0x0>; | ||
74 | xlnx,i-lmb = <0x1>; | ||
75 | xlnx,i-lmb-mon = <0x0>; | ||
76 | xlnx,iaddr-size = <0x20>; | ||
77 | xlnx,ic-axi-mon = <0x0>; | ||
78 | xlnx,icache-always-used = <0x1>; | ||
79 | xlnx,icache-data-width = <0x0>; | ||
80 | xlnx,icache-force-tag-lutram = <0x0>; | ||
81 | xlnx,icache-line-len = <0x4>; | ||
82 | xlnx,icache-streams = <0x1>; | ||
83 | xlnx,icache-victims = <0x8>; | ||
84 | xlnx,ill-opcode-exception = <0x1>; | ||
85 | xlnx,imprecise-exceptions = <0x0>; | ||
86 | xlnx,instr-size = <0x20>; | ||
87 | xlnx,interconnect = <0x2>; | ||
88 | xlnx,interrupt-is-edge = <0x0>; | ||
89 | xlnx,interrupt-mon = <0x0>; | ||
90 | xlnx,ip-axi-mon = <0x0>; | ||
91 | xlnx,lockstep-master = <0x0>; | ||
92 | xlnx,lockstep-select = <0x0>; | ||
93 | xlnx,lockstep-slave = <0x0>; | ||
94 | xlnx,mmu-dtlb-size = <0x4>; | ||
95 | xlnx,mmu-itlb-size = <0x2>; | ||
96 | xlnx,mmu-privileged-instr = <0x0>; | ||
97 | xlnx,mmu-tlb-access = <0x3>; | ||
98 | xlnx,mmu-zones = <0x2>; | ||
99 | xlnx,num-sync-ff-clk = <0x2>; | ||
100 | xlnx,num-sync-ff-clk-debug = <0x2>; | ||
101 | xlnx,num-sync-ff-clk-irq = <0x1>; | ||
102 | xlnx,num-sync-ff-dbg-clk = <0x1>; | ||
103 | xlnx,num-sync-ff-dbg-trace-clk = <0x2>; | ||
104 | xlnx,number-of-pc-brk = <0x1>; | ||
105 | xlnx,number-of-rd-addr-brk = <0x0>; | ||
106 | xlnx,number-of-wr-addr-brk = <0x0>; | ||
107 | xlnx,opcode-0x0-illegal = <0x1>; | ||
108 | xlnx,optimization = <0x0>; | ||
109 | xlnx,pc-width = <0x20>; | ||
110 | xlnx,piaddr-size = <0x20>; | ||
111 | xlnx,pvr = <0x2>; | ||
112 | xlnx,pvr-user1 = <0x00>; | ||
113 | xlnx,pvr-user2 = <0x00000000>; | ||
114 | xlnx,reset-msr = <0x00000000>; | ||
115 | xlnx,reset-msr-bip = <0x0>; | ||
116 | xlnx,reset-msr-dce = <0x0>; | ||
117 | xlnx,reset-msr-ee = <0x0>; | ||
118 | xlnx,reset-msr-eip = <0x0>; | ||
119 | xlnx,reset-msr-ice = <0x0>; | ||
120 | xlnx,reset-msr-ie = <0x0>; | ||
121 | xlnx,sco = <0x0>; | ||
122 | xlnx,trace = <0x0>; | ||
123 | xlnx,unaligned-exceptions = <0x1>; | ||
124 | xlnx,use-barrel = <0x1>; | ||
125 | xlnx,use-branch-target-cache = <0x0>; | ||
126 | xlnx,use-config-reset = <0x0>; | ||
127 | xlnx,use-dcache = <0x1>; | ||
128 | xlnx,use-div = <0x1>; | ||
129 | xlnx,use-ext-brk = <0x0>; | ||
130 | xlnx,use-ext-nm-brk = <0x0>; | ||
131 | xlnx,use-extended-fsl-instr = <0x0>; | ||
132 | xlnx,use-fpu = <0x0>; | ||
133 | xlnx,use-hw-mul = <0x2>; | ||
134 | xlnx,use-icache = <0x1>; | ||
135 | xlnx,use-interrupt = <0x2>; | ||
136 | xlnx,use-mmu = <0x3>; | ||
137 | xlnx,use-msr-instr = <0x1>; | ||
138 | xlnx,use-non-secure = <0x0>; | ||
139 | xlnx,use-pcmp-instr = <0x1>; | ||
140 | xlnx,use-reorder-instr = <0x1>; | ||
141 | xlnx,use-stack-protection = <0x0>; | ||
142 | }; | ||
143 | }; | ||
144 | clocks { | ||
145 | #address-cells = <1>; | ||
146 | #size-cells = <0>; | ||
147 | clk_cpu: clk_cpu@0 { | ||
148 | #clock-cells = <0>; | ||
149 | clock-frequency = <200000000>; | ||
150 | clock-output-names = "clk_cpu"; | ||
151 | compatible = "fixed-clock"; | ||
152 | reg = <0>; | ||
153 | }; | ||
154 | clk_bus_0: clk_bus_0@1 { | ||
155 | #clock-cells = <0>; | ||
156 | clock-frequency = <200000000>; | ||
157 | clock-output-names = "clk_bus_0"; | ||
158 | compatible = "fixed-clock"; | ||
159 | reg = <1>; | ||
160 | }; | ||
161 | }; | ||
162 | amba_pl: amba_pl { | ||
163 | #address-cells = <1>; | ||
164 | #size-cells = <1>; | ||
165 | compatible = "simple-bus"; | ||
166 | ranges ; | ||
167 | axi_ethernet: ethernet@40c00000 { | ||
168 | axistream-connected = <&axi_ethernet_dma>; | ||
169 | axistream-control-connected = <&axi_ethernet_dma>; | ||
170 | clock-frequency = <100000000>; | ||
171 | compatible = "xlnx,axi-ethernet-1.00.a"; | ||
172 | device_type = "network"; | ||
173 | interrupt-parent = <µblaze_0_axi_intc>; | ||
174 | interrupts = <4 2>; | ||
175 | phy-mode = "gmii"; | ||
176 | reg = <0x40c00000 0x40000>; | ||
177 | xlnx = <0x0>; | ||
178 | xlnx,axiliteclkrate = <0x0>; | ||
179 | xlnx,axisclkrate = <0x0>; | ||
180 | xlnx,clockselection = <0x0>; | ||
181 | xlnx,enableasyncsgmii = <0x0>; | ||
182 | xlnx,gt-type = <0x0>; | ||
183 | xlnx,gtinex = <0x0>; | ||
184 | xlnx,gtlocation = <0x0>; | ||
185 | xlnx,gtrefclksrc = <0x0>; | ||
186 | xlnx,include-dre ; | ||
187 | xlnx,instantiatebitslice0 = <0x0>; | ||
188 | xlnx,phy-type = <0x1>; | ||
189 | xlnx,phyaddr = <0x1>; | ||
190 | xlnx,rable = <0x0>; | ||
191 | xlnx,rxcsum = <0x0>; | ||
192 | xlnx,rxlane0-placement = <0x0>; | ||
193 | xlnx,rxlane1-placement = <0x0>; | ||
194 | xlnx,rxmem = <0x1000>; | ||
195 | xlnx,rxnibblebitslice0used = <0x0>; | ||
196 | xlnx,tx-in-upper-nibble = <0x1>; | ||
197 | xlnx,txcsum = <0x0>; | ||
198 | xlnx,txlane0-placement = <0x0>; | ||
199 | xlnx,txlane1-placement = <0x0>; | ||
200 | axi_ethernet_mdio: mdio { | ||
201 | #address-cells = <1>; | ||
202 | #size-cells = <0>; | ||
203 | }; | ||
204 | }; | ||
205 | axi_ethernet_dma: dma@41e00000 { | ||
206 | #dma-cells = <1>; | ||
207 | axistream-connected = <&axi_ethernet>; | ||
208 | axistream-control-connected = <&axi_ethernet>; | ||
209 | clock-frequency = <200000000>; | ||
210 | clock-names = "s_axi_lite_aclk"; | ||
211 | clocks = <&clk_bus_0>; | ||
212 | compatible = "xlnx,eth-dma"; | ||
213 | interrupt-parent = <µblaze_0_axi_intc>; | ||
214 | interrupts = <3 2 2 2>; | ||
215 | reg = <0x41e00000 0x10000>; | ||
216 | xlnx,include-dre ; | ||
217 | }; | ||
218 | axi_timer_0: timer@41c00000 { | ||
219 | clock-frequency = <200000000>; | ||
220 | clocks = <&clk_bus_0>; | ||
221 | compatible = "xlnx,xps-timer-1.00.a"; | ||
222 | interrupt-parent = <µblaze_0_axi_intc>; | ||
223 | interrupts = <5 2>; | ||
224 | reg = <0x41c00000 0x10000>; | ||
225 | xlnx,count-width = <0x20>; | ||
226 | xlnx,gen0-assert = <0x1>; | ||
227 | xlnx,gen1-assert = <0x1>; | ||
228 | xlnx,one-timer-only = <0x0>; | ||
229 | xlnx,trig0-assert = <0x1>; | ||
230 | xlnx,trig1-assert = <0x1>; | ||
231 | }; | ||
232 | calib_complete_gpio: gpio@40010000 { | ||
233 | #gpio-cells = <2>; | ||
234 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
235 | gpio-controller ; | ||
236 | reg = <0x40010000 0x10000>; | ||
237 | xlnx,all-inputs = <0x1>; | ||
238 | xlnx,all-inputs-2 = <0x0>; | ||
239 | xlnx,all-outputs = <0x0>; | ||
240 | xlnx,all-outputs-2 = <0x0>; | ||
241 | xlnx,dout-default = <0x00000000>; | ||
242 | xlnx,dout-default-2 = <0x00000000>; | ||
243 | xlnx,gpio-width = <0x1>; | ||
244 | xlnx,gpio2-width = <0x20>; | ||
245 | xlnx,interrupt-present = <0x0>; | ||
246 | xlnx,is-dual = <0x0>; | ||
247 | xlnx,tri-default = <0xFFFFFFFF>; | ||
248 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
249 | }; | ||
250 | dip_switches_4bits: gpio@40020000 { | ||
251 | #gpio-cells = <2>; | ||
252 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
253 | gpio-controller ; | ||
254 | reg = <0x40020000 0x10000>; | ||
255 | xlnx,all-inputs = <0x1>; | ||
256 | xlnx,all-inputs-2 = <0x0>; | ||
257 | xlnx,all-outputs = <0x0>; | ||
258 | xlnx,all-outputs-2 = <0x0>; | ||
259 | xlnx,dout-default = <0x00000000>; | ||
260 | xlnx,dout-default-2 = <0x00000000>; | ||
261 | xlnx,gpio-width = <0x4>; | ||
262 | xlnx,gpio2-width = <0x20>; | ||
263 | xlnx,interrupt-present = <0x0>; | ||
264 | xlnx,is-dual = <0x0>; | ||
265 | xlnx,tri-default = <0xFFFFFFFF>; | ||
266 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
267 | }; | ||
268 | iic_main: i2c@40800000 { | ||
269 | #address-cells = <1>; | ||
270 | #size-cells = <0>; | ||
271 | clock-frequency = <200000000>; | ||
272 | clocks = <&clk_bus_0>; | ||
273 | compatible = "xlnx,xps-iic-2.00.a"; | ||
274 | interrupt-parent = <µblaze_0_axi_intc>; | ||
275 | interrupts = <1 2>; | ||
276 | reg = <0x40800000 0x10000>; | ||
277 | }; | ||
278 | led_8bits: gpio@40030000 { | ||
279 | #gpio-cells = <2>; | ||
280 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
281 | gpio-controller ; | ||
282 | reg = <0x40030000 0x10000>; | ||
283 | xlnx,all-inputs = <0x0>; | ||
284 | xlnx,all-inputs-2 = <0x0>; | ||
285 | xlnx,all-outputs = <0x1>; | ||
286 | xlnx,all-outputs-2 = <0x0>; | ||
287 | xlnx,dout-default = <0x00000000>; | ||
288 | xlnx,dout-default-2 = <0x00000000>; | ||
289 | xlnx,gpio-width = <0x8>; | ||
290 | xlnx,gpio2-width = <0x20>; | ||
291 | xlnx,interrupt-present = <0x0>; | ||
292 | xlnx,is-dual = <0x0>; | ||
293 | xlnx,tri-default = <0xFFFFFFFF>; | ||
294 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
295 | }; | ||
296 | linear_flash: flash@60000000 { | ||
297 | bank-width = <2>; | ||
298 | compatible = "cfi-flash"; | ||
299 | reg = <0x60000000 0x8000000>; | ||
300 | xlnx,axi-clk-period-ps = <0x1388>; | ||
301 | xlnx,include-datawidth-matching-0 = <0x1>; | ||
302 | xlnx,include-datawidth-matching-1 = <0x1>; | ||
303 | xlnx,include-datawidth-matching-2 = <0x1>; | ||
304 | xlnx,include-datawidth-matching-3 = <0x1>; | ||
305 | xlnx,include-negedge-ioregs = <0x0>; | ||
306 | xlnx,lflash-period-ps = <0x1388>; | ||
307 | xlnx,linear-flash-sync-burst = <0x0>; | ||
308 | xlnx,max-mem-width = <0x10>; | ||
309 | xlnx,mem-a-lsb = <0x0>; | ||
310 | xlnx,mem-a-msb = <0x1f>; | ||
311 | xlnx,mem0-type = <0x2>; | ||
312 | xlnx,mem0-width = <0x10>; | ||
313 | xlnx,mem1-type = <0x0>; | ||
314 | xlnx,mem1-width = <0x10>; | ||
315 | xlnx,mem2-type = <0x0>; | ||
316 | xlnx,mem2-width = <0x10>; | ||
317 | xlnx,mem3-type = <0x0>; | ||
318 | xlnx,mem3-width = <0x10>; | ||
319 | xlnx,num-banks-mem = <0x1>; | ||
320 | xlnx,page-size = <0x10>; | ||
321 | xlnx,parity-type-mem-0 = <0x0>; | ||
322 | xlnx,parity-type-mem-1 = <0x0>; | ||
323 | xlnx,parity-type-mem-2 = <0x0>; | ||
324 | xlnx,parity-type-mem-3 = <0x0>; | ||
325 | xlnx,port-diff = <0x0>; | ||
326 | xlnx,s-axi-en-reg = <0x0>; | ||
327 | xlnx,s-axi-mem-addr-width = <0x20>; | ||
328 | xlnx,s-axi-mem-data-width = <0x20>; | ||
329 | xlnx,s-axi-mem-id-width = <0x1>; | ||
330 | xlnx,s-axi-reg-addr-width = <0x5>; | ||
331 | xlnx,s-axi-reg-data-width = <0x20>; | ||
332 | xlnx,synch-pipedelay-0 = <0x1>; | ||
333 | xlnx,synch-pipedelay-1 = <0x1>; | ||
334 | xlnx,synch-pipedelay-2 = <0x1>; | ||
335 | xlnx,synch-pipedelay-3 = <0x1>; | ||
336 | xlnx,tavdv-ps-mem-0 = <0x1fbd0>; | ||
337 | xlnx,tavdv-ps-mem-1 = <0x3a98>; | ||
338 | xlnx,tavdv-ps-mem-2 = <0x3a98>; | ||
339 | xlnx,tavdv-ps-mem-3 = <0x3a98>; | ||
340 | xlnx,tcedv-ps-mem-0 = <0x1fbd0>; | ||
341 | xlnx,tcedv-ps-mem-1 = <0x3a98>; | ||
342 | xlnx,tcedv-ps-mem-2 = <0x3a98>; | ||
343 | xlnx,tcedv-ps-mem-3 = <0x3a98>; | ||
344 | xlnx,thzce-ps-mem-0 = <0x88b8>; | ||
345 | xlnx,thzce-ps-mem-1 = <0x1b58>; | ||
346 | xlnx,thzce-ps-mem-2 = <0x1b58>; | ||
347 | xlnx,thzce-ps-mem-3 = <0x1b58>; | ||
348 | xlnx,thzoe-ps-mem-0 = <0x1b58>; | ||
349 | xlnx,thzoe-ps-mem-1 = <0x1b58>; | ||
350 | xlnx,thzoe-ps-mem-2 = <0x1b58>; | ||
351 | xlnx,thzoe-ps-mem-3 = <0x1b58>; | ||
352 | xlnx,tlzwe-ps-mem-0 = <0xc350>; | ||
353 | xlnx,tlzwe-ps-mem-1 = <0x0>; | ||
354 | xlnx,tlzwe-ps-mem-2 = <0x0>; | ||
355 | xlnx,tlzwe-ps-mem-3 = <0x0>; | ||
356 | xlnx,tpacc-ps-flash-0 = <0x61a8>; | ||
357 | xlnx,tpacc-ps-flash-1 = <0x61a8>; | ||
358 | xlnx,tpacc-ps-flash-2 = <0x61a8>; | ||
359 | xlnx,tpacc-ps-flash-3 = <0x61a8>; | ||
360 | xlnx,twc-ps-mem-0 = <0x11170>; | ||
361 | xlnx,twc-ps-mem-1 = <0x3a98>; | ||
362 | xlnx,twc-ps-mem-2 = <0x3a98>; | ||
363 | xlnx,twc-ps-mem-3 = <0x3a98>; | ||
364 | xlnx,twp-ps-mem-0 = <0x13880>; | ||
365 | xlnx,twp-ps-mem-1 = <0x2ee0>; | ||
366 | xlnx,twp-ps-mem-2 = <0x2ee0>; | ||
367 | xlnx,twp-ps-mem-3 = <0x2ee0>; | ||
368 | xlnx,twph-ps-mem-0 = <0x13880>; | ||
369 | xlnx,twph-ps-mem-1 = <0x2ee0>; | ||
370 | xlnx,twph-ps-mem-2 = <0x2ee0>; | ||
371 | xlnx,twph-ps-mem-3 = <0x2ee0>; | ||
372 | xlnx,use-startup = <0x0>; | ||
373 | xlnx,use-startup-int = <0x0>; | ||
374 | xlnx,wr-rec-time-mem-0 = <0x186a0>; | ||
375 | xlnx,wr-rec-time-mem-1 = <0x6978>; | ||
376 | xlnx,wr-rec-time-mem-2 = <0x6978>; | ||
377 | xlnx,wr-rec-time-mem-3 = <0x6978>; | ||
378 | }; | ||
379 | microblaze_0_axi_intc: interrupt-controller@41200000 { | ||
380 | #interrupt-cells = <2>; | ||
381 | compatible = "xlnx,xps-intc-1.00.a"; | ||
382 | interrupt-controller ; | ||
383 | reg = <0x41200000 0x10000>; | ||
384 | xlnx,kind-of-intr = <0x0>; | ||
385 | xlnx,num-intr-inputs = <0x6>; | ||
386 | }; | ||
387 | push_buttons_5bits: gpio@40040000 { | ||
388 | #gpio-cells = <2>; | ||
389 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
390 | gpio-controller ; | ||
391 | reg = <0x40040000 0x10000>; | ||
392 | xlnx,all-inputs = <0x1>; | ||
393 | xlnx,all-inputs-2 = <0x0>; | ||
394 | xlnx,all-outputs = <0x0>; | ||
395 | xlnx,all-outputs-2 = <0x0>; | ||
396 | xlnx,dout-default = <0x00000000>; | ||
397 | xlnx,dout-default-2 = <0x00000000>; | ||
398 | xlnx,gpio-width = <0x5>; | ||
399 | xlnx,gpio2-width = <0x20>; | ||
400 | xlnx,interrupt-present = <0x0>; | ||
401 | xlnx,is-dual = <0x0>; | ||
402 | xlnx,tri-default = <0xFFFFFFFF>; | ||
403 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
404 | }; | ||
405 | reset_gpio: gpio@40000000 { | ||
406 | #gpio-cells = <2>; | ||
407 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
408 | gpio-controller ; | ||
409 | reg = <0x40000000 0x10000>; | ||
410 | xlnx,all-inputs = <0x0>; | ||
411 | xlnx,all-inputs-2 = <0x0>; | ||
412 | xlnx,all-outputs = <0x1>; | ||
413 | xlnx,all-outputs-2 = <0x0>; | ||
414 | xlnx,dout-default = <0x00000000>; | ||
415 | xlnx,dout-default-2 = <0x00000000>; | ||
416 | xlnx,gpio-width = <0x1>; | ||
417 | xlnx,gpio2-width = <0x20>; | ||
418 | xlnx,interrupt-present = <0x0>; | ||
419 | xlnx,is-dual = <0x0>; | ||
420 | xlnx,tri-default = <0xFFFFFFFF>; | ||
421 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
422 | }; | ||
423 | rs232_uart: serial@44a00000 { | ||
424 | clock-frequency = <200000000>; | ||
425 | clocks = <&clk_bus_0>; | ||
426 | compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; | ||
427 | current-speed = <115200>; | ||
428 | device_type = "serial"; | ||
429 | interrupt-parent = <µblaze_0_axi_intc>; | ||
430 | interrupts = <0 2>; | ||
431 | port-number = <0>; | ||
432 | reg = <0x44a00000 0x10000>; | ||
433 | reg-offset = <0x1000>; | ||
434 | reg-shift = <2>; | ||
435 | xlnx,external-xin-clk-hz = <0x17d7840>; | ||
436 | xlnx,external-xin-clk-hz-d = <0x19>; | ||
437 | xlnx,has-external-rclk = <0x0>; | ||
438 | xlnx,has-external-xin = <0x0>; | ||
439 | xlnx,is-a-16550 = <0x1>; | ||
440 | xlnx,s-axi-aclk-freq-hz-d = "200.0"; | ||
441 | xlnx,use-modem-ports = <0x1>; | ||
442 | xlnx,use-user-ports = <0x1>; | ||
443 | }; | ||
444 | }; | ||
445 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi deleted file mode 100644 index 09b26c6a..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi +++ /dev/null | |||
@@ -1,43 +0,0 @@ | |||
1 | /* | ||
2 | * CAUTION: This file is automatically generated by PetaLinux SDK. | ||
3 | * DO NOT modify this file | ||
4 | */ | ||
5 | |||
6 | |||
7 | / { | ||
8 | chosen { | ||
9 | bootargs = "console=ttyS0,115200 earlyprintk"; | ||
10 | stdout-path = "serial0:115200n8"; | ||
11 | }; | ||
12 | }; | ||
13 | |||
14 | &axi_ethernet { | ||
15 | local-mac-address = [00 0a 35 00 22 01]; | ||
16 | }; | ||
17 | |||
18 | &linear_flash { | ||
19 | reg = <0x60000000 0x08000000>; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | partition@0x00000000 { | ||
23 | label = "fpga"; | ||
24 | reg = <0x00000000 0x00b00000>; | ||
25 | }; | ||
26 | partition@0x00b00000 { | ||
27 | label = "boot"; | ||
28 | reg = <0x00b00000 0x00080000>; | ||
29 | }; | ||
30 | partition@0x00b80000 { | ||
31 | label = "bootenv"; | ||
32 | reg = <0x00b80000 0x00020000>; | ||
33 | }; | ||
34 | partition@0x00ba0000 { | ||
35 | label = "kernel"; | ||
36 | reg = <0x00ba0000 0x00c00000>; | ||
37 | }; | ||
38 | partition@0x017a0000 { | ||
39 | label = "spare"; | ||
40 | reg = <0x017a0000 0x00000000>; | ||
41 | }; | ||
42 | }; | ||
43 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts deleted file mode 100644 index 6f9b653a..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/picozed-zynq7.dts +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "zynq-7000.dtsi" | ||
3 | /include/ "zynq-7000-qspi-dummy.dtsi" | ||
4 | |||
5 | / { | ||
6 | model = "Avnet picoZed"; | ||
7 | compatible = "avnet,picozed", "xlnx,zynq-7000"; | ||
8 | |||
9 | aliases { | ||
10 | ethernet0 = &gem0; | ||
11 | serial0 = &uart1; | ||
12 | }; | ||
13 | |||
14 | memory { | ||
15 | device_type = "memory"; | ||
16 | reg = <0x0 0x40000000>; | ||
17 | }; | ||
18 | |||
19 | chosen { | ||
20 | bootargs = "earlyprintk"; | ||
21 | stdout-path = "serial0:115200n8"; | ||
22 | }; | ||
23 | |||
24 | usb_phy0: phy0 { | ||
25 | compatible = "usb-nop-xceiv"; | ||
26 | #phy-cells = <0>; | ||
27 | reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */ | ||
28 | }; | ||
29 | }; | ||
30 | |||
31 | &gem0 { | ||
32 | status = "okay"; | ||
33 | phy-mode = "rgmii-id"; | ||
34 | phy-handle = <ðernet_phy>; | ||
35 | |||
36 | ethernet_phy: ethernet-phy@0 { | ||
37 | compatible = "marvell,88e1512", "marvell,88e1510"; | ||
38 | device_type = "ethernet-phy"; | ||
39 | reg = <0>; | ||
40 | }; | ||
41 | }; | ||
42 | |||
43 | &sdhci1 { | ||
44 | status = "okay"; | ||
45 | /* SD1 is onnected to a non-removable eMMC flash device */ | ||
46 | non-removable; | ||
47 | }; | ||
48 | |||
49 | &uart1 { | ||
50 | status = "okay"; | ||
51 | }; | ||
52 | |||
53 | &usb0 { | ||
54 | status = "okay"; | ||
55 | dr_mode = "host"; | ||
56 | usb-phy = <&usb_phy0>; | ||
57 | }; | ||
58 | |||
59 | &qspi { | ||
60 | status = "okay"; | ||
61 | primary_flash: ps7-qspi@0 { | ||
62 | #address-cells = <1>; | ||
63 | #size-cells = <1>; | ||
64 | compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor"; | ||
65 | reg = <0x0>; | ||
66 | spi-max-frequency = <50000000>; | ||
67 | /* Example 16M partition table using U-Boot + U-Boot SPL */ | ||
68 | partition@0x0 { | ||
69 | label = "boot"; | ||
70 | reg = <0x0 0xe0000>; | ||
71 | }; | ||
72 | partition@0xe0000 { | ||
73 | label = "ubootenv"; | ||
74 | reg = <0xe0000 0x20000>; | ||
75 | }; | ||
76 | partition@0x100000 { | ||
77 | label = "uboot"; | ||
78 | reg = <0x100000 0x100000>; | ||
79 | }; | ||
80 | partition@0x200000 { | ||
81 | label = "kernel"; | ||
82 | reg = <0x200000 0x4f0000>; | ||
83 | }; | ||
84 | partition@0x6f0000 { | ||
85 | label = "devicetree"; | ||
86 | reg = <0x6f0000 0x10000>; | ||
87 | }; | ||
88 | partition@0x700000 { | ||
89 | label = "rootfs"; | ||
90 | reg = <0x700000 0x400000>; | ||
91 | }; | ||
92 | partition@0xb00000 { | ||
93 | label = "spare"; | ||
94 | reg = <0xb00000 0x500000>; | ||
95 | }; | ||
96 | }; | ||
97 | }; | ||
98 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts deleted file mode 100644 index cd0694d6..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/qemu-zynq7.dts +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "zynq-7000.dtsi" | ||
3 | /include/ "zynq-7000-qspi-dummy.dtsi" | ||
4 | |||
5 | / { | ||
6 | model = "Zynq A9 QEMU"; | ||
7 | compatible = "qemu,xilinx-zynq-a9", "xlnx,zynq-7000"; | ||
8 | |||
9 | aliases { | ||
10 | ethernet0 = &gem0; | ||
11 | serial0 = &uart1; | ||
12 | }; | ||
13 | |||
14 | memory { | ||
15 | device_type = "memory"; | ||
16 | reg = <0x0 0x40000000>; | ||
17 | }; | ||
18 | |||
19 | chosen { | ||
20 | bootargs = "earlyprintk"; | ||
21 | stdout-path = "serial0:115200n8"; | ||
22 | }; | ||
23 | }; | ||
24 | |||
25 | &amba { | ||
26 | /* Setup a fixed 25 MHz clock (100Mbps) to trick the ethernet driver */ | ||
27 | fixednetclk: clock { | ||
28 | #clock-cells = <0>; | ||
29 | compatible = "fixed-clock"; | ||
30 | clock-frequency = <25000000>; | ||
31 | }; | ||
32 | }; | ||
33 | |||
34 | &gem0 { | ||
35 | status = "okay"; | ||
36 | clocks = <&clkc 30>, <&clkc 30>, <&fixednetclk>, <&fixednetclk>, <&clkc 30>; | ||
37 | phy-mode = "rgmii-id"; | ||
38 | phy-handle = <ðernet_phy>; | ||
39 | |||
40 | ethernet_phy: ethernet-phy@23 { | ||
41 | device_type = "ethernet-phy"; | ||
42 | reg = <23>; | ||
43 | }; | ||
44 | }; | ||
45 | |||
46 | &sdhci0 { | ||
47 | status = "okay"; | ||
48 | }; | ||
49 | |||
50 | &uart1 { | ||
51 | status = "okay"; | ||
52 | }; | ||
53 | |||
54 | &qspi { | ||
55 | status = "okay"; | ||
56 | is-dual = <1>; | ||
57 | primary_flash: ps7-qspi@0 { | ||
58 | #address-cells = <1>; | ||
59 | #size-cells = <1>; | ||
60 | compatible = "st,m25p80"; | ||
61 | reg = <0x0>; | ||
62 | spi-max-frequency = <50000000>; | ||
63 | partition@0x00000000 { | ||
64 | label = "boot"; | ||
65 | reg = <0x00000000 0x00500000>; | ||
66 | }; | ||
67 | partition@0x00500000 { | ||
68 | label = "bootenv"; | ||
69 | reg = <0x00500000 0x00020000>; | ||
70 | }; | ||
71 | partition@0x00520000 { | ||
72 | label = "config"; | ||
73 | reg = <0x00520000 0x00020000>; | ||
74 | }; | ||
75 | partition@0x00540000 { | ||
76 | label = "image"; | ||
77 | reg = <0x00540000 0x00a80000>; | ||
78 | }; | ||
79 | partition@0x00fc0000 { | ||
80 | label = "spare"; | ||
81 | reg = <0x00fc0000 0x00000000>; | ||
82 | }; | ||
83 | }; | ||
84 | }; | ||
85 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi deleted file mode 100644 index 0f678d39..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi +++ /dev/null | |||
@@ -1,63 +0,0 @@ | |||
1 | /* | ||
2 | * CAUTION: This file is automatically generated by Xilinx. | ||
3 | * Version: HSI 2015.4 | ||
4 | * Today is: Fri Mar 4 15:40:49 2016 | ||
5 | */ | ||
6 | |||
7 | |||
8 | / { | ||
9 | cpus { | ||
10 | cpu@0 { | ||
11 | operating-points = <650000 1000000 325000 1000000>; | ||
12 | }; | ||
13 | }; | ||
14 | }; | ||
15 | &gem0 { | ||
16 | phy-mode = "rgmii-id"; | ||
17 | status = "okay"; | ||
18 | xlnx,ptp-enet-clock = <0x6750918>; | ||
19 | }; | ||
20 | &gpio0 { | ||
21 | emio-gpio-width = <64>; | ||
22 | gpio-mask-high = <0x0>; | ||
23 | gpio-mask-low = <0x5600>; | ||
24 | }; | ||
25 | &i2c0 { | ||
26 | clock-frequency = <400000>; | ||
27 | status = "okay"; | ||
28 | }; | ||
29 | &i2c1 { | ||
30 | clock-frequency = <400000>; | ||
31 | status = "okay"; | ||
32 | }; | ||
33 | &intc { | ||
34 | num_cpus = <2>; | ||
35 | num_interrupts = <96>; | ||
36 | }; | ||
37 | &qspi { | ||
38 | is-dual = <0>; | ||
39 | num-cs = <1>; | ||
40 | status = "okay"; | ||
41 | }; | ||
42 | &sdhci0 { | ||
43 | status = "okay"; | ||
44 | xlnx,has-cd = <0x1>; | ||
45 | xlnx,has-power = <0x0>; | ||
46 | xlnx,has-wp = <0x1>; | ||
47 | }; | ||
48 | &uart1 { | ||
49 | current-speed = <115200>; | ||
50 | device_type = "serial"; | ||
51 | port-number = <0>; | ||
52 | status = "okay"; | ||
53 | }; | ||
54 | &usb0 { | ||
55 | dr_mode = "host"; | ||
56 | phy_type = "ulpi"; | ||
57 | status = "okay"; | ||
58 | usb-reset = <&gpio0 46 0>; | ||
59 | }; | ||
60 | &clkc { | ||
61 | fclk-enable = <0x3>; | ||
62 | ps-clk-frequency = <50000000>; | ||
63 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi deleted file mode 100644 index 32bc7688..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi +++ /dev/null | |||
@@ -1,215 +0,0 @@ | |||
1 | /* | ||
2 | * CAUTION: This file is automatically generated by Xilinx. | ||
3 | * Version: HSI 2015.4 | ||
4 | * Today is: Fri Mar 4 15:40:49 2016 | ||
5 | */ | ||
6 | |||
7 | |||
8 | / { | ||
9 | amba_pl: amba_pl { | ||
10 | #address-cells = <1>; | ||
11 | #size-cells = <1>; | ||
12 | compatible = "simple-bus"; | ||
13 | ranges ; | ||
14 | axi_dynclk_0: axi_dynclk@43c10000 { | ||
15 | compatible = "xlnx,axi-dynclk-1.0"; | ||
16 | reg = <0x43c10000 0x10000>; | ||
17 | xlnx,s00-axi-addr-width = <0x5>; | ||
18 | xlnx,s00-axi-data-width = <0x20>; | ||
19 | }; | ||
20 | axi_gpio_btn: gpio@41210000 { | ||
21 | #gpio-cells = <2>; | ||
22 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
23 | gpio-controller ; | ||
24 | reg = <0x41210000 0x10000>; | ||
25 | xlnx,all-inputs = <0x1>; | ||
26 | xlnx,all-inputs-2 = <0x0>; | ||
27 | xlnx,all-outputs = <0x0>; | ||
28 | xlnx,all-outputs-2 = <0x0>; | ||
29 | xlnx,dout-default = <0x00000000>; | ||
30 | xlnx,dout-default-2 = <0x00000000>; | ||
31 | xlnx,gpio-width = <0x4>; | ||
32 | xlnx,gpio2-width = <0x20>; | ||
33 | xlnx,interrupt-present = <0x0>; | ||
34 | xlnx,is-dual = <0x0>; | ||
35 | xlnx,tri-default = <0xFFFFFFFF>; | ||
36 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
37 | }; | ||
38 | axi_gpio_hdmi: gpio@41230000 { | ||
39 | #gpio-cells = <2>; | ||
40 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
41 | gpio-controller ; | ||
42 | interrupt-parent = <&intc>; | ||
43 | interrupts = <0 29 4>; | ||
44 | reg = <0x41230000 0x10000>; | ||
45 | xlnx,all-inputs = <0x1>; | ||
46 | xlnx,all-inputs-2 = <0x0>; | ||
47 | xlnx,all-outputs = <0x0>; | ||
48 | xlnx,all-outputs-2 = <0x0>; | ||
49 | xlnx,dout-default = <0x00000000>; | ||
50 | xlnx,dout-default-2 = <0x00000000>; | ||
51 | xlnx,gpio-width = <0x1>; | ||
52 | xlnx,gpio2-width = <0x20>; | ||
53 | xlnx,interrupt-present = <0x1>; | ||
54 | xlnx,is-dual = <0x0>; | ||
55 | xlnx,tri-default = <0xFFFFFFFF>; | ||
56 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
57 | }; | ||
58 | axi_gpio_led: gpio@41200000 { | ||
59 | #gpio-cells = <2>; | ||
60 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
61 | gpio-controller ; | ||
62 | reg = <0x41200000 0x10000>; | ||
63 | xlnx,all-inputs = <0x0>; | ||
64 | xlnx,all-inputs-2 = <0x0>; | ||
65 | xlnx,all-outputs = <0x1>; | ||
66 | xlnx,all-outputs-2 = <0x0>; | ||
67 | xlnx,dout-default = <0x00000000>; | ||
68 | xlnx,dout-default-2 = <0x00000000>; | ||
69 | xlnx,gpio-width = <0x4>; | ||
70 | xlnx,gpio2-width = <0x20>; | ||
71 | xlnx,interrupt-present = <0x0>; | ||
72 | xlnx,is-dual = <0x0>; | ||
73 | xlnx,tri-default = <0xFFFFFFFF>; | ||
74 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
75 | }; | ||
76 | axi_gpio_sw: gpio@41220000 { | ||
77 | #gpio-cells = <2>; | ||
78 | compatible = "xlnx,xps-gpio-1.00.a"; | ||
79 | gpio-controller ; | ||
80 | reg = <0x41220000 0x10000>; | ||
81 | xlnx,all-inputs = <0x1>; | ||
82 | xlnx,all-inputs-2 = <0x0>; | ||
83 | xlnx,all-outputs = <0x0>; | ||
84 | xlnx,all-outputs-2 = <0x0>; | ||
85 | xlnx,dout-default = <0x00000000>; | ||
86 | xlnx,dout-default-2 = <0x00000000>; | ||
87 | xlnx,gpio-width = <0x4>; | ||
88 | xlnx,gpio2-width = <0x20>; | ||
89 | xlnx,interrupt-present = <0x0>; | ||
90 | xlnx,is-dual = <0x0>; | ||
91 | xlnx,tri-default = <0xFFFFFFFF>; | ||
92 | xlnx,tri-default-2 = <0xFFFFFFFF>; | ||
93 | }; | ||
94 | axi_i2s_adi_0: axi_i2s_adi@43c20000 { | ||
95 | compatible = "xlnx,axi-i2s-adi-1.0"; | ||
96 | reg = <0x43c20000 0x10000>; | ||
97 | xlnx,bclk-pol = <0x0>; | ||
98 | xlnx,dma-type = <0x1>; | ||
99 | xlnx,has-rx = <0x1>; | ||
100 | xlnx,has-tx = <0x1>; | ||
101 | xlnx,lrclk-pol = <0x0>; | ||
102 | xlnx,num-ch = <0x1>; | ||
103 | xlnx,s-axi-min-size = <0x000001FF>; | ||
104 | xlnx,slot-width = <0x18>; | ||
105 | }; | ||
106 | axi_vdma_0: dma@43000000 { | ||
107 | #dma-cells = <1>; | ||
108 | compatible = "xlnx,axi-vdma-1.00.a"; | ||
109 | clocks = <&clkc 15>; | ||
110 | clock-names = "s_axi_lite_aclk"; | ||
111 | interrupt-parent = <&intc>; | ||
112 | interrupts = <0 30 4>; | ||
113 | reg = <0x43000000 0x10000>; | ||
114 | xlnx,flush-fsync = <0x1>; | ||
115 | xlnx,num-fstores = <0x1>; | ||
116 | dma-channel@43000000 { | ||
117 | compatible = "xlnx,axi-vdma-mm2s-channel"; | ||
118 | interrupts = <0 30 4>; | ||
119 | xlnx,datawidth = <0x20>; | ||
120 | xlnx,device-id = <0x0>; | ||
121 | }; | ||
122 | }; | ||
123 | v_tc_0: v_tc@43c00000 { | ||
124 | compatible = "xlnx,v-tc-6.1"; | ||
125 | interrupt-parent = <&intc>; | ||
126 | interrupts = <0 31 4>; | ||
127 | reg = <0x43c00000 0x10000>; | ||
128 | xlnx,det-achroma-en = <0x0>; | ||
129 | xlnx,det-avideo-en = <0x1>; | ||
130 | xlnx,det-fieldid-en = <0x0>; | ||
131 | xlnx,det-hblank-en = <0x1>; | ||
132 | xlnx,det-hsync-en = <0x1>; | ||
133 | xlnx,det-vblank-en = <0x1>; | ||
134 | xlnx,det-vsync-en = <0x1>; | ||
135 | xlnx,detect-en = <0x0>; | ||
136 | xlnx,fsync-hstart0 = <0x0>; | ||
137 | xlnx,fsync-hstart1 = <0x0>; | ||
138 | xlnx,fsync-hstart10 = <0x0>; | ||
139 | xlnx,fsync-hstart11 = <0x0>; | ||
140 | xlnx,fsync-hstart12 = <0x0>; | ||
141 | xlnx,fsync-hstart13 = <0x0>; | ||
142 | xlnx,fsync-hstart14 = <0x0>; | ||
143 | xlnx,fsync-hstart15 = <0x0>; | ||
144 | xlnx,fsync-hstart2 = <0x0>; | ||
145 | xlnx,fsync-hstart3 = <0x0>; | ||
146 | xlnx,fsync-hstart4 = <0x0>; | ||
147 | xlnx,fsync-hstart5 = <0x0>; | ||
148 | xlnx,fsync-hstart6 = <0x0>; | ||
149 | xlnx,fsync-hstart7 = <0x0>; | ||
150 | xlnx,fsync-hstart8 = <0x0>; | ||
151 | xlnx,fsync-hstart9 = <0x0>; | ||
152 | xlnx,fsync-vstart0 = <0x0>; | ||
153 | xlnx,fsync-vstart1 = <0x0>; | ||
154 | xlnx,fsync-vstart10 = <0x0>; | ||
155 | xlnx,fsync-vstart11 = <0x0>; | ||
156 | xlnx,fsync-vstart12 = <0x0>; | ||
157 | xlnx,fsync-vstart13 = <0x0>; | ||
158 | xlnx,fsync-vstart14 = <0x0>; | ||
159 | xlnx,fsync-vstart15 = <0x0>; | ||
160 | xlnx,fsync-vstart2 = <0x0>; | ||
161 | xlnx,fsync-vstart3 = <0x0>; | ||
162 | xlnx,fsync-vstart4 = <0x0>; | ||
163 | xlnx,fsync-vstart5 = <0x0>; | ||
164 | xlnx,fsync-vstart6 = <0x0>; | ||
165 | xlnx,fsync-vstart7 = <0x0>; | ||
166 | xlnx,fsync-vstart8 = <0x0>; | ||
167 | xlnx,fsync-vstart9 = <0x0>; | ||
168 | xlnx,gen-achroma-en = <0x0>; | ||
169 | xlnx,gen-achroma-polarity = <0x1>; | ||
170 | xlnx,gen-auto-switch = <0x0>; | ||
171 | xlnx,gen-avideo-en = <0x1>; | ||
172 | xlnx,gen-avideo-polarity = <0x1>; | ||
173 | xlnx,gen-cparity = <0x0>; | ||
174 | xlnx,gen-f0-vblank-hend = <0x500>; | ||
175 | xlnx,gen-f0-vblank-hstart = <0x500>; | ||
176 | xlnx,gen-f0-vframe-size = <0x2ee>; | ||
177 | xlnx,gen-f0-vsync-hend = <0x500>; | ||
178 | xlnx,gen-f0-vsync-hstart = <0x500>; | ||
179 | xlnx,gen-f0-vsync-vend = <0x2d9>; | ||
180 | xlnx,gen-f0-vsync-vstart = <0x2d4>; | ||
181 | xlnx,gen-f1-vblank-hend = <0x500>; | ||
182 | xlnx,gen-f1-vblank-hstart = <0x500>; | ||
183 | xlnx,gen-f1-vframe-size = <0x2ee>; | ||
184 | xlnx,gen-f1-vsync-hend = <0x500>; | ||
185 | xlnx,gen-f1-vsync-hstart = <0x500>; | ||
186 | xlnx,gen-f1-vsync-vend = <0x2d9>; | ||
187 | xlnx,gen-f1-vsync-vstart = <0x2d4>; | ||
188 | xlnx,gen-fieldid-en = <0x0>; | ||
189 | xlnx,gen-fieldid-polarity = <0x1>; | ||
190 | xlnx,gen-hactive-size = <0x500>; | ||
191 | xlnx,gen-hblank-en = <0x1>; | ||
192 | xlnx,gen-hblank-polarity = <0x1>; | ||
193 | xlnx,gen-hframe-size = <0x672>; | ||
194 | xlnx,gen-hsync-en = <0x1>; | ||
195 | xlnx,gen-hsync-end = <0x596>; | ||
196 | xlnx,gen-hsync-polarity = <0x1>; | ||
197 | xlnx,gen-hsync-start = <0x56e>; | ||
198 | xlnx,gen-interlaced = <0x0>; | ||
199 | xlnx,gen-vactive-size = <0x2d0>; | ||
200 | xlnx,gen-vblank-en = <0x1>; | ||
201 | xlnx,gen-vblank-polarity = <0x1>; | ||
202 | xlnx,gen-video-format = <0x2>; | ||
203 | xlnx,gen-vsync-en = <0x1>; | ||
204 | xlnx,gen-vsync-polarity = <0x1>; | ||
205 | xlnx,generate-en = <0x1>; | ||
206 | xlnx,has-axi4-lite = <0x1>; | ||
207 | xlnx,has-intc-if = <0x0>; | ||
208 | xlnx,interlace-en = <0x0>; | ||
209 | xlnx,max-lines = <0x1000>; | ||
210 | xlnx,max-pixels = <0x1000>; | ||
211 | xlnx,num-fsyncs = <0x1>; | ||
212 | xlnx,sync-en = <0x0>; | ||
213 | }; | ||
214 | }; | ||
215 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts deleted file mode 100644 index 19654392..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts +++ /dev/null | |||
@@ -1,184 +0,0 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "skeleton.dtsi" | ||
3 | /include/ "zynq-7000.dtsi" | ||
4 | /include/ "zynq-7000-qspi-dummy.dtsi" | ||
5 | /include/ "pcw.dtsi" | ||
6 | /include/ "pl.dtsi" | ||
7 | |||
8 | / { | ||
9 | model = "Digilent-Zybo-Linux-BD-v2015.4"; | ||
10 | aliases { | ||
11 | serial0 = &uart1; | ||
12 | ethernet0 = &gem0; | ||
13 | spi0 = &qspi; | ||
14 | }; | ||
15 | chosen { | ||
16 | bootargs = ""; | ||
17 | stdout-path = "serial0:115200n8"; | ||
18 | }; | ||
19 | memory { | ||
20 | device_type = "memory"; | ||
21 | reg = <0x0 0x20000000>; | ||
22 | }; | ||
23 | |||
24 | gpio-keys { | ||
25 | compatible = "gpio-keys"; | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <0>; | ||
28 | autorepeat; | ||
29 | btn4 { | ||
30 | label = "btn4"; | ||
31 | gpios = <&gpio0 50 0>; | ||
32 | linux,code = <108>; /* down */ | ||
33 | gpio-key,wakeup; | ||
34 | autorepeat; | ||
35 | }; | ||
36 | btn5 { | ||
37 | label = "btn5"; | ||
38 | gpios = <&gpio0 51 0>; | ||
39 | linux,code = <103>; /* up */ | ||
40 | gpio-key,wakeup; | ||
41 | autorepeat; | ||
42 | }; | ||
43 | }; | ||
44 | |||
45 | usb_phy0: usb_phy@0 { | ||
46 | compatible = "usb-nop-xceiv"; | ||
47 | #phy-cells = <0>; | ||
48 | reset-gpios = <&gpio0 46 1>; | ||
49 | }; | ||
50 | }; | ||
51 | |||
52 | &amba { | ||
53 | u-boot,dm-pre-reloc; | ||
54 | }; | ||
55 | |||
56 | &amba_pl { | ||
57 | encoder_0: digilent_encoder { | ||
58 | compatible = "digilent,drm-encoder"; | ||
59 | dglnt,edid-i2c = <&i2c1>; | ||
60 | }; | ||
61 | |||
62 | xilinx_drm { | ||
63 | compatible = "xlnx,drm"; | ||
64 | xlnx,vtc = <&v_tc_0>; | ||
65 | xlnx,connector-type = "HDMIA"; | ||
66 | xlnx,encoder-slave = <&encoder_0>; | ||
67 | clocks = <&axi_dynclk_0>; | ||
68 | planes { | ||
69 | xlnx,pixel-format = "xrgb8888"; | ||
70 | plane0 { | ||
71 | dmas = <&axi_vdma_0 0>; | ||
72 | dma-names = "dma0"; | ||
73 | }; | ||
74 | }; | ||
75 | }; | ||
76 | |||
77 | i2s_clk: i2s_clk { | ||
78 | #clock-cells = <0>; | ||
79 | compatible = "fixed-clock"; | ||
80 | clock-frequency = <12288000>; | ||
81 | clock-output-names = "i2s_clk"; | ||
82 | }; | ||
83 | |||
84 | sound { | ||
85 | compatible = "simple-audio-card"; | ||
86 | simple-audio-card,name = "ZYBO-Sound-Card"; | ||
87 | simple-audio-card,format = "i2s"; | ||
88 | simple-audio-card,bitclock-master = <&dailink0_master>; | ||
89 | simple-audio-card,frame-master = <&dailink0_master>; | ||
90 | simple-audio-card,widgets = | ||
91 | "Microphone", "Microphone Jack", | ||
92 | "Headphone", "Headphone Jack", | ||
93 | "Line", "Line In Jack"; | ||
94 | simple-audio-card,routing = | ||
95 | "MICIN", "Microphone Jack", | ||
96 | "Headphone Jack", "LHPOUT", | ||
97 | "Headphone Jack", "RHPOUT", | ||
98 | "LLINEIN", "Line In Jack", | ||
99 | "RLINEIN", "Line In Jack"; | ||
100 | dailink0_master: simple-audio-card,cpu { | ||
101 | clocks = <&i2s_clk>; | ||
102 | sound-dai = <&axi_i2s_adi_0>; | ||
103 | }; | ||
104 | simple-audio-card,codec { | ||
105 | clocks = <&i2s_clk>; | ||
106 | sound-dai = <&ssm2603>; | ||
107 | }; | ||
108 | }; | ||
109 | }; | ||
110 | |||
111 | &axi_dynclk_0 { | ||
112 | compatible = "digilent,axi-dynclk"; | ||
113 | #clock-cells = <0>; | ||
114 | clocks = <&clkc 15>; | ||
115 | }; | ||
116 | |||
117 | &axi_i2s_adi_0 { | ||
118 | #sound-dai-cells = <0>; | ||
119 | compatible = "adi,axi-i2s-1.00.a"; | ||
120 | clocks = <&clkc 15>, <&i2s_clk>; | ||
121 | clock-names = "axi", "ref"; | ||
122 | dmas = <&dmac_s 0 &dmac_s 1>; | ||
123 | dma-names = "tx", "rx"; | ||
124 | }; | ||
125 | |||
126 | &gem0 { | ||
127 | phy-handle = <&phy0>; | ||
128 | phy-mode = "rgmii-id"; | ||
129 | local-mac-address = []; | ||
130 | phy0: phy@0 { | ||
131 | device_type = "ethernet-phy"; | ||
132 | reg = <0>; | ||
133 | }; | ||
134 | }; | ||
135 | |||
136 | &i2c0 { | ||
137 | eeprom@50 { | ||
138 | /* Microchip 24AA02E48 */ | ||
139 | compatible = "microchip,24c02"; | ||
140 | reg = <0x50>; | ||
141 | }; | ||
142 | |||
143 | ssm2603: ssm2603@1a{ | ||
144 | #sound-dai-cells = <0>; | ||
145 | compatible = "adi,ssm2603"; | ||
146 | reg = <0x1a>; | ||
147 | }; | ||
148 | }; | ||
149 | |||
150 | &qspi { | ||
151 | #address-cells = <1>; | ||
152 | #size-cells = <0>; | ||
153 | flash0: flash@0 { | ||
154 | compatible = "micron,m25p80", "s25fl128s"; | ||
155 | reg = <0x0>; | ||
156 | #address-cells = <1>; | ||
157 | #size-cells = <1>; | ||
158 | spi-max-frequency = <50000000>; | ||
159 | partition@0x00000000 { | ||
160 | label = "boot"; | ||
161 | reg = <0x00000000 0x00300000>; | ||
162 | }; | ||
163 | partition@0x00300000 { | ||
164 | label = "bootenv"; | ||
165 | reg = <0x00300000 0x00020000>; | ||
166 | }; | ||
167 | partition@0x00320000 { | ||
168 | label = "kernel"; | ||
169 | reg = <0x00320000 0x00a80000>; | ||
170 | }; | ||
171 | partition@0x00da0000 { | ||
172 | label = "spare"; | ||
173 | reg = <0x00da0000 0x00000000>; | ||
174 | }; | ||
175 | }; | ||
176 | }; | ||
177 | |||
178 | &usb0 { | ||
179 | usb-phy = <&usb_phy0>; | ||
180 | }; | ||
181 | |||
182 | &v_tc_0 { | ||
183 | compatible = "xlnx,v-tc-5.01.a"; | ||
184 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi b/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi deleted file mode 100644 index d059a2da..00000000 --- a/meta-xilinx-bsp/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi +++ /dev/null | |||
@@ -1,4 +0,0 @@ | |||
1 | &amba { | ||
2 | /* empty defintion for kernels that don't have qspi node */ | ||
3 | qspi: spi@e000d000 { }; | ||
4 | }; | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/embeddedsw/fsbl.bb b/meta-xilinx-bsp/recipes-bsp/embeddedsw/fsbl.bb deleted file mode 100644 index 2fa71309..00000000 --- a/meta-xilinx-bsp/recipes-bsp/embeddedsw/fsbl.bb +++ /dev/null | |||
@@ -1,60 +0,0 @@ | |||
1 | DESCRIPTION = "Xilinx First Stage Boot Loader" | ||
2 | |||
3 | LICENSE = "MIT" | ||
4 | |||
5 | PROVIDES = "virtual/fsbl" | ||
6 | |||
7 | INHERIT_DEFAULT_DEPENDS = "1" | ||
8 | |||
9 | COMPATIBLE_MACHINE = "^$" | ||
10 | COMPATIBLE_MACHINE:zynq = "zynq" | ||
11 | COMPATIBLE_MACHINE:zynqmp = "zynqmp" | ||
12 | |||
13 | # Specify a default in case boardvariant isn't available | ||
14 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
15 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
16 | |||
17 | # Default would be a multiconfig (versal) build | ||
18 | # For this to work, BBMULTICONFIG += "fsbl-fw" must be in the user's local.conf! | ||
19 | FSBL_DEPENDS ??= "" | ||
20 | FSBL_MCDEPENDS ??= "mc::fsbl-fw:fsbl-firmware:do_deploy" | ||
21 | |||
22 | # This must be defined to the file output by whatever is providing the fsbl-firmware | ||
23 | # The following sets the default, but the BSP may select a different name | ||
24 | FSBL_IMAGE_NAME ??= "fsbl" | ||
25 | FSBL_DEPLOY_DIR ??= "${TOPDIR}/tmp-fsbl-fw/deploy/images/${MACHINE}" | ||
26 | |||
27 | # Default is for the multilib case (without the extension .elf/.bin) | ||
28 | FSBL_FILE ??= "${FSBL_DEPLOY_DIR}/${FSBL_IMAGE_NAME}" | ||
29 | FSBL_FILE[vardepsexclude] = "FSBL_DEPLOY_DIR" | ||
30 | |||
31 | do_fetch[depends] += "${FSBL_DEPENDS}" | ||
32 | do_fetch[mcdepends] += "${FSBL_MCDEPENDS}" | ||
33 | |||
34 | inherit deploy | ||
35 | |||
36 | do_install() { | ||
37 | if [ ! -e ${FSBL_FILE}.elf ]; then | ||
38 | echo "Unable to find FSBL_FILE (${FSBL_FILE}.elf)" | ||
39 | exit 1 | ||
40 | fi | ||
41 | |||
42 | install -Dm 0644 ${FSBL_FILE}.elf ${D}/boot/${PN}.elf | ||
43 | } | ||
44 | |||
45 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
46 | SHOULD_DEPLOY = "${@'false' if (d.getVar('FSBL_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}" | ||
47 | do_deploy() { | ||
48 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
49 | if ${SHOULD_DEPLOY}; then | ||
50 | install -Dm 0644 ${FSBL_FILE}.elf ${DEPLOYDIR}/${FSBL_IMAGE_NAME}.elf | ||
51 | fi | ||
52 | } | ||
53 | |||
54 | addtask deploy before do_build after do_install | ||
55 | |||
56 | INSANE_SKIP:${PN} = "arch" | ||
57 | INSANE_SKIP:${PN}-dbg = "arch" | ||
58 | |||
59 | SYSROOT_DIRS += "/boot" | ||
60 | FILES:${PN} = "/boot/${PN}.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/embeddedsw/plmfw.bb b/meta-xilinx-bsp/recipes-bsp/embeddedsw/plmfw.bb deleted file mode 100644 index 70d234c9..00000000 --- a/meta-xilinx-bsp/recipes-bsp/embeddedsw/plmfw.bb +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | DESCRIPTION = "Platform Loader and Manager" | ||
2 | SUMMARY = "Platform Loader and Manager for Versal devices" | ||
3 | |||
4 | LICENSE = "MIT" | ||
5 | |||
6 | PROVIDES = "virtual/plm" | ||
7 | |||
8 | INHERIT_DEFAULT_DEPENDS = "1" | ||
9 | |||
10 | COMPATIBLE_MACHINE = "^$" | ||
11 | COMPATIBLE_MACHINE:versal = "versal" | ||
12 | |||
13 | # Specify a default in case boardvariant isn't available | ||
14 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
15 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
16 | |||
17 | # Default would be a multiconfig (versal) build | ||
18 | # For this to work, BBMULTICONFIG += "versal-fw" must be in the user's local.conf! | ||
19 | PLM_DEPENDS ??= "" | ||
20 | PLM_MCDEPENDS ??= "mc::versal-fw:plm-firmware:do_deploy" | ||
21 | |||
22 | # This must be defined to the file output by whatever is providing the plm-firmware | ||
23 | # The following sets the default, but the BSP may select a different name | ||
24 | PLM_IMAGE_NAME ??= "plm-versal-mb" | ||
25 | PLM_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}" | ||
26 | |||
27 | # Default is for the multilib case (without the extension .elf/.bin) | ||
28 | PLM_FILE ??= "${PLM_DEPLOY_DIR}/${PLM_IMAGE_NAME}" | ||
29 | PLM_FILE[vardepsexclude] = "PLM_DEPLOY_DIR" | ||
30 | |||
31 | do_fetch[depends] += "${PLM_DEPENDS}" | ||
32 | do_fetch[mcdepends] += "${PLM_MCDEPENDS}" | ||
33 | |||
34 | inherit deploy | ||
35 | |||
36 | do_install() { | ||
37 | if [ ! -e ${PLM_FILE}.elf ]; then | ||
38 | echo "Unable to find PLM_FILE (${PLM_FILE}.elf)" | ||
39 | exit 1 | ||
40 | fi | ||
41 | |||
42 | install -Dm 0644 ${PLM_FILE}.elf ${D}/boot/${PN}.elf | ||
43 | } | ||
44 | |||
45 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
46 | SHOULD_DEPLOY = "${@'false' if (d.getVar('PLM_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}" | ||
47 | do_deploy() { | ||
48 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
49 | if ${SHOULD_DEPLOY}; then | ||
50 | install -Dm 0644 ${PLM_FILE}.elf ${DEPLOYDIR}/${PLM_IMAGE_NAME}.elf | ||
51 | install -Dm 0644 ${PLM_FILE}.bin ${DEPLOYDIR}/${PLM_IMAGE_NAME}.bin | ||
52 | fi | ||
53 | } | ||
54 | |||
55 | addtask deploy before do_build after do_install | ||
56 | |||
57 | INSANE_SKIP:${PN} = "arch" | ||
58 | INSANE_SKIP:${PN}-dbg = "arch" | ||
59 | |||
60 | SYSROOT_DIRS += "/boot" | ||
61 | FILES:${PN} = "/boot/${PN}.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/embeddedsw/pmufw.bb b/meta-xilinx-bsp/recipes-bsp/embeddedsw/pmufw.bb deleted file mode 100644 index 7371127c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/embeddedsw/pmufw.bb +++ /dev/null | |||
@@ -1,59 +0,0 @@ | |||
1 | DESCRIPTION = "PMU Firmware" | ||
2 | |||
3 | LICENSE = "MIT" | ||
4 | |||
5 | PROVIDES = "virtual/pmu-firmware" | ||
6 | |||
7 | INHERIT_DEFAULT_DEPENDS = "1" | ||
8 | |||
9 | COMPATIBLE_MACHINE = "^$" | ||
10 | COMPATIBLE_MACHINE:zynqmp = "zynqmp" | ||
11 | |||
12 | # Specify a default in case boardvariant isn't available | ||
13 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
14 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
15 | |||
16 | # Default would be a multiconfig (zynqmp-pmufw) build | ||
17 | # For this to work, BBMULTICONFIG += "zynqmp-pmufw" must be in the user's local.conf! | ||
18 | PMU_DEPENDS ??= "" | ||
19 | PMU_MCDEPENDS ??= "mc::zynqmp-pmufw:pmu-firmware:do_deploy" | ||
20 | |||
21 | # This must be defined to the file output by whatever is providing the pmu-firmware | ||
22 | # The following sets the default, but the BSP may select a different name | ||
23 | PMU_FIRMWARE_IMAGE_NAME ??= "pmu-firmware-zynqmp-pmu" | ||
24 | PMU_FIRMWARE_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-zynqmp-pmufw/deploy/images/${MACHINE}" | ||
25 | |||
26 | # Default is for the multilib case (without the extension .elf/.bin) | ||
27 | PMU_FILE ??= "${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}" | ||
28 | PMU_FILE[vardepsexclude] = "PMU_FIRMWARE_DEPLOY_DIR" | ||
29 | |||
30 | do_fetch[depends] += "${PMU_DEPENDS}" | ||
31 | do_fetch[mcdepends] += "${PMU_MCDEPENDS}" | ||
32 | |||
33 | inherit deploy | ||
34 | |||
35 | do_install() { | ||
36 | if [ ! -e ${PMU_FILE}.elf ]; then | ||
37 | echo "Unable to find PMU_FILE (${PMU_FILE}.elf)" | ||
38 | exit 1 | ||
39 | fi | ||
40 | |||
41 | install -Dm 0644 ${PMU_FILE}.elf ${D}/boot/${PN}.elf | ||
42 | } | ||
43 | |||
44 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
45 | SHOULD_DEPLOY = "${@'false' if (d.getVar('PMU_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}" | ||
46 | do_deploy() { | ||
47 | if ${SHOULD_DEPLOY}; then | ||
48 | install -Dm 0644 ${PMU_FILE}.elf ${DEPLOYDIR}/${PMU_FIRMWARE_IMAGE_NAME}.elf | ||
49 | install -Dm 0644 ${PMU_FILE}.bin ${DEPLOYDIR}/${PMU_FIRMWARE_IMAGE_NAME}.bin | ||
50 | fi | ||
51 | } | ||
52 | |||
53 | addtask deploy before do_build after do_install | ||
54 | |||
55 | INSANE_SKIP:${PN} = "arch" | ||
56 | INSANE_SKIP:${PN}-dbg = "arch" | ||
57 | |||
58 | SYSROOT_DIRS += "/boot" | ||
59 | FILES:${PN} = "/boot/${PN}.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/embeddedsw/psmfw.bb b/meta-xilinx-bsp/recipes-bsp/embeddedsw/psmfw.bb deleted file mode 100644 index 5a885b3b..00000000 --- a/meta-xilinx-bsp/recipes-bsp/embeddedsw/psmfw.bb +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | DESCRIPTION = "PSM Firmware" | ||
2 | SUMMARY = "PSM firmware for versal devices" | ||
3 | |||
4 | LICENSE = "MIT" | ||
5 | |||
6 | PROVIDES = "virtual/psm-firmware" | ||
7 | |||
8 | INHERIT_DEFAULT_DEPENDS = "1" | ||
9 | |||
10 | COMPATIBLE_MACHINE = "^$" | ||
11 | COMPATIBLE_MACHINE:versal = "versal" | ||
12 | |||
13 | # Specify a default in case boardvariant isn't available | ||
14 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
15 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
16 | |||
17 | # Default would be a multiconfig (versal) build | ||
18 | # For this to work, BBMULTICONFIG += "versal-fw" must be in the user's local.conf! | ||
19 | PSM_DEPENDS ??= "" | ||
20 | PSM_MCDEPENDS ??= "mc::versal-fw:psm-firmware:do_deploy" | ||
21 | |||
22 | # This must be defined to the file output by whatever is providing the psm-firmware | ||
23 | # The following sets the default, but the BSP may select a different name | ||
24 | PSM_FIRMWARE_IMAGE_NAME ??= "psm-firmware-versal-mb" | ||
25 | PSM_FIRMWARE_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}" | ||
26 | |||
27 | # Default is for the multilib case (without the extension .elf/.bin) | ||
28 | PSM_FILE ??= "${PSM_FIRMWARE_DEPLOY_DIR}/${PSM_FIRMWARE_IMAGE_NAME}" | ||
29 | PSM_FILE[vardepsexclude] = "PSM_FIRMWARE_DEPLOY_DIR" | ||
30 | |||
31 | do_fetch[depends] += "${PSM_DEPENDS}" | ||
32 | do_fetch[mcdepends] += "${PSM_MCDEPENDS}" | ||
33 | |||
34 | inherit deploy | ||
35 | |||
36 | do_install() { | ||
37 | if [ ! -e ${PSM_FILE}.elf ]; then | ||
38 | echo "Unable to find PSM_FILE (${PSM_FILE}.elf)" | ||
39 | exit 1 | ||
40 | fi | ||
41 | |||
42 | install -Dm 0644 ${PSM_FILE}.elf ${D}/boot/${PN}.elf | ||
43 | } | ||
44 | |||
45 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
46 | SHOULD_DEPLOY = "${@'false' if (d.getVar('PSM_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}" | ||
47 | do_deploy() { | ||
48 | # If the item is already in OUR deploy_image_dir, nothing to deploy! | ||
49 | if ${SHOULD_DEPLOY}; then | ||
50 | install -Dm 0644 ${PSM_FILE}.elf ${DEPLOYDIR}/${PSM_FIRMWARE_IMAGE_NAME}.elf | ||
51 | install -Dm 0644 ${PSM_FILE}.bin ${DEPLOYDIR}/${PSM_FIRMWARE_IMAGE_NAME}.bin | ||
52 | fi | ||
53 | } | ||
54 | |||
55 | addtask deploy before do_build after do_install | ||
56 | |||
57 | INSANE_SKIP:${PN} = "arch" | ||
58 | INSANE_SKIP:${PN}-dbg = "arch" | ||
59 | |||
60 | SYSROOT_DIRS += "/boot" | ||
61 | FILES:${PN} = "/boot/${PN}.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb deleted file mode 100644 index cac8bbfc..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init.bb +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | SUMMARY = "Xilinx Platform Headers" | ||
2 | DESCRPTION = "Xilinx ps*_init_gpl.c/h platform init code, used for building u-boot-spl and fsbl" | ||
3 | HOMEPAGE = "http://www.xilinx.com" | ||
4 | SECTION = "bsp" | ||
5 | |||
6 | INHIBIT_DEFAULT_DEPS = "1" | ||
7 | |||
8 | PACKAGE_ARCH = "${MACHINE_ARCH}" | ||
9 | |||
10 | inherit xilinx-platform-init | ||
11 | |||
12 | COMPATIBLE_MACHINE = "$^" | ||
13 | COMPATIBLE_MACHINE_picozed-zynq7 = "picozed-zynq7" | ||
14 | |||
15 | LICENSE = "GPLv2+" | ||
16 | LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6" | ||
17 | |||
18 | PROVIDES += "virtual/xilinx-platform-init" | ||
19 | |||
20 | SRC_URI = "${@" ".join(["file://%s" % f for f in (d.getVar('PLATFORM_INIT_FILES') or "").split()])}" | ||
21 | |||
22 | S = "${WORKDIR}" | ||
23 | |||
24 | SYSROOT_DIRS += "${PLATFORM_INIT_DIR}" | ||
25 | |||
26 | do_compile() { | ||
27 | : | ||
28 | } | ||
29 | |||
30 | do_install() { | ||
31 | install -d ${D}${PLATFORM_INIT_DIR} | ||
32 | for i in ${PLATFORM_INIT_FILES}; do | ||
33 | install -m 0644 ${S}/$i ${D}${PLATFORM_INIT_DIR}/ | ||
34 | done | ||
35 | } | ||
36 | |||
37 | FILES:${PN} += "${PLATFORM_INIT_DIR}/*" | ||
38 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c deleted file mode 100644 index 5587ab25..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c +++ /dev/null | |||
@@ -1,13191 +0,0 @@ | |||
1 | /****************************************************************************** | ||
2 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License along | ||
15 | * with this program; if not, see <http://www.gnu.org/licenses/> | ||
16 | * | ||
17 | * | ||
18 | ******************************************************************************/ | ||
19 | /****************************************************************************/ | ||
20 | /** | ||
21 | * | ||
22 | * @file ps7_init_gpl.c | ||
23 | * | ||
24 | * This file is automatically generated | ||
25 | * | ||
26 | *****************************************************************************/ | ||
27 | |||
28 | #include "ps7_init_gpl.h" | ||
29 | |||
30 | unsigned long ps7_pll_init_data_3_0[] = { | ||
31 | // START: top | ||
32 | // .. START: SLCR SETTINGS | ||
33 | // .. UNLOCK_KEY = 0XDF0D | ||
34 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
35 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
36 | // .. | ||
37 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
38 | // .. FINISH: SLCR SETTINGS | ||
39 | // .. START: PLL SLCR REGISTERS | ||
40 | // .. .. START: ARM PLL INIT | ||
41 | // .. .. PLL_RES = 0x4 | ||
42 | // .. .. ==> 0XF8000110[7:4] = 0x00000004U | ||
43 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
44 | // .. .. PLL_CP = 0x2 | ||
45 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
46 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
47 | // .. .. LOCK_CNT = 0xfa | ||
48 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | ||
49 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
50 | // .. .. | ||
51 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), | ||
52 | // .. .. .. START: UPDATE FB_DIV | ||
53 | // .. .. .. PLL_FDIV = 0x3c | ||
54 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU | ||
55 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
56 | // .. .. .. | ||
57 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), | ||
58 | // .. .. .. FINISH: UPDATE FB_DIV | ||
59 | // .. .. .. START: BY PASS PLL | ||
60 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
61 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
62 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
63 | // .. .. .. | ||
64 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
65 | // .. .. .. FINISH: BY PASS PLL | ||
66 | // .. .. .. START: ASSERT RESET | ||
67 | // .. .. .. PLL_RESET = 1 | ||
68 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
69 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
70 | // .. .. .. | ||
71 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
72 | // .. .. .. FINISH: ASSERT RESET | ||
73 | // .. .. .. START: DEASSERT RESET | ||
74 | // .. .. .. PLL_RESET = 0 | ||
75 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
76 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
77 | // .. .. .. | ||
78 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
79 | // .. .. .. FINISH: DEASSERT RESET | ||
80 | // .. .. .. START: CHECK PLL STATUS | ||
81 | // .. .. .. ARM_PLL_LOCK = 1 | ||
82 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
83 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
84 | // .. .. .. | ||
85 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
86 | // .. .. .. FINISH: CHECK PLL STATUS | ||
87 | // .. .. .. START: REMOVE PLL BY PASS | ||
88 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
89 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
90 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
91 | // .. .. .. | ||
92 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
93 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
94 | // .. .. .. SRCSEL = 0x0 | ||
95 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
96 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
97 | // .. .. .. DIVISOR = 0x3 | ||
98 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U | ||
99 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U | ||
100 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
101 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
102 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
103 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
104 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
105 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
106 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
107 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
108 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
109 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
110 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
111 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
112 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
113 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
114 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
115 | // .. .. .. | ||
116 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), | ||
117 | // .. .. FINISH: ARM PLL INIT | ||
118 | // .. .. START: DDR PLL INIT | ||
119 | // .. .. PLL_RES = 0x2 | ||
120 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | ||
121 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
122 | // .. .. PLL_CP = 0x2 | ||
123 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
124 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
125 | // .. .. LOCK_CNT = 0x12c | ||
126 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | ||
127 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | ||
128 | // .. .. | ||
129 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | ||
130 | // .. .. .. START: UPDATE FB_DIV | ||
131 | // .. .. .. PLL_FDIV = 0x20 | ||
132 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | ||
133 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | ||
134 | // .. .. .. | ||
135 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | ||
136 | // .. .. .. FINISH: UPDATE FB_DIV | ||
137 | // .. .. .. START: BY PASS PLL | ||
138 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
139 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
140 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
141 | // .. .. .. | ||
142 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
143 | // .. .. .. FINISH: BY PASS PLL | ||
144 | // .. .. .. START: ASSERT RESET | ||
145 | // .. .. .. PLL_RESET = 1 | ||
146 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
147 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
148 | // .. .. .. | ||
149 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
150 | // .. .. .. FINISH: ASSERT RESET | ||
151 | // .. .. .. START: DEASSERT RESET | ||
152 | // .. .. .. PLL_RESET = 0 | ||
153 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
154 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
155 | // .. .. .. | ||
156 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
157 | // .. .. .. FINISH: DEASSERT RESET | ||
158 | // .. .. .. START: CHECK PLL STATUS | ||
159 | // .. .. .. DDR_PLL_LOCK = 1 | ||
160 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
161 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
162 | // .. .. .. | ||
163 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
164 | // .. .. .. FINISH: CHECK PLL STATUS | ||
165 | // .. .. .. START: REMOVE PLL BY PASS | ||
166 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
167 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
168 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
169 | // .. .. .. | ||
170 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
171 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
172 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
173 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
174 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
175 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
176 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
177 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
178 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
179 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
180 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
181 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
182 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
183 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
184 | // .. .. .. | ||
185 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
186 | // .. .. FINISH: DDR PLL INIT | ||
187 | // .. .. START: IO PLL INIT | ||
188 | // .. .. PLL_RES = 0x4 | ||
189 | // .. .. ==> 0XF8000118[7:4] = 0x00000004U | ||
190 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
191 | // .. .. PLL_CP = 0x2 | ||
192 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
193 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
194 | // .. .. LOCK_CNT = 0xfa | ||
195 | // .. .. ==> 0XF8000118[21:12] = 0x000000FAU | ||
196 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
197 | // .. .. | ||
198 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), | ||
199 | // .. .. .. START: UPDATE FB_DIV | ||
200 | // .. .. .. PLL_FDIV = 0x3c | ||
201 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU | ||
202 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
203 | // .. .. .. | ||
204 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), | ||
205 | // .. .. .. FINISH: UPDATE FB_DIV | ||
206 | // .. .. .. START: BY PASS PLL | ||
207 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
208 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
209 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
210 | // .. .. .. | ||
211 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
212 | // .. .. .. FINISH: BY PASS PLL | ||
213 | // .. .. .. START: ASSERT RESET | ||
214 | // .. .. .. PLL_RESET = 1 | ||
215 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
216 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
217 | // .. .. .. | ||
218 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
219 | // .. .. .. FINISH: ASSERT RESET | ||
220 | // .. .. .. START: DEASSERT RESET | ||
221 | // .. .. .. PLL_RESET = 0 | ||
222 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
223 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
224 | // .. .. .. | ||
225 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
226 | // .. .. .. FINISH: DEASSERT RESET | ||
227 | // .. .. .. START: CHECK PLL STATUS | ||
228 | // .. .. .. IO_PLL_LOCK = 1 | ||
229 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
230 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
231 | // .. .. .. | ||
232 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
233 | // .. .. .. FINISH: CHECK PLL STATUS | ||
234 | // .. .. .. START: REMOVE PLL BY PASS | ||
235 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
236 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
237 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
238 | // .. .. .. | ||
239 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
240 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
241 | // .. .. FINISH: IO PLL INIT | ||
242 | // .. FINISH: PLL SLCR REGISTERS | ||
243 | // .. START: LOCK IT BACK | ||
244 | // .. LOCK_KEY = 0X767B | ||
245 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
246 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
247 | // .. | ||
248 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
249 | // .. FINISH: LOCK IT BACK | ||
250 | // FINISH: top | ||
251 | // | ||
252 | EMIT_EXIT(), | ||
253 | |||
254 | // | ||
255 | }; | ||
256 | |||
257 | unsigned long ps7_clock_init_data_3_0[] = { | ||
258 | // START: top | ||
259 | // .. START: SLCR SETTINGS | ||
260 | // .. UNLOCK_KEY = 0XDF0D | ||
261 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
262 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
263 | // .. | ||
264 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
265 | // .. FINISH: SLCR SETTINGS | ||
266 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
267 | // .. CLKACT = 0x1 | ||
268 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
269 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
270 | // .. DIVISOR0 = 0x23 | ||
271 | // .. ==> 0XF8000128[13:8] = 0x00000023U | ||
272 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | ||
273 | // .. DIVISOR1 = 0x3 | ||
274 | // .. ==> 0XF8000128[25:20] = 0x00000003U | ||
275 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | ||
276 | // .. | ||
277 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | ||
278 | // .. CLKACT = 0x1 | ||
279 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
280 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
281 | // .. SRCSEL = 0x0 | ||
282 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
283 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
284 | // .. | ||
285 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
286 | // .. CLKACT = 0x1 | ||
287 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
288 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
289 | // .. SRCSEL = 0x0 | ||
290 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
291 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
292 | // .. DIVISOR = 0x10 | ||
293 | // .. ==> 0XF8000140[13:8] = 0x00000010U | ||
294 | // .. ==> MASK : 0x00003F00U VAL : 0x00001000U | ||
295 | // .. DIVISOR1 = 0x1 | ||
296 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
297 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
298 | // .. | ||
299 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), | ||
300 | // .. CLKACT = 0x1 | ||
301 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
302 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
303 | // .. SRCSEL = 0x0 | ||
304 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
305 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
306 | // .. DIVISOR = 0xa | ||
307 | // .. ==> 0XF800014C[13:8] = 0x0000000AU | ||
308 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
309 | // .. | ||
310 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), | ||
311 | // .. CLKACT0 = 0x0 | ||
312 | // .. ==> 0XF8000150[0:0] = 0x00000000U | ||
313 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
314 | // .. CLKACT1 = 0x1 | ||
315 | // .. ==> 0XF8000150[1:1] = 0x00000001U | ||
316 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
317 | // .. SRCSEL = 0x0 | ||
318 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
319 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
320 | // .. DIVISOR = 0x28 | ||
321 | // .. ==> 0XF8000150[13:8] = 0x00000028U | ||
322 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
323 | // .. | ||
324 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), | ||
325 | // .. CLKACT0 = 0x0 | ||
326 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
327 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
328 | // .. CLKACT1 = 0x1 | ||
329 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
330 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
331 | // .. SRCSEL = 0x0 | ||
332 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
333 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
334 | // .. DIVISOR = 0x28 | ||
335 | // .. ==> 0XF8000154[13:8] = 0x00000028U | ||
336 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
337 | // .. | ||
338 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), | ||
339 | // .. .. START: TRACE CLOCK | ||
340 | // .. .. FINISH: TRACE CLOCK | ||
341 | // .. .. CLKACT = 0x1 | ||
342 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
343 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
344 | // .. .. SRCSEL = 0x0 | ||
345 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
346 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
347 | // .. .. DIVISOR = 0xa | ||
348 | // .. .. ==> 0XF8000168[13:8] = 0x0000000AU | ||
349 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
350 | // .. .. | ||
351 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), | ||
352 | // .. .. SRCSEL = 0x0 | ||
353 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
354 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
355 | // .. .. DIVISOR0 = 0x14 | ||
356 | // .. .. ==> 0XF8000170[13:8] = 0x00000014U | ||
357 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
358 | // .. .. DIVISOR1 = 0x1 | ||
359 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
360 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
361 | // .. .. | ||
362 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), | ||
363 | // .. .. SRCSEL = 0x0 | ||
364 | // .. .. ==> 0XF8000180[5:4] = 0x00000000U | ||
365 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
366 | // .. .. DIVISOR0 = 0x14 | ||
367 | // .. .. ==> 0XF8000180[13:8] = 0x00000014U | ||
368 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
369 | // .. .. DIVISOR1 = 0x1 | ||
370 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
371 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
372 | // .. .. | ||
373 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), | ||
374 | // .. .. SRCSEL = 0x0 | ||
375 | // .. .. ==> 0XF8000190[5:4] = 0x00000000U | ||
376 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
377 | // .. .. DIVISOR0 = 0x3c | ||
378 | // .. .. ==> 0XF8000190[13:8] = 0x0000003CU | ||
379 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U | ||
380 | // .. .. DIVISOR1 = 0x1 | ||
381 | // .. .. ==> 0XF8000190[25:20] = 0x00000001U | ||
382 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
383 | // .. .. | ||
384 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), | ||
385 | // .. .. SRCSEL = 0x0 | ||
386 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
387 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
388 | // .. .. DIVISOR0 = 0x28 | ||
389 | // .. .. ==> 0XF80001A0[13:8] = 0x00000028U | ||
390 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
391 | // .. .. DIVISOR1 = 0x1 | ||
392 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
393 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
394 | // .. .. | ||
395 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), | ||
396 | // .. .. CLK_621_TRUE = 0x1 | ||
397 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
398 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
399 | // .. .. | ||
400 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
401 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
402 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
403 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
404 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
405 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
406 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
407 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
408 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
409 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
410 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
411 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
412 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
413 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
414 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
415 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
416 | // .. .. SDI0_CPU_1XCLKACT = 0x0 | ||
417 | // .. .. ==> 0XF800012C[10:10] = 0x00000000U | ||
418 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
419 | // .. .. SDI1_CPU_1XCLKACT = 0x1 | ||
420 | // .. .. ==> 0XF800012C[11:11] = 0x00000001U | ||
421 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U | ||
422 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
423 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
424 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
425 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
426 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
427 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
428 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
429 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
430 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
431 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
432 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
433 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
434 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
435 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
436 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
437 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
438 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
439 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
440 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
441 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
442 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
443 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
444 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
445 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
446 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
447 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
448 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
449 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
450 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
451 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
452 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
453 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
454 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
455 | // .. .. | ||
456 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), | ||
457 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
458 | // .. START: THIS SHOULD BE BLANK | ||
459 | // .. FINISH: THIS SHOULD BE BLANK | ||
460 | // .. START: LOCK IT BACK | ||
461 | // .. LOCK_KEY = 0X767B | ||
462 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
463 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
464 | // .. | ||
465 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
466 | // .. FINISH: LOCK IT BACK | ||
467 | // FINISH: top | ||
468 | // | ||
469 | EMIT_EXIT(), | ||
470 | |||
471 | // | ||
472 | }; | ||
473 | |||
474 | unsigned long ps7_ddr_init_data_3_0[] = { | ||
475 | // START: top | ||
476 | // .. START: DDR INITIALIZATION | ||
477 | // .. .. START: LOCK DDR | ||
478 | // .. .. reg_ddrc_soft_rstb = 0 | ||
479 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
480 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
481 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
482 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
483 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
484 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
485 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
486 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
487 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
488 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
489 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
490 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
491 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
492 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
493 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
494 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
495 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
496 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
497 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
498 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
499 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
500 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
501 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
502 | // .. .. | ||
503 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
504 | // .. .. FINISH: LOCK DDR | ||
505 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | ||
506 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | ||
507 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | ||
508 | // .. .. reserved_reg_ddrc_active_ranks = 0x1 | ||
509 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
510 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
511 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
512 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
513 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
514 | // .. .. | ||
515 | EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), | ||
516 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
517 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
518 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
519 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
520 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
521 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
522 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
523 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
524 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
525 | // .. .. | ||
526 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
527 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
528 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
529 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
530 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
531 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
532 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
533 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
534 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
535 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
536 | // .. .. | ||
537 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
538 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
539 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
540 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
541 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
542 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
543 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
544 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
545 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
546 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
547 | // .. .. | ||
548 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
549 | // .. .. reg_ddrc_t_rc = 0x1a | ||
550 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
551 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
552 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | ||
553 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | ||
554 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | ||
555 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
556 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
557 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
558 | // .. .. | ||
559 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | ||
560 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
561 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
562 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
563 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
564 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
565 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
566 | // .. .. reg_ddrc_t_faw = 0x16 | ||
567 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | ||
568 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | ||
569 | // .. .. reg_ddrc_t_ras_max = 0x24 | ||
570 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | ||
571 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | ||
572 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
573 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
574 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
575 | // .. .. reg_ddrc_t_cke = 0x4 | ||
576 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
577 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
578 | // .. .. | ||
579 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | ||
580 | // .. .. reg_ddrc_write_latency = 0x5 | ||
581 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
582 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
583 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
584 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
585 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
586 | // .. .. reg_ddrc_wr2rd = 0xe | ||
587 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
588 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
589 | // .. .. reg_ddrc_t_xp = 0x4 | ||
590 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
591 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
592 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
593 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
594 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
595 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
596 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
597 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
598 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
599 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
600 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
601 | // .. .. | ||
602 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
603 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
604 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
605 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
606 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
607 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
608 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
609 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
610 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
611 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
612 | // .. .. reg_ddrc_t_rp = 0x7 | ||
613 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
614 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
615 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
616 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
617 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
618 | // .. .. reg_ddrc_mobile = 0x0 | ||
619 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
620 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
621 | // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 | ||
622 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
623 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
624 | // .. .. reg_ddrc_read_latency = 0x7 | ||
625 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
626 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
627 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
628 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
629 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
630 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
631 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
632 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
633 | // .. .. | ||
634 | EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), | ||
635 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
636 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
637 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
638 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
639 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
640 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
641 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
642 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
643 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
644 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
645 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
646 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
647 | // .. .. reg_ddrc_mr_data = 0x0 | ||
648 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
649 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
650 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
651 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
652 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
653 | // .. .. reg_ddrc_mr_type = 0x0 | ||
654 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
655 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
656 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
657 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
658 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
659 | // .. .. | ||
660 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), | ||
661 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
662 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
663 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
664 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
665 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
666 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
667 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
668 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
669 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
670 | // .. .. | ||
671 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
672 | // .. .. reg_ddrc_emr2 = 0x8 | ||
673 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
674 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
675 | // .. .. reg_ddrc_emr3 = 0x0 | ||
676 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
677 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
678 | // .. .. | ||
679 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
680 | // .. .. reg_ddrc_mr = 0x930 | ||
681 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
682 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
683 | // .. .. reg_ddrc_emr = 0x4 | ||
684 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
685 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
686 | // .. .. | ||
687 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
688 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
689 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
690 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
691 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | ||
692 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | ||
693 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | ||
694 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
695 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
696 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
697 | // .. .. reg_ddrc_burstchop = 0x0 | ||
698 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
699 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
700 | // .. .. | ||
701 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | ||
702 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
703 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
704 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
705 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
706 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
707 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
708 | // .. .. | ||
709 | EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), | ||
710 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
711 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
712 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
713 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
714 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
715 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
716 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
717 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
718 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
719 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
720 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
721 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
722 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
723 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
724 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
725 | // .. .. | ||
726 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
727 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
728 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
729 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
730 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
731 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
732 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
733 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
734 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
735 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
736 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
737 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
738 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
739 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
740 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
741 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
742 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
743 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
744 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
745 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
746 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
747 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
748 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
749 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
750 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
751 | // .. .. | ||
752 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
753 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
754 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
755 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
756 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
757 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
758 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
759 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
760 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
761 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
762 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
763 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
764 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
765 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
766 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
767 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
768 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | ||
769 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | ||
770 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | ||
771 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
772 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
773 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
774 | // .. .. | ||
775 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | ||
776 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
777 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
778 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
779 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
780 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
781 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
782 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
783 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
784 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
785 | // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 | ||
786 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
787 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
788 | // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 | ||
789 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
790 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
791 | // .. .. | ||
792 | EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), | ||
793 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
794 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
795 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
796 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
797 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
798 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
799 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
800 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
801 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
802 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
803 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
804 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
805 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
806 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
807 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
808 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
809 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
810 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
811 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
812 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
813 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
814 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
815 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
816 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
817 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
818 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
819 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
820 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
821 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
822 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
823 | // .. .. | ||
824 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
825 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
826 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
827 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
828 | // .. .. | ||
829 | EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), | ||
830 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
831 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
832 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
833 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
834 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
835 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
836 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
837 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
838 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
839 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
840 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
841 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
842 | // .. .. | ||
843 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
844 | // .. .. reg_ddrc_pageclose = 0x0 | ||
845 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
846 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
847 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
848 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
849 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
850 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
851 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
852 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
853 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
854 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
855 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
856 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
857 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
858 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
859 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
860 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
861 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
862 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
863 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
864 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
865 | // .. .. | ||
866 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
867 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
868 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
869 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
870 | // .. .. reg_arb_go2critical_en = 0x1 | ||
871 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
872 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
873 | // .. .. | ||
874 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
875 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
876 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
877 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
878 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
879 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
880 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
881 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
882 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
883 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
884 | // .. .. | ||
885 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
886 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
887 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
888 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
889 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
890 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
891 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
892 | // .. .. | ||
893 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
894 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | ||
895 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | ||
896 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | ||
897 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | ||
898 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | ||
899 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | ||
900 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | ||
901 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | ||
902 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | ||
903 | // .. .. reg_ddrc_t_cksre = 0x6 | ||
904 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | ||
905 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
906 | // .. .. reg_ddrc_t_cksrx = 0x6 | ||
907 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | ||
908 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
909 | // .. .. reg_ddrc_t_ckesr = 0x4 | ||
910 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | ||
911 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | ||
912 | // .. .. | ||
913 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | ||
914 | // .. .. reg_ddrc_t_ckpde = 0x2 | ||
915 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | ||
916 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | ||
917 | // .. .. reg_ddrc_t_ckpdx = 0x2 | ||
918 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | ||
919 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
920 | // .. .. reg_ddrc_t_ckdpde = 0x2 | ||
921 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | ||
922 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
923 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | ||
924 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | ||
925 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | ||
926 | // .. .. reg_ddrc_t_ckcsx = 0x3 | ||
927 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | ||
928 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | ||
929 | // .. .. | ||
930 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | ||
931 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
932 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
933 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
934 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
935 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
936 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
937 | // .. .. reg_ddrc_t_mod = 0x200 | ||
938 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
939 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
940 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
941 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
942 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
943 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
944 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
945 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
946 | // .. .. | ||
947 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
948 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | ||
949 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | ||
950 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | ||
951 | // .. .. dram_rstn_x1024 = 0x69 | ||
952 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | ||
953 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | ||
954 | // .. .. | ||
955 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | ||
956 | // .. .. deeppowerdown_en = 0x0 | ||
957 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
958 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
959 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
960 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
961 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
962 | // .. .. | ||
963 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
964 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
965 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
966 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
967 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
968 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
969 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
970 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
971 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
972 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
973 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
974 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
975 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
976 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
977 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
978 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
979 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
980 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
981 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
982 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
983 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
984 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
985 | // .. .. | ||
986 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
987 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
988 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
989 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
990 | // .. .. | ||
991 | EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), | ||
992 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
993 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
994 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
995 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
996 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
997 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
998 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
999 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
1000 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
1001 | // .. .. | ||
1002 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
1003 | // .. .. START: RESET ECC ERROR | ||
1004 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
1005 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
1006 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1007 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
1008 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
1009 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
1010 | // .. .. | ||
1011 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
1012 | // .. .. FINISH: RESET ECC ERROR | ||
1013 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
1014 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
1015 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1016 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
1017 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
1018 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1019 | // .. .. | ||
1020 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
1021 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
1022 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
1023 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1024 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
1025 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
1026 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
1027 | // .. .. | ||
1028 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
1029 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
1030 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
1031 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1032 | // .. .. | ||
1033 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
1034 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
1035 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
1036 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
1037 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
1038 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
1039 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
1040 | // .. .. | ||
1041 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
1042 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
1043 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
1044 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
1045 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
1046 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
1047 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
1048 | // .. .. | ||
1049 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
1050 | // .. .. reg_phy_dif_on = 0x0 | ||
1051 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
1052 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
1053 | // .. .. reg_phy_dif_off = 0x0 | ||
1054 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
1055 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
1056 | // .. .. | ||
1057 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
1058 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
1059 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
1060 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1061 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
1062 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
1063 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1064 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
1065 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
1066 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1067 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
1068 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
1069 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1070 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
1071 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
1072 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
1073 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
1074 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
1075 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
1076 | // .. .. reg_phy_dq_offset = 0x40 | ||
1077 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
1078 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
1079 | // .. .. | ||
1080 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), | ||
1081 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
1082 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
1083 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1084 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
1085 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
1086 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1087 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
1088 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
1089 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1090 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
1091 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
1092 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1093 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
1094 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
1095 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
1096 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
1097 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
1098 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
1099 | // .. .. reg_phy_dq_offset = 0x40 | ||
1100 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
1101 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
1102 | // .. .. | ||
1103 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), | ||
1104 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
1105 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
1106 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1107 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
1108 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
1109 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1110 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
1111 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
1112 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1113 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
1114 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
1115 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1116 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
1117 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
1118 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
1119 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
1120 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
1121 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
1122 | // .. .. reg_phy_dq_offset = 0x40 | ||
1123 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
1124 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
1125 | // .. .. | ||
1126 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), | ||
1127 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
1128 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
1129 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1130 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
1131 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
1132 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1133 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
1134 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
1135 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1136 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
1137 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
1138 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1139 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
1140 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
1141 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
1142 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
1143 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
1144 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
1145 | // .. .. reg_phy_dq_offset = 0x40 | ||
1146 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
1147 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
1148 | // .. .. | ||
1149 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), | ||
1150 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
1151 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
1152 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
1153 | // .. .. reg_phy_gatelvl_init_ratio = 0xa1 | ||
1154 | // .. .. ==> 0XF800612C[19:10] = 0x000000A1U | ||
1155 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U | ||
1156 | // .. .. | ||
1157 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), | ||
1158 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
1159 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
1160 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
1161 | // .. .. reg_phy_gatelvl_init_ratio = 0xa0 | ||
1162 | // .. .. ==> 0XF8006130[19:10] = 0x000000A0U | ||
1163 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U | ||
1164 | // .. .. | ||
1165 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), | ||
1166 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
1167 | // .. .. ==> 0XF8006134[9:0] = 0x00000007U | ||
1168 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
1169 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
1170 | // .. .. ==> 0XF8006134[19:10] = 0x000000ADU | ||
1171 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
1172 | // .. .. | ||
1173 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), | ||
1174 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
1175 | // .. .. ==> 0XF8006138[9:0] = 0x00000007U | ||
1176 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
1177 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
1178 | // .. .. ==> 0XF8006138[19:10] = 0x000000ADU | ||
1179 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
1180 | // .. .. | ||
1181 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), | ||
1182 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
1183 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
1184 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
1185 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
1186 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
1187 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1188 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
1189 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
1190 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1191 | // .. .. | ||
1192 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
1193 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
1194 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
1195 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
1196 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
1197 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
1198 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1199 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
1200 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
1201 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1202 | // .. .. | ||
1203 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
1204 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
1205 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
1206 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
1207 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
1208 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
1209 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1210 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
1211 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
1212 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1213 | // .. .. | ||
1214 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
1215 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
1216 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
1217 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
1218 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
1219 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
1220 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1221 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
1222 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
1223 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1224 | // .. .. | ||
1225 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
1226 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
1227 | // .. .. ==> 0XF8006154[9:0] = 0x0000007CU | ||
1228 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
1229 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
1230 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
1231 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1232 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
1233 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
1234 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1235 | // .. .. | ||
1236 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), | ||
1237 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
1238 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
1239 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
1240 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
1241 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
1242 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1243 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
1244 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
1245 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1246 | // .. .. | ||
1247 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
1248 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
1249 | // .. .. ==> 0XF800615C[9:0] = 0x00000087U | ||
1250 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
1251 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
1252 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
1253 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1254 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
1255 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
1256 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1257 | // .. .. | ||
1258 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), | ||
1259 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
1260 | // .. .. ==> 0XF8006160[9:0] = 0x00000087U | ||
1261 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
1262 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
1263 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
1264 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1265 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
1266 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
1267 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1268 | // .. .. | ||
1269 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), | ||
1270 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 | ||
1271 | // .. .. ==> 0XF8006168[10:0] = 0x000000F6U | ||
1272 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U | ||
1273 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
1274 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
1275 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1276 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
1277 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
1278 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
1279 | // .. .. | ||
1280 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), | ||
1281 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 | ||
1282 | // .. .. ==> 0XF800616C[10:0] = 0x000000F5U | ||
1283 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U | ||
1284 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
1285 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
1286 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1287 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
1288 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
1289 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
1290 | // .. .. | ||
1291 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), | ||
1292 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
1293 | // .. .. ==> 0XF8006170[10:0] = 0x00000102U | ||
1294 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
1295 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
1296 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
1297 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1298 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
1299 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
1300 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
1301 | // .. .. | ||
1302 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), | ||
1303 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
1304 | // .. .. ==> 0XF8006174[10:0] = 0x00000102U | ||
1305 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
1306 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
1307 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
1308 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1309 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
1310 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
1311 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
1312 | // .. .. | ||
1313 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), | ||
1314 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
1315 | // .. .. ==> 0XF800617C[9:0] = 0x000000BCU | ||
1316 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
1317 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
1318 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
1319 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1320 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
1321 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
1322 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1323 | // .. .. | ||
1324 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), | ||
1325 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
1326 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
1327 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
1328 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
1329 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
1330 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1331 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
1332 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
1333 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1334 | // .. .. | ||
1335 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
1336 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
1337 | // .. .. ==> 0XF8006184[9:0] = 0x000000C7U | ||
1338 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
1339 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
1340 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
1341 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1342 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
1343 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
1344 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1345 | // .. .. | ||
1346 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), | ||
1347 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
1348 | // .. .. ==> 0XF8006188[9:0] = 0x000000C7U | ||
1349 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
1350 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
1351 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
1352 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
1353 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
1354 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
1355 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
1356 | // .. .. | ||
1357 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), | ||
1358 | // .. .. reg_phy_bl2 = 0x0 | ||
1359 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
1360 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1361 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
1362 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
1363 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1364 | // .. .. reg_phy_bist_enable = 0x0 | ||
1365 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
1366 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1367 | // .. .. reg_phy_bist_force_err = 0x0 | ||
1368 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
1369 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
1370 | // .. .. reg_phy_bist_mode = 0x0 | ||
1371 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
1372 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
1373 | // .. .. reg_phy_invert_clkout = 0x1 | ||
1374 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
1375 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
1376 | // .. .. reg_phy_sel_logic = 0x0 | ||
1377 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
1378 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
1379 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
1380 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
1381 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
1382 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
1383 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
1384 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
1385 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
1386 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
1387 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
1388 | // .. .. reg_phy_lpddr = 0x0 | ||
1389 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
1390 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
1391 | // .. .. reg_phy_cmd_latency = 0x0 | ||
1392 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
1393 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
1394 | // .. .. | ||
1395 | EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), | ||
1396 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
1397 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
1398 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
1399 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
1400 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
1401 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
1402 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
1403 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
1404 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
1405 | // .. .. reg_phy_use_wr_level = 0x1 | ||
1406 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
1407 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
1408 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
1409 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
1410 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
1411 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
1412 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
1413 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
1414 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
1415 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
1416 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1417 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
1418 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
1419 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
1420 | // .. .. | ||
1421 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
1422 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
1423 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
1424 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
1425 | // .. .. | ||
1426 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
1427 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
1428 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
1429 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1430 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
1431 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
1432 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1433 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
1434 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
1435 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1436 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
1437 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
1438 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1439 | // .. .. | ||
1440 | EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), | ||
1441 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
1442 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
1443 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1444 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
1445 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
1446 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1447 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
1448 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
1449 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1450 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
1451 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
1452 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1453 | // .. .. | ||
1454 | EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), | ||
1455 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
1456 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
1457 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1458 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
1459 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
1460 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1461 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
1462 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
1463 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1464 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
1465 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
1466 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1467 | // .. .. | ||
1468 | EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), | ||
1469 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
1470 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
1471 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1472 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
1473 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
1474 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1475 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
1476 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
1477 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1478 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
1479 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
1480 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1481 | // .. .. | ||
1482 | EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), | ||
1483 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
1484 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
1485 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1486 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
1487 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
1488 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1489 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
1490 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
1491 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1492 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
1493 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
1494 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1495 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
1496 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
1497 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
1498 | // .. .. | ||
1499 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
1500 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
1501 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
1502 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1503 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
1504 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
1505 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1506 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
1507 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
1508 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1509 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
1510 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
1511 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1512 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
1513 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
1514 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
1515 | // .. .. | ||
1516 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
1517 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
1518 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
1519 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1520 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
1521 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
1522 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1523 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
1524 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
1525 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1526 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
1527 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
1528 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1529 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
1530 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
1531 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
1532 | // .. .. | ||
1533 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
1534 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
1535 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
1536 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
1537 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
1538 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
1539 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1540 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
1541 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
1542 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
1543 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
1544 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
1545 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
1546 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
1547 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
1548 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
1549 | // .. .. | ||
1550 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
1551 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
1552 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
1553 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1554 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
1555 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
1556 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1557 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
1558 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
1559 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
1560 | // .. .. | ||
1561 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), | ||
1562 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
1563 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
1564 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
1565 | // .. .. | ||
1566 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
1567 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
1568 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
1569 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
1570 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
1571 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
1572 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
1573 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
1574 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
1575 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
1576 | // .. .. | ||
1577 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
1578 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | ||
1579 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | ||
1580 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | ||
1581 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
1582 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
1583 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
1584 | // .. .. | ||
1585 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | ||
1586 | // .. .. START: POLL ON DCI STATUS | ||
1587 | // .. .. DONE = 1 | ||
1588 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
1589 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
1590 | // .. .. | ||
1591 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
1592 | // .. .. FINISH: POLL ON DCI STATUS | ||
1593 | // .. .. START: UNLOCK DDR | ||
1594 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
1595 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
1596 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1597 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
1598 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
1599 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
1600 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
1601 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
1602 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
1603 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
1604 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
1605 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
1606 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
1607 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
1608 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
1609 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
1610 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
1611 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
1612 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
1613 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
1614 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
1615 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
1616 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
1617 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
1618 | // .. .. | ||
1619 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
1620 | // .. .. FINISH: UNLOCK DDR | ||
1621 | // .. .. START: CHECK DDR STATUS | ||
1622 | // .. .. ddrc_reg_operating_mode = 1 | ||
1623 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
1624 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
1625 | // .. .. | ||
1626 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
1627 | // .. .. FINISH: CHECK DDR STATUS | ||
1628 | // .. FINISH: DDR INITIALIZATION | ||
1629 | // FINISH: top | ||
1630 | // | ||
1631 | EMIT_EXIT(), | ||
1632 | |||
1633 | // | ||
1634 | }; | ||
1635 | |||
1636 | unsigned long ps7_mio_init_data_3_0[] = { | ||
1637 | // START: top | ||
1638 | // .. START: SLCR SETTINGS | ||
1639 | // .. UNLOCK_KEY = 0XDF0D | ||
1640 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
1641 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
1642 | // .. | ||
1643 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
1644 | // .. FINISH: SLCR SETTINGS | ||
1645 | // .. START: OCM REMAPPING | ||
1646 | // .. FINISH: OCM REMAPPING | ||
1647 | // .. START: DDRIOB SETTINGS | ||
1648 | // .. reserved_INP_POWER = 0x0 | ||
1649 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
1650 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1651 | // .. INP_TYPE = 0x0 | ||
1652 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
1653 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
1654 | // .. DCI_UPDATE_B = 0x0 | ||
1655 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
1656 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1657 | // .. TERM_EN = 0x0 | ||
1658 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
1659 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
1660 | // .. DCI_TYPE = 0x0 | ||
1661 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
1662 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
1663 | // .. IBUF_DISABLE_MODE = 0x0 | ||
1664 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
1665 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1666 | // .. TERM_DISABLE_MODE = 0x0 | ||
1667 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
1668 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1669 | // .. OUTPUT_EN = 0x3 | ||
1670 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
1671 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1672 | // .. PULLUP_EN = 0x0 | ||
1673 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
1674 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1675 | // .. | ||
1676 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
1677 | // .. reserved_INP_POWER = 0x0 | ||
1678 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
1679 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1680 | // .. INP_TYPE = 0x0 | ||
1681 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
1682 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
1683 | // .. DCI_UPDATE_B = 0x0 | ||
1684 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
1685 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1686 | // .. TERM_EN = 0x0 | ||
1687 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
1688 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
1689 | // .. DCI_TYPE = 0x0 | ||
1690 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
1691 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
1692 | // .. IBUF_DISABLE_MODE = 0x0 | ||
1693 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
1694 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1695 | // .. TERM_DISABLE_MODE = 0x0 | ||
1696 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
1697 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1698 | // .. OUTPUT_EN = 0x3 | ||
1699 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
1700 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1701 | // .. PULLUP_EN = 0x0 | ||
1702 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
1703 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1704 | // .. | ||
1705 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
1706 | // .. reserved_INP_POWER = 0x0 | ||
1707 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
1708 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1709 | // .. INP_TYPE = 0x1 | ||
1710 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
1711 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
1712 | // .. DCI_UPDATE_B = 0x0 | ||
1713 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
1714 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1715 | // .. TERM_EN = 0x1 | ||
1716 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
1717 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
1718 | // .. DCI_TYPE = 0x3 | ||
1719 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
1720 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
1721 | // .. IBUF_DISABLE_MODE = 0 | ||
1722 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
1723 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1724 | // .. TERM_DISABLE_MODE = 0 | ||
1725 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
1726 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1727 | // .. OUTPUT_EN = 0x3 | ||
1728 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
1729 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1730 | // .. PULLUP_EN = 0x0 | ||
1731 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
1732 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1733 | // .. | ||
1734 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
1735 | // .. reserved_INP_POWER = 0x0 | ||
1736 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
1737 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1738 | // .. INP_TYPE = 0x1 | ||
1739 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
1740 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
1741 | // .. DCI_UPDATE_B = 0x0 | ||
1742 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
1743 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1744 | // .. TERM_EN = 0x1 | ||
1745 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
1746 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
1747 | // .. DCI_TYPE = 0x3 | ||
1748 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
1749 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
1750 | // .. IBUF_DISABLE_MODE = 0 | ||
1751 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
1752 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1753 | // .. TERM_DISABLE_MODE = 0 | ||
1754 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
1755 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1756 | // .. OUTPUT_EN = 0x3 | ||
1757 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
1758 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1759 | // .. PULLUP_EN = 0x0 | ||
1760 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
1761 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1762 | // .. | ||
1763 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
1764 | // .. reserved_INP_POWER = 0x0 | ||
1765 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
1766 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1767 | // .. INP_TYPE = 0x2 | ||
1768 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
1769 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
1770 | // .. DCI_UPDATE_B = 0x0 | ||
1771 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
1772 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1773 | // .. TERM_EN = 0x1 | ||
1774 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
1775 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
1776 | // .. DCI_TYPE = 0x3 | ||
1777 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
1778 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
1779 | // .. IBUF_DISABLE_MODE = 0 | ||
1780 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
1781 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1782 | // .. TERM_DISABLE_MODE = 0 | ||
1783 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
1784 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1785 | // .. OUTPUT_EN = 0x3 | ||
1786 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
1787 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1788 | // .. PULLUP_EN = 0x0 | ||
1789 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
1790 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1791 | // .. | ||
1792 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
1793 | // .. reserved_INP_POWER = 0x0 | ||
1794 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
1795 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1796 | // .. INP_TYPE = 0x2 | ||
1797 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
1798 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
1799 | // .. DCI_UPDATE_B = 0x0 | ||
1800 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
1801 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1802 | // .. TERM_EN = 0x1 | ||
1803 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
1804 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
1805 | // .. DCI_TYPE = 0x3 | ||
1806 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
1807 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
1808 | // .. IBUF_DISABLE_MODE = 0 | ||
1809 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
1810 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1811 | // .. TERM_DISABLE_MODE = 0 | ||
1812 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
1813 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1814 | // .. OUTPUT_EN = 0x3 | ||
1815 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
1816 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1817 | // .. PULLUP_EN = 0x0 | ||
1818 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
1819 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1820 | // .. | ||
1821 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
1822 | // .. reserved_INP_POWER = 0x0 | ||
1823 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
1824 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1825 | // .. INP_TYPE = 0x0 | ||
1826 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
1827 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
1828 | // .. DCI_UPDATE_B = 0x0 | ||
1829 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
1830 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1831 | // .. TERM_EN = 0x0 | ||
1832 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
1833 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
1834 | // .. DCI_TYPE = 0x0 | ||
1835 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
1836 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
1837 | // .. IBUF_DISABLE_MODE = 0x0 | ||
1838 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
1839 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
1840 | // .. TERM_DISABLE_MODE = 0x0 | ||
1841 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
1842 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
1843 | // .. OUTPUT_EN = 0x3 | ||
1844 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
1845 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
1846 | // .. PULLUP_EN = 0x0 | ||
1847 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
1848 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
1849 | // .. | ||
1850 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
1851 | // .. reserved_DRIVE_P = 0x1c | ||
1852 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
1853 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
1854 | // .. reserved_DRIVE_N = 0xc | ||
1855 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
1856 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
1857 | // .. reserved_SLEW_P = 0x3 | ||
1858 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
1859 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
1860 | // .. reserved_SLEW_N = 0x3 | ||
1861 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
1862 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
1863 | // .. reserved_GTL = 0x0 | ||
1864 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
1865 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
1866 | // .. reserved_RTERM = 0x0 | ||
1867 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
1868 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
1869 | // .. | ||
1870 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
1871 | // .. reserved_DRIVE_P = 0x1c | ||
1872 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
1873 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
1874 | // .. reserved_DRIVE_N = 0xc | ||
1875 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
1876 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
1877 | // .. reserved_SLEW_P = 0x6 | ||
1878 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
1879 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
1880 | // .. reserved_SLEW_N = 0x1f | ||
1881 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
1882 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
1883 | // .. reserved_GTL = 0x0 | ||
1884 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
1885 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
1886 | // .. reserved_RTERM = 0x0 | ||
1887 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
1888 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
1889 | // .. | ||
1890 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
1891 | // .. reserved_DRIVE_P = 0x1c | ||
1892 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
1893 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
1894 | // .. reserved_DRIVE_N = 0xc | ||
1895 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
1896 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
1897 | // .. reserved_SLEW_P = 0x6 | ||
1898 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
1899 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
1900 | // .. reserved_SLEW_N = 0x1f | ||
1901 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
1902 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
1903 | // .. reserved_GTL = 0x0 | ||
1904 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
1905 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
1906 | // .. reserved_RTERM = 0x0 | ||
1907 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
1908 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
1909 | // .. | ||
1910 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
1911 | // .. reserved_DRIVE_P = 0x1c | ||
1912 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
1913 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
1914 | // .. reserved_DRIVE_N = 0xc | ||
1915 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
1916 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
1917 | // .. reserved_SLEW_P = 0x6 | ||
1918 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
1919 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
1920 | // .. reserved_SLEW_N = 0x1f | ||
1921 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
1922 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
1923 | // .. reserved_GTL = 0x0 | ||
1924 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
1925 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
1926 | // .. reserved_RTERM = 0x0 | ||
1927 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
1928 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
1929 | // .. | ||
1930 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
1931 | // .. VREF_INT_EN = 0x1 | ||
1932 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | ||
1933 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1934 | // .. VREF_SEL = 0x4 | ||
1935 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | ||
1936 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | ||
1937 | // .. VREF_EXT_EN = 0x0 | ||
1938 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | ||
1939 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
1940 | // .. reserved_VREF_PULLUP_EN = 0x0 | ||
1941 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
1942 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
1943 | // .. REFIO_EN = 0x1 | ||
1944 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
1945 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
1946 | // .. reserved_REFIO_TEST = 0x0 | ||
1947 | // .. ==> 0XF8000B6C[11:10] = 0x00000000U | ||
1948 | // .. ==> MASK : 0x00000C00U VAL : 0x00000000U | ||
1949 | // .. reserved_REFIO_PULLUP_EN = 0x0 | ||
1950 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
1951 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
1952 | // .. reserved_DRST_B_PULLUP_EN = 0x0 | ||
1953 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
1954 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
1955 | // .. reserved_CKE_PULLUP_EN = 0x0 | ||
1956 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
1957 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
1958 | // .. | ||
1959 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), | ||
1960 | // .. .. START: ASSERT RESET | ||
1961 | // .. .. RESET = 1 | ||
1962 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
1963 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1964 | // .. .. | ||
1965 | EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), | ||
1966 | // .. .. FINISH: ASSERT RESET | ||
1967 | // .. .. START: DEASSERT RESET | ||
1968 | // .. .. RESET = 0 | ||
1969 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
1970 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
1971 | // .. .. reserved_VRN_OUT = 0x1 | ||
1972 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
1973 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
1974 | // .. .. | ||
1975 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
1976 | // .. .. FINISH: DEASSERT RESET | ||
1977 | // .. .. RESET = 0x1 | ||
1978 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
1979 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
1980 | // .. .. ENABLE = 0x1 | ||
1981 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
1982 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
1983 | // .. .. reserved_VRP_TRI = 0x0 | ||
1984 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
1985 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
1986 | // .. .. reserved_VRN_TRI = 0x0 | ||
1987 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
1988 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
1989 | // .. .. reserved_VRP_OUT = 0x0 | ||
1990 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
1991 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
1992 | // .. .. reserved_VRN_OUT = 0x1 | ||
1993 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
1994 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
1995 | // .. .. NREF_OPT1 = 0x0 | ||
1996 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
1997 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
1998 | // .. .. NREF_OPT2 = 0x0 | ||
1999 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
2000 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
2001 | // .. .. NREF_OPT4 = 0x1 | ||
2002 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
2003 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
2004 | // .. .. PREF_OPT1 = 0x0 | ||
2005 | // .. .. ==> 0XF8000B70[15:14] = 0x00000000U | ||
2006 | // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
2007 | // .. .. PREF_OPT2 = 0x0 | ||
2008 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
2009 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
2010 | // .. .. UPDATE_CONTROL = 0x0 | ||
2011 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
2012 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
2013 | // .. .. reserved_INIT_COMPLETE = 0x0 | ||
2014 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
2015 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
2016 | // .. .. reserved_TST_CLK = 0x0 | ||
2017 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
2018 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
2019 | // .. .. reserved_TST_HLN = 0x0 | ||
2020 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
2021 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
2022 | // .. .. reserved_TST_HLP = 0x0 | ||
2023 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
2024 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
2025 | // .. .. reserved_TST_RST = 0x0 | ||
2026 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
2027 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
2028 | // .. .. reserved_INT_DCI_EN = 0x0 | ||
2029 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
2030 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
2031 | // .. .. | ||
2032 | EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), | ||
2033 | // .. FINISH: DDRIOB SETTINGS | ||
2034 | // .. START: MIO PROGRAMMING | ||
2035 | // .. TRI_ENABLE = 0 | ||
2036 | // .. ==> 0XF8000700[0:0] = 0x00000000U | ||
2037 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2038 | // .. L0_SEL = 0 | ||
2039 | // .. ==> 0XF8000700[1:1] = 0x00000000U | ||
2040 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2041 | // .. L1_SEL = 0 | ||
2042 | // .. ==> 0XF8000700[2:2] = 0x00000000U | ||
2043 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2044 | // .. L2_SEL = 0 | ||
2045 | // .. ==> 0XF8000700[4:3] = 0x00000000U | ||
2046 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2047 | // .. L3_SEL = 0 | ||
2048 | // .. ==> 0XF8000700[7:5] = 0x00000000U | ||
2049 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2050 | // .. Speed = 0 | ||
2051 | // .. ==> 0XF8000700[8:8] = 0x00000000U | ||
2052 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2053 | // .. IO_Type = 3 | ||
2054 | // .. ==> 0XF8000700[11:9] = 0x00000003U | ||
2055 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2056 | // .. PULLUP = 0 | ||
2057 | // .. ==> 0XF8000700[12:12] = 0x00000000U | ||
2058 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2059 | // .. DisableRcvr = 0 | ||
2060 | // .. ==> 0XF8000700[13:13] = 0x00000000U | ||
2061 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2062 | // .. | ||
2063 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | ||
2064 | // .. TRI_ENABLE = 0 | ||
2065 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
2066 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2067 | // .. L0_SEL = 1 | ||
2068 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
2069 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2070 | // .. L1_SEL = 0 | ||
2071 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
2072 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2073 | // .. L2_SEL = 0 | ||
2074 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
2075 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2076 | // .. L3_SEL = 0 | ||
2077 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
2078 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2079 | // .. Speed = 0 | ||
2080 | // .. ==> 0XF8000704[8:8] = 0x00000000U | ||
2081 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2082 | // .. IO_Type = 3 | ||
2083 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
2084 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2085 | // .. PULLUP = 0 | ||
2086 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
2087 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2088 | // .. DisableRcvr = 0 | ||
2089 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
2090 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2091 | // .. | ||
2092 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | ||
2093 | // .. TRI_ENABLE = 0 | ||
2094 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
2095 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2096 | // .. L0_SEL = 1 | ||
2097 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
2098 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2099 | // .. L1_SEL = 0 | ||
2100 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
2101 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2102 | // .. L2_SEL = 0 | ||
2103 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
2104 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2105 | // .. L3_SEL = 0 | ||
2106 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
2107 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2108 | // .. Speed = 0 | ||
2109 | // .. ==> 0XF8000708[8:8] = 0x00000000U | ||
2110 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2111 | // .. IO_Type = 3 | ||
2112 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
2113 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2114 | // .. PULLUP = 0 | ||
2115 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
2116 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2117 | // .. DisableRcvr = 0 | ||
2118 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
2119 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2120 | // .. | ||
2121 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | ||
2122 | // .. TRI_ENABLE = 0 | ||
2123 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
2124 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2125 | // .. L0_SEL = 1 | ||
2126 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
2127 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2128 | // .. L1_SEL = 0 | ||
2129 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
2130 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2131 | // .. L2_SEL = 0 | ||
2132 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
2133 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2134 | // .. L3_SEL = 0 | ||
2135 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
2136 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2137 | // .. Speed = 0 | ||
2138 | // .. ==> 0XF800070C[8:8] = 0x00000000U | ||
2139 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2140 | // .. IO_Type = 3 | ||
2141 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
2142 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2143 | // .. PULLUP = 0 | ||
2144 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
2145 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2146 | // .. DisableRcvr = 0 | ||
2147 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
2148 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2149 | // .. | ||
2150 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | ||
2151 | // .. TRI_ENABLE = 0 | ||
2152 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
2153 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2154 | // .. L0_SEL = 1 | ||
2155 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
2156 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2157 | // .. L1_SEL = 0 | ||
2158 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
2159 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2160 | // .. L2_SEL = 0 | ||
2161 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
2162 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2163 | // .. L3_SEL = 0 | ||
2164 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
2165 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2166 | // .. Speed = 0 | ||
2167 | // .. ==> 0XF8000710[8:8] = 0x00000000U | ||
2168 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2169 | // .. IO_Type = 3 | ||
2170 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
2171 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2172 | // .. PULLUP = 0 | ||
2173 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
2174 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2175 | // .. DisableRcvr = 0 | ||
2176 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
2177 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2178 | // .. | ||
2179 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | ||
2180 | // .. TRI_ENABLE = 0 | ||
2181 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
2182 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2183 | // .. L0_SEL = 1 | ||
2184 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
2185 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2186 | // .. L1_SEL = 0 | ||
2187 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
2188 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2189 | // .. L2_SEL = 0 | ||
2190 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
2191 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2192 | // .. L3_SEL = 0 | ||
2193 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
2194 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2195 | // .. Speed = 0 | ||
2196 | // .. ==> 0XF8000714[8:8] = 0x00000000U | ||
2197 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2198 | // .. IO_Type = 3 | ||
2199 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
2200 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2201 | // .. PULLUP = 0 | ||
2202 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
2203 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2204 | // .. DisableRcvr = 0 | ||
2205 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
2206 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2207 | // .. | ||
2208 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | ||
2209 | // .. TRI_ENABLE = 0 | ||
2210 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
2211 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2212 | // .. L0_SEL = 1 | ||
2213 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
2214 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2215 | // .. L1_SEL = 0 | ||
2216 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
2217 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2218 | // .. L2_SEL = 0 | ||
2219 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
2220 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2221 | // .. L3_SEL = 0 | ||
2222 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
2223 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2224 | // .. Speed = 0 | ||
2225 | // .. ==> 0XF8000718[8:8] = 0x00000000U | ||
2226 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2227 | // .. IO_Type = 3 | ||
2228 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
2229 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2230 | // .. PULLUP = 0 | ||
2231 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
2232 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2233 | // .. DisableRcvr = 0 | ||
2234 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
2235 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2236 | // .. | ||
2237 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | ||
2238 | // .. TRI_ENABLE = 0 | ||
2239 | // .. ==> 0XF800071C[0:0] = 0x00000000U | ||
2240 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2241 | // .. L0_SEL = 0 | ||
2242 | // .. ==> 0XF800071C[1:1] = 0x00000000U | ||
2243 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2244 | // .. L1_SEL = 0 | ||
2245 | // .. ==> 0XF800071C[2:2] = 0x00000000U | ||
2246 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2247 | // .. L2_SEL = 0 | ||
2248 | // .. ==> 0XF800071C[4:3] = 0x00000000U | ||
2249 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2250 | // .. L3_SEL = 0 | ||
2251 | // .. ==> 0XF800071C[7:5] = 0x00000000U | ||
2252 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2253 | // .. Speed = 0 | ||
2254 | // .. ==> 0XF800071C[8:8] = 0x00000000U | ||
2255 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2256 | // .. IO_Type = 3 | ||
2257 | // .. ==> 0XF800071C[11:9] = 0x00000003U | ||
2258 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2259 | // .. PULLUP = 0 | ||
2260 | // .. ==> 0XF800071C[12:12] = 0x00000000U | ||
2261 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2262 | // .. DisableRcvr = 0 | ||
2263 | // .. ==> 0XF800071C[13:13] = 0x00000000U | ||
2264 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2265 | // .. | ||
2266 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | ||
2267 | // .. TRI_ENABLE = 0 | ||
2268 | // .. ==> 0XF8000720[0:0] = 0x00000000U | ||
2269 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2270 | // .. L0_SEL = 1 | ||
2271 | // .. ==> 0XF8000720[1:1] = 0x00000001U | ||
2272 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2273 | // .. L1_SEL = 0 | ||
2274 | // .. ==> 0XF8000720[2:2] = 0x00000000U | ||
2275 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2276 | // .. L2_SEL = 0 | ||
2277 | // .. ==> 0XF8000720[4:3] = 0x00000000U | ||
2278 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2279 | // .. L3_SEL = 0 | ||
2280 | // .. ==> 0XF8000720[7:5] = 0x00000000U | ||
2281 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2282 | // .. Speed = 0 | ||
2283 | // .. ==> 0XF8000720[8:8] = 0x00000000U | ||
2284 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2285 | // .. IO_Type = 3 | ||
2286 | // .. ==> 0XF8000720[11:9] = 0x00000003U | ||
2287 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2288 | // .. PULLUP = 0 | ||
2289 | // .. ==> 0XF8000720[12:12] = 0x00000000U | ||
2290 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2291 | // .. DisableRcvr = 0 | ||
2292 | // .. ==> 0XF8000720[13:13] = 0x00000000U | ||
2293 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2294 | // .. | ||
2295 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | ||
2296 | // .. TRI_ENABLE = 0 | ||
2297 | // .. ==> 0XF8000724[0:0] = 0x00000000U | ||
2298 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2299 | // .. L0_SEL = 0 | ||
2300 | // .. ==> 0XF8000724[1:1] = 0x00000000U | ||
2301 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2302 | // .. L1_SEL = 0 | ||
2303 | // .. ==> 0XF8000724[2:2] = 0x00000000U | ||
2304 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2305 | // .. L2_SEL = 0 | ||
2306 | // .. ==> 0XF8000724[4:3] = 0x00000000U | ||
2307 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2308 | // .. L3_SEL = 0 | ||
2309 | // .. ==> 0XF8000724[7:5] = 0x00000000U | ||
2310 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2311 | // .. Speed = 0 | ||
2312 | // .. ==> 0XF8000724[8:8] = 0x00000000U | ||
2313 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2314 | // .. IO_Type = 3 | ||
2315 | // .. ==> 0XF8000724[11:9] = 0x00000003U | ||
2316 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2317 | // .. PULLUP = 0 | ||
2318 | // .. ==> 0XF8000724[12:12] = 0x00000000U | ||
2319 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2320 | // .. DisableRcvr = 0 | ||
2321 | // .. ==> 0XF8000724[13:13] = 0x00000000U | ||
2322 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2323 | // .. | ||
2324 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | ||
2325 | // .. TRI_ENABLE = 0 | ||
2326 | // .. ==> 0XF8000728[0:0] = 0x00000000U | ||
2327 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2328 | // .. L0_SEL = 0 | ||
2329 | // .. ==> 0XF8000728[1:1] = 0x00000000U | ||
2330 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2331 | // .. L1_SEL = 0 | ||
2332 | // .. ==> 0XF8000728[2:2] = 0x00000000U | ||
2333 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2334 | // .. L2_SEL = 0 | ||
2335 | // .. ==> 0XF8000728[4:3] = 0x00000000U | ||
2336 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2337 | // .. L3_SEL = 4 | ||
2338 | // .. ==> 0XF8000728[7:5] = 0x00000004U | ||
2339 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2340 | // .. Speed = 0 | ||
2341 | // .. ==> 0XF8000728[8:8] = 0x00000000U | ||
2342 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2343 | // .. IO_Type = 3 | ||
2344 | // .. ==> 0XF8000728[11:9] = 0x00000003U | ||
2345 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2346 | // .. PULLUP = 0 | ||
2347 | // .. ==> 0XF8000728[12:12] = 0x00000000U | ||
2348 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2349 | // .. DisableRcvr = 0 | ||
2350 | // .. ==> 0XF8000728[13:13] = 0x00000000U | ||
2351 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2352 | // .. | ||
2353 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), | ||
2354 | // .. TRI_ENABLE = 0 | ||
2355 | // .. ==> 0XF800072C[0:0] = 0x00000000U | ||
2356 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2357 | // .. L0_SEL = 0 | ||
2358 | // .. ==> 0XF800072C[1:1] = 0x00000000U | ||
2359 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2360 | // .. L1_SEL = 0 | ||
2361 | // .. ==> 0XF800072C[2:2] = 0x00000000U | ||
2362 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2363 | // .. L2_SEL = 0 | ||
2364 | // .. ==> 0XF800072C[4:3] = 0x00000000U | ||
2365 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2366 | // .. L3_SEL = 4 | ||
2367 | // .. ==> 0XF800072C[7:5] = 0x00000004U | ||
2368 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2369 | // .. Speed = 0 | ||
2370 | // .. ==> 0XF800072C[8:8] = 0x00000000U | ||
2371 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2372 | // .. IO_Type = 3 | ||
2373 | // .. ==> 0XF800072C[11:9] = 0x00000003U | ||
2374 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2375 | // .. PULLUP = 0 | ||
2376 | // .. ==> 0XF800072C[12:12] = 0x00000000U | ||
2377 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2378 | // .. DisableRcvr = 0 | ||
2379 | // .. ==> 0XF800072C[13:13] = 0x00000000U | ||
2380 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2381 | // .. | ||
2382 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), | ||
2383 | // .. TRI_ENABLE = 0 | ||
2384 | // .. ==> 0XF8000730[0:0] = 0x00000000U | ||
2385 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2386 | // .. L0_SEL = 0 | ||
2387 | // .. ==> 0XF8000730[1:1] = 0x00000000U | ||
2388 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2389 | // .. L1_SEL = 0 | ||
2390 | // .. ==> 0XF8000730[2:2] = 0x00000000U | ||
2391 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2392 | // .. L2_SEL = 0 | ||
2393 | // .. ==> 0XF8000730[4:3] = 0x00000000U | ||
2394 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2395 | // .. L3_SEL = 4 | ||
2396 | // .. ==> 0XF8000730[7:5] = 0x00000004U | ||
2397 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2398 | // .. Speed = 0 | ||
2399 | // .. ==> 0XF8000730[8:8] = 0x00000000U | ||
2400 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2401 | // .. IO_Type = 3 | ||
2402 | // .. ==> 0XF8000730[11:9] = 0x00000003U | ||
2403 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2404 | // .. PULLUP = 0 | ||
2405 | // .. ==> 0XF8000730[12:12] = 0x00000000U | ||
2406 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2407 | // .. DisableRcvr = 0 | ||
2408 | // .. ==> 0XF8000730[13:13] = 0x00000000U | ||
2409 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2410 | // .. | ||
2411 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), | ||
2412 | // .. TRI_ENABLE = 0 | ||
2413 | // .. ==> 0XF8000734[0:0] = 0x00000000U | ||
2414 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2415 | // .. L0_SEL = 0 | ||
2416 | // .. ==> 0XF8000734[1:1] = 0x00000000U | ||
2417 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2418 | // .. L1_SEL = 0 | ||
2419 | // .. ==> 0XF8000734[2:2] = 0x00000000U | ||
2420 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2421 | // .. L2_SEL = 0 | ||
2422 | // .. ==> 0XF8000734[4:3] = 0x00000000U | ||
2423 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2424 | // .. L3_SEL = 4 | ||
2425 | // .. ==> 0XF8000734[7:5] = 0x00000004U | ||
2426 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2427 | // .. Speed = 0 | ||
2428 | // .. ==> 0XF8000734[8:8] = 0x00000000U | ||
2429 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2430 | // .. IO_Type = 3 | ||
2431 | // .. ==> 0XF8000734[11:9] = 0x00000003U | ||
2432 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2433 | // .. PULLUP = 0 | ||
2434 | // .. ==> 0XF8000734[12:12] = 0x00000000U | ||
2435 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2436 | // .. DisableRcvr = 0 | ||
2437 | // .. ==> 0XF8000734[13:13] = 0x00000000U | ||
2438 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2439 | // .. | ||
2440 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), | ||
2441 | // .. TRI_ENABLE = 0 | ||
2442 | // .. ==> 0XF8000738[0:0] = 0x00000000U | ||
2443 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2444 | // .. L0_SEL = 0 | ||
2445 | // .. ==> 0XF8000738[1:1] = 0x00000000U | ||
2446 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2447 | // .. L1_SEL = 0 | ||
2448 | // .. ==> 0XF8000738[2:2] = 0x00000000U | ||
2449 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2450 | // .. L2_SEL = 0 | ||
2451 | // .. ==> 0XF8000738[4:3] = 0x00000000U | ||
2452 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2453 | // .. L3_SEL = 4 | ||
2454 | // .. ==> 0XF8000738[7:5] = 0x00000004U | ||
2455 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2456 | // .. Speed = 0 | ||
2457 | // .. ==> 0XF8000738[8:8] = 0x00000000U | ||
2458 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2459 | // .. IO_Type = 3 | ||
2460 | // .. ==> 0XF8000738[11:9] = 0x00000003U | ||
2461 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2462 | // .. PULLUP = 0 | ||
2463 | // .. ==> 0XF8000738[12:12] = 0x00000000U | ||
2464 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2465 | // .. DisableRcvr = 0 | ||
2466 | // .. ==> 0XF8000738[13:13] = 0x00000000U | ||
2467 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2468 | // .. | ||
2469 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), | ||
2470 | // .. TRI_ENABLE = 0 | ||
2471 | // .. ==> 0XF800073C[0:0] = 0x00000000U | ||
2472 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2473 | // .. L0_SEL = 0 | ||
2474 | // .. ==> 0XF800073C[1:1] = 0x00000000U | ||
2475 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2476 | // .. L1_SEL = 0 | ||
2477 | // .. ==> 0XF800073C[2:2] = 0x00000000U | ||
2478 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2479 | // .. L2_SEL = 0 | ||
2480 | // .. ==> 0XF800073C[4:3] = 0x00000000U | ||
2481 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2482 | // .. L3_SEL = 4 | ||
2483 | // .. ==> 0XF800073C[7:5] = 0x00000004U | ||
2484 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
2485 | // .. Speed = 0 | ||
2486 | // .. ==> 0XF800073C[8:8] = 0x00000000U | ||
2487 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2488 | // .. IO_Type = 3 | ||
2489 | // .. ==> 0XF800073C[11:9] = 0x00000003U | ||
2490 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
2491 | // .. PULLUP = 0 | ||
2492 | // .. ==> 0XF800073C[12:12] = 0x00000000U | ||
2493 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2494 | // .. DisableRcvr = 0 | ||
2495 | // .. ==> 0XF800073C[13:13] = 0x00000000U | ||
2496 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2497 | // .. | ||
2498 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), | ||
2499 | // .. TRI_ENABLE = 0 | ||
2500 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
2501 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2502 | // .. L0_SEL = 1 | ||
2503 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
2504 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2505 | // .. L1_SEL = 0 | ||
2506 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
2507 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2508 | // .. L2_SEL = 0 | ||
2509 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
2510 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2511 | // .. L3_SEL = 0 | ||
2512 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
2513 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2514 | // .. Speed = 0 | ||
2515 | // .. ==> 0XF8000740[8:8] = 0x00000000U | ||
2516 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2517 | // .. IO_Type = 1 | ||
2518 | // .. ==> 0XF8000740[11:9] = 0x00000001U | ||
2519 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2520 | // .. PULLUP = 0 | ||
2521 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
2522 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2523 | // .. DisableRcvr = 0 | ||
2524 | // .. ==> 0XF8000740[13:13] = 0x00000000U | ||
2525 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2526 | // .. | ||
2527 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | ||
2528 | // .. TRI_ENABLE = 0 | ||
2529 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
2530 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2531 | // .. L0_SEL = 1 | ||
2532 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
2533 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2534 | // .. L1_SEL = 0 | ||
2535 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
2536 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2537 | // .. L2_SEL = 0 | ||
2538 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
2539 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2540 | // .. L3_SEL = 0 | ||
2541 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
2542 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2543 | // .. Speed = 0 | ||
2544 | // .. ==> 0XF8000744[8:8] = 0x00000000U | ||
2545 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2546 | // .. IO_Type = 1 | ||
2547 | // .. ==> 0XF8000744[11:9] = 0x00000001U | ||
2548 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2549 | // .. PULLUP = 0 | ||
2550 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
2551 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2552 | // .. DisableRcvr = 0 | ||
2553 | // .. ==> 0XF8000744[13:13] = 0x00000000U | ||
2554 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2555 | // .. | ||
2556 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | ||
2557 | // .. TRI_ENABLE = 0 | ||
2558 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
2559 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2560 | // .. L0_SEL = 1 | ||
2561 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
2562 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2563 | // .. L1_SEL = 0 | ||
2564 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
2565 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2566 | // .. L2_SEL = 0 | ||
2567 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
2568 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2569 | // .. L3_SEL = 0 | ||
2570 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
2571 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2572 | // .. Speed = 0 | ||
2573 | // .. ==> 0XF8000748[8:8] = 0x00000000U | ||
2574 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2575 | // .. IO_Type = 1 | ||
2576 | // .. ==> 0XF8000748[11:9] = 0x00000001U | ||
2577 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2578 | // .. PULLUP = 0 | ||
2579 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
2580 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2581 | // .. DisableRcvr = 0 | ||
2582 | // .. ==> 0XF8000748[13:13] = 0x00000000U | ||
2583 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2584 | // .. | ||
2585 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | ||
2586 | // .. TRI_ENABLE = 0 | ||
2587 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
2588 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2589 | // .. L0_SEL = 1 | ||
2590 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
2591 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2592 | // .. L1_SEL = 0 | ||
2593 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
2594 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2595 | // .. L2_SEL = 0 | ||
2596 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
2597 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2598 | // .. L3_SEL = 0 | ||
2599 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
2600 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2601 | // .. Speed = 0 | ||
2602 | // .. ==> 0XF800074C[8:8] = 0x00000000U | ||
2603 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2604 | // .. IO_Type = 1 | ||
2605 | // .. ==> 0XF800074C[11:9] = 0x00000001U | ||
2606 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2607 | // .. PULLUP = 0 | ||
2608 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
2609 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2610 | // .. DisableRcvr = 0 | ||
2611 | // .. ==> 0XF800074C[13:13] = 0x00000000U | ||
2612 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2613 | // .. | ||
2614 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | ||
2615 | // .. TRI_ENABLE = 0 | ||
2616 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
2617 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2618 | // .. L0_SEL = 1 | ||
2619 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
2620 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2621 | // .. L1_SEL = 0 | ||
2622 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
2623 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2624 | // .. L2_SEL = 0 | ||
2625 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
2626 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2627 | // .. L3_SEL = 0 | ||
2628 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
2629 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2630 | // .. Speed = 0 | ||
2631 | // .. ==> 0XF8000750[8:8] = 0x00000000U | ||
2632 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2633 | // .. IO_Type = 1 | ||
2634 | // .. ==> 0XF8000750[11:9] = 0x00000001U | ||
2635 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2636 | // .. PULLUP = 0 | ||
2637 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
2638 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2639 | // .. DisableRcvr = 0 | ||
2640 | // .. ==> 0XF8000750[13:13] = 0x00000000U | ||
2641 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2642 | // .. | ||
2643 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | ||
2644 | // .. TRI_ENABLE = 0 | ||
2645 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
2646 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2647 | // .. L0_SEL = 1 | ||
2648 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
2649 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2650 | // .. L1_SEL = 0 | ||
2651 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
2652 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2653 | // .. L2_SEL = 0 | ||
2654 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
2655 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2656 | // .. L3_SEL = 0 | ||
2657 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
2658 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2659 | // .. Speed = 0 | ||
2660 | // .. ==> 0XF8000754[8:8] = 0x00000000U | ||
2661 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2662 | // .. IO_Type = 1 | ||
2663 | // .. ==> 0XF8000754[11:9] = 0x00000001U | ||
2664 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2665 | // .. PULLUP = 0 | ||
2666 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
2667 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2668 | // .. DisableRcvr = 0 | ||
2669 | // .. ==> 0XF8000754[13:13] = 0x00000000U | ||
2670 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2671 | // .. | ||
2672 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | ||
2673 | // .. TRI_ENABLE = 1 | ||
2674 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
2675 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2676 | // .. L0_SEL = 1 | ||
2677 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
2678 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2679 | // .. L1_SEL = 0 | ||
2680 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
2681 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2682 | // .. L2_SEL = 0 | ||
2683 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
2684 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2685 | // .. L3_SEL = 0 | ||
2686 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
2687 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2688 | // .. Speed = 0 | ||
2689 | // .. ==> 0XF8000758[8:8] = 0x00000000U | ||
2690 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2691 | // .. IO_Type = 1 | ||
2692 | // .. ==> 0XF8000758[11:9] = 0x00000001U | ||
2693 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2694 | // .. PULLUP = 0 | ||
2695 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
2696 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2697 | // .. DisableRcvr = 0 | ||
2698 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
2699 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2700 | // .. | ||
2701 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | ||
2702 | // .. TRI_ENABLE = 1 | ||
2703 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
2704 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2705 | // .. L0_SEL = 1 | ||
2706 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
2707 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2708 | // .. L1_SEL = 0 | ||
2709 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
2710 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2711 | // .. L2_SEL = 0 | ||
2712 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
2713 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2714 | // .. L3_SEL = 0 | ||
2715 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
2716 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2717 | // .. Speed = 0 | ||
2718 | // .. ==> 0XF800075C[8:8] = 0x00000000U | ||
2719 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2720 | // .. IO_Type = 1 | ||
2721 | // .. ==> 0XF800075C[11:9] = 0x00000001U | ||
2722 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2723 | // .. PULLUP = 0 | ||
2724 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
2725 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2726 | // .. DisableRcvr = 0 | ||
2727 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
2728 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2729 | // .. | ||
2730 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | ||
2731 | // .. TRI_ENABLE = 1 | ||
2732 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
2733 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2734 | // .. L0_SEL = 1 | ||
2735 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
2736 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2737 | // .. L1_SEL = 0 | ||
2738 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
2739 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2740 | // .. L2_SEL = 0 | ||
2741 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
2742 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2743 | // .. L3_SEL = 0 | ||
2744 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
2745 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2746 | // .. Speed = 0 | ||
2747 | // .. ==> 0XF8000760[8:8] = 0x00000000U | ||
2748 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2749 | // .. IO_Type = 1 | ||
2750 | // .. ==> 0XF8000760[11:9] = 0x00000001U | ||
2751 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2752 | // .. PULLUP = 0 | ||
2753 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
2754 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2755 | // .. DisableRcvr = 0 | ||
2756 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
2757 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2758 | // .. | ||
2759 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | ||
2760 | // .. TRI_ENABLE = 1 | ||
2761 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
2762 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2763 | // .. L0_SEL = 1 | ||
2764 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
2765 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2766 | // .. L1_SEL = 0 | ||
2767 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
2768 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2769 | // .. L2_SEL = 0 | ||
2770 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
2771 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2772 | // .. L3_SEL = 0 | ||
2773 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
2774 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2775 | // .. Speed = 0 | ||
2776 | // .. ==> 0XF8000764[8:8] = 0x00000000U | ||
2777 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2778 | // .. IO_Type = 1 | ||
2779 | // .. ==> 0XF8000764[11:9] = 0x00000001U | ||
2780 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2781 | // .. PULLUP = 0 | ||
2782 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
2783 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2784 | // .. DisableRcvr = 0 | ||
2785 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
2786 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2787 | // .. | ||
2788 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | ||
2789 | // .. TRI_ENABLE = 1 | ||
2790 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
2791 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2792 | // .. L0_SEL = 1 | ||
2793 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
2794 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2795 | // .. L1_SEL = 0 | ||
2796 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
2797 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2798 | // .. L2_SEL = 0 | ||
2799 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
2800 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2801 | // .. L3_SEL = 0 | ||
2802 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
2803 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2804 | // .. Speed = 0 | ||
2805 | // .. ==> 0XF8000768[8:8] = 0x00000000U | ||
2806 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2807 | // .. IO_Type = 1 | ||
2808 | // .. ==> 0XF8000768[11:9] = 0x00000001U | ||
2809 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2810 | // .. PULLUP = 0 | ||
2811 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
2812 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2813 | // .. DisableRcvr = 0 | ||
2814 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
2815 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2816 | // .. | ||
2817 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | ||
2818 | // .. TRI_ENABLE = 1 | ||
2819 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
2820 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2821 | // .. L0_SEL = 1 | ||
2822 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
2823 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
2824 | // .. L1_SEL = 0 | ||
2825 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
2826 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
2827 | // .. L2_SEL = 0 | ||
2828 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
2829 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2830 | // .. L3_SEL = 0 | ||
2831 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
2832 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2833 | // .. Speed = 0 | ||
2834 | // .. ==> 0XF800076C[8:8] = 0x00000000U | ||
2835 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2836 | // .. IO_Type = 1 | ||
2837 | // .. ==> 0XF800076C[11:9] = 0x00000001U | ||
2838 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2839 | // .. PULLUP = 0 | ||
2840 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
2841 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2842 | // .. DisableRcvr = 0 | ||
2843 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
2844 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2845 | // .. | ||
2846 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | ||
2847 | // .. TRI_ENABLE = 0 | ||
2848 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
2849 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2850 | // .. L0_SEL = 0 | ||
2851 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
2852 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2853 | // .. L1_SEL = 1 | ||
2854 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
2855 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
2856 | // .. L2_SEL = 0 | ||
2857 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
2858 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2859 | // .. L3_SEL = 0 | ||
2860 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
2861 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2862 | // .. Speed = 0 | ||
2863 | // .. ==> 0XF8000770[8:8] = 0x00000000U | ||
2864 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2865 | // .. IO_Type = 1 | ||
2866 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
2867 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2868 | // .. PULLUP = 0 | ||
2869 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
2870 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2871 | // .. DisableRcvr = 0 | ||
2872 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
2873 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2874 | // .. | ||
2875 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | ||
2876 | // .. TRI_ENABLE = 1 | ||
2877 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
2878 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2879 | // .. L0_SEL = 0 | ||
2880 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
2881 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2882 | // .. L1_SEL = 1 | ||
2883 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
2884 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
2885 | // .. L2_SEL = 0 | ||
2886 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
2887 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2888 | // .. L3_SEL = 0 | ||
2889 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
2890 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2891 | // .. Speed = 0 | ||
2892 | // .. ==> 0XF8000774[8:8] = 0x00000000U | ||
2893 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2894 | // .. IO_Type = 1 | ||
2895 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
2896 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2897 | // .. PULLUP = 0 | ||
2898 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
2899 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2900 | // .. DisableRcvr = 0 | ||
2901 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
2902 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2903 | // .. | ||
2904 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | ||
2905 | // .. TRI_ENABLE = 0 | ||
2906 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
2907 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2908 | // .. L0_SEL = 0 | ||
2909 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
2910 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2911 | // .. L1_SEL = 1 | ||
2912 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
2913 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
2914 | // .. L2_SEL = 0 | ||
2915 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
2916 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2917 | // .. L3_SEL = 0 | ||
2918 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
2919 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2920 | // .. Speed = 0 | ||
2921 | // .. ==> 0XF8000778[8:8] = 0x00000000U | ||
2922 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2923 | // .. IO_Type = 1 | ||
2924 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
2925 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2926 | // .. PULLUP = 0 | ||
2927 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
2928 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2929 | // .. DisableRcvr = 0 | ||
2930 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
2931 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2932 | // .. | ||
2933 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | ||
2934 | // .. TRI_ENABLE = 1 | ||
2935 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
2936 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
2937 | // .. L0_SEL = 0 | ||
2938 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
2939 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2940 | // .. L1_SEL = 1 | ||
2941 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
2942 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
2943 | // .. L2_SEL = 0 | ||
2944 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
2945 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2946 | // .. L3_SEL = 0 | ||
2947 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
2948 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2949 | // .. Speed = 0 | ||
2950 | // .. ==> 0XF800077C[8:8] = 0x00000000U | ||
2951 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2952 | // .. IO_Type = 1 | ||
2953 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
2954 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2955 | // .. PULLUP = 0 | ||
2956 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
2957 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2958 | // .. DisableRcvr = 0 | ||
2959 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
2960 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2961 | // .. | ||
2962 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | ||
2963 | // .. TRI_ENABLE = 0 | ||
2964 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
2965 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2966 | // .. L0_SEL = 0 | ||
2967 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
2968 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2969 | // .. L1_SEL = 1 | ||
2970 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
2971 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
2972 | // .. L2_SEL = 0 | ||
2973 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
2974 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
2975 | // .. L3_SEL = 0 | ||
2976 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
2977 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
2978 | // .. Speed = 0 | ||
2979 | // .. ==> 0XF8000780[8:8] = 0x00000000U | ||
2980 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
2981 | // .. IO_Type = 1 | ||
2982 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
2983 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
2984 | // .. PULLUP = 0 | ||
2985 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
2986 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
2987 | // .. DisableRcvr = 0 | ||
2988 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
2989 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
2990 | // .. | ||
2991 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | ||
2992 | // .. TRI_ENABLE = 0 | ||
2993 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
2994 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
2995 | // .. L0_SEL = 0 | ||
2996 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
2997 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
2998 | // .. L1_SEL = 1 | ||
2999 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
3000 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3001 | // .. L2_SEL = 0 | ||
3002 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
3003 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3004 | // .. L3_SEL = 0 | ||
3005 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
3006 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3007 | // .. Speed = 0 | ||
3008 | // .. ==> 0XF8000784[8:8] = 0x00000000U | ||
3009 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3010 | // .. IO_Type = 1 | ||
3011 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
3012 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3013 | // .. PULLUP = 0 | ||
3014 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
3015 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3016 | // .. DisableRcvr = 0 | ||
3017 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
3018 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3019 | // .. | ||
3020 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | ||
3021 | // .. TRI_ENABLE = 0 | ||
3022 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
3023 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3024 | // .. L0_SEL = 0 | ||
3025 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
3026 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3027 | // .. L1_SEL = 1 | ||
3028 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
3029 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3030 | // .. L2_SEL = 0 | ||
3031 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
3032 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3033 | // .. L3_SEL = 0 | ||
3034 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
3035 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3036 | // .. Speed = 0 | ||
3037 | // .. ==> 0XF8000788[8:8] = 0x00000000U | ||
3038 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3039 | // .. IO_Type = 1 | ||
3040 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
3041 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3042 | // .. PULLUP = 0 | ||
3043 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
3044 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3045 | // .. DisableRcvr = 0 | ||
3046 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
3047 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3048 | // .. | ||
3049 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | ||
3050 | // .. TRI_ENABLE = 0 | ||
3051 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
3052 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3053 | // .. L0_SEL = 0 | ||
3054 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
3055 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3056 | // .. L1_SEL = 1 | ||
3057 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
3058 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3059 | // .. L2_SEL = 0 | ||
3060 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
3061 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3062 | // .. L3_SEL = 0 | ||
3063 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
3064 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3065 | // .. Speed = 0 | ||
3066 | // .. ==> 0XF800078C[8:8] = 0x00000000U | ||
3067 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3068 | // .. IO_Type = 1 | ||
3069 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
3070 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3071 | // .. PULLUP = 0 | ||
3072 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
3073 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3074 | // .. DisableRcvr = 0 | ||
3075 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
3076 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3077 | // .. | ||
3078 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | ||
3079 | // .. TRI_ENABLE = 1 | ||
3080 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
3081 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
3082 | // .. L0_SEL = 0 | ||
3083 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
3084 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3085 | // .. L1_SEL = 1 | ||
3086 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
3087 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3088 | // .. L2_SEL = 0 | ||
3089 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
3090 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3091 | // .. L3_SEL = 0 | ||
3092 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
3093 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3094 | // .. Speed = 0 | ||
3095 | // .. ==> 0XF8000790[8:8] = 0x00000000U | ||
3096 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3097 | // .. IO_Type = 1 | ||
3098 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
3099 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3100 | // .. PULLUP = 0 | ||
3101 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
3102 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3103 | // .. DisableRcvr = 0 | ||
3104 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
3105 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3106 | // .. | ||
3107 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | ||
3108 | // .. TRI_ENABLE = 0 | ||
3109 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
3110 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3111 | // .. L0_SEL = 0 | ||
3112 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
3113 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3114 | // .. L1_SEL = 1 | ||
3115 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
3116 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3117 | // .. L2_SEL = 0 | ||
3118 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
3119 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3120 | // .. L3_SEL = 0 | ||
3121 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
3122 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3123 | // .. Speed = 0 | ||
3124 | // .. ==> 0XF8000794[8:8] = 0x00000000U | ||
3125 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3126 | // .. IO_Type = 1 | ||
3127 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
3128 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3129 | // .. PULLUP = 0 | ||
3130 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
3131 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3132 | // .. DisableRcvr = 0 | ||
3133 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
3134 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3135 | // .. | ||
3136 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | ||
3137 | // .. TRI_ENABLE = 0 | ||
3138 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
3139 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3140 | // .. L0_SEL = 0 | ||
3141 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
3142 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3143 | // .. L1_SEL = 1 | ||
3144 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
3145 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3146 | // .. L2_SEL = 0 | ||
3147 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
3148 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3149 | // .. L3_SEL = 0 | ||
3150 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
3151 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3152 | // .. Speed = 0 | ||
3153 | // .. ==> 0XF8000798[8:8] = 0x00000000U | ||
3154 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3155 | // .. IO_Type = 1 | ||
3156 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
3157 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3158 | // .. PULLUP = 0 | ||
3159 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
3160 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3161 | // .. DisableRcvr = 0 | ||
3162 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
3163 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3164 | // .. | ||
3165 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | ||
3166 | // .. TRI_ENABLE = 0 | ||
3167 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
3168 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3169 | // .. L0_SEL = 0 | ||
3170 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
3171 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3172 | // .. L1_SEL = 1 | ||
3173 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
3174 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3175 | // .. L2_SEL = 0 | ||
3176 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
3177 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3178 | // .. L3_SEL = 0 | ||
3179 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
3180 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3181 | // .. Speed = 0 | ||
3182 | // .. ==> 0XF800079C[8:8] = 0x00000000U | ||
3183 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3184 | // .. IO_Type = 1 | ||
3185 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
3186 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3187 | // .. PULLUP = 0 | ||
3188 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
3189 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3190 | // .. DisableRcvr = 0 | ||
3191 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
3192 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3193 | // .. | ||
3194 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | ||
3195 | // .. TRI_ENABLE = 0 | ||
3196 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
3197 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3198 | // .. L0_SEL = 0 | ||
3199 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
3200 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3201 | // .. L1_SEL = 0 | ||
3202 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
3203 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3204 | // .. L2_SEL = 0 | ||
3205 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
3206 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3207 | // .. L3_SEL = 0 | ||
3208 | // .. ==> 0XF80007A0[7:5] = 0x00000000U | ||
3209 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3210 | // .. Speed = 0 | ||
3211 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | ||
3212 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3213 | // .. IO_Type = 1 | ||
3214 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
3215 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3216 | // .. PULLUP = 0 | ||
3217 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
3218 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3219 | // .. DisableRcvr = 0 | ||
3220 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
3221 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3222 | // .. | ||
3223 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), | ||
3224 | // .. TRI_ENABLE = 0 | ||
3225 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
3226 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3227 | // .. L0_SEL = 0 | ||
3228 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
3229 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3230 | // .. L1_SEL = 0 | ||
3231 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
3232 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3233 | // .. L2_SEL = 0 | ||
3234 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
3235 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3236 | // .. L3_SEL = 0 | ||
3237 | // .. ==> 0XF80007A4[7:5] = 0x00000000U | ||
3238 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3239 | // .. Speed = 0 | ||
3240 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | ||
3241 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3242 | // .. IO_Type = 1 | ||
3243 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
3244 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3245 | // .. PULLUP = 0 | ||
3246 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
3247 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3248 | // .. DisableRcvr = 0 | ||
3249 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
3250 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3251 | // .. | ||
3252 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), | ||
3253 | // .. TRI_ENABLE = 0 | ||
3254 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
3255 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3256 | // .. L0_SEL = 0 | ||
3257 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
3258 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3259 | // .. L1_SEL = 0 | ||
3260 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
3261 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3262 | // .. L2_SEL = 0 | ||
3263 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
3264 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3265 | // .. L3_SEL = 0 | ||
3266 | // .. ==> 0XF80007A8[7:5] = 0x00000000U | ||
3267 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3268 | // .. Speed = 0 | ||
3269 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | ||
3270 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3271 | // .. IO_Type = 1 | ||
3272 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
3273 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3274 | // .. PULLUP = 0 | ||
3275 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
3276 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3277 | // .. DisableRcvr = 0 | ||
3278 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
3279 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3280 | // .. | ||
3281 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), | ||
3282 | // .. TRI_ENABLE = 0 | ||
3283 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
3284 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3285 | // .. L0_SEL = 0 | ||
3286 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
3287 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3288 | // .. L1_SEL = 0 | ||
3289 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
3290 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3291 | // .. L2_SEL = 0 | ||
3292 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
3293 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3294 | // .. L3_SEL = 0 | ||
3295 | // .. ==> 0XF80007AC[7:5] = 0x00000000U | ||
3296 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3297 | // .. Speed = 0 | ||
3298 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | ||
3299 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3300 | // .. IO_Type = 1 | ||
3301 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
3302 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3303 | // .. PULLUP = 0 | ||
3304 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
3305 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3306 | // .. DisableRcvr = 0 | ||
3307 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
3308 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3309 | // .. | ||
3310 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), | ||
3311 | // .. TRI_ENABLE = 0 | ||
3312 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
3313 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3314 | // .. L0_SEL = 0 | ||
3315 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
3316 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3317 | // .. L1_SEL = 0 | ||
3318 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
3319 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3320 | // .. L2_SEL = 0 | ||
3321 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
3322 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3323 | // .. L3_SEL = 0 | ||
3324 | // .. ==> 0XF80007B0[7:5] = 0x00000000U | ||
3325 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3326 | // .. Speed = 0 | ||
3327 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | ||
3328 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3329 | // .. IO_Type = 1 | ||
3330 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
3331 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3332 | // .. PULLUP = 0 | ||
3333 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
3334 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3335 | // .. DisableRcvr = 0 | ||
3336 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
3337 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3338 | // .. | ||
3339 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), | ||
3340 | // .. TRI_ENABLE = 0 | ||
3341 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
3342 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3343 | // .. L0_SEL = 0 | ||
3344 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
3345 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3346 | // .. L1_SEL = 0 | ||
3347 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
3348 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3349 | // .. L2_SEL = 0 | ||
3350 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
3351 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3352 | // .. L3_SEL = 0 | ||
3353 | // .. ==> 0XF80007B4[7:5] = 0x00000000U | ||
3354 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3355 | // .. Speed = 0 | ||
3356 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | ||
3357 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3358 | // .. IO_Type = 1 | ||
3359 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
3360 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3361 | // .. PULLUP = 0 | ||
3362 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
3363 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3364 | // .. DisableRcvr = 0 | ||
3365 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
3366 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3367 | // .. | ||
3368 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), | ||
3369 | // .. TRI_ENABLE = 0 | ||
3370 | // .. ==> 0XF80007B8[0:0] = 0x00000000U | ||
3371 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3372 | // .. L0_SEL = 0 | ||
3373 | // .. ==> 0XF80007B8[1:1] = 0x00000000U | ||
3374 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3375 | // .. L1_SEL = 0 | ||
3376 | // .. ==> 0XF80007B8[2:2] = 0x00000000U | ||
3377 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3378 | // .. L2_SEL = 0 | ||
3379 | // .. ==> 0XF80007B8[4:3] = 0x00000000U | ||
3380 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3381 | // .. L3_SEL = 0 | ||
3382 | // .. ==> 0XF80007B8[7:5] = 0x00000000U | ||
3383 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3384 | // .. Speed = 0 | ||
3385 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | ||
3386 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3387 | // .. IO_Type = 1 | ||
3388 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | ||
3389 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3390 | // .. PULLUP = 0 | ||
3391 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | ||
3392 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3393 | // .. DisableRcvr = 0 | ||
3394 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | ||
3395 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3396 | // .. | ||
3397 | EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), | ||
3398 | // .. TRI_ENABLE = 0 | ||
3399 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | ||
3400 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3401 | // .. L0_SEL = 0 | ||
3402 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | ||
3403 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3404 | // .. L1_SEL = 0 | ||
3405 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | ||
3406 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3407 | // .. L2_SEL = 0 | ||
3408 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | ||
3409 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3410 | // .. L3_SEL = 0 | ||
3411 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | ||
3412 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3413 | // .. Speed = 0 | ||
3414 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
3415 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3416 | // .. IO_Type = 1 | ||
3417 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
3418 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3419 | // .. PULLUP = 0 | ||
3420 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
3421 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3422 | // .. DisableRcvr = 0 | ||
3423 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
3424 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3425 | // .. | ||
3426 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | ||
3427 | // .. TRI_ENABLE = 0 | ||
3428 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
3429 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3430 | // .. L0_SEL = 0 | ||
3431 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
3432 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3433 | // .. L1_SEL = 0 | ||
3434 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
3435 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3436 | // .. L2_SEL = 0 | ||
3437 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
3438 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3439 | // .. L3_SEL = 7 | ||
3440 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
3441 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
3442 | // .. Speed = 0 | ||
3443 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
3444 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3445 | // .. IO_Type = 1 | ||
3446 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
3447 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3448 | // .. PULLUP = 0 | ||
3449 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
3450 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3451 | // .. DisableRcvr = 0 | ||
3452 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
3453 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3454 | // .. | ||
3455 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
3456 | // .. TRI_ENABLE = 1 | ||
3457 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
3458 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
3459 | // .. L0_SEL = 0 | ||
3460 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
3461 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3462 | // .. L1_SEL = 0 | ||
3463 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
3464 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3465 | // .. L2_SEL = 0 | ||
3466 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
3467 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3468 | // .. L3_SEL = 7 | ||
3469 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
3470 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
3471 | // .. Speed = 0 | ||
3472 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
3473 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3474 | // .. IO_Type = 1 | ||
3475 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
3476 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3477 | // .. PULLUP = 0 | ||
3478 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
3479 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3480 | // .. DisableRcvr = 0 | ||
3481 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
3482 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3483 | // .. | ||
3484 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
3485 | // .. TRI_ENABLE = 0 | ||
3486 | // .. ==> 0XF80007C8[0:0] = 0x00000000U | ||
3487 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3488 | // .. L0_SEL = 0 | ||
3489 | // .. ==> 0XF80007C8[1:1] = 0x00000000U | ||
3490 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3491 | // .. L1_SEL = 0 | ||
3492 | // .. ==> 0XF80007C8[2:2] = 0x00000000U | ||
3493 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3494 | // .. L2_SEL = 0 | ||
3495 | // .. ==> 0XF80007C8[4:3] = 0x00000000U | ||
3496 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3497 | // .. L3_SEL = 0 | ||
3498 | // .. ==> 0XF80007C8[7:5] = 0x00000000U | ||
3499 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3500 | // .. Speed = 0 | ||
3501 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | ||
3502 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3503 | // .. IO_Type = 1 | ||
3504 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | ||
3505 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3506 | // .. PULLUP = 0 | ||
3507 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | ||
3508 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3509 | // .. DisableRcvr = 0 | ||
3510 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | ||
3511 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3512 | // .. | ||
3513 | EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), | ||
3514 | // .. TRI_ENABLE = 0 | ||
3515 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | ||
3516 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3517 | // .. L0_SEL = 0 | ||
3518 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | ||
3519 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3520 | // .. L1_SEL = 0 | ||
3521 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | ||
3522 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3523 | // .. L2_SEL = 0 | ||
3524 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | ||
3525 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3526 | // .. L3_SEL = 0 | ||
3527 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | ||
3528 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
3529 | // .. Speed = 0 | ||
3530 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | ||
3531 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3532 | // .. IO_Type = 1 | ||
3533 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | ||
3534 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3535 | // .. PULLUP = 0 | ||
3536 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | ||
3537 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3538 | // .. DisableRcvr = 0 | ||
3539 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | ||
3540 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3541 | // .. | ||
3542 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | ||
3543 | // .. TRI_ENABLE = 0 | ||
3544 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
3545 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3546 | // .. L0_SEL = 0 | ||
3547 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
3548 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3549 | // .. L1_SEL = 0 | ||
3550 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
3551 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3552 | // .. L2_SEL = 0 | ||
3553 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
3554 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3555 | // .. L3_SEL = 4 | ||
3556 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
3557 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
3558 | // .. Speed = 0 | ||
3559 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
3560 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3561 | // .. IO_Type = 1 | ||
3562 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
3563 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3564 | // .. PULLUP = 0 | ||
3565 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
3566 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3567 | // .. DisableRcvr = 0 | ||
3568 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
3569 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3570 | // .. | ||
3571 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
3572 | // .. TRI_ENABLE = 0 | ||
3573 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
3574 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3575 | // .. L0_SEL = 0 | ||
3576 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
3577 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
3578 | // .. L1_SEL = 0 | ||
3579 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
3580 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
3581 | // .. L2_SEL = 0 | ||
3582 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
3583 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
3584 | // .. L3_SEL = 4 | ||
3585 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
3586 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
3587 | // .. Speed = 0 | ||
3588 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
3589 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3590 | // .. IO_Type = 1 | ||
3591 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
3592 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
3593 | // .. PULLUP = 0 | ||
3594 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
3595 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
3596 | // .. DisableRcvr = 0 | ||
3597 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
3598 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
3599 | // .. | ||
3600 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
3601 | // .. SDIO1_CD_SEL = 58 | ||
3602 | // .. ==> 0XF8000834[21:16] = 0x0000003AU | ||
3603 | // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U | ||
3604 | // .. | ||
3605 | EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), | ||
3606 | // .. FINISH: MIO PROGRAMMING | ||
3607 | // .. START: LOCK IT BACK | ||
3608 | // .. LOCK_KEY = 0X767B | ||
3609 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
3610 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
3611 | // .. | ||
3612 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
3613 | // .. FINISH: LOCK IT BACK | ||
3614 | // FINISH: top | ||
3615 | // | ||
3616 | EMIT_EXIT(), | ||
3617 | |||
3618 | // | ||
3619 | }; | ||
3620 | |||
3621 | unsigned long ps7_peripherals_init_data_3_0[] = { | ||
3622 | // START: top | ||
3623 | // .. START: SLCR SETTINGS | ||
3624 | // .. UNLOCK_KEY = 0XDF0D | ||
3625 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
3626 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
3627 | // .. | ||
3628 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
3629 | // .. FINISH: SLCR SETTINGS | ||
3630 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
3631 | // .. IBUF_DISABLE_MODE = 0x1 | ||
3632 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
3633 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
3634 | // .. TERM_DISABLE_MODE = 0x1 | ||
3635 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
3636 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
3637 | // .. | ||
3638 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
3639 | // .. IBUF_DISABLE_MODE = 0x1 | ||
3640 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
3641 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
3642 | // .. TERM_DISABLE_MODE = 0x1 | ||
3643 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
3644 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
3645 | // .. | ||
3646 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
3647 | // .. IBUF_DISABLE_MODE = 0x1 | ||
3648 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
3649 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
3650 | // .. TERM_DISABLE_MODE = 0x1 | ||
3651 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
3652 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
3653 | // .. | ||
3654 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
3655 | // .. IBUF_DISABLE_MODE = 0x1 | ||
3656 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
3657 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
3658 | // .. TERM_DISABLE_MODE = 0x1 | ||
3659 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
3660 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
3661 | // .. | ||
3662 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
3663 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
3664 | // .. START: LOCK IT BACK | ||
3665 | // .. LOCK_KEY = 0X767B | ||
3666 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
3667 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
3668 | // .. | ||
3669 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
3670 | // .. FINISH: LOCK IT BACK | ||
3671 | // .. START: SRAM/NOR SET OPMODE | ||
3672 | // .. FINISH: SRAM/NOR SET OPMODE | ||
3673 | // .. START: UART REGISTERS | ||
3674 | // .. BDIV = 0x6 | ||
3675 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
3676 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
3677 | // .. | ||
3678 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
3679 | // .. CD = 0x3e | ||
3680 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
3681 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
3682 | // .. | ||
3683 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
3684 | // .. STPBRK = 0x0 | ||
3685 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
3686 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
3687 | // .. STTBRK = 0x0 | ||
3688 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
3689 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
3690 | // .. RSTTO = 0x0 | ||
3691 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
3692 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
3693 | // .. TXDIS = 0x0 | ||
3694 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
3695 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
3696 | // .. TXEN = 0x1 | ||
3697 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
3698 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
3699 | // .. RXDIS = 0x0 | ||
3700 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
3701 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
3702 | // .. RXEN = 0x1 | ||
3703 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
3704 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
3705 | // .. TXRES = 0x1 | ||
3706 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
3707 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
3708 | // .. RXRES = 0x1 | ||
3709 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
3710 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
3711 | // .. | ||
3712 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
3713 | // .. CHMODE = 0x0 | ||
3714 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
3715 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
3716 | // .. NBSTOP = 0x0 | ||
3717 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
3718 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
3719 | // .. PAR = 0x4 | ||
3720 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
3721 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
3722 | // .. CHRL = 0x0 | ||
3723 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
3724 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
3725 | // .. CLKS = 0x0 | ||
3726 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
3727 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
3728 | // .. | ||
3729 | EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), | ||
3730 | // .. FINISH: UART REGISTERS | ||
3731 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
3732 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
3733 | // .. .. a = 0XC5ACCE55 | ||
3734 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
3735 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
3736 | // .. .. | ||
3737 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
3738 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
3739 | // .. .. START: TRACE CURRENT PORT SIZE | ||
3740 | // .. .. a = 2 | ||
3741 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
3742 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
3743 | // .. .. | ||
3744 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
3745 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
3746 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
3747 | // .. .. a = 0X0 | ||
3748 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
3749 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
3750 | // .. .. | ||
3751 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
3752 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
3753 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
3754 | // .. START: QSPI REGISTERS | ||
3755 | // .. Holdb_dr = 1 | ||
3756 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
3757 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
3758 | // .. | ||
3759 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
3760 | // .. FINISH: QSPI REGISTERS | ||
3761 | // .. START: PL POWER ON RESET REGISTERS | ||
3762 | // .. PCFG_POR_CNT_4K = 0 | ||
3763 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
3764 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
3765 | // .. | ||
3766 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
3767 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
3768 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
3769 | // .. .. START: NAND SET CYCLE | ||
3770 | // .. .. FINISH: NAND SET CYCLE | ||
3771 | // .. .. START: OPMODE | ||
3772 | // .. .. FINISH: OPMODE | ||
3773 | // .. .. START: DIRECT COMMAND | ||
3774 | // .. .. FINISH: DIRECT COMMAND | ||
3775 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
3776 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
3777 | // .. .. START: DIRECT COMMAND | ||
3778 | // .. .. FINISH: DIRECT COMMAND | ||
3779 | // .. .. START: NOR CS0 BASE ADDRESS | ||
3780 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
3781 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
3782 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
3783 | // .. .. START: DIRECT COMMAND | ||
3784 | // .. .. FINISH: DIRECT COMMAND | ||
3785 | // .. .. START: NOR CS1 BASE ADDRESS | ||
3786 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
3787 | // .. .. START: USB RESET | ||
3788 | // .. .. .. START: USB0 RESET | ||
3789 | // .. .. .. .. START: DIR MODE BANK 0 | ||
3790 | // .. .. .. .. DIRECTION_0 = 0x80 | ||
3791 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | ||
3792 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
3793 | // .. .. .. .. | ||
3794 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | ||
3795 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
3796 | // .. .. .. .. START: DIR MODE BANK 1 | ||
3797 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
3798 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3799 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
3800 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
3801 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
3802 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
3803 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
3804 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
3805 | // .. .. .. .. | ||
3806 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
3807 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3808 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3809 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3810 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3811 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3812 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3813 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3814 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
3815 | // .. .. .. .. OP_ENABLE_0 = 0x80 | ||
3816 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | ||
3817 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
3818 | // .. .. .. .. | ||
3819 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | ||
3820 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
3821 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
3822 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
3823 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3824 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
3825 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
3826 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
3827 | // .. .. .. .. DATA_0_LSW = 0x0 | ||
3828 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | ||
3829 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | ||
3830 | // .. .. .. .. | ||
3831 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | ||
3832 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3833 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3834 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3835 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3836 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3837 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3838 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3839 | // .. .. .. .. START: ADD 1 MS DELAY | ||
3840 | // .. .. .. .. | ||
3841 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
3842 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
3843 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3844 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
3845 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
3846 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
3847 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
3848 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
3849 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
3850 | // .. .. .. .. | ||
3851 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
3852 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3853 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3854 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3855 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3856 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3857 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3858 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3859 | // .. .. .. FINISH: USB0 RESET | ||
3860 | // .. .. .. START: USB1 RESET | ||
3861 | // .. .. .. .. START: DIR MODE BANK 0 | ||
3862 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
3863 | // .. .. .. .. START: DIR MODE BANK 1 | ||
3864 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
3865 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3866 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3867 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3868 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3869 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3870 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3871 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3872 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3873 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
3874 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
3875 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
3876 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
3877 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3878 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3879 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3880 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3881 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3882 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3883 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3884 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3885 | // .. .. .. .. START: ADD 1 MS DELAY | ||
3886 | // .. .. .. .. | ||
3887 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
3888 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
3889 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3890 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3891 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3892 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3893 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3894 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3895 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3896 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3897 | // .. .. .. FINISH: USB1 RESET | ||
3898 | // .. .. FINISH: USB RESET | ||
3899 | // .. .. START: ENET RESET | ||
3900 | // .. .. .. START: ENET0 RESET | ||
3901 | // .. .. .. .. START: DIR MODE BANK 0 | ||
3902 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
3903 | // .. .. .. .. START: DIR MODE BANK 1 | ||
3904 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
3905 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3906 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3907 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3908 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3909 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3910 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3911 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3912 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3913 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
3914 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
3915 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
3916 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
3917 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3918 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3919 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3920 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3921 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3922 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3923 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3924 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3925 | // .. .. .. .. START: ADD 1 MS DELAY | ||
3926 | // .. .. .. .. | ||
3927 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
3928 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
3929 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3930 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3931 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3932 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3933 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3934 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3935 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3936 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3937 | // .. .. .. FINISH: ENET0 RESET | ||
3938 | // .. .. .. START: ENET1 RESET | ||
3939 | // .. .. .. .. START: DIR MODE BANK 0 | ||
3940 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
3941 | // .. .. .. .. START: DIR MODE BANK 1 | ||
3942 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
3943 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3944 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3945 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3946 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3947 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3948 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3949 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3950 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3951 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
3952 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
3953 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
3954 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
3955 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3956 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3957 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3958 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3959 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3960 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
3961 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3962 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
3963 | // .. .. .. .. START: ADD 1 MS DELAY | ||
3964 | // .. .. .. .. | ||
3965 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
3966 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
3967 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3968 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3969 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3970 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3971 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3972 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3973 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3974 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3975 | // .. .. .. FINISH: ENET1 RESET | ||
3976 | // .. .. FINISH: ENET RESET | ||
3977 | // .. .. START: I2C RESET | ||
3978 | // .. .. .. START: I2C0 RESET | ||
3979 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
3980 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
3981 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
3982 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
3983 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3984 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
3985 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3986 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
3987 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3988 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
3989 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3990 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
3991 | // .. .. .. .. START: OUTPUT ENABLE | ||
3992 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
3993 | // .. .. .. .. START: OUTPUT ENABLE | ||
3994 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
3995 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3996 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
3997 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3998 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
3999 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
4000 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
4001 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
4002 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
4003 | // .. .. .. .. START: ADD 1 MS DELAY | ||
4004 | // .. .. .. .. | ||
4005 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
4006 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
4007 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4008 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4009 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4010 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4011 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4012 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4013 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4014 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4015 | // .. .. .. FINISH: I2C0 RESET | ||
4016 | // .. .. .. START: I2C1 RESET | ||
4017 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
4018 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
4019 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
4020 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
4021 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4022 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4023 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4024 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4025 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4026 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4027 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4028 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4029 | // .. .. .. .. START: OUTPUT ENABLE | ||
4030 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
4031 | // .. .. .. .. START: OUTPUT ENABLE | ||
4032 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
4033 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
4034 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
4035 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
4036 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
4037 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
4038 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
4039 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
4040 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
4041 | // .. .. .. .. START: ADD 1 MS DELAY | ||
4042 | // .. .. .. .. | ||
4043 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
4044 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
4045 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4046 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4047 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4048 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
4049 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4050 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
4051 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4052 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
4053 | // .. .. .. FINISH: I2C1 RESET | ||
4054 | // .. .. FINISH: I2C RESET | ||
4055 | // .. .. START: NOR CHIP SELECT | ||
4056 | // .. .. .. START: DIR MODE BANK 0 | ||
4057 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
4058 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4059 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
4060 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
4061 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
4062 | // .. .. FINISH: NOR CHIP SELECT | ||
4063 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
4064 | // FINISH: top | ||
4065 | // | ||
4066 | EMIT_EXIT(), | ||
4067 | |||
4068 | // | ||
4069 | }; | ||
4070 | |||
4071 | unsigned long ps7_post_config_3_0[] = { | ||
4072 | // START: top | ||
4073 | // .. START: SLCR SETTINGS | ||
4074 | // .. UNLOCK_KEY = 0XDF0D | ||
4075 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
4076 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
4077 | // .. | ||
4078 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
4079 | // .. FINISH: SLCR SETTINGS | ||
4080 | // .. START: ENABLING LEVEL SHIFTER | ||
4081 | // .. USER_LVL_INP_EN_0 = 1 | ||
4082 | // .. ==> 0XF8000900[3:3] = 0x00000001U | ||
4083 | // .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
4084 | // .. USER_LVL_OUT_EN_0 = 1 | ||
4085 | // .. ==> 0XF8000900[2:2] = 0x00000001U | ||
4086 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
4087 | // .. USER_LVL_INP_EN_1 = 1 | ||
4088 | // .. ==> 0XF8000900[1:1] = 0x00000001U | ||
4089 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
4090 | // .. USER_LVL_OUT_EN_1 = 1 | ||
4091 | // .. ==> 0XF8000900[0:0] = 0x00000001U | ||
4092 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4093 | // .. | ||
4094 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
4095 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
4096 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
4097 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
4098 | // .. .. a = 0XC5ACCE55 | ||
4099 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
4100 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
4101 | // .. .. | ||
4102 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
4103 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
4104 | // .. .. START: TRACE CURRENT PORT SIZE | ||
4105 | // .. .. a = 2 | ||
4106 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
4107 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
4108 | // .. .. | ||
4109 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
4110 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
4111 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
4112 | // .. .. a = 0X0 | ||
4113 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
4114 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
4115 | // .. .. | ||
4116 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
4117 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
4118 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
4119 | // .. START: FPGA RESETS TO 0 | ||
4120 | // .. reserved_3 = 0 | ||
4121 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
4122 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
4123 | // .. reserved_FPGA_ACP_RST = 0 | ||
4124 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
4125 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
4126 | // .. reserved_FPGA_AXDS3_RST = 0 | ||
4127 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
4128 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
4129 | // .. reserved_FPGA_AXDS2_RST = 0 | ||
4130 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
4131 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
4132 | // .. reserved_FPGA_AXDS1_RST = 0 | ||
4133 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
4134 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
4135 | // .. reserved_FPGA_AXDS0_RST = 0 | ||
4136 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
4137 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
4138 | // .. reserved_2 = 0 | ||
4139 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
4140 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
4141 | // .. reserved_FSSW1_FPGA_RST = 0 | ||
4142 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
4143 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
4144 | // .. reserved_FSSW0_FPGA_RST = 0 | ||
4145 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
4146 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
4147 | // .. reserved_1 = 0 | ||
4148 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
4149 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
4150 | // .. reserved_FPGA_FMSW1_RST = 0 | ||
4151 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
4152 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
4153 | // .. reserved_FPGA_FMSW0_RST = 0 | ||
4154 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
4155 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
4156 | // .. reserved_FPGA_DMA3_RST = 0 | ||
4157 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
4158 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
4159 | // .. reserved_FPGA_DMA2_RST = 0 | ||
4160 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
4161 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
4162 | // .. reserved_FPGA_DMA1_RST = 0 | ||
4163 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
4164 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
4165 | // .. reserved_FPGA_DMA0_RST = 0 | ||
4166 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
4167 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
4168 | // .. reserved = 0 | ||
4169 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
4170 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
4171 | // .. FPGA3_OUT_RST = 0 | ||
4172 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
4173 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
4174 | // .. FPGA2_OUT_RST = 0 | ||
4175 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
4176 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
4177 | // .. FPGA1_OUT_RST = 0 | ||
4178 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
4179 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
4180 | // .. FPGA0_OUT_RST = 0 | ||
4181 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
4182 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4183 | // .. | ||
4184 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
4185 | // .. FINISH: FPGA RESETS TO 0 | ||
4186 | // .. START: AFI REGISTERS | ||
4187 | // .. .. START: AFI0 REGISTERS | ||
4188 | // .. .. FINISH: AFI0 REGISTERS | ||
4189 | // .. .. START: AFI1 REGISTERS | ||
4190 | // .. .. FINISH: AFI1 REGISTERS | ||
4191 | // .. .. START: AFI2 REGISTERS | ||
4192 | // .. .. FINISH: AFI2 REGISTERS | ||
4193 | // .. .. START: AFI3 REGISTERS | ||
4194 | // .. .. FINISH: AFI3 REGISTERS | ||
4195 | // .. FINISH: AFI REGISTERS | ||
4196 | // .. START: LOCK IT BACK | ||
4197 | // .. LOCK_KEY = 0X767B | ||
4198 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
4199 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
4200 | // .. | ||
4201 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
4202 | // .. FINISH: LOCK IT BACK | ||
4203 | // FINISH: top | ||
4204 | // | ||
4205 | EMIT_EXIT(), | ||
4206 | |||
4207 | // | ||
4208 | }; | ||
4209 | |||
4210 | unsigned long ps7_debug_3_0[] = { | ||
4211 | // START: top | ||
4212 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
4213 | // .. .. START: UNLOCKING CTI REGISTERS | ||
4214 | // .. .. KEY = 0XC5ACCE55 | ||
4215 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
4216 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
4217 | // .. .. | ||
4218 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
4219 | // .. .. KEY = 0XC5ACCE55 | ||
4220 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
4221 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
4222 | // .. .. | ||
4223 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
4224 | // .. .. KEY = 0XC5ACCE55 | ||
4225 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
4226 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
4227 | // .. .. | ||
4228 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
4229 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
4230 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
4231 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
4232 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
4233 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
4234 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
4235 | // FINISH: top | ||
4236 | // | ||
4237 | EMIT_EXIT(), | ||
4238 | |||
4239 | // | ||
4240 | }; | ||
4241 | |||
4242 | unsigned long ps7_pll_init_data_2_0[] = { | ||
4243 | // START: top | ||
4244 | // .. START: SLCR SETTINGS | ||
4245 | // .. UNLOCK_KEY = 0XDF0D | ||
4246 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
4247 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
4248 | // .. | ||
4249 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
4250 | // .. FINISH: SLCR SETTINGS | ||
4251 | // .. START: PLL SLCR REGISTERS | ||
4252 | // .. .. START: ARM PLL INIT | ||
4253 | // .. .. PLL_RES = 0x4 | ||
4254 | // .. .. ==> 0XF8000110[7:4] = 0x00000004U | ||
4255 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
4256 | // .. .. PLL_CP = 0x2 | ||
4257 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
4258 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
4259 | // .. .. LOCK_CNT = 0xfa | ||
4260 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | ||
4261 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
4262 | // .. .. | ||
4263 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), | ||
4264 | // .. .. .. START: UPDATE FB_DIV | ||
4265 | // .. .. .. PLL_FDIV = 0x3c | ||
4266 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU | ||
4267 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
4268 | // .. .. .. | ||
4269 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), | ||
4270 | // .. .. .. FINISH: UPDATE FB_DIV | ||
4271 | // .. .. .. START: BY PASS PLL | ||
4272 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
4273 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
4274 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
4275 | // .. .. .. | ||
4276 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
4277 | // .. .. .. FINISH: BY PASS PLL | ||
4278 | // .. .. .. START: ASSERT RESET | ||
4279 | // .. .. .. PLL_RESET = 1 | ||
4280 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
4281 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4282 | // .. .. .. | ||
4283 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
4284 | // .. .. .. FINISH: ASSERT RESET | ||
4285 | // .. .. .. START: DEASSERT RESET | ||
4286 | // .. .. .. PLL_RESET = 0 | ||
4287 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
4288 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4289 | // .. .. .. | ||
4290 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
4291 | // .. .. .. FINISH: DEASSERT RESET | ||
4292 | // .. .. .. START: CHECK PLL STATUS | ||
4293 | // .. .. .. ARM_PLL_LOCK = 1 | ||
4294 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
4295 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4296 | // .. .. .. | ||
4297 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
4298 | // .. .. .. FINISH: CHECK PLL STATUS | ||
4299 | // .. .. .. START: REMOVE PLL BY PASS | ||
4300 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
4301 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
4302 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
4303 | // .. .. .. | ||
4304 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
4305 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
4306 | // .. .. .. SRCSEL = 0x0 | ||
4307 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
4308 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4309 | // .. .. .. DIVISOR = 0x3 | ||
4310 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U | ||
4311 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U | ||
4312 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
4313 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
4314 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
4315 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
4316 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
4317 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
4318 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
4319 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
4320 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
4321 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
4322 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
4323 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
4324 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
4325 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
4326 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
4327 | // .. .. .. | ||
4328 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), | ||
4329 | // .. .. FINISH: ARM PLL INIT | ||
4330 | // .. .. START: DDR PLL INIT | ||
4331 | // .. .. PLL_RES = 0x2 | ||
4332 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | ||
4333 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
4334 | // .. .. PLL_CP = 0x2 | ||
4335 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
4336 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
4337 | // .. .. LOCK_CNT = 0x12c | ||
4338 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | ||
4339 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | ||
4340 | // .. .. | ||
4341 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | ||
4342 | // .. .. .. START: UPDATE FB_DIV | ||
4343 | // .. .. .. PLL_FDIV = 0x20 | ||
4344 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | ||
4345 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | ||
4346 | // .. .. .. | ||
4347 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | ||
4348 | // .. .. .. FINISH: UPDATE FB_DIV | ||
4349 | // .. .. .. START: BY PASS PLL | ||
4350 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
4351 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
4352 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
4353 | // .. .. .. | ||
4354 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
4355 | // .. .. .. FINISH: BY PASS PLL | ||
4356 | // .. .. .. START: ASSERT RESET | ||
4357 | // .. .. .. PLL_RESET = 1 | ||
4358 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
4359 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4360 | // .. .. .. | ||
4361 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
4362 | // .. .. .. FINISH: ASSERT RESET | ||
4363 | // .. .. .. START: DEASSERT RESET | ||
4364 | // .. .. .. PLL_RESET = 0 | ||
4365 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
4366 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4367 | // .. .. .. | ||
4368 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
4369 | // .. .. .. FINISH: DEASSERT RESET | ||
4370 | // .. .. .. START: CHECK PLL STATUS | ||
4371 | // .. .. .. DDR_PLL_LOCK = 1 | ||
4372 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
4373 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
4374 | // .. .. .. | ||
4375 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
4376 | // .. .. .. FINISH: CHECK PLL STATUS | ||
4377 | // .. .. .. START: REMOVE PLL BY PASS | ||
4378 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
4379 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
4380 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
4381 | // .. .. .. | ||
4382 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
4383 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
4384 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
4385 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
4386 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4387 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
4388 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
4389 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
4390 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
4391 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
4392 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
4393 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
4394 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
4395 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
4396 | // .. .. .. | ||
4397 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
4398 | // .. .. FINISH: DDR PLL INIT | ||
4399 | // .. .. START: IO PLL INIT | ||
4400 | // .. .. PLL_RES = 0x4 | ||
4401 | // .. .. ==> 0XF8000118[7:4] = 0x00000004U | ||
4402 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
4403 | // .. .. PLL_CP = 0x2 | ||
4404 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
4405 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
4406 | // .. .. LOCK_CNT = 0xfa | ||
4407 | // .. .. ==> 0XF8000118[21:12] = 0x000000FAU | ||
4408 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
4409 | // .. .. | ||
4410 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), | ||
4411 | // .. .. .. START: UPDATE FB_DIV | ||
4412 | // .. .. .. PLL_FDIV = 0x3c | ||
4413 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU | ||
4414 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
4415 | // .. .. .. | ||
4416 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), | ||
4417 | // .. .. .. FINISH: UPDATE FB_DIV | ||
4418 | // .. .. .. START: BY PASS PLL | ||
4419 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
4420 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
4421 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
4422 | // .. .. .. | ||
4423 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
4424 | // .. .. .. FINISH: BY PASS PLL | ||
4425 | // .. .. .. START: ASSERT RESET | ||
4426 | // .. .. .. PLL_RESET = 1 | ||
4427 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
4428 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4429 | // .. .. .. | ||
4430 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
4431 | // .. .. .. FINISH: ASSERT RESET | ||
4432 | // .. .. .. START: DEASSERT RESET | ||
4433 | // .. .. .. PLL_RESET = 0 | ||
4434 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
4435 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4436 | // .. .. .. | ||
4437 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
4438 | // .. .. .. FINISH: DEASSERT RESET | ||
4439 | // .. .. .. START: CHECK PLL STATUS | ||
4440 | // .. .. .. IO_PLL_LOCK = 1 | ||
4441 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
4442 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
4443 | // .. .. .. | ||
4444 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
4445 | // .. .. .. FINISH: CHECK PLL STATUS | ||
4446 | // .. .. .. START: REMOVE PLL BY PASS | ||
4447 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
4448 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
4449 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
4450 | // .. .. .. | ||
4451 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
4452 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
4453 | // .. .. FINISH: IO PLL INIT | ||
4454 | // .. FINISH: PLL SLCR REGISTERS | ||
4455 | // .. START: LOCK IT BACK | ||
4456 | // .. LOCK_KEY = 0X767B | ||
4457 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
4458 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
4459 | // .. | ||
4460 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
4461 | // .. FINISH: LOCK IT BACK | ||
4462 | // FINISH: top | ||
4463 | // | ||
4464 | EMIT_EXIT(), | ||
4465 | |||
4466 | // | ||
4467 | }; | ||
4468 | |||
4469 | unsigned long ps7_clock_init_data_2_0[] = { | ||
4470 | // START: top | ||
4471 | // .. START: SLCR SETTINGS | ||
4472 | // .. UNLOCK_KEY = 0XDF0D | ||
4473 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
4474 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
4475 | // .. | ||
4476 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
4477 | // .. FINISH: SLCR SETTINGS | ||
4478 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
4479 | // .. CLKACT = 0x1 | ||
4480 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
4481 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4482 | // .. DIVISOR0 = 0x23 | ||
4483 | // .. ==> 0XF8000128[13:8] = 0x00000023U | ||
4484 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | ||
4485 | // .. DIVISOR1 = 0x3 | ||
4486 | // .. ==> 0XF8000128[25:20] = 0x00000003U | ||
4487 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | ||
4488 | // .. | ||
4489 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | ||
4490 | // .. CLKACT = 0x1 | ||
4491 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
4492 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4493 | // .. SRCSEL = 0x0 | ||
4494 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
4495 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
4496 | // .. | ||
4497 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
4498 | // .. CLKACT = 0x1 | ||
4499 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
4500 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4501 | // .. SRCSEL = 0x0 | ||
4502 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
4503 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
4504 | // .. DIVISOR = 0x10 | ||
4505 | // .. ==> 0XF8000140[13:8] = 0x00000010U | ||
4506 | // .. ==> MASK : 0x00003F00U VAL : 0x00001000U | ||
4507 | // .. DIVISOR1 = 0x1 | ||
4508 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
4509 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
4510 | // .. | ||
4511 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), | ||
4512 | // .. CLKACT = 0x1 | ||
4513 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
4514 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4515 | // .. SRCSEL = 0x0 | ||
4516 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
4517 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4518 | // .. DIVISOR = 0xa | ||
4519 | // .. ==> 0XF800014C[13:8] = 0x0000000AU | ||
4520 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
4521 | // .. | ||
4522 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), | ||
4523 | // .. CLKACT0 = 0x0 | ||
4524 | // .. ==> 0XF8000150[0:0] = 0x00000000U | ||
4525 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4526 | // .. CLKACT1 = 0x1 | ||
4527 | // .. ==> 0XF8000150[1:1] = 0x00000001U | ||
4528 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
4529 | // .. SRCSEL = 0x0 | ||
4530 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
4531 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4532 | // .. DIVISOR = 0x28 | ||
4533 | // .. ==> 0XF8000150[13:8] = 0x00000028U | ||
4534 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
4535 | // .. | ||
4536 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), | ||
4537 | // .. CLKACT0 = 0x0 | ||
4538 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
4539 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4540 | // .. CLKACT1 = 0x1 | ||
4541 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
4542 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
4543 | // .. SRCSEL = 0x0 | ||
4544 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
4545 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4546 | // .. DIVISOR = 0x28 | ||
4547 | // .. ==> 0XF8000154[13:8] = 0x00000028U | ||
4548 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
4549 | // .. | ||
4550 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), | ||
4551 | // .. .. START: TRACE CLOCK | ||
4552 | // .. .. FINISH: TRACE CLOCK | ||
4553 | // .. .. CLKACT = 0x1 | ||
4554 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
4555 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4556 | // .. .. SRCSEL = 0x0 | ||
4557 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
4558 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4559 | // .. .. DIVISOR = 0xa | ||
4560 | // .. .. ==> 0XF8000168[13:8] = 0x0000000AU | ||
4561 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
4562 | // .. .. | ||
4563 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), | ||
4564 | // .. .. SRCSEL = 0x0 | ||
4565 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
4566 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4567 | // .. .. DIVISOR0 = 0x14 | ||
4568 | // .. .. ==> 0XF8000170[13:8] = 0x00000014U | ||
4569 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
4570 | // .. .. DIVISOR1 = 0x1 | ||
4571 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
4572 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
4573 | // .. .. | ||
4574 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), | ||
4575 | // .. .. SRCSEL = 0x0 | ||
4576 | // .. .. ==> 0XF8000180[5:4] = 0x00000000U | ||
4577 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4578 | // .. .. DIVISOR0 = 0x14 | ||
4579 | // .. .. ==> 0XF8000180[13:8] = 0x00000014U | ||
4580 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
4581 | // .. .. DIVISOR1 = 0x1 | ||
4582 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
4583 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
4584 | // .. .. | ||
4585 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), | ||
4586 | // .. .. SRCSEL = 0x0 | ||
4587 | // .. .. ==> 0XF8000190[5:4] = 0x00000000U | ||
4588 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4589 | // .. .. DIVISOR0 = 0x3c | ||
4590 | // .. .. ==> 0XF8000190[13:8] = 0x0000003CU | ||
4591 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U | ||
4592 | // .. .. DIVISOR1 = 0x1 | ||
4593 | // .. .. ==> 0XF8000190[25:20] = 0x00000001U | ||
4594 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
4595 | // .. .. | ||
4596 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), | ||
4597 | // .. .. SRCSEL = 0x0 | ||
4598 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
4599 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
4600 | // .. .. DIVISOR0 = 0x28 | ||
4601 | // .. .. ==> 0XF80001A0[13:8] = 0x00000028U | ||
4602 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
4603 | // .. .. DIVISOR1 = 0x1 | ||
4604 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
4605 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
4606 | // .. .. | ||
4607 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), | ||
4608 | // .. .. CLK_621_TRUE = 0x1 | ||
4609 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
4610 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4611 | // .. .. | ||
4612 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
4613 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
4614 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
4615 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
4616 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
4617 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
4618 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
4619 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
4620 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
4621 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
4622 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
4623 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
4624 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
4625 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
4626 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
4627 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
4628 | // .. .. SDI0_CPU_1XCLKACT = 0x0 | ||
4629 | // .. .. ==> 0XF800012C[10:10] = 0x00000000U | ||
4630 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
4631 | // .. .. SDI1_CPU_1XCLKACT = 0x1 | ||
4632 | // .. .. ==> 0XF800012C[11:11] = 0x00000001U | ||
4633 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U | ||
4634 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
4635 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
4636 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
4637 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
4638 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
4639 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
4640 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
4641 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
4642 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
4643 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
4644 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
4645 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
4646 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
4647 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
4648 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
4649 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
4650 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
4651 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
4652 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
4653 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
4654 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
4655 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
4656 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
4657 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
4658 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
4659 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
4660 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
4661 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
4662 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
4663 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
4664 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
4665 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
4666 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
4667 | // .. .. | ||
4668 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), | ||
4669 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
4670 | // .. START: THIS SHOULD BE BLANK | ||
4671 | // .. FINISH: THIS SHOULD BE BLANK | ||
4672 | // .. START: LOCK IT BACK | ||
4673 | // .. LOCK_KEY = 0X767B | ||
4674 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
4675 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
4676 | // .. | ||
4677 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
4678 | // .. FINISH: LOCK IT BACK | ||
4679 | // FINISH: top | ||
4680 | // | ||
4681 | EMIT_EXIT(), | ||
4682 | |||
4683 | // | ||
4684 | }; | ||
4685 | |||
4686 | unsigned long ps7_ddr_init_data_2_0[] = { | ||
4687 | // START: top | ||
4688 | // .. START: DDR INITIALIZATION | ||
4689 | // .. .. START: LOCK DDR | ||
4690 | // .. .. reg_ddrc_soft_rstb = 0 | ||
4691 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
4692 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4693 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
4694 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
4695 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
4696 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
4697 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
4698 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
4699 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
4700 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
4701 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
4702 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
4703 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
4704 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
4705 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
4706 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
4707 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
4708 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
4709 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
4710 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
4711 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
4712 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
4713 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
4714 | // .. .. | ||
4715 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
4716 | // .. .. FINISH: LOCK DDR | ||
4717 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | ||
4718 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | ||
4719 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | ||
4720 | // .. .. reg_ddrc_active_ranks = 0x1 | ||
4721 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
4722 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
4723 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
4724 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
4725 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
4726 | // .. .. reg_ddrc_wr_odt_block = 0x1 | ||
4727 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | ||
4728 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | ||
4729 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | ||
4730 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | ||
4731 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
4732 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | ||
4733 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | ||
4734 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | ||
4735 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | ||
4736 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | ||
4737 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
4738 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | ||
4739 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | ||
4740 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
4741 | // .. .. | ||
4742 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), | ||
4743 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
4744 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
4745 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
4746 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
4747 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
4748 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
4749 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
4750 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
4751 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
4752 | // .. .. | ||
4753 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
4754 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
4755 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
4756 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
4757 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
4758 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
4759 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
4760 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
4761 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
4762 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
4763 | // .. .. | ||
4764 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
4765 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
4766 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
4767 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
4768 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
4769 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
4770 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
4771 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
4772 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
4773 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
4774 | // .. .. | ||
4775 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
4776 | // .. .. reg_ddrc_t_rc = 0x1a | ||
4777 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
4778 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
4779 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | ||
4780 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | ||
4781 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | ||
4782 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
4783 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
4784 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
4785 | // .. .. | ||
4786 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | ||
4787 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
4788 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
4789 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
4790 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
4791 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
4792 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
4793 | // .. .. reg_ddrc_t_faw = 0x16 | ||
4794 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | ||
4795 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | ||
4796 | // .. .. reg_ddrc_t_ras_max = 0x24 | ||
4797 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | ||
4798 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | ||
4799 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
4800 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
4801 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
4802 | // .. .. reg_ddrc_t_cke = 0x4 | ||
4803 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
4804 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
4805 | // .. .. | ||
4806 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | ||
4807 | // .. .. reg_ddrc_write_latency = 0x5 | ||
4808 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
4809 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
4810 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
4811 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
4812 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
4813 | // .. .. reg_ddrc_wr2rd = 0xe | ||
4814 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
4815 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
4816 | // .. .. reg_ddrc_t_xp = 0x4 | ||
4817 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
4818 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
4819 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
4820 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
4821 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
4822 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
4823 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
4824 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
4825 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
4826 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
4827 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
4828 | // .. .. | ||
4829 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
4830 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
4831 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
4832 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
4833 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
4834 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
4835 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
4836 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
4837 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
4838 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
4839 | // .. .. reg_ddrc_t_rp = 0x7 | ||
4840 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
4841 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
4842 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
4843 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
4844 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
4845 | // .. .. reg_ddrc_sdram = 0x1 | ||
4846 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | ||
4847 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
4848 | // .. .. reg_ddrc_mobile = 0x0 | ||
4849 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
4850 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
4851 | // .. .. reg_ddrc_clock_stop_en = 0x0 | ||
4852 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
4853 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
4854 | // .. .. reg_ddrc_read_latency = 0x7 | ||
4855 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
4856 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
4857 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
4858 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
4859 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
4860 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
4861 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
4862 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
4863 | // .. .. reg_ddrc_loopback = 0x0 | ||
4864 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | ||
4865 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
4866 | // .. .. | ||
4867 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | ||
4868 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
4869 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
4870 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4871 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
4872 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
4873 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
4874 | // .. .. reg_ddrc_max_rank_rd = 0xf | ||
4875 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | ||
4876 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | ||
4877 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
4878 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
4879 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
4880 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
4881 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
4882 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
4883 | // .. .. reg_ddrc_mr_data = 0x0 | ||
4884 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
4885 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
4886 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
4887 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
4888 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
4889 | // .. .. reg_ddrc_mr_type = 0x0 | ||
4890 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
4891 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
4892 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
4893 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
4894 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
4895 | // .. .. | ||
4896 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | ||
4897 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
4898 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
4899 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
4900 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
4901 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
4902 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
4903 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
4904 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
4905 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
4906 | // .. .. | ||
4907 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
4908 | // .. .. reg_ddrc_emr2 = 0x8 | ||
4909 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
4910 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
4911 | // .. .. reg_ddrc_emr3 = 0x0 | ||
4912 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
4913 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
4914 | // .. .. | ||
4915 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
4916 | // .. .. reg_ddrc_mr = 0x930 | ||
4917 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
4918 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
4919 | // .. .. reg_ddrc_emr = 0x4 | ||
4920 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
4921 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
4922 | // .. .. | ||
4923 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
4924 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
4925 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
4926 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
4927 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | ||
4928 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | ||
4929 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | ||
4930 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
4931 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
4932 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
4933 | // .. .. reg_ddrc_burstchop = 0x0 | ||
4934 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
4935 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
4936 | // .. .. | ||
4937 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | ||
4938 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
4939 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
4940 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
4941 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
4942 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
4943 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
4944 | // .. .. reg_phy_debug_mode = 0x0 | ||
4945 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | ||
4946 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
4947 | // .. .. reg_phy_wr_level_start = 0x0 | ||
4948 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | ||
4949 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
4950 | // .. .. reg_phy_rd_level_start = 0x0 | ||
4951 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | ||
4952 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
4953 | // .. .. reg_phy_dq0_wait_t = 0x0 | ||
4954 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | ||
4955 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | ||
4956 | // .. .. | ||
4957 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | ||
4958 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
4959 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
4960 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
4961 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
4962 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
4963 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
4964 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
4965 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
4966 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
4967 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
4968 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
4969 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
4970 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
4971 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
4972 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
4973 | // .. .. | ||
4974 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
4975 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
4976 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
4977 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
4978 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
4979 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
4980 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
4981 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
4982 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
4983 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
4984 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
4985 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
4986 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
4987 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
4988 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
4989 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
4990 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
4991 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
4992 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
4993 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
4994 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
4995 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
4996 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
4997 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
4998 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
4999 | // .. .. | ||
5000 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
5001 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
5002 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
5003 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
5004 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
5005 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
5006 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
5007 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
5008 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
5009 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
5010 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
5011 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
5012 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
5013 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
5014 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
5015 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
5016 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | ||
5017 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | ||
5018 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | ||
5019 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
5020 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
5021 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
5022 | // .. .. | ||
5023 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | ||
5024 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | ||
5025 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
5026 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
5027 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | ||
5028 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
5029 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
5030 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | ||
5031 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | ||
5032 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | ||
5033 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | ||
5034 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | ||
5035 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
5036 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
5037 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
5038 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
5039 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
5040 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
5041 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
5042 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
5043 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
5044 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
5045 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | ||
5046 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | ||
5047 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | ||
5048 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | ||
5049 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | ||
5050 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | ||
5051 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | ||
5052 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | ||
5053 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
5054 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | ||
5055 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | ||
5056 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | ||
5057 | // .. .. | ||
5058 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | ||
5059 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
5060 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
5061 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
5062 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
5063 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
5064 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
5065 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
5066 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
5067 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
5068 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
5069 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
5070 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
5071 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
5072 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
5073 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
5074 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
5075 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
5076 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5077 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
5078 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
5079 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5080 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
5081 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
5082 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
5083 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
5084 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
5085 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
5086 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
5087 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
5088 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
5089 | // .. .. | ||
5090 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
5091 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | ||
5092 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | ||
5093 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | ||
5094 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | ||
5095 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | ||
5096 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | ||
5097 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
5098 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
5099 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5100 | // .. .. | ||
5101 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | ||
5102 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
5103 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
5104 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
5105 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
5106 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
5107 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
5108 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
5109 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
5110 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
5111 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
5112 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
5113 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
5114 | // .. .. | ||
5115 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
5116 | // .. .. reg_ddrc_pageclose = 0x0 | ||
5117 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
5118 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5119 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
5120 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
5121 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
5122 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
5123 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
5124 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
5125 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
5126 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
5127 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
5128 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
5129 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
5130 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
5131 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
5132 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
5133 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5134 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
5135 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
5136 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
5137 | // .. .. | ||
5138 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
5139 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
5140 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
5141 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
5142 | // .. .. reg_arb_go2critical_en = 0x1 | ||
5143 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
5144 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
5145 | // .. .. | ||
5146 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
5147 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
5148 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
5149 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
5150 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
5151 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
5152 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
5153 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
5154 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
5155 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
5156 | // .. .. | ||
5157 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
5158 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
5159 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
5160 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
5161 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
5162 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
5163 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
5164 | // .. .. | ||
5165 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
5166 | // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 | ||
5167 | // .. .. ==> 0XF8006078[3:0] = 0x00000001U | ||
5168 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U | ||
5169 | // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 | ||
5170 | // .. .. ==> 0XF8006078[7:4] = 0x00000001U | ||
5171 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U | ||
5172 | // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 | ||
5173 | // .. .. ==> 0XF8006078[11:8] = 0x00000001U | ||
5174 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U | ||
5175 | // .. .. reg_ddrc_t_cksre = 0x6 | ||
5176 | // .. .. ==> 0XF8006078[15:12] = 0x00000006U | ||
5177 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
5178 | // .. .. reg_ddrc_t_cksrx = 0x6 | ||
5179 | // .. .. ==> 0XF8006078[19:16] = 0x00000006U | ||
5180 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
5181 | // .. .. reg_ddrc_t_ckesr = 0x4 | ||
5182 | // .. .. ==> 0XF8006078[25:20] = 0x00000004U | ||
5183 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U | ||
5184 | // .. .. | ||
5185 | EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), | ||
5186 | // .. .. reg_ddrc_t_ckpde = 0x2 | ||
5187 | // .. .. ==> 0XF800607C[3:0] = 0x00000002U | ||
5188 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U | ||
5189 | // .. .. reg_ddrc_t_ckpdx = 0x2 | ||
5190 | // .. .. ==> 0XF800607C[7:4] = 0x00000002U | ||
5191 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
5192 | // .. .. reg_ddrc_t_ckdpde = 0x2 | ||
5193 | // .. .. ==> 0XF800607C[11:8] = 0x00000002U | ||
5194 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
5195 | // .. .. reg_ddrc_t_ckdpdx = 0x2 | ||
5196 | // .. .. ==> 0XF800607C[15:12] = 0x00000002U | ||
5197 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U | ||
5198 | // .. .. reg_ddrc_t_ckcsx = 0x3 | ||
5199 | // .. .. ==> 0XF800607C[19:16] = 0x00000003U | ||
5200 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U | ||
5201 | // .. .. | ||
5202 | EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), | ||
5203 | // .. .. refresh_timer0_start_value_x32 = 0x0 | ||
5204 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | ||
5205 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | ||
5206 | // .. .. refresh_timer1_start_value_x32 = 0x8 | ||
5207 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | ||
5208 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | ||
5209 | // .. .. | ||
5210 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | ||
5211 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
5212 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
5213 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5214 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
5215 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
5216 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
5217 | // .. .. reg_ddrc_t_mod = 0x200 | ||
5218 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
5219 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
5220 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
5221 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
5222 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
5223 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
5224 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
5225 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
5226 | // .. .. | ||
5227 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
5228 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | ||
5229 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | ||
5230 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | ||
5231 | // .. .. dram_rstn_x1024 = 0x69 | ||
5232 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | ||
5233 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | ||
5234 | // .. .. | ||
5235 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | ||
5236 | // .. .. deeppowerdown_en = 0x0 | ||
5237 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
5238 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5239 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
5240 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
5241 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
5242 | // .. .. | ||
5243 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
5244 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
5245 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
5246 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
5247 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
5248 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
5249 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
5250 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
5251 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
5252 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
5253 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
5254 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
5255 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
5256 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
5257 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
5258 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
5259 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
5260 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
5261 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
5262 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
5263 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
5264 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
5265 | // .. .. | ||
5266 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
5267 | // .. .. reg_ddrc_2t_delay = 0x0 | ||
5268 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | ||
5269 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | ||
5270 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
5271 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
5272 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
5273 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | ||
5274 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | ||
5275 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5276 | // .. .. | ||
5277 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | ||
5278 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
5279 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
5280 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
5281 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
5282 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
5283 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
5284 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
5285 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
5286 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
5287 | // .. .. | ||
5288 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
5289 | // .. .. START: RESET ECC ERROR | ||
5290 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
5291 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
5292 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5293 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
5294 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
5295 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
5296 | // .. .. | ||
5297 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
5298 | // .. .. FINISH: RESET ECC ERROR | ||
5299 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
5300 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
5301 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5302 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
5303 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
5304 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5305 | // .. .. | ||
5306 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
5307 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
5308 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
5309 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5310 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
5311 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
5312 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
5313 | // .. .. | ||
5314 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
5315 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
5316 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
5317 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5318 | // .. .. | ||
5319 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
5320 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
5321 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
5322 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
5323 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
5324 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
5325 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
5326 | // .. .. | ||
5327 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
5328 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
5329 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
5330 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
5331 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
5332 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
5333 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
5334 | // .. .. | ||
5335 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
5336 | // .. .. reg_phy_dif_on = 0x0 | ||
5337 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
5338 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
5339 | // .. .. reg_phy_dif_off = 0x0 | ||
5340 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
5341 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
5342 | // .. .. | ||
5343 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
5344 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
5345 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
5346 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5347 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
5348 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
5349 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5350 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
5351 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
5352 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5353 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
5354 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
5355 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5356 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
5357 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | ||
5358 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5359 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
5360 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | ||
5361 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
5362 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
5363 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
5364 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
5365 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
5366 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
5367 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
5368 | // .. .. reg_phy_dq_offset = 0x40 | ||
5369 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
5370 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
5371 | // .. .. | ||
5372 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | ||
5373 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
5374 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
5375 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5376 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
5377 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
5378 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5379 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
5380 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
5381 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5382 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
5383 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
5384 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5385 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
5386 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | ||
5387 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5388 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
5389 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | ||
5390 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
5391 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
5392 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
5393 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
5394 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
5395 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
5396 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
5397 | // .. .. reg_phy_dq_offset = 0x40 | ||
5398 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
5399 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
5400 | // .. .. | ||
5401 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | ||
5402 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
5403 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
5404 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5405 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
5406 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
5407 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5408 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
5409 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
5410 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5411 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
5412 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
5413 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5414 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
5415 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
5416 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5417 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
5418 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
5419 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
5420 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
5421 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
5422 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
5423 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
5424 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
5425 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
5426 | // .. .. reg_phy_dq_offset = 0x40 | ||
5427 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
5428 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
5429 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
5430 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
5431 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5432 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
5433 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
5434 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5435 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
5436 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
5437 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5438 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
5439 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
5440 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5441 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
5442 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
5443 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5444 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
5445 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
5446 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
5447 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
5448 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
5449 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
5450 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
5451 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
5452 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
5453 | // .. .. reg_phy_dq_offset = 0x40 | ||
5454 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
5455 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
5456 | // .. .. | ||
5457 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | ||
5458 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
5459 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
5460 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5461 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
5462 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
5463 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5464 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
5465 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
5466 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5467 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
5468 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
5469 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5470 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
5471 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | ||
5472 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5473 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
5474 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | ||
5475 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
5476 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
5477 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
5478 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
5479 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
5480 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
5481 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
5482 | // .. .. reg_phy_dq_offset = 0x40 | ||
5483 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
5484 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
5485 | // .. .. | ||
5486 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | ||
5487 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
5488 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
5489 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
5490 | // .. .. reg_phy_gatelvl_init_ratio = 0xa1 | ||
5491 | // .. .. ==> 0XF800612C[19:10] = 0x000000A1U | ||
5492 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U | ||
5493 | // .. .. | ||
5494 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), | ||
5495 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
5496 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
5497 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
5498 | // .. .. reg_phy_gatelvl_init_ratio = 0xa0 | ||
5499 | // .. .. ==> 0XF8006130[19:10] = 0x000000A0U | ||
5500 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U | ||
5501 | // .. .. | ||
5502 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), | ||
5503 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
5504 | // .. .. ==> 0XF8006134[9:0] = 0x00000007U | ||
5505 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
5506 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
5507 | // .. .. ==> 0XF8006134[19:10] = 0x000000ADU | ||
5508 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
5509 | // .. .. | ||
5510 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), | ||
5511 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
5512 | // .. .. ==> 0XF8006138[9:0] = 0x00000007U | ||
5513 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
5514 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
5515 | // .. .. ==> 0XF8006138[19:10] = 0x000000ADU | ||
5516 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
5517 | // .. .. | ||
5518 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), | ||
5519 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
5520 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
5521 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
5522 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
5523 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
5524 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5525 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
5526 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
5527 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5528 | // .. .. | ||
5529 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
5530 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
5531 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
5532 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
5533 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
5534 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
5535 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5536 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
5537 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
5538 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5539 | // .. .. | ||
5540 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
5541 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
5542 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
5543 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
5544 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
5545 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
5546 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5547 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
5548 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
5549 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5550 | // .. .. | ||
5551 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
5552 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
5553 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
5554 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
5555 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
5556 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
5557 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5558 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
5559 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
5560 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5561 | // .. .. | ||
5562 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
5563 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
5564 | // .. .. ==> 0XF8006154[9:0] = 0x0000007CU | ||
5565 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
5566 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
5567 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
5568 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5569 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
5570 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
5571 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5572 | // .. .. | ||
5573 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), | ||
5574 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
5575 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
5576 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
5577 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
5578 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
5579 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5580 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
5581 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
5582 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5583 | // .. .. | ||
5584 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
5585 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
5586 | // .. .. ==> 0XF800615C[9:0] = 0x00000087U | ||
5587 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
5588 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
5589 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
5590 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5591 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
5592 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
5593 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5594 | // .. .. | ||
5595 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), | ||
5596 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
5597 | // .. .. ==> 0XF8006160[9:0] = 0x00000087U | ||
5598 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
5599 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
5600 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
5601 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5602 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
5603 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
5604 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5605 | // .. .. | ||
5606 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), | ||
5607 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 | ||
5608 | // .. .. ==> 0XF8006168[10:0] = 0x000000F6U | ||
5609 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U | ||
5610 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
5611 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
5612 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
5613 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
5614 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
5615 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
5616 | // .. .. | ||
5617 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), | ||
5618 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 | ||
5619 | // .. .. ==> 0XF800616C[10:0] = 0x000000F5U | ||
5620 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U | ||
5621 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
5622 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
5623 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
5624 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
5625 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
5626 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
5627 | // .. .. | ||
5628 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), | ||
5629 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
5630 | // .. .. ==> 0XF8006170[10:0] = 0x00000102U | ||
5631 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
5632 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
5633 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
5634 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
5635 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
5636 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
5637 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
5638 | // .. .. | ||
5639 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), | ||
5640 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
5641 | // .. .. ==> 0XF8006174[10:0] = 0x00000102U | ||
5642 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
5643 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
5644 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
5645 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
5646 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
5647 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
5648 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
5649 | // .. .. | ||
5650 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), | ||
5651 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
5652 | // .. .. ==> 0XF800617C[9:0] = 0x000000BCU | ||
5653 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
5654 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
5655 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
5656 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5657 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
5658 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
5659 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5660 | // .. .. | ||
5661 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), | ||
5662 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
5663 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
5664 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
5665 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
5666 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
5667 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5668 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
5669 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
5670 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5671 | // .. .. | ||
5672 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
5673 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
5674 | // .. .. ==> 0XF8006184[9:0] = 0x000000C7U | ||
5675 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
5676 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
5677 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
5678 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5679 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
5680 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
5681 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5682 | // .. .. | ||
5683 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), | ||
5684 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
5685 | // .. .. ==> 0XF8006188[9:0] = 0x000000C7U | ||
5686 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
5687 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
5688 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
5689 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
5690 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
5691 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
5692 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
5693 | // .. .. | ||
5694 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), | ||
5695 | // .. .. reg_phy_loopback = 0x0 | ||
5696 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | ||
5697 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5698 | // .. .. reg_phy_bl2 = 0x0 | ||
5699 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
5700 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5701 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
5702 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
5703 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5704 | // .. .. reg_phy_bist_enable = 0x0 | ||
5705 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
5706 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
5707 | // .. .. reg_phy_bist_force_err = 0x0 | ||
5708 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
5709 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
5710 | // .. .. reg_phy_bist_mode = 0x0 | ||
5711 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
5712 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
5713 | // .. .. reg_phy_invert_clkout = 0x1 | ||
5714 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
5715 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
5716 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | ||
5717 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | ||
5718 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
5719 | // .. .. reg_phy_sel_logic = 0x0 | ||
5720 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
5721 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
5722 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
5723 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
5724 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
5725 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
5726 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
5727 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
5728 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
5729 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
5730 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
5731 | // .. .. reg_phy_use_rank0_delays = 0x1 | ||
5732 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | ||
5733 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
5734 | // .. .. reg_phy_lpddr = 0x0 | ||
5735 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
5736 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
5737 | // .. .. reg_phy_cmd_latency = 0x0 | ||
5738 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
5739 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
5740 | // .. .. reg_phy_int_lpbk = 0x0 | ||
5741 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | ||
5742 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
5743 | // .. .. | ||
5744 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | ||
5745 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
5746 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
5747 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
5748 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
5749 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
5750 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
5751 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
5752 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
5753 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
5754 | // .. .. reg_phy_use_wr_level = 0x1 | ||
5755 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
5756 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
5757 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
5758 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
5759 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
5760 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
5761 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
5762 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
5763 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
5764 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
5765 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5766 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
5767 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
5768 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
5769 | // .. .. | ||
5770 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
5771 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
5772 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
5773 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
5774 | // .. .. | ||
5775 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
5776 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
5777 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
5778 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5779 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
5780 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
5781 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5782 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
5783 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
5784 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5785 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
5786 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
5787 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5788 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
5789 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | ||
5790 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
5791 | // .. .. | ||
5792 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | ||
5793 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
5794 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
5795 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5796 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
5797 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
5798 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5799 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
5800 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
5801 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5802 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
5803 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
5804 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5805 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
5806 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | ||
5807 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
5808 | // .. .. | ||
5809 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | ||
5810 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
5811 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
5812 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5813 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
5814 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
5815 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5816 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
5817 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
5818 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5819 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
5820 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
5821 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5822 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
5823 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | ||
5824 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
5825 | // .. .. | ||
5826 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | ||
5827 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
5828 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
5829 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5830 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
5831 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
5832 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5833 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
5834 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
5835 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5836 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
5837 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
5838 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5839 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
5840 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | ||
5841 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
5842 | // .. .. | ||
5843 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | ||
5844 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
5845 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
5846 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5847 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
5848 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
5849 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5850 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
5851 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
5852 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5853 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
5854 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
5855 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5856 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
5857 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
5858 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
5859 | // .. .. | ||
5860 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
5861 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
5862 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
5863 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5864 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
5865 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
5866 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5867 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
5868 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
5869 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5870 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
5871 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
5872 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5873 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
5874 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
5875 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
5876 | // .. .. | ||
5877 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
5878 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
5879 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
5880 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5881 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
5882 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
5883 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5884 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
5885 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
5886 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5887 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
5888 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
5889 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5890 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
5891 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
5892 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
5893 | // .. .. | ||
5894 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
5895 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
5896 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
5897 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
5898 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
5899 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
5900 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5901 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
5902 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
5903 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
5904 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
5905 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
5906 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
5907 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
5908 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
5909 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
5910 | // .. .. | ||
5911 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
5912 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
5913 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
5914 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
5915 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | ||
5916 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | ||
5917 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5918 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
5919 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
5920 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
5921 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
5922 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
5923 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
5924 | // .. .. | ||
5925 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | ||
5926 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
5927 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
5928 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
5929 | // .. .. | ||
5930 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
5931 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
5932 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
5933 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
5934 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
5935 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
5936 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
5937 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
5938 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
5939 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
5940 | // .. .. | ||
5941 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
5942 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | ||
5943 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | ||
5944 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | ||
5945 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
5946 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
5947 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
5948 | // .. .. | ||
5949 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | ||
5950 | // .. .. START: POLL ON DCI STATUS | ||
5951 | // .. .. DONE = 1 | ||
5952 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
5953 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
5954 | // .. .. | ||
5955 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
5956 | // .. .. FINISH: POLL ON DCI STATUS | ||
5957 | // .. .. START: UNLOCK DDR | ||
5958 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
5959 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
5960 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
5961 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
5962 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
5963 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
5964 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
5965 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
5966 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
5967 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
5968 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
5969 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
5970 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
5971 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
5972 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
5973 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
5974 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
5975 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
5976 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
5977 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
5978 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
5979 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
5980 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
5981 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
5982 | // .. .. | ||
5983 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
5984 | // .. .. FINISH: UNLOCK DDR | ||
5985 | // .. .. START: CHECK DDR STATUS | ||
5986 | // .. .. ddrc_reg_operating_mode = 1 | ||
5987 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
5988 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
5989 | // .. .. | ||
5990 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
5991 | // .. .. FINISH: CHECK DDR STATUS | ||
5992 | // .. FINISH: DDR INITIALIZATION | ||
5993 | // FINISH: top | ||
5994 | // | ||
5995 | EMIT_EXIT(), | ||
5996 | |||
5997 | // | ||
5998 | }; | ||
5999 | |||
6000 | unsigned long ps7_mio_init_data_2_0[] = { | ||
6001 | // START: top | ||
6002 | // .. START: SLCR SETTINGS | ||
6003 | // .. UNLOCK_KEY = 0XDF0D | ||
6004 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
6005 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
6006 | // .. | ||
6007 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
6008 | // .. FINISH: SLCR SETTINGS | ||
6009 | // .. START: OCM REMAPPING | ||
6010 | // .. FINISH: OCM REMAPPING | ||
6011 | // .. START: DDRIOB SETTINGS | ||
6012 | // .. INP_POWER = 0x0 | ||
6013 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
6014 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6015 | // .. INP_TYPE = 0x0 | ||
6016 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
6017 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
6018 | // .. DCI_UPDATE = 0x0 | ||
6019 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
6020 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6021 | // .. TERM_EN = 0x0 | ||
6022 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
6023 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
6024 | // .. DCR_TYPE = 0x0 | ||
6025 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
6026 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
6027 | // .. IBUF_DISABLE_MODE = 0x0 | ||
6028 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
6029 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6030 | // .. TERM_DISABLE_MODE = 0x0 | ||
6031 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
6032 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6033 | // .. OUTPUT_EN = 0x3 | ||
6034 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
6035 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6036 | // .. PULLUP_EN = 0x0 | ||
6037 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
6038 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6039 | // .. | ||
6040 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
6041 | // .. INP_POWER = 0x0 | ||
6042 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
6043 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6044 | // .. INP_TYPE = 0x0 | ||
6045 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
6046 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
6047 | // .. DCI_UPDATE = 0x0 | ||
6048 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
6049 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6050 | // .. TERM_EN = 0x0 | ||
6051 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
6052 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
6053 | // .. DCR_TYPE = 0x0 | ||
6054 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
6055 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
6056 | // .. IBUF_DISABLE_MODE = 0x0 | ||
6057 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
6058 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6059 | // .. TERM_DISABLE_MODE = 0x0 | ||
6060 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
6061 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6062 | // .. OUTPUT_EN = 0x3 | ||
6063 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
6064 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6065 | // .. PULLUP_EN = 0x0 | ||
6066 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
6067 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6068 | // .. | ||
6069 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
6070 | // .. INP_POWER = 0x0 | ||
6071 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
6072 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6073 | // .. INP_TYPE = 0x1 | ||
6074 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
6075 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
6076 | // .. DCI_UPDATE = 0x0 | ||
6077 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
6078 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6079 | // .. TERM_EN = 0x1 | ||
6080 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
6081 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
6082 | // .. DCR_TYPE = 0x3 | ||
6083 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
6084 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
6085 | // .. IBUF_DISABLE_MODE = 0 | ||
6086 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
6087 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6088 | // .. TERM_DISABLE_MODE = 0 | ||
6089 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
6090 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6091 | // .. OUTPUT_EN = 0x3 | ||
6092 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
6093 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6094 | // .. PULLUP_EN = 0x0 | ||
6095 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
6096 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6097 | // .. | ||
6098 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
6099 | // .. INP_POWER = 0x0 | ||
6100 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
6101 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6102 | // .. INP_TYPE = 0x1 | ||
6103 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
6104 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
6105 | // .. DCI_UPDATE = 0x0 | ||
6106 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
6107 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6108 | // .. TERM_EN = 0x1 | ||
6109 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
6110 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
6111 | // .. DCR_TYPE = 0x3 | ||
6112 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
6113 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
6114 | // .. IBUF_DISABLE_MODE = 0 | ||
6115 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
6116 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6117 | // .. TERM_DISABLE_MODE = 0 | ||
6118 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
6119 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6120 | // .. OUTPUT_EN = 0x3 | ||
6121 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
6122 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6123 | // .. PULLUP_EN = 0x0 | ||
6124 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
6125 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6126 | // .. | ||
6127 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
6128 | // .. INP_POWER = 0x0 | ||
6129 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
6130 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6131 | // .. INP_TYPE = 0x2 | ||
6132 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
6133 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
6134 | // .. DCI_UPDATE = 0x0 | ||
6135 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
6136 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6137 | // .. TERM_EN = 0x1 | ||
6138 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
6139 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
6140 | // .. DCR_TYPE = 0x3 | ||
6141 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
6142 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
6143 | // .. IBUF_DISABLE_MODE = 0 | ||
6144 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
6145 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6146 | // .. TERM_DISABLE_MODE = 0 | ||
6147 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
6148 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6149 | // .. OUTPUT_EN = 0x3 | ||
6150 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
6151 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6152 | // .. PULLUP_EN = 0x0 | ||
6153 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
6154 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6155 | // .. | ||
6156 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
6157 | // .. INP_POWER = 0x0 | ||
6158 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
6159 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6160 | // .. INP_TYPE = 0x2 | ||
6161 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
6162 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
6163 | // .. DCI_UPDATE = 0x0 | ||
6164 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
6165 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6166 | // .. TERM_EN = 0x1 | ||
6167 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
6168 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
6169 | // .. DCR_TYPE = 0x3 | ||
6170 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
6171 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
6172 | // .. IBUF_DISABLE_MODE = 0 | ||
6173 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
6174 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6175 | // .. TERM_DISABLE_MODE = 0 | ||
6176 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
6177 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6178 | // .. OUTPUT_EN = 0x3 | ||
6179 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
6180 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6181 | // .. PULLUP_EN = 0x0 | ||
6182 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
6183 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6184 | // .. | ||
6185 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
6186 | // .. INP_POWER = 0x0 | ||
6187 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
6188 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6189 | // .. INP_TYPE = 0x0 | ||
6190 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
6191 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
6192 | // .. DCI_UPDATE = 0x0 | ||
6193 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
6194 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6195 | // .. TERM_EN = 0x0 | ||
6196 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
6197 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
6198 | // .. DCR_TYPE = 0x0 | ||
6199 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
6200 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
6201 | // .. IBUF_DISABLE_MODE = 0x0 | ||
6202 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
6203 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
6204 | // .. TERM_DISABLE_MODE = 0x0 | ||
6205 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
6206 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6207 | // .. OUTPUT_EN = 0x3 | ||
6208 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
6209 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
6210 | // .. PULLUP_EN = 0x0 | ||
6211 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
6212 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
6213 | // .. | ||
6214 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
6215 | // .. DRIVE_P = 0x1c | ||
6216 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
6217 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
6218 | // .. DRIVE_N = 0xc | ||
6219 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
6220 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
6221 | // .. SLEW_P = 0x3 | ||
6222 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
6223 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
6224 | // .. SLEW_N = 0x3 | ||
6225 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
6226 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
6227 | // .. GTL = 0x0 | ||
6228 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
6229 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
6230 | // .. RTERM = 0x0 | ||
6231 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
6232 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
6233 | // .. | ||
6234 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
6235 | // .. DRIVE_P = 0x1c | ||
6236 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
6237 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
6238 | // .. DRIVE_N = 0xc | ||
6239 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
6240 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
6241 | // .. SLEW_P = 0x6 | ||
6242 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
6243 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
6244 | // .. SLEW_N = 0x1f | ||
6245 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
6246 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
6247 | // .. GTL = 0x0 | ||
6248 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
6249 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
6250 | // .. RTERM = 0x0 | ||
6251 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
6252 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
6253 | // .. | ||
6254 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
6255 | // .. DRIVE_P = 0x1c | ||
6256 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
6257 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
6258 | // .. DRIVE_N = 0xc | ||
6259 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
6260 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
6261 | // .. SLEW_P = 0x6 | ||
6262 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
6263 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
6264 | // .. SLEW_N = 0x1f | ||
6265 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
6266 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
6267 | // .. GTL = 0x0 | ||
6268 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
6269 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
6270 | // .. RTERM = 0x0 | ||
6271 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
6272 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
6273 | // .. | ||
6274 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
6275 | // .. DRIVE_P = 0x1c | ||
6276 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
6277 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
6278 | // .. DRIVE_N = 0xc | ||
6279 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
6280 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
6281 | // .. SLEW_P = 0x6 | ||
6282 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
6283 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
6284 | // .. SLEW_N = 0x1f | ||
6285 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
6286 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
6287 | // .. GTL = 0x0 | ||
6288 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
6289 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
6290 | // .. RTERM = 0x0 | ||
6291 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
6292 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
6293 | // .. | ||
6294 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
6295 | // .. VREF_INT_EN = 0x1 | ||
6296 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | ||
6297 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
6298 | // .. VREF_SEL = 0x4 | ||
6299 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | ||
6300 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | ||
6301 | // .. VREF_EXT_EN = 0x0 | ||
6302 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | ||
6303 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
6304 | // .. VREF_PULLUP_EN = 0x0 | ||
6305 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
6306 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
6307 | // .. REFIO_EN = 0x1 | ||
6308 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
6309 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
6310 | // .. REFIO_TEST = 0x0 | ||
6311 | // .. ==> 0XF8000B6C[11:10] = 0x00000000U | ||
6312 | // .. ==> MASK : 0x00000C00U VAL : 0x00000000U | ||
6313 | // .. REFIO_PULLUP_EN = 0x0 | ||
6314 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
6315 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6316 | // .. DRST_B_PULLUP_EN = 0x0 | ||
6317 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
6318 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6319 | // .. CKE_PULLUP_EN = 0x0 | ||
6320 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
6321 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
6322 | // .. | ||
6323 | EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), | ||
6324 | // .. .. START: ASSERT RESET | ||
6325 | // .. .. RESET = 1 | ||
6326 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
6327 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
6328 | // .. .. VRN_OUT = 0x1 | ||
6329 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
6330 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
6331 | // .. .. | ||
6332 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | ||
6333 | // .. .. FINISH: ASSERT RESET | ||
6334 | // .. .. START: DEASSERT RESET | ||
6335 | // .. .. RESET = 0 | ||
6336 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
6337 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6338 | // .. .. VRN_OUT = 0x1 | ||
6339 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
6340 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
6341 | // .. .. | ||
6342 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
6343 | // .. .. FINISH: DEASSERT RESET | ||
6344 | // .. .. RESET = 0x1 | ||
6345 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
6346 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
6347 | // .. .. ENABLE = 0x1 | ||
6348 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
6349 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6350 | // .. .. VRP_TRI = 0x0 | ||
6351 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
6352 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6353 | // .. .. VRN_TRI = 0x0 | ||
6354 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
6355 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
6356 | // .. .. VRP_OUT = 0x0 | ||
6357 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
6358 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
6359 | // .. .. VRN_OUT = 0x1 | ||
6360 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
6361 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
6362 | // .. .. NREF_OPT1 = 0x0 | ||
6363 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
6364 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
6365 | // .. .. NREF_OPT2 = 0x0 | ||
6366 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
6367 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
6368 | // .. .. NREF_OPT4 = 0x1 | ||
6369 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
6370 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
6371 | // .. .. PREF_OPT1 = 0x0 | ||
6372 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | ||
6373 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | ||
6374 | // .. .. PREF_OPT2 = 0x0 | ||
6375 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
6376 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
6377 | // .. .. UPDATE_CONTROL = 0x0 | ||
6378 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
6379 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
6380 | // .. .. INIT_COMPLETE = 0x0 | ||
6381 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
6382 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
6383 | // .. .. TST_CLK = 0x0 | ||
6384 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
6385 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
6386 | // .. .. TST_HLN = 0x0 | ||
6387 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
6388 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
6389 | // .. .. TST_HLP = 0x0 | ||
6390 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
6391 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
6392 | // .. .. TST_RST = 0x0 | ||
6393 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
6394 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
6395 | // .. .. INT_DCI_EN = 0x0 | ||
6396 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
6397 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
6398 | // .. .. | ||
6399 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | ||
6400 | // .. FINISH: DDRIOB SETTINGS | ||
6401 | // .. START: MIO PROGRAMMING | ||
6402 | // .. TRI_ENABLE = 0 | ||
6403 | // .. ==> 0XF8000700[0:0] = 0x00000000U | ||
6404 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6405 | // .. L0_SEL = 0 | ||
6406 | // .. ==> 0XF8000700[1:1] = 0x00000000U | ||
6407 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6408 | // .. L1_SEL = 0 | ||
6409 | // .. ==> 0XF8000700[2:2] = 0x00000000U | ||
6410 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6411 | // .. L2_SEL = 0 | ||
6412 | // .. ==> 0XF8000700[4:3] = 0x00000000U | ||
6413 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6414 | // .. L3_SEL = 0 | ||
6415 | // .. ==> 0XF8000700[7:5] = 0x00000000U | ||
6416 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6417 | // .. Speed = 0 | ||
6418 | // .. ==> 0XF8000700[8:8] = 0x00000000U | ||
6419 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6420 | // .. IO_Type = 3 | ||
6421 | // .. ==> 0XF8000700[11:9] = 0x00000003U | ||
6422 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6423 | // .. PULLUP = 0 | ||
6424 | // .. ==> 0XF8000700[12:12] = 0x00000000U | ||
6425 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6426 | // .. DisableRcvr = 0 | ||
6427 | // .. ==> 0XF8000700[13:13] = 0x00000000U | ||
6428 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6429 | // .. | ||
6430 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | ||
6431 | // .. TRI_ENABLE = 0 | ||
6432 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
6433 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6434 | // .. L0_SEL = 1 | ||
6435 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
6436 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6437 | // .. L1_SEL = 0 | ||
6438 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
6439 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6440 | // .. L2_SEL = 0 | ||
6441 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
6442 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6443 | // .. L3_SEL = 0 | ||
6444 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
6445 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6446 | // .. Speed = 0 | ||
6447 | // .. ==> 0XF8000704[8:8] = 0x00000000U | ||
6448 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6449 | // .. IO_Type = 3 | ||
6450 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
6451 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6452 | // .. PULLUP = 0 | ||
6453 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
6454 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6455 | // .. DisableRcvr = 0 | ||
6456 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
6457 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6458 | // .. | ||
6459 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | ||
6460 | // .. TRI_ENABLE = 0 | ||
6461 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
6462 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6463 | // .. L0_SEL = 1 | ||
6464 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
6465 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6466 | // .. L1_SEL = 0 | ||
6467 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
6468 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6469 | // .. L2_SEL = 0 | ||
6470 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
6471 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6472 | // .. L3_SEL = 0 | ||
6473 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
6474 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6475 | // .. Speed = 0 | ||
6476 | // .. ==> 0XF8000708[8:8] = 0x00000000U | ||
6477 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6478 | // .. IO_Type = 3 | ||
6479 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
6480 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6481 | // .. PULLUP = 0 | ||
6482 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
6483 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6484 | // .. DisableRcvr = 0 | ||
6485 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
6486 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6487 | // .. | ||
6488 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | ||
6489 | // .. TRI_ENABLE = 0 | ||
6490 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
6491 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6492 | // .. L0_SEL = 1 | ||
6493 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
6494 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6495 | // .. L1_SEL = 0 | ||
6496 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
6497 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6498 | // .. L2_SEL = 0 | ||
6499 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
6500 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6501 | // .. L3_SEL = 0 | ||
6502 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
6503 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6504 | // .. Speed = 0 | ||
6505 | // .. ==> 0XF800070C[8:8] = 0x00000000U | ||
6506 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6507 | // .. IO_Type = 3 | ||
6508 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
6509 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6510 | // .. PULLUP = 0 | ||
6511 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
6512 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6513 | // .. DisableRcvr = 0 | ||
6514 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
6515 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6516 | // .. | ||
6517 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | ||
6518 | // .. TRI_ENABLE = 0 | ||
6519 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
6520 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6521 | // .. L0_SEL = 1 | ||
6522 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
6523 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6524 | // .. L1_SEL = 0 | ||
6525 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
6526 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6527 | // .. L2_SEL = 0 | ||
6528 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
6529 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6530 | // .. L3_SEL = 0 | ||
6531 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
6532 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6533 | // .. Speed = 0 | ||
6534 | // .. ==> 0XF8000710[8:8] = 0x00000000U | ||
6535 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6536 | // .. IO_Type = 3 | ||
6537 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
6538 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6539 | // .. PULLUP = 0 | ||
6540 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
6541 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6542 | // .. DisableRcvr = 0 | ||
6543 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
6544 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6545 | // .. | ||
6546 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | ||
6547 | // .. TRI_ENABLE = 0 | ||
6548 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
6549 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6550 | // .. L0_SEL = 1 | ||
6551 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
6552 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6553 | // .. L1_SEL = 0 | ||
6554 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
6555 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6556 | // .. L2_SEL = 0 | ||
6557 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
6558 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6559 | // .. L3_SEL = 0 | ||
6560 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
6561 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6562 | // .. Speed = 0 | ||
6563 | // .. ==> 0XF8000714[8:8] = 0x00000000U | ||
6564 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6565 | // .. IO_Type = 3 | ||
6566 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
6567 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6568 | // .. PULLUP = 0 | ||
6569 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
6570 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6571 | // .. DisableRcvr = 0 | ||
6572 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
6573 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6574 | // .. | ||
6575 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | ||
6576 | // .. TRI_ENABLE = 0 | ||
6577 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
6578 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6579 | // .. L0_SEL = 1 | ||
6580 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
6581 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6582 | // .. L1_SEL = 0 | ||
6583 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
6584 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6585 | // .. L2_SEL = 0 | ||
6586 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
6587 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6588 | // .. L3_SEL = 0 | ||
6589 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
6590 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6591 | // .. Speed = 0 | ||
6592 | // .. ==> 0XF8000718[8:8] = 0x00000000U | ||
6593 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6594 | // .. IO_Type = 3 | ||
6595 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
6596 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6597 | // .. PULLUP = 0 | ||
6598 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
6599 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6600 | // .. DisableRcvr = 0 | ||
6601 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
6602 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6603 | // .. | ||
6604 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | ||
6605 | // .. TRI_ENABLE = 0 | ||
6606 | // .. ==> 0XF800071C[0:0] = 0x00000000U | ||
6607 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6608 | // .. L0_SEL = 0 | ||
6609 | // .. ==> 0XF800071C[1:1] = 0x00000000U | ||
6610 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6611 | // .. L1_SEL = 0 | ||
6612 | // .. ==> 0XF800071C[2:2] = 0x00000000U | ||
6613 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6614 | // .. L2_SEL = 0 | ||
6615 | // .. ==> 0XF800071C[4:3] = 0x00000000U | ||
6616 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6617 | // .. L3_SEL = 0 | ||
6618 | // .. ==> 0XF800071C[7:5] = 0x00000000U | ||
6619 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6620 | // .. Speed = 0 | ||
6621 | // .. ==> 0XF800071C[8:8] = 0x00000000U | ||
6622 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6623 | // .. IO_Type = 3 | ||
6624 | // .. ==> 0XF800071C[11:9] = 0x00000003U | ||
6625 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6626 | // .. PULLUP = 0 | ||
6627 | // .. ==> 0XF800071C[12:12] = 0x00000000U | ||
6628 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6629 | // .. DisableRcvr = 0 | ||
6630 | // .. ==> 0XF800071C[13:13] = 0x00000000U | ||
6631 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6632 | // .. | ||
6633 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | ||
6634 | // .. TRI_ENABLE = 0 | ||
6635 | // .. ==> 0XF8000720[0:0] = 0x00000000U | ||
6636 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6637 | // .. L0_SEL = 1 | ||
6638 | // .. ==> 0XF8000720[1:1] = 0x00000001U | ||
6639 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6640 | // .. L1_SEL = 0 | ||
6641 | // .. ==> 0XF8000720[2:2] = 0x00000000U | ||
6642 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6643 | // .. L2_SEL = 0 | ||
6644 | // .. ==> 0XF8000720[4:3] = 0x00000000U | ||
6645 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6646 | // .. L3_SEL = 0 | ||
6647 | // .. ==> 0XF8000720[7:5] = 0x00000000U | ||
6648 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6649 | // .. Speed = 0 | ||
6650 | // .. ==> 0XF8000720[8:8] = 0x00000000U | ||
6651 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6652 | // .. IO_Type = 3 | ||
6653 | // .. ==> 0XF8000720[11:9] = 0x00000003U | ||
6654 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6655 | // .. PULLUP = 0 | ||
6656 | // .. ==> 0XF8000720[12:12] = 0x00000000U | ||
6657 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6658 | // .. DisableRcvr = 0 | ||
6659 | // .. ==> 0XF8000720[13:13] = 0x00000000U | ||
6660 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6661 | // .. | ||
6662 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | ||
6663 | // .. TRI_ENABLE = 0 | ||
6664 | // .. ==> 0XF8000724[0:0] = 0x00000000U | ||
6665 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6666 | // .. L0_SEL = 0 | ||
6667 | // .. ==> 0XF8000724[1:1] = 0x00000000U | ||
6668 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6669 | // .. L1_SEL = 0 | ||
6670 | // .. ==> 0XF8000724[2:2] = 0x00000000U | ||
6671 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6672 | // .. L2_SEL = 0 | ||
6673 | // .. ==> 0XF8000724[4:3] = 0x00000000U | ||
6674 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6675 | // .. L3_SEL = 0 | ||
6676 | // .. ==> 0XF8000724[7:5] = 0x00000000U | ||
6677 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6678 | // .. Speed = 0 | ||
6679 | // .. ==> 0XF8000724[8:8] = 0x00000000U | ||
6680 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6681 | // .. IO_Type = 3 | ||
6682 | // .. ==> 0XF8000724[11:9] = 0x00000003U | ||
6683 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6684 | // .. PULLUP = 0 | ||
6685 | // .. ==> 0XF8000724[12:12] = 0x00000000U | ||
6686 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6687 | // .. DisableRcvr = 0 | ||
6688 | // .. ==> 0XF8000724[13:13] = 0x00000000U | ||
6689 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6690 | // .. | ||
6691 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | ||
6692 | // .. TRI_ENABLE = 0 | ||
6693 | // .. ==> 0XF8000728[0:0] = 0x00000000U | ||
6694 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6695 | // .. L0_SEL = 0 | ||
6696 | // .. ==> 0XF8000728[1:1] = 0x00000000U | ||
6697 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6698 | // .. L1_SEL = 0 | ||
6699 | // .. ==> 0XF8000728[2:2] = 0x00000000U | ||
6700 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6701 | // .. L2_SEL = 0 | ||
6702 | // .. ==> 0XF8000728[4:3] = 0x00000000U | ||
6703 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6704 | // .. L3_SEL = 4 | ||
6705 | // .. ==> 0XF8000728[7:5] = 0x00000004U | ||
6706 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6707 | // .. Speed = 0 | ||
6708 | // .. ==> 0XF8000728[8:8] = 0x00000000U | ||
6709 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6710 | // .. IO_Type = 3 | ||
6711 | // .. ==> 0XF8000728[11:9] = 0x00000003U | ||
6712 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6713 | // .. PULLUP = 0 | ||
6714 | // .. ==> 0XF8000728[12:12] = 0x00000000U | ||
6715 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6716 | // .. DisableRcvr = 0 | ||
6717 | // .. ==> 0XF8000728[13:13] = 0x00000000U | ||
6718 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6719 | // .. | ||
6720 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), | ||
6721 | // .. TRI_ENABLE = 0 | ||
6722 | // .. ==> 0XF800072C[0:0] = 0x00000000U | ||
6723 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6724 | // .. L0_SEL = 0 | ||
6725 | // .. ==> 0XF800072C[1:1] = 0x00000000U | ||
6726 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6727 | // .. L1_SEL = 0 | ||
6728 | // .. ==> 0XF800072C[2:2] = 0x00000000U | ||
6729 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6730 | // .. L2_SEL = 0 | ||
6731 | // .. ==> 0XF800072C[4:3] = 0x00000000U | ||
6732 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6733 | // .. L3_SEL = 4 | ||
6734 | // .. ==> 0XF800072C[7:5] = 0x00000004U | ||
6735 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6736 | // .. Speed = 0 | ||
6737 | // .. ==> 0XF800072C[8:8] = 0x00000000U | ||
6738 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6739 | // .. IO_Type = 3 | ||
6740 | // .. ==> 0XF800072C[11:9] = 0x00000003U | ||
6741 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6742 | // .. PULLUP = 0 | ||
6743 | // .. ==> 0XF800072C[12:12] = 0x00000000U | ||
6744 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6745 | // .. DisableRcvr = 0 | ||
6746 | // .. ==> 0XF800072C[13:13] = 0x00000000U | ||
6747 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6748 | // .. | ||
6749 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), | ||
6750 | // .. TRI_ENABLE = 0 | ||
6751 | // .. ==> 0XF8000730[0:0] = 0x00000000U | ||
6752 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6753 | // .. L0_SEL = 0 | ||
6754 | // .. ==> 0XF8000730[1:1] = 0x00000000U | ||
6755 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6756 | // .. L1_SEL = 0 | ||
6757 | // .. ==> 0XF8000730[2:2] = 0x00000000U | ||
6758 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6759 | // .. L2_SEL = 0 | ||
6760 | // .. ==> 0XF8000730[4:3] = 0x00000000U | ||
6761 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6762 | // .. L3_SEL = 4 | ||
6763 | // .. ==> 0XF8000730[7:5] = 0x00000004U | ||
6764 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6765 | // .. Speed = 0 | ||
6766 | // .. ==> 0XF8000730[8:8] = 0x00000000U | ||
6767 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6768 | // .. IO_Type = 3 | ||
6769 | // .. ==> 0XF8000730[11:9] = 0x00000003U | ||
6770 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6771 | // .. PULLUP = 0 | ||
6772 | // .. ==> 0XF8000730[12:12] = 0x00000000U | ||
6773 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6774 | // .. DisableRcvr = 0 | ||
6775 | // .. ==> 0XF8000730[13:13] = 0x00000000U | ||
6776 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6777 | // .. | ||
6778 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), | ||
6779 | // .. TRI_ENABLE = 0 | ||
6780 | // .. ==> 0XF8000734[0:0] = 0x00000000U | ||
6781 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6782 | // .. L0_SEL = 0 | ||
6783 | // .. ==> 0XF8000734[1:1] = 0x00000000U | ||
6784 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6785 | // .. L1_SEL = 0 | ||
6786 | // .. ==> 0XF8000734[2:2] = 0x00000000U | ||
6787 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6788 | // .. L2_SEL = 0 | ||
6789 | // .. ==> 0XF8000734[4:3] = 0x00000000U | ||
6790 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6791 | // .. L3_SEL = 4 | ||
6792 | // .. ==> 0XF8000734[7:5] = 0x00000004U | ||
6793 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6794 | // .. Speed = 0 | ||
6795 | // .. ==> 0XF8000734[8:8] = 0x00000000U | ||
6796 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6797 | // .. IO_Type = 3 | ||
6798 | // .. ==> 0XF8000734[11:9] = 0x00000003U | ||
6799 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6800 | // .. PULLUP = 0 | ||
6801 | // .. ==> 0XF8000734[12:12] = 0x00000000U | ||
6802 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6803 | // .. DisableRcvr = 0 | ||
6804 | // .. ==> 0XF8000734[13:13] = 0x00000000U | ||
6805 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6806 | // .. | ||
6807 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), | ||
6808 | // .. TRI_ENABLE = 0 | ||
6809 | // .. ==> 0XF8000738[0:0] = 0x00000000U | ||
6810 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6811 | // .. L0_SEL = 0 | ||
6812 | // .. ==> 0XF8000738[1:1] = 0x00000000U | ||
6813 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6814 | // .. L1_SEL = 0 | ||
6815 | // .. ==> 0XF8000738[2:2] = 0x00000000U | ||
6816 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6817 | // .. L2_SEL = 0 | ||
6818 | // .. ==> 0XF8000738[4:3] = 0x00000000U | ||
6819 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6820 | // .. L3_SEL = 4 | ||
6821 | // .. ==> 0XF8000738[7:5] = 0x00000004U | ||
6822 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6823 | // .. Speed = 0 | ||
6824 | // .. ==> 0XF8000738[8:8] = 0x00000000U | ||
6825 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6826 | // .. IO_Type = 3 | ||
6827 | // .. ==> 0XF8000738[11:9] = 0x00000003U | ||
6828 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6829 | // .. PULLUP = 0 | ||
6830 | // .. ==> 0XF8000738[12:12] = 0x00000000U | ||
6831 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6832 | // .. DisableRcvr = 0 | ||
6833 | // .. ==> 0XF8000738[13:13] = 0x00000000U | ||
6834 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6835 | // .. | ||
6836 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), | ||
6837 | // .. TRI_ENABLE = 0 | ||
6838 | // .. ==> 0XF800073C[0:0] = 0x00000000U | ||
6839 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6840 | // .. L0_SEL = 0 | ||
6841 | // .. ==> 0XF800073C[1:1] = 0x00000000U | ||
6842 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
6843 | // .. L1_SEL = 0 | ||
6844 | // .. ==> 0XF800073C[2:2] = 0x00000000U | ||
6845 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6846 | // .. L2_SEL = 0 | ||
6847 | // .. ==> 0XF800073C[4:3] = 0x00000000U | ||
6848 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6849 | // .. L3_SEL = 4 | ||
6850 | // .. ==> 0XF800073C[7:5] = 0x00000004U | ||
6851 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
6852 | // .. Speed = 0 | ||
6853 | // .. ==> 0XF800073C[8:8] = 0x00000000U | ||
6854 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6855 | // .. IO_Type = 3 | ||
6856 | // .. ==> 0XF800073C[11:9] = 0x00000003U | ||
6857 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
6858 | // .. PULLUP = 0 | ||
6859 | // .. ==> 0XF800073C[12:12] = 0x00000000U | ||
6860 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6861 | // .. DisableRcvr = 0 | ||
6862 | // .. ==> 0XF800073C[13:13] = 0x00000000U | ||
6863 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6864 | // .. | ||
6865 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), | ||
6866 | // .. TRI_ENABLE = 0 | ||
6867 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
6868 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6869 | // .. L0_SEL = 1 | ||
6870 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
6871 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6872 | // .. L1_SEL = 0 | ||
6873 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
6874 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6875 | // .. L2_SEL = 0 | ||
6876 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
6877 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6878 | // .. L3_SEL = 0 | ||
6879 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
6880 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6881 | // .. Speed = 0 | ||
6882 | // .. ==> 0XF8000740[8:8] = 0x00000000U | ||
6883 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6884 | // .. IO_Type = 1 | ||
6885 | // .. ==> 0XF8000740[11:9] = 0x00000001U | ||
6886 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
6887 | // .. PULLUP = 0 | ||
6888 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
6889 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6890 | // .. DisableRcvr = 0 | ||
6891 | // .. ==> 0XF8000740[13:13] = 0x00000000U | ||
6892 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6893 | // .. | ||
6894 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | ||
6895 | // .. TRI_ENABLE = 0 | ||
6896 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
6897 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6898 | // .. L0_SEL = 1 | ||
6899 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
6900 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6901 | // .. L1_SEL = 0 | ||
6902 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
6903 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6904 | // .. L2_SEL = 0 | ||
6905 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
6906 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6907 | // .. L3_SEL = 0 | ||
6908 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
6909 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6910 | // .. Speed = 0 | ||
6911 | // .. ==> 0XF8000744[8:8] = 0x00000000U | ||
6912 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6913 | // .. IO_Type = 1 | ||
6914 | // .. ==> 0XF8000744[11:9] = 0x00000001U | ||
6915 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
6916 | // .. PULLUP = 0 | ||
6917 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
6918 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6919 | // .. DisableRcvr = 0 | ||
6920 | // .. ==> 0XF8000744[13:13] = 0x00000000U | ||
6921 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6922 | // .. | ||
6923 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | ||
6924 | // .. TRI_ENABLE = 0 | ||
6925 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
6926 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6927 | // .. L0_SEL = 1 | ||
6928 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
6929 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6930 | // .. L1_SEL = 0 | ||
6931 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
6932 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6933 | // .. L2_SEL = 0 | ||
6934 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
6935 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6936 | // .. L3_SEL = 0 | ||
6937 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
6938 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6939 | // .. Speed = 0 | ||
6940 | // .. ==> 0XF8000748[8:8] = 0x00000000U | ||
6941 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6942 | // .. IO_Type = 1 | ||
6943 | // .. ==> 0XF8000748[11:9] = 0x00000001U | ||
6944 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
6945 | // .. PULLUP = 0 | ||
6946 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
6947 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6948 | // .. DisableRcvr = 0 | ||
6949 | // .. ==> 0XF8000748[13:13] = 0x00000000U | ||
6950 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6951 | // .. | ||
6952 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | ||
6953 | // .. TRI_ENABLE = 0 | ||
6954 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
6955 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6956 | // .. L0_SEL = 1 | ||
6957 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
6958 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6959 | // .. L1_SEL = 0 | ||
6960 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
6961 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6962 | // .. L2_SEL = 0 | ||
6963 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
6964 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6965 | // .. L3_SEL = 0 | ||
6966 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
6967 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6968 | // .. Speed = 0 | ||
6969 | // .. ==> 0XF800074C[8:8] = 0x00000000U | ||
6970 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
6971 | // .. IO_Type = 1 | ||
6972 | // .. ==> 0XF800074C[11:9] = 0x00000001U | ||
6973 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
6974 | // .. PULLUP = 0 | ||
6975 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
6976 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
6977 | // .. DisableRcvr = 0 | ||
6978 | // .. ==> 0XF800074C[13:13] = 0x00000000U | ||
6979 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
6980 | // .. | ||
6981 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | ||
6982 | // .. TRI_ENABLE = 0 | ||
6983 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
6984 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
6985 | // .. L0_SEL = 1 | ||
6986 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
6987 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
6988 | // .. L1_SEL = 0 | ||
6989 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
6990 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
6991 | // .. L2_SEL = 0 | ||
6992 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
6993 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
6994 | // .. L3_SEL = 0 | ||
6995 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
6996 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
6997 | // .. Speed = 0 | ||
6998 | // .. ==> 0XF8000750[8:8] = 0x00000000U | ||
6999 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7000 | // .. IO_Type = 1 | ||
7001 | // .. ==> 0XF8000750[11:9] = 0x00000001U | ||
7002 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7003 | // .. PULLUP = 0 | ||
7004 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
7005 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7006 | // .. DisableRcvr = 0 | ||
7007 | // .. ==> 0XF8000750[13:13] = 0x00000000U | ||
7008 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7009 | // .. | ||
7010 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | ||
7011 | // .. TRI_ENABLE = 0 | ||
7012 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
7013 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7014 | // .. L0_SEL = 1 | ||
7015 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
7016 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7017 | // .. L1_SEL = 0 | ||
7018 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
7019 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7020 | // .. L2_SEL = 0 | ||
7021 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
7022 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7023 | // .. L3_SEL = 0 | ||
7024 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
7025 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7026 | // .. Speed = 0 | ||
7027 | // .. ==> 0XF8000754[8:8] = 0x00000000U | ||
7028 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7029 | // .. IO_Type = 1 | ||
7030 | // .. ==> 0XF8000754[11:9] = 0x00000001U | ||
7031 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7032 | // .. PULLUP = 0 | ||
7033 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
7034 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7035 | // .. DisableRcvr = 0 | ||
7036 | // .. ==> 0XF8000754[13:13] = 0x00000000U | ||
7037 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7038 | // .. | ||
7039 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | ||
7040 | // .. TRI_ENABLE = 1 | ||
7041 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
7042 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7043 | // .. L0_SEL = 1 | ||
7044 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
7045 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7046 | // .. L1_SEL = 0 | ||
7047 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
7048 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7049 | // .. L2_SEL = 0 | ||
7050 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
7051 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7052 | // .. L3_SEL = 0 | ||
7053 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
7054 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7055 | // .. Speed = 0 | ||
7056 | // .. ==> 0XF8000758[8:8] = 0x00000000U | ||
7057 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7058 | // .. IO_Type = 1 | ||
7059 | // .. ==> 0XF8000758[11:9] = 0x00000001U | ||
7060 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7061 | // .. PULLUP = 0 | ||
7062 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
7063 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7064 | // .. DisableRcvr = 0 | ||
7065 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
7066 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7067 | // .. | ||
7068 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | ||
7069 | // .. TRI_ENABLE = 1 | ||
7070 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
7071 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7072 | // .. L0_SEL = 1 | ||
7073 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
7074 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7075 | // .. L1_SEL = 0 | ||
7076 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
7077 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7078 | // .. L2_SEL = 0 | ||
7079 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
7080 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7081 | // .. L3_SEL = 0 | ||
7082 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
7083 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7084 | // .. Speed = 0 | ||
7085 | // .. ==> 0XF800075C[8:8] = 0x00000000U | ||
7086 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7087 | // .. IO_Type = 1 | ||
7088 | // .. ==> 0XF800075C[11:9] = 0x00000001U | ||
7089 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7090 | // .. PULLUP = 0 | ||
7091 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
7092 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7093 | // .. DisableRcvr = 0 | ||
7094 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
7095 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7096 | // .. | ||
7097 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | ||
7098 | // .. TRI_ENABLE = 1 | ||
7099 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
7100 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7101 | // .. L0_SEL = 1 | ||
7102 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
7103 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7104 | // .. L1_SEL = 0 | ||
7105 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
7106 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7107 | // .. L2_SEL = 0 | ||
7108 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
7109 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7110 | // .. L3_SEL = 0 | ||
7111 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
7112 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7113 | // .. Speed = 0 | ||
7114 | // .. ==> 0XF8000760[8:8] = 0x00000000U | ||
7115 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7116 | // .. IO_Type = 1 | ||
7117 | // .. ==> 0XF8000760[11:9] = 0x00000001U | ||
7118 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7119 | // .. PULLUP = 0 | ||
7120 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
7121 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7122 | // .. DisableRcvr = 0 | ||
7123 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
7124 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7125 | // .. | ||
7126 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | ||
7127 | // .. TRI_ENABLE = 1 | ||
7128 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
7129 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7130 | // .. L0_SEL = 1 | ||
7131 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
7132 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7133 | // .. L1_SEL = 0 | ||
7134 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
7135 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7136 | // .. L2_SEL = 0 | ||
7137 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
7138 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7139 | // .. L3_SEL = 0 | ||
7140 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
7141 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7142 | // .. Speed = 0 | ||
7143 | // .. ==> 0XF8000764[8:8] = 0x00000000U | ||
7144 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7145 | // .. IO_Type = 1 | ||
7146 | // .. ==> 0XF8000764[11:9] = 0x00000001U | ||
7147 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7148 | // .. PULLUP = 0 | ||
7149 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
7150 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7151 | // .. DisableRcvr = 0 | ||
7152 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
7153 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7154 | // .. | ||
7155 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | ||
7156 | // .. TRI_ENABLE = 1 | ||
7157 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
7158 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7159 | // .. L0_SEL = 1 | ||
7160 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
7161 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7162 | // .. L1_SEL = 0 | ||
7163 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
7164 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7165 | // .. L2_SEL = 0 | ||
7166 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
7167 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7168 | // .. L3_SEL = 0 | ||
7169 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
7170 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7171 | // .. Speed = 0 | ||
7172 | // .. ==> 0XF8000768[8:8] = 0x00000000U | ||
7173 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7174 | // .. IO_Type = 1 | ||
7175 | // .. ==> 0XF8000768[11:9] = 0x00000001U | ||
7176 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7177 | // .. PULLUP = 0 | ||
7178 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
7179 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7180 | // .. DisableRcvr = 0 | ||
7181 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
7182 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7183 | // .. | ||
7184 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | ||
7185 | // .. TRI_ENABLE = 1 | ||
7186 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
7187 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7188 | // .. L0_SEL = 1 | ||
7189 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
7190 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
7191 | // .. L1_SEL = 0 | ||
7192 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
7193 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7194 | // .. L2_SEL = 0 | ||
7195 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
7196 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7197 | // .. L3_SEL = 0 | ||
7198 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
7199 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7200 | // .. Speed = 0 | ||
7201 | // .. ==> 0XF800076C[8:8] = 0x00000000U | ||
7202 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7203 | // .. IO_Type = 1 | ||
7204 | // .. ==> 0XF800076C[11:9] = 0x00000001U | ||
7205 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7206 | // .. PULLUP = 0 | ||
7207 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
7208 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7209 | // .. DisableRcvr = 0 | ||
7210 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
7211 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7212 | // .. | ||
7213 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | ||
7214 | // .. TRI_ENABLE = 0 | ||
7215 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
7216 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7217 | // .. L0_SEL = 0 | ||
7218 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
7219 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7220 | // .. L1_SEL = 1 | ||
7221 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
7222 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7223 | // .. L2_SEL = 0 | ||
7224 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
7225 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7226 | // .. L3_SEL = 0 | ||
7227 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
7228 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7229 | // .. Speed = 0 | ||
7230 | // .. ==> 0XF8000770[8:8] = 0x00000000U | ||
7231 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7232 | // .. IO_Type = 1 | ||
7233 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
7234 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7235 | // .. PULLUP = 0 | ||
7236 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
7237 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7238 | // .. DisableRcvr = 0 | ||
7239 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
7240 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7241 | // .. | ||
7242 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | ||
7243 | // .. TRI_ENABLE = 1 | ||
7244 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
7245 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7246 | // .. L0_SEL = 0 | ||
7247 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
7248 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7249 | // .. L1_SEL = 1 | ||
7250 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
7251 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7252 | // .. L2_SEL = 0 | ||
7253 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
7254 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7255 | // .. L3_SEL = 0 | ||
7256 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
7257 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7258 | // .. Speed = 0 | ||
7259 | // .. ==> 0XF8000774[8:8] = 0x00000000U | ||
7260 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7261 | // .. IO_Type = 1 | ||
7262 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
7263 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7264 | // .. PULLUP = 0 | ||
7265 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
7266 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7267 | // .. DisableRcvr = 0 | ||
7268 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
7269 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7270 | // .. | ||
7271 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | ||
7272 | // .. TRI_ENABLE = 0 | ||
7273 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
7274 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7275 | // .. L0_SEL = 0 | ||
7276 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
7277 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7278 | // .. L1_SEL = 1 | ||
7279 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
7280 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7281 | // .. L2_SEL = 0 | ||
7282 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
7283 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7284 | // .. L3_SEL = 0 | ||
7285 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
7286 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7287 | // .. Speed = 0 | ||
7288 | // .. ==> 0XF8000778[8:8] = 0x00000000U | ||
7289 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7290 | // .. IO_Type = 1 | ||
7291 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
7292 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7293 | // .. PULLUP = 0 | ||
7294 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
7295 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7296 | // .. DisableRcvr = 0 | ||
7297 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
7298 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7299 | // .. | ||
7300 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | ||
7301 | // .. TRI_ENABLE = 1 | ||
7302 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
7303 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7304 | // .. L0_SEL = 0 | ||
7305 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
7306 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7307 | // .. L1_SEL = 1 | ||
7308 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
7309 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7310 | // .. L2_SEL = 0 | ||
7311 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
7312 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7313 | // .. L3_SEL = 0 | ||
7314 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
7315 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7316 | // .. Speed = 0 | ||
7317 | // .. ==> 0XF800077C[8:8] = 0x00000000U | ||
7318 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7319 | // .. IO_Type = 1 | ||
7320 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
7321 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7322 | // .. PULLUP = 0 | ||
7323 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
7324 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7325 | // .. DisableRcvr = 0 | ||
7326 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
7327 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7328 | // .. | ||
7329 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | ||
7330 | // .. TRI_ENABLE = 0 | ||
7331 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
7332 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7333 | // .. L0_SEL = 0 | ||
7334 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
7335 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7336 | // .. L1_SEL = 1 | ||
7337 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
7338 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7339 | // .. L2_SEL = 0 | ||
7340 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
7341 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7342 | // .. L3_SEL = 0 | ||
7343 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
7344 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7345 | // .. Speed = 0 | ||
7346 | // .. ==> 0XF8000780[8:8] = 0x00000000U | ||
7347 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7348 | // .. IO_Type = 1 | ||
7349 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
7350 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7351 | // .. PULLUP = 0 | ||
7352 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
7353 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7354 | // .. DisableRcvr = 0 | ||
7355 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
7356 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7357 | // .. | ||
7358 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | ||
7359 | // .. TRI_ENABLE = 0 | ||
7360 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
7361 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7362 | // .. L0_SEL = 0 | ||
7363 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
7364 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7365 | // .. L1_SEL = 1 | ||
7366 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
7367 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7368 | // .. L2_SEL = 0 | ||
7369 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
7370 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7371 | // .. L3_SEL = 0 | ||
7372 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
7373 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7374 | // .. Speed = 0 | ||
7375 | // .. ==> 0XF8000784[8:8] = 0x00000000U | ||
7376 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7377 | // .. IO_Type = 1 | ||
7378 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
7379 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7380 | // .. PULLUP = 0 | ||
7381 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
7382 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7383 | // .. DisableRcvr = 0 | ||
7384 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
7385 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7386 | // .. | ||
7387 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | ||
7388 | // .. TRI_ENABLE = 0 | ||
7389 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
7390 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7391 | // .. L0_SEL = 0 | ||
7392 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
7393 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7394 | // .. L1_SEL = 1 | ||
7395 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
7396 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7397 | // .. L2_SEL = 0 | ||
7398 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
7399 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7400 | // .. L3_SEL = 0 | ||
7401 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
7402 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7403 | // .. Speed = 0 | ||
7404 | // .. ==> 0XF8000788[8:8] = 0x00000000U | ||
7405 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7406 | // .. IO_Type = 1 | ||
7407 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
7408 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7409 | // .. PULLUP = 0 | ||
7410 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
7411 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7412 | // .. DisableRcvr = 0 | ||
7413 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
7414 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7415 | // .. | ||
7416 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | ||
7417 | // .. TRI_ENABLE = 0 | ||
7418 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
7419 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7420 | // .. L0_SEL = 0 | ||
7421 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
7422 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7423 | // .. L1_SEL = 1 | ||
7424 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
7425 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7426 | // .. L2_SEL = 0 | ||
7427 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
7428 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7429 | // .. L3_SEL = 0 | ||
7430 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
7431 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7432 | // .. Speed = 0 | ||
7433 | // .. ==> 0XF800078C[8:8] = 0x00000000U | ||
7434 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7435 | // .. IO_Type = 1 | ||
7436 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
7437 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7438 | // .. PULLUP = 0 | ||
7439 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
7440 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7441 | // .. DisableRcvr = 0 | ||
7442 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
7443 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7444 | // .. | ||
7445 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | ||
7446 | // .. TRI_ENABLE = 1 | ||
7447 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
7448 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7449 | // .. L0_SEL = 0 | ||
7450 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
7451 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7452 | // .. L1_SEL = 1 | ||
7453 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
7454 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7455 | // .. L2_SEL = 0 | ||
7456 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
7457 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7458 | // .. L3_SEL = 0 | ||
7459 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
7460 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7461 | // .. Speed = 0 | ||
7462 | // .. ==> 0XF8000790[8:8] = 0x00000000U | ||
7463 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7464 | // .. IO_Type = 1 | ||
7465 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
7466 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7467 | // .. PULLUP = 0 | ||
7468 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
7469 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7470 | // .. DisableRcvr = 0 | ||
7471 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
7472 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7473 | // .. | ||
7474 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | ||
7475 | // .. TRI_ENABLE = 0 | ||
7476 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
7477 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7478 | // .. L0_SEL = 0 | ||
7479 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
7480 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7481 | // .. L1_SEL = 1 | ||
7482 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
7483 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7484 | // .. L2_SEL = 0 | ||
7485 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
7486 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7487 | // .. L3_SEL = 0 | ||
7488 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
7489 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7490 | // .. Speed = 0 | ||
7491 | // .. ==> 0XF8000794[8:8] = 0x00000000U | ||
7492 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7493 | // .. IO_Type = 1 | ||
7494 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
7495 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7496 | // .. PULLUP = 0 | ||
7497 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
7498 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7499 | // .. DisableRcvr = 0 | ||
7500 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
7501 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7502 | // .. | ||
7503 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | ||
7504 | // .. TRI_ENABLE = 0 | ||
7505 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
7506 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7507 | // .. L0_SEL = 0 | ||
7508 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
7509 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7510 | // .. L1_SEL = 1 | ||
7511 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
7512 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7513 | // .. L2_SEL = 0 | ||
7514 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
7515 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7516 | // .. L3_SEL = 0 | ||
7517 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
7518 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7519 | // .. Speed = 0 | ||
7520 | // .. ==> 0XF8000798[8:8] = 0x00000000U | ||
7521 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7522 | // .. IO_Type = 1 | ||
7523 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
7524 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7525 | // .. PULLUP = 0 | ||
7526 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
7527 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7528 | // .. DisableRcvr = 0 | ||
7529 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
7530 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7531 | // .. | ||
7532 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | ||
7533 | // .. TRI_ENABLE = 0 | ||
7534 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
7535 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7536 | // .. L0_SEL = 0 | ||
7537 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
7538 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7539 | // .. L1_SEL = 1 | ||
7540 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
7541 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
7542 | // .. L2_SEL = 0 | ||
7543 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
7544 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7545 | // .. L3_SEL = 0 | ||
7546 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
7547 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7548 | // .. Speed = 0 | ||
7549 | // .. ==> 0XF800079C[8:8] = 0x00000000U | ||
7550 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7551 | // .. IO_Type = 1 | ||
7552 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
7553 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7554 | // .. PULLUP = 0 | ||
7555 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
7556 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7557 | // .. DisableRcvr = 0 | ||
7558 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
7559 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7560 | // .. | ||
7561 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | ||
7562 | // .. TRI_ENABLE = 0 | ||
7563 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
7564 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7565 | // .. L0_SEL = 0 | ||
7566 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
7567 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7568 | // .. L1_SEL = 0 | ||
7569 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
7570 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7571 | // .. L2_SEL = 0 | ||
7572 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
7573 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7574 | // .. L3_SEL = 0 | ||
7575 | // .. ==> 0XF80007A0[7:5] = 0x00000000U | ||
7576 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7577 | // .. Speed = 0 | ||
7578 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | ||
7579 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7580 | // .. IO_Type = 1 | ||
7581 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
7582 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7583 | // .. PULLUP = 0 | ||
7584 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
7585 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7586 | // .. DisableRcvr = 0 | ||
7587 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
7588 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7589 | // .. | ||
7590 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), | ||
7591 | // .. TRI_ENABLE = 0 | ||
7592 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
7593 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7594 | // .. L0_SEL = 0 | ||
7595 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
7596 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7597 | // .. L1_SEL = 0 | ||
7598 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
7599 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7600 | // .. L2_SEL = 0 | ||
7601 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
7602 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7603 | // .. L3_SEL = 0 | ||
7604 | // .. ==> 0XF80007A4[7:5] = 0x00000000U | ||
7605 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7606 | // .. Speed = 0 | ||
7607 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | ||
7608 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7609 | // .. IO_Type = 1 | ||
7610 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
7611 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7612 | // .. PULLUP = 0 | ||
7613 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
7614 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7615 | // .. DisableRcvr = 0 | ||
7616 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
7617 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7618 | // .. | ||
7619 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), | ||
7620 | // .. TRI_ENABLE = 0 | ||
7621 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
7622 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7623 | // .. L0_SEL = 0 | ||
7624 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
7625 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7626 | // .. L1_SEL = 0 | ||
7627 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
7628 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7629 | // .. L2_SEL = 0 | ||
7630 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
7631 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7632 | // .. L3_SEL = 0 | ||
7633 | // .. ==> 0XF80007A8[7:5] = 0x00000000U | ||
7634 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7635 | // .. Speed = 0 | ||
7636 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | ||
7637 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7638 | // .. IO_Type = 1 | ||
7639 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
7640 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7641 | // .. PULLUP = 0 | ||
7642 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
7643 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7644 | // .. DisableRcvr = 0 | ||
7645 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
7646 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7647 | // .. | ||
7648 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), | ||
7649 | // .. TRI_ENABLE = 0 | ||
7650 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
7651 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7652 | // .. L0_SEL = 0 | ||
7653 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
7654 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7655 | // .. L1_SEL = 0 | ||
7656 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
7657 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7658 | // .. L2_SEL = 0 | ||
7659 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
7660 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7661 | // .. L3_SEL = 0 | ||
7662 | // .. ==> 0XF80007AC[7:5] = 0x00000000U | ||
7663 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7664 | // .. Speed = 0 | ||
7665 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | ||
7666 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7667 | // .. IO_Type = 1 | ||
7668 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
7669 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7670 | // .. PULLUP = 0 | ||
7671 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
7672 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7673 | // .. DisableRcvr = 0 | ||
7674 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
7675 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7676 | // .. | ||
7677 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), | ||
7678 | // .. TRI_ENABLE = 0 | ||
7679 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
7680 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7681 | // .. L0_SEL = 0 | ||
7682 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
7683 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7684 | // .. L1_SEL = 0 | ||
7685 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
7686 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7687 | // .. L2_SEL = 0 | ||
7688 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
7689 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7690 | // .. L3_SEL = 0 | ||
7691 | // .. ==> 0XF80007B0[7:5] = 0x00000000U | ||
7692 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7693 | // .. Speed = 0 | ||
7694 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | ||
7695 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7696 | // .. IO_Type = 1 | ||
7697 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
7698 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7699 | // .. PULLUP = 0 | ||
7700 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
7701 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7702 | // .. DisableRcvr = 0 | ||
7703 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
7704 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7705 | // .. | ||
7706 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), | ||
7707 | // .. TRI_ENABLE = 0 | ||
7708 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
7709 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7710 | // .. L0_SEL = 0 | ||
7711 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
7712 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7713 | // .. L1_SEL = 0 | ||
7714 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
7715 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7716 | // .. L2_SEL = 0 | ||
7717 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
7718 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7719 | // .. L3_SEL = 0 | ||
7720 | // .. ==> 0XF80007B4[7:5] = 0x00000000U | ||
7721 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7722 | // .. Speed = 0 | ||
7723 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | ||
7724 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7725 | // .. IO_Type = 1 | ||
7726 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
7727 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7728 | // .. PULLUP = 0 | ||
7729 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
7730 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7731 | // .. DisableRcvr = 0 | ||
7732 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
7733 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7734 | // .. | ||
7735 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), | ||
7736 | // .. TRI_ENABLE = 0 | ||
7737 | // .. ==> 0XF80007B8[0:0] = 0x00000000U | ||
7738 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7739 | // .. L0_SEL = 0 | ||
7740 | // .. ==> 0XF80007B8[1:1] = 0x00000000U | ||
7741 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7742 | // .. L1_SEL = 0 | ||
7743 | // .. ==> 0XF80007B8[2:2] = 0x00000000U | ||
7744 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7745 | // .. L2_SEL = 0 | ||
7746 | // .. ==> 0XF80007B8[4:3] = 0x00000000U | ||
7747 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7748 | // .. L3_SEL = 0 | ||
7749 | // .. ==> 0XF80007B8[7:5] = 0x00000000U | ||
7750 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7751 | // .. Speed = 0 | ||
7752 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | ||
7753 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7754 | // .. IO_Type = 1 | ||
7755 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | ||
7756 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7757 | // .. PULLUP = 0 | ||
7758 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | ||
7759 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7760 | // .. DisableRcvr = 0 | ||
7761 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | ||
7762 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7763 | // .. | ||
7764 | EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), | ||
7765 | // .. TRI_ENABLE = 0 | ||
7766 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | ||
7767 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7768 | // .. L0_SEL = 0 | ||
7769 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | ||
7770 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7771 | // .. L1_SEL = 0 | ||
7772 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | ||
7773 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7774 | // .. L2_SEL = 0 | ||
7775 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | ||
7776 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7777 | // .. L3_SEL = 0 | ||
7778 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | ||
7779 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7780 | // .. Speed = 0 | ||
7781 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
7782 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7783 | // .. IO_Type = 1 | ||
7784 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
7785 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7786 | // .. PULLUP = 0 | ||
7787 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
7788 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7789 | // .. DisableRcvr = 0 | ||
7790 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
7791 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7792 | // .. | ||
7793 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | ||
7794 | // .. TRI_ENABLE = 0 | ||
7795 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
7796 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7797 | // .. L0_SEL = 0 | ||
7798 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
7799 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7800 | // .. L1_SEL = 0 | ||
7801 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
7802 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7803 | // .. L2_SEL = 0 | ||
7804 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
7805 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7806 | // .. L3_SEL = 7 | ||
7807 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
7808 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
7809 | // .. Speed = 0 | ||
7810 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
7811 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7812 | // .. IO_Type = 1 | ||
7813 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
7814 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7815 | // .. PULLUP = 0 | ||
7816 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
7817 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7818 | // .. DisableRcvr = 0 | ||
7819 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
7820 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7821 | // .. | ||
7822 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
7823 | // .. TRI_ENABLE = 1 | ||
7824 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
7825 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
7826 | // .. L0_SEL = 0 | ||
7827 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
7828 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7829 | // .. L1_SEL = 0 | ||
7830 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
7831 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7832 | // .. L2_SEL = 0 | ||
7833 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
7834 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7835 | // .. L3_SEL = 7 | ||
7836 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
7837 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
7838 | // .. Speed = 0 | ||
7839 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
7840 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7841 | // .. IO_Type = 1 | ||
7842 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
7843 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7844 | // .. PULLUP = 0 | ||
7845 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
7846 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7847 | // .. DisableRcvr = 0 | ||
7848 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
7849 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7850 | // .. | ||
7851 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
7852 | // .. TRI_ENABLE = 0 | ||
7853 | // .. ==> 0XF80007C8[0:0] = 0x00000000U | ||
7854 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7855 | // .. L0_SEL = 0 | ||
7856 | // .. ==> 0XF80007C8[1:1] = 0x00000000U | ||
7857 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7858 | // .. L1_SEL = 0 | ||
7859 | // .. ==> 0XF80007C8[2:2] = 0x00000000U | ||
7860 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7861 | // .. L2_SEL = 0 | ||
7862 | // .. ==> 0XF80007C8[4:3] = 0x00000000U | ||
7863 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7864 | // .. L3_SEL = 0 | ||
7865 | // .. ==> 0XF80007C8[7:5] = 0x00000000U | ||
7866 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7867 | // .. Speed = 0 | ||
7868 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | ||
7869 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7870 | // .. IO_Type = 1 | ||
7871 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | ||
7872 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7873 | // .. PULLUP = 0 | ||
7874 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | ||
7875 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7876 | // .. DisableRcvr = 0 | ||
7877 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | ||
7878 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7879 | // .. | ||
7880 | EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), | ||
7881 | // .. TRI_ENABLE = 0 | ||
7882 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | ||
7883 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7884 | // .. L0_SEL = 0 | ||
7885 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | ||
7886 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7887 | // .. L1_SEL = 0 | ||
7888 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | ||
7889 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7890 | // .. L2_SEL = 0 | ||
7891 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | ||
7892 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7893 | // .. L3_SEL = 0 | ||
7894 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | ||
7895 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
7896 | // .. Speed = 0 | ||
7897 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | ||
7898 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7899 | // .. IO_Type = 1 | ||
7900 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | ||
7901 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7902 | // .. PULLUP = 0 | ||
7903 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | ||
7904 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7905 | // .. DisableRcvr = 0 | ||
7906 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | ||
7907 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7908 | // .. | ||
7909 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | ||
7910 | // .. TRI_ENABLE = 0 | ||
7911 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
7912 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7913 | // .. L0_SEL = 0 | ||
7914 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
7915 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7916 | // .. L1_SEL = 0 | ||
7917 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
7918 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7919 | // .. L2_SEL = 0 | ||
7920 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
7921 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7922 | // .. L3_SEL = 4 | ||
7923 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
7924 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
7925 | // .. Speed = 0 | ||
7926 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
7927 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7928 | // .. IO_Type = 1 | ||
7929 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
7930 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7931 | // .. PULLUP = 0 | ||
7932 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
7933 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7934 | // .. DisableRcvr = 0 | ||
7935 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
7936 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7937 | // .. | ||
7938 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
7939 | // .. TRI_ENABLE = 0 | ||
7940 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
7941 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
7942 | // .. L0_SEL = 0 | ||
7943 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
7944 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
7945 | // .. L1_SEL = 0 | ||
7946 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
7947 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
7948 | // .. L2_SEL = 0 | ||
7949 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
7950 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
7951 | // .. L3_SEL = 4 | ||
7952 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
7953 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
7954 | // .. Speed = 0 | ||
7955 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
7956 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
7957 | // .. IO_Type = 1 | ||
7958 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
7959 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
7960 | // .. PULLUP = 0 | ||
7961 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
7962 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
7963 | // .. DisableRcvr = 0 | ||
7964 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
7965 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
7966 | // .. | ||
7967 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
7968 | // .. SDIO1_CD_SEL = 58 | ||
7969 | // .. ==> 0XF8000834[21:16] = 0x0000003AU | ||
7970 | // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U | ||
7971 | // .. | ||
7972 | EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), | ||
7973 | // .. FINISH: MIO PROGRAMMING | ||
7974 | // .. START: LOCK IT BACK | ||
7975 | // .. LOCK_KEY = 0X767B | ||
7976 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
7977 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
7978 | // .. | ||
7979 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
7980 | // .. FINISH: LOCK IT BACK | ||
7981 | // FINISH: top | ||
7982 | // | ||
7983 | EMIT_EXIT(), | ||
7984 | |||
7985 | // | ||
7986 | }; | ||
7987 | |||
7988 | unsigned long ps7_peripherals_init_data_2_0[] = { | ||
7989 | // START: top | ||
7990 | // .. START: SLCR SETTINGS | ||
7991 | // .. UNLOCK_KEY = 0XDF0D | ||
7992 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
7993 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
7994 | // .. | ||
7995 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
7996 | // .. FINISH: SLCR SETTINGS | ||
7997 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
7998 | // .. IBUF_DISABLE_MODE = 0x1 | ||
7999 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
8000 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
8001 | // .. TERM_DISABLE_MODE = 0x1 | ||
8002 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
8003 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
8004 | // .. | ||
8005 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
8006 | // .. IBUF_DISABLE_MODE = 0x1 | ||
8007 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
8008 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
8009 | // .. TERM_DISABLE_MODE = 0x1 | ||
8010 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
8011 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
8012 | // .. | ||
8013 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
8014 | // .. IBUF_DISABLE_MODE = 0x1 | ||
8015 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
8016 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
8017 | // .. TERM_DISABLE_MODE = 0x1 | ||
8018 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
8019 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
8020 | // .. | ||
8021 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
8022 | // .. IBUF_DISABLE_MODE = 0x1 | ||
8023 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
8024 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
8025 | // .. TERM_DISABLE_MODE = 0x1 | ||
8026 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
8027 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
8028 | // .. | ||
8029 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
8030 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
8031 | // .. START: LOCK IT BACK | ||
8032 | // .. LOCK_KEY = 0X767B | ||
8033 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
8034 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
8035 | // .. | ||
8036 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
8037 | // .. FINISH: LOCK IT BACK | ||
8038 | // .. START: SRAM/NOR SET OPMODE | ||
8039 | // .. FINISH: SRAM/NOR SET OPMODE | ||
8040 | // .. START: UART REGISTERS | ||
8041 | // .. BDIV = 0x6 | ||
8042 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
8043 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
8044 | // .. | ||
8045 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
8046 | // .. CD = 0x3e | ||
8047 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
8048 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
8049 | // .. | ||
8050 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
8051 | // .. STPBRK = 0x0 | ||
8052 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
8053 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
8054 | // .. STTBRK = 0x0 | ||
8055 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
8056 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
8057 | // .. RSTTO = 0x0 | ||
8058 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
8059 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
8060 | // .. TXDIS = 0x0 | ||
8061 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
8062 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
8063 | // .. TXEN = 0x1 | ||
8064 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
8065 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
8066 | // .. RXDIS = 0x0 | ||
8067 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
8068 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
8069 | // .. RXEN = 0x1 | ||
8070 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
8071 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
8072 | // .. TXRES = 0x1 | ||
8073 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
8074 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
8075 | // .. RXRES = 0x1 | ||
8076 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
8077 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8078 | // .. | ||
8079 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
8080 | // .. IRMODE = 0x0 | ||
8081 | // .. ==> 0XE0001004[11:11] = 0x00000000U | ||
8082 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
8083 | // .. UCLKEN = 0x0 | ||
8084 | // .. ==> 0XE0001004[10:10] = 0x00000000U | ||
8085 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
8086 | // .. CHMODE = 0x0 | ||
8087 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
8088 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
8089 | // .. NBSTOP = 0x0 | ||
8090 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
8091 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
8092 | // .. PAR = 0x4 | ||
8093 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
8094 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
8095 | // .. CHRL = 0x0 | ||
8096 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
8097 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
8098 | // .. CLKS = 0x0 | ||
8099 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
8100 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8101 | // .. | ||
8102 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | ||
8103 | // .. FINISH: UART REGISTERS | ||
8104 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
8105 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
8106 | // .. .. a = 0XC5ACCE55 | ||
8107 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
8108 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
8109 | // .. .. | ||
8110 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
8111 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
8112 | // .. .. START: TRACE CURRENT PORT SIZE | ||
8113 | // .. .. a = 2 | ||
8114 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
8115 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
8116 | // .. .. | ||
8117 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
8118 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
8119 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
8120 | // .. .. a = 0X0 | ||
8121 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
8122 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
8123 | // .. .. | ||
8124 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
8125 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
8126 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
8127 | // .. START: QSPI REGISTERS | ||
8128 | // .. Holdb_dr = 1 | ||
8129 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
8130 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
8131 | // .. | ||
8132 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
8133 | // .. FINISH: QSPI REGISTERS | ||
8134 | // .. START: PL POWER ON RESET REGISTERS | ||
8135 | // .. PCFG_POR_CNT_4K = 0 | ||
8136 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
8137 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
8138 | // .. | ||
8139 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
8140 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
8141 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
8142 | // .. .. START: NAND SET CYCLE | ||
8143 | // .. .. FINISH: NAND SET CYCLE | ||
8144 | // .. .. START: OPMODE | ||
8145 | // .. .. FINISH: OPMODE | ||
8146 | // .. .. START: DIRECT COMMAND | ||
8147 | // .. .. FINISH: DIRECT COMMAND | ||
8148 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
8149 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
8150 | // .. .. START: DIRECT COMMAND | ||
8151 | // .. .. FINISH: DIRECT COMMAND | ||
8152 | // .. .. START: NOR CS0 BASE ADDRESS | ||
8153 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
8154 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
8155 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
8156 | // .. .. START: DIRECT COMMAND | ||
8157 | // .. .. FINISH: DIRECT COMMAND | ||
8158 | // .. .. START: NOR CS1 BASE ADDRESS | ||
8159 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
8160 | // .. .. START: USB RESET | ||
8161 | // .. .. .. START: USB0 RESET | ||
8162 | // .. .. .. .. START: DIR MODE BANK 0 | ||
8163 | // .. .. .. .. DIRECTION_0 = 0x80 | ||
8164 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | ||
8165 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
8166 | // .. .. .. .. | ||
8167 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | ||
8168 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
8169 | // .. .. .. .. START: DIR MODE BANK 1 | ||
8170 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
8171 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8172 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
8173 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
8174 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
8175 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
8176 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
8177 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
8178 | // .. .. .. .. | ||
8179 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
8180 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8181 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8182 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8183 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8184 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8185 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8186 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8187 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
8188 | // .. .. .. .. OP_ENABLE_0 = 0x80 | ||
8189 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | ||
8190 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
8191 | // .. .. .. .. | ||
8192 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | ||
8193 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
8194 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
8195 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
8196 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8197 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
8198 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
8199 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
8200 | // .. .. .. .. DATA_0_LSW = 0x0 | ||
8201 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | ||
8202 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | ||
8203 | // .. .. .. .. | ||
8204 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | ||
8205 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8206 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8207 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8208 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8209 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8210 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8211 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8212 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8213 | // .. .. .. .. | ||
8214 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8215 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8216 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8217 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
8218 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
8219 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
8220 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
8221 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
8222 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
8223 | // .. .. .. .. | ||
8224 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
8225 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8226 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8227 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8228 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8229 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8230 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8231 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8232 | // .. .. .. FINISH: USB0 RESET | ||
8233 | // .. .. .. START: USB1 RESET | ||
8234 | // .. .. .. .. START: DIR MODE BANK 0 | ||
8235 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
8236 | // .. .. .. .. START: DIR MODE BANK 1 | ||
8237 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
8238 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8239 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8240 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8241 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8242 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8243 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8244 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8245 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8246 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
8247 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
8248 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
8249 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
8250 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8251 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8252 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8253 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8254 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8255 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8256 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8257 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8258 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8259 | // .. .. .. .. | ||
8260 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8261 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8262 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8263 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8264 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8265 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8266 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8267 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8268 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8269 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8270 | // .. .. .. FINISH: USB1 RESET | ||
8271 | // .. .. FINISH: USB RESET | ||
8272 | // .. .. START: ENET RESET | ||
8273 | // .. .. .. START: ENET0 RESET | ||
8274 | // .. .. .. .. START: DIR MODE BANK 0 | ||
8275 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
8276 | // .. .. .. .. START: DIR MODE BANK 1 | ||
8277 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
8278 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8279 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8280 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8281 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8282 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8283 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8284 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8285 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8286 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
8287 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
8288 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
8289 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
8290 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8291 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8292 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8293 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8294 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8295 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8296 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8297 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8298 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8299 | // .. .. .. .. | ||
8300 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8301 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8302 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8303 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8304 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8305 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8306 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8307 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8308 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8309 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8310 | // .. .. .. FINISH: ENET0 RESET | ||
8311 | // .. .. .. START: ENET1 RESET | ||
8312 | // .. .. .. .. START: DIR MODE BANK 0 | ||
8313 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
8314 | // .. .. .. .. START: DIR MODE BANK 1 | ||
8315 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
8316 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8317 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8318 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8319 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8320 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8321 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8322 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8323 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8324 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
8325 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
8326 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
8327 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
8328 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8329 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8330 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8331 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8332 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8333 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8334 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8335 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8336 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8337 | // .. .. .. .. | ||
8338 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8339 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8340 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8341 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8342 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8343 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8344 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8345 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8346 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8347 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8348 | // .. .. .. FINISH: ENET1 RESET | ||
8349 | // .. .. FINISH: ENET RESET | ||
8350 | // .. .. START: I2C RESET | ||
8351 | // .. .. .. START: I2C0 RESET | ||
8352 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
8353 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
8354 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
8355 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
8356 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8357 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8358 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8359 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8360 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8361 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8362 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8363 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8364 | // .. .. .. .. START: OUTPUT ENABLE | ||
8365 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
8366 | // .. .. .. .. START: OUTPUT ENABLE | ||
8367 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
8368 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8369 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8370 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8371 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8372 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8373 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8374 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8375 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8376 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8377 | // .. .. .. .. | ||
8378 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8379 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8380 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8381 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8382 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8383 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8384 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8385 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8386 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8387 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8388 | // .. .. .. FINISH: I2C0 RESET | ||
8389 | // .. .. .. START: I2C1 RESET | ||
8390 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
8391 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
8392 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
8393 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
8394 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8395 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8396 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8397 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8398 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8399 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8400 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8401 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8402 | // .. .. .. .. START: OUTPUT ENABLE | ||
8403 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
8404 | // .. .. .. .. START: OUTPUT ENABLE | ||
8405 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
8406 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8407 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
8408 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8409 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
8410 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8411 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
8412 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8413 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
8414 | // .. .. .. .. START: ADD 1 MS DELAY | ||
8415 | // .. .. .. .. | ||
8416 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
8417 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
8418 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8419 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8420 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8421 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
8422 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8423 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
8424 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8425 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
8426 | // .. .. .. FINISH: I2C1 RESET | ||
8427 | // .. .. FINISH: I2C RESET | ||
8428 | // .. .. START: NOR CHIP SELECT | ||
8429 | // .. .. .. START: DIR MODE BANK 0 | ||
8430 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
8431 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8432 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
8433 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
8434 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
8435 | // .. .. FINISH: NOR CHIP SELECT | ||
8436 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
8437 | // FINISH: top | ||
8438 | // | ||
8439 | EMIT_EXIT(), | ||
8440 | |||
8441 | // | ||
8442 | }; | ||
8443 | |||
8444 | unsigned long ps7_post_config_2_0[] = { | ||
8445 | // START: top | ||
8446 | // .. START: SLCR SETTINGS | ||
8447 | // .. UNLOCK_KEY = 0XDF0D | ||
8448 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
8449 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
8450 | // .. | ||
8451 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
8452 | // .. FINISH: SLCR SETTINGS | ||
8453 | // .. START: ENABLING LEVEL SHIFTER | ||
8454 | // .. USER_INP_ICT_EN_0 = 3 | ||
8455 | // .. ==> 0XF8000900[1:0] = 0x00000003U | ||
8456 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | ||
8457 | // .. USER_INP_ICT_EN_1 = 3 | ||
8458 | // .. ==> 0XF8000900[3:2] = 0x00000003U | ||
8459 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | ||
8460 | // .. | ||
8461 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
8462 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
8463 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
8464 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
8465 | // .. .. a = 0XC5ACCE55 | ||
8466 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
8467 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
8468 | // .. .. | ||
8469 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
8470 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
8471 | // .. .. START: TRACE CURRENT PORT SIZE | ||
8472 | // .. .. a = 2 | ||
8473 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
8474 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
8475 | // .. .. | ||
8476 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
8477 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
8478 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
8479 | // .. .. a = 0X0 | ||
8480 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
8481 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
8482 | // .. .. | ||
8483 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
8484 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
8485 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
8486 | // .. START: FPGA RESETS TO 0 | ||
8487 | // .. reserved_3 = 0 | ||
8488 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
8489 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
8490 | // .. FPGA_ACP_RST = 0 | ||
8491 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
8492 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
8493 | // .. FPGA_AXDS3_RST = 0 | ||
8494 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
8495 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
8496 | // .. FPGA_AXDS2_RST = 0 | ||
8497 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
8498 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
8499 | // .. FPGA_AXDS1_RST = 0 | ||
8500 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
8501 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
8502 | // .. FPGA_AXDS0_RST = 0 | ||
8503 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
8504 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
8505 | // .. reserved_2 = 0 | ||
8506 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
8507 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
8508 | // .. FSSW1_FPGA_RST = 0 | ||
8509 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
8510 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
8511 | // .. FSSW0_FPGA_RST = 0 | ||
8512 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
8513 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
8514 | // .. reserved_1 = 0 | ||
8515 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
8516 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
8517 | // .. FPGA_FMSW1_RST = 0 | ||
8518 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
8519 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
8520 | // .. FPGA_FMSW0_RST = 0 | ||
8521 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
8522 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
8523 | // .. FPGA_DMA3_RST = 0 | ||
8524 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
8525 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
8526 | // .. FPGA_DMA2_RST = 0 | ||
8527 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
8528 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
8529 | // .. FPGA_DMA1_RST = 0 | ||
8530 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
8531 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
8532 | // .. FPGA_DMA0_RST = 0 | ||
8533 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
8534 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
8535 | // .. reserved = 0 | ||
8536 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
8537 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
8538 | // .. FPGA3_OUT_RST = 0 | ||
8539 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
8540 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
8541 | // .. FPGA2_OUT_RST = 0 | ||
8542 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
8543 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
8544 | // .. FPGA1_OUT_RST = 0 | ||
8545 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
8546 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
8547 | // .. FPGA0_OUT_RST = 0 | ||
8548 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
8549 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8550 | // .. | ||
8551 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
8552 | // .. FINISH: FPGA RESETS TO 0 | ||
8553 | // .. START: AFI REGISTERS | ||
8554 | // .. .. START: AFI0 REGISTERS | ||
8555 | // .. .. FINISH: AFI0 REGISTERS | ||
8556 | // .. .. START: AFI1 REGISTERS | ||
8557 | // .. .. FINISH: AFI1 REGISTERS | ||
8558 | // .. .. START: AFI2 REGISTERS | ||
8559 | // .. .. FINISH: AFI2 REGISTERS | ||
8560 | // .. .. START: AFI3 REGISTERS | ||
8561 | // .. .. FINISH: AFI3 REGISTERS | ||
8562 | // .. FINISH: AFI REGISTERS | ||
8563 | // .. START: LOCK IT BACK | ||
8564 | // .. LOCK_KEY = 0X767B | ||
8565 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
8566 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
8567 | // .. | ||
8568 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
8569 | // .. FINISH: LOCK IT BACK | ||
8570 | // FINISH: top | ||
8571 | // | ||
8572 | EMIT_EXIT(), | ||
8573 | |||
8574 | // | ||
8575 | }; | ||
8576 | |||
8577 | unsigned long ps7_debug_2_0[] = { | ||
8578 | // START: top | ||
8579 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
8580 | // .. .. START: UNLOCKING CTI REGISTERS | ||
8581 | // .. .. KEY = 0XC5ACCE55 | ||
8582 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
8583 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
8584 | // .. .. | ||
8585 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
8586 | // .. .. KEY = 0XC5ACCE55 | ||
8587 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
8588 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
8589 | // .. .. | ||
8590 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
8591 | // .. .. KEY = 0XC5ACCE55 | ||
8592 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
8593 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
8594 | // .. .. | ||
8595 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
8596 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
8597 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
8598 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
8599 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
8600 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
8601 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
8602 | // FINISH: top | ||
8603 | // | ||
8604 | EMIT_EXIT(), | ||
8605 | |||
8606 | // | ||
8607 | }; | ||
8608 | |||
8609 | unsigned long ps7_pll_init_data_1_0[] = { | ||
8610 | // START: top | ||
8611 | // .. START: SLCR SETTINGS | ||
8612 | // .. UNLOCK_KEY = 0XDF0D | ||
8613 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
8614 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
8615 | // .. | ||
8616 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
8617 | // .. FINISH: SLCR SETTINGS | ||
8618 | // .. START: PLL SLCR REGISTERS | ||
8619 | // .. .. START: ARM PLL INIT | ||
8620 | // .. .. PLL_RES = 0x4 | ||
8621 | // .. .. ==> 0XF8000110[7:4] = 0x00000004U | ||
8622 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
8623 | // .. .. PLL_CP = 0x2 | ||
8624 | // .. .. ==> 0XF8000110[11:8] = 0x00000002U | ||
8625 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
8626 | // .. .. LOCK_CNT = 0xfa | ||
8627 | // .. .. ==> 0XF8000110[21:12] = 0x000000FAU | ||
8628 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
8629 | // .. .. | ||
8630 | EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U), | ||
8631 | // .. .. .. START: UPDATE FB_DIV | ||
8632 | // .. .. .. PLL_FDIV = 0x3c | ||
8633 | // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU | ||
8634 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
8635 | // .. .. .. | ||
8636 | EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U), | ||
8637 | // .. .. .. FINISH: UPDATE FB_DIV | ||
8638 | // .. .. .. START: BY PASS PLL | ||
8639 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
8640 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U | ||
8641 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
8642 | // .. .. .. | ||
8643 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), | ||
8644 | // .. .. .. FINISH: BY PASS PLL | ||
8645 | // .. .. .. START: ASSERT RESET | ||
8646 | // .. .. .. PLL_RESET = 1 | ||
8647 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U | ||
8648 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8649 | // .. .. .. | ||
8650 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), | ||
8651 | // .. .. .. FINISH: ASSERT RESET | ||
8652 | // .. .. .. START: DEASSERT RESET | ||
8653 | // .. .. .. PLL_RESET = 0 | ||
8654 | // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U | ||
8655 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8656 | // .. .. .. | ||
8657 | EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), | ||
8658 | // .. .. .. FINISH: DEASSERT RESET | ||
8659 | // .. .. .. START: CHECK PLL STATUS | ||
8660 | // .. .. .. ARM_PLL_LOCK = 1 | ||
8661 | // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U | ||
8662 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8663 | // .. .. .. | ||
8664 | EMIT_MASKPOLL(0XF800010C, 0x00000001U), | ||
8665 | // .. .. .. FINISH: CHECK PLL STATUS | ||
8666 | // .. .. .. START: REMOVE PLL BY PASS | ||
8667 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
8668 | // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U | ||
8669 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
8670 | // .. .. .. | ||
8671 | EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), | ||
8672 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
8673 | // .. .. .. SRCSEL = 0x0 | ||
8674 | // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U | ||
8675 | // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8676 | // .. .. .. DIVISOR = 0x3 | ||
8677 | // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U | ||
8678 | // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000300U | ||
8679 | // .. .. .. CPU_6OR4XCLKACT = 0x1 | ||
8680 | // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U | ||
8681 | // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
8682 | // .. .. .. CPU_3OR2XCLKACT = 0x1 | ||
8683 | // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U | ||
8684 | // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U | ||
8685 | // .. .. .. CPU_2XCLKACT = 0x1 | ||
8686 | // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U | ||
8687 | // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
8688 | // .. .. .. CPU_1XCLKACT = 0x1 | ||
8689 | // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U | ||
8690 | // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
8691 | // .. .. .. CPU_PERI_CLKACT = 0x1 | ||
8692 | // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U | ||
8693 | // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
8694 | // .. .. .. | ||
8695 | EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U), | ||
8696 | // .. .. FINISH: ARM PLL INIT | ||
8697 | // .. .. START: DDR PLL INIT | ||
8698 | // .. .. PLL_RES = 0x2 | ||
8699 | // .. .. ==> 0XF8000114[7:4] = 0x00000002U | ||
8700 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U | ||
8701 | // .. .. PLL_CP = 0x2 | ||
8702 | // .. .. ==> 0XF8000114[11:8] = 0x00000002U | ||
8703 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
8704 | // .. .. LOCK_CNT = 0x12c | ||
8705 | // .. .. ==> 0XF8000114[21:12] = 0x0000012CU | ||
8706 | // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U | ||
8707 | // .. .. | ||
8708 | EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), | ||
8709 | // .. .. .. START: UPDATE FB_DIV | ||
8710 | // .. .. .. PLL_FDIV = 0x20 | ||
8711 | // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U | ||
8712 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U | ||
8713 | // .. .. .. | ||
8714 | EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), | ||
8715 | // .. .. .. FINISH: UPDATE FB_DIV | ||
8716 | // .. .. .. START: BY PASS PLL | ||
8717 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
8718 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U | ||
8719 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
8720 | // .. .. .. | ||
8721 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), | ||
8722 | // .. .. .. FINISH: BY PASS PLL | ||
8723 | // .. .. .. START: ASSERT RESET | ||
8724 | // .. .. .. PLL_RESET = 1 | ||
8725 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U | ||
8726 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8727 | // .. .. .. | ||
8728 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), | ||
8729 | // .. .. .. FINISH: ASSERT RESET | ||
8730 | // .. .. .. START: DEASSERT RESET | ||
8731 | // .. .. .. PLL_RESET = 0 | ||
8732 | // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U | ||
8733 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8734 | // .. .. .. | ||
8735 | EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), | ||
8736 | // .. .. .. FINISH: DEASSERT RESET | ||
8737 | // .. .. .. START: CHECK PLL STATUS | ||
8738 | // .. .. .. DDR_PLL_LOCK = 1 | ||
8739 | // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U | ||
8740 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
8741 | // .. .. .. | ||
8742 | EMIT_MASKPOLL(0XF800010C, 0x00000002U), | ||
8743 | // .. .. .. FINISH: CHECK PLL STATUS | ||
8744 | // .. .. .. START: REMOVE PLL BY PASS | ||
8745 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
8746 | // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U | ||
8747 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
8748 | // .. .. .. | ||
8749 | EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), | ||
8750 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
8751 | // .. .. .. DDR_3XCLKACT = 0x1 | ||
8752 | // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U | ||
8753 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8754 | // .. .. .. DDR_2XCLKACT = 0x1 | ||
8755 | // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U | ||
8756 | // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
8757 | // .. .. .. DDR_3XCLK_DIVISOR = 0x2 | ||
8758 | // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U | ||
8759 | // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U | ||
8760 | // .. .. .. DDR_2XCLK_DIVISOR = 0x3 | ||
8761 | // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U | ||
8762 | // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U | ||
8763 | // .. .. .. | ||
8764 | EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), | ||
8765 | // .. .. FINISH: DDR PLL INIT | ||
8766 | // .. .. START: IO PLL INIT | ||
8767 | // .. .. PLL_RES = 0x4 | ||
8768 | // .. .. ==> 0XF8000118[7:4] = 0x00000004U | ||
8769 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U | ||
8770 | // .. .. PLL_CP = 0x2 | ||
8771 | // .. .. ==> 0XF8000118[11:8] = 0x00000002U | ||
8772 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
8773 | // .. .. LOCK_CNT = 0xfa | ||
8774 | // .. .. ==> 0XF8000118[21:12] = 0x000000FAU | ||
8775 | // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U | ||
8776 | // .. .. | ||
8777 | EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), | ||
8778 | // .. .. .. START: UPDATE FB_DIV | ||
8779 | // .. .. .. PLL_FDIV = 0x3c | ||
8780 | // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU | ||
8781 | // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0003C000U | ||
8782 | // .. .. .. | ||
8783 | EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U), | ||
8784 | // .. .. .. FINISH: UPDATE FB_DIV | ||
8785 | // .. .. .. START: BY PASS PLL | ||
8786 | // .. .. .. PLL_BYPASS_FORCE = 1 | ||
8787 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U | ||
8788 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
8789 | // .. .. .. | ||
8790 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), | ||
8791 | // .. .. .. FINISH: BY PASS PLL | ||
8792 | // .. .. .. START: ASSERT RESET | ||
8793 | // .. .. .. PLL_RESET = 1 | ||
8794 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U | ||
8795 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8796 | // .. .. .. | ||
8797 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), | ||
8798 | // .. .. .. FINISH: ASSERT RESET | ||
8799 | // .. .. .. START: DEASSERT RESET | ||
8800 | // .. .. .. PLL_RESET = 0 | ||
8801 | // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U | ||
8802 | // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8803 | // .. .. .. | ||
8804 | EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), | ||
8805 | // .. .. .. FINISH: DEASSERT RESET | ||
8806 | // .. .. .. START: CHECK PLL STATUS | ||
8807 | // .. .. .. IO_PLL_LOCK = 1 | ||
8808 | // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U | ||
8809 | // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
8810 | // .. .. .. | ||
8811 | EMIT_MASKPOLL(0XF800010C, 0x00000004U), | ||
8812 | // .. .. .. FINISH: CHECK PLL STATUS | ||
8813 | // .. .. .. START: REMOVE PLL BY PASS | ||
8814 | // .. .. .. PLL_BYPASS_FORCE = 0 | ||
8815 | // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U | ||
8816 | // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
8817 | // .. .. .. | ||
8818 | EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), | ||
8819 | // .. .. .. FINISH: REMOVE PLL BY PASS | ||
8820 | // .. .. FINISH: IO PLL INIT | ||
8821 | // .. FINISH: PLL SLCR REGISTERS | ||
8822 | // .. START: LOCK IT BACK | ||
8823 | // .. LOCK_KEY = 0X767B | ||
8824 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
8825 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
8826 | // .. | ||
8827 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
8828 | // .. FINISH: LOCK IT BACK | ||
8829 | // FINISH: top | ||
8830 | // | ||
8831 | EMIT_EXIT(), | ||
8832 | |||
8833 | // | ||
8834 | }; | ||
8835 | |||
8836 | unsigned long ps7_clock_init_data_1_0[] = { | ||
8837 | // START: top | ||
8838 | // .. START: SLCR SETTINGS | ||
8839 | // .. UNLOCK_KEY = 0XDF0D | ||
8840 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
8841 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
8842 | // .. | ||
8843 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
8844 | // .. FINISH: SLCR SETTINGS | ||
8845 | // .. START: CLOCK CONTROL SLCR REGISTERS | ||
8846 | // .. CLKACT = 0x1 | ||
8847 | // .. ==> 0XF8000128[0:0] = 0x00000001U | ||
8848 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8849 | // .. DIVISOR0 = 0x23 | ||
8850 | // .. ==> 0XF8000128[13:8] = 0x00000023U | ||
8851 | // .. ==> MASK : 0x00003F00U VAL : 0x00002300U | ||
8852 | // .. DIVISOR1 = 0x3 | ||
8853 | // .. ==> 0XF8000128[25:20] = 0x00000003U | ||
8854 | // .. ==> MASK : 0x03F00000U VAL : 0x00300000U | ||
8855 | // .. | ||
8856 | EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), | ||
8857 | // .. CLKACT = 0x1 | ||
8858 | // .. ==> 0XF8000138[0:0] = 0x00000001U | ||
8859 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8860 | // .. SRCSEL = 0x0 | ||
8861 | // .. ==> 0XF8000138[4:4] = 0x00000000U | ||
8862 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
8863 | // .. | ||
8864 | EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), | ||
8865 | // .. CLKACT = 0x1 | ||
8866 | // .. ==> 0XF8000140[0:0] = 0x00000001U | ||
8867 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8868 | // .. SRCSEL = 0x0 | ||
8869 | // .. ==> 0XF8000140[6:4] = 0x00000000U | ||
8870 | // .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
8871 | // .. DIVISOR = 0x10 | ||
8872 | // .. ==> 0XF8000140[13:8] = 0x00000010U | ||
8873 | // .. ==> MASK : 0x00003F00U VAL : 0x00001000U | ||
8874 | // .. DIVISOR1 = 0x1 | ||
8875 | // .. ==> 0XF8000140[25:20] = 0x00000001U | ||
8876 | // .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
8877 | // .. | ||
8878 | EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U), | ||
8879 | // .. CLKACT = 0x1 | ||
8880 | // .. ==> 0XF800014C[0:0] = 0x00000001U | ||
8881 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8882 | // .. SRCSEL = 0x0 | ||
8883 | // .. ==> 0XF800014C[5:4] = 0x00000000U | ||
8884 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8885 | // .. DIVISOR = 0xa | ||
8886 | // .. ==> 0XF800014C[13:8] = 0x0000000AU | ||
8887 | // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
8888 | // .. | ||
8889 | EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U), | ||
8890 | // .. CLKACT0 = 0x0 | ||
8891 | // .. ==> 0XF8000150[0:0] = 0x00000000U | ||
8892 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8893 | // .. CLKACT1 = 0x1 | ||
8894 | // .. ==> 0XF8000150[1:1] = 0x00000001U | ||
8895 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
8896 | // .. SRCSEL = 0x0 | ||
8897 | // .. ==> 0XF8000150[5:4] = 0x00000000U | ||
8898 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8899 | // .. DIVISOR = 0x28 | ||
8900 | // .. ==> 0XF8000150[13:8] = 0x00000028U | ||
8901 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
8902 | // .. | ||
8903 | EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U), | ||
8904 | // .. CLKACT0 = 0x0 | ||
8905 | // .. ==> 0XF8000154[0:0] = 0x00000000U | ||
8906 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
8907 | // .. CLKACT1 = 0x1 | ||
8908 | // .. ==> 0XF8000154[1:1] = 0x00000001U | ||
8909 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
8910 | // .. SRCSEL = 0x0 | ||
8911 | // .. ==> 0XF8000154[5:4] = 0x00000000U | ||
8912 | // .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8913 | // .. DIVISOR = 0x28 | ||
8914 | // .. ==> 0XF8000154[13:8] = 0x00000028U | ||
8915 | // .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
8916 | // .. | ||
8917 | EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U), | ||
8918 | // .. .. START: TRACE CLOCK | ||
8919 | // .. .. FINISH: TRACE CLOCK | ||
8920 | // .. .. CLKACT = 0x1 | ||
8921 | // .. .. ==> 0XF8000168[0:0] = 0x00000001U | ||
8922 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8923 | // .. .. SRCSEL = 0x0 | ||
8924 | // .. .. ==> 0XF8000168[5:4] = 0x00000000U | ||
8925 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8926 | // .. .. DIVISOR = 0xa | ||
8927 | // .. .. ==> 0XF8000168[13:8] = 0x0000000AU | ||
8928 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U | ||
8929 | // .. .. | ||
8930 | EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U), | ||
8931 | // .. .. SRCSEL = 0x0 | ||
8932 | // .. .. ==> 0XF8000170[5:4] = 0x00000000U | ||
8933 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8934 | // .. .. DIVISOR0 = 0x14 | ||
8935 | // .. .. ==> 0XF8000170[13:8] = 0x00000014U | ||
8936 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
8937 | // .. .. DIVISOR1 = 0x1 | ||
8938 | // .. .. ==> 0XF8000170[25:20] = 0x00000001U | ||
8939 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
8940 | // .. .. | ||
8941 | EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), | ||
8942 | // .. .. SRCSEL = 0x0 | ||
8943 | // .. .. ==> 0XF8000180[5:4] = 0x00000000U | ||
8944 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8945 | // .. .. DIVISOR0 = 0x14 | ||
8946 | // .. .. ==> 0XF8000180[13:8] = 0x00000014U | ||
8947 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U | ||
8948 | // .. .. DIVISOR1 = 0x1 | ||
8949 | // .. .. ==> 0XF8000180[25:20] = 0x00000001U | ||
8950 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
8951 | // .. .. | ||
8952 | EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), | ||
8953 | // .. .. SRCSEL = 0x0 | ||
8954 | // .. .. ==> 0XF8000190[5:4] = 0x00000000U | ||
8955 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8956 | // .. .. DIVISOR0 = 0x3c | ||
8957 | // .. .. ==> 0XF8000190[13:8] = 0x0000003CU | ||
8958 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00003C00U | ||
8959 | // .. .. DIVISOR1 = 0x1 | ||
8960 | // .. .. ==> 0XF8000190[25:20] = 0x00000001U | ||
8961 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
8962 | // .. .. | ||
8963 | EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U), | ||
8964 | // .. .. SRCSEL = 0x0 | ||
8965 | // .. .. ==> 0XF80001A0[5:4] = 0x00000000U | ||
8966 | // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U | ||
8967 | // .. .. DIVISOR0 = 0x28 | ||
8968 | // .. .. ==> 0XF80001A0[13:8] = 0x00000028U | ||
8969 | // .. .. ==> MASK : 0x00003F00U VAL : 0x00002800U | ||
8970 | // .. .. DIVISOR1 = 0x1 | ||
8971 | // .. .. ==> 0XF80001A0[25:20] = 0x00000001U | ||
8972 | // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U | ||
8973 | // .. .. | ||
8974 | EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U), | ||
8975 | // .. .. CLK_621_TRUE = 0x1 | ||
8976 | // .. .. ==> 0XF80001C4[0:0] = 0x00000001U | ||
8977 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8978 | // .. .. | ||
8979 | EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), | ||
8980 | // .. .. DMA_CPU_2XCLKACT = 0x1 | ||
8981 | // .. .. ==> 0XF800012C[0:0] = 0x00000001U | ||
8982 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
8983 | // .. .. USB0_CPU_1XCLKACT = 0x1 | ||
8984 | // .. .. ==> 0XF800012C[2:2] = 0x00000001U | ||
8985 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
8986 | // .. .. USB1_CPU_1XCLKACT = 0x1 | ||
8987 | // .. .. ==> 0XF800012C[3:3] = 0x00000001U | ||
8988 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
8989 | // .. .. GEM0_CPU_1XCLKACT = 0x1 | ||
8990 | // .. .. ==> 0XF800012C[6:6] = 0x00000001U | ||
8991 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U | ||
8992 | // .. .. GEM1_CPU_1XCLKACT = 0x0 | ||
8993 | // .. .. ==> 0XF800012C[7:7] = 0x00000000U | ||
8994 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
8995 | // .. .. SDI0_CPU_1XCLKACT = 0x0 | ||
8996 | // .. .. ==> 0XF800012C[10:10] = 0x00000000U | ||
8997 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
8998 | // .. .. SDI1_CPU_1XCLKACT = 0x1 | ||
8999 | // .. .. ==> 0XF800012C[11:11] = 0x00000001U | ||
9000 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U | ||
9001 | // .. .. SPI0_CPU_1XCLKACT = 0x0 | ||
9002 | // .. .. ==> 0XF800012C[14:14] = 0x00000000U | ||
9003 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
9004 | // .. .. SPI1_CPU_1XCLKACT = 0x0 | ||
9005 | // .. .. ==> 0XF800012C[15:15] = 0x00000000U | ||
9006 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
9007 | // .. .. CAN0_CPU_1XCLKACT = 0x0 | ||
9008 | // .. .. ==> 0XF800012C[16:16] = 0x00000000U | ||
9009 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
9010 | // .. .. CAN1_CPU_1XCLKACT = 0x0 | ||
9011 | // .. .. ==> 0XF800012C[17:17] = 0x00000000U | ||
9012 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
9013 | // .. .. I2C0_CPU_1XCLKACT = 0x1 | ||
9014 | // .. .. ==> 0XF800012C[18:18] = 0x00000001U | ||
9015 | // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U | ||
9016 | // .. .. I2C1_CPU_1XCLKACT = 0x1 | ||
9017 | // .. .. ==> 0XF800012C[19:19] = 0x00000001U | ||
9018 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
9019 | // .. .. UART0_CPU_1XCLKACT = 0x0 | ||
9020 | // .. .. ==> 0XF800012C[20:20] = 0x00000000U | ||
9021 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
9022 | // .. .. UART1_CPU_1XCLKACT = 0x1 | ||
9023 | // .. .. ==> 0XF800012C[21:21] = 0x00000001U | ||
9024 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
9025 | // .. .. GPIO_CPU_1XCLKACT = 0x1 | ||
9026 | // .. .. ==> 0XF800012C[22:22] = 0x00000001U | ||
9027 | // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U | ||
9028 | // .. .. LQSPI_CPU_1XCLKACT = 0x1 | ||
9029 | // .. .. ==> 0XF800012C[23:23] = 0x00000001U | ||
9030 | // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U | ||
9031 | // .. .. SMC_CPU_1XCLKACT = 0x1 | ||
9032 | // .. .. ==> 0XF800012C[24:24] = 0x00000001U | ||
9033 | // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U | ||
9034 | // .. .. | ||
9035 | EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU), | ||
9036 | // .. FINISH: CLOCK CONTROL SLCR REGISTERS | ||
9037 | // .. START: THIS SHOULD BE BLANK | ||
9038 | // .. FINISH: THIS SHOULD BE BLANK | ||
9039 | // .. START: LOCK IT BACK | ||
9040 | // .. LOCK_KEY = 0X767B | ||
9041 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
9042 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
9043 | // .. | ||
9044 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
9045 | // .. FINISH: LOCK IT BACK | ||
9046 | // FINISH: top | ||
9047 | // | ||
9048 | EMIT_EXIT(), | ||
9049 | |||
9050 | // | ||
9051 | }; | ||
9052 | |||
9053 | unsigned long ps7_ddr_init_data_1_0[] = { | ||
9054 | // START: top | ||
9055 | // .. START: DDR INITIALIZATION | ||
9056 | // .. .. START: LOCK DDR | ||
9057 | // .. .. reg_ddrc_soft_rstb = 0 | ||
9058 | // .. .. ==> 0XF8006000[0:0] = 0x00000000U | ||
9059 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9060 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
9061 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
9062 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9063 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
9064 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
9065 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
9066 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
9067 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
9068 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
9069 | // .. .. reg_ddrc_rdwr_idle_gap = 0x1 | ||
9070 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
9071 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
9072 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
9073 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
9074 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
9075 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
9076 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
9077 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
9078 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
9079 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
9080 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
9081 | // .. .. | ||
9082 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), | ||
9083 | // .. .. FINISH: LOCK DDR | ||
9084 | // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 | ||
9085 | // .. .. ==> 0XF8006004[11:0] = 0x00000081U | ||
9086 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U | ||
9087 | // .. .. reg_ddrc_active_ranks = 0x1 | ||
9088 | // .. .. ==> 0XF8006004[13:12] = 0x00000001U | ||
9089 | // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U | ||
9090 | // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 | ||
9091 | // .. .. ==> 0XF8006004[18:14] = 0x00000000U | ||
9092 | // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U | ||
9093 | // .. .. reg_ddrc_wr_odt_block = 0x1 | ||
9094 | // .. .. ==> 0XF8006004[20:19] = 0x00000001U | ||
9095 | // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U | ||
9096 | // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 | ||
9097 | // .. .. ==> 0XF8006004[21:21] = 0x00000000U | ||
9098 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
9099 | // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 | ||
9100 | // .. .. ==> 0XF8006004[26:22] = 0x00000000U | ||
9101 | // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U | ||
9102 | // .. .. reg_ddrc_addrmap_open_bank = 0x0 | ||
9103 | // .. .. ==> 0XF8006004[27:27] = 0x00000000U | ||
9104 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
9105 | // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 | ||
9106 | // .. .. ==> 0XF8006004[28:28] = 0x00000000U | ||
9107 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
9108 | // .. .. | ||
9109 | EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), | ||
9110 | // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf | ||
9111 | // .. .. ==> 0XF8006008[10:0] = 0x0000000FU | ||
9112 | // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU | ||
9113 | // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf | ||
9114 | // .. .. ==> 0XF8006008[21:11] = 0x0000000FU | ||
9115 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U | ||
9116 | // .. .. reg_ddrc_hpr_xact_run_length = 0xf | ||
9117 | // .. .. ==> 0XF8006008[25:22] = 0x0000000FU | ||
9118 | // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U | ||
9119 | // .. .. | ||
9120 | EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), | ||
9121 | // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 | ||
9122 | // .. .. ==> 0XF800600C[10:0] = 0x00000001U | ||
9123 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
9124 | // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 | ||
9125 | // .. .. ==> 0XF800600C[21:11] = 0x00000002U | ||
9126 | // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U | ||
9127 | // .. .. reg_ddrc_lpr_xact_run_length = 0x8 | ||
9128 | // .. .. ==> 0XF800600C[25:22] = 0x00000008U | ||
9129 | // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U | ||
9130 | // .. .. | ||
9131 | EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), | ||
9132 | // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 | ||
9133 | // .. .. ==> 0XF8006010[10:0] = 0x00000001U | ||
9134 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U | ||
9135 | // .. .. reg_ddrc_w_xact_run_length = 0x8 | ||
9136 | // .. .. ==> 0XF8006010[14:11] = 0x00000008U | ||
9137 | // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U | ||
9138 | // .. .. reg_ddrc_w_max_starve_x32 = 0x2 | ||
9139 | // .. .. ==> 0XF8006010[25:15] = 0x00000002U | ||
9140 | // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U | ||
9141 | // .. .. | ||
9142 | EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), | ||
9143 | // .. .. reg_ddrc_t_rc = 0x1a | ||
9144 | // .. .. ==> 0XF8006014[5:0] = 0x0000001AU | ||
9145 | // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU | ||
9146 | // .. .. reg_ddrc_t_rfc_min = 0xa0 | ||
9147 | // .. .. ==> 0XF8006014[13:6] = 0x000000A0U | ||
9148 | // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U | ||
9149 | // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 | ||
9150 | // .. .. ==> 0XF8006014[20:14] = 0x00000010U | ||
9151 | // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U | ||
9152 | // .. .. | ||
9153 | EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU), | ||
9154 | // .. .. reg_ddrc_wr2pre = 0x12 | ||
9155 | // .. .. ==> 0XF8006018[4:0] = 0x00000012U | ||
9156 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U | ||
9157 | // .. .. reg_ddrc_powerdown_to_x32 = 0x6 | ||
9158 | // .. .. ==> 0XF8006018[9:5] = 0x00000006U | ||
9159 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U | ||
9160 | // .. .. reg_ddrc_t_faw = 0x16 | ||
9161 | // .. .. ==> 0XF8006018[15:10] = 0x00000016U | ||
9162 | // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U | ||
9163 | // .. .. reg_ddrc_t_ras_max = 0x24 | ||
9164 | // .. .. ==> 0XF8006018[21:16] = 0x00000024U | ||
9165 | // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U | ||
9166 | // .. .. reg_ddrc_t_ras_min = 0x13 | ||
9167 | // .. .. ==> 0XF8006018[26:22] = 0x00000013U | ||
9168 | // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U | ||
9169 | // .. .. reg_ddrc_t_cke = 0x4 | ||
9170 | // .. .. ==> 0XF8006018[31:28] = 0x00000004U | ||
9171 | // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U | ||
9172 | // .. .. | ||
9173 | EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), | ||
9174 | // .. .. reg_ddrc_write_latency = 0x5 | ||
9175 | // .. .. ==> 0XF800601C[4:0] = 0x00000005U | ||
9176 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U | ||
9177 | // .. .. reg_ddrc_rd2wr = 0x7 | ||
9178 | // .. .. ==> 0XF800601C[9:5] = 0x00000007U | ||
9179 | // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U | ||
9180 | // .. .. reg_ddrc_wr2rd = 0xe | ||
9181 | // .. .. ==> 0XF800601C[14:10] = 0x0000000EU | ||
9182 | // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U | ||
9183 | // .. .. reg_ddrc_t_xp = 0x4 | ||
9184 | // .. .. ==> 0XF800601C[19:15] = 0x00000004U | ||
9185 | // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U | ||
9186 | // .. .. reg_ddrc_pad_pd = 0x0 | ||
9187 | // .. .. ==> 0XF800601C[22:20] = 0x00000000U | ||
9188 | // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U | ||
9189 | // .. .. reg_ddrc_rd2pre = 0x4 | ||
9190 | // .. .. ==> 0XF800601C[27:23] = 0x00000004U | ||
9191 | // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U | ||
9192 | // .. .. reg_ddrc_t_rcd = 0x7 | ||
9193 | // .. .. ==> 0XF800601C[31:28] = 0x00000007U | ||
9194 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
9195 | // .. .. | ||
9196 | EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), | ||
9197 | // .. .. reg_ddrc_t_ccd = 0x4 | ||
9198 | // .. .. ==> 0XF8006020[4:2] = 0x00000004U | ||
9199 | // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U | ||
9200 | // .. .. reg_ddrc_t_rrd = 0x6 | ||
9201 | // .. .. ==> 0XF8006020[7:5] = 0x00000006U | ||
9202 | // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U | ||
9203 | // .. .. reg_ddrc_refresh_margin = 0x2 | ||
9204 | // .. .. ==> 0XF8006020[11:8] = 0x00000002U | ||
9205 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U | ||
9206 | // .. .. reg_ddrc_t_rp = 0x7 | ||
9207 | // .. .. ==> 0XF8006020[15:12] = 0x00000007U | ||
9208 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U | ||
9209 | // .. .. reg_ddrc_refresh_to_x32 = 0x8 | ||
9210 | // .. .. ==> 0XF8006020[20:16] = 0x00000008U | ||
9211 | // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U | ||
9212 | // .. .. reg_ddrc_sdram = 0x1 | ||
9213 | // .. .. ==> 0XF8006020[21:21] = 0x00000001U | ||
9214 | // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U | ||
9215 | // .. .. reg_ddrc_mobile = 0x0 | ||
9216 | // .. .. ==> 0XF8006020[22:22] = 0x00000000U | ||
9217 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
9218 | // .. .. reg_ddrc_clock_stop_en = 0x0 | ||
9219 | // .. .. ==> 0XF8006020[23:23] = 0x00000000U | ||
9220 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
9221 | // .. .. reg_ddrc_read_latency = 0x7 | ||
9222 | // .. .. ==> 0XF8006020[28:24] = 0x00000007U | ||
9223 | // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U | ||
9224 | // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 | ||
9225 | // .. .. ==> 0XF8006020[29:29] = 0x00000001U | ||
9226 | // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U | ||
9227 | // .. .. reg_ddrc_dis_pad_pd = 0x0 | ||
9228 | // .. .. ==> 0XF8006020[30:30] = 0x00000000U | ||
9229 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
9230 | // .. .. reg_ddrc_loopback = 0x0 | ||
9231 | // .. .. ==> 0XF8006020[31:31] = 0x00000000U | ||
9232 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
9233 | // .. .. | ||
9234 | EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), | ||
9235 | // .. .. reg_ddrc_en_2t_timing_mode = 0x0 | ||
9236 | // .. .. ==> 0XF8006024[0:0] = 0x00000000U | ||
9237 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9238 | // .. .. reg_ddrc_prefer_write = 0x0 | ||
9239 | // .. .. ==> 0XF8006024[1:1] = 0x00000000U | ||
9240 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9241 | // .. .. reg_ddrc_max_rank_rd = 0xf | ||
9242 | // .. .. ==> 0XF8006024[5:2] = 0x0000000FU | ||
9243 | // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU | ||
9244 | // .. .. reg_ddrc_mr_wr = 0x0 | ||
9245 | // .. .. ==> 0XF8006024[6:6] = 0x00000000U | ||
9246 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
9247 | // .. .. reg_ddrc_mr_addr = 0x0 | ||
9248 | // .. .. ==> 0XF8006024[8:7] = 0x00000000U | ||
9249 | // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
9250 | // .. .. reg_ddrc_mr_data = 0x0 | ||
9251 | // .. .. ==> 0XF8006024[24:9] = 0x00000000U | ||
9252 | // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U | ||
9253 | // .. .. ddrc_reg_mr_wr_busy = 0x0 | ||
9254 | // .. .. ==> 0XF8006024[25:25] = 0x00000000U | ||
9255 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
9256 | // .. .. reg_ddrc_mr_type = 0x0 | ||
9257 | // .. .. ==> 0XF8006024[26:26] = 0x00000000U | ||
9258 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
9259 | // .. .. reg_ddrc_mr_rdata_valid = 0x0 | ||
9260 | // .. .. ==> 0XF8006024[27:27] = 0x00000000U | ||
9261 | // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U | ||
9262 | // .. .. | ||
9263 | EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), | ||
9264 | // .. .. reg_ddrc_final_wait_x32 = 0x7 | ||
9265 | // .. .. ==> 0XF8006028[6:0] = 0x00000007U | ||
9266 | // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U | ||
9267 | // .. .. reg_ddrc_pre_ocd_x32 = 0x0 | ||
9268 | // .. .. ==> 0XF8006028[10:7] = 0x00000000U | ||
9269 | // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U | ||
9270 | // .. .. reg_ddrc_t_mrd = 0x4 | ||
9271 | // .. .. ==> 0XF8006028[13:11] = 0x00000004U | ||
9272 | // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U | ||
9273 | // .. .. | ||
9274 | EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), | ||
9275 | // .. .. reg_ddrc_emr2 = 0x8 | ||
9276 | // .. .. ==> 0XF800602C[15:0] = 0x00000008U | ||
9277 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U | ||
9278 | // .. .. reg_ddrc_emr3 = 0x0 | ||
9279 | // .. .. ==> 0XF800602C[31:16] = 0x00000000U | ||
9280 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U | ||
9281 | // .. .. | ||
9282 | EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), | ||
9283 | // .. .. reg_ddrc_mr = 0x930 | ||
9284 | // .. .. ==> 0XF8006030[15:0] = 0x00000930U | ||
9285 | // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U | ||
9286 | // .. .. reg_ddrc_emr = 0x4 | ||
9287 | // .. .. ==> 0XF8006030[31:16] = 0x00000004U | ||
9288 | // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U | ||
9289 | // .. .. | ||
9290 | EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), | ||
9291 | // .. .. reg_ddrc_burst_rdwr = 0x4 | ||
9292 | // .. .. ==> 0XF8006034[3:0] = 0x00000004U | ||
9293 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U | ||
9294 | // .. .. reg_ddrc_pre_cke_x1024 = 0x105 | ||
9295 | // .. .. ==> 0XF8006034[13:4] = 0x00000105U | ||
9296 | // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U | ||
9297 | // .. .. reg_ddrc_post_cke_x1024 = 0x1 | ||
9298 | // .. .. ==> 0XF8006034[25:16] = 0x00000001U | ||
9299 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U | ||
9300 | // .. .. reg_ddrc_burstchop = 0x0 | ||
9301 | // .. .. ==> 0XF8006034[28:28] = 0x00000000U | ||
9302 | // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U | ||
9303 | // .. .. | ||
9304 | EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), | ||
9305 | // .. .. reg_ddrc_force_low_pri_n = 0x0 | ||
9306 | // .. .. ==> 0XF8006038[0:0] = 0x00000000U | ||
9307 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9308 | // .. .. reg_ddrc_dis_dq = 0x0 | ||
9309 | // .. .. ==> 0XF8006038[1:1] = 0x00000000U | ||
9310 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9311 | // .. .. reg_phy_debug_mode = 0x0 | ||
9312 | // .. .. ==> 0XF8006038[6:6] = 0x00000000U | ||
9313 | // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
9314 | // .. .. reg_phy_wr_level_start = 0x0 | ||
9315 | // .. .. ==> 0XF8006038[7:7] = 0x00000000U | ||
9316 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
9317 | // .. .. reg_phy_rd_level_start = 0x0 | ||
9318 | // .. .. ==> 0XF8006038[8:8] = 0x00000000U | ||
9319 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
9320 | // .. .. reg_phy_dq0_wait_t = 0x0 | ||
9321 | // .. .. ==> 0XF8006038[12:9] = 0x00000000U | ||
9322 | // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U | ||
9323 | // .. .. | ||
9324 | EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), | ||
9325 | // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 | ||
9326 | // .. .. ==> 0XF800603C[3:0] = 0x00000007U | ||
9327 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U | ||
9328 | // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 | ||
9329 | // .. .. ==> 0XF800603C[7:4] = 0x00000007U | ||
9330 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U | ||
9331 | // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 | ||
9332 | // .. .. ==> 0XF800603C[11:8] = 0x00000007U | ||
9333 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U | ||
9334 | // .. .. reg_ddrc_addrmap_col_b5 = 0x0 | ||
9335 | // .. .. ==> 0XF800603C[15:12] = 0x00000000U | ||
9336 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
9337 | // .. .. reg_ddrc_addrmap_col_b6 = 0x0 | ||
9338 | // .. .. ==> 0XF800603C[19:16] = 0x00000000U | ||
9339 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
9340 | // .. .. | ||
9341 | EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), | ||
9342 | // .. .. reg_ddrc_addrmap_col_b2 = 0x0 | ||
9343 | // .. .. ==> 0XF8006040[3:0] = 0x00000000U | ||
9344 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
9345 | // .. .. reg_ddrc_addrmap_col_b3 = 0x0 | ||
9346 | // .. .. ==> 0XF8006040[7:4] = 0x00000000U | ||
9347 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
9348 | // .. .. reg_ddrc_addrmap_col_b4 = 0x0 | ||
9349 | // .. .. ==> 0XF8006040[11:8] = 0x00000000U | ||
9350 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
9351 | // .. .. reg_ddrc_addrmap_col_b7 = 0x0 | ||
9352 | // .. .. ==> 0XF8006040[15:12] = 0x00000000U | ||
9353 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U | ||
9354 | // .. .. reg_ddrc_addrmap_col_b8 = 0x0 | ||
9355 | // .. .. ==> 0XF8006040[19:16] = 0x00000000U | ||
9356 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U | ||
9357 | // .. .. reg_ddrc_addrmap_col_b9 = 0xf | ||
9358 | // .. .. ==> 0XF8006040[23:20] = 0x0000000FU | ||
9359 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U | ||
9360 | // .. .. reg_ddrc_addrmap_col_b10 = 0xf | ||
9361 | // .. .. ==> 0XF8006040[27:24] = 0x0000000FU | ||
9362 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
9363 | // .. .. reg_ddrc_addrmap_col_b11 = 0xf | ||
9364 | // .. .. ==> 0XF8006040[31:28] = 0x0000000FU | ||
9365 | // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U | ||
9366 | // .. .. | ||
9367 | EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), | ||
9368 | // .. .. reg_ddrc_addrmap_row_b0 = 0x6 | ||
9369 | // .. .. ==> 0XF8006044[3:0] = 0x00000006U | ||
9370 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U | ||
9371 | // .. .. reg_ddrc_addrmap_row_b1 = 0x6 | ||
9372 | // .. .. ==> 0XF8006044[7:4] = 0x00000006U | ||
9373 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U | ||
9374 | // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 | ||
9375 | // .. .. ==> 0XF8006044[11:8] = 0x00000006U | ||
9376 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U | ||
9377 | // .. .. reg_ddrc_addrmap_row_b12 = 0x6 | ||
9378 | // .. .. ==> 0XF8006044[15:12] = 0x00000006U | ||
9379 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U | ||
9380 | // .. .. reg_ddrc_addrmap_row_b13 = 0x6 | ||
9381 | // .. .. ==> 0XF8006044[19:16] = 0x00000006U | ||
9382 | // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U | ||
9383 | // .. .. reg_ddrc_addrmap_row_b14 = 0x6 | ||
9384 | // .. .. ==> 0XF8006044[23:20] = 0x00000006U | ||
9385 | // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U | ||
9386 | // .. .. reg_ddrc_addrmap_row_b15 = 0xf | ||
9387 | // .. .. ==> 0XF8006044[27:24] = 0x0000000FU | ||
9388 | // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U | ||
9389 | // .. .. | ||
9390 | EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), | ||
9391 | // .. .. reg_ddrc_rank0_rd_odt = 0x0 | ||
9392 | // .. .. ==> 0XF8006048[2:0] = 0x00000000U | ||
9393 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
9394 | // .. .. reg_ddrc_rank0_wr_odt = 0x1 | ||
9395 | // .. .. ==> 0XF8006048[5:3] = 0x00000001U | ||
9396 | // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U | ||
9397 | // .. .. reg_ddrc_rank1_rd_odt = 0x1 | ||
9398 | // .. .. ==> 0XF8006048[8:6] = 0x00000001U | ||
9399 | // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U | ||
9400 | // .. .. reg_ddrc_rank1_wr_odt = 0x1 | ||
9401 | // .. .. ==> 0XF8006048[11:9] = 0x00000001U | ||
9402 | // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
9403 | // .. .. reg_phy_rd_local_odt = 0x0 | ||
9404 | // .. .. ==> 0XF8006048[13:12] = 0x00000000U | ||
9405 | // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U | ||
9406 | // .. .. reg_phy_wr_local_odt = 0x3 | ||
9407 | // .. .. ==> 0XF8006048[15:14] = 0x00000003U | ||
9408 | // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U | ||
9409 | // .. .. reg_phy_idle_local_odt = 0x3 | ||
9410 | // .. .. ==> 0XF8006048[17:16] = 0x00000003U | ||
9411 | // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U | ||
9412 | // .. .. reg_ddrc_rank2_rd_odt = 0x0 | ||
9413 | // .. .. ==> 0XF8006048[20:18] = 0x00000000U | ||
9414 | // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U | ||
9415 | // .. .. reg_ddrc_rank2_wr_odt = 0x0 | ||
9416 | // .. .. ==> 0XF8006048[23:21] = 0x00000000U | ||
9417 | // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U | ||
9418 | // .. .. reg_ddrc_rank3_rd_odt = 0x0 | ||
9419 | // .. .. ==> 0XF8006048[26:24] = 0x00000000U | ||
9420 | // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
9421 | // .. .. reg_ddrc_rank3_wr_odt = 0x0 | ||
9422 | // .. .. ==> 0XF8006048[29:27] = 0x00000000U | ||
9423 | // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U | ||
9424 | // .. .. | ||
9425 | EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), | ||
9426 | // .. .. reg_phy_rd_cmd_to_data = 0x0 | ||
9427 | // .. .. ==> 0XF8006050[3:0] = 0x00000000U | ||
9428 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
9429 | // .. .. reg_phy_wr_cmd_to_data = 0x0 | ||
9430 | // .. .. ==> 0XF8006050[7:4] = 0x00000000U | ||
9431 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
9432 | // .. .. reg_phy_rdc_we_to_re_delay = 0x8 | ||
9433 | // .. .. ==> 0XF8006050[11:8] = 0x00000008U | ||
9434 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U | ||
9435 | // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 | ||
9436 | // .. .. ==> 0XF8006050[15:15] = 0x00000000U | ||
9437 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
9438 | // .. .. reg_phy_use_fixed_re = 0x1 | ||
9439 | // .. .. ==> 0XF8006050[16:16] = 0x00000001U | ||
9440 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
9441 | // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 | ||
9442 | // .. .. ==> 0XF8006050[17:17] = 0x00000000U | ||
9443 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
9444 | // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 | ||
9445 | // .. .. ==> 0XF8006050[18:18] = 0x00000000U | ||
9446 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
9447 | // .. .. reg_phy_clk_stall_level = 0x0 | ||
9448 | // .. .. ==> 0XF8006050[19:19] = 0x00000000U | ||
9449 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
9450 | // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 | ||
9451 | // .. .. ==> 0XF8006050[27:24] = 0x00000007U | ||
9452 | // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U | ||
9453 | // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 | ||
9454 | // .. .. ==> 0XF8006050[31:28] = 0x00000007U | ||
9455 | // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U | ||
9456 | // .. .. | ||
9457 | EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), | ||
9458 | // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 | ||
9459 | // .. .. ==> 0XF8006058[7:0] = 0x00000001U | ||
9460 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U | ||
9461 | // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 | ||
9462 | // .. .. ==> 0XF8006058[15:8] = 0x00000001U | ||
9463 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U | ||
9464 | // .. .. reg_ddrc_dis_dll_calib = 0x0 | ||
9465 | // .. .. ==> 0XF8006058[16:16] = 0x00000000U | ||
9466 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
9467 | // .. .. | ||
9468 | EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), | ||
9469 | // .. .. reg_ddrc_rd_odt_delay = 0x3 | ||
9470 | // .. .. ==> 0XF800605C[3:0] = 0x00000003U | ||
9471 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U | ||
9472 | // .. .. reg_ddrc_wr_odt_delay = 0x0 | ||
9473 | // .. .. ==> 0XF800605C[7:4] = 0x00000000U | ||
9474 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
9475 | // .. .. reg_ddrc_rd_odt_hold = 0x0 | ||
9476 | // .. .. ==> 0XF800605C[11:8] = 0x00000000U | ||
9477 | // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U | ||
9478 | // .. .. reg_ddrc_wr_odt_hold = 0x5 | ||
9479 | // .. .. ==> 0XF800605C[15:12] = 0x00000005U | ||
9480 | // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U | ||
9481 | // .. .. | ||
9482 | EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), | ||
9483 | // .. .. reg_ddrc_pageclose = 0x0 | ||
9484 | // .. .. ==> 0XF8006060[0:0] = 0x00000000U | ||
9485 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9486 | // .. .. reg_ddrc_lpr_num_entries = 0x1f | ||
9487 | // .. .. ==> 0XF8006060[6:1] = 0x0000001FU | ||
9488 | // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU | ||
9489 | // .. .. reg_ddrc_auto_pre_en = 0x0 | ||
9490 | // .. .. ==> 0XF8006060[7:7] = 0x00000000U | ||
9491 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
9492 | // .. .. reg_ddrc_refresh_update_level = 0x0 | ||
9493 | // .. .. ==> 0XF8006060[8:8] = 0x00000000U | ||
9494 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
9495 | // .. .. reg_ddrc_dis_wc = 0x0 | ||
9496 | // .. .. ==> 0XF8006060[9:9] = 0x00000000U | ||
9497 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
9498 | // .. .. reg_ddrc_dis_collision_page_opt = 0x0 | ||
9499 | // .. .. ==> 0XF8006060[10:10] = 0x00000000U | ||
9500 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9501 | // .. .. reg_ddrc_selfref_en = 0x0 | ||
9502 | // .. .. ==> 0XF8006060[12:12] = 0x00000000U | ||
9503 | // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
9504 | // .. .. | ||
9505 | EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), | ||
9506 | // .. .. reg_ddrc_go2critical_hysteresis = 0x0 | ||
9507 | // .. .. ==> 0XF8006064[12:5] = 0x00000000U | ||
9508 | // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U | ||
9509 | // .. .. reg_arb_go2critical_en = 0x1 | ||
9510 | // .. .. ==> 0XF8006064[17:17] = 0x00000001U | ||
9511 | // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U | ||
9512 | // .. .. | ||
9513 | EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), | ||
9514 | // .. .. reg_ddrc_wrlvl_ww = 0x41 | ||
9515 | // .. .. ==> 0XF8006068[7:0] = 0x00000041U | ||
9516 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U | ||
9517 | // .. .. reg_ddrc_rdlvl_rr = 0x41 | ||
9518 | // .. .. ==> 0XF8006068[15:8] = 0x00000041U | ||
9519 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U | ||
9520 | // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 | ||
9521 | // .. .. ==> 0XF8006068[25:16] = 0x00000028U | ||
9522 | // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U | ||
9523 | // .. .. | ||
9524 | EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), | ||
9525 | // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 | ||
9526 | // .. .. ==> 0XF800606C[7:0] = 0x00000010U | ||
9527 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U | ||
9528 | // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 | ||
9529 | // .. .. ==> 0XF800606C[15:8] = 0x00000016U | ||
9530 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U | ||
9531 | // .. .. | ||
9532 | EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), | ||
9533 | // .. .. refresh_timer0_start_value_x32 = 0x0 | ||
9534 | // .. .. ==> 0XF80060A0[11:0] = 0x00000000U | ||
9535 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U | ||
9536 | // .. .. refresh_timer1_start_value_x32 = 0x8 | ||
9537 | // .. .. ==> 0XF80060A0[23:12] = 0x00000008U | ||
9538 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U | ||
9539 | // .. .. | ||
9540 | EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), | ||
9541 | // .. .. reg_ddrc_dis_auto_zq = 0x0 | ||
9542 | // .. .. ==> 0XF80060A4[0:0] = 0x00000000U | ||
9543 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9544 | // .. .. reg_ddrc_ddr3 = 0x1 | ||
9545 | // .. .. ==> 0XF80060A4[1:1] = 0x00000001U | ||
9546 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
9547 | // .. .. reg_ddrc_t_mod = 0x200 | ||
9548 | // .. .. ==> 0XF80060A4[11:2] = 0x00000200U | ||
9549 | // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U | ||
9550 | // .. .. reg_ddrc_t_zq_long_nop = 0x200 | ||
9551 | // .. .. ==> 0XF80060A4[21:12] = 0x00000200U | ||
9552 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U | ||
9553 | // .. .. reg_ddrc_t_zq_short_nop = 0x40 | ||
9554 | // .. .. ==> 0XF80060A4[31:22] = 0x00000040U | ||
9555 | // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U | ||
9556 | // .. .. | ||
9557 | EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), | ||
9558 | // .. .. t_zq_short_interval_x1024 = 0xcb73 | ||
9559 | // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U | ||
9560 | // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U | ||
9561 | // .. .. dram_rstn_x1024 = 0x69 | ||
9562 | // .. .. ==> 0XF80060A8[27:20] = 0x00000069U | ||
9563 | // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U | ||
9564 | // .. .. | ||
9565 | EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), | ||
9566 | // .. .. deeppowerdown_en = 0x0 | ||
9567 | // .. .. ==> 0XF80060AC[0:0] = 0x00000000U | ||
9568 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9569 | // .. .. deeppowerdown_to_x1024 = 0xff | ||
9570 | // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU | ||
9571 | // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU | ||
9572 | // .. .. | ||
9573 | EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), | ||
9574 | // .. .. dfi_wrlvl_max_x1024 = 0xfff | ||
9575 | // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU | ||
9576 | // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU | ||
9577 | // .. .. dfi_rdlvl_max_x1024 = 0xfff | ||
9578 | // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU | ||
9579 | // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U | ||
9580 | // .. .. ddrc_reg_twrlvl_max_error = 0x0 | ||
9581 | // .. .. ==> 0XF80060B0[24:24] = 0x00000000U | ||
9582 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
9583 | // .. .. ddrc_reg_trdlvl_max_error = 0x0 | ||
9584 | // .. .. ==> 0XF80060B0[25:25] = 0x00000000U | ||
9585 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
9586 | // .. .. reg_ddrc_dfi_wr_level_en = 0x1 | ||
9587 | // .. .. ==> 0XF80060B0[26:26] = 0x00000001U | ||
9588 | // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U | ||
9589 | // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 | ||
9590 | // .. .. ==> 0XF80060B0[27:27] = 0x00000001U | ||
9591 | // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U | ||
9592 | // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 | ||
9593 | // .. .. ==> 0XF80060B0[28:28] = 0x00000001U | ||
9594 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
9595 | // .. .. | ||
9596 | EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), | ||
9597 | // .. .. reg_ddrc_2t_delay = 0x0 | ||
9598 | // .. .. ==> 0XF80060B4[8:0] = 0x00000000U | ||
9599 | // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U | ||
9600 | // .. .. reg_ddrc_skip_ocd = 0x1 | ||
9601 | // .. .. ==> 0XF80060B4[9:9] = 0x00000001U | ||
9602 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
9603 | // .. .. reg_ddrc_dis_pre_bypass = 0x0 | ||
9604 | // .. .. ==> 0XF80060B4[10:10] = 0x00000000U | ||
9605 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9606 | // .. .. | ||
9607 | EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), | ||
9608 | // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 | ||
9609 | // .. .. ==> 0XF80060B8[4:0] = 0x00000006U | ||
9610 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U | ||
9611 | // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 | ||
9612 | // .. .. ==> 0XF80060B8[14:5] = 0x00000003U | ||
9613 | // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U | ||
9614 | // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 | ||
9615 | // .. .. ==> 0XF80060B8[24:15] = 0x00000040U | ||
9616 | // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U | ||
9617 | // .. .. | ||
9618 | EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), | ||
9619 | // .. .. START: RESET ECC ERROR | ||
9620 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 | ||
9621 | // .. .. ==> 0XF80060C4[0:0] = 0x00000001U | ||
9622 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
9623 | // .. .. Clear_Correctable_DRAM_ECC_error = 1 | ||
9624 | // .. .. ==> 0XF80060C4[1:1] = 0x00000001U | ||
9625 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
9626 | // .. .. | ||
9627 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), | ||
9628 | // .. .. FINISH: RESET ECC ERROR | ||
9629 | // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 | ||
9630 | // .. .. ==> 0XF80060C4[0:0] = 0x00000000U | ||
9631 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9632 | // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 | ||
9633 | // .. .. ==> 0XF80060C4[1:1] = 0x00000000U | ||
9634 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9635 | // .. .. | ||
9636 | EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), | ||
9637 | // .. .. CORR_ECC_LOG_VALID = 0x0 | ||
9638 | // .. .. ==> 0XF80060C8[0:0] = 0x00000000U | ||
9639 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9640 | // .. .. ECC_CORRECTED_BIT_NUM = 0x0 | ||
9641 | // .. .. ==> 0XF80060C8[7:1] = 0x00000000U | ||
9642 | // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U | ||
9643 | // .. .. | ||
9644 | EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), | ||
9645 | // .. .. UNCORR_ECC_LOG_VALID = 0x0 | ||
9646 | // .. .. ==> 0XF80060DC[0:0] = 0x00000000U | ||
9647 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
9648 | // .. .. | ||
9649 | EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), | ||
9650 | // .. .. STAT_NUM_CORR_ERR = 0x0 | ||
9651 | // .. .. ==> 0XF80060F0[15:8] = 0x00000000U | ||
9652 | // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U | ||
9653 | // .. .. STAT_NUM_UNCORR_ERR = 0x0 | ||
9654 | // .. .. ==> 0XF80060F0[7:0] = 0x00000000U | ||
9655 | // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U | ||
9656 | // .. .. | ||
9657 | EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), | ||
9658 | // .. .. reg_ddrc_ecc_mode = 0x0 | ||
9659 | // .. .. ==> 0XF80060F4[2:0] = 0x00000000U | ||
9660 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U | ||
9661 | // .. .. reg_ddrc_dis_scrub = 0x1 | ||
9662 | // .. .. ==> 0XF80060F4[3:3] = 0x00000001U | ||
9663 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U | ||
9664 | // .. .. | ||
9665 | EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), | ||
9666 | // .. .. reg_phy_dif_on = 0x0 | ||
9667 | // .. .. ==> 0XF8006114[3:0] = 0x00000000U | ||
9668 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U | ||
9669 | // .. .. reg_phy_dif_off = 0x0 | ||
9670 | // .. .. ==> 0XF8006114[7:4] = 0x00000000U | ||
9671 | // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
9672 | // .. .. | ||
9673 | EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), | ||
9674 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
9675 | // .. .. ==> 0XF8006118[0:0] = 0x00000001U | ||
9676 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
9677 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
9678 | // .. .. ==> 0XF8006118[1:1] = 0x00000000U | ||
9679 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9680 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
9681 | // .. .. ==> 0XF8006118[2:2] = 0x00000000U | ||
9682 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
9683 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
9684 | // .. .. ==> 0XF8006118[3:3] = 0x00000000U | ||
9685 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
9686 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
9687 | // .. .. ==> 0XF8006118[4:4] = 0x00000000U | ||
9688 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
9689 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
9690 | // .. .. ==> 0XF8006118[5:5] = 0x00000000U | ||
9691 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
9692 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
9693 | // .. .. ==> 0XF8006118[14:6] = 0x00000000U | ||
9694 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
9695 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
9696 | // .. .. ==> 0XF8006118[23:15] = 0x00000000U | ||
9697 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
9698 | // .. .. reg_phy_dq_offset = 0x40 | ||
9699 | // .. .. ==> 0XF8006118[30:24] = 0x00000040U | ||
9700 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
9701 | // .. .. | ||
9702 | EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), | ||
9703 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
9704 | // .. .. ==> 0XF800611C[0:0] = 0x00000001U | ||
9705 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
9706 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
9707 | // .. .. ==> 0XF800611C[1:1] = 0x00000000U | ||
9708 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9709 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
9710 | // .. .. ==> 0XF800611C[2:2] = 0x00000000U | ||
9711 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
9712 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
9713 | // .. .. ==> 0XF800611C[3:3] = 0x00000000U | ||
9714 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
9715 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
9716 | // .. .. ==> 0XF800611C[4:4] = 0x00000000U | ||
9717 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
9718 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
9719 | // .. .. ==> 0XF800611C[5:5] = 0x00000000U | ||
9720 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
9721 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
9722 | // .. .. ==> 0XF800611C[14:6] = 0x00000000U | ||
9723 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
9724 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
9725 | // .. .. ==> 0XF800611C[23:15] = 0x00000000U | ||
9726 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
9727 | // .. .. reg_phy_dq_offset = 0x40 | ||
9728 | // .. .. ==> 0XF800611C[30:24] = 0x00000040U | ||
9729 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
9730 | // .. .. | ||
9731 | EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), | ||
9732 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
9733 | // .. .. ==> 0XF8006120[0:0] = 0x00000001U | ||
9734 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
9735 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
9736 | // .. .. ==> 0XF8006120[1:1] = 0x00000000U | ||
9737 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9738 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
9739 | // .. .. ==> 0XF8006120[2:2] = 0x00000000U | ||
9740 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
9741 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
9742 | // .. .. ==> 0XF8006120[3:3] = 0x00000000U | ||
9743 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
9744 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
9745 | // .. .. ==> 0XF8006120[4:4] = 0x00000000U | ||
9746 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
9747 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
9748 | // .. .. ==> 0XF8006120[5:5] = 0x00000000U | ||
9749 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
9750 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
9751 | // .. .. ==> 0XF8006120[14:6] = 0x00000000U | ||
9752 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
9753 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
9754 | // .. .. ==> 0XF8006120[23:15] = 0x00000000U | ||
9755 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
9756 | // .. .. reg_phy_dq_offset = 0x40 | ||
9757 | // .. .. ==> 0XF8006120[30:24] = 0x00000040U | ||
9758 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
9759 | // .. .. | ||
9760 | EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), | ||
9761 | // .. .. reg_phy_data_slice_in_use = 0x1 | ||
9762 | // .. .. ==> 0XF8006124[0:0] = 0x00000001U | ||
9763 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
9764 | // .. .. reg_phy_rdlvl_inc_mode = 0x0 | ||
9765 | // .. .. ==> 0XF8006124[1:1] = 0x00000000U | ||
9766 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
9767 | // .. .. reg_phy_gatelvl_inc_mode = 0x0 | ||
9768 | // .. .. ==> 0XF8006124[2:2] = 0x00000000U | ||
9769 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
9770 | // .. .. reg_phy_wrlvl_inc_mode = 0x0 | ||
9771 | // .. .. ==> 0XF8006124[3:3] = 0x00000000U | ||
9772 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
9773 | // .. .. reg_phy_board_lpbk_tx = 0x0 | ||
9774 | // .. .. ==> 0XF8006124[4:4] = 0x00000000U | ||
9775 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
9776 | // .. .. reg_phy_board_lpbk_rx = 0x0 | ||
9777 | // .. .. ==> 0XF8006124[5:5] = 0x00000000U | ||
9778 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
9779 | // .. .. reg_phy_bist_shift_dq = 0x0 | ||
9780 | // .. .. ==> 0XF8006124[14:6] = 0x00000000U | ||
9781 | // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U | ||
9782 | // .. .. reg_phy_bist_err_clr = 0x0 | ||
9783 | // .. .. ==> 0XF8006124[23:15] = 0x00000000U | ||
9784 | // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U | ||
9785 | // .. .. reg_phy_dq_offset = 0x40 | ||
9786 | // .. .. ==> 0XF8006124[30:24] = 0x00000040U | ||
9787 | // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U | ||
9788 | // .. .. | ||
9789 | EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), | ||
9790 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
9791 | // .. .. ==> 0XF800612C[9:0] = 0x00000000U | ||
9792 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
9793 | // .. .. reg_phy_gatelvl_init_ratio = 0xa1 | ||
9794 | // .. .. ==> 0XF800612C[19:10] = 0x000000A1U | ||
9795 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028400U | ||
9796 | // .. .. | ||
9797 | EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U), | ||
9798 | // .. .. reg_phy_wrlvl_init_ratio = 0x0 | ||
9799 | // .. .. ==> 0XF8006130[9:0] = 0x00000000U | ||
9800 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U | ||
9801 | // .. .. reg_phy_gatelvl_init_ratio = 0xa0 | ||
9802 | // .. .. ==> 0XF8006130[19:10] = 0x000000A0U | ||
9803 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00028000U | ||
9804 | // .. .. | ||
9805 | EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U), | ||
9806 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
9807 | // .. .. ==> 0XF8006134[9:0] = 0x00000007U | ||
9808 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
9809 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
9810 | // .. .. ==> 0XF8006134[19:10] = 0x000000ADU | ||
9811 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
9812 | // .. .. | ||
9813 | EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U), | ||
9814 | // .. .. reg_phy_wrlvl_init_ratio = 0x7 | ||
9815 | // .. .. ==> 0XF8006138[9:0] = 0x00000007U | ||
9816 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000007U | ||
9817 | // .. .. reg_phy_gatelvl_init_ratio = 0xad | ||
9818 | // .. .. ==> 0XF8006138[19:10] = 0x000000ADU | ||
9819 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x0002B400U | ||
9820 | // .. .. | ||
9821 | EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U), | ||
9822 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
9823 | // .. .. ==> 0XF8006140[9:0] = 0x00000035U | ||
9824 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
9825 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
9826 | // .. .. ==> 0XF8006140[10:10] = 0x00000000U | ||
9827 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9828 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
9829 | // .. .. ==> 0XF8006140[19:11] = 0x00000000U | ||
9830 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9831 | // .. .. | ||
9832 | EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), | ||
9833 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
9834 | // .. .. ==> 0XF8006144[9:0] = 0x00000035U | ||
9835 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
9836 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
9837 | // .. .. ==> 0XF8006144[10:10] = 0x00000000U | ||
9838 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9839 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
9840 | // .. .. ==> 0XF8006144[19:11] = 0x00000000U | ||
9841 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9842 | // .. .. | ||
9843 | EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), | ||
9844 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
9845 | // .. .. ==> 0XF8006148[9:0] = 0x00000035U | ||
9846 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
9847 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
9848 | // .. .. ==> 0XF8006148[10:10] = 0x00000000U | ||
9849 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9850 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
9851 | // .. .. ==> 0XF8006148[19:11] = 0x00000000U | ||
9852 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9853 | // .. .. | ||
9854 | EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), | ||
9855 | // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 | ||
9856 | // .. .. ==> 0XF800614C[9:0] = 0x00000035U | ||
9857 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U | ||
9858 | // .. .. reg_phy_rd_dqs_slave_force = 0x0 | ||
9859 | // .. .. ==> 0XF800614C[10:10] = 0x00000000U | ||
9860 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9861 | // .. .. reg_phy_rd_dqs_slave_delay = 0x0 | ||
9862 | // .. .. ==> 0XF800614C[19:11] = 0x00000000U | ||
9863 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9864 | // .. .. | ||
9865 | EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), | ||
9866 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
9867 | // .. .. ==> 0XF8006154[9:0] = 0x0000007CU | ||
9868 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
9869 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
9870 | // .. .. ==> 0XF8006154[10:10] = 0x00000000U | ||
9871 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9872 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
9873 | // .. .. ==> 0XF8006154[19:11] = 0x00000000U | ||
9874 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9875 | // .. .. | ||
9876 | EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU), | ||
9877 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c | ||
9878 | // .. .. ==> 0XF8006158[9:0] = 0x0000007CU | ||
9879 | // .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU | ||
9880 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
9881 | // .. .. ==> 0XF8006158[10:10] = 0x00000000U | ||
9882 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9883 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
9884 | // .. .. ==> 0XF8006158[19:11] = 0x00000000U | ||
9885 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9886 | // .. .. | ||
9887 | EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU), | ||
9888 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
9889 | // .. .. ==> 0XF800615C[9:0] = 0x00000087U | ||
9890 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
9891 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
9892 | // .. .. ==> 0XF800615C[10:10] = 0x00000000U | ||
9893 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9894 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
9895 | // .. .. ==> 0XF800615C[19:11] = 0x00000000U | ||
9896 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9897 | // .. .. | ||
9898 | EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U), | ||
9899 | // .. .. reg_phy_wr_dqs_slave_ratio = 0x87 | ||
9900 | // .. .. ==> 0XF8006160[9:0] = 0x00000087U | ||
9901 | // .. .. ==> MASK : 0x000003FFU VAL : 0x00000087U | ||
9902 | // .. .. reg_phy_wr_dqs_slave_force = 0x0 | ||
9903 | // .. .. ==> 0XF8006160[10:10] = 0x00000000U | ||
9904 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9905 | // .. .. reg_phy_wr_dqs_slave_delay = 0x0 | ||
9906 | // .. .. ==> 0XF8006160[19:11] = 0x00000000U | ||
9907 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9908 | // .. .. | ||
9909 | EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U), | ||
9910 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf6 | ||
9911 | // .. .. ==> 0XF8006168[10:0] = 0x000000F6U | ||
9912 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F6U | ||
9913 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
9914 | // .. .. ==> 0XF8006168[11:11] = 0x00000000U | ||
9915 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
9916 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
9917 | // .. .. ==> 0XF8006168[20:12] = 0x00000000U | ||
9918 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
9919 | // .. .. | ||
9920 | EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U), | ||
9921 | // .. .. reg_phy_fifo_we_slave_ratio = 0xf5 | ||
9922 | // .. .. ==> 0XF800616C[10:0] = 0x000000F5U | ||
9923 | // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F5U | ||
9924 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
9925 | // .. .. ==> 0XF800616C[11:11] = 0x00000000U | ||
9926 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
9927 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
9928 | // .. .. ==> 0XF800616C[20:12] = 0x00000000U | ||
9929 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
9930 | // .. .. | ||
9931 | EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U), | ||
9932 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
9933 | // .. .. ==> 0XF8006170[10:0] = 0x00000102U | ||
9934 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
9935 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
9936 | // .. .. ==> 0XF8006170[11:11] = 0x00000000U | ||
9937 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
9938 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
9939 | // .. .. ==> 0XF8006170[20:12] = 0x00000000U | ||
9940 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
9941 | // .. .. | ||
9942 | EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U), | ||
9943 | // .. .. reg_phy_fifo_we_slave_ratio = 0x102 | ||
9944 | // .. .. ==> 0XF8006174[10:0] = 0x00000102U | ||
9945 | // .. .. ==> MASK : 0x000007FFU VAL : 0x00000102U | ||
9946 | // .. .. reg_phy_fifo_we_in_force = 0x0 | ||
9947 | // .. .. ==> 0XF8006174[11:11] = 0x00000000U | ||
9948 | // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
9949 | // .. .. reg_phy_fifo_we_in_delay = 0x0 | ||
9950 | // .. .. ==> 0XF8006174[20:12] = 0x00000000U | ||
9951 | // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U | ||
9952 | // .. .. | ||
9953 | EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U), | ||
9954 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
9955 | // .. .. ==> 0XF800617C[9:0] = 0x000000BCU | ||
9956 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
9957 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
9958 | // .. .. ==> 0XF800617C[10:10] = 0x00000000U | ||
9959 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9960 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
9961 | // .. .. ==> 0XF800617C[19:11] = 0x00000000U | ||
9962 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9963 | // .. .. | ||
9964 | EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU), | ||
9965 | // .. .. reg_phy_wr_data_slave_ratio = 0xbc | ||
9966 | // .. .. ==> 0XF8006180[9:0] = 0x000000BCU | ||
9967 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU | ||
9968 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
9969 | // .. .. ==> 0XF8006180[10:10] = 0x00000000U | ||
9970 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9971 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
9972 | // .. .. ==> 0XF8006180[19:11] = 0x00000000U | ||
9973 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9974 | // .. .. | ||
9975 | EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU), | ||
9976 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
9977 | // .. .. ==> 0XF8006184[9:0] = 0x000000C7U | ||
9978 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
9979 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
9980 | // .. .. ==> 0XF8006184[10:10] = 0x00000000U | ||
9981 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9982 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
9983 | // .. .. ==> 0XF8006184[19:11] = 0x00000000U | ||
9984 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9985 | // .. .. | ||
9986 | EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U), | ||
9987 | // .. .. reg_phy_wr_data_slave_ratio = 0xc7 | ||
9988 | // .. .. ==> 0XF8006188[9:0] = 0x000000C7U | ||
9989 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C7U | ||
9990 | // .. .. reg_phy_wr_data_slave_force = 0x0 | ||
9991 | // .. .. ==> 0XF8006188[10:10] = 0x00000000U | ||
9992 | // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
9993 | // .. .. reg_phy_wr_data_slave_delay = 0x0 | ||
9994 | // .. .. ==> 0XF8006188[19:11] = 0x00000000U | ||
9995 | // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U | ||
9996 | // .. .. | ||
9997 | EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U), | ||
9998 | // .. .. reg_phy_loopback = 0x0 | ||
9999 | // .. .. ==> 0XF8006190[0:0] = 0x00000000U | ||
10000 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10001 | // .. .. reg_phy_bl2 = 0x0 | ||
10002 | // .. .. ==> 0XF8006190[1:1] = 0x00000000U | ||
10003 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10004 | // .. .. reg_phy_at_spd_atpg = 0x0 | ||
10005 | // .. .. ==> 0XF8006190[2:2] = 0x00000000U | ||
10006 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10007 | // .. .. reg_phy_bist_enable = 0x0 | ||
10008 | // .. .. ==> 0XF8006190[3:3] = 0x00000000U | ||
10009 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10010 | // .. .. reg_phy_bist_force_err = 0x0 | ||
10011 | // .. .. ==> 0XF8006190[4:4] = 0x00000000U | ||
10012 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
10013 | // .. .. reg_phy_bist_mode = 0x0 | ||
10014 | // .. .. ==> 0XF8006190[6:5] = 0x00000000U | ||
10015 | // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
10016 | // .. .. reg_phy_invert_clkout = 0x1 | ||
10017 | // .. .. ==> 0XF8006190[7:7] = 0x00000001U | ||
10018 | // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
10019 | // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 | ||
10020 | // .. .. ==> 0XF8006190[8:8] = 0x00000000U | ||
10021 | // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10022 | // .. .. reg_phy_sel_logic = 0x0 | ||
10023 | // .. .. ==> 0XF8006190[9:9] = 0x00000000U | ||
10024 | // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
10025 | // .. .. reg_phy_ctrl_slave_ratio = 0x100 | ||
10026 | // .. .. ==> 0XF8006190[19:10] = 0x00000100U | ||
10027 | // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U | ||
10028 | // .. .. reg_phy_ctrl_slave_force = 0x0 | ||
10029 | // .. .. ==> 0XF8006190[20:20] = 0x00000000U | ||
10030 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
10031 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
10032 | // .. .. ==> 0XF8006190[27:21] = 0x00000000U | ||
10033 | // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U | ||
10034 | // .. .. reg_phy_use_rank0_delays = 0x1 | ||
10035 | // .. .. ==> 0XF8006190[28:28] = 0x00000001U | ||
10036 | // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U | ||
10037 | // .. .. reg_phy_lpddr = 0x0 | ||
10038 | // .. .. ==> 0XF8006190[29:29] = 0x00000000U | ||
10039 | // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
10040 | // .. .. reg_phy_cmd_latency = 0x0 | ||
10041 | // .. .. ==> 0XF8006190[30:30] = 0x00000000U | ||
10042 | // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U | ||
10043 | // .. .. reg_phy_int_lpbk = 0x0 | ||
10044 | // .. .. ==> 0XF8006190[31:31] = 0x00000000U | ||
10045 | // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U | ||
10046 | // .. .. | ||
10047 | EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), | ||
10048 | // .. .. reg_phy_wr_rl_delay = 0x2 | ||
10049 | // .. .. ==> 0XF8006194[4:0] = 0x00000002U | ||
10050 | // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U | ||
10051 | // .. .. reg_phy_rd_rl_delay = 0x4 | ||
10052 | // .. .. ==> 0XF8006194[9:5] = 0x00000004U | ||
10053 | // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U | ||
10054 | // .. .. reg_phy_dll_lock_diff = 0xf | ||
10055 | // .. .. ==> 0XF8006194[13:10] = 0x0000000FU | ||
10056 | // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U | ||
10057 | // .. .. reg_phy_use_wr_level = 0x1 | ||
10058 | // .. .. ==> 0XF8006194[14:14] = 0x00000001U | ||
10059 | // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U | ||
10060 | // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 | ||
10061 | // .. .. ==> 0XF8006194[15:15] = 0x00000001U | ||
10062 | // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U | ||
10063 | // .. .. reg_phy_use_rd_data_eye_level = 0x1 | ||
10064 | // .. .. ==> 0XF8006194[16:16] = 0x00000001U | ||
10065 | // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U | ||
10066 | // .. .. reg_phy_dis_calib_rst = 0x0 | ||
10067 | // .. .. ==> 0XF8006194[17:17] = 0x00000000U | ||
10068 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10069 | // .. .. reg_phy_ctrl_slave_delay = 0x0 | ||
10070 | // .. .. ==> 0XF8006194[19:18] = 0x00000000U | ||
10071 | // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
10072 | // .. .. | ||
10073 | EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), | ||
10074 | // .. .. reg_arb_page_addr_mask = 0x0 | ||
10075 | // .. .. ==> 0XF8006204[31:0] = 0x00000000U | ||
10076 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
10077 | // .. .. | ||
10078 | EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), | ||
10079 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
10080 | // .. .. ==> 0XF8006208[9:0] = 0x000003FFU | ||
10081 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10082 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
10083 | // .. .. ==> 0XF8006208[16:16] = 0x00000000U | ||
10084 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10085 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
10086 | // .. .. ==> 0XF8006208[17:17] = 0x00000000U | ||
10087 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10088 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
10089 | // .. .. ==> 0XF8006208[18:18] = 0x00000000U | ||
10090 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10091 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
10092 | // .. .. ==> 0XF8006208[19:19] = 0x00000001U | ||
10093 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
10094 | // .. .. | ||
10095 | EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), | ||
10096 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
10097 | // .. .. ==> 0XF800620C[9:0] = 0x000003FFU | ||
10098 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10099 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
10100 | // .. .. ==> 0XF800620C[16:16] = 0x00000000U | ||
10101 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10102 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
10103 | // .. .. ==> 0XF800620C[17:17] = 0x00000000U | ||
10104 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10105 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
10106 | // .. .. ==> 0XF800620C[18:18] = 0x00000000U | ||
10107 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10108 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
10109 | // .. .. ==> 0XF800620C[19:19] = 0x00000001U | ||
10110 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
10111 | // .. .. | ||
10112 | EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), | ||
10113 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
10114 | // .. .. ==> 0XF8006210[9:0] = 0x000003FFU | ||
10115 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10116 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
10117 | // .. .. ==> 0XF8006210[16:16] = 0x00000000U | ||
10118 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10119 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
10120 | // .. .. ==> 0XF8006210[17:17] = 0x00000000U | ||
10121 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10122 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
10123 | // .. .. ==> 0XF8006210[18:18] = 0x00000000U | ||
10124 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10125 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
10126 | // .. .. ==> 0XF8006210[19:19] = 0x00000001U | ||
10127 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
10128 | // .. .. | ||
10129 | EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), | ||
10130 | // .. .. reg_arb_pri_wr_portn = 0x3ff | ||
10131 | // .. .. ==> 0XF8006214[9:0] = 0x000003FFU | ||
10132 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10133 | // .. .. reg_arb_disable_aging_wr_portn = 0x0 | ||
10134 | // .. .. ==> 0XF8006214[16:16] = 0x00000000U | ||
10135 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10136 | // .. .. reg_arb_disable_urgent_wr_portn = 0x0 | ||
10137 | // .. .. ==> 0XF8006214[17:17] = 0x00000000U | ||
10138 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10139 | // .. .. reg_arb_dis_page_match_wr_portn = 0x0 | ||
10140 | // .. .. ==> 0XF8006214[18:18] = 0x00000000U | ||
10141 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10142 | // .. .. reg_arb_dis_rmw_portn = 0x1 | ||
10143 | // .. .. ==> 0XF8006214[19:19] = 0x00000001U | ||
10144 | // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
10145 | // .. .. | ||
10146 | EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), | ||
10147 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
10148 | // .. .. ==> 0XF8006218[9:0] = 0x000003FFU | ||
10149 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10150 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
10151 | // .. .. ==> 0XF8006218[16:16] = 0x00000000U | ||
10152 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10153 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
10154 | // .. .. ==> 0XF8006218[17:17] = 0x00000000U | ||
10155 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10156 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
10157 | // .. .. ==> 0XF8006218[18:18] = 0x00000000U | ||
10158 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10159 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
10160 | // .. .. ==> 0XF8006218[19:19] = 0x00000000U | ||
10161 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
10162 | // .. .. | ||
10163 | EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), | ||
10164 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
10165 | // .. .. ==> 0XF800621C[9:0] = 0x000003FFU | ||
10166 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10167 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
10168 | // .. .. ==> 0XF800621C[16:16] = 0x00000000U | ||
10169 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10170 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
10171 | // .. .. ==> 0XF800621C[17:17] = 0x00000000U | ||
10172 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10173 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
10174 | // .. .. ==> 0XF800621C[18:18] = 0x00000000U | ||
10175 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10176 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
10177 | // .. .. ==> 0XF800621C[19:19] = 0x00000000U | ||
10178 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
10179 | // .. .. | ||
10180 | EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), | ||
10181 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
10182 | // .. .. ==> 0XF8006220[9:0] = 0x000003FFU | ||
10183 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10184 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
10185 | // .. .. ==> 0XF8006220[16:16] = 0x00000000U | ||
10186 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10187 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
10188 | // .. .. ==> 0XF8006220[17:17] = 0x00000000U | ||
10189 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10190 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
10191 | // .. .. ==> 0XF8006220[18:18] = 0x00000000U | ||
10192 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10193 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
10194 | // .. .. ==> 0XF8006220[19:19] = 0x00000000U | ||
10195 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
10196 | // .. .. | ||
10197 | EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), | ||
10198 | // .. .. reg_arb_pri_rd_portn = 0x3ff | ||
10199 | // .. .. ==> 0XF8006224[9:0] = 0x000003FFU | ||
10200 | // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU | ||
10201 | // .. .. reg_arb_disable_aging_rd_portn = 0x0 | ||
10202 | // .. .. ==> 0XF8006224[16:16] = 0x00000000U | ||
10203 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10204 | // .. .. reg_arb_disable_urgent_rd_portn = 0x0 | ||
10205 | // .. .. ==> 0XF8006224[17:17] = 0x00000000U | ||
10206 | // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
10207 | // .. .. reg_arb_dis_page_match_rd_portn = 0x0 | ||
10208 | // .. .. ==> 0XF8006224[18:18] = 0x00000000U | ||
10209 | // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U | ||
10210 | // .. .. reg_arb_set_hpr_rd_portn = 0x0 | ||
10211 | // .. .. ==> 0XF8006224[19:19] = 0x00000000U | ||
10212 | // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U | ||
10213 | // .. .. | ||
10214 | EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), | ||
10215 | // .. .. reg_ddrc_lpddr2 = 0x0 | ||
10216 | // .. .. ==> 0XF80062A8[0:0] = 0x00000000U | ||
10217 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10218 | // .. .. reg_ddrc_per_bank_refresh = 0x0 | ||
10219 | // .. .. ==> 0XF80062A8[1:1] = 0x00000000U | ||
10220 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10221 | // .. .. reg_ddrc_derate_enable = 0x0 | ||
10222 | // .. .. ==> 0XF80062A8[2:2] = 0x00000000U | ||
10223 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10224 | // .. .. reg_ddrc_mr4_margin = 0x0 | ||
10225 | // .. .. ==> 0XF80062A8[11:4] = 0x00000000U | ||
10226 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U | ||
10227 | // .. .. | ||
10228 | EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), | ||
10229 | // .. .. reg_ddrc_mr4_read_interval = 0x0 | ||
10230 | // .. .. ==> 0XF80062AC[31:0] = 0x00000000U | ||
10231 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
10232 | // .. .. | ||
10233 | EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), | ||
10234 | // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 | ||
10235 | // .. .. ==> 0XF80062B0[3:0] = 0x00000005U | ||
10236 | // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U | ||
10237 | // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 | ||
10238 | // .. .. ==> 0XF80062B0[11:4] = 0x00000012U | ||
10239 | // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U | ||
10240 | // .. .. reg_ddrc_t_mrw = 0x5 | ||
10241 | // .. .. ==> 0XF80062B0[21:12] = 0x00000005U | ||
10242 | // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U | ||
10243 | // .. .. | ||
10244 | EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), | ||
10245 | // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 | ||
10246 | // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U | ||
10247 | // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U | ||
10248 | // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 | ||
10249 | // .. .. ==> 0XF80062B4[17:8] = 0x00000012U | ||
10250 | // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U | ||
10251 | // .. .. | ||
10252 | EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), | ||
10253 | // .. .. START: POLL ON DCI STATUS | ||
10254 | // .. .. DONE = 1 | ||
10255 | // .. .. ==> 0XF8000B74[13:13] = 0x00000001U | ||
10256 | // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U | ||
10257 | // .. .. | ||
10258 | EMIT_MASKPOLL(0XF8000B74, 0x00002000U), | ||
10259 | // .. .. FINISH: POLL ON DCI STATUS | ||
10260 | // .. .. START: UNLOCK DDR | ||
10261 | // .. .. reg_ddrc_soft_rstb = 0x1 | ||
10262 | // .. .. ==> 0XF8006000[0:0] = 0x00000001U | ||
10263 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
10264 | // .. .. reg_ddrc_powerdown_en = 0x0 | ||
10265 | // .. .. ==> 0XF8006000[1:1] = 0x00000000U | ||
10266 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10267 | // .. .. reg_ddrc_data_bus_width = 0x0 | ||
10268 | // .. .. ==> 0XF8006000[3:2] = 0x00000000U | ||
10269 | // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U | ||
10270 | // .. .. reg_ddrc_burst8_refresh = 0x0 | ||
10271 | // .. .. ==> 0XF8006000[6:4] = 0x00000000U | ||
10272 | // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U | ||
10273 | // .. .. reg_ddrc_rdwr_idle_gap = 1 | ||
10274 | // .. .. ==> 0XF8006000[13:7] = 0x00000001U | ||
10275 | // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U | ||
10276 | // .. .. reg_ddrc_dis_rd_bypass = 0x0 | ||
10277 | // .. .. ==> 0XF8006000[14:14] = 0x00000000U | ||
10278 | // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
10279 | // .. .. reg_ddrc_dis_act_bypass = 0x0 | ||
10280 | // .. .. ==> 0XF8006000[15:15] = 0x00000000U | ||
10281 | // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U | ||
10282 | // .. .. reg_ddrc_dis_auto_refresh = 0x0 | ||
10283 | // .. .. ==> 0XF8006000[16:16] = 0x00000000U | ||
10284 | // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
10285 | // .. .. | ||
10286 | EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), | ||
10287 | // .. .. FINISH: UNLOCK DDR | ||
10288 | // .. .. START: CHECK DDR STATUS | ||
10289 | // .. .. ddrc_reg_operating_mode = 1 | ||
10290 | // .. .. ==> 0XF8006054[2:0] = 0x00000001U | ||
10291 | // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U | ||
10292 | // .. .. | ||
10293 | EMIT_MASKPOLL(0XF8006054, 0x00000007U), | ||
10294 | // .. .. FINISH: CHECK DDR STATUS | ||
10295 | // .. FINISH: DDR INITIALIZATION | ||
10296 | // FINISH: top | ||
10297 | // | ||
10298 | EMIT_EXIT(), | ||
10299 | |||
10300 | // | ||
10301 | }; | ||
10302 | |||
10303 | unsigned long ps7_mio_init_data_1_0[] = { | ||
10304 | // START: top | ||
10305 | // .. START: SLCR SETTINGS | ||
10306 | // .. UNLOCK_KEY = 0XDF0D | ||
10307 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
10308 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
10309 | // .. | ||
10310 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
10311 | // .. FINISH: SLCR SETTINGS | ||
10312 | // .. START: OCM REMAPPING | ||
10313 | // .. FINISH: OCM REMAPPING | ||
10314 | // .. START: DDRIOB SETTINGS | ||
10315 | // .. INP_POWER = 0x0 | ||
10316 | // .. ==> 0XF8000B40[0:0] = 0x00000000U | ||
10317 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10318 | // .. INP_TYPE = 0x0 | ||
10319 | // .. ==> 0XF8000B40[2:1] = 0x00000000U | ||
10320 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
10321 | // .. DCI_UPDATE = 0x0 | ||
10322 | // .. ==> 0XF8000B40[3:3] = 0x00000000U | ||
10323 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10324 | // .. TERM_EN = 0x0 | ||
10325 | // .. ==> 0XF8000B40[4:4] = 0x00000000U | ||
10326 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
10327 | // .. DCR_TYPE = 0x0 | ||
10328 | // .. ==> 0XF8000B40[6:5] = 0x00000000U | ||
10329 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
10330 | // .. IBUF_DISABLE_MODE = 0x0 | ||
10331 | // .. ==> 0XF8000B40[7:7] = 0x00000000U | ||
10332 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10333 | // .. TERM_DISABLE_MODE = 0x0 | ||
10334 | // .. ==> 0XF8000B40[8:8] = 0x00000000U | ||
10335 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10336 | // .. OUTPUT_EN = 0x3 | ||
10337 | // .. ==> 0XF8000B40[10:9] = 0x00000003U | ||
10338 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10339 | // .. PULLUP_EN = 0x0 | ||
10340 | // .. ==> 0XF8000B40[11:11] = 0x00000000U | ||
10341 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10342 | // .. | ||
10343 | EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), | ||
10344 | // .. INP_POWER = 0x0 | ||
10345 | // .. ==> 0XF8000B44[0:0] = 0x00000000U | ||
10346 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10347 | // .. INP_TYPE = 0x0 | ||
10348 | // .. ==> 0XF8000B44[2:1] = 0x00000000U | ||
10349 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
10350 | // .. DCI_UPDATE = 0x0 | ||
10351 | // .. ==> 0XF8000B44[3:3] = 0x00000000U | ||
10352 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10353 | // .. TERM_EN = 0x0 | ||
10354 | // .. ==> 0XF8000B44[4:4] = 0x00000000U | ||
10355 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
10356 | // .. DCR_TYPE = 0x0 | ||
10357 | // .. ==> 0XF8000B44[6:5] = 0x00000000U | ||
10358 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
10359 | // .. IBUF_DISABLE_MODE = 0x0 | ||
10360 | // .. ==> 0XF8000B44[7:7] = 0x00000000U | ||
10361 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10362 | // .. TERM_DISABLE_MODE = 0x0 | ||
10363 | // .. ==> 0XF8000B44[8:8] = 0x00000000U | ||
10364 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10365 | // .. OUTPUT_EN = 0x3 | ||
10366 | // .. ==> 0XF8000B44[10:9] = 0x00000003U | ||
10367 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10368 | // .. PULLUP_EN = 0x0 | ||
10369 | // .. ==> 0XF8000B44[11:11] = 0x00000000U | ||
10370 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10371 | // .. | ||
10372 | EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), | ||
10373 | // .. INP_POWER = 0x0 | ||
10374 | // .. ==> 0XF8000B48[0:0] = 0x00000000U | ||
10375 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10376 | // .. INP_TYPE = 0x1 | ||
10377 | // .. ==> 0XF8000B48[2:1] = 0x00000001U | ||
10378 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
10379 | // .. DCI_UPDATE = 0x0 | ||
10380 | // .. ==> 0XF8000B48[3:3] = 0x00000000U | ||
10381 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10382 | // .. TERM_EN = 0x1 | ||
10383 | // .. ==> 0XF8000B48[4:4] = 0x00000001U | ||
10384 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
10385 | // .. DCR_TYPE = 0x3 | ||
10386 | // .. ==> 0XF8000B48[6:5] = 0x00000003U | ||
10387 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
10388 | // .. IBUF_DISABLE_MODE = 0 | ||
10389 | // .. ==> 0XF8000B48[7:7] = 0x00000000U | ||
10390 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10391 | // .. TERM_DISABLE_MODE = 0 | ||
10392 | // .. ==> 0XF8000B48[8:8] = 0x00000000U | ||
10393 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10394 | // .. OUTPUT_EN = 0x3 | ||
10395 | // .. ==> 0XF8000B48[10:9] = 0x00000003U | ||
10396 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10397 | // .. PULLUP_EN = 0x0 | ||
10398 | // .. ==> 0XF8000B48[11:11] = 0x00000000U | ||
10399 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10400 | // .. | ||
10401 | EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), | ||
10402 | // .. INP_POWER = 0x0 | ||
10403 | // .. ==> 0XF8000B4C[0:0] = 0x00000000U | ||
10404 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10405 | // .. INP_TYPE = 0x1 | ||
10406 | // .. ==> 0XF8000B4C[2:1] = 0x00000001U | ||
10407 | // .. ==> MASK : 0x00000006U VAL : 0x00000002U | ||
10408 | // .. DCI_UPDATE = 0x0 | ||
10409 | // .. ==> 0XF8000B4C[3:3] = 0x00000000U | ||
10410 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10411 | // .. TERM_EN = 0x1 | ||
10412 | // .. ==> 0XF8000B4C[4:4] = 0x00000001U | ||
10413 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
10414 | // .. DCR_TYPE = 0x3 | ||
10415 | // .. ==> 0XF8000B4C[6:5] = 0x00000003U | ||
10416 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
10417 | // .. IBUF_DISABLE_MODE = 0 | ||
10418 | // .. ==> 0XF8000B4C[7:7] = 0x00000000U | ||
10419 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10420 | // .. TERM_DISABLE_MODE = 0 | ||
10421 | // .. ==> 0XF8000B4C[8:8] = 0x00000000U | ||
10422 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10423 | // .. OUTPUT_EN = 0x3 | ||
10424 | // .. ==> 0XF8000B4C[10:9] = 0x00000003U | ||
10425 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10426 | // .. PULLUP_EN = 0x0 | ||
10427 | // .. ==> 0XF8000B4C[11:11] = 0x00000000U | ||
10428 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10429 | // .. | ||
10430 | EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), | ||
10431 | // .. INP_POWER = 0x0 | ||
10432 | // .. ==> 0XF8000B50[0:0] = 0x00000000U | ||
10433 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10434 | // .. INP_TYPE = 0x2 | ||
10435 | // .. ==> 0XF8000B50[2:1] = 0x00000002U | ||
10436 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
10437 | // .. DCI_UPDATE = 0x0 | ||
10438 | // .. ==> 0XF8000B50[3:3] = 0x00000000U | ||
10439 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10440 | // .. TERM_EN = 0x1 | ||
10441 | // .. ==> 0XF8000B50[4:4] = 0x00000001U | ||
10442 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
10443 | // .. DCR_TYPE = 0x3 | ||
10444 | // .. ==> 0XF8000B50[6:5] = 0x00000003U | ||
10445 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
10446 | // .. IBUF_DISABLE_MODE = 0 | ||
10447 | // .. ==> 0XF8000B50[7:7] = 0x00000000U | ||
10448 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10449 | // .. TERM_DISABLE_MODE = 0 | ||
10450 | // .. ==> 0XF8000B50[8:8] = 0x00000000U | ||
10451 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10452 | // .. OUTPUT_EN = 0x3 | ||
10453 | // .. ==> 0XF8000B50[10:9] = 0x00000003U | ||
10454 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10455 | // .. PULLUP_EN = 0x0 | ||
10456 | // .. ==> 0XF8000B50[11:11] = 0x00000000U | ||
10457 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10458 | // .. | ||
10459 | EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), | ||
10460 | // .. INP_POWER = 0x0 | ||
10461 | // .. ==> 0XF8000B54[0:0] = 0x00000000U | ||
10462 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10463 | // .. INP_TYPE = 0x2 | ||
10464 | // .. ==> 0XF8000B54[2:1] = 0x00000002U | ||
10465 | // .. ==> MASK : 0x00000006U VAL : 0x00000004U | ||
10466 | // .. DCI_UPDATE = 0x0 | ||
10467 | // .. ==> 0XF8000B54[3:3] = 0x00000000U | ||
10468 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10469 | // .. TERM_EN = 0x1 | ||
10470 | // .. ==> 0XF8000B54[4:4] = 0x00000001U | ||
10471 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
10472 | // .. DCR_TYPE = 0x3 | ||
10473 | // .. ==> 0XF8000B54[6:5] = 0x00000003U | ||
10474 | // .. ==> MASK : 0x00000060U VAL : 0x00000060U | ||
10475 | // .. IBUF_DISABLE_MODE = 0 | ||
10476 | // .. ==> 0XF8000B54[7:7] = 0x00000000U | ||
10477 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10478 | // .. TERM_DISABLE_MODE = 0 | ||
10479 | // .. ==> 0XF8000B54[8:8] = 0x00000000U | ||
10480 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10481 | // .. OUTPUT_EN = 0x3 | ||
10482 | // .. ==> 0XF8000B54[10:9] = 0x00000003U | ||
10483 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10484 | // .. PULLUP_EN = 0x0 | ||
10485 | // .. ==> 0XF8000B54[11:11] = 0x00000000U | ||
10486 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10487 | // .. | ||
10488 | EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), | ||
10489 | // .. INP_POWER = 0x0 | ||
10490 | // .. ==> 0XF8000B58[0:0] = 0x00000000U | ||
10491 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10492 | // .. INP_TYPE = 0x0 | ||
10493 | // .. ==> 0XF8000B58[2:1] = 0x00000000U | ||
10494 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
10495 | // .. DCI_UPDATE = 0x0 | ||
10496 | // .. ==> 0XF8000B58[3:3] = 0x00000000U | ||
10497 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10498 | // .. TERM_EN = 0x0 | ||
10499 | // .. ==> 0XF8000B58[4:4] = 0x00000000U | ||
10500 | // .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
10501 | // .. DCR_TYPE = 0x0 | ||
10502 | // .. ==> 0XF8000B58[6:5] = 0x00000000U | ||
10503 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
10504 | // .. IBUF_DISABLE_MODE = 0x0 | ||
10505 | // .. ==> 0XF8000B58[7:7] = 0x00000000U | ||
10506 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
10507 | // .. TERM_DISABLE_MODE = 0x0 | ||
10508 | // .. ==> 0XF8000B58[8:8] = 0x00000000U | ||
10509 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10510 | // .. OUTPUT_EN = 0x3 | ||
10511 | // .. ==> 0XF8000B58[10:9] = 0x00000003U | ||
10512 | // .. ==> MASK : 0x00000600U VAL : 0x00000600U | ||
10513 | // .. PULLUP_EN = 0x0 | ||
10514 | // .. ==> 0XF8000B58[11:11] = 0x00000000U | ||
10515 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
10516 | // .. | ||
10517 | EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), | ||
10518 | // .. DRIVE_P = 0x1c | ||
10519 | // .. ==> 0XF8000B5C[6:0] = 0x0000001CU | ||
10520 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
10521 | // .. DRIVE_N = 0xc | ||
10522 | // .. ==> 0XF8000B5C[13:7] = 0x0000000CU | ||
10523 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
10524 | // .. SLEW_P = 0x3 | ||
10525 | // .. ==> 0XF8000B5C[18:14] = 0x00000003U | ||
10526 | // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U | ||
10527 | // .. SLEW_N = 0x3 | ||
10528 | // .. ==> 0XF8000B5C[23:19] = 0x00000003U | ||
10529 | // .. ==> MASK : 0x00F80000U VAL : 0x00180000U | ||
10530 | // .. GTL = 0x0 | ||
10531 | // .. ==> 0XF8000B5C[26:24] = 0x00000000U | ||
10532 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
10533 | // .. RTERM = 0x0 | ||
10534 | // .. ==> 0XF8000B5C[31:27] = 0x00000000U | ||
10535 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
10536 | // .. | ||
10537 | EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), | ||
10538 | // .. DRIVE_P = 0x1c | ||
10539 | // .. ==> 0XF8000B60[6:0] = 0x0000001CU | ||
10540 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
10541 | // .. DRIVE_N = 0xc | ||
10542 | // .. ==> 0XF8000B60[13:7] = 0x0000000CU | ||
10543 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
10544 | // .. SLEW_P = 0x6 | ||
10545 | // .. ==> 0XF8000B60[18:14] = 0x00000006U | ||
10546 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
10547 | // .. SLEW_N = 0x1f | ||
10548 | // .. ==> 0XF8000B60[23:19] = 0x0000001FU | ||
10549 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
10550 | // .. GTL = 0x0 | ||
10551 | // .. ==> 0XF8000B60[26:24] = 0x00000000U | ||
10552 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
10553 | // .. RTERM = 0x0 | ||
10554 | // .. ==> 0XF8000B60[31:27] = 0x00000000U | ||
10555 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
10556 | // .. | ||
10557 | EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), | ||
10558 | // .. DRIVE_P = 0x1c | ||
10559 | // .. ==> 0XF8000B64[6:0] = 0x0000001CU | ||
10560 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
10561 | // .. DRIVE_N = 0xc | ||
10562 | // .. ==> 0XF8000B64[13:7] = 0x0000000CU | ||
10563 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
10564 | // .. SLEW_P = 0x6 | ||
10565 | // .. ==> 0XF8000B64[18:14] = 0x00000006U | ||
10566 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
10567 | // .. SLEW_N = 0x1f | ||
10568 | // .. ==> 0XF8000B64[23:19] = 0x0000001FU | ||
10569 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
10570 | // .. GTL = 0x0 | ||
10571 | // .. ==> 0XF8000B64[26:24] = 0x00000000U | ||
10572 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
10573 | // .. RTERM = 0x0 | ||
10574 | // .. ==> 0XF8000B64[31:27] = 0x00000000U | ||
10575 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
10576 | // .. | ||
10577 | EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), | ||
10578 | // .. DRIVE_P = 0x1c | ||
10579 | // .. ==> 0XF8000B68[6:0] = 0x0000001CU | ||
10580 | // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU | ||
10581 | // .. DRIVE_N = 0xc | ||
10582 | // .. ==> 0XF8000B68[13:7] = 0x0000000CU | ||
10583 | // .. ==> MASK : 0x00003F80U VAL : 0x00000600U | ||
10584 | // .. SLEW_P = 0x6 | ||
10585 | // .. ==> 0XF8000B68[18:14] = 0x00000006U | ||
10586 | // .. ==> MASK : 0x0007C000U VAL : 0x00018000U | ||
10587 | // .. SLEW_N = 0x1f | ||
10588 | // .. ==> 0XF8000B68[23:19] = 0x0000001FU | ||
10589 | // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U | ||
10590 | // .. GTL = 0x0 | ||
10591 | // .. ==> 0XF8000B68[26:24] = 0x00000000U | ||
10592 | // .. ==> MASK : 0x07000000U VAL : 0x00000000U | ||
10593 | // .. RTERM = 0x0 | ||
10594 | // .. ==> 0XF8000B68[31:27] = 0x00000000U | ||
10595 | // .. ==> MASK : 0xF8000000U VAL : 0x00000000U | ||
10596 | // .. | ||
10597 | EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), | ||
10598 | // .. VREF_INT_EN = 0x1 | ||
10599 | // .. ==> 0XF8000B6C[0:0] = 0x00000001U | ||
10600 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
10601 | // .. VREF_SEL = 0x4 | ||
10602 | // .. ==> 0XF8000B6C[4:1] = 0x00000004U | ||
10603 | // .. ==> MASK : 0x0000001EU VAL : 0x00000008U | ||
10604 | // .. VREF_EXT_EN = 0x0 | ||
10605 | // .. ==> 0XF8000B6C[6:5] = 0x00000000U | ||
10606 | // .. ==> MASK : 0x00000060U VAL : 0x00000000U | ||
10607 | // .. VREF_PULLUP_EN = 0x0 | ||
10608 | // .. ==> 0XF8000B6C[8:7] = 0x00000000U | ||
10609 | // .. ==> MASK : 0x00000180U VAL : 0x00000000U | ||
10610 | // .. REFIO_EN = 0x1 | ||
10611 | // .. ==> 0XF8000B6C[9:9] = 0x00000001U | ||
10612 | // .. ==> MASK : 0x00000200U VAL : 0x00000200U | ||
10613 | // .. REFIO_PULLUP_EN = 0x0 | ||
10614 | // .. ==> 0XF8000B6C[12:12] = 0x00000000U | ||
10615 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10616 | // .. DRST_B_PULLUP_EN = 0x0 | ||
10617 | // .. ==> 0XF8000B6C[13:13] = 0x00000000U | ||
10618 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10619 | // .. CKE_PULLUP_EN = 0x0 | ||
10620 | // .. ==> 0XF8000B6C[14:14] = 0x00000000U | ||
10621 | // .. ==> MASK : 0x00004000U VAL : 0x00000000U | ||
10622 | // .. | ||
10623 | EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), | ||
10624 | // .. .. START: ASSERT RESET | ||
10625 | // .. .. RESET = 1 | ||
10626 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
10627 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
10628 | // .. .. VRN_OUT = 0x1 | ||
10629 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
10630 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
10631 | // .. .. | ||
10632 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), | ||
10633 | // .. .. FINISH: ASSERT RESET | ||
10634 | // .. .. START: DEASSERT RESET | ||
10635 | // .. .. RESET = 0 | ||
10636 | // .. .. ==> 0XF8000B70[0:0] = 0x00000000U | ||
10637 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10638 | // .. .. VRN_OUT = 0x1 | ||
10639 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
10640 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
10641 | // .. .. | ||
10642 | EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), | ||
10643 | // .. .. FINISH: DEASSERT RESET | ||
10644 | // .. .. RESET = 0x1 | ||
10645 | // .. .. ==> 0XF8000B70[0:0] = 0x00000001U | ||
10646 | // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
10647 | // .. .. ENABLE = 0x1 | ||
10648 | // .. .. ==> 0XF8000B70[1:1] = 0x00000001U | ||
10649 | // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10650 | // .. .. VRP_TRI = 0x0 | ||
10651 | // .. .. ==> 0XF8000B70[2:2] = 0x00000000U | ||
10652 | // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10653 | // .. .. VRN_TRI = 0x0 | ||
10654 | // .. .. ==> 0XF8000B70[3:3] = 0x00000000U | ||
10655 | // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
10656 | // .. .. VRP_OUT = 0x0 | ||
10657 | // .. .. ==> 0XF8000B70[4:4] = 0x00000000U | ||
10658 | // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U | ||
10659 | // .. .. VRN_OUT = 0x1 | ||
10660 | // .. .. ==> 0XF8000B70[5:5] = 0x00000001U | ||
10661 | // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U | ||
10662 | // .. .. NREF_OPT1 = 0x0 | ||
10663 | // .. .. ==> 0XF8000B70[7:6] = 0x00000000U | ||
10664 | // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
10665 | // .. .. NREF_OPT2 = 0x0 | ||
10666 | // .. .. ==> 0XF8000B70[10:8] = 0x00000000U | ||
10667 | // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U | ||
10668 | // .. .. NREF_OPT4 = 0x1 | ||
10669 | // .. .. ==> 0XF8000B70[13:11] = 0x00000001U | ||
10670 | // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U | ||
10671 | // .. .. PREF_OPT1 = 0x0 | ||
10672 | // .. .. ==> 0XF8000B70[16:14] = 0x00000000U | ||
10673 | // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U | ||
10674 | // .. .. PREF_OPT2 = 0x0 | ||
10675 | // .. .. ==> 0XF8000B70[19:17] = 0x00000000U | ||
10676 | // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U | ||
10677 | // .. .. UPDATE_CONTROL = 0x0 | ||
10678 | // .. .. ==> 0XF8000B70[20:20] = 0x00000000U | ||
10679 | // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
10680 | // .. .. INIT_COMPLETE = 0x0 | ||
10681 | // .. .. ==> 0XF8000B70[21:21] = 0x00000000U | ||
10682 | // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
10683 | // .. .. TST_CLK = 0x0 | ||
10684 | // .. .. ==> 0XF8000B70[22:22] = 0x00000000U | ||
10685 | // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
10686 | // .. .. TST_HLN = 0x0 | ||
10687 | // .. .. ==> 0XF8000B70[23:23] = 0x00000000U | ||
10688 | // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
10689 | // .. .. TST_HLP = 0x0 | ||
10690 | // .. .. ==> 0XF8000B70[24:24] = 0x00000000U | ||
10691 | // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
10692 | // .. .. TST_RST = 0x0 | ||
10693 | // .. .. ==> 0XF8000B70[25:25] = 0x00000000U | ||
10694 | // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U | ||
10695 | // .. .. INT_DCI_EN = 0x0 | ||
10696 | // .. .. ==> 0XF8000B70[26:26] = 0x00000000U | ||
10697 | // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U | ||
10698 | // .. .. | ||
10699 | EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), | ||
10700 | // .. FINISH: DDRIOB SETTINGS | ||
10701 | // .. START: MIO PROGRAMMING | ||
10702 | // .. TRI_ENABLE = 0 | ||
10703 | // .. ==> 0XF8000700[0:0] = 0x00000000U | ||
10704 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10705 | // .. L0_SEL = 0 | ||
10706 | // .. ==> 0XF8000700[1:1] = 0x00000000U | ||
10707 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10708 | // .. L1_SEL = 0 | ||
10709 | // .. ==> 0XF8000700[2:2] = 0x00000000U | ||
10710 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10711 | // .. L2_SEL = 0 | ||
10712 | // .. ==> 0XF8000700[4:3] = 0x00000000U | ||
10713 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10714 | // .. L3_SEL = 0 | ||
10715 | // .. ==> 0XF8000700[7:5] = 0x00000000U | ||
10716 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10717 | // .. Speed = 0 | ||
10718 | // .. ==> 0XF8000700[8:8] = 0x00000000U | ||
10719 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10720 | // .. IO_Type = 3 | ||
10721 | // .. ==> 0XF8000700[11:9] = 0x00000003U | ||
10722 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10723 | // .. PULLUP = 0 | ||
10724 | // .. ==> 0XF8000700[12:12] = 0x00000000U | ||
10725 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10726 | // .. DisableRcvr = 0 | ||
10727 | // .. ==> 0XF8000700[13:13] = 0x00000000U | ||
10728 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10729 | // .. | ||
10730 | EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U), | ||
10731 | // .. TRI_ENABLE = 0 | ||
10732 | // .. ==> 0XF8000704[0:0] = 0x00000000U | ||
10733 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10734 | // .. L0_SEL = 1 | ||
10735 | // .. ==> 0XF8000704[1:1] = 0x00000001U | ||
10736 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10737 | // .. L1_SEL = 0 | ||
10738 | // .. ==> 0XF8000704[2:2] = 0x00000000U | ||
10739 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10740 | // .. L2_SEL = 0 | ||
10741 | // .. ==> 0XF8000704[4:3] = 0x00000000U | ||
10742 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10743 | // .. L3_SEL = 0 | ||
10744 | // .. ==> 0XF8000704[7:5] = 0x00000000U | ||
10745 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10746 | // .. Speed = 0 | ||
10747 | // .. ==> 0XF8000704[8:8] = 0x00000000U | ||
10748 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10749 | // .. IO_Type = 3 | ||
10750 | // .. ==> 0XF8000704[11:9] = 0x00000003U | ||
10751 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10752 | // .. PULLUP = 0 | ||
10753 | // .. ==> 0XF8000704[12:12] = 0x00000000U | ||
10754 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10755 | // .. DisableRcvr = 0 | ||
10756 | // .. ==> 0XF8000704[13:13] = 0x00000000U | ||
10757 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10758 | // .. | ||
10759 | EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U), | ||
10760 | // .. TRI_ENABLE = 0 | ||
10761 | // .. ==> 0XF8000708[0:0] = 0x00000000U | ||
10762 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10763 | // .. L0_SEL = 1 | ||
10764 | // .. ==> 0XF8000708[1:1] = 0x00000001U | ||
10765 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10766 | // .. L1_SEL = 0 | ||
10767 | // .. ==> 0XF8000708[2:2] = 0x00000000U | ||
10768 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10769 | // .. L2_SEL = 0 | ||
10770 | // .. ==> 0XF8000708[4:3] = 0x00000000U | ||
10771 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10772 | // .. L3_SEL = 0 | ||
10773 | // .. ==> 0XF8000708[7:5] = 0x00000000U | ||
10774 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10775 | // .. Speed = 0 | ||
10776 | // .. ==> 0XF8000708[8:8] = 0x00000000U | ||
10777 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10778 | // .. IO_Type = 3 | ||
10779 | // .. ==> 0XF8000708[11:9] = 0x00000003U | ||
10780 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10781 | // .. PULLUP = 0 | ||
10782 | // .. ==> 0XF8000708[12:12] = 0x00000000U | ||
10783 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10784 | // .. DisableRcvr = 0 | ||
10785 | // .. ==> 0XF8000708[13:13] = 0x00000000U | ||
10786 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10787 | // .. | ||
10788 | EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), | ||
10789 | // .. TRI_ENABLE = 0 | ||
10790 | // .. ==> 0XF800070C[0:0] = 0x00000000U | ||
10791 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10792 | // .. L0_SEL = 1 | ||
10793 | // .. ==> 0XF800070C[1:1] = 0x00000001U | ||
10794 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10795 | // .. L1_SEL = 0 | ||
10796 | // .. ==> 0XF800070C[2:2] = 0x00000000U | ||
10797 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10798 | // .. L2_SEL = 0 | ||
10799 | // .. ==> 0XF800070C[4:3] = 0x00000000U | ||
10800 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10801 | // .. L3_SEL = 0 | ||
10802 | // .. ==> 0XF800070C[7:5] = 0x00000000U | ||
10803 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10804 | // .. Speed = 0 | ||
10805 | // .. ==> 0XF800070C[8:8] = 0x00000000U | ||
10806 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10807 | // .. IO_Type = 3 | ||
10808 | // .. ==> 0XF800070C[11:9] = 0x00000003U | ||
10809 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10810 | // .. PULLUP = 0 | ||
10811 | // .. ==> 0XF800070C[12:12] = 0x00000000U | ||
10812 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10813 | // .. DisableRcvr = 0 | ||
10814 | // .. ==> 0XF800070C[13:13] = 0x00000000U | ||
10815 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10816 | // .. | ||
10817 | EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), | ||
10818 | // .. TRI_ENABLE = 0 | ||
10819 | // .. ==> 0XF8000710[0:0] = 0x00000000U | ||
10820 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10821 | // .. L0_SEL = 1 | ||
10822 | // .. ==> 0XF8000710[1:1] = 0x00000001U | ||
10823 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10824 | // .. L1_SEL = 0 | ||
10825 | // .. ==> 0XF8000710[2:2] = 0x00000000U | ||
10826 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10827 | // .. L2_SEL = 0 | ||
10828 | // .. ==> 0XF8000710[4:3] = 0x00000000U | ||
10829 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10830 | // .. L3_SEL = 0 | ||
10831 | // .. ==> 0XF8000710[7:5] = 0x00000000U | ||
10832 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10833 | // .. Speed = 0 | ||
10834 | // .. ==> 0XF8000710[8:8] = 0x00000000U | ||
10835 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10836 | // .. IO_Type = 3 | ||
10837 | // .. ==> 0XF8000710[11:9] = 0x00000003U | ||
10838 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10839 | // .. PULLUP = 0 | ||
10840 | // .. ==> 0XF8000710[12:12] = 0x00000000U | ||
10841 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10842 | // .. DisableRcvr = 0 | ||
10843 | // .. ==> 0XF8000710[13:13] = 0x00000000U | ||
10844 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10845 | // .. | ||
10846 | EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), | ||
10847 | // .. TRI_ENABLE = 0 | ||
10848 | // .. ==> 0XF8000714[0:0] = 0x00000000U | ||
10849 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10850 | // .. L0_SEL = 1 | ||
10851 | // .. ==> 0XF8000714[1:1] = 0x00000001U | ||
10852 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10853 | // .. L1_SEL = 0 | ||
10854 | // .. ==> 0XF8000714[2:2] = 0x00000000U | ||
10855 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10856 | // .. L2_SEL = 0 | ||
10857 | // .. ==> 0XF8000714[4:3] = 0x00000000U | ||
10858 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10859 | // .. L3_SEL = 0 | ||
10860 | // .. ==> 0XF8000714[7:5] = 0x00000000U | ||
10861 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10862 | // .. Speed = 0 | ||
10863 | // .. ==> 0XF8000714[8:8] = 0x00000000U | ||
10864 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10865 | // .. IO_Type = 3 | ||
10866 | // .. ==> 0XF8000714[11:9] = 0x00000003U | ||
10867 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10868 | // .. PULLUP = 0 | ||
10869 | // .. ==> 0XF8000714[12:12] = 0x00000000U | ||
10870 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10871 | // .. DisableRcvr = 0 | ||
10872 | // .. ==> 0XF8000714[13:13] = 0x00000000U | ||
10873 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10874 | // .. | ||
10875 | EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), | ||
10876 | // .. TRI_ENABLE = 0 | ||
10877 | // .. ==> 0XF8000718[0:0] = 0x00000000U | ||
10878 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10879 | // .. L0_SEL = 1 | ||
10880 | // .. ==> 0XF8000718[1:1] = 0x00000001U | ||
10881 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10882 | // .. L1_SEL = 0 | ||
10883 | // .. ==> 0XF8000718[2:2] = 0x00000000U | ||
10884 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10885 | // .. L2_SEL = 0 | ||
10886 | // .. ==> 0XF8000718[4:3] = 0x00000000U | ||
10887 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10888 | // .. L3_SEL = 0 | ||
10889 | // .. ==> 0XF8000718[7:5] = 0x00000000U | ||
10890 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10891 | // .. Speed = 0 | ||
10892 | // .. ==> 0XF8000718[8:8] = 0x00000000U | ||
10893 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10894 | // .. IO_Type = 3 | ||
10895 | // .. ==> 0XF8000718[11:9] = 0x00000003U | ||
10896 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10897 | // .. PULLUP = 0 | ||
10898 | // .. ==> 0XF8000718[12:12] = 0x00000000U | ||
10899 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10900 | // .. DisableRcvr = 0 | ||
10901 | // .. ==> 0XF8000718[13:13] = 0x00000000U | ||
10902 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10903 | // .. | ||
10904 | EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), | ||
10905 | // .. TRI_ENABLE = 0 | ||
10906 | // .. ==> 0XF800071C[0:0] = 0x00000000U | ||
10907 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10908 | // .. L0_SEL = 0 | ||
10909 | // .. ==> 0XF800071C[1:1] = 0x00000000U | ||
10910 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10911 | // .. L1_SEL = 0 | ||
10912 | // .. ==> 0XF800071C[2:2] = 0x00000000U | ||
10913 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10914 | // .. L2_SEL = 0 | ||
10915 | // .. ==> 0XF800071C[4:3] = 0x00000000U | ||
10916 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10917 | // .. L3_SEL = 0 | ||
10918 | // .. ==> 0XF800071C[7:5] = 0x00000000U | ||
10919 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10920 | // .. Speed = 0 | ||
10921 | // .. ==> 0XF800071C[8:8] = 0x00000000U | ||
10922 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10923 | // .. IO_Type = 3 | ||
10924 | // .. ==> 0XF800071C[11:9] = 0x00000003U | ||
10925 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10926 | // .. PULLUP = 0 | ||
10927 | // .. ==> 0XF800071C[12:12] = 0x00000000U | ||
10928 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10929 | // .. DisableRcvr = 0 | ||
10930 | // .. ==> 0XF800071C[13:13] = 0x00000000U | ||
10931 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10932 | // .. | ||
10933 | EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), | ||
10934 | // .. TRI_ENABLE = 0 | ||
10935 | // .. ==> 0XF8000720[0:0] = 0x00000000U | ||
10936 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10937 | // .. L0_SEL = 1 | ||
10938 | // .. ==> 0XF8000720[1:1] = 0x00000001U | ||
10939 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
10940 | // .. L1_SEL = 0 | ||
10941 | // .. ==> 0XF8000720[2:2] = 0x00000000U | ||
10942 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10943 | // .. L2_SEL = 0 | ||
10944 | // .. ==> 0XF8000720[4:3] = 0x00000000U | ||
10945 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10946 | // .. L3_SEL = 0 | ||
10947 | // .. ==> 0XF8000720[7:5] = 0x00000000U | ||
10948 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10949 | // .. Speed = 0 | ||
10950 | // .. ==> 0XF8000720[8:8] = 0x00000000U | ||
10951 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10952 | // .. IO_Type = 3 | ||
10953 | // .. ==> 0XF8000720[11:9] = 0x00000003U | ||
10954 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10955 | // .. PULLUP = 0 | ||
10956 | // .. ==> 0XF8000720[12:12] = 0x00000000U | ||
10957 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10958 | // .. DisableRcvr = 0 | ||
10959 | // .. ==> 0XF8000720[13:13] = 0x00000000U | ||
10960 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10961 | // .. | ||
10962 | EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U), | ||
10963 | // .. TRI_ENABLE = 0 | ||
10964 | // .. ==> 0XF8000724[0:0] = 0x00000000U | ||
10965 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10966 | // .. L0_SEL = 0 | ||
10967 | // .. ==> 0XF8000724[1:1] = 0x00000000U | ||
10968 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10969 | // .. L1_SEL = 0 | ||
10970 | // .. ==> 0XF8000724[2:2] = 0x00000000U | ||
10971 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
10972 | // .. L2_SEL = 0 | ||
10973 | // .. ==> 0XF8000724[4:3] = 0x00000000U | ||
10974 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
10975 | // .. L3_SEL = 0 | ||
10976 | // .. ==> 0XF8000724[7:5] = 0x00000000U | ||
10977 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
10978 | // .. Speed = 0 | ||
10979 | // .. ==> 0XF8000724[8:8] = 0x00000000U | ||
10980 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
10981 | // .. IO_Type = 3 | ||
10982 | // .. ==> 0XF8000724[11:9] = 0x00000003U | ||
10983 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
10984 | // .. PULLUP = 0 | ||
10985 | // .. ==> 0XF8000724[12:12] = 0x00000000U | ||
10986 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
10987 | // .. DisableRcvr = 0 | ||
10988 | // .. ==> 0XF8000724[13:13] = 0x00000000U | ||
10989 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
10990 | // .. | ||
10991 | EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U), | ||
10992 | // .. TRI_ENABLE = 0 | ||
10993 | // .. ==> 0XF8000728[0:0] = 0x00000000U | ||
10994 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
10995 | // .. L0_SEL = 0 | ||
10996 | // .. ==> 0XF8000728[1:1] = 0x00000000U | ||
10997 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
10998 | // .. L1_SEL = 0 | ||
10999 | // .. ==> 0XF8000728[2:2] = 0x00000000U | ||
11000 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11001 | // .. L2_SEL = 0 | ||
11002 | // .. ==> 0XF8000728[4:3] = 0x00000000U | ||
11003 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11004 | // .. L3_SEL = 4 | ||
11005 | // .. ==> 0XF8000728[7:5] = 0x00000004U | ||
11006 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11007 | // .. Speed = 0 | ||
11008 | // .. ==> 0XF8000728[8:8] = 0x00000000U | ||
11009 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11010 | // .. IO_Type = 3 | ||
11011 | // .. ==> 0XF8000728[11:9] = 0x00000003U | ||
11012 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11013 | // .. PULLUP = 0 | ||
11014 | // .. ==> 0XF8000728[12:12] = 0x00000000U | ||
11015 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11016 | // .. DisableRcvr = 0 | ||
11017 | // .. ==> 0XF8000728[13:13] = 0x00000000U | ||
11018 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11019 | // .. | ||
11020 | EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), | ||
11021 | // .. TRI_ENABLE = 0 | ||
11022 | // .. ==> 0XF800072C[0:0] = 0x00000000U | ||
11023 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11024 | // .. L0_SEL = 0 | ||
11025 | // .. ==> 0XF800072C[1:1] = 0x00000000U | ||
11026 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11027 | // .. L1_SEL = 0 | ||
11028 | // .. ==> 0XF800072C[2:2] = 0x00000000U | ||
11029 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11030 | // .. L2_SEL = 0 | ||
11031 | // .. ==> 0XF800072C[4:3] = 0x00000000U | ||
11032 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11033 | // .. L3_SEL = 4 | ||
11034 | // .. ==> 0XF800072C[7:5] = 0x00000004U | ||
11035 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11036 | // .. Speed = 0 | ||
11037 | // .. ==> 0XF800072C[8:8] = 0x00000000U | ||
11038 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11039 | // .. IO_Type = 3 | ||
11040 | // .. ==> 0XF800072C[11:9] = 0x00000003U | ||
11041 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11042 | // .. PULLUP = 0 | ||
11043 | // .. ==> 0XF800072C[12:12] = 0x00000000U | ||
11044 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11045 | // .. DisableRcvr = 0 | ||
11046 | // .. ==> 0XF800072C[13:13] = 0x00000000U | ||
11047 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11048 | // .. | ||
11049 | EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), | ||
11050 | // .. TRI_ENABLE = 0 | ||
11051 | // .. ==> 0XF8000730[0:0] = 0x00000000U | ||
11052 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11053 | // .. L0_SEL = 0 | ||
11054 | // .. ==> 0XF8000730[1:1] = 0x00000000U | ||
11055 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11056 | // .. L1_SEL = 0 | ||
11057 | // .. ==> 0XF8000730[2:2] = 0x00000000U | ||
11058 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11059 | // .. L2_SEL = 0 | ||
11060 | // .. ==> 0XF8000730[4:3] = 0x00000000U | ||
11061 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11062 | // .. L3_SEL = 4 | ||
11063 | // .. ==> 0XF8000730[7:5] = 0x00000004U | ||
11064 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11065 | // .. Speed = 0 | ||
11066 | // .. ==> 0XF8000730[8:8] = 0x00000000U | ||
11067 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11068 | // .. IO_Type = 3 | ||
11069 | // .. ==> 0XF8000730[11:9] = 0x00000003U | ||
11070 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11071 | // .. PULLUP = 0 | ||
11072 | // .. ==> 0XF8000730[12:12] = 0x00000000U | ||
11073 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11074 | // .. DisableRcvr = 0 | ||
11075 | // .. ==> 0XF8000730[13:13] = 0x00000000U | ||
11076 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11077 | // .. | ||
11078 | EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), | ||
11079 | // .. TRI_ENABLE = 0 | ||
11080 | // .. ==> 0XF8000734[0:0] = 0x00000000U | ||
11081 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11082 | // .. L0_SEL = 0 | ||
11083 | // .. ==> 0XF8000734[1:1] = 0x00000000U | ||
11084 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11085 | // .. L1_SEL = 0 | ||
11086 | // .. ==> 0XF8000734[2:2] = 0x00000000U | ||
11087 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11088 | // .. L2_SEL = 0 | ||
11089 | // .. ==> 0XF8000734[4:3] = 0x00000000U | ||
11090 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11091 | // .. L3_SEL = 4 | ||
11092 | // .. ==> 0XF8000734[7:5] = 0x00000004U | ||
11093 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11094 | // .. Speed = 0 | ||
11095 | // .. ==> 0XF8000734[8:8] = 0x00000000U | ||
11096 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11097 | // .. IO_Type = 3 | ||
11098 | // .. ==> 0XF8000734[11:9] = 0x00000003U | ||
11099 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11100 | // .. PULLUP = 0 | ||
11101 | // .. ==> 0XF8000734[12:12] = 0x00000000U | ||
11102 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11103 | // .. DisableRcvr = 0 | ||
11104 | // .. ==> 0XF8000734[13:13] = 0x00000000U | ||
11105 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11106 | // .. | ||
11107 | EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), | ||
11108 | // .. TRI_ENABLE = 0 | ||
11109 | // .. ==> 0XF8000738[0:0] = 0x00000000U | ||
11110 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11111 | // .. L0_SEL = 0 | ||
11112 | // .. ==> 0XF8000738[1:1] = 0x00000000U | ||
11113 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11114 | // .. L1_SEL = 0 | ||
11115 | // .. ==> 0XF8000738[2:2] = 0x00000000U | ||
11116 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11117 | // .. L2_SEL = 0 | ||
11118 | // .. ==> 0XF8000738[4:3] = 0x00000000U | ||
11119 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11120 | // .. L3_SEL = 4 | ||
11121 | // .. ==> 0XF8000738[7:5] = 0x00000004U | ||
11122 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11123 | // .. Speed = 0 | ||
11124 | // .. ==> 0XF8000738[8:8] = 0x00000000U | ||
11125 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11126 | // .. IO_Type = 3 | ||
11127 | // .. ==> 0XF8000738[11:9] = 0x00000003U | ||
11128 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11129 | // .. PULLUP = 0 | ||
11130 | // .. ==> 0XF8000738[12:12] = 0x00000000U | ||
11131 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11132 | // .. DisableRcvr = 0 | ||
11133 | // .. ==> 0XF8000738[13:13] = 0x00000000U | ||
11134 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11135 | // .. | ||
11136 | EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), | ||
11137 | // .. TRI_ENABLE = 0 | ||
11138 | // .. ==> 0XF800073C[0:0] = 0x00000000U | ||
11139 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11140 | // .. L0_SEL = 0 | ||
11141 | // .. ==> 0XF800073C[1:1] = 0x00000000U | ||
11142 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11143 | // .. L1_SEL = 0 | ||
11144 | // .. ==> 0XF800073C[2:2] = 0x00000000U | ||
11145 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11146 | // .. L2_SEL = 0 | ||
11147 | // .. ==> 0XF800073C[4:3] = 0x00000000U | ||
11148 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11149 | // .. L3_SEL = 4 | ||
11150 | // .. ==> 0XF800073C[7:5] = 0x00000004U | ||
11151 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
11152 | // .. Speed = 0 | ||
11153 | // .. ==> 0XF800073C[8:8] = 0x00000000U | ||
11154 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11155 | // .. IO_Type = 3 | ||
11156 | // .. ==> 0XF800073C[11:9] = 0x00000003U | ||
11157 | // .. ==> MASK : 0x00000E00U VAL : 0x00000600U | ||
11158 | // .. PULLUP = 0 | ||
11159 | // .. ==> 0XF800073C[12:12] = 0x00000000U | ||
11160 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11161 | // .. DisableRcvr = 0 | ||
11162 | // .. ==> 0XF800073C[13:13] = 0x00000000U | ||
11163 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11164 | // .. | ||
11165 | EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), | ||
11166 | // .. TRI_ENABLE = 0 | ||
11167 | // .. ==> 0XF8000740[0:0] = 0x00000000U | ||
11168 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11169 | // .. L0_SEL = 1 | ||
11170 | // .. ==> 0XF8000740[1:1] = 0x00000001U | ||
11171 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11172 | // .. L1_SEL = 0 | ||
11173 | // .. ==> 0XF8000740[2:2] = 0x00000000U | ||
11174 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11175 | // .. L2_SEL = 0 | ||
11176 | // .. ==> 0XF8000740[4:3] = 0x00000000U | ||
11177 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11178 | // .. L3_SEL = 0 | ||
11179 | // .. ==> 0XF8000740[7:5] = 0x00000000U | ||
11180 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11181 | // .. Speed = 0 | ||
11182 | // .. ==> 0XF8000740[8:8] = 0x00000000U | ||
11183 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11184 | // .. IO_Type = 1 | ||
11185 | // .. ==> 0XF8000740[11:9] = 0x00000001U | ||
11186 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11187 | // .. PULLUP = 0 | ||
11188 | // .. ==> 0XF8000740[12:12] = 0x00000000U | ||
11189 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11190 | // .. DisableRcvr = 0 | ||
11191 | // .. ==> 0XF8000740[13:13] = 0x00000000U | ||
11192 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11193 | // .. | ||
11194 | EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U), | ||
11195 | // .. TRI_ENABLE = 0 | ||
11196 | // .. ==> 0XF8000744[0:0] = 0x00000000U | ||
11197 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11198 | // .. L0_SEL = 1 | ||
11199 | // .. ==> 0XF8000744[1:1] = 0x00000001U | ||
11200 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11201 | // .. L1_SEL = 0 | ||
11202 | // .. ==> 0XF8000744[2:2] = 0x00000000U | ||
11203 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11204 | // .. L2_SEL = 0 | ||
11205 | // .. ==> 0XF8000744[4:3] = 0x00000000U | ||
11206 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11207 | // .. L3_SEL = 0 | ||
11208 | // .. ==> 0XF8000744[7:5] = 0x00000000U | ||
11209 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11210 | // .. Speed = 0 | ||
11211 | // .. ==> 0XF8000744[8:8] = 0x00000000U | ||
11212 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11213 | // .. IO_Type = 1 | ||
11214 | // .. ==> 0XF8000744[11:9] = 0x00000001U | ||
11215 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11216 | // .. PULLUP = 0 | ||
11217 | // .. ==> 0XF8000744[12:12] = 0x00000000U | ||
11218 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11219 | // .. DisableRcvr = 0 | ||
11220 | // .. ==> 0XF8000744[13:13] = 0x00000000U | ||
11221 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11222 | // .. | ||
11223 | EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U), | ||
11224 | // .. TRI_ENABLE = 0 | ||
11225 | // .. ==> 0XF8000748[0:0] = 0x00000000U | ||
11226 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11227 | // .. L0_SEL = 1 | ||
11228 | // .. ==> 0XF8000748[1:1] = 0x00000001U | ||
11229 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11230 | // .. L1_SEL = 0 | ||
11231 | // .. ==> 0XF8000748[2:2] = 0x00000000U | ||
11232 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11233 | // .. L2_SEL = 0 | ||
11234 | // .. ==> 0XF8000748[4:3] = 0x00000000U | ||
11235 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11236 | // .. L3_SEL = 0 | ||
11237 | // .. ==> 0XF8000748[7:5] = 0x00000000U | ||
11238 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11239 | // .. Speed = 0 | ||
11240 | // .. ==> 0XF8000748[8:8] = 0x00000000U | ||
11241 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11242 | // .. IO_Type = 1 | ||
11243 | // .. ==> 0XF8000748[11:9] = 0x00000001U | ||
11244 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11245 | // .. PULLUP = 0 | ||
11246 | // .. ==> 0XF8000748[12:12] = 0x00000000U | ||
11247 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11248 | // .. DisableRcvr = 0 | ||
11249 | // .. ==> 0XF8000748[13:13] = 0x00000000U | ||
11250 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11251 | // .. | ||
11252 | EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U), | ||
11253 | // .. TRI_ENABLE = 0 | ||
11254 | // .. ==> 0XF800074C[0:0] = 0x00000000U | ||
11255 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11256 | // .. L0_SEL = 1 | ||
11257 | // .. ==> 0XF800074C[1:1] = 0x00000001U | ||
11258 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11259 | // .. L1_SEL = 0 | ||
11260 | // .. ==> 0XF800074C[2:2] = 0x00000000U | ||
11261 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11262 | // .. L2_SEL = 0 | ||
11263 | // .. ==> 0XF800074C[4:3] = 0x00000000U | ||
11264 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11265 | // .. L3_SEL = 0 | ||
11266 | // .. ==> 0XF800074C[7:5] = 0x00000000U | ||
11267 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11268 | // .. Speed = 0 | ||
11269 | // .. ==> 0XF800074C[8:8] = 0x00000000U | ||
11270 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11271 | // .. IO_Type = 1 | ||
11272 | // .. ==> 0XF800074C[11:9] = 0x00000001U | ||
11273 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11274 | // .. PULLUP = 0 | ||
11275 | // .. ==> 0XF800074C[12:12] = 0x00000000U | ||
11276 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11277 | // .. DisableRcvr = 0 | ||
11278 | // .. ==> 0XF800074C[13:13] = 0x00000000U | ||
11279 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11280 | // .. | ||
11281 | EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U), | ||
11282 | // .. TRI_ENABLE = 0 | ||
11283 | // .. ==> 0XF8000750[0:0] = 0x00000000U | ||
11284 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11285 | // .. L0_SEL = 1 | ||
11286 | // .. ==> 0XF8000750[1:1] = 0x00000001U | ||
11287 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11288 | // .. L1_SEL = 0 | ||
11289 | // .. ==> 0XF8000750[2:2] = 0x00000000U | ||
11290 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11291 | // .. L2_SEL = 0 | ||
11292 | // .. ==> 0XF8000750[4:3] = 0x00000000U | ||
11293 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11294 | // .. L3_SEL = 0 | ||
11295 | // .. ==> 0XF8000750[7:5] = 0x00000000U | ||
11296 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11297 | // .. Speed = 0 | ||
11298 | // .. ==> 0XF8000750[8:8] = 0x00000000U | ||
11299 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11300 | // .. IO_Type = 1 | ||
11301 | // .. ==> 0XF8000750[11:9] = 0x00000001U | ||
11302 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11303 | // .. PULLUP = 0 | ||
11304 | // .. ==> 0XF8000750[12:12] = 0x00000000U | ||
11305 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11306 | // .. DisableRcvr = 0 | ||
11307 | // .. ==> 0XF8000750[13:13] = 0x00000000U | ||
11308 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11309 | // .. | ||
11310 | EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U), | ||
11311 | // .. TRI_ENABLE = 0 | ||
11312 | // .. ==> 0XF8000754[0:0] = 0x00000000U | ||
11313 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11314 | // .. L0_SEL = 1 | ||
11315 | // .. ==> 0XF8000754[1:1] = 0x00000001U | ||
11316 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11317 | // .. L1_SEL = 0 | ||
11318 | // .. ==> 0XF8000754[2:2] = 0x00000000U | ||
11319 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11320 | // .. L2_SEL = 0 | ||
11321 | // .. ==> 0XF8000754[4:3] = 0x00000000U | ||
11322 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11323 | // .. L3_SEL = 0 | ||
11324 | // .. ==> 0XF8000754[7:5] = 0x00000000U | ||
11325 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11326 | // .. Speed = 0 | ||
11327 | // .. ==> 0XF8000754[8:8] = 0x00000000U | ||
11328 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11329 | // .. IO_Type = 1 | ||
11330 | // .. ==> 0XF8000754[11:9] = 0x00000001U | ||
11331 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11332 | // .. PULLUP = 0 | ||
11333 | // .. ==> 0XF8000754[12:12] = 0x00000000U | ||
11334 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11335 | // .. DisableRcvr = 0 | ||
11336 | // .. ==> 0XF8000754[13:13] = 0x00000000U | ||
11337 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11338 | // .. | ||
11339 | EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U), | ||
11340 | // .. TRI_ENABLE = 1 | ||
11341 | // .. ==> 0XF8000758[0:0] = 0x00000001U | ||
11342 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11343 | // .. L0_SEL = 1 | ||
11344 | // .. ==> 0XF8000758[1:1] = 0x00000001U | ||
11345 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11346 | // .. L1_SEL = 0 | ||
11347 | // .. ==> 0XF8000758[2:2] = 0x00000000U | ||
11348 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11349 | // .. L2_SEL = 0 | ||
11350 | // .. ==> 0XF8000758[4:3] = 0x00000000U | ||
11351 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11352 | // .. L3_SEL = 0 | ||
11353 | // .. ==> 0XF8000758[7:5] = 0x00000000U | ||
11354 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11355 | // .. Speed = 0 | ||
11356 | // .. ==> 0XF8000758[8:8] = 0x00000000U | ||
11357 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11358 | // .. IO_Type = 1 | ||
11359 | // .. ==> 0XF8000758[11:9] = 0x00000001U | ||
11360 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11361 | // .. PULLUP = 0 | ||
11362 | // .. ==> 0XF8000758[12:12] = 0x00000000U | ||
11363 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11364 | // .. DisableRcvr = 0 | ||
11365 | // .. ==> 0XF8000758[13:13] = 0x00000000U | ||
11366 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11367 | // .. | ||
11368 | EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U), | ||
11369 | // .. TRI_ENABLE = 1 | ||
11370 | // .. ==> 0XF800075C[0:0] = 0x00000001U | ||
11371 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11372 | // .. L0_SEL = 1 | ||
11373 | // .. ==> 0XF800075C[1:1] = 0x00000001U | ||
11374 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11375 | // .. L1_SEL = 0 | ||
11376 | // .. ==> 0XF800075C[2:2] = 0x00000000U | ||
11377 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11378 | // .. L2_SEL = 0 | ||
11379 | // .. ==> 0XF800075C[4:3] = 0x00000000U | ||
11380 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11381 | // .. L3_SEL = 0 | ||
11382 | // .. ==> 0XF800075C[7:5] = 0x00000000U | ||
11383 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11384 | // .. Speed = 0 | ||
11385 | // .. ==> 0XF800075C[8:8] = 0x00000000U | ||
11386 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11387 | // .. IO_Type = 1 | ||
11388 | // .. ==> 0XF800075C[11:9] = 0x00000001U | ||
11389 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11390 | // .. PULLUP = 0 | ||
11391 | // .. ==> 0XF800075C[12:12] = 0x00000000U | ||
11392 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11393 | // .. DisableRcvr = 0 | ||
11394 | // .. ==> 0XF800075C[13:13] = 0x00000000U | ||
11395 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11396 | // .. | ||
11397 | EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U), | ||
11398 | // .. TRI_ENABLE = 1 | ||
11399 | // .. ==> 0XF8000760[0:0] = 0x00000001U | ||
11400 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11401 | // .. L0_SEL = 1 | ||
11402 | // .. ==> 0XF8000760[1:1] = 0x00000001U | ||
11403 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11404 | // .. L1_SEL = 0 | ||
11405 | // .. ==> 0XF8000760[2:2] = 0x00000000U | ||
11406 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11407 | // .. L2_SEL = 0 | ||
11408 | // .. ==> 0XF8000760[4:3] = 0x00000000U | ||
11409 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11410 | // .. L3_SEL = 0 | ||
11411 | // .. ==> 0XF8000760[7:5] = 0x00000000U | ||
11412 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11413 | // .. Speed = 0 | ||
11414 | // .. ==> 0XF8000760[8:8] = 0x00000000U | ||
11415 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11416 | // .. IO_Type = 1 | ||
11417 | // .. ==> 0XF8000760[11:9] = 0x00000001U | ||
11418 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11419 | // .. PULLUP = 0 | ||
11420 | // .. ==> 0XF8000760[12:12] = 0x00000000U | ||
11421 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11422 | // .. DisableRcvr = 0 | ||
11423 | // .. ==> 0XF8000760[13:13] = 0x00000000U | ||
11424 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11425 | // .. | ||
11426 | EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U), | ||
11427 | // .. TRI_ENABLE = 1 | ||
11428 | // .. ==> 0XF8000764[0:0] = 0x00000001U | ||
11429 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11430 | // .. L0_SEL = 1 | ||
11431 | // .. ==> 0XF8000764[1:1] = 0x00000001U | ||
11432 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11433 | // .. L1_SEL = 0 | ||
11434 | // .. ==> 0XF8000764[2:2] = 0x00000000U | ||
11435 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11436 | // .. L2_SEL = 0 | ||
11437 | // .. ==> 0XF8000764[4:3] = 0x00000000U | ||
11438 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11439 | // .. L3_SEL = 0 | ||
11440 | // .. ==> 0XF8000764[7:5] = 0x00000000U | ||
11441 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11442 | // .. Speed = 0 | ||
11443 | // .. ==> 0XF8000764[8:8] = 0x00000000U | ||
11444 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11445 | // .. IO_Type = 1 | ||
11446 | // .. ==> 0XF8000764[11:9] = 0x00000001U | ||
11447 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11448 | // .. PULLUP = 0 | ||
11449 | // .. ==> 0XF8000764[12:12] = 0x00000000U | ||
11450 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11451 | // .. DisableRcvr = 0 | ||
11452 | // .. ==> 0XF8000764[13:13] = 0x00000000U | ||
11453 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11454 | // .. | ||
11455 | EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U), | ||
11456 | // .. TRI_ENABLE = 1 | ||
11457 | // .. ==> 0XF8000768[0:0] = 0x00000001U | ||
11458 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11459 | // .. L0_SEL = 1 | ||
11460 | // .. ==> 0XF8000768[1:1] = 0x00000001U | ||
11461 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11462 | // .. L1_SEL = 0 | ||
11463 | // .. ==> 0XF8000768[2:2] = 0x00000000U | ||
11464 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11465 | // .. L2_SEL = 0 | ||
11466 | // .. ==> 0XF8000768[4:3] = 0x00000000U | ||
11467 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11468 | // .. L3_SEL = 0 | ||
11469 | // .. ==> 0XF8000768[7:5] = 0x00000000U | ||
11470 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11471 | // .. Speed = 0 | ||
11472 | // .. ==> 0XF8000768[8:8] = 0x00000000U | ||
11473 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11474 | // .. IO_Type = 1 | ||
11475 | // .. ==> 0XF8000768[11:9] = 0x00000001U | ||
11476 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11477 | // .. PULLUP = 0 | ||
11478 | // .. ==> 0XF8000768[12:12] = 0x00000000U | ||
11479 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11480 | // .. DisableRcvr = 0 | ||
11481 | // .. ==> 0XF8000768[13:13] = 0x00000000U | ||
11482 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11483 | // .. | ||
11484 | EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U), | ||
11485 | // .. TRI_ENABLE = 1 | ||
11486 | // .. ==> 0XF800076C[0:0] = 0x00000001U | ||
11487 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11488 | // .. L0_SEL = 1 | ||
11489 | // .. ==> 0XF800076C[1:1] = 0x00000001U | ||
11490 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
11491 | // .. L1_SEL = 0 | ||
11492 | // .. ==> 0XF800076C[2:2] = 0x00000000U | ||
11493 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11494 | // .. L2_SEL = 0 | ||
11495 | // .. ==> 0XF800076C[4:3] = 0x00000000U | ||
11496 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11497 | // .. L3_SEL = 0 | ||
11498 | // .. ==> 0XF800076C[7:5] = 0x00000000U | ||
11499 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11500 | // .. Speed = 0 | ||
11501 | // .. ==> 0XF800076C[8:8] = 0x00000000U | ||
11502 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11503 | // .. IO_Type = 1 | ||
11504 | // .. ==> 0XF800076C[11:9] = 0x00000001U | ||
11505 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11506 | // .. PULLUP = 0 | ||
11507 | // .. ==> 0XF800076C[12:12] = 0x00000000U | ||
11508 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11509 | // .. DisableRcvr = 0 | ||
11510 | // .. ==> 0XF800076C[13:13] = 0x00000000U | ||
11511 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11512 | // .. | ||
11513 | EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U), | ||
11514 | // .. TRI_ENABLE = 0 | ||
11515 | // .. ==> 0XF8000770[0:0] = 0x00000000U | ||
11516 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11517 | // .. L0_SEL = 0 | ||
11518 | // .. ==> 0XF8000770[1:1] = 0x00000000U | ||
11519 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11520 | // .. L1_SEL = 1 | ||
11521 | // .. ==> 0XF8000770[2:2] = 0x00000001U | ||
11522 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11523 | // .. L2_SEL = 0 | ||
11524 | // .. ==> 0XF8000770[4:3] = 0x00000000U | ||
11525 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11526 | // .. L3_SEL = 0 | ||
11527 | // .. ==> 0XF8000770[7:5] = 0x00000000U | ||
11528 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11529 | // .. Speed = 0 | ||
11530 | // .. ==> 0XF8000770[8:8] = 0x00000000U | ||
11531 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11532 | // .. IO_Type = 1 | ||
11533 | // .. ==> 0XF8000770[11:9] = 0x00000001U | ||
11534 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11535 | // .. PULLUP = 0 | ||
11536 | // .. ==> 0XF8000770[12:12] = 0x00000000U | ||
11537 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11538 | // .. DisableRcvr = 0 | ||
11539 | // .. ==> 0XF8000770[13:13] = 0x00000000U | ||
11540 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11541 | // .. | ||
11542 | EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), | ||
11543 | // .. TRI_ENABLE = 1 | ||
11544 | // .. ==> 0XF8000774[0:0] = 0x00000001U | ||
11545 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11546 | // .. L0_SEL = 0 | ||
11547 | // .. ==> 0XF8000774[1:1] = 0x00000000U | ||
11548 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11549 | // .. L1_SEL = 1 | ||
11550 | // .. ==> 0XF8000774[2:2] = 0x00000001U | ||
11551 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11552 | // .. L2_SEL = 0 | ||
11553 | // .. ==> 0XF8000774[4:3] = 0x00000000U | ||
11554 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11555 | // .. L3_SEL = 0 | ||
11556 | // .. ==> 0XF8000774[7:5] = 0x00000000U | ||
11557 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11558 | // .. Speed = 0 | ||
11559 | // .. ==> 0XF8000774[8:8] = 0x00000000U | ||
11560 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11561 | // .. IO_Type = 1 | ||
11562 | // .. ==> 0XF8000774[11:9] = 0x00000001U | ||
11563 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11564 | // .. PULLUP = 0 | ||
11565 | // .. ==> 0XF8000774[12:12] = 0x00000000U | ||
11566 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11567 | // .. DisableRcvr = 0 | ||
11568 | // .. ==> 0XF8000774[13:13] = 0x00000000U | ||
11569 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11570 | // .. | ||
11571 | EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), | ||
11572 | // .. TRI_ENABLE = 0 | ||
11573 | // .. ==> 0XF8000778[0:0] = 0x00000000U | ||
11574 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11575 | // .. L0_SEL = 0 | ||
11576 | // .. ==> 0XF8000778[1:1] = 0x00000000U | ||
11577 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11578 | // .. L1_SEL = 1 | ||
11579 | // .. ==> 0XF8000778[2:2] = 0x00000001U | ||
11580 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11581 | // .. L2_SEL = 0 | ||
11582 | // .. ==> 0XF8000778[4:3] = 0x00000000U | ||
11583 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11584 | // .. L3_SEL = 0 | ||
11585 | // .. ==> 0XF8000778[7:5] = 0x00000000U | ||
11586 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11587 | // .. Speed = 0 | ||
11588 | // .. ==> 0XF8000778[8:8] = 0x00000000U | ||
11589 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11590 | // .. IO_Type = 1 | ||
11591 | // .. ==> 0XF8000778[11:9] = 0x00000001U | ||
11592 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11593 | // .. PULLUP = 0 | ||
11594 | // .. ==> 0XF8000778[12:12] = 0x00000000U | ||
11595 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11596 | // .. DisableRcvr = 0 | ||
11597 | // .. ==> 0XF8000778[13:13] = 0x00000000U | ||
11598 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11599 | // .. | ||
11600 | EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), | ||
11601 | // .. TRI_ENABLE = 1 | ||
11602 | // .. ==> 0XF800077C[0:0] = 0x00000001U | ||
11603 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11604 | // .. L0_SEL = 0 | ||
11605 | // .. ==> 0XF800077C[1:1] = 0x00000000U | ||
11606 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11607 | // .. L1_SEL = 1 | ||
11608 | // .. ==> 0XF800077C[2:2] = 0x00000001U | ||
11609 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11610 | // .. L2_SEL = 0 | ||
11611 | // .. ==> 0XF800077C[4:3] = 0x00000000U | ||
11612 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11613 | // .. L3_SEL = 0 | ||
11614 | // .. ==> 0XF800077C[7:5] = 0x00000000U | ||
11615 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11616 | // .. Speed = 0 | ||
11617 | // .. ==> 0XF800077C[8:8] = 0x00000000U | ||
11618 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11619 | // .. IO_Type = 1 | ||
11620 | // .. ==> 0XF800077C[11:9] = 0x00000001U | ||
11621 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11622 | // .. PULLUP = 0 | ||
11623 | // .. ==> 0XF800077C[12:12] = 0x00000000U | ||
11624 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11625 | // .. DisableRcvr = 0 | ||
11626 | // .. ==> 0XF800077C[13:13] = 0x00000000U | ||
11627 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11628 | // .. | ||
11629 | EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), | ||
11630 | // .. TRI_ENABLE = 0 | ||
11631 | // .. ==> 0XF8000780[0:0] = 0x00000000U | ||
11632 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11633 | // .. L0_SEL = 0 | ||
11634 | // .. ==> 0XF8000780[1:1] = 0x00000000U | ||
11635 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11636 | // .. L1_SEL = 1 | ||
11637 | // .. ==> 0XF8000780[2:2] = 0x00000001U | ||
11638 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11639 | // .. L2_SEL = 0 | ||
11640 | // .. ==> 0XF8000780[4:3] = 0x00000000U | ||
11641 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11642 | // .. L3_SEL = 0 | ||
11643 | // .. ==> 0XF8000780[7:5] = 0x00000000U | ||
11644 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11645 | // .. Speed = 0 | ||
11646 | // .. ==> 0XF8000780[8:8] = 0x00000000U | ||
11647 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11648 | // .. IO_Type = 1 | ||
11649 | // .. ==> 0XF8000780[11:9] = 0x00000001U | ||
11650 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11651 | // .. PULLUP = 0 | ||
11652 | // .. ==> 0XF8000780[12:12] = 0x00000000U | ||
11653 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11654 | // .. DisableRcvr = 0 | ||
11655 | // .. ==> 0XF8000780[13:13] = 0x00000000U | ||
11656 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11657 | // .. | ||
11658 | EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), | ||
11659 | // .. TRI_ENABLE = 0 | ||
11660 | // .. ==> 0XF8000784[0:0] = 0x00000000U | ||
11661 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11662 | // .. L0_SEL = 0 | ||
11663 | // .. ==> 0XF8000784[1:1] = 0x00000000U | ||
11664 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11665 | // .. L1_SEL = 1 | ||
11666 | // .. ==> 0XF8000784[2:2] = 0x00000001U | ||
11667 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11668 | // .. L2_SEL = 0 | ||
11669 | // .. ==> 0XF8000784[4:3] = 0x00000000U | ||
11670 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11671 | // .. L3_SEL = 0 | ||
11672 | // .. ==> 0XF8000784[7:5] = 0x00000000U | ||
11673 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11674 | // .. Speed = 0 | ||
11675 | // .. ==> 0XF8000784[8:8] = 0x00000000U | ||
11676 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11677 | // .. IO_Type = 1 | ||
11678 | // .. ==> 0XF8000784[11:9] = 0x00000001U | ||
11679 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11680 | // .. PULLUP = 0 | ||
11681 | // .. ==> 0XF8000784[12:12] = 0x00000000U | ||
11682 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11683 | // .. DisableRcvr = 0 | ||
11684 | // .. ==> 0XF8000784[13:13] = 0x00000000U | ||
11685 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11686 | // .. | ||
11687 | EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), | ||
11688 | // .. TRI_ENABLE = 0 | ||
11689 | // .. ==> 0XF8000788[0:0] = 0x00000000U | ||
11690 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11691 | // .. L0_SEL = 0 | ||
11692 | // .. ==> 0XF8000788[1:1] = 0x00000000U | ||
11693 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11694 | // .. L1_SEL = 1 | ||
11695 | // .. ==> 0XF8000788[2:2] = 0x00000001U | ||
11696 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11697 | // .. L2_SEL = 0 | ||
11698 | // .. ==> 0XF8000788[4:3] = 0x00000000U | ||
11699 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11700 | // .. L3_SEL = 0 | ||
11701 | // .. ==> 0XF8000788[7:5] = 0x00000000U | ||
11702 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11703 | // .. Speed = 0 | ||
11704 | // .. ==> 0XF8000788[8:8] = 0x00000000U | ||
11705 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11706 | // .. IO_Type = 1 | ||
11707 | // .. ==> 0XF8000788[11:9] = 0x00000001U | ||
11708 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11709 | // .. PULLUP = 0 | ||
11710 | // .. ==> 0XF8000788[12:12] = 0x00000000U | ||
11711 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11712 | // .. DisableRcvr = 0 | ||
11713 | // .. ==> 0XF8000788[13:13] = 0x00000000U | ||
11714 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11715 | // .. | ||
11716 | EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), | ||
11717 | // .. TRI_ENABLE = 0 | ||
11718 | // .. ==> 0XF800078C[0:0] = 0x00000000U | ||
11719 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11720 | // .. L0_SEL = 0 | ||
11721 | // .. ==> 0XF800078C[1:1] = 0x00000000U | ||
11722 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11723 | // .. L1_SEL = 1 | ||
11724 | // .. ==> 0XF800078C[2:2] = 0x00000001U | ||
11725 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11726 | // .. L2_SEL = 0 | ||
11727 | // .. ==> 0XF800078C[4:3] = 0x00000000U | ||
11728 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11729 | // .. L3_SEL = 0 | ||
11730 | // .. ==> 0XF800078C[7:5] = 0x00000000U | ||
11731 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11732 | // .. Speed = 0 | ||
11733 | // .. ==> 0XF800078C[8:8] = 0x00000000U | ||
11734 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11735 | // .. IO_Type = 1 | ||
11736 | // .. ==> 0XF800078C[11:9] = 0x00000001U | ||
11737 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11738 | // .. PULLUP = 0 | ||
11739 | // .. ==> 0XF800078C[12:12] = 0x00000000U | ||
11740 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11741 | // .. DisableRcvr = 0 | ||
11742 | // .. ==> 0XF800078C[13:13] = 0x00000000U | ||
11743 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11744 | // .. | ||
11745 | EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), | ||
11746 | // .. TRI_ENABLE = 1 | ||
11747 | // .. ==> 0XF8000790[0:0] = 0x00000001U | ||
11748 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
11749 | // .. L0_SEL = 0 | ||
11750 | // .. ==> 0XF8000790[1:1] = 0x00000000U | ||
11751 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11752 | // .. L1_SEL = 1 | ||
11753 | // .. ==> 0XF8000790[2:2] = 0x00000001U | ||
11754 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11755 | // .. L2_SEL = 0 | ||
11756 | // .. ==> 0XF8000790[4:3] = 0x00000000U | ||
11757 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11758 | // .. L3_SEL = 0 | ||
11759 | // .. ==> 0XF8000790[7:5] = 0x00000000U | ||
11760 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11761 | // .. Speed = 0 | ||
11762 | // .. ==> 0XF8000790[8:8] = 0x00000000U | ||
11763 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11764 | // .. IO_Type = 1 | ||
11765 | // .. ==> 0XF8000790[11:9] = 0x00000001U | ||
11766 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11767 | // .. PULLUP = 0 | ||
11768 | // .. ==> 0XF8000790[12:12] = 0x00000000U | ||
11769 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11770 | // .. DisableRcvr = 0 | ||
11771 | // .. ==> 0XF8000790[13:13] = 0x00000000U | ||
11772 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11773 | // .. | ||
11774 | EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), | ||
11775 | // .. TRI_ENABLE = 0 | ||
11776 | // .. ==> 0XF8000794[0:0] = 0x00000000U | ||
11777 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11778 | // .. L0_SEL = 0 | ||
11779 | // .. ==> 0XF8000794[1:1] = 0x00000000U | ||
11780 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11781 | // .. L1_SEL = 1 | ||
11782 | // .. ==> 0XF8000794[2:2] = 0x00000001U | ||
11783 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11784 | // .. L2_SEL = 0 | ||
11785 | // .. ==> 0XF8000794[4:3] = 0x00000000U | ||
11786 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11787 | // .. L3_SEL = 0 | ||
11788 | // .. ==> 0XF8000794[7:5] = 0x00000000U | ||
11789 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11790 | // .. Speed = 0 | ||
11791 | // .. ==> 0XF8000794[8:8] = 0x00000000U | ||
11792 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11793 | // .. IO_Type = 1 | ||
11794 | // .. ==> 0XF8000794[11:9] = 0x00000001U | ||
11795 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11796 | // .. PULLUP = 0 | ||
11797 | // .. ==> 0XF8000794[12:12] = 0x00000000U | ||
11798 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11799 | // .. DisableRcvr = 0 | ||
11800 | // .. ==> 0XF8000794[13:13] = 0x00000000U | ||
11801 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11802 | // .. | ||
11803 | EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), | ||
11804 | // .. TRI_ENABLE = 0 | ||
11805 | // .. ==> 0XF8000798[0:0] = 0x00000000U | ||
11806 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11807 | // .. L0_SEL = 0 | ||
11808 | // .. ==> 0XF8000798[1:1] = 0x00000000U | ||
11809 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11810 | // .. L1_SEL = 1 | ||
11811 | // .. ==> 0XF8000798[2:2] = 0x00000001U | ||
11812 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11813 | // .. L2_SEL = 0 | ||
11814 | // .. ==> 0XF8000798[4:3] = 0x00000000U | ||
11815 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11816 | // .. L3_SEL = 0 | ||
11817 | // .. ==> 0XF8000798[7:5] = 0x00000000U | ||
11818 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11819 | // .. Speed = 0 | ||
11820 | // .. ==> 0XF8000798[8:8] = 0x00000000U | ||
11821 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11822 | // .. IO_Type = 1 | ||
11823 | // .. ==> 0XF8000798[11:9] = 0x00000001U | ||
11824 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11825 | // .. PULLUP = 0 | ||
11826 | // .. ==> 0XF8000798[12:12] = 0x00000000U | ||
11827 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11828 | // .. DisableRcvr = 0 | ||
11829 | // .. ==> 0XF8000798[13:13] = 0x00000000U | ||
11830 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11831 | // .. | ||
11832 | EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), | ||
11833 | // .. TRI_ENABLE = 0 | ||
11834 | // .. ==> 0XF800079C[0:0] = 0x00000000U | ||
11835 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11836 | // .. L0_SEL = 0 | ||
11837 | // .. ==> 0XF800079C[1:1] = 0x00000000U | ||
11838 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11839 | // .. L1_SEL = 1 | ||
11840 | // .. ==> 0XF800079C[2:2] = 0x00000001U | ||
11841 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
11842 | // .. L2_SEL = 0 | ||
11843 | // .. ==> 0XF800079C[4:3] = 0x00000000U | ||
11844 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11845 | // .. L3_SEL = 0 | ||
11846 | // .. ==> 0XF800079C[7:5] = 0x00000000U | ||
11847 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11848 | // .. Speed = 0 | ||
11849 | // .. ==> 0XF800079C[8:8] = 0x00000000U | ||
11850 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11851 | // .. IO_Type = 1 | ||
11852 | // .. ==> 0XF800079C[11:9] = 0x00000001U | ||
11853 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11854 | // .. PULLUP = 0 | ||
11855 | // .. ==> 0XF800079C[12:12] = 0x00000000U | ||
11856 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11857 | // .. DisableRcvr = 0 | ||
11858 | // .. ==> 0XF800079C[13:13] = 0x00000000U | ||
11859 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11860 | // .. | ||
11861 | EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), | ||
11862 | // .. TRI_ENABLE = 0 | ||
11863 | // .. ==> 0XF80007A0[0:0] = 0x00000000U | ||
11864 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11865 | // .. L0_SEL = 0 | ||
11866 | // .. ==> 0XF80007A0[1:1] = 0x00000000U | ||
11867 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11868 | // .. L1_SEL = 0 | ||
11869 | // .. ==> 0XF80007A0[2:2] = 0x00000000U | ||
11870 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11871 | // .. L2_SEL = 0 | ||
11872 | // .. ==> 0XF80007A0[4:3] = 0x00000000U | ||
11873 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11874 | // .. L3_SEL = 0 | ||
11875 | // .. ==> 0XF80007A0[7:5] = 0x00000000U | ||
11876 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11877 | // .. Speed = 0 | ||
11878 | // .. ==> 0XF80007A0[8:8] = 0x00000000U | ||
11879 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11880 | // .. IO_Type = 1 | ||
11881 | // .. ==> 0XF80007A0[11:9] = 0x00000001U | ||
11882 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11883 | // .. PULLUP = 0 | ||
11884 | // .. ==> 0XF80007A0[12:12] = 0x00000000U | ||
11885 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11886 | // .. DisableRcvr = 0 | ||
11887 | // .. ==> 0XF80007A0[13:13] = 0x00000000U | ||
11888 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11889 | // .. | ||
11890 | EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U), | ||
11891 | // .. TRI_ENABLE = 0 | ||
11892 | // .. ==> 0XF80007A4[0:0] = 0x00000000U | ||
11893 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11894 | // .. L0_SEL = 0 | ||
11895 | // .. ==> 0XF80007A4[1:1] = 0x00000000U | ||
11896 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11897 | // .. L1_SEL = 0 | ||
11898 | // .. ==> 0XF80007A4[2:2] = 0x00000000U | ||
11899 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11900 | // .. L2_SEL = 0 | ||
11901 | // .. ==> 0XF80007A4[4:3] = 0x00000000U | ||
11902 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11903 | // .. L3_SEL = 0 | ||
11904 | // .. ==> 0XF80007A4[7:5] = 0x00000000U | ||
11905 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11906 | // .. Speed = 0 | ||
11907 | // .. ==> 0XF80007A4[8:8] = 0x00000000U | ||
11908 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11909 | // .. IO_Type = 1 | ||
11910 | // .. ==> 0XF80007A4[11:9] = 0x00000001U | ||
11911 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11912 | // .. PULLUP = 0 | ||
11913 | // .. ==> 0XF80007A4[12:12] = 0x00000000U | ||
11914 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11915 | // .. DisableRcvr = 0 | ||
11916 | // .. ==> 0XF80007A4[13:13] = 0x00000000U | ||
11917 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11918 | // .. | ||
11919 | EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U), | ||
11920 | // .. TRI_ENABLE = 0 | ||
11921 | // .. ==> 0XF80007A8[0:0] = 0x00000000U | ||
11922 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11923 | // .. L0_SEL = 0 | ||
11924 | // .. ==> 0XF80007A8[1:1] = 0x00000000U | ||
11925 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11926 | // .. L1_SEL = 0 | ||
11927 | // .. ==> 0XF80007A8[2:2] = 0x00000000U | ||
11928 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11929 | // .. L2_SEL = 0 | ||
11930 | // .. ==> 0XF80007A8[4:3] = 0x00000000U | ||
11931 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11932 | // .. L3_SEL = 0 | ||
11933 | // .. ==> 0XF80007A8[7:5] = 0x00000000U | ||
11934 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11935 | // .. Speed = 0 | ||
11936 | // .. ==> 0XF80007A8[8:8] = 0x00000000U | ||
11937 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11938 | // .. IO_Type = 1 | ||
11939 | // .. ==> 0XF80007A8[11:9] = 0x00000001U | ||
11940 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11941 | // .. PULLUP = 0 | ||
11942 | // .. ==> 0XF80007A8[12:12] = 0x00000000U | ||
11943 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11944 | // .. DisableRcvr = 0 | ||
11945 | // .. ==> 0XF80007A8[13:13] = 0x00000000U | ||
11946 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11947 | // .. | ||
11948 | EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U), | ||
11949 | // .. TRI_ENABLE = 0 | ||
11950 | // .. ==> 0XF80007AC[0:0] = 0x00000000U | ||
11951 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11952 | // .. L0_SEL = 0 | ||
11953 | // .. ==> 0XF80007AC[1:1] = 0x00000000U | ||
11954 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11955 | // .. L1_SEL = 0 | ||
11956 | // .. ==> 0XF80007AC[2:2] = 0x00000000U | ||
11957 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11958 | // .. L2_SEL = 0 | ||
11959 | // .. ==> 0XF80007AC[4:3] = 0x00000000U | ||
11960 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11961 | // .. L3_SEL = 0 | ||
11962 | // .. ==> 0XF80007AC[7:5] = 0x00000000U | ||
11963 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11964 | // .. Speed = 0 | ||
11965 | // .. ==> 0XF80007AC[8:8] = 0x00000000U | ||
11966 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11967 | // .. IO_Type = 1 | ||
11968 | // .. ==> 0XF80007AC[11:9] = 0x00000001U | ||
11969 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11970 | // .. PULLUP = 0 | ||
11971 | // .. ==> 0XF80007AC[12:12] = 0x00000000U | ||
11972 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
11973 | // .. DisableRcvr = 0 | ||
11974 | // .. ==> 0XF80007AC[13:13] = 0x00000000U | ||
11975 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
11976 | // .. | ||
11977 | EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U), | ||
11978 | // .. TRI_ENABLE = 0 | ||
11979 | // .. ==> 0XF80007B0[0:0] = 0x00000000U | ||
11980 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
11981 | // .. L0_SEL = 0 | ||
11982 | // .. ==> 0XF80007B0[1:1] = 0x00000000U | ||
11983 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
11984 | // .. L1_SEL = 0 | ||
11985 | // .. ==> 0XF80007B0[2:2] = 0x00000000U | ||
11986 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
11987 | // .. L2_SEL = 0 | ||
11988 | // .. ==> 0XF80007B0[4:3] = 0x00000000U | ||
11989 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
11990 | // .. L3_SEL = 0 | ||
11991 | // .. ==> 0XF80007B0[7:5] = 0x00000000U | ||
11992 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
11993 | // .. Speed = 0 | ||
11994 | // .. ==> 0XF80007B0[8:8] = 0x00000000U | ||
11995 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
11996 | // .. IO_Type = 1 | ||
11997 | // .. ==> 0XF80007B0[11:9] = 0x00000001U | ||
11998 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
11999 | // .. PULLUP = 0 | ||
12000 | // .. ==> 0XF80007B0[12:12] = 0x00000000U | ||
12001 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12002 | // .. DisableRcvr = 0 | ||
12003 | // .. ==> 0XF80007B0[13:13] = 0x00000000U | ||
12004 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12005 | // .. | ||
12006 | EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U), | ||
12007 | // .. TRI_ENABLE = 0 | ||
12008 | // .. ==> 0XF80007B4[0:0] = 0x00000000U | ||
12009 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12010 | // .. L0_SEL = 0 | ||
12011 | // .. ==> 0XF80007B4[1:1] = 0x00000000U | ||
12012 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12013 | // .. L1_SEL = 0 | ||
12014 | // .. ==> 0XF80007B4[2:2] = 0x00000000U | ||
12015 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12016 | // .. L2_SEL = 0 | ||
12017 | // .. ==> 0XF80007B4[4:3] = 0x00000000U | ||
12018 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12019 | // .. L3_SEL = 0 | ||
12020 | // .. ==> 0XF80007B4[7:5] = 0x00000000U | ||
12021 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
12022 | // .. Speed = 0 | ||
12023 | // .. ==> 0XF80007B4[8:8] = 0x00000000U | ||
12024 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12025 | // .. IO_Type = 1 | ||
12026 | // .. ==> 0XF80007B4[11:9] = 0x00000001U | ||
12027 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12028 | // .. PULLUP = 0 | ||
12029 | // .. ==> 0XF80007B4[12:12] = 0x00000000U | ||
12030 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12031 | // .. DisableRcvr = 0 | ||
12032 | // .. ==> 0XF80007B4[13:13] = 0x00000000U | ||
12033 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12034 | // .. | ||
12035 | EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U), | ||
12036 | // .. TRI_ENABLE = 0 | ||
12037 | // .. ==> 0XF80007B8[0:0] = 0x00000000U | ||
12038 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12039 | // .. L0_SEL = 0 | ||
12040 | // .. ==> 0XF80007B8[1:1] = 0x00000000U | ||
12041 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12042 | // .. L1_SEL = 0 | ||
12043 | // .. ==> 0XF80007B8[2:2] = 0x00000000U | ||
12044 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12045 | // .. L2_SEL = 0 | ||
12046 | // .. ==> 0XF80007B8[4:3] = 0x00000000U | ||
12047 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12048 | // .. L3_SEL = 0 | ||
12049 | // .. ==> 0XF80007B8[7:5] = 0x00000000U | ||
12050 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
12051 | // .. Speed = 0 | ||
12052 | // .. ==> 0XF80007B8[8:8] = 0x00000000U | ||
12053 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12054 | // .. IO_Type = 1 | ||
12055 | // .. ==> 0XF80007B8[11:9] = 0x00000001U | ||
12056 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12057 | // .. PULLUP = 0 | ||
12058 | // .. ==> 0XF80007B8[12:12] = 0x00000000U | ||
12059 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12060 | // .. DisableRcvr = 0 | ||
12061 | // .. ==> 0XF80007B8[13:13] = 0x00000000U | ||
12062 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12063 | // .. | ||
12064 | EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U), | ||
12065 | // .. TRI_ENABLE = 0 | ||
12066 | // .. ==> 0XF80007BC[0:0] = 0x00000000U | ||
12067 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12068 | // .. L0_SEL = 0 | ||
12069 | // .. ==> 0XF80007BC[1:1] = 0x00000000U | ||
12070 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12071 | // .. L1_SEL = 0 | ||
12072 | // .. ==> 0XF80007BC[2:2] = 0x00000000U | ||
12073 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12074 | // .. L2_SEL = 0 | ||
12075 | // .. ==> 0XF80007BC[4:3] = 0x00000000U | ||
12076 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12077 | // .. L3_SEL = 0 | ||
12078 | // .. ==> 0XF80007BC[7:5] = 0x00000000U | ||
12079 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
12080 | // .. Speed = 0 | ||
12081 | // .. ==> 0XF80007BC[8:8] = 0x00000000U | ||
12082 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12083 | // .. IO_Type = 1 | ||
12084 | // .. ==> 0XF80007BC[11:9] = 0x00000001U | ||
12085 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12086 | // .. PULLUP = 0 | ||
12087 | // .. ==> 0XF80007BC[12:12] = 0x00000000U | ||
12088 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12089 | // .. DisableRcvr = 0 | ||
12090 | // .. ==> 0XF80007BC[13:13] = 0x00000000U | ||
12091 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12092 | // .. | ||
12093 | EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U), | ||
12094 | // .. TRI_ENABLE = 0 | ||
12095 | // .. ==> 0XF80007C0[0:0] = 0x00000000U | ||
12096 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12097 | // .. L0_SEL = 0 | ||
12098 | // .. ==> 0XF80007C0[1:1] = 0x00000000U | ||
12099 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12100 | // .. L1_SEL = 0 | ||
12101 | // .. ==> 0XF80007C0[2:2] = 0x00000000U | ||
12102 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12103 | // .. L2_SEL = 0 | ||
12104 | // .. ==> 0XF80007C0[4:3] = 0x00000000U | ||
12105 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12106 | // .. L3_SEL = 7 | ||
12107 | // .. ==> 0XF80007C0[7:5] = 0x00000007U | ||
12108 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
12109 | // .. Speed = 0 | ||
12110 | // .. ==> 0XF80007C0[8:8] = 0x00000000U | ||
12111 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12112 | // .. IO_Type = 1 | ||
12113 | // .. ==> 0XF80007C0[11:9] = 0x00000001U | ||
12114 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12115 | // .. PULLUP = 0 | ||
12116 | // .. ==> 0XF80007C0[12:12] = 0x00000000U | ||
12117 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12118 | // .. DisableRcvr = 0 | ||
12119 | // .. ==> 0XF80007C0[13:13] = 0x00000000U | ||
12120 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12121 | // .. | ||
12122 | EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), | ||
12123 | // .. TRI_ENABLE = 1 | ||
12124 | // .. ==> 0XF80007C4[0:0] = 0x00000001U | ||
12125 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
12126 | // .. L0_SEL = 0 | ||
12127 | // .. ==> 0XF80007C4[1:1] = 0x00000000U | ||
12128 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12129 | // .. L1_SEL = 0 | ||
12130 | // .. ==> 0XF80007C4[2:2] = 0x00000000U | ||
12131 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12132 | // .. L2_SEL = 0 | ||
12133 | // .. ==> 0XF80007C4[4:3] = 0x00000000U | ||
12134 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12135 | // .. L3_SEL = 7 | ||
12136 | // .. ==> 0XF80007C4[7:5] = 0x00000007U | ||
12137 | // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U | ||
12138 | // .. Speed = 0 | ||
12139 | // .. ==> 0XF80007C4[8:8] = 0x00000000U | ||
12140 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12141 | // .. IO_Type = 1 | ||
12142 | // .. ==> 0XF80007C4[11:9] = 0x00000001U | ||
12143 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12144 | // .. PULLUP = 0 | ||
12145 | // .. ==> 0XF80007C4[12:12] = 0x00000000U | ||
12146 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12147 | // .. DisableRcvr = 0 | ||
12148 | // .. ==> 0XF80007C4[13:13] = 0x00000000U | ||
12149 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12150 | // .. | ||
12151 | EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), | ||
12152 | // .. TRI_ENABLE = 0 | ||
12153 | // .. ==> 0XF80007C8[0:0] = 0x00000000U | ||
12154 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12155 | // .. L0_SEL = 0 | ||
12156 | // .. ==> 0XF80007C8[1:1] = 0x00000000U | ||
12157 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12158 | // .. L1_SEL = 0 | ||
12159 | // .. ==> 0XF80007C8[2:2] = 0x00000000U | ||
12160 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12161 | // .. L2_SEL = 0 | ||
12162 | // .. ==> 0XF80007C8[4:3] = 0x00000000U | ||
12163 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12164 | // .. L3_SEL = 0 | ||
12165 | // .. ==> 0XF80007C8[7:5] = 0x00000000U | ||
12166 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
12167 | // .. Speed = 0 | ||
12168 | // .. ==> 0XF80007C8[8:8] = 0x00000000U | ||
12169 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12170 | // .. IO_Type = 1 | ||
12171 | // .. ==> 0XF80007C8[11:9] = 0x00000001U | ||
12172 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12173 | // .. PULLUP = 0 | ||
12174 | // .. ==> 0XF80007C8[12:12] = 0x00000000U | ||
12175 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12176 | // .. DisableRcvr = 0 | ||
12177 | // .. ==> 0XF80007C8[13:13] = 0x00000000U | ||
12178 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12179 | // .. | ||
12180 | EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U), | ||
12181 | // .. TRI_ENABLE = 0 | ||
12182 | // .. ==> 0XF80007CC[0:0] = 0x00000000U | ||
12183 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12184 | // .. L0_SEL = 0 | ||
12185 | // .. ==> 0XF80007CC[1:1] = 0x00000000U | ||
12186 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12187 | // .. L1_SEL = 0 | ||
12188 | // .. ==> 0XF80007CC[2:2] = 0x00000000U | ||
12189 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12190 | // .. L2_SEL = 0 | ||
12191 | // .. ==> 0XF80007CC[4:3] = 0x00000000U | ||
12192 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12193 | // .. L3_SEL = 0 | ||
12194 | // .. ==> 0XF80007CC[7:5] = 0x00000000U | ||
12195 | // .. ==> MASK : 0x000000E0U VAL : 0x00000000U | ||
12196 | // .. Speed = 0 | ||
12197 | // .. ==> 0XF80007CC[8:8] = 0x00000000U | ||
12198 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12199 | // .. IO_Type = 1 | ||
12200 | // .. ==> 0XF80007CC[11:9] = 0x00000001U | ||
12201 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12202 | // .. PULLUP = 0 | ||
12203 | // .. ==> 0XF80007CC[12:12] = 0x00000000U | ||
12204 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12205 | // .. DisableRcvr = 0 | ||
12206 | // .. ==> 0XF80007CC[13:13] = 0x00000000U | ||
12207 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12208 | // .. | ||
12209 | EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U), | ||
12210 | // .. TRI_ENABLE = 0 | ||
12211 | // .. ==> 0XF80007D0[0:0] = 0x00000000U | ||
12212 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12213 | // .. L0_SEL = 0 | ||
12214 | // .. ==> 0XF80007D0[1:1] = 0x00000000U | ||
12215 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12216 | // .. L1_SEL = 0 | ||
12217 | // .. ==> 0XF80007D0[2:2] = 0x00000000U | ||
12218 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12219 | // .. L2_SEL = 0 | ||
12220 | // .. ==> 0XF80007D0[4:3] = 0x00000000U | ||
12221 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12222 | // .. L3_SEL = 4 | ||
12223 | // .. ==> 0XF80007D0[7:5] = 0x00000004U | ||
12224 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
12225 | // .. Speed = 0 | ||
12226 | // .. ==> 0XF80007D0[8:8] = 0x00000000U | ||
12227 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12228 | // .. IO_Type = 1 | ||
12229 | // .. ==> 0XF80007D0[11:9] = 0x00000001U | ||
12230 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12231 | // .. PULLUP = 0 | ||
12232 | // .. ==> 0XF80007D0[12:12] = 0x00000000U | ||
12233 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12234 | // .. DisableRcvr = 0 | ||
12235 | // .. ==> 0XF80007D0[13:13] = 0x00000000U | ||
12236 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12237 | // .. | ||
12238 | EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), | ||
12239 | // .. TRI_ENABLE = 0 | ||
12240 | // .. ==> 0XF80007D4[0:0] = 0x00000000U | ||
12241 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12242 | // .. L0_SEL = 0 | ||
12243 | // .. ==> 0XF80007D4[1:1] = 0x00000000U | ||
12244 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12245 | // .. L1_SEL = 0 | ||
12246 | // .. ==> 0XF80007D4[2:2] = 0x00000000U | ||
12247 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12248 | // .. L2_SEL = 0 | ||
12249 | // .. ==> 0XF80007D4[4:3] = 0x00000000U | ||
12250 | // .. ==> MASK : 0x00000018U VAL : 0x00000000U | ||
12251 | // .. L3_SEL = 4 | ||
12252 | // .. ==> 0XF80007D4[7:5] = 0x00000004U | ||
12253 | // .. ==> MASK : 0x000000E0U VAL : 0x00000080U | ||
12254 | // .. Speed = 0 | ||
12255 | // .. ==> 0XF80007D4[8:8] = 0x00000000U | ||
12256 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12257 | // .. IO_Type = 1 | ||
12258 | // .. ==> 0XF80007D4[11:9] = 0x00000001U | ||
12259 | // .. ==> MASK : 0x00000E00U VAL : 0x00000200U | ||
12260 | // .. PULLUP = 0 | ||
12261 | // .. ==> 0XF80007D4[12:12] = 0x00000000U | ||
12262 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12263 | // .. DisableRcvr = 0 | ||
12264 | // .. ==> 0XF80007D4[13:13] = 0x00000000U | ||
12265 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12266 | // .. | ||
12267 | EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), | ||
12268 | // .. SDIO1_CD_SEL = 58 | ||
12269 | // .. ==> 0XF8000834[21:16] = 0x0000003AU | ||
12270 | // .. ==> MASK : 0x003F0000U VAL : 0x003A0000U | ||
12271 | // .. | ||
12272 | EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U), | ||
12273 | // .. FINISH: MIO PROGRAMMING | ||
12274 | // .. START: LOCK IT BACK | ||
12275 | // .. LOCK_KEY = 0X767B | ||
12276 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
12277 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
12278 | // .. | ||
12279 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
12280 | // .. FINISH: LOCK IT BACK | ||
12281 | // FINISH: top | ||
12282 | // | ||
12283 | EMIT_EXIT(), | ||
12284 | |||
12285 | // | ||
12286 | }; | ||
12287 | |||
12288 | unsigned long ps7_peripherals_init_data_1_0[] = { | ||
12289 | // START: top | ||
12290 | // .. START: SLCR SETTINGS | ||
12291 | // .. UNLOCK_KEY = 0XDF0D | ||
12292 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
12293 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
12294 | // .. | ||
12295 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
12296 | // .. FINISH: SLCR SETTINGS | ||
12297 | // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
12298 | // .. IBUF_DISABLE_MODE = 0x1 | ||
12299 | // .. ==> 0XF8000B48[7:7] = 0x00000001U | ||
12300 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
12301 | // .. TERM_DISABLE_MODE = 0x1 | ||
12302 | // .. ==> 0XF8000B48[8:8] = 0x00000001U | ||
12303 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
12304 | // .. | ||
12305 | EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), | ||
12306 | // .. IBUF_DISABLE_MODE = 0x1 | ||
12307 | // .. ==> 0XF8000B4C[7:7] = 0x00000001U | ||
12308 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
12309 | // .. TERM_DISABLE_MODE = 0x1 | ||
12310 | // .. ==> 0XF8000B4C[8:8] = 0x00000001U | ||
12311 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
12312 | // .. | ||
12313 | EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), | ||
12314 | // .. IBUF_DISABLE_MODE = 0x1 | ||
12315 | // .. ==> 0XF8000B50[7:7] = 0x00000001U | ||
12316 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
12317 | // .. TERM_DISABLE_MODE = 0x1 | ||
12318 | // .. ==> 0XF8000B50[8:8] = 0x00000001U | ||
12319 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
12320 | // .. | ||
12321 | EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), | ||
12322 | // .. IBUF_DISABLE_MODE = 0x1 | ||
12323 | // .. ==> 0XF8000B54[7:7] = 0x00000001U | ||
12324 | // .. ==> MASK : 0x00000080U VAL : 0x00000080U | ||
12325 | // .. TERM_DISABLE_MODE = 0x1 | ||
12326 | // .. ==> 0XF8000B54[8:8] = 0x00000001U | ||
12327 | // .. ==> MASK : 0x00000100U VAL : 0x00000100U | ||
12328 | // .. | ||
12329 | EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), | ||
12330 | // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS | ||
12331 | // .. START: LOCK IT BACK | ||
12332 | // .. LOCK_KEY = 0X767B | ||
12333 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
12334 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
12335 | // .. | ||
12336 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
12337 | // .. FINISH: LOCK IT BACK | ||
12338 | // .. START: SRAM/NOR SET OPMODE | ||
12339 | // .. FINISH: SRAM/NOR SET OPMODE | ||
12340 | // .. START: UART REGISTERS | ||
12341 | // .. BDIV = 0x6 | ||
12342 | // .. ==> 0XE0001034[7:0] = 0x00000006U | ||
12343 | // .. ==> MASK : 0x000000FFU VAL : 0x00000006U | ||
12344 | // .. | ||
12345 | EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), | ||
12346 | // .. CD = 0x3e | ||
12347 | // .. ==> 0XE0001018[15:0] = 0x0000003EU | ||
12348 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU | ||
12349 | // .. | ||
12350 | EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), | ||
12351 | // .. STPBRK = 0x0 | ||
12352 | // .. ==> 0XE0001000[8:8] = 0x00000000U | ||
12353 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12354 | // .. STTBRK = 0x0 | ||
12355 | // .. ==> 0XE0001000[7:7] = 0x00000000U | ||
12356 | // .. ==> MASK : 0x00000080U VAL : 0x00000000U | ||
12357 | // .. RSTTO = 0x0 | ||
12358 | // .. ==> 0XE0001000[6:6] = 0x00000000U | ||
12359 | // .. ==> MASK : 0x00000040U VAL : 0x00000000U | ||
12360 | // .. TXDIS = 0x0 | ||
12361 | // .. ==> 0XE0001000[5:5] = 0x00000000U | ||
12362 | // .. ==> MASK : 0x00000020U VAL : 0x00000000U | ||
12363 | // .. TXEN = 0x1 | ||
12364 | // .. ==> 0XE0001000[4:4] = 0x00000001U | ||
12365 | // .. ==> MASK : 0x00000010U VAL : 0x00000010U | ||
12366 | // .. RXDIS = 0x0 | ||
12367 | // .. ==> 0XE0001000[3:3] = 0x00000000U | ||
12368 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
12369 | // .. RXEN = 0x1 | ||
12370 | // .. ==> 0XE0001000[2:2] = 0x00000001U | ||
12371 | // .. ==> MASK : 0x00000004U VAL : 0x00000004U | ||
12372 | // .. TXRES = 0x1 | ||
12373 | // .. ==> 0XE0001000[1:1] = 0x00000001U | ||
12374 | // .. ==> MASK : 0x00000002U VAL : 0x00000002U | ||
12375 | // .. RXRES = 0x1 | ||
12376 | // .. ==> 0XE0001000[0:0] = 0x00000001U | ||
12377 | // .. ==> MASK : 0x00000001U VAL : 0x00000001U | ||
12378 | // .. | ||
12379 | EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), | ||
12380 | // .. IRMODE = 0x0 | ||
12381 | // .. ==> 0XE0001004[11:11] = 0x00000000U | ||
12382 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
12383 | // .. UCLKEN = 0x0 | ||
12384 | // .. ==> 0XE0001004[10:10] = 0x00000000U | ||
12385 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
12386 | // .. CHMODE = 0x0 | ||
12387 | // .. ==> 0XE0001004[9:8] = 0x00000000U | ||
12388 | // .. ==> MASK : 0x00000300U VAL : 0x00000000U | ||
12389 | // .. NBSTOP = 0x0 | ||
12390 | // .. ==> 0XE0001004[7:6] = 0x00000000U | ||
12391 | // .. ==> MASK : 0x000000C0U VAL : 0x00000000U | ||
12392 | // .. PAR = 0x4 | ||
12393 | // .. ==> 0XE0001004[5:3] = 0x00000004U | ||
12394 | // .. ==> MASK : 0x00000038U VAL : 0x00000020U | ||
12395 | // .. CHRL = 0x0 | ||
12396 | // .. ==> 0XE0001004[2:1] = 0x00000000U | ||
12397 | // .. ==> MASK : 0x00000006U VAL : 0x00000000U | ||
12398 | // .. CLKS = 0x0 | ||
12399 | // .. ==> 0XE0001004[0:0] = 0x00000000U | ||
12400 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12401 | // .. | ||
12402 | EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), | ||
12403 | // .. FINISH: UART REGISTERS | ||
12404 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
12405 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
12406 | // .. .. a = 0XC5ACCE55 | ||
12407 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
12408 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
12409 | // .. .. | ||
12410 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
12411 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
12412 | // .. .. START: TRACE CURRENT PORT SIZE | ||
12413 | // .. .. a = 2 | ||
12414 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
12415 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
12416 | // .. .. | ||
12417 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
12418 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
12419 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
12420 | // .. .. a = 0X0 | ||
12421 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
12422 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
12423 | // .. .. | ||
12424 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
12425 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
12426 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
12427 | // .. START: QSPI REGISTERS | ||
12428 | // .. Holdb_dr = 1 | ||
12429 | // .. ==> 0XE000D000[19:19] = 0x00000001U | ||
12430 | // .. ==> MASK : 0x00080000U VAL : 0x00080000U | ||
12431 | // .. | ||
12432 | EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), | ||
12433 | // .. FINISH: QSPI REGISTERS | ||
12434 | // .. START: PL POWER ON RESET REGISTERS | ||
12435 | // .. PCFG_POR_CNT_4K = 0 | ||
12436 | // .. ==> 0XF8007000[29:29] = 0x00000000U | ||
12437 | // .. ==> MASK : 0x20000000U VAL : 0x00000000U | ||
12438 | // .. | ||
12439 | EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), | ||
12440 | // .. FINISH: PL POWER ON RESET REGISTERS | ||
12441 | // .. START: SMC TIMING CALCULATION REGISTER UPDATE | ||
12442 | // .. .. START: NAND SET CYCLE | ||
12443 | // .. .. FINISH: NAND SET CYCLE | ||
12444 | // .. .. START: OPMODE | ||
12445 | // .. .. FINISH: OPMODE | ||
12446 | // .. .. START: DIRECT COMMAND | ||
12447 | // .. .. FINISH: DIRECT COMMAND | ||
12448 | // .. .. START: SRAM/NOR CS0 SET CYCLE | ||
12449 | // .. .. FINISH: SRAM/NOR CS0 SET CYCLE | ||
12450 | // .. .. START: DIRECT COMMAND | ||
12451 | // .. .. FINISH: DIRECT COMMAND | ||
12452 | // .. .. START: NOR CS0 BASE ADDRESS | ||
12453 | // .. .. FINISH: NOR CS0 BASE ADDRESS | ||
12454 | // .. .. START: SRAM/NOR CS1 SET CYCLE | ||
12455 | // .. .. FINISH: SRAM/NOR CS1 SET CYCLE | ||
12456 | // .. .. START: DIRECT COMMAND | ||
12457 | // .. .. FINISH: DIRECT COMMAND | ||
12458 | // .. .. START: NOR CS1 BASE ADDRESS | ||
12459 | // .. .. FINISH: NOR CS1 BASE ADDRESS | ||
12460 | // .. .. START: USB RESET | ||
12461 | // .. .. .. START: USB0 RESET | ||
12462 | // .. .. .. .. START: DIR MODE BANK 0 | ||
12463 | // .. .. .. .. DIRECTION_0 = 0x80 | ||
12464 | // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U | ||
12465 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
12466 | // .. .. .. .. | ||
12467 | EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), | ||
12468 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
12469 | // .. .. .. .. START: DIR MODE BANK 1 | ||
12470 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
12471 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12472 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
12473 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
12474 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
12475 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
12476 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
12477 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
12478 | // .. .. .. .. | ||
12479 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
12480 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12481 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12482 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12483 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12484 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12485 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12486 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12487 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
12488 | // .. .. .. .. OP_ENABLE_0 = 0x80 | ||
12489 | // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U | ||
12490 | // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U | ||
12491 | // .. .. .. .. | ||
12492 | EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), | ||
12493 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
12494 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
12495 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
12496 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12497 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
12498 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
12499 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
12500 | // .. .. .. .. DATA_0_LSW = 0x0 | ||
12501 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U | ||
12502 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U | ||
12503 | // .. .. .. .. | ||
12504 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), | ||
12505 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12506 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12507 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12508 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12509 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12510 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12511 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12512 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12513 | // .. .. .. .. | ||
12514 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12515 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12516 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12517 | // .. .. .. .. MASK_0_LSW = 0xff7f | ||
12518 | // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU | ||
12519 | // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U | ||
12520 | // .. .. .. .. DATA_0_LSW = 0x80 | ||
12521 | // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U | ||
12522 | // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U | ||
12523 | // .. .. .. .. | ||
12524 | EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), | ||
12525 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12526 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12527 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12528 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12529 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12530 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12531 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12532 | // .. .. .. FINISH: USB0 RESET | ||
12533 | // .. .. .. START: USB1 RESET | ||
12534 | // .. .. .. .. START: DIR MODE BANK 0 | ||
12535 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
12536 | // .. .. .. .. START: DIR MODE BANK 1 | ||
12537 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
12538 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12539 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12540 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12541 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12542 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12543 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12544 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12545 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12546 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
12547 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
12548 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
12549 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
12550 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12551 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12552 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12553 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12554 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12555 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12556 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12557 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12558 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12559 | // .. .. .. .. | ||
12560 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12561 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12562 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12563 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12564 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12565 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12566 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12567 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12568 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12569 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12570 | // .. .. .. FINISH: USB1 RESET | ||
12571 | // .. .. FINISH: USB RESET | ||
12572 | // .. .. START: ENET RESET | ||
12573 | // .. .. .. START: ENET0 RESET | ||
12574 | // .. .. .. .. START: DIR MODE BANK 0 | ||
12575 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
12576 | // .. .. .. .. START: DIR MODE BANK 1 | ||
12577 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
12578 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12579 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12580 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12581 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12582 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12583 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12584 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12585 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12586 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
12587 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
12588 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
12589 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
12590 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12591 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12592 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12593 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12594 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12595 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12596 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12597 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12598 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12599 | // .. .. .. .. | ||
12600 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12601 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12602 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12603 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12604 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12605 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12606 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12607 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12608 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12609 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12610 | // .. .. .. FINISH: ENET0 RESET | ||
12611 | // .. .. .. START: ENET1 RESET | ||
12612 | // .. .. .. .. START: DIR MODE BANK 0 | ||
12613 | // .. .. .. .. FINISH: DIR MODE BANK 0 | ||
12614 | // .. .. .. .. START: DIR MODE BANK 1 | ||
12615 | // .. .. .. .. FINISH: DIR MODE BANK 1 | ||
12616 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12617 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12618 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12619 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12620 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12621 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12622 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12623 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12624 | // .. .. .. .. START: OUTPUT ENABLE BANK 0 | ||
12625 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
12626 | // .. .. .. .. START: OUTPUT ENABLE BANK 1 | ||
12627 | // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 | ||
12628 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12629 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12630 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12631 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12632 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12633 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12634 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12635 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12636 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12637 | // .. .. .. .. | ||
12638 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12639 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12640 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12641 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12642 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12643 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12644 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12645 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12646 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12647 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12648 | // .. .. .. FINISH: ENET1 RESET | ||
12649 | // .. .. FINISH: ENET RESET | ||
12650 | // .. .. START: I2C RESET | ||
12651 | // .. .. .. START: I2C0 RESET | ||
12652 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
12653 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
12654 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
12655 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
12656 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12657 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12658 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12659 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12660 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12661 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12662 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12663 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12664 | // .. .. .. .. START: OUTPUT ENABLE | ||
12665 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
12666 | // .. .. .. .. START: OUTPUT ENABLE | ||
12667 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
12668 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12669 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12670 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12671 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12672 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12673 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12674 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12675 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12676 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12677 | // .. .. .. .. | ||
12678 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12679 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12680 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12681 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12682 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12683 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12684 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12685 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12686 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12687 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12688 | // .. .. .. FINISH: I2C0 RESET | ||
12689 | // .. .. .. START: I2C1 RESET | ||
12690 | // .. .. .. .. START: DIR MODE GPIO BANK0 | ||
12691 | // .. .. .. .. FINISH: DIR MODE GPIO BANK0 | ||
12692 | // .. .. .. .. START: DIR MODE GPIO BANK1 | ||
12693 | // .. .. .. .. FINISH: DIR MODE GPIO BANK1 | ||
12694 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12695 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12696 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12697 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12698 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12699 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12700 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12701 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12702 | // .. .. .. .. START: OUTPUT ENABLE | ||
12703 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
12704 | // .. .. .. .. START: OUTPUT ENABLE | ||
12705 | // .. .. .. .. FINISH: OUTPUT ENABLE | ||
12706 | // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12707 | // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] | ||
12708 | // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12709 | // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] | ||
12710 | // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12711 | // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] | ||
12712 | // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12713 | // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] | ||
12714 | // .. .. .. .. START: ADD 1 MS DELAY | ||
12715 | // .. .. .. .. | ||
12716 | EMIT_MASKDELAY(0XF8F00200, 1), | ||
12717 | // .. .. .. .. FINISH: ADD 1 MS DELAY | ||
12718 | // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12719 | // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12720 | // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12721 | // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] | ||
12722 | // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12723 | // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] | ||
12724 | // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12725 | // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] | ||
12726 | // .. .. .. FINISH: I2C1 RESET | ||
12727 | // .. .. FINISH: I2C RESET | ||
12728 | // .. .. START: NOR CHIP SELECT | ||
12729 | // .. .. .. START: DIR MODE BANK 0 | ||
12730 | // .. .. .. FINISH: DIR MODE BANK 0 | ||
12731 | // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12732 | // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] | ||
12733 | // .. .. .. START: OUTPUT ENABLE BANK 0 | ||
12734 | // .. .. .. FINISH: OUTPUT ENABLE BANK 0 | ||
12735 | // .. .. FINISH: NOR CHIP SELECT | ||
12736 | // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE | ||
12737 | // FINISH: top | ||
12738 | // | ||
12739 | EMIT_EXIT(), | ||
12740 | |||
12741 | // | ||
12742 | }; | ||
12743 | |||
12744 | unsigned long ps7_post_config_1_0[] = { | ||
12745 | // START: top | ||
12746 | // .. START: SLCR SETTINGS | ||
12747 | // .. UNLOCK_KEY = 0XDF0D | ||
12748 | // .. ==> 0XF8000008[15:0] = 0x0000DF0DU | ||
12749 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU | ||
12750 | // .. | ||
12751 | EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), | ||
12752 | // .. FINISH: SLCR SETTINGS | ||
12753 | // .. START: ENABLING LEVEL SHIFTER | ||
12754 | // .. USER_INP_ICT_EN_0 = 3 | ||
12755 | // .. ==> 0XF8000900[1:0] = 0x00000003U | ||
12756 | // .. ==> MASK : 0x00000003U VAL : 0x00000003U | ||
12757 | // .. USER_INP_ICT_EN_1 = 3 | ||
12758 | // .. ==> 0XF8000900[3:2] = 0x00000003U | ||
12759 | // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU | ||
12760 | // .. | ||
12761 | EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), | ||
12762 | // .. FINISH: ENABLING LEVEL SHIFTER | ||
12763 | // .. START: TPIU WIDTH IN CASE OF EMIO | ||
12764 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
12765 | // .. .. a = 0XC5ACCE55 | ||
12766 | // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U | ||
12767 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
12768 | // .. .. | ||
12769 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
12770 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
12771 | // .. .. START: TRACE CURRENT PORT SIZE | ||
12772 | // .. .. a = 2 | ||
12773 | // .. .. ==> 0XF8803004[31:0] = 0x00000002U | ||
12774 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U | ||
12775 | // .. .. | ||
12776 | EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U), | ||
12777 | // .. .. FINISH: TRACE CURRENT PORT SIZE | ||
12778 | // .. .. START: TRACE LOCK ACCESS REGISTER | ||
12779 | // .. .. a = 0X0 | ||
12780 | // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U | ||
12781 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U | ||
12782 | // .. .. | ||
12783 | EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U), | ||
12784 | // .. .. FINISH: TRACE LOCK ACCESS REGISTER | ||
12785 | // .. FINISH: TPIU WIDTH IN CASE OF EMIO | ||
12786 | // .. START: FPGA RESETS TO 0 | ||
12787 | // .. reserved_3 = 0 | ||
12788 | // .. ==> 0XF8000240[31:25] = 0x00000000U | ||
12789 | // .. ==> MASK : 0xFE000000U VAL : 0x00000000U | ||
12790 | // .. FPGA_ACP_RST = 0 | ||
12791 | // .. ==> 0XF8000240[24:24] = 0x00000000U | ||
12792 | // .. ==> MASK : 0x01000000U VAL : 0x00000000U | ||
12793 | // .. FPGA_AXDS3_RST = 0 | ||
12794 | // .. ==> 0XF8000240[23:23] = 0x00000000U | ||
12795 | // .. ==> MASK : 0x00800000U VAL : 0x00000000U | ||
12796 | // .. FPGA_AXDS2_RST = 0 | ||
12797 | // .. ==> 0XF8000240[22:22] = 0x00000000U | ||
12798 | // .. ==> MASK : 0x00400000U VAL : 0x00000000U | ||
12799 | // .. FPGA_AXDS1_RST = 0 | ||
12800 | // .. ==> 0XF8000240[21:21] = 0x00000000U | ||
12801 | // .. ==> MASK : 0x00200000U VAL : 0x00000000U | ||
12802 | // .. FPGA_AXDS0_RST = 0 | ||
12803 | // .. ==> 0XF8000240[20:20] = 0x00000000U | ||
12804 | // .. ==> MASK : 0x00100000U VAL : 0x00000000U | ||
12805 | // .. reserved_2 = 0 | ||
12806 | // .. ==> 0XF8000240[19:18] = 0x00000000U | ||
12807 | // .. ==> MASK : 0x000C0000U VAL : 0x00000000U | ||
12808 | // .. FSSW1_FPGA_RST = 0 | ||
12809 | // .. ==> 0XF8000240[17:17] = 0x00000000U | ||
12810 | // .. ==> MASK : 0x00020000U VAL : 0x00000000U | ||
12811 | // .. FSSW0_FPGA_RST = 0 | ||
12812 | // .. ==> 0XF8000240[16:16] = 0x00000000U | ||
12813 | // .. ==> MASK : 0x00010000U VAL : 0x00000000U | ||
12814 | // .. reserved_1 = 0 | ||
12815 | // .. ==> 0XF8000240[15:14] = 0x00000000U | ||
12816 | // .. ==> MASK : 0x0000C000U VAL : 0x00000000U | ||
12817 | // .. FPGA_FMSW1_RST = 0 | ||
12818 | // .. ==> 0XF8000240[13:13] = 0x00000000U | ||
12819 | // .. ==> MASK : 0x00002000U VAL : 0x00000000U | ||
12820 | // .. FPGA_FMSW0_RST = 0 | ||
12821 | // .. ==> 0XF8000240[12:12] = 0x00000000U | ||
12822 | // .. ==> MASK : 0x00001000U VAL : 0x00000000U | ||
12823 | // .. FPGA_DMA3_RST = 0 | ||
12824 | // .. ==> 0XF8000240[11:11] = 0x00000000U | ||
12825 | // .. ==> MASK : 0x00000800U VAL : 0x00000000U | ||
12826 | // .. FPGA_DMA2_RST = 0 | ||
12827 | // .. ==> 0XF8000240[10:10] = 0x00000000U | ||
12828 | // .. ==> MASK : 0x00000400U VAL : 0x00000000U | ||
12829 | // .. FPGA_DMA1_RST = 0 | ||
12830 | // .. ==> 0XF8000240[9:9] = 0x00000000U | ||
12831 | // .. ==> MASK : 0x00000200U VAL : 0x00000000U | ||
12832 | // .. FPGA_DMA0_RST = 0 | ||
12833 | // .. ==> 0XF8000240[8:8] = 0x00000000U | ||
12834 | // .. ==> MASK : 0x00000100U VAL : 0x00000000U | ||
12835 | // .. reserved = 0 | ||
12836 | // .. ==> 0XF8000240[7:4] = 0x00000000U | ||
12837 | // .. ==> MASK : 0x000000F0U VAL : 0x00000000U | ||
12838 | // .. FPGA3_OUT_RST = 0 | ||
12839 | // .. ==> 0XF8000240[3:3] = 0x00000000U | ||
12840 | // .. ==> MASK : 0x00000008U VAL : 0x00000000U | ||
12841 | // .. FPGA2_OUT_RST = 0 | ||
12842 | // .. ==> 0XF8000240[2:2] = 0x00000000U | ||
12843 | // .. ==> MASK : 0x00000004U VAL : 0x00000000U | ||
12844 | // .. FPGA1_OUT_RST = 0 | ||
12845 | // .. ==> 0XF8000240[1:1] = 0x00000000U | ||
12846 | // .. ==> MASK : 0x00000002U VAL : 0x00000000U | ||
12847 | // .. FPGA0_OUT_RST = 0 | ||
12848 | // .. ==> 0XF8000240[0:0] = 0x00000000U | ||
12849 | // .. ==> MASK : 0x00000001U VAL : 0x00000000U | ||
12850 | // .. | ||
12851 | EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), | ||
12852 | // .. FINISH: FPGA RESETS TO 0 | ||
12853 | // .. START: AFI REGISTERS | ||
12854 | // .. .. START: AFI0 REGISTERS | ||
12855 | // .. .. FINISH: AFI0 REGISTERS | ||
12856 | // .. .. START: AFI1 REGISTERS | ||
12857 | // .. .. FINISH: AFI1 REGISTERS | ||
12858 | // .. .. START: AFI2 REGISTERS | ||
12859 | // .. .. FINISH: AFI2 REGISTERS | ||
12860 | // .. .. START: AFI3 REGISTERS | ||
12861 | // .. .. FINISH: AFI3 REGISTERS | ||
12862 | // .. FINISH: AFI REGISTERS | ||
12863 | // .. START: LOCK IT BACK | ||
12864 | // .. LOCK_KEY = 0X767B | ||
12865 | // .. ==> 0XF8000004[15:0] = 0x0000767BU | ||
12866 | // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU | ||
12867 | // .. | ||
12868 | EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), | ||
12869 | // .. FINISH: LOCK IT BACK | ||
12870 | // FINISH: top | ||
12871 | // | ||
12872 | EMIT_EXIT(), | ||
12873 | |||
12874 | // | ||
12875 | }; | ||
12876 | |||
12877 | unsigned long ps7_debug_1_0[] = { | ||
12878 | // START: top | ||
12879 | // .. START: CROSS TRIGGER CONFIGURATIONS | ||
12880 | // .. .. START: UNLOCKING CTI REGISTERS | ||
12881 | // .. .. KEY = 0XC5ACCE55 | ||
12882 | // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U | ||
12883 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
12884 | // .. .. | ||
12885 | EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
12886 | // .. .. KEY = 0XC5ACCE55 | ||
12887 | // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U | ||
12888 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
12889 | // .. .. | ||
12890 | EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
12891 | // .. .. KEY = 0XC5ACCE55 | ||
12892 | // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U | ||
12893 | // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U | ||
12894 | // .. .. | ||
12895 | EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), | ||
12896 | // .. .. FINISH: UNLOCKING CTI REGISTERS | ||
12897 | // .. .. START: ENABLING CTI MODULES AND CHANNELS | ||
12898 | // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS | ||
12899 | // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
12900 | // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS | ||
12901 | // .. FINISH: CROSS TRIGGER CONFIGURATIONS | ||
12902 | // FINISH: top | ||
12903 | // | ||
12904 | EMIT_EXIT(), | ||
12905 | |||
12906 | // | ||
12907 | }; | ||
12908 | |||
12909 | |||
12910 | #include "xil_io.h" | ||
12911 | #define PS7_MASK_POLL_TIME 100000000 | ||
12912 | |||
12913 | char* | ||
12914 | getPS7MessageInfo(unsigned key) { | ||
12915 | |||
12916 | char* err_msg = ""; | ||
12917 | switch (key) { | ||
12918 | case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; | ||
12919 | case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; | ||
12920 | case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; | ||
12921 | case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; | ||
12922 | case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; | ||
12923 | case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; | ||
12924 | default: err_msg = "Undefined error status"; break; | ||
12925 | } | ||
12926 | |||
12927 | return err_msg; | ||
12928 | } | ||
12929 | |||
12930 | unsigned long | ||
12931 | ps7GetSiliconVersion () { | ||
12932 | // Read PS version from MCTRL register [31:28] | ||
12933 | unsigned long mask = 0xF0000000; | ||
12934 | unsigned long *addr = (unsigned long*) 0XF8007080; | ||
12935 | unsigned long ps_version = (*addr & mask) >> 28; | ||
12936 | return ps_version; | ||
12937 | } | ||
12938 | |||
12939 | void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { | ||
12940 | unsigned long *addr = (unsigned long*) add; | ||
12941 | *addr = ( val & mask ) | ( *addr & ~mask); | ||
12942 | //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); | ||
12943 | } | ||
12944 | |||
12945 | |||
12946 | int mask_poll(unsigned long add , unsigned long mask ) { | ||
12947 | volatile unsigned long *addr = (volatile unsigned long*) add; | ||
12948 | int i = 0; | ||
12949 | while (!(*addr & mask)) { | ||
12950 | if (i == PS7_MASK_POLL_TIME) { | ||
12951 | return -1; | ||
12952 | } | ||
12953 | i++; | ||
12954 | } | ||
12955 | return 1; | ||
12956 | //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); | ||
12957 | } | ||
12958 | |||
12959 | unsigned long mask_read(unsigned long add , unsigned long mask ) { | ||
12960 | unsigned long *addr = (unsigned long*) add; | ||
12961 | unsigned long val = (*addr & mask); | ||
12962 | //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); | ||
12963 | return val; | ||
12964 | } | ||
12965 | |||
12966 | |||
12967 | |||
12968 | int | ||
12969 | ps7_config(unsigned long * ps7_config_init) | ||
12970 | { | ||
12971 | unsigned long *ptr = ps7_config_init; | ||
12972 | |||
12973 | unsigned long opcode; // current instruction .. | ||
12974 | unsigned long args[16]; // no opcode has so many args ... | ||
12975 | int numargs; // number of arguments of this instruction | ||
12976 | int j; // general purpose index | ||
12977 | |||
12978 | volatile unsigned long *addr; // some variable to make code readable | ||
12979 | unsigned long val,mask; // some variable to make code readable | ||
12980 | |||
12981 | int finish = -1 ; // loop while this is negative ! | ||
12982 | int i = 0; // Timeout variable | ||
12983 | |||
12984 | while( finish < 0 ) { | ||
12985 | numargs = ptr[0] & 0xF; | ||
12986 | opcode = ptr[0] >> 4; | ||
12987 | |||
12988 | for( j = 0 ; j < numargs ; j ++ ) | ||
12989 | args[j] = ptr[j+1]; | ||
12990 | ptr += numargs + 1; | ||
12991 | |||
12992 | |||
12993 | switch ( opcode ) { | ||
12994 | |||
12995 | case OPCODE_EXIT: | ||
12996 | finish = PS7_INIT_SUCCESS; | ||
12997 | break; | ||
12998 | |||
12999 | case OPCODE_CLEAR: | ||
13000 | addr = (unsigned long*) args[0]; | ||
13001 | *addr = 0; | ||
13002 | break; | ||
13003 | |||
13004 | case OPCODE_WRITE: | ||
13005 | addr = (unsigned long*) args[0]; | ||
13006 | val = args[1]; | ||
13007 | *addr = val; | ||
13008 | break; | ||
13009 | |||
13010 | case OPCODE_MASKWRITE: | ||
13011 | addr = (unsigned long*) args[0]; | ||
13012 | mask = args[1]; | ||
13013 | val = args[2]; | ||
13014 | *addr = ( val & mask ) | ( *addr & ~mask); | ||
13015 | break; | ||
13016 | |||
13017 | case OPCODE_MASKPOLL: | ||
13018 | addr = (unsigned long*) args[0]; | ||
13019 | mask = args[1]; | ||
13020 | i = 0; | ||
13021 | while (!(*addr & mask)) { | ||
13022 | if (i == PS7_MASK_POLL_TIME) { | ||
13023 | finish = PS7_INIT_TIMEOUT; | ||
13024 | break; | ||
13025 | } | ||
13026 | i++; | ||
13027 | } | ||
13028 | break; | ||
13029 | case OPCODE_MASKDELAY: | ||
13030 | addr = (unsigned long*) args[0]; | ||
13031 | mask = args[1]; | ||
13032 | int delay = get_number_of_cycles_for_delay(mask); | ||
13033 | perf_reset_and_start_timer(); | ||
13034 | while ((*addr < delay)) { | ||
13035 | } | ||
13036 | break; | ||
13037 | default: | ||
13038 | finish = PS7_INIT_CORRUPT; | ||
13039 | break; | ||
13040 | } | ||
13041 | } | ||
13042 | return finish; | ||
13043 | } | ||
13044 | |||
13045 | unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; | ||
13046 | unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; | ||
13047 | unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; | ||
13048 | unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; | ||
13049 | unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | ||
13050 | |||
13051 | int | ||
13052 | ps7_post_config() | ||
13053 | { | ||
13054 | // Get the PS_VERSION on run time | ||
13055 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
13056 | int ret = -1; | ||
13057 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
13058 | ret = ps7_config (ps7_post_config_1_0); | ||
13059 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13060 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
13061 | ret = ps7_config (ps7_post_config_2_0); | ||
13062 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13063 | } else { | ||
13064 | ret = ps7_config (ps7_post_config_3_0); | ||
13065 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13066 | } | ||
13067 | return PS7_INIT_SUCCESS; | ||
13068 | } | ||
13069 | |||
13070 | int | ||
13071 | ps7_debug() | ||
13072 | { | ||
13073 | // Get the PS_VERSION on run time | ||
13074 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
13075 | int ret = -1; | ||
13076 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
13077 | ret = ps7_config (ps7_debug_1_0); | ||
13078 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13079 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
13080 | ret = ps7_config (ps7_debug_2_0); | ||
13081 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13082 | } else { | ||
13083 | ret = ps7_config (ps7_debug_3_0); | ||
13084 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13085 | } | ||
13086 | return PS7_INIT_SUCCESS; | ||
13087 | } | ||
13088 | |||
13089 | int | ||
13090 | ps7_init() | ||
13091 | { | ||
13092 | // Get the PS_VERSION on run time | ||
13093 | unsigned long si_ver = ps7GetSiliconVersion (); | ||
13094 | int ret; | ||
13095 | //int pcw_ver = 0; | ||
13096 | |||
13097 | if (si_ver == PCW_SILICON_VERSION_1) { | ||
13098 | ps7_mio_init_data = ps7_mio_init_data_1_0; | ||
13099 | ps7_pll_init_data = ps7_pll_init_data_1_0; | ||
13100 | ps7_clock_init_data = ps7_clock_init_data_1_0; | ||
13101 | ps7_ddr_init_data = ps7_ddr_init_data_1_0; | ||
13102 | ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; | ||
13103 | //pcw_ver = 1; | ||
13104 | |||
13105 | } else if (si_ver == PCW_SILICON_VERSION_2) { | ||
13106 | ps7_mio_init_data = ps7_mio_init_data_2_0; | ||
13107 | ps7_pll_init_data = ps7_pll_init_data_2_0; | ||
13108 | ps7_clock_init_data = ps7_clock_init_data_2_0; | ||
13109 | ps7_ddr_init_data = ps7_ddr_init_data_2_0; | ||
13110 | ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; | ||
13111 | //pcw_ver = 2; | ||
13112 | |||
13113 | } else { | ||
13114 | ps7_mio_init_data = ps7_mio_init_data_3_0; | ||
13115 | ps7_pll_init_data = ps7_pll_init_data_3_0; | ||
13116 | ps7_clock_init_data = ps7_clock_init_data_3_0; | ||
13117 | ps7_ddr_init_data = ps7_ddr_init_data_3_0; | ||
13118 | ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; | ||
13119 | //pcw_ver = 3; | ||
13120 | } | ||
13121 | |||
13122 | // MIO init | ||
13123 | ret = ps7_config (ps7_mio_init_data); | ||
13124 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13125 | |||
13126 | // PLL init | ||
13127 | ret = ps7_config (ps7_pll_init_data); | ||
13128 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13129 | |||
13130 | // Clock init | ||
13131 | ret = ps7_config (ps7_clock_init_data); | ||
13132 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13133 | |||
13134 | // DDR init | ||
13135 | ret = ps7_config (ps7_ddr_init_data); | ||
13136 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13137 | |||
13138 | |||
13139 | |||
13140 | // Peripherals init | ||
13141 | ret = ps7_config (ps7_peripherals_init_data); | ||
13142 | if (ret != PS7_INIT_SUCCESS) return ret; | ||
13143 | //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); | ||
13144 | return PS7_INIT_SUCCESS; | ||
13145 | } | ||
13146 | |||
13147 | |||
13148 | |||
13149 | |||
13150 | /* For delay calculation using global timer */ | ||
13151 | |||
13152 | /* start timer */ | ||
13153 | void perf_start_clock(void) | ||
13154 | { | ||
13155 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable | ||
13156 | (1 << 3) | // Auto-increment | ||
13157 | (0 << 8) // Pre-scale | ||
13158 | ); | ||
13159 | } | ||
13160 | |||
13161 | /* stop timer and reset timer count regs */ | ||
13162 | void perf_reset_clock(void) | ||
13163 | { | ||
13164 | perf_disable_clock(); | ||
13165 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; | ||
13166 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; | ||
13167 | } | ||
13168 | |||
13169 | /* Compute mask for given delay in miliseconds*/ | ||
13170 | int get_number_of_cycles_for_delay(unsigned int delay) | ||
13171 | { | ||
13172 | // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) | ||
13173 | return (APU_FREQ*delay/(2*1000)); | ||
13174 | |||
13175 | } | ||
13176 | |||
13177 | /* stop timer */ | ||
13178 | void perf_disable_clock(void) | ||
13179 | { | ||
13180 | *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; | ||
13181 | } | ||
13182 | |||
13183 | void perf_reset_and_start_timer() | ||
13184 | { | ||
13185 | perf_reset_clock(); | ||
13186 | perf_start_clock(); | ||
13187 | } | ||
13188 | |||
13189 | |||
13190 | |||
13191 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h deleted file mode 100644 index df5205e8..00000000 --- a/meta-xilinx-bsp/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h +++ /dev/null | |||
@@ -1,130 +0,0 @@ | |||
1 | |||
2 | /****************************************************************************** | ||
3 | * | ||
4 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, see <http://www.gnu.org/licenses/> | ||
18 | * | ||
19 | * | ||
20 | *******************************************************************************/ | ||
21 | /****************************************************************************/ | ||
22 | /** | ||
23 | * | ||
24 | * @file ps7_init.h | ||
25 | * | ||
26 | * This file can be included in FSBL code | ||
27 | * to get prototype of ps7_init() function | ||
28 | * and error codes | ||
29 | * | ||
30 | *****************************************************************************/ | ||
31 | |||
32 | #ifdef __cplusplus | ||
33 | extern "C" { | ||
34 | #endif | ||
35 | |||
36 | |||
37 | //typedef unsigned int u32; | ||
38 | |||
39 | |||
40 | /** do we need to make this name more unique ? **/ | ||
41 | //extern u32 ps7_init_data[]; | ||
42 | extern unsigned long * ps7_ddr_init_data; | ||
43 | extern unsigned long * ps7_mio_init_data; | ||
44 | extern unsigned long * ps7_pll_init_data; | ||
45 | extern unsigned long * ps7_clock_init_data; | ||
46 | extern unsigned long * ps7_peripherals_init_data; | ||
47 | |||
48 | |||
49 | |||
50 | #define OPCODE_EXIT 0U | ||
51 | #define OPCODE_CLEAR 1U | ||
52 | #define OPCODE_WRITE 2U | ||
53 | #define OPCODE_MASKWRITE 3U | ||
54 | #define OPCODE_MASKPOLL 4U | ||
55 | #define OPCODE_MASKDELAY 5U | ||
56 | #define NEW_PS7_ERR_CODE 1 | ||
57 | |||
58 | /* Encode number of arguments in last nibble */ | ||
59 | #define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) | ||
60 | #define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr | ||
61 | #define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val | ||
62 | #define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val | ||
63 | #define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask | ||
64 | #define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask | ||
65 | |||
66 | /* Returns codes of PS7_Init */ | ||
67 | #define PS7_INIT_SUCCESS (0) // 0 is success in good old C | ||
68 | #define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now | ||
69 | #define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out | ||
70 | #define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init | ||
71 | #define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit | ||
72 | #define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init | ||
73 | |||
74 | |||
75 | /* Silicon Versions */ | ||
76 | #define PCW_SILICON_VERSION_1 0 | ||
77 | #define PCW_SILICON_VERSION_2 1 | ||
78 | #define PCW_SILICON_VERSION_3 2 | ||
79 | |||
80 | /* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ | ||
81 | #define PS7_POST_CONFIG | ||
82 | |||
83 | /* Freq of all peripherals */ | ||
84 | |||
85 | #define APU_FREQ 666666687 | ||
86 | #define DDR_FREQ 533333374 | ||
87 | #define DCI_FREQ 10158731 | ||
88 | #define QSPI_FREQ 200000000 | ||
89 | #define SMC_FREQ 10000000 | ||
90 | #define ENET0_FREQ 125000000 | ||
91 | #define ENET1_FREQ 10000000 | ||
92 | #define USB0_FREQ 60000000 | ||
93 | #define USB1_FREQ 60000000 | ||
94 | #define SDIO_FREQ 50000000 | ||
95 | #define UART_FREQ 50000000 | ||
96 | #define SPI_FREQ 10000000 | ||
97 | #define I2C_FREQ 111111115 | ||
98 | #define WDT_FREQ 111111115 | ||
99 | #define TTC_FREQ 50000000 | ||
100 | #define CAN_FREQ 10000000 | ||
101 | #define PCAP_FREQ 200000000 | ||
102 | #define TPIU_FREQ 200000000 | ||
103 | #define FPGA0_FREQ 100000000 | ||
104 | #define FPGA1_FREQ 100000000 | ||
105 | #define FPGA2_FREQ 33333336 | ||
106 | #define FPGA3_FREQ 50000000 | ||
107 | |||
108 | |||
109 | /* For delay calculation using global registers*/ | ||
110 | #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 | ||
111 | #define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 | ||
112 | #define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 | ||
113 | #define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 | ||
114 | |||
115 | int ps7_config( unsigned long*); | ||
116 | int ps7_init(); | ||
117 | int ps7_post_config(); | ||
118 | int ps7_debug(); | ||
119 | char* getPS7MessageInfo(unsigned key); | ||
120 | |||
121 | void perf_start_clock(void); | ||
122 | void perf_disable_clock(void); | ||
123 | void perf_reset_clock(void); | ||
124 | void perf_reset_and_start_timer(); | ||
125 | int get_number_of_cycles_for_delay(unsigned int delay); | ||
126 | #ifdef __cplusplus | ||
127 | } | ||
128 | #endif | ||
129 | |||
130 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb b/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb deleted file mode 100644 index 195c6309..00000000 --- a/meta-xilinx-bsp/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | SUMMARY = "PMU ROM for QEMU" | ||
2 | DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation" | ||
3 | HOMEPAGE = "http://www.xilinx.com" | ||
4 | SECTION = "bsp" | ||
5 | |||
6 | # The BSP package does not include any license information. | ||
7 | LICENSE = "Proprietary" | ||
8 | LICENSE_FLAGS = "xilinx" | ||
9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" | ||
10 | |||
11 | COMPATIBLE_MACHINE = "zcu102-zynqmp" | ||
12 | |||
13 | inherit deploy | ||
14 | inherit xilinx-fetch-restricted | ||
15 | |||
16 | BSP_NAME = "xilinx-zcu102" | ||
17 | BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" | ||
18 | SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" | ||
19 | SRC_URI[md5sum] = "cea5f11761e7f38cbfcf0a07a19094e0" | ||
20 | SRC_URI[sha256sum] = "7ac0ac3a5fb7dd162c0a922c66edb33b5737955ef6570a1a1d3b15b4344f7cc1" | ||
21 | |||
22 | INHIBIT_DEFAULT_DEPS = "1" | ||
23 | PACKAGE_ARCH = "${MACHINE_ARCH}" | ||
24 | |||
25 | do_compile() { | ||
26 | # Extract the rom into workdir | ||
27 | tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-${PV}/pre-built/linux/images/pmu_rom_qemu_sha3.elf -C ${S} | ||
28 | # tar preserves the tree, so use find to get the full path and move to to the root | ||
29 | for i in $(find ${S} -type f -name *.elf); do mv $i ${S}/pmu-rom.elf; done | ||
30 | } | ||
31 | |||
32 | do_install() { | ||
33 | : | ||
34 | } | ||
35 | |||
36 | do_deploy () { | ||
37 | install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf | ||
38 | } | ||
39 | |||
40 | addtask deploy before do_build after do_install | ||
41 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb deleted file mode 100644 index e512777c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | SUMMARY = "KC705 Pre-built Bitstream" | ||
2 | DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system." | ||
3 | HOMEPAGE = "http://www.xilinx.com" | ||
4 | SECTION = "bsp" | ||
5 | |||
6 | # The BSP package does not include any license information. | ||
7 | LICENSE = "Proprietary" | ||
8 | LICENSE_FLAGS = "xilinx" | ||
9 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28" | ||
10 | |||
11 | COMPATIBLE_MACHINE = "kc705-microblazeel" | ||
12 | |||
13 | inherit deploy | ||
14 | inherit xilinx-fetch-restricted | ||
15 | |||
16 | BSP_NAME = "xilinx-kc705" | ||
17 | BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp" | ||
18 | SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}" | ||
19 | SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351" | ||
20 | SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773" | ||
21 | |||
22 | PROVIDES = "virtual/bitstream" | ||
23 | |||
24 | FILES:${PN} += "/boot/download.bit" | ||
25 | |||
26 | INHIBIT_DEFAULT_DEPS = "1" | ||
27 | PACKAGE_ARCH = "${MACHINE_ARCH}" | ||
28 | |||
29 | # deps needed to extract content from the .bsp file | ||
30 | DEPENDS += "tar-native gzip-native" | ||
31 | |||
32 | do_compile() { | ||
33 | # Extract the bitstream into workdir | ||
34 | tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S} | ||
35 | # move the bit file to ${S}/ as it is in a subdir in the tar file | ||
36 | for i in $(find -type f -name download.bit); do mv $i ${S}; done | ||
37 | } | ||
38 | |||
39 | do_install() { | ||
40 | install -D ${S}/download.bit ${D}/boot/download.bit | ||
41 | } | ||
42 | |||
43 | do_deploy () { | ||
44 | install -D ${S}/download.bit ${DEPLOYDIR}/download.bit | ||
45 | } | ||
46 | |||
47 | addtask deploy before do_build after do_install | ||
48 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch deleted file mode 100644 index 7091098c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | From 8127b19aa42ccfb3faae1173a12b3eb0cebf8941 Mon Sep 17 00:00:00 2001 | ||
2 | From: Peter Robinson <pbrobinson@gmail.com> | ||
3 | Date: Thu, 30 Jan 2020 09:37:15 +0000 | ||
4 | Subject: [PATCH] Remove redundant YYLOC global declaration | ||
5 | |||
6 | Same as the upstream fix for building dtc with gcc 10. | ||
7 | |||
8 | Signed-off-by: Peter Robinson <pbrobinson@gmail.com> | ||
9 | State: upstream (e33a814e772cdc36436c8c188d8c42d019fda639) | ||
10 | --- | ||
11 | scripts/dtc/dtc-lexer.l | 1 - | ||
12 | 1 file changed, 1 deletion(-) | ||
13 | |||
14 | diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l | ||
15 | index fd825ebba6..24af549977 100644 | ||
16 | --- a/scripts/dtc/dtc-lexer.l | ||
17 | +++ b/scripts/dtc/dtc-lexer.l | ||
18 | @@ -38,7 +38,6 @@ LINECOMMENT "//".*\n | ||
19 | #include "srcpos.h" | ||
20 | #include "dtc-parser.tab.h" | ||
21 | |||
22 | -YYLTYPE yylloc; | ||
23 | extern bool treesource_error; | ||
24 | |||
25 | /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ | ||
26 | -- | ||
27 | 2.29.2 | ||
28 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc deleted file mode 100644 index 6638c9e5..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | inherit xilinx-platform-init | ||
2 | |||
3 | FORCE_PLATFORM_INIT[doc] = "This variable is used to force the overriding of all platform init files in u-boot source." | ||
4 | |||
5 | PLATFORM_BOARD_DIR ?= "" | ||
6 | PLATFORM_BOARD_DIR:zynq = "board/xilinx/zynq" | ||
7 | PLATFORM_BOARD_DIR:zynqmp = "board/xilinx/zynqmp" | ||
8 | |||
9 | do_zynq_platform_init() { | ||
10 | for f in ${PLATFORM_INIT_FILES}; do | ||
11 | if [ -d "${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform" ]; then | ||
12 | cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform/ | ||
13 | else | ||
14 | cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/ | ||
15 | fi | ||
16 | # Newer u-boot sources use the init files in a sub directory named | ||
17 | # based on the name of the device tree. This is not straight forward to | ||
18 | # detect. Instead of detecting just overwrite all the platform init | ||
19 | # files so that the correct one is always used. This shotgun approach | ||
20 | # only works due to this recipe being machine arch specific. Do this | ||
21 | # overwrite un-conditionally as there is no guarantees that the chosen | ||
22 | # board config does not have the device tree config set. | ||
23 | for i in ${S}/${PLATFORM_BOARD_DIR}/*/; do | ||
24 | [ -d $i ] && cp ${PLATFORM_INIT_STAGE_DIR}/$f $i | ||
25 | done | ||
26 | done | ||
27 | } | ||
28 | |||
29 | python () { | ||
30 | # strip the tail _config/_defconfig for better comparison | ||
31 | def strip_config_name(c): | ||
32 | for i in ["_config", "_defconfig"]: | ||
33 | if c.endswith(i): | ||
34 | return c[0:len(c) - len(i)] | ||
35 | return c | ||
36 | |||
37 | if d.getVar("SOC_FAMILY") not in ["zynq", "zynqmp"]: | ||
38 | # continue on this is not a zynq/zynqmp target | ||
39 | return | ||
40 | |||
41 | # Determine if target machine needs to provide a custom platform init files | ||
42 | if d.getVar("SPL_BINARY"): | ||
43 | hasconfigs = [strip_config_name(c) for c in (d.getVar("HAS_PLATFORM_INIT") or "").split()] | ||
44 | currentconfig = strip_config_name(d.getVar("UBOOT_MACHINE")) | ||
45 | |||
46 | # only add the dependency if u-boot doesn't already provide the platform init files | ||
47 | if (currentconfig not in hasconfigs) or (d.getVar("FORCE_PLATFORM_INIT") == "1"): | ||
48 | # force the dependency on a recipe that provides the platform init files | ||
49 | d.appendVar("DEPENDS", " virtual/xilinx-platform-init") | ||
50 | # setup task to modify platform init after unpack and prepare_recipe_sysroot, and before configure | ||
51 | bb.build.addtask("do_zynq_platform_init", "do_configure", "do_unpack do_prepare_recipe_sysroot", d) | ||
52 | |||
53 | if "boot.bin" not in d.getVar("SPL_BINARY"): | ||
54 | # not deploying the boot.bin, just building SPL | ||
55 | return | ||
56 | |||
57 | # assume that U-Boot is to provide the boot.bin if no other provides are selected or U-Boot is selected | ||
58 | providesbin = not(d.getVar("PREFERRED_PROVIDER_virtual/boot-bin")) or d.getVar("PREFERRED_PROVIDER_virtual/boot-bin") == d.getVar("PN") | ||
59 | if providesbin: | ||
60 | # add provides, if U-Boot is set to provide boot.bin | ||
61 | d.appendVar("PROVIDES", " virtual/boot-bin") | ||
62 | else: | ||
63 | # prevent U-Boot from deploying the boot.bin | ||
64 | d.setVar("SPL_BINARY", "") | ||
65 | |||
66 | if providesbin and d.getVar("SOC_FAMILY") in ["zynqmp"]: | ||
67 | # setup PMU Firmware path via MAKEFLAGS | ||
68 | d.appendVar("EXTRA_OEMAKE", " CONFIG_PMUFW_INIT_FILE=\"{0}\"".format("${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.bin")) | ||
69 | } | ||
70 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb deleted file mode 100644 index 3e40bfa1..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx-dev.bb +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | # This recipe allows for a 'bleeding edge' u-boot-xlnx build. | ||
2 | # Since this tree is frequently updated, AUTOREV is used to track its contents. | ||
3 | # | ||
4 | # To enable this recipe, set the following in your machine or local.conf | ||
5 | # PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx-dev" | ||
6 | |||
7 | UBRANCH ?= "master" | ||
8 | |||
9 | include u-boot-xlnx.inc | ||
10 | include u-boot-spl-zynq-init.inc | ||
11 | |||
12 | LICENSE = "GPLv2+" | ||
13 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" | ||
14 | |||
15 | SRCREV_DEFAULT = "aebea9d20a5aa32857f320c07ca8f9fd1b3dec1f" | ||
16 | SRCREV ?= "${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/bootloader", "u-boot-xlnx-dev", "${AUTOREV}", "${SRCREV_DEFAULT}", d)}" | ||
17 | |||
18 | PV = "${UBRANCH}-xilinx-dev+git${SRCPV}" | ||
19 | |||
20 | # Newer versions of u-boot have support for these | ||
21 | HAS_PLATFORM_INIT ?= " \ | ||
22 | zynq_microzed_config \ | ||
23 | zynq_zed_config \ | ||
24 | zynq_zc702_config \ | ||
25 | zynq_zc706_config \ | ||
26 | zynq_zybo_config \ | ||
27 | " | ||
28 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc deleted file mode 100644 index 893b8f6c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | require recipes-bsp/u-boot/u-boot.inc | ||
2 | |||
3 | DEPENDS += "bc-native dtc-native bison-native" | ||
4 | |||
5 | XILINX_RELEASE_VERSION ?= "" | ||
6 | UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" | ||
7 | PV = "${UBOOT_VERSION}${UBOOT_VERSION_EXTENSION}+git${SRCPV}" | ||
8 | |||
9 | UBOOTURI ?= "git://github.com/Xilinx/u-boot-xlnx.git;protocol=https" | ||
10 | UBRANCH ?= "" | ||
11 | UBRANCHARG = "${@['nobranch=1', 'branch=${UBRANCH}'][d.getVar('UBRANCH', True) != '']}" | ||
12 | |||
13 | SRC_URI = "${UBOOTURI};${UBRANCHARG}" | ||
14 | |||
15 | S = "${WORKDIR}/git" | ||
16 | B = "${WORKDIR}/build" | ||
17 | |||
18 | FILESEXTRAPATHS:prepend := "${THISDIR}/u-boot:" | ||
19 | |||
20 | SYSROOT_DIRS += "/boot" | ||
21 | |||
22 | # Specify a default in case boardvariant isn't available | ||
23 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
24 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb deleted file mode 100644 index a4fedbe2..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | UBOOT_VERSION = "v2021.01" | ||
2 | |||
3 | UBRANCH ?= "xlnx_rebase_v2021.01" | ||
4 | |||
5 | SRCREV = "63b6d260dbe64a005407439e2caeb32da9025954" | ||
6 | |||
7 | include u-boot-xlnx.inc | ||
8 | include u-boot-spl-zynq-init.inc | ||
9 | |||
10 | LICENSE = "GPLv2+" | ||
11 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" | ||
12 | |||
13 | # u-boot-xlnx has support for these | ||
14 | HAS_PLATFORM_INIT ?= " \ | ||
15 | xilinx_zynqmp_virt_config \ | ||
16 | xilinx_zynq_virt_defconfig \ | ||
17 | xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \ | ||
18 | " | ||
19 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb deleted file mode 100644 index a75484a8..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr.bb +++ /dev/null | |||
@@ -1,238 +0,0 @@ | |||
1 | SUMMARY = "U-boot boot scripts for Xilinx devices" | ||
2 | LICENSE = "MIT" | ||
3 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" | ||
4 | |||
5 | DEPENDS = "u-boot-mkimage-native" | ||
6 | |||
7 | inherit deploy nopackages image-wic-utils | ||
8 | |||
9 | INHIBIT_DEFAULT_DEPS = "1" | ||
10 | |||
11 | COMPATIBLE_MACHINE ?= "^$" | ||
12 | COMPATIBLE_MACHINE:zynqmp = "zynqmp" | ||
13 | COMPATIBLE_MACHINE:zynq = "zynq" | ||
14 | COMPATIBLE_MACHINE:versal = "versal" | ||
15 | COMPATIBLE_MACHINE:microblaze = "microblaze" | ||
16 | |||
17 | KERNELDT = "${@os.path.basename(d.getVar('KERNEL_DEVICETREE').split(' ')[0]) if d.getVar('KERNEL_DEVICETREE') else ''}" | ||
18 | DEVICE_TREE_NAME ?= "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', d.getVar('KERNELDT'), d)}" | ||
19 | #Need to copy a rootfs.cpio.gz.u-boot as uramdisk.image.gz into boot partition | ||
20 | RAMDISK_IMAGE ?= "" | ||
21 | RAMDISK_IMAGE:zynq ?= "uramdisk.image.gz" | ||
22 | |||
23 | PXERAMDISK_IMAGE ?= "${@'ramdisk.cpio.gz.u-boot' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}" | ||
24 | |||
25 | KERNEL_BOOTCMD:zynqmp ?= "booti" | ||
26 | KERNEL_BOOTCMD:zynq ?= "bootm" | ||
27 | KERNEL_BOOTCMD:versal ?= "booti" | ||
28 | KERNEL_BOOTCMD:microblaze ?= "bootm" | ||
29 | |||
30 | BOOTMODE ?= "sd" | ||
31 | BOOTFILE_EXT ?= ".${SOC_FAMILY}" | ||
32 | |||
33 | #Make this value to "1" to skip appending base address to ddr offsets. | ||
34 | SKIP_APPEND_BASEADDR ?= "0" | ||
35 | |||
36 | DDR_BASEADDR ?= "0x0" | ||
37 | DDR_BASEADDR:microblaze ?= "0x80000000" | ||
38 | PRE_BOOTENV ?= "" | ||
39 | |||
40 | SRC_URI = " \ | ||
41 | file://boot.cmd.sd.zynq \ | ||
42 | file://boot.cmd.sd.zynqmp \ | ||
43 | file://boot.cmd.sd.versal \ | ||
44 | file://boot.cmd.qspi.versal \ | ||
45 | file://boot.cmd.generic \ | ||
46 | file://boot.cmd.ubifs \ | ||
47 | file://pxeboot.pxe \ | ||
48 | " | ||
49 | |||
50 | # Specify a default in case boardvariant isn't available | ||
51 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
52 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
53 | |||
54 | # On zynqmp-dr, we know we're different so if BOARD is not defined, fall back | ||
55 | # to the SOC_VARIANT_ARCH instead | ||
56 | SOC_VARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
57 | PACKAGE_ARCH:zynqmp-dr = "${@['${BOARDVARIANT_ARCH}', '${SOC_VARIANT_ARCH}'][d.getVar('BOARDVARIANT_ARCH')==d.getVar('MACHINE_ARCH')]}" | ||
58 | |||
59 | inherit image-artifact-names | ||
60 | UENV_TEXTFILE ?= "uEnv.txt" | ||
61 | UENV_MMC_OFFSET:zynqmp ?= "0x200000" | ||
62 | UENV_MMC_OFFSET:zynq ?= "0x2080000" | ||
63 | UENV_MMC_OFFSET:versal ?= "0x200000" | ||
64 | UENV_MMC_OFFSET:microblaze ?= "0x0" | ||
65 | |||
66 | UENV_MMC_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('UENV_MMC_OFFSET'))}" | ||
67 | |||
68 | UBOOTSCR_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}" | ||
69 | UBOOTPXE_CONFIG ?= "pxelinux.cfg" | ||
70 | UBOOTPXE_CONFIG_NAME = "${UBOOTPXE_CONFIG}${IMAGE_VERSION_SUFFIX}" | ||
71 | |||
72 | DEVICETREE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('DEVICETREE_OFFSET'))}" | ||
73 | |||
74 | DEVICETREE_OFFSET:microblaze ?= "0x1e00000" | ||
75 | DEVICETREE_OFFSET:zynqmp ?= "0x100000" | ||
76 | DEVICETREE_OFFSET:zynq ?= "0x2000000" | ||
77 | DEVICETREE_OFFSET:versal ?= "0x1000" | ||
78 | |||
79 | KERNEL_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('KERNEL_OFFSET'))}" | ||
80 | |||
81 | KERNEL_OFFSET:microblaze ?= "0x0" | ||
82 | KERNEL_OFFSET:zynqmp ?= "0x200000" | ||
83 | KERNEL_OFFSET:zynq ?= "0x2080000" | ||
84 | KERNEL_OFFSET:versal ?= "0x200000" | ||
85 | |||
86 | KERNEL_IMAGE ?= "${KERNEL_IMAGETYPE}" | ||
87 | |||
88 | RAMDISK_IMAGE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('RAMDISK_OFFSET'))}" | ||
89 | |||
90 | RAMDISK_OFFSET:microblaze ?= "0x2e00000" | ||
91 | RAMDISK_OFFSET:zynq ?= "0x4000000" | ||
92 | RAMDISK_OFFSET:zynqmp ?= "0x4000000" | ||
93 | RAMDISK_OFFSET:versal ?= "0x6000000" | ||
94 | |||
95 | FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('FIT_IMAGE_OFFSET'))}" | ||
96 | FIT_IMAGE_OFFSET ?= "0x10000000" | ||
97 | FIT_IMAGE ?= "image.ub" | ||
98 | |||
99 | ## Below offsets and sizes are based on 32MB QSPI Memory for zynq | ||
100 | ## For MB | ||
101 | ## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory | ||
102 | QSPI_KERNEL_OFFSET:microblaze ?= "0xBC0000" | ||
103 | QSPI_KERNEL_SIZE:microblaze ?= "0x500000" | ||
104 | QSPI_RAMDISK_SIZE:microblaze ?= "0xA00000" | ||
105 | |||
106 | ## For zynq | ||
107 | ## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory | ||
108 | QSPI_KERNEL_OFFSET:zynq ?= "0x1000000" | ||
109 | QSPI_RAMDISK_OFFSET:zynq ?= "0x1580000" | ||
110 | |||
111 | NAND_KERNEL_OFFSET:zynq ?= "0x1000000" | ||
112 | NAND_RAMDISK_OFFSET:zynq ?= "0x4600000" | ||
113 | |||
114 | QSPI_KERNEL_SIZE:zynq ?= "0x500000" | ||
115 | QSPI_RAMDISK_SIZE:zynq ?= "0xA00000" | ||
116 | |||
117 | NAND_KERNEL_SIZE ?= "0x3200000" | ||
118 | NAND_RAMDISK_SIZE ?= "0x3200000" | ||
119 | |||
120 | ## Below offsets and sizes are based on 128MB QSPI Memory for zynqmp/versal | ||
121 | ## For zynqMP | ||
122 | ## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory | ||
123 | QSPI_KERNEL_OFFSET ?= "0xF00000" | ||
124 | QSPI_KERNEL_OFFSET:zynqmpdr ?= "0x3F00000" | ||
125 | QSPI_RAMDISK_OFFSET ?= "0x4000000" | ||
126 | QSPI_RAMDISK_OFFSET:zynqmpdr ?= "0x5D00000" | ||
127 | |||
128 | NAND_KERNEL_OFFSET:zynqmp ?= "0x4100000" | ||
129 | NAND_RAMDISK_OFFSET:zynqmp ?= "0x7800000" | ||
130 | |||
131 | QSPI_KERNEL_SIZE:zynqmp ?= "0x1D00000" | ||
132 | QSPI_RAMDISK_SIZE ?= "0x4000000" | ||
133 | QSPI_RAMDISK_SIZE:zynqmpdr ?= "0x1D00000" | ||
134 | |||
135 | ## For versal | ||
136 | ## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory | ||
137 | QSPI_KERNEL_OFFSET:versal ?= "0xF00000" | ||
138 | QSPI_RAMDISK_OFFSET:versal ?= "0x2E00000" | ||
139 | |||
140 | NAND_KERNEL_OFFSET:versal ?= "0x4100000" | ||
141 | NAND_RAMDISK_OFFSET:versal ?= "0x8200000" | ||
142 | |||
143 | QSPI_KERNEL_SIZE:versal ?= "0x1D00000" | ||
144 | QSPI_RAMDISK_SIZE:versal ?= "0x4000000" | ||
145 | |||
146 | QSPI_KERNEL_IMAGE:microblaze ?= "image.ub" | ||
147 | QSPI_KERNEL_IMAGE:zynq ?= "image.ub" | ||
148 | QSPI_KERNEL_IMAGE:zynqmp ?= "image.ub" | ||
149 | QSPI_KERNEL_IMAGE:versal ?= "image.ub" | ||
150 | |||
151 | NAND_KERNEL_IMAGE ?= "image.ub" | ||
152 | |||
153 | QSPI_FIT_IMAGE_OFFSET ?= "0x1080000" | ||
154 | QSPI_FIT_IMAGE_SIZE ?= "0x6400000" | ||
155 | QSPI_FIT_IMAGE_SIZE:zynqmpdr ?= "0x3F00000" | ||
156 | QSPI_FIT_IMAGE_SIZE:zynq ?= "0xF00000" | ||
157 | QSPI_FIT_IMAGE_SIZE:microblaze ?= "0xF00000" | ||
158 | |||
159 | NAND_FIT_IMAGE_OFFSET ?= "0x1080000" | ||
160 | NAND_FIT_IMAGE_SIZE ?= "0x6400000" | ||
161 | |||
162 | SDBOOTDEV ?= "0" | ||
163 | |||
164 | BITSTREAM_LOAD_ADDRESS ?= "0x100000" | ||
165 | |||
166 | do_configure[noexec] = "1" | ||
167 | do_install[noexec] = "1" | ||
168 | |||
169 | def append_baseaddr(d,offset): | ||
170 | skip_append = d.getVar('SKIP_APPEND_BASEADDR') or "" | ||
171 | if skip_append == "1": | ||
172 | return offset | ||
173 | import subprocess | ||
174 | baseaddr = d.getVar('DDR_BASEADDR') or "0x0" | ||
175 | subcmd = "$((%s+%s));" % (baseaddr,offset) | ||
176 | cmd = "printf '0x%08x' " + str(subcmd) | ||
177 | output = subprocess.check_output(cmd, shell=True).decode("utf-8") | ||
178 | return output | ||
179 | |||
180 | def get_bitstream_load_type(d): | ||
181 | if boot_files_bitstream(d)[1] : | ||
182 | return "loadb" | ||
183 | else: | ||
184 | return "load" | ||
185 | |||
186 | do_compile() { | ||
187 | sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \ | ||
188 | -e 's/@@KERNEL_LOAD_ADDRESS@@/${KERNEL_LOAD_ADDRESS}/' \ | ||
189 | -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \ | ||
190 | -e 's/@@DEVICETREE_ADDRESS@@/${DEVICETREE_ADDRESS}/' \ | ||
191 | -e 's/@@RAMDISK_IMAGE@@/${RAMDISK_IMAGE}/' \ | ||
192 | -e 's/@@RAMDISK_IMAGE_ADDRESS@@/${RAMDISK_IMAGE_ADDRESS}/' \ | ||
193 | -e 's/@@KERNEL_BOOTCMD@@/${KERNEL_BOOTCMD}/' \ | ||
194 | -e 's/@@SDBOOTDEV@@/${SDBOOTDEV}/' \ | ||
195 | -e 's/@@BITSTREAM@@/${@boot_files_bitstream(d)[0]}/g' \ | ||
196 | -e 's/@@BITSTREAM_LOAD_ADDRESS@@/${BITSTREAM_LOAD_ADDRESS}/g' \ | ||
197 | -e 's/@@BITSTREAM_IMAGE@@/${@boot_files_bitstream(d)[0]}/g' \ | ||
198 | -e 's/@@BITSTREAM_LOAD_TYPE@@/${@get_bitstream_load_type(d)}/g' \ | ||
199 | -e 's/@@QSPI_KERNEL_OFFSET@@/${QSPI_KERNEL_OFFSET}/' \ | ||
200 | -e 's/@@NAND_KERNEL_OFFSET@@/${NAND_KERNEL_OFFSET}/' \ | ||
201 | -e 's/@@QSPI_KERNEL_SIZE@@/${QSPI_KERNEL_SIZE}/' \ | ||
202 | -e 's/@@NAND_KERNEL_SIZE@@/${NAND_KERNEL_SIZE}/' \ | ||
203 | -e 's/@@QSPI_RAMDISK_OFFSET@@/${QSPI_RAMDISK_OFFSET}/' \ | ||
204 | -e 's/@@NAND_RAMDISK_OFFSET@@/${NAND_RAMDISK_OFFSET}/' \ | ||
205 | -e 's/@@QSPI_RAMDISK_SIZE@@/${QSPI_RAMDISK_SIZE}/' \ | ||
206 | -e 's/@@NAND_RAMDISK_SIZE@@/${NAND_RAMDISK_SIZE}/' \ | ||
207 | -e 's/@@KERNEL_IMAGE@@/${KERNEL_IMAGE}/' \ | ||
208 | -e 's/@@QSPI_KERNEL_IMAGE@@/${QSPI_KERNEL_IMAGE}/' \ | ||
209 | -e 's/@@NAND_KERNEL_IMAGE@@/${NAND_KERNEL_IMAGE}/' \ | ||
210 | -e 's/@@FIT_IMAGE_LOAD_ADDRESS@@/${FIT_IMAGE_LOAD_ADDRESS}/' \ | ||
211 | -e 's/@@QSPI_FIT_IMAGE_OFFSET@@/${QSPI_FIT_IMAGE_OFFSET}/' \ | ||
212 | -e 's/@@QSPI_FIT_IMAGE_SIZE@@/${QSPI_FIT_IMAGE_SIZE}/' \ | ||
213 | -e 's/@@NAND_FIT_IMAGE_OFFSET@@/${NAND_FIT_IMAGE_OFFSET}/' \ | ||
214 | -e 's/@@NAND_FIT_IMAGE_SIZE@@/${NAND_FIT_IMAGE_SIZE}/' \ | ||
215 | -e 's/@@FIT_IMAGE@@/${FIT_IMAGE}/' \ | ||
216 | -e 's/@@PRE_BOOTENV@@/${PRE_BOOTENV}/' \ | ||
217 | -e 's/@@UENV_MMC_LOAD_ADDRESS@@/${UENV_MMC_LOAD_ADDRESS}/' \ | ||
218 | -e 's/@@UENV_TEXTFILE@@/${UENV_TEXTFILE}/' \ | ||
219 | -e 's/@@RAMDISK_IMAGE1@@/${RAMDISK_IMAGE1}/' \ | ||
220 | "${WORKDIR}/boot.cmd.${BOOTMODE}${BOOTFILE_EXT}" > "${WORKDIR}/boot.cmd" | ||
221 | mkimage -A arm -T script -C none -n "Boot script" -d "${WORKDIR}/boot.cmd" boot.scr | ||
222 | sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \ | ||
223 | -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \ | ||
224 | -e 's/@@RAMDISK_IMAGE@@/${PXERAMDISK_IMAGE}/' \ | ||
225 | "${WORKDIR}/pxeboot.pxe" > "pxeboot.pxe" | ||
226 | } | ||
227 | |||
228 | |||
229 | do_deploy() { | ||
230 | install -d ${DEPLOYDIR} | ||
231 | install -m 0644 boot.scr ${DEPLOYDIR}/${UBOOTSCR_BASE_NAME}.scr | ||
232 | ln -sf ${UBOOTSCR_BASE_NAME}.scr ${DEPLOYDIR}/boot.scr | ||
233 | install -d ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME} | ||
234 | install -m 0644 pxeboot.pxe ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME}/default | ||
235 | ln -sf pxeboot/${UBOOTPXE_CONFIG_NAME} ${DEPLOYDIR}/${UBOOTPXE_CONFIG} | ||
236 | } | ||
237 | |||
238 | addtask do_deploy after do_compile before do_build | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic deleted file mode 100644 index 0249a8a0..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | # This is a boot script for U-Boot | ||
2 | # Generate boot.scr: | ||
3 | # mkimage -c none -A arm -T script -d boot.cmd.default boot.scr | ||
4 | # | ||
5 | ################ | ||
6 | fitimage_name=@@FIT_IMAGE@@ | ||
7 | kernel_name=@@KERNEL_IMAGE@@ | ||
8 | ramdisk_name=@@RAMDISK_IMAGE1@@ | ||
9 | rootfs_name=@@RAMDISK_IMAGE@@ | ||
10 | @@PRE_BOOTENV@@ | ||
11 | |||
12 | for boot_target in ${boot_targets}; | ||
13 | do | ||
14 | echo "Trying to load boot images from ${boot_target}" | ||
15 | if test "${boot_target}" = "jtag" ; then | ||
16 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
17 | fi | ||
18 | if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then | ||
19 | if test -e ${devtype} ${devnum}:${distro_bootpart} /@@UENV_TEXTFILE@@; then | ||
20 | fatload ${devtype} ${devnum}:${distro_bootpart} @@UENV_MMC_LOAD_ADDRESS@@ @@UENV_TEXTFILE@@; | ||
21 | echo "Importing environment(@@UENV_TEXTFILE@@) from ${boot_target}..." | ||
22 | env import -t @@UENV_MMC_LOAD_ADDRESS@@ $filesize | ||
23 | if test -n $uenvcmd; then | ||
24 | echo "Running uenvcmd ..."; | ||
25 | run uenvcmd; | ||
26 | fi | ||
27 | fi | ||
28 | if test -e ${devtype} ${devnum}:${distro_bootpart} /${fitimage_name}; then | ||
29 | fatload ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ ${fitimage_name}; | ||
30 | bootm @@FIT_IMAGE_LOAD_ADDRESS@@; | ||
31 | fi | ||
32 | if test -e ${devtype} ${devnum}:${distro_bootpart} /${kernel_name}; then | ||
33 | fatload ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ ${kernel_name}; | ||
34 | fi | ||
35 | if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then | ||
36 | fatload ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb; | ||
37 | fi | ||
38 | if test -e ${devtype} ${devnum}:${distro_bootpart} /${ramdisk_name} && test "${skip_tinyramdisk}" != "yes"; then | ||
39 | fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${ramdisk_name}; | ||
40 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
41 | fi | ||
42 | if test -e ${devtype} ${devnum}:${distro_bootpart} /${rootfs_name} && test "${skip_ramdisk}" != "yes"; then | ||
43 | fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${rootfs_name}; | ||
44 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
45 | fi | ||
46 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ | ||
47 | fi | ||
48 | if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then | ||
49 | sf probe 0 0 0; | ||
50 | sf read @@FIT_IMAGE_LOAD_ADDRESS@@ @@QSPI_FIT_IMAGE_OFFSET@@ @@QSPI_FIT_IMAGE_SIZE@@ | ||
51 | bootm @@FIT_IMAGE_LOAD_ADDRESS@@; | ||
52 | echo "Booting using Fit image failed" | ||
53 | |||
54 | sf read @@KERNEL_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_KERNEL_SIZE@@ | ||
55 | sf read @@RAMDISK_IMAGE_ADDRESS@@ @@QSPI_RAMDISK_OFFSET@@ @@QSPI_RAMDISK_SIZE@@ | ||
56 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@; | ||
57 | echo "Booting using Separate images failed" | ||
58 | fi | ||
59 | if test "${boot_target}" = "nand" || test "${boot_target}" = "nand0"; then | ||
60 | nand info; | ||
61 | nand read @@FIT_IMAGE_LOAD_ADDRESS@@ @@NAND_FIT_IMAGE_OFFSET@@ @@NAND_FIT_IMAGE_SIZE@@ | ||
62 | bootm @@FIT_IMAGE_LOAD_ADDRESS@@; | ||
63 | echo "Booting using Fit image failed" | ||
64 | |||
65 | nand read @@KERNEL_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_KERNEL_SIZE@@ | ||
66 | nand read @@RAMDISK_IMAGE_ADDRESS@@ @@NAND_RAMDISK_OFFSET@@ @@NAND_RAMDISK_SIZE@@ | ||
67 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@; | ||
68 | echo "Booting using Separate images failed" | ||
69 | fi | ||
70 | done | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal deleted file mode 100644 index d56b7c8c..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal +++ /dev/null | |||
@@ -1 +0,0 @@ | |||
1 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal deleted file mode 100644 index 10e83cd0..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal +++ /dev/null | |||
@@ -1,3 +0,0 @@ | |||
1 | setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused | ||
2 | fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ | ||
3 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq deleted file mode 100644 index bbd2e01e..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | if test -n "@@BITSTREAM@@"; then | ||
2 | fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize} | ||
3 | fi | ||
4 | fatload mmc 0 @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@ | ||
5 | fatload mmc 0 @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ | ||
6 | fatload mmc 0 @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@ | ||
7 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp deleted file mode 100644 index b234a8df..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp +++ /dev/null | |||
@@ -1,8 +0,0 @@ | |||
1 | setenv sdbootdev @@SDBOOTDEV@@ | ||
2 | setenv bootargs $bootargs root=/dev/mmcblk${sdbootdev}p2 rw rootwait earlycon clk_ignore_unused | ||
3 | if test -n "@@BITSTREAM@@"; then | ||
4 | fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize} | ||
5 | fi | ||
6 | fatload mmc $sdbootdev @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@ | ||
7 | fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@ | ||
8 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs deleted file mode 100644 index 60c48eda..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs +++ /dev/null | |||
@@ -1,54 +0,0 @@ | |||
1 | # This is a boot script for U-Boot | ||
2 | # Generate boot.scr: | ||
3 | # mkimage -c none -A arm -T script -d boot.cmd.default boot.scr | ||
4 | # | ||
5 | ################ | ||
6 | @@PRE_BOOTENV@@ | ||
7 | |||
8 | for boot_target in ${boot_targets}; | ||
9 | do | ||
10 | if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then | ||
11 | ubifsls @@FIT_IMAGE@@ | ||
12 | if test $? = 0; then | ||
13 | ubifsload @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@; | ||
14 | bootm @@FIT_IMAGE_LOAD_ADDRESS@@; | ||
15 | fi | ||
16 | ubifsls @@KERNEL_IMAGE@@ | ||
17 | if test $? = 0; then | ||
18 | ubifsload @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@; | ||
19 | fi | ||
20 | ubifsls system.dtb | ||
21 | if test $? = 0; then | ||
22 | ubifsload @@DEVICETREE_ADDRESS@@ system.dtb | ||
23 | fi | ||
24 | ubifsls @@RAMDISK_IMAGE@@ | ||
25 | if test $? = 0; then | ||
26 | ubifsload @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@ | ||
27 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
28 | exit; | ||
29 | fi | ||
30 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ | ||
31 | exit; | ||
32 | fi | ||
33 | if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then | ||
34 | run bootcmd_${boot_target}; | ||
35 | if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then | ||
36 | ext4load ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@; | ||
37 | bootm @@FIT_IMAGE_LOAD_ADDRESS@@; | ||
38 | exit; | ||
39 | fi | ||
40 | if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then | ||
41 | ext4load ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@; | ||
42 | fi | ||
43 | if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then | ||
44 | ext4load ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb; | ||
45 | fi | ||
46 | if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then | ||
47 | ext4load ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@; | ||
48 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@ | ||
49 | exit; | ||
50 | fi | ||
51 | @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@ | ||
52 | exit; | ||
53 | fi | ||
54 | done | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe deleted file mode 100644 index 40796545..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe +++ /dev/null | |||
@@ -1,4 +0,0 @@ | |||
1 | LABEL Linux | ||
2 | KERNEL @@KERNEL_IMAGETYPE@@ | ||
3 | FDT @@DEVICE_TREE_NAME@@ | ||
4 | INITRD @@RAMDISK_IMAGE@@ | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb deleted file mode 100644 index 52ae09f0..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-zynq-uenv.bb +++ /dev/null | |||
@@ -1,109 +0,0 @@ | |||
1 | SUMMARY = "U-Boot uEnv.txt SD boot environment generation for Zynq targets" | ||
2 | LICENSE = "MIT" | ||
3 | LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302" | ||
4 | |||
5 | INHIBIT_DEFAULT_DEPS = "1" | ||
6 | |||
7 | BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}" | ||
8 | PACKAGE_ARCH = "${BOARDVARIANT_ARCH}" | ||
9 | |||
10 | python () { | ||
11 | # The device trees must be populated in the deploy directory to correctly | ||
12 | # detect them and their names. This means that this recipe needs to depend | ||
13 | # on those deployables just like the image recipe does. | ||
14 | deploydeps = ["virtual/kernel"] | ||
15 | for i in (d.getVar("EXTRA_IMAGEDEPENDS") or "").split(): | ||
16 | if i != d.getVar("BPN"): | ||
17 | deploydeps.append(i) | ||
18 | |||
19 | # add as DEPENDS since the targets might not have do_deploy tasks | ||
20 | if len(deploydeps) != 0: | ||
21 | d.appendVar("DEPENDS", " " + " ".join(deploydeps)) | ||
22 | } | ||
23 | |||
24 | COMPATIBLE_MACHINE = "^$" | ||
25 | COMPATIBLE_MACHINE:zynq = ".*" | ||
26 | COMPATIBLE_MACHINE:zynqmp = ".*" | ||
27 | |||
28 | inherit deploy image-wic-utils | ||
29 | |||
30 | def uboot_boot_cmd(d): | ||
31 | if d.getVar("KERNEL_IMAGETYPE") in ["uImage", "fitImage"]: | ||
32 | return "bootm" | ||
33 | if d.getVar("KERNEL_IMAGETYPE") in ["zImage"]: | ||
34 | return "bootz" | ||
35 | if d.getVar("KERNEL_IMAGETYPE") in ["Image"]: | ||
36 | return "booti" | ||
37 | raise bb.parse.SkipRecipe("Unsupport kernel image type") | ||
38 | |||
39 | def get_sdbootdev(d): | ||
40 | if d.getVar("SOC_FAMILY") in ["zynqmp"]: | ||
41 | return "${sdbootdev}" | ||
42 | else: | ||
43 | return "0" | ||
44 | |||
45 | def uenv_populate(d): | ||
46 | # populate the environment values | ||
47 | env = {} | ||
48 | |||
49 | env["machine_name"] = d.getVar("MACHINE") | ||
50 | |||
51 | env["kernel_image"] = d.getVar("KERNEL_IMAGETYPE") | ||
52 | env["kernel_load_address"] = d.getVar("KERNEL_LOAD_ADDRESS") | ||
53 | |||
54 | env["devicetree_image"] = boot_files_dtb_filepath(d) | ||
55 | env["devicetree_load_address"] = d.getVar("DEVICETREE_LOAD_ADDRESS") | ||
56 | |||
57 | env["bootargs"] = d.getVar("KERNEL_BOOTARGS") | ||
58 | |||
59 | env["loadkernel"] = "fatload mmc " + get_sdbootdev(d) + " ${kernel_load_address} ${kernel_image}" | ||
60 | env["loaddtb"] = "fatload mmc " + get_sdbootdev(d) + " ${devicetree_load_address} ${devicetree_image}" | ||
61 | env["bootkernel"] = "run loadkernel && run loaddtb && " + uboot_boot_cmd(d) + " ${kernel_load_address} - ${devicetree_load_address}" | ||
62 | |||
63 | if d.getVar("SOC_FAMILY") in ["zynqmp"]: | ||
64 | env["bootkernel"] = "setenv bootargs " + d.getVar("KERNEL_BOOTARGS") + " ; " + env["bootkernel"] | ||
65 | |||
66 | # default uenvcmd does not load bitstream | ||
67 | env["uenvcmd"] = "run bootkernel" | ||
68 | |||
69 | bitstream, bitstreamtype = boot_files_bitstream(d) | ||
70 | if bitstream: | ||
71 | env["bitstream_image"] = bitstream | ||
72 | env["bitstream_load_address"] = "0x100000" | ||
73 | |||
74 | # if bitstream is "bit" format use loadb, otherwise use load | ||
75 | env["bitstream_type"] = "loadb" if bitstreamtype else "load" | ||
76 | |||
77 | # load bitstream first with loadfpa | ||
78 | env["loadfpga"] = "fatload mmc " + get_sdbootdev(d) + " ${bitstream_load_address} ${bitstream_image} && fpga ${bitstream_type} 0 ${bitstream_load_address} ${filesize}" | ||
79 | env["uenvcmd"] = "run loadfpga && run bootkernel" | ||
80 | |||
81 | return env | ||
82 | |||
83 | # bootargs, default to booting with the rootfs device being partition 2 | ||
84 | KERNEL_BOOTARGS:zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait" | ||
85 | KERNEL_BOOTARGS:zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${sdbootdev}p2 rw rootwait" | ||
86 | |||
87 | KERNEL_LOAD_ADDRESS:zynq = "0x2080000" | ||
88 | KERNEL_LOAD_ADDRESS:zynqmp = "0x200000" | ||
89 | DEVICETREE_LOAD_ADDRESS:zynq = "0x2000000" | ||
90 | DEVICETREE_LOAD_ADDRESS:zynqmp = "0x4000000" | ||
91 | |||
92 | python do_compile() { | ||
93 | env = uenv_populate(d) | ||
94 | with open(d.expand("${WORKDIR}/uEnv.txt"), "w") as f: | ||
95 | for k, v in env.items(): | ||
96 | f.write("{0}={1}\n".format(k, v)) | ||
97 | } | ||
98 | |||
99 | FILES:${PN} += "/boot/uEnv.txt" | ||
100 | |||
101 | do_install() { | ||
102 | install -Dm 0644 ${WORKDIR}/uEnv.txt ${D}/boot/uEnv.txt | ||
103 | } | ||
104 | |||
105 | do_deploy() { | ||
106 | install -Dm 0644 ${WORKDIR}/uEnv.txt ${DEPLOYDIR}/uEnv.txt | ||
107 | } | ||
108 | addtask do_deploy after do_compile before do_build | ||
109 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend deleted file mode 100644 index b8522369..00000000 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ /dev/null | |||
@@ -1,11 +0,0 @@ | |||
1 | include u-boot-spl-zynq-init.inc | ||
2 | |||
3 | # u-boot 2016.11 has support for these | ||
4 | HAS_PLATFORM_INIT ??= " \ | ||
5 | zynq_microzed_config \ | ||
6 | zynq_zed_config \ | ||
7 | zynq_zc702_config \ | ||
8 | zynq_zc706_config \ | ||
9 | zynq_zybo_config \ | ||
10 | " | ||
11 | |||