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authorSivaprasad Addepalli <sivaprasad.addepalli@xilinx.com>2023-07-04 17:55:47 +0530
committerSiva Addepalli <sivaprasad.addepalli@xilinx.com>2023-07-04 19:17:10 +0530
commitfc94b1dfffc57711f0c00505941f656b8f50ed4c (patch)
tree2973c7ab38a71ef2039eaa030423740313025a35
parent3f290f76cd935ee2bb01f3dc0d9a79c27a33302b (diff)
downloadmeta-xilinx-fc94b1dfffc57711f0c00505941f656b8f50ed4c.tar.gz
embeddedsw : Updated SRCREV for 2023.2_8643
sw_apps: zynqmp_pmufw: MPSoC PMU MIO Reset Pin Control sw_services: xilpm: Integrate xilpm into vitisng/rigel flow versal: psmfw: Integrate psmfw into vitisng/rigel flow sw_apps: zynqmp_pmufw: Integrate pmufw into vitisng/rigel flow xilpm: server: Add support for device security, coherency and virt handling in Versal Net FB_Wr Driver: Updated addtogroup in driver src directory FB_Wr Driver: New video format to driver changes are added - Y_U_V8_420 FB_Wr Driver: Incremented driver version to v4.7 xilpm: versal: server: Add support for DDRMC5c pre-config xilpm: versal_common: server: XPm_WritePggs and XPm_ReadPggs bug fix xilpm: versal_net: server: Add CPM5N Bisr support xdmapcie: Update mdd version xdmapcie: Fix BAR allocation to consider maximum xdmapcie: Fix macro declaration for header type mask xdmapcie: Fix the BAR allocation issues based on requests. xdmapcie: Update copyright year SDITXSS Driver: Updated addtogroup driver in src files SDITXSS MDD: Incremented Driver version to v4_3 SDITXSS Driver: Modified Driver TCL file to correct device id value wdttb: Fix code format issue wdttb: Correct the interrupt ID for Versal-net platform rtcpsu: Fix code formatting issues with checkpatch rtcpsu: Add support for system device-tree flow for examples. rtcpsu: Add support for system device-tree flow client: Add specific error codes for failure cases server: Add specific error codes for KAT failure cases xilpm: CPPUTEST macro added to files xilpm: versal: SSIT temperature propagation xilrsa: Added Rigel support drivers: Fix code formatting issues with checkpatch drivers: Update doxygen documentation csudma: Fixed code formatting issue using checkpatch tool csudma: Update DCache operation for R52 bsp: standalone: Add xpm support for versal and versal net xilpm: Add SMC support for Request node, Reset Assert and Release Node canfd: Add support for request/release node canfd: Invoke XCanFd_stop function to release canfd node Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
-rw-r--r--meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 49bb8ce2..039b11da 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -8,7 +8,7 @@ ESW_BRANCH[2023.2] = "master-next"
8BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" 8BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}"
9 9
10ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab" 10ESW_REV[2023.1] = "e24fe92b5517ee447e560790e798cad792f53bab"
11ESW_REV[2023.2] = "7b32e8799d7733ff5e450699ced43dc355e81389" 11ESW_REV[2023.2] = "ef08558128ad75f34df43e59b57928519a56fbf9"
12SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" 12SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"
13 13
14EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" 14EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"