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author | Jaewon Lee <jaewon.lee@xilinx.com> | 2019-03-27 10:50:40 -0700 |
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committer | Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> | 2019-12-09 16:55:23 -0800 |
commit | 2f7eeaadc25fc6e5e9deb9ebe5145e15bd631d1c (patch) | |
tree | 2e92d80a008087f649f152f574777458ba9aac65 | |
parent | 5e7c4ffd6fe8013e8c4ac7e39e9fc0b251cafaeb (diff) | |
download | meta-xilinx-2f7eeaadc25fc6e5e9deb9ebe5145e15bd631d1c.tar.gz |
Update recipes for 2019.2 release
Update u-boot, kernel, ATF, QEMU, pmu-firmware, multimedia recipes for
2019.2 release.
The patch also upgrades gcc microblaze, newlib and libgloss versions.
Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
-rw-r--r-- | meta-xilinx-bsp/conf/layer.conf | 3 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | 5 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb | 7 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb (renamed from meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc | 1 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch (renamed from meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb (renamed from meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb) | 3 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch | 105 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb | 4 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc | 4 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb (renamed from meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb) | 3 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb (renamed from meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb) | 1 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc | 21 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch | 93 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb (renamed from meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb) | 1 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb | 7 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch) | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch) | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch) | 13 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch) | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch) | 8 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch) | 4 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch) | 4 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch) | 8 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch) | 17 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch) | 6 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch) | 8 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch) | 8 | ||||
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-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch) | 6 | ||||
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-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch) | 11 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch) | 10 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch) | 8 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch) | 8 | ||||
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-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch) | 8 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch) | 8 | ||||
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-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch | 51 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch | 466 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch | 479 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | 41 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch | 107 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch | 44 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend) | 18 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb | 5 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb | 5 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb | 5 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb | 5 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb | 14 | ||||
-rw-r--r-- | meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb | 7 | ||||
-rw-r--r-- | meta-xilinx-contrib/conf/layer.conf | 3 | ||||
-rw-r--r-- | meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch (renamed from meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch (renamed from meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch (renamed from meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch) | 0 | ||||
-rw-r--r-- | meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg (renamed from meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg) | 0 | ||||
-rw-r--r-- | meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend (renamed from meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend) | 0 | ||||
-rw-r--r-- | meta-xilinx-standalone/conf/layer.conf | 3 | ||||
-rw-r--r-- | meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend (renamed from meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend) | 0 | ||||
-rw-r--r-- | meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend (renamed from meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend) | 0 | ||||
-rw-r--r-- | meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb (renamed from meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb) | 6 |
108 files changed, 2085 insertions, 512 deletions
diff --git a/meta-xilinx-bsp/conf/layer.conf b/meta-xilinx-bsp/conf/layer.conf index 437616cf..2a0af10e 100644 --- a/meta-xilinx-bsp/conf/layer.conf +++ b/meta-xilinx-bsp/conf/layer.conf | |||
@@ -11,7 +11,8 @@ BBFILE_PRIORITY_xilinx = "5" | |||
11 | 11 | ||
12 | LAYERDEPENDS_xilinx = "core" | 12 | LAYERDEPENDS_xilinx = "core" |
13 | 13 | ||
14 | LAYERSERIES_COMPAT_xilinx = "warrior" | 14 | LAYERSERIES_COMPAT_xilinx = "zeus" |
15 | 15 | ||
16 | BB_DANGLINGAPPENDS_WARNONLY ?= "1" | 16 | BB_DANGLINGAPPENDS_WARNONLY ?= "1" |
17 | 17 | ||
18 | XILINX_RELEASE_VERSION = "v2019.2" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index 785f915e..8c4806bf 100644 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc | |||
@@ -12,6 +12,8 @@ DEPENDS += "u-boot-mkimage-native" | |||
12 | S = "${WORKDIR}/git" | 12 | S = "${WORKDIR}/git" |
13 | B = "${WORKDIR}/build" | 13 | B = "${WORKDIR}/build" |
14 | 14 | ||
15 | SYSROOT_DIRS += "/boot" | ||
16 | |||
15 | XILINX_RELEASE_VERSION ?= "" | 17 | XILINX_RELEASE_VERSION ?= "" |
16 | ATF_VERSION ?= "2.0" | 18 | ATF_VERSION ?= "2.0" |
17 | ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" | 19 | ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}" |
@@ -72,7 +74,7 @@ do_compile() { | |||
72 | } | 74 | } |
73 | 75 | ||
74 | do_install() { | 76 | do_install() { |
75 | : | 77 | install -Dm 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${D}/boot/arm-trusted-firmware.elf |
76 | } | 78 | } |
77 | 79 | ||
78 | do_deploy() { | 80 | do_deploy() { |
@@ -91,3 +93,4 @@ do_deploy() { | |||
91 | ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub | 93 | ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub |
92 | } | 94 | } |
93 | addtask deploy before do_build after do_compile | 95 | addtask deploy before do_build after do_compile |
96 | FILES_${PN} = "/boot/arm-trusted-firmware.elf" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb deleted file mode 100644 index 64cbddc4..00000000 --- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | ATF_VERSION = "2.0" | ||
2 | XILINX_RELEASE_VERSION = "v2019.1" | ||
3 | BRANCH ?= "master" | ||
4 | SRCREV ?= "80d1c79007fda42d4cc0be31b185a1da5799cd4d" | ||
5 | |||
6 | include arm-trusted-firmware.inc | ||
7 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb new file mode 100644 index 00000000..a7ba1098 --- /dev/null +++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb | |||
@@ -0,0 +1,6 @@ | |||
1 | ATF_VERSION = "2.0" | ||
2 | BRANCH ?= "master" | ||
3 | SRCREV ?= "713dace94b259845fd8eede11061fbd8f039011e" | ||
4 | |||
5 | include arm-trusted-firmware.inc | ||
6 | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb index 6a2ca7cc..6a2ca7cc 100644 --- a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb +++ b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc index 737f5f91..61ed1804 100644 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc +++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc | |||
@@ -18,3 +18,4 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot:" | |||
18 | FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:" | 18 | FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:" |
19 | FILESEXTRAPATHS_prepend := "${@'${THISDIR}/u-boot-xlnx/${XILINX_RELEASE_VERSION}:' if d.getVar('XILINX_RELEASE_VERSION') else ''}" | 19 | FILESEXTRAPATHS_prepend := "${@'${THISDIR}/u-boot-xlnx/${XILINX_RELEASE_VERSION}:' if d.getVar('XILINX_RELEASE_VERSION') else ''}" |
20 | 20 | ||
21 | SYSROOT_DIRS += "/boot" | ||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch index 7e25f87c..7e25f87c 100644 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch +++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch | |||
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb index 3377635d..712b2528 100644 --- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb +++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb | |||
@@ -1,9 +1,8 @@ | |||
1 | UBOOT_VERSION = "v2019.01" | 1 | UBOOT_VERSION = "v2019.01" |
2 | XILINX_RELEASE_VERSION = "v2019.1" | ||
3 | 2 | ||
4 | UBRANCH ?= "master" | 3 | UBRANCH ?= "master" |
5 | 4 | ||
6 | SRCREV ?= "d895ac5e94815d4b45dcf09d4752c5c2334a51db" | 5 | SRCREV ?= "dc61275b1d505f6a236de1c5b0f35485914d2bcc" |
7 | 6 | ||
8 | include u-boot-xlnx.inc | 7 | include u-boot-xlnx.inc |
9 | include u-boot-spl-zynq-init.inc | 8 | include u-boot-spl-zynq-init.inc |
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch b/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch new file mode 100644 index 00000000..97cf71d9 --- /dev/null +++ b/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch | |||
@@ -0,0 +1,105 @@ | |||
1 | From 4fdb6551ea8856cc2df25d33e4103bf1736d7935 Mon Sep 17 00:00:00 2001 | ||
2 | From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= <berrange@redhat.com> | ||
3 | Date: Wed, 20 Nov 2019 13:53:16 -0800 | ||
4 | Subject: [PATCH] The glibc-2.29.9000-6.fc31.x86_64 package finally includes | ||
5 | the gettid() function as part of unistd.h when __USE_GNU is defined. This | ||
6 | clashes with linux-user code which unconditionally defines this function name | ||
7 | itself. | ||
8 | MIME-Version: 1.0 | ||
9 | Content-Type: text/plain; charset=UTF-8 | ||
10 | Content-Transfer-Encoding: 8bit | ||
11 | |||
12 | /home/berrange/src/virt/qemu/linux-user/syscall.c:253:16: error: static | ||
13 | declaration of ‘gettid’ follows non-static declaration | ||
14 | 253 | _syscall0(int, gettid) | ||
15 | | ^~~~~~ | ||
16 | /home/berrange/src/virt/qemu/linux-user/syscall.c:184:13: note: in | ||
17 | definition of macro ‘_syscall0’ | ||
18 | 184 | static type name (void) \ | ||
19 | | ^~~~ | ||
20 | In file included from /usr/include/unistd.h:1170, | ||
21 | from | ||
22 | /home/berrange/src/virt/qemu/include/qemu/osdep.h:107, | ||
23 | from | ||
24 | /home/berrange/src/virt/qemu/linux-user/syscall.c:20: | ||
25 | /usr/include/bits/unistd_ext.h:34:16: note: previous declaration of | ||
26 | ‘gettid’ was here | ||
27 | 34 | extern __pid_t gettid (void) __THROW; | ||
28 | | ^~~~~~ | ||
29 | CC aarch64-linux-user/linux-user/signal.o | ||
30 | make[1]: *** [/home/berrange/src/virt/qemu/rules.mak:69: | ||
31 | linux-user/syscall.o] Error 1 | ||
32 | make[1]: *** Waiting for unfinished jobs.... | ||
33 | make: *** [Makefile:449: subdir-aarch64-linux-user] Error 2 | ||
34 | |||
35 | While we could make our definition conditional and rely on glibc's impl, | ||
36 | this patch simply renames our definition to sys_gettid() which is a | ||
37 | common pattern in this file. | ||
38 | |||
39 | Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> | ||
40 | Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com> | ||
41 | --- | ||
42 | linux-user/syscall.c | 15 ++++++++------- | ||
43 | 1 file changed, 8 insertions(+), 7 deletions(-) | ||
44 | |||
45 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
46 | index 11c9116..464c3b9 100644 | ||
47 | --- a/linux-user/syscall.c | ||
48 | +++ b/linux-user/syscall.c | ||
49 | @@ -34,6 +34,7 @@ | ||
50 | #include <sys/resource.h> | ||
51 | #include <sys/swap.h> | ||
52 | #include <linux/capability.h> | ||
53 | +#include <linux/sockios.h> | ||
54 | #include <sched.h> | ||
55 | #include <sys/timex.h> | ||
56 | #ifdef __ia64__ | ||
57 | @@ -256,12 +257,12 @@ static type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5, \ | ||
58 | #define TARGET_NR__llseek TARGET_NR_llseek | ||
59 | #endif | ||
60 | |||
61 | -#ifdef __NR_gettid | ||
62 | -_syscall0(int, gettid) | ||
63 | +#ifdef __NR_sys_gettid | ||
64 | +_syscall0(int, sys_gettid) | ||
65 | #else | ||
66 | /* This is a replacement for the host gettid() and must return a host | ||
67 | errno. */ | ||
68 | -static int gettid(void) { | ||
69 | +static int sys_gettid(void) { | ||
70 | return -ENOSYS; | ||
71 | } | ||
72 | #endif | ||
73 | @@ -6246,7 +6247,7 @@ static void *clone_func(void *arg) | ||
74 | cpu = ENV_GET_CPU(env); | ||
75 | thread_cpu = cpu; | ||
76 | ts = (TaskState *)cpu->opaque; | ||
77 | - info->tid = gettid(); | ||
78 | + info->tid = sys_gettid(); | ||
79 | task_settid(ts); | ||
80 | if (info->child_tidptr) | ||
81 | put_user_u32(info->tid, info->child_tidptr); | ||
82 | @@ -6390,9 +6391,9 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, | ||
83 | mapping. We can't repeat the spinlock hack used above because | ||
84 | the child process gets its own copy of the lock. */ | ||
85 | if (flags & CLONE_CHILD_SETTID) | ||
86 | - put_user_u32(gettid(), child_tidptr); | ||
87 | + put_user_u32(sys_gettid(), child_tidptr); | ||
88 | if (flags & CLONE_PARENT_SETTID) | ||
89 | - put_user_u32(gettid(), parent_tidptr); | ||
90 | + put_user_u32(sys_gettid(), parent_tidptr); | ||
91 | ts = (TaskState *)cpu->opaque; | ||
92 | if (flags & CLONE_SETTLS) | ||
93 | cpu_set_tls (env, newtls); | ||
94 | @@ -11454,7 +11455,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, | ||
95 | break; | ||
96 | #endif | ||
97 | case TARGET_NR_gettid: | ||
98 | - ret = get_errno(gettid()); | ||
99 | + ret = get_errno(sys_gettid()); | ||
100 | break; | ||
101 | #ifdef TARGET_NR_readahead | ||
102 | case TARGET_NR_readahead: | ||
103 | -- | ||
104 | 2.7.4 | ||
105 | |||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb deleted file mode 100644 index 06481660..00000000 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb +++ /dev/null | |||
@@ -1,6 +0,0 @@ | |||
1 | require qemu-devicetrees.inc | ||
2 | |||
3 | XILINX_RELEASE_VERSION = "v2019.1" | ||
4 | |||
5 | BRANCH ?= "branch/xilinx-v2019.1" | ||
6 | SRCREV ?= "445406ef4d06303f00387f7d81e8718255336fd0" | ||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb new file mode 100644 index 00000000..22f19bfd --- /dev/null +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb | |||
@@ -0,0 +1,4 @@ | |||
1 | require qemu-devicetrees.inc | ||
2 | |||
3 | BRANCH ?= "branch/xilinx-v2019.2" | ||
4 | SRCREV ?= "d119986a6dd800bc3e71ea171b5b6741e0128289" | ||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc index aae607f5..438b9246 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc | |||
@@ -3,5 +3,5 @@ require qemu-xilinx.inc | |||
3 | 3 | ||
4 | DEPENDS = "glib-2.0-native zlib-native" | 4 | DEPENDS = "glib-2.0-native zlib-native" |
5 | 5 | ||
6 | SRC_URI_remove = "file://0012-fix-libcap-header-issue-on-some-distro.patch" | 6 | SRC_URI_remove = "file://0010-fix-libcap-header-issue-on-some-distro.patch" |
7 | SRC_URI_remove = "file://0013-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch" \ No newline at end of file | 7 | SRC_URI_remove = "file://0011-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch" |
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb index bc5a3850..2814de0c 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb | |||
@@ -3,5 +3,4 @@ BPN = "qemu-xilinx" | |||
3 | 3 | ||
4 | EXTRA_OECONF_append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent" | 4 | EXTRA_OECONF_append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent" |
5 | 5 | ||
6 | 6 | SRC_URI_append = " file://0001-linux-user-disable-qemu-bridge-helper-and-socket_scm.patch" | |
7 | SRC_URI_append = "file://0001-linux-user-disable-qemu-bridge-helper-and-socket_scm.patch" | ||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb index a138704e..93afebed 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb | |||
@@ -12,5 +12,6 @@ do_install_append() { | |||
12 | # The following is also installed by qemu-native | 12 | # The following is also installed by qemu-native |
13 | rm -f ${D}${datadir}/${BPN}/trace-events-all | 13 | rm -f ${D}${datadir}/${BPN}/trace-events-all |
14 | rm -rf ${D}${datadir}/${BPN}/keymaps | 14 | rm -rf ${D}${datadir}/${BPN}/keymaps |
15 | rm -rf ${D}${datadir}/icons | ||
15 | } | 16 | } |
16 | 17 | ||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc index ad44f098..657d6422 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc | |||
@@ -3,18 +3,17 @@ HOMEPAGE = "https://github.com/xilinx/qemu/" | |||
3 | 3 | ||
4 | QEMU_TARGETS = "aarch64 arm microblaze microblazeel" | 4 | QEMU_TARGETS = "aarch64 arm microblaze microblazeel" |
5 | 5 | ||
6 | XILINX_RELEASE_VERSION = "v2019.1" | ||
7 | XILINX_QEMU_VERSION ?= "v2.11.1" | ||
8 | BRANCH ?= "branch/xilinx-v2019.1" | ||
9 | SRCREV ?= "5f38ea92fb697b94ad43f01fe162f3ed6e6b0e16" | ||
10 | |||
11 | |||
12 | LIC_FILES_CHKSUM = " \ | 6 | LIC_FILES_CHKSUM = " \ |
13 | file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ | 7 | file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ |
14 | file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \ | 8 | file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \ |
15 | " | 9 | " |
16 | DEPENDS = "glib-2.0 zlib pixman" | 10 | DEPENDS = "glib-2.0 zlib pixman" |
17 | 11 | ||
12 | XILINX_RELEASE_VERSION = "v2019.2" | ||
13 | XILINX_QEMU_VERSION ?= "v2.11.1" | ||
14 | BRANCH ?= "branch/xilinx-v2019.2" | ||
15 | SRCREV ?= "6617fbc8be3525ca524f7d4ef7fc7b14c5b0c822" | ||
16 | |||
18 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:" | 17 | FILESEXTRAPATHS_prepend := "${THISDIR}/files:" |
19 | 18 | ||
20 | PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" | 19 | PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" |
@@ -24,13 +23,19 @@ REPO ?= "git://github.com/Xilinx/qemu.git;protocol=https" | |||
24 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | 23 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" |
25 | SRC_URI = "${REPO};${BRANCHARG}" | 24 | SRC_URI = "${REPO};${BRANCHARG}" |
26 | 25 | ||
26 | SRC_URI_append = " file://0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch" | ||
27 | |||
27 | S = "${WORKDIR}/git" | 28 | S = "${WORKDIR}/git" |
28 | 29 | ||
30 | EXTRA_OECONF_append= " --python=python2.7" | ||
31 | |||
29 | # Disable KVM completely | 32 | # Disable KVM completely |
30 | PACKAGECONFIG_remove = "kvm" | 33 | PACKAGECONFIG_remove = "kvm" |
34 | PACKAGECONFIG_append = " fdt" | ||
35 | PACKAGECONFIG[ssh] = "--enable-libssh,," | ||
31 | 36 | ||
32 | # Enable libgcrypt | 37 | # Enable libgcrypt |
33 | PACKAGECONFIG_append = " gcrypt" | 38 | PACKAGECONFIG_append = " gcrypt fdt alsa kvm" |
34 | 39 | ||
35 | DISABLE_STATIC_pn-${PN} = "" | 40 | DISABLE_STATIC_pn-${PN} = "" |
36 | 41 | ||
@@ -50,4 +55,4 @@ do_configure_prepend() { | |||
50 | do_install_append() { | 55 | do_install_append() { |
51 | # Prevent QA warnings about installed ${localstatedir}/run | 56 | # Prevent QA warnings about installed ${localstatedir}/run |
52 | if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi | 57 | if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi |
53 | } \ No newline at end of file | 58 | } |
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch new file mode 100644 index 00000000..a8ab7daa --- /dev/null +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch | |||
@@ -0,0 +1,93 @@ | |||
1 | From 5214dd4461f2090ef0965b4d2518f49927d61cbc Mon Sep 17 00:00:00 2001 | ||
2 | From: He Zhe <zhe.he@windriver.com> | ||
3 | Date: Wed, 28 Aug 2019 19:56:28 +0800 | ||
4 | Subject: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt | ||
5 | |||
6 | libgcrypt may also be controlled by pkg-config, this patch adds pkg-config | ||
7 | handling for libgcrypt. | ||
8 | |||
9 | Upstream-Status: Denied [https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg06333.html] | ||
10 | |||
11 | Signed-off-by: He Zhe <zhe.he@windriver.com> | ||
12 | --- | ||
13 | configure | 48 ++++++++++++++++++++++++++++++++++++++++-------- | ||
14 | 1 file changed, 40 insertions(+), 8 deletions(-) | ||
15 | |||
16 | diff --git a/configure b/configure | ||
17 | index e44e454..0f362a7 100755 | ||
18 | --- a/configure | ||
19 | +++ b/configure | ||
20 | @@ -2875,6 +2875,30 @@ has_libgcrypt() { | ||
21 | return 0 | ||
22 | } | ||
23 | |||
24 | +has_libgcrypt_pkgconfig() { | ||
25 | + if ! has $pkg_config ; then | ||
26 | + return 1 | ||
27 | + fi | ||
28 | + | ||
29 | + if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then | ||
30 | + return 1 | ||
31 | + fi | ||
32 | + | ||
33 | + if test -n "$cross_prefix" ; then | ||
34 | + host=$($pkg_config --variable=host libgcrypt) | ||
35 | + if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then | ||
36 | + print_error "host($host) does not match cross_prefix($cross_prefix)" | ||
37 | + return 1 | ||
38 | + fi | ||
39 | + fi | ||
40 | + | ||
41 | + if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then | ||
42 | + print_error "libgcrypt version is $($pkg_config --modversion libgcrypt)" | ||
43 | + return 1 | ||
44 | + fi | ||
45 | + | ||
46 | + return 0 | ||
47 | +} | ||
48 | |||
49 | if test "$nettle" != "no"; then | ||
50 | pass="no" | ||
51 | @@ -2902,7 +2926,14 @@ fi | ||
52 | |||
53 | if test "$gcrypt" != "no"; then | ||
54 | pass="no" | ||
55 | - if has_libgcrypt; then | ||
56 | + if has_libgcrypt_pkgconfig; then | ||
57 | + gcrypt_cflags=$($pkg_config --cflags libgcrypt) | ||
58 | + if test "$static" = "yes" ; then | ||
59 | + gcrypt_libs=$($pkg_config --libs --static libgcrypt) | ||
60 | + else | ||
61 | + gcrypt_libs=$($pkg_config --libs libgcrypt) | ||
62 | + fi | ||
63 | + elif has_libgcrypt; then | ||
64 | gcrypt_cflags=$(libgcrypt-config --cflags) | ||
65 | gcrypt_libs=$(libgcrypt-config --libs) | ||
66 | # Debian has removed -lgpg-error from libgcrypt-config | ||
67 | @@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then | ||
68 | then | ||
69 | gcrypt_libs="$gcrypt_libs -lgpg-error" | ||
70 | fi | ||
71 | + fi | ||
72 | |||
73 | - # Link test to make sure the given libraries work (e.g for static). | ||
74 | - write_c_skeleton | ||
75 | - if compile_prog "" "$gcrypt_libs" ; then | ||
76 | - LIBS="$gcrypt_libs $LIBS" | ||
77 | - QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" | ||
78 | - pass="yes" | ||
79 | - fi | ||
80 | + # Link test to make sure the given libraries work (e.g for static). | ||
81 | + write_c_skeleton | ||
82 | + if compile_prog "" "$gcrypt_libs" ; then | ||
83 | + LIBS="$gcrypt_libs $LIBS" | ||
84 | + QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags" | ||
85 | + pass="yes" | ||
86 | fi | ||
87 | + | ||
88 | if test "$pass" = "yes"; then | ||
89 | gcrypt="yes" | ||
90 | cat > $TMPC << EOF | ||
91 | -- | ||
92 | 2.7.4 | ||
93 | |||
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb index c158b185..d540f6c3 100644 --- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb +++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb | |||
@@ -11,3 +11,4 @@ EXTRA_OECONF_append_class-nativesdk = " --target-list=${@get_qemu_target_list(d) | |||
11 | do_install_append_class-nativesdk() { | 11 | do_install_append_class-nativesdk() { |
12 | ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} | 12 | ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)} |
13 | } | 13 | } |
14 | |||
diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb deleted file mode 100644 index 5bac31e9..00000000 --- a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb +++ /dev/null | |||
@@ -1,7 +0,0 @@ | |||
1 | LINUX_VERSION = "4.19" | ||
2 | XILINX_RELEASE_VERSION = "v2019.1" | ||
3 | KBRANCH ?= "xlnx_rebase_v4.19" | ||
4 | SRCREV ?= "9811303824b66a8db9a8ec61b570879336a9fde5" | ||
5 | |||
6 | include linux-xlnx.inc | ||
7 | |||
diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb new file mode 100644 index 00000000..58f163c4 --- /dev/null +++ b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb | |||
@@ -0,0 +1,6 @@ | |||
1 | LINUX_VERSION = "4.19" | ||
2 | KBRANCH ?= "xlnx_rebase_v4.19" | ||
3 | SRCREV ?= "b983d5fd71d4feaf494cdbe0593ecc29ed471cb8" | ||
4 | |||
5 | include linux-xlnx.inc | ||
6 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch index 5d29531d..28247daa 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 7fbf19ba660c72a1d4817780cad5c4ae52cbe0b5 Mon Sep 17 00:00:00 2001 | 1 | From 23e6126392ab228c1d6483c02ffc32b15f00777e Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 13:13:57 +0530 | 3 | Date: Wed, 11 Jan 2017 13:13:57 +0530 |
4 | Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic | 4 | Subject: [PATCH 01/63] LOCAL]: Testsuite - builtins tests require fpic |
5 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | 5 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> |
6 | 6 | ||
7 | Conflicts: | 7 | Conflicts: |
@@ -12,7 +12,7 @@ Conflicts: | |||
12 | 1 file changed, 8 insertions(+) | 12 | 1 file changed, 8 insertions(+) |
13 | 13 | ||
14 | diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 14 | diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
15 | index 9f0b24a..1cb4f97 100644 | 15 | index acb9eac..363ce07 100644 |
16 | --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 16 | --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
17 | +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 17 | +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
18 | @@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] | 18 | @@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch index 503b1ecf..8e4a2a32 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 4b675eeabceea22ec51abfa7c37e11a631e58659 Mon Sep 17 00:00:00 2001 | 1 | From e9c8884f473eae307945ceabaa1ff03278236c23 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 14:31:10 +0530 | 3 | Date: Wed, 11 Jan 2017 14:31:10 +0530 |
4 | Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This | 4 | Subject: [PATCH 02/63] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This |
5 | particular testcase fails with a timeout. Instead, fail it at compile-time | 5 | particular testcase fails with a timeout. Instead, fail it at compile-time |
6 | for microblaze. This speeds up the testsuite without removing it from the | 6 | for microblaze. This speeds up the testsuite without removing it from the |
7 | FAIL reports. | 7 | FAIL reports. |
@@ -12,7 +12,7 @@ Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> | |||
12 | 1 file changed, 4 insertions(+) | 12 | 1 file changed, 4 insertions(+) |
13 | 13 | ||
14 | diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C | 14 | diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C |
15 | index 66411cd..d951fee 100644 | 15 | index 3862756..db9f990 100644 |
16 | --- a/gcc/testsuite/g++.dg/opt/memcpy1.C | 16 | --- a/gcc/testsuite/g++.dg/opt/memcpy1.C |
17 | +++ b/gcc/testsuite/g++.dg/opt/memcpy1.C | 17 | +++ b/gcc/testsuite/g++.dg/opt/memcpy1.C |
18 | @@ -4,6 +4,10 @@ | 18 | @@ -4,6 +4,10 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch index 39058496..ef994457 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch | |||
@@ -1,11 +1,14 @@ | |||
1 | From 03d4d7335be2b2f72c199ab5177685b6dfd1a9d6 Mon Sep 17 00:00:00 2001 | 1 | From fb4b4d4ecba04859d52a653d7c453df92014dc38 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 15:28:38 +0530 | 3 | Date: Wed, 11 Jan 2017 15:28:38 +0530 |
4 | Subject: [PATCH 03/54] [LOCAL]: Testsuite - explicitly add -fivopts for tests | 4 | Subject: [PATCH 03/63] [LOCAL]: Testsuite - explicitly add -fivopts for tests |
5 | that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt | 5 | that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt |
6 | exist in 4.6 branch) | 6 | exist in 4.6 branch) |
7 | 7 | ||
8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> | 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> |
9 | |||
10 | Conflicts: | ||
11 | gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | ||
9 | --- | 12 | --- |
10 | gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +- | 13 | gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +- |
11 | gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +- | 14 | gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +- |
@@ -79,13 +82,13 @@ index 5f42857..9bc86ee 100644 | |||
79 | void foo(long); | 82 | void foo(long); |
80 | 83 | ||
81 | diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 84 | diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c |
82 | index 0fa5600..94caa44 100644 | 85 | index 50d86a0..1e3eacd 100644 |
83 | --- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 86 | --- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c |
84 | +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 87 | +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c |
85 | @@ -1,5 +1,5 @@ | 88 | @@ -1,5 +1,5 @@ |
86 | /* { dg-do compile } */ | 89 | /* { dg-do compile } */ |
87 | -/* { dg-options "-O2 -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ | 90 | -/* { dg-options "-O2 -fopt-info-loop-missed" } */ |
88 | +/* { dg-options "-O2 -fivopts -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ | 91 | +/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */ |
89 | extern void g(void); | 92 | extern void g(void); |
90 | 93 | ||
91 | void | 94 | void |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch index e16528b6..a575b518 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From a4c99f7f7775f105eb6f1dfbdf304e6b7e498e2e Mon Sep 17 00:00:00 2001 | 1 | From 38022a87b01cf2e36b605d4f6d0faab22a0d2f44 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 15:46:28 +0530 | 3 | Date: Wed, 11 Jan 2017 15:46:28 +0530 |
4 | Subject: [PATCH 04/54] [LOCAL]: For dejagnu static testing on qemu, suppress | 4 | Subject: [PATCH 04/63] [LOCAL]: For dejagnu static testing on qemu, suppress |
5 | warnings about multiple definitions from the test function and libc in line | 5 | warnings about multiple definitions from the test function and libc in line |
6 | with method used by powerpc. Dynamic linking and using a qemu binary which | 6 | with method used by powerpc. Dynamic linking and using a qemu binary which |
7 | understands sysroot resolves all test failures with builtins | 7 | understands sysroot resolves all test failures with builtins |
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
12 | 1 file changed, 4 deletions(-) | 12 | 1 file changed, 4 deletions(-) |
13 | 13 | ||
14 | diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 14 | diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
15 | index 1cb4f97..bdfa08a 100644 | 15 | index 363ce07..56b1a9a 100644 |
16 | --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 16 | --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
17 | +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 17 | +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp |
18 | @@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] | 18 | @@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch index 33688f14..18fd6dec 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 6b0de6811796b6834d426263eaa855b65c9b3389 Mon Sep 17 00:00:00 2001 | 1 | From a7dfb5f158f16f88b30aabe903c4fb088889eeef Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 15:50:35 +0530 | 3 | Date: Wed, 11 Jan 2017 15:50:35 +0530 |
4 | Subject: [PATCH 05/54] [Patch, testsuite]: Add MicroBlaze to target-supports | 4 | Subject: [PATCH 05/63] [Patch, testsuite]: Add MicroBlaze to target-supports |
5 | for atomic buil. .tin tests | 5 | for atomic buil. .tin tests |
6 | 6 | ||
7 | MicroBlaze added to supported targets for atomic builtin tests. | 7 | MicroBlaze added to supported targets for atomic builtin tests. |
@@ -19,10 +19,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
19 | 1 file changed, 1 insertion(+) | 19 | 1 file changed, 1 insertion(+) |
20 | 20 | ||
21 | diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp | 21 | diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp |
22 | index c591acd..94353cc 100644 | 22 | index cda0f3d..0a69659e 100644 |
23 | --- a/gcc/testsuite/lib/target-supports.exp | 23 | --- a/gcc/testsuite/lib/target-supports.exp |
24 | +++ b/gcc/testsuite/lib/target-supports.exp | 24 | +++ b/gcc/testsuite/lib/target-supports.exp |
25 | @@ -7428,6 +7428,7 @@ proc check_effective_target_sync_int_long { } { | 25 | @@ -6829,6 +6829,7 @@ proc check_effective_target_sync_int_long { } { |
26 | && [check_effective_target_arm_acq_rel]) | 26 | && [check_effective_target_arm_acq_rel]) |
27 | || [istarget bfin*-*linux*] | 27 | || [istarget bfin*-*linux*] |
28 | || [istarget hppa*-*linux*] | 28 | || [istarget hppa*-*linux*] |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch index b428d121..b428d121 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch index 3e2368f2..e4a86dc4 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 0d2cca275f3e85ae42dac7888d862975d65ffb36 Mon Sep 17 00:00:00 2001 | 1 | From e23b1a424cfd852f7a33f29c0b80d867ca533c3b Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 11 Jan 2017 16:20:01 +0530 | 3 | Date: Wed, 11 Jan 2017 16:20:01 +0530 |
4 | Subject: [PATCH 06/54] [Patch, testsuite]: Update MicroBlaze strings test for | 4 | Subject: [PATCH 06/63] [Patch, testsuite]: Update MicroBlaze strings test for |
5 | new scan-assembly output resulting in use of $LC label | 5 | new scan-assembly output resulting in use of $LC label |
6 | 6 | ||
7 | ChangeLog/testsuite | 7 | ChangeLog/testsuite |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch index bcd5dbad..8c43de05 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From b6f828da3caa827d8ccc08bbf260a2a01b2b2613 Mon Sep 17 00:00:00 2001 | 1 | From c210044f15df2433438b6b74e5c2bcf79458c2e4 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:14:15 +0530 | 3 | Date: Thu, 12 Jan 2017 16:14:15 +0530 |
4 | Subject: [PATCH 07/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern | 4 | Subject: [PATCH 07/63] [Patch, testsuite]: Allow MicroBlaze .weakext pattern |
5 | in regex match Extend regex pattern to include optional ext at the end of | 5 | in regex match Extend regex pattern to include optional ext at the end of |
6 | .weak to match the MicroBlaze weak label .weakext | 6 | .weak to match the MicroBlaze weak label .weakext |
7 | 7 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch index 6232535d..d02be316 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From d27a2545486da9c6a4d3d5ca06b4affb83f8d0a1 Mon Sep 17 00:00:00 2001 | 1 | From 283d8576d2599b3c38814e7c70e3f36ed51df9da Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:34:27 +0530 | 3 | Date: Thu, 12 Jan 2017 16:34:27 +0530 |
4 | Subject: [PATCH 08/54] [Patch, testsuite]: Add MicroBlaze to | 4 | Subject: [PATCH 08/63] [Patch, testsuite]: Add MicroBlaze to |
5 | check_profiling_available Testsuite, add microblaze*-*-* target in | 5 | check_profiling_available Testsuite, add microblaze*-*-* target in |
6 | check_profiling_available inline with other archs setting | 6 | check_profiling_available inline with other archs setting |
7 | profiling_available_saved to 0 | 7 | profiling_available_saved to 0 |
@@ -12,10 +12,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
12 | 1 file changed, 1 insertion(+) | 12 | 1 file changed, 1 insertion(+) |
13 | 13 | ||
14 | diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp | 14 | diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp |
15 | index 94353cc..ecfbe4d 100644 | 15 | index 0a69659e..d47819c 100644 |
16 | --- a/gcc/testsuite/lib/target-supports.exp | 16 | --- a/gcc/testsuite/lib/target-supports.exp |
17 | +++ b/gcc/testsuite/lib/target-supports.exp | 17 | +++ b/gcc/testsuite/lib/target-supports.exp |
18 | @@ -676,6 +676,7 @@ proc check_profiling_available { test_what } { | 18 | @@ -678,6 +678,7 @@ proc check_profiling_available { test_what } { |
19 | || [istarget m68k-*-elf] | 19 | || [istarget m68k-*-elf] |
20 | || [istarget m68k-*-uclinux*] | 20 | || [istarget m68k-*-uclinux*] |
21 | || [istarget mips*-*-elf*] | 21 | || [istarget mips*-*-elf*] |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch index db730f43..ae24c080 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 8711bdfe27bce04d35ba93a1d18ccccd61371829 Mon Sep 17 00:00:00 2001 | 1 | From 1905061b279e6fe5fd9861fc490fd4075edac4a8 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:41:43 +0530 | 3 | Date: Thu, 12 Jan 2017 16:41:43 +0530 |
4 | Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In | 4 | Subject: [PATCH 09/63] [Patch, microblaze]: Fix atomic side effects. In |
5 | atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions | 5 | atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions |
6 | during optimization. Previously, the outputs were considered unused; this | 6 | during optimization. Previously, the outputs were considered unused; this |
7 | generated assembly code with undefined side effects after invocation of the | 7 | generated assembly code with undefined side effects after invocation of the |
@@ -9,19 +9,22 @@ Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In | |||
9 | 9 | ||
10 | Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> | 10 | Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> |
11 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | 11 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> |
12 | |||
13 | Conflicts: | ||
14 | gcc/config/microblaze/microblaze.md | ||
12 | --- | 15 | --- |
13 | gcc/config/microblaze/microblaze.md | 3 +++ | 16 | gcc/config/microblaze/microblaze.md | 3 +++ |
14 | gcc/config/microblaze/sync.md | 21 +++++++++++++-------- | 17 | gcc/config/microblaze/sync.md | 21 +++++++++++++-------- |
15 | 2 files changed, 16 insertions(+), 8 deletions(-) | 18 | 2 files changed, 16 insertions(+), 8 deletions(-) |
16 | 19 | ||
17 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 20 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
18 | index f698e54..93f5fa2 100644 | 21 | index 183afff..7a40c53 100644 |
19 | --- a/gcc/config/microblaze/microblaze.md | 22 | --- a/gcc/config/microblaze/microblaze.md |
20 | +++ b/gcc/config/microblaze/microblaze.md | 23 | +++ b/gcc/config/microblaze/microblaze.md |
21 | @@ -41,6 +41,9 @@ | 24 | @@ -43,6 +43,9 @@ |
22 | (UNSPEC_CMP 104) ;; signed compare | ||
23 | (UNSPEC_CMPU 105) ;; unsigned compare | ||
24 | (UNSPEC_TLS 106) ;; jump table | 25 | (UNSPEC_TLS 106) ;; jump table |
26 | (UNSPEC_SET_TEXT 107) ;; set text start | ||
27 | (UNSPEC_TEXT 108) ;; data text relative | ||
25 | + (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) | 28 | + (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool) |
26 | + (UNSPECV_CAS_VAL 202) ;; compare and swap (val) | 29 | + (UNSPECV_CAS_VAL 202) ;; compare and swap (val) |
27 | + (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) | 30 | + (UNSPECV_CAS_MEM 203) ;; compare and swap (mem) |
@@ -29,7 +32,7 @@ index f698e54..93f5fa2 100644 | |||
29 | 32 | ||
30 | (define_c_enum "unspec" [ | 33 | (define_c_enum "unspec" [ |
31 | diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md | 34 | diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md |
32 | index b34bd54..8e694e9 100644 | 35 | index 6f16ca6..bebab5c 100644 |
33 | --- a/gcc/config/microblaze/sync.md | 36 | --- a/gcc/config/microblaze/sync.md |
34 | +++ b/gcc/config/microblaze/sync.md | 37 | +++ b/gcc/config/microblaze/sync.md |
35 | @@ -18,14 +18,19 @@ | 38 | @@ -18,14 +18,19 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch index 5058529a..07a43177 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 92015c19e5d1baabd62067bf1cfc4522e85d1b25 Mon Sep 17 00:00:00 2001 | 1 | From 65bc1969bd652df4bf9d01d30547a947da293550 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:45:45 +0530 | 3 | Date: Thu, 12 Jan 2017 16:45:45 +0530 |
4 | Subject: [PATCH 10/54] [Patch, microblaze]: Fix atomic boolean return value. | 4 | Subject: [PATCH 10/63] [Patch, microblaze]: Fix atomic boolean return value. |
5 | In atomic_compare_and_swapsi, fix boolean return value. Previously, it | 5 | In atomic_compare_and_swapsi, fix boolean return value. Previously, it |
6 | contained zero if successful and non-zero if unsuccessful. | 6 | contained zero if successful and non-zero if unsuccessful. |
7 | 7 | ||
@@ -12,7 +12,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
12 | 1 file changed, 4 insertions(+), 3 deletions(-) | 12 | 1 file changed, 4 insertions(+), 3 deletions(-) |
13 | 13 | ||
14 | diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md | 14 | diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md |
15 | index 8e694e9..8ddb10d 100644 | 15 | index bebab5c..72eac09 100644 |
16 | --- a/gcc/config/microblaze/sync.md | 16 | --- a/gcc/config/microblaze/sync.md |
17 | +++ b/gcc/config/microblaze/sync.md | 17 | +++ b/gcc/config/microblaze/sync.md |
18 | @@ -34,15 +34,16 @@ | 18 | @@ -34,15 +34,16 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch index 2451c938..b9ba239f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 658476aef537c0c2d031eb1c7a001f00c1d9bf7b Mon Sep 17 00:00:00 2001 | 1 | From 4e4409f10b450ec9254e69445ffeb8d116906d16 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:50:17 +0530 | 3 | Date: Thu, 12 Jan 2017 16:50:17 +0530 |
4 | Subject: [PATCH 11/54] [Patch, microblaze]: Fix the Microblaze crash with | 4 | Subject: [PATCH 11/63] [Patch, microblaze]: Fix the Microblaze crash with |
5 | msmall-divides flag Compiler is crashing when we use msmall-divides and | 5 | msmall-divides flag Compiler is crashing when we use msmall-divides and |
6 | mxl-barrel-shift flag. This is because when use above flags | 6 | mxl-barrel-shift flag. This is because when use above flags |
7 | microblaze_expand_divide function will be called for division operation. In | 7 | microblaze_expand_divide function will be called for division operation. In |
@@ -15,10 +15,10 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> | |||
15 | 1 file changed, 1 insertion(+), 2 deletions(-) | 15 | 1 file changed, 1 insertion(+), 2 deletions(-) |
16 | 16 | ||
17 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 17 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
18 | index 9a4a287..cbe8cb7 100644 | 18 | index 55c1bec..ae45038 100644 |
19 | --- a/gcc/config/microblaze/microblaze.c | 19 | --- a/gcc/config/microblaze/microblaze.c |
20 | +++ b/gcc/config/microblaze/microblaze.c | 20 | +++ b/gcc/config/microblaze/microblaze.c |
21 | @@ -3575,8 +3575,7 @@ microblaze_expand_divide (rtx operands[]) | 21 | @@ -3715,8 +3715,7 @@ microblaze_expand_divide (rtx operands[]) |
22 | mem_rtx = gen_rtx_MEM (QImode, | 22 | mem_rtx = gen_rtx_MEM (QImode, |
23 | gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); | 23 | gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); |
24 | 24 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch index b58df873..fc47bae6 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001 | 1 | From 6dbeb53f0185dd587ece39d624d193768633a7ab Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 16:52:56 +0530 | 3 | Date: Thu, 12 Jan 2017 16:52:56 +0530 |
4 | Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added | 4 | Subject: [PATCH 12/63] [Patch, microblaze]: Added ashrsi3_with_size_opt Added |
5 | ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os | 5 | ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os |
6 | optimization is used. lshrsi3_with_size_opt is being removed as it has | 6 | optimization is used. lshrsi3_with_size_opt is being removed as it has |
7 | conflicts with unsigned int variables | 7 | conflicts with unsigned int variables |
@@ -12,10 +12,10 @@ Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> | |||
12 | 1 file changed, 21 insertions(+) | 12 | 1 file changed, 21 insertions(+) |
13 | 13 | ||
14 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 14 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
15 | index 93f5fa2..fe90a14 100644 | 15 | index 7a40c53..3d2636e 100644 |
16 | --- a/gcc/config/microblaze/microblaze.md | 16 | --- a/gcc/config/microblaze/microblaze.md |
17 | +++ b/gcc/config/microblaze/microblaze.md | 17 | +++ b/gcc/config/microblaze/microblaze.md |
18 | @@ -1506,6 +1506,27 @@ | 18 | @@ -1508,6 +1508,27 @@ |
19 | (set_attr "length" "4,4")] | 19 | (set_attr "length" "4,4")] |
20 | ) | 20 | ) |
21 | 21 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch index 6af0f10e..3b4b4c70 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From ed23e22fb25a2d3dc357c0743f51b2735fc46a6a Mon Sep 17 00:00:00 2001 | 1 | From 53ab5a3fec283aeb9d2efeb632d423b774192e65 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 17:50:03 +0530 | 3 | Date: Thu, 12 Jan 2017 17:50:03 +0530 |
4 | Subject: [PATCH 13/54] [Patch, microblaze]: Fixed missing save of r18 in | 4 | Subject: [PATCH 13/63] [Patch, microblaze]: Fixed missing save of r18 in |
5 | fast_interrupt. Register 18 is used as a clobber register, and must be stored | 5 | fast_interrupt. Register 18 is used as a clobber register, and must be stored |
6 | when entering a fast_interrupt. Before this fix, register 18 was only saved | 6 | when entering a fast_interrupt. Before this fix, register 18 was only saved |
7 | if it was used directly in the interrupt function. | 7 | if it was used directly in the interrupt function. |
@@ -24,10 +24,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
24 | 1 file changed, 1 insertion(+), 1 deletion(-) | 24 | 1 file changed, 1 insertion(+), 1 deletion(-) |
25 | 25 | ||
26 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 26 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
27 | index cbe8cb7..6f0b4f4 100644 | 27 | index ae45038..c834b49 100644 |
28 | --- a/gcc/config/microblaze/microblaze.c | 28 | --- a/gcc/config/microblaze/microblaze.c |
29 | +++ b/gcc/config/microblaze/microblaze.c | 29 | +++ b/gcc/config/microblaze/microblaze.c |
30 | @@ -1967,7 +1967,7 @@ microblaze_must_save_register (int regno) | 30 | @@ -2043,7 +2043,7 @@ microblaze_must_save_register (int regno) |
31 | { | 31 | { |
32 | if (df_regs_ever_live_p (regno) | 32 | if (df_regs_ever_live_p (regno) |
33 | || regno == MB_ABI_MSR_SAVE_REG | 33 | || regno == MB_ABI_MSR_SAVE_REG |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch index f47265b0..889a1e69 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 582558f3c18d096885ab24e645899f310b148b5c Mon Sep 17 00:00:00 2001 | 1 | From cbf1854e3569122ee1143e6716ff68275c26aced Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 10:57:19 +0530 | 3 | Date: Tue, 17 Jan 2017 10:57:19 +0530 |
4 | Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls | 4 | Subject: [PATCH 14/63] [Patch, microblaze]: Use bralid for profiler calls |
5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> | 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,7 +9,7 @@ Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls | |||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 11 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
12 | index 0d3718f..88e0351 100644 | 12 | index fa0806e..0a435b8 100644 |
13 | --- a/gcc/config/microblaze/microblaze.h | 13 | --- a/gcc/config/microblaze/microblaze.h |
14 | +++ b/gcc/config/microblaze/microblaze.h | 14 | +++ b/gcc/config/microblaze/microblaze.h |
15 | @@ -486,7 +486,7 @@ typedef struct microblaze_args | 15 | @@ -486,7 +486,7 @@ typedef struct microblaze_args |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0015-Patch-microblaze-Disable-fivopts-by-default.patch index acfa083f..0ada80eb 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0015-Patch-microblaze-Disable-fivopts-by-default.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From b60068cbdd3c830e541fbd35f2ed119245911461 Mon Sep 17 00:00:00 2001 | 1 | From 604cae83ce9d2942568178966f69614acbbcbefd Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 11:10:21 +0530 | 3 | Date: Tue, 17 Jan 2017 11:10:21 +0530 |
4 | Subject: [PATCH 15/54] [Patch, microblaze]: Disable fivopts by default Turn | 4 | Subject: [PATCH 15/63] [Patch, microblaze]: Disable fivopts by default Turn |
5 | off ivopts by default. Interferes with cse. | 5 | off ivopts by default. Interferes with cse. |
6 | 6 | ||
7 | Changelog | 7 | Changelog |
@@ -18,7 +18,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
18 | 1 file changed, 9 insertions(+) | 18 | 1 file changed, 9 insertions(+) |
19 | 19 | ||
20 | diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c | 20 | diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c |
21 | index 3e75675..fe45f2e 100644 | 21 | index c30bdef..9b6ef21 100644 |
22 | --- a/gcc/common/config/microblaze/microblaze-common.c | 22 | --- a/gcc/common/config/microblaze/microblaze-common.c |
23 | +++ b/gcc/common/config/microblaze/microblaze-common.c | 23 | +++ b/gcc/common/config/microblaze/microblaze-common.c |
24 | @@ -24,6 +24,15 @@ | 24 | @@ -24,6 +24,15 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch index dbd7b2e2..87bc1668 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch | |||
@@ -1,10 +1,13 @@ | |||
1 | From 640628680ff6f028ad6d5fef2e41da29664f036f Mon Sep 17 00:00:00 2001 | 1 | From 14ddb3217fbb84c48903124ec6a3614b4707630d Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 12 Jan 2017 17:36:16 +0530 | 3 | Date: Thu, 12 Jan 2017 17:36:16 +0530 |
4 | Subject: [PATCH 16/54] [Patch, microblaze]: Removed moddi3 routinue Using the | 4 | Subject: [PATCH 16/63] [Patch, microblaze]: Removed moddi3 routinue Using the |
5 | default moddi3 function as the existing implementation has many bugs | 5 | default moddi3 function as the existing implementation has many bugs |
6 | 6 | ||
7 | Signed-off-by:Nagaraju <nmekala@xilix.com> | 7 | Signed-off-by:Nagaraju <nmekala@xilix.com> |
8 | |||
9 | Conflicts: | ||
10 | libgcc/config/microblaze/moddi3.S | ||
8 | --- | 11 | --- |
9 | libgcc/config/microblaze/moddi3.S | 121 ---------------------------------- | 12 | libgcc/config/microblaze/moddi3.S | 121 ---------------------------------- |
10 | libgcc/config/microblaze/t-microblaze | 3 +- | 13 | libgcc/config/microblaze/t-microblaze | 3 +- |
@@ -13,13 +16,13 @@ Signed-off-by:Nagaraju <nmekala@xilix.com> | |||
13 | 16 | ||
14 | diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S | 17 | diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S |
15 | deleted file mode 100644 | 18 | deleted file mode 100644 |
16 | index a8f17d7..0000000 | 19 | index abfe4fc..0000000 |
17 | --- a/libgcc/config/microblaze/moddi3.S | 20 | --- a/libgcc/config/microblaze/moddi3.S |
18 | +++ /dev/null | 21 | +++ /dev/null |
19 | @@ -1,121 +0,0 @@ | 22 | @@ -1,121 +0,0 @@ |
20 | -################################### | 23 | -################################### |
21 | -# | 24 | -# |
22 | -# Copyright (C) 2009-2018 Free Software Foundation, Inc. | 25 | -# Copyright (C) 2009-2019 Free Software Foundation, Inc. |
23 | -# | 26 | -# |
24 | -# Contributed by Michael Eager <eager@eagercon.com>. | 27 | -# Contributed by Michael Eager <eager@eagercon.com>. |
25 | -# | 28 | -# |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch index 6fb1b32f..ca1c2d1c 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From c0e74b79cc1db2f68dd560154225da1e5ddfd920 Mon Sep 17 00:00:00 2001 | 1 | From 032e50c1b267306338cff4d136db88f08350de72 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 14:41:58 +0530 | 3 | Date: Tue, 17 Jan 2017 14:41:58 +0530 |
4 | Subject: [PATCH 17/54] [Patch, microblaze]: Add INIT_PRIORITY support Added | 4 | Subject: [PATCH 17/63] [Patch, microblaze]: Add INIT_PRIORITY support Added |
5 | TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. | 5 | TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. |
6 | 6 | ||
7 | These macros allows users to control the order of initialization | 7 | These macros allows users to control the order of initialization |
@@ -26,10 +26,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
26 | 1 file changed, 53 insertions(+) | 26 | 1 file changed, 53 insertions(+) |
27 | 27 | ||
28 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 28 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
29 | index 6f0b4f4..53b44df 100644 | 29 | index c834b49..c54b96b 100644 |
30 | --- a/gcc/config/microblaze/microblaze.c | 30 | --- a/gcc/config/microblaze/microblaze.c |
31 | +++ b/gcc/config/microblaze/microblaze.c | 31 | +++ b/gcc/config/microblaze/microblaze.c |
32 | @@ -2554,6 +2554,53 @@ print_operand_address (FILE * file, rtx addr) | 32 | @@ -2642,6 +2642,53 @@ print_operand_address (FILE * file, rtx addr) |
33 | } | 33 | } |
34 | } | 34 | } |
35 | 35 | ||
@@ -83,7 +83,7 @@ index 6f0b4f4..53b44df 100644 | |||
83 | /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol | 83 | /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol |
84 | is used, so that we don't emit an .extern for it in | 84 | is used, so that we don't emit an .extern for it in |
85 | microblaze_asm_file_end. */ | 85 | microblaze_asm_file_end. */ |
86 | @@ -3841,6 +3888,12 @@ microblaze_starting_frame_offset (void) | 86 | @@ -3981,6 +4028,12 @@ microblaze_starting_frame_offset (void) |
87 | #undef TARGET_ATTRIBUTE_TABLE | 87 | #undef TARGET_ATTRIBUTE_TABLE |
88 | #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table | 88 | #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table |
89 | 89 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch index ab2473a3..de35f286 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 2cba68c3e27ffaea77cc5469233cf4dcb9383142 Mon Sep 17 00:00:00 2001 | 1 | From 6db9d068e32a424ac04c27e963d1e58cb3ef8bdf Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 15:23:57 +0530 | 3 | Date: Tue, 17 Jan 2017 15:23:57 +0530 |
4 | Subject: [PATCH 18/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel | 4 | Subject: [PATCH 18/63] [Patch, microblaze]: Add optimized lshrsi3 When barrel |
5 | shifter is not present, the immediate value is greater than #5 and | 5 | shifter is not present, the immediate value is greater than #5 and |
6 | optimization is -OS, the compiler will generate shift operation using loop. | 6 | optimization is -OS, the compiler will generate shift operation using loop. |
7 | 7 | ||
@@ -26,10 +26,10 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | |||
26 | create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c | 26 | create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c |
27 | 27 | ||
28 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 28 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
29 | index fe90a14..c063ffc 100644 | 29 | index 3d2636e..aa2eda3 100644 |
30 | --- a/gcc/config/microblaze/microblaze.md | 30 | --- a/gcc/config/microblaze/microblaze.md |
31 | +++ b/gcc/config/microblaze/microblaze.md | 31 | +++ b/gcc/config/microblaze/microblaze.md |
32 | @@ -1616,6 +1616,27 @@ | 32 | @@ -1618,6 +1618,27 @@ |
33 | (set_attr "length" "4,4")] | 33 | (set_attr "length" "4,4")] |
34 | ) | 34 | ) |
35 | 35 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch index 5afcff43..dc9b61cf 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From e8b05b5105655d276c93864ab90e15bfbe46cf74 Mon Sep 17 00:00:00 2001 | 1 | From 614bacc058b94c7b12cd40fde1b19b4709870f3b Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 15:42:15 +0530 | 3 | Date: Tue, 17 Jan 2017 15:42:15 +0530 |
4 | Subject: [PATCH 19/54] [Patch, microblaze]: Modified trap instruction The | 4 | Subject: [PATCH 19/63] [Patch, microblaze]: Modified trap instruction The |
5 | instruction was wrongly written to brki r0,-1 it should be bri r0. Modified | 5 | instruction was wrongly written to brki r0,-1 it should be bri r0. Modified |
6 | with the correct instruction | 6 | with the correct instruction |
7 | 7 | ||
@@ -12,10 +12,10 @@ Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | |||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | 13 | ||
14 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 14 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
15 | index c063ffc..7bbdbe1 100644 | 15 | index aa2eda3..3c80760 100644 |
16 | --- a/gcc/config/microblaze/microblaze.md | 16 | --- a/gcc/config/microblaze/microblaze.md |
17 | +++ b/gcc/config/microblaze/microblaze.md | 17 | +++ b/gcc/config/microblaze/microblaze.md |
18 | @@ -2344,7 +2344,7 @@ | 18 | @@ -2348,7 +2348,7 @@ |
19 | (define_insn "trap" | 19 | (define_insn "trap" |
20 | [(trap_if (const_int 1) (const_int 0))] | 20 | [(trap_if (const_int 1) (const_int 0))] |
21 | "" | 21 | "" |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch index 6e07ac4f..b60a4e95 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 0cc6aabbd3f7b331c3995f11efec545499297358 Mon Sep 17 00:00:00 2001 | 1 | From 372bbc75146166df9b82ca5e8f236971b7cef16e Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 16:42:44 +0530 | 3 | Date: Tue, 17 Jan 2017 16:42:44 +0530 |
4 | Subject: [PATCH 20/54] [Patch, microblaze]: Reducing Stack space for arguments | 4 | Subject: [PATCH 20/63] [Patch, microblaze]: Reducing Stack space for arguments |
5 | Currently in Microblaze target stack space for arguments in register is being | 5 | Currently in Microblaze target stack space for arguments in register is being |
6 | allocated even if there are no arguments in the function. This patch will | 6 | allocated even if there are no arguments in the function. This patch will |
7 | optimize the extra 24 bytes that are being allocated. | 7 | optimize the extra 24 bytes that are being allocated. |
@@ -22,10 +22,10 @@ ChangeLog: | |||
22 | 3 files changed, 136 insertions(+), 3 deletions(-) | 22 | 3 files changed, 136 insertions(+), 3 deletions(-) |
23 | 23 | ||
24 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h | 24 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h |
25 | index 4cbba0c..f8a56f7 100644 | 25 | index 1f5ca80..6647cbc 100644 |
26 | --- a/gcc/config/microblaze/microblaze-protos.h | 26 | --- a/gcc/config/microblaze/microblaze-protos.h |
27 | +++ b/gcc/config/microblaze/microblaze-protos.h | 27 | +++ b/gcc/config/microblaze/microblaze-protos.h |
28 | @@ -58,6 +58,7 @@ extern int symbol_mentioned_p (rtx); | 28 | @@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx); |
29 | extern int label_mentioned_p (rtx); | 29 | extern int label_mentioned_p (rtx); |
30 | extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); | 30 | extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); |
31 | extern void microblaze_eh_return (rtx op0); | 31 | extern void microblaze_eh_return (rtx op0); |
@@ -34,10 +34,10 @@ index 4cbba0c..f8a56f7 100644 | |||
34 | 34 | ||
35 | /* Declare functions in microblaze-c.c. */ | 35 | /* Declare functions in microblaze-c.c. */ |
36 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 36 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
37 | index 53b44df..0dec362 100644 | 37 | index c54b96b..0ce9d13 100644 |
38 | --- a/gcc/config/microblaze/microblaze.c | 38 | --- a/gcc/config/microblaze/microblaze.c |
39 | +++ b/gcc/config/microblaze/microblaze.c | 39 | +++ b/gcc/config/microblaze/microblaze.c |
40 | @@ -1989,6 +1989,138 @@ microblaze_must_save_register (int regno) | 40 | @@ -2065,6 +2065,138 @@ microblaze_must_save_register (int regno) |
41 | return 0; | 41 | return 0; |
42 | } | 42 | } |
43 | 43 | ||
@@ -176,7 +176,7 @@ index 53b44df..0dec362 100644 | |||
176 | /* Return the bytes needed to compute the frame pointer from the current | 176 | /* Return the bytes needed to compute the frame pointer from the current |
177 | stack pointer. | 177 | stack pointer. |
178 | 178 | ||
179 | @@ -3298,7 +3430,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | 179 | @@ -3411,7 +3543,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
180 | emit_insn (gen_indirect_jump (temp2)); | 180 | emit_insn (gen_indirect_jump (temp2)); |
181 | 181 | ||
182 | /* Run just enough of rest_of_compilation. This sequence was | 182 | /* Run just enough of rest_of_compilation. This sequence was |
@@ -186,7 +186,7 @@ index 53b44df..0dec362 100644 | |||
186 | shorten_branches (insn); | 186 | shorten_branches (insn); |
187 | final_start_function (insn, file, 1); | 187 | final_start_function (insn, file, 1); |
188 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 188 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
189 | index 88e0351..9f74ec8 100644 | 189 | index 0a435b8..346e47b 100644 |
190 | --- a/gcc/config/microblaze/microblaze.h | 190 | --- a/gcc/config/microblaze/microblaze.h |
191 | +++ b/gcc/config/microblaze/microblaze.h | 191 | +++ b/gcc/config/microblaze/microblaze.h |
192 | @@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info; | 192 | @@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch index b04ee580..c79f9552 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From f846bd900d5277dd9defb5fe0625f97e3417ee61 Mon Sep 17 00:00:00 2001 | 1 | From 1c226901aec38e2e824177418dcd82b6cd49ffca Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 17:04:37 +0530 | 3 | Date: Tue, 17 Jan 2017 17:04:37 +0530 |
4 | Subject: [PATCH 21/54] [Patch, microblaze]: Add cbranchsi4_reg This patch | 4 | Subject: [PATCH 21/63] [Patch, microblaze]: Add cbranchsi4_reg This patch |
5 | optimizes the generation of pcmpne/pcmpeq instruction if the compare | 5 | optimizes the generation of pcmpne/pcmpeq instruction if the compare |
6 | instruction has no immediate values.For the immediate values the xor | 6 | instruction has no immediate values.For the immediate values the xor |
7 | instruction is generated | 7 | instruction is generated |
@@ -31,10 +31,10 @@ Conflicts: | |||
31 | 8 files changed, 19 insertions(+), 19 deletions(-) | 31 | 8 files changed, 19 insertions(+), 19 deletions(-) |
32 | 32 | ||
33 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h | 33 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h |
34 | index f8a56f7..c39e2e9 100644 | 34 | index 6647cbc..bdc9b69 100644 |
35 | --- a/gcc/config/microblaze/microblaze-protos.h | 35 | --- a/gcc/config/microblaze/microblaze-protos.h |
36 | +++ b/gcc/config/microblaze/microblaze-protos.h | 36 | +++ b/gcc/config/microblaze/microblaze-protos.h |
37 | @@ -32,7 +32,7 @@ extern int microblaze_expand_shift (rtx *); | 37 | @@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *); |
38 | extern bool microblaze_expand_move (machine_mode, rtx *); | 38 | extern bool microblaze_expand_move (machine_mode, rtx *); |
39 | extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); | 39 | extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); |
40 | extern void microblaze_expand_divide (rtx *); | 40 | extern void microblaze_expand_divide (rtx *); |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch index beeb80fd..c3822d06 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 7d70a287544dd915b66a5658a3857ebecb8b3583 Mon Sep 17 00:00:00 2001 | 1 | From 791d65feae4f3cab47833579bc6f523e54194cbd Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 17:11:04 +0530 | 3 | Date: Tue, 17 Jan 2017 17:11:04 +0530 |
4 | Subject: [PATCH 22/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin. | 4 | Subject: [PATCH 22/63] [Patch,microblaze]: Inline Expansion of fsqrt builtin. |
5 | The changes are made in the patch for the inline expansion of the fsqrt | 5 | The changes are made in the patch for the inline expansion of the fsqrt |
6 | builtin with fqrt instruction. The sqrt math function takes double as | 6 | builtin with fqrt instruction. The sqrt math function takes double as |
7 | argument and return double as argument. The pattern is selected while | 7 | argument and return double as argument. The pattern is selected while |
@@ -29,10 +29,10 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com | |||
29 | 1 file changed, 14 insertions(+) | 29 | 1 file changed, 14 insertions(+) |
30 | 30 | ||
31 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 31 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
32 | index 7bbdbe1..3a53e24 100644 | 32 | index 3c80760..1fb5582 100644 |
33 | --- a/gcc/config/microblaze/microblaze.md | 33 | --- a/gcc/config/microblaze/microblaze.md |
34 | +++ b/gcc/config/microblaze/microblaze.md | 34 | +++ b/gcc/config/microblaze/microblaze.md |
35 | @@ -449,6 +449,20 @@ | 35 | @@ -451,6 +451,20 @@ |
36 | (set_attr "mode" "SF") | 36 | (set_attr "mode" "SF") |
37 | (set_attr "length" "4")]) | 37 | (set_attr "length" "4")]) |
38 | 38 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch index 8f5bed52..a314170f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From a28768eec0a9d5137196bed8e8c6d284cf4c3cbc Mon Sep 17 00:00:00 2001 | 1 | From 2c4a1d46e4f1b2342f899d6741d09dbf7cc87aa2 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 17:33:31 +0530 | 3 | Date: Tue, 17 Jan 2017 17:33:31 +0530 |
4 | Subject: [PATCH 23/54] [Patch] OPT: Update heuristics for loop-invariant for | 4 | Subject: [PATCH 23/63] [Patch] OPT: Update heuristics for loop-invariant for |
5 | address arithme. .tic. | 5 | address arithme. .tic. |
6 | 6 | ||
7 | The changes are made in the patch to update the heuristics | 7 | The changes are made in the patch to update the heuristics |
@@ -26,10 +26,10 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com | |||
26 | 1 file changed, 2 insertions(+), 4 deletions(-) | 26 | 1 file changed, 2 insertions(+), 4 deletions(-) |
27 | 27 | ||
28 | diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c | 28 | diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c |
29 | index bd31a51..8e22ca0 100644 | 29 | index b880ead..fd7a019 100644 |
30 | --- a/gcc/loop-invariant.c | 30 | --- a/gcc/loop-invariant.c |
31 | +++ b/gcc/loop-invariant.c | 31 | +++ b/gcc/loop-invariant.c |
32 | @@ -1466,10 +1466,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, | 32 | @@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, |
33 | 33 | ||
34 | if (! flag_ira_loop_pressure) | 34 | if (! flag_ira_loop_pressure) |
35 | { | 35 | { |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch index 85a749e5..a786ba09 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From be9c512be09fa4ef67870ab0456eb3781394dac3 Mon Sep 17 00:00:00 2001 | 1 | From c2b64f2f7a06231d8da0a53c6761939583ac56da Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 18:07:24 +0530 | 3 | Date: Tue, 17 Jan 2017 18:07:24 +0530 |
4 | Subject: [PATCH 24/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' | 4 | Subject: [PATCH 24/63] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' |
5 | insn definitions Change adddi3 to handle DI immediates as the second operand, | 5 | insn definitions Change adddi3 to handle DI immediates as the second operand, |
6 | this requires modification to the output template however reduces the need to | 6 | this requires modification to the output template however reduces the need to |
7 | specify seperate templates for 16-bit positive/negative immediate operands. | 7 | specify seperate templates for 16-bit positive/negative immediate operands. |
@@ -23,10 +23,10 @@ Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> | |||
23 | 1 file changed, 6 insertions(+), 7 deletions(-) | 23 | 1 file changed, 6 insertions(+), 7 deletions(-) |
24 | 24 | ||
25 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 25 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
26 | index 3a53e24..949e103 100644 | 26 | index 1fb5582..216219b 100644 |
27 | --- a/gcc/config/microblaze/microblaze.md | 27 | --- a/gcc/config/microblaze/microblaze.md |
28 | +++ b/gcc/config/microblaze/microblaze.md | 28 | +++ b/gcc/config/microblaze/microblaze.md |
29 | @@ -500,17 +500,16 @@ | 29 | @@ -502,17 +502,16 @@ |
30 | ;; Adding 2 DI operands in register or reg/imm | 30 | ;; Adding 2 DI operands in register or reg/imm |
31 | 31 | ||
32 | (define_insn "adddi3" | 32 | (define_insn "adddi3" |
@@ -49,7 +49,7 @@ index 3a53e24..949e103 100644 | |||
49 | 49 | ||
50 | ;;---------------------------------------------------------------- | 50 | ;;---------------------------------------------------------------- |
51 | ;; Subtraction | 51 | ;; Subtraction |
52 | @@ -547,7 +546,7 @@ | 52 | @@ -549,7 +548,7 @@ |
53 | (define_insn "subdi3" | 53 | (define_insn "subdi3" |
54 | [(set (match_operand:DI 0 "register_operand" "=&d") | 54 | [(set (match_operand:DI 0 "register_operand" "=&d") |
55 | (minus:DI (match_operand:DI 1 "register_operand" "d") | 55 | (minus:DI (match_operand:DI 1 "register_operand" "d") |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch index 17f25448..98310b36 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From c8ee051fa3e0ad05b19eb6141a7cb72245b412b7 Mon Sep 17 00:00:00 2001 | 1 | From c7e5c253b1e7800bc5ec8cc69850118ed938e22f Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 18:18:41 +0530 | 3 | Date: Tue, 17 Jan 2017 18:18:41 +0530 |
4 | Subject: [PATCH 25/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns | 4 | Subject: [PATCH 25/63] [Patch, microblaze]: Update ashlsi3 & movsf patterns |
5 | This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand | 5 | This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand |
6 | of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal | 6 | of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal |
7 | patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our | 7 | patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our |
@@ -27,10 +27,10 @@ ChangeLog: | |||
27 | 2 files changed, 9 insertions(+), 3 deletions(-) | 27 | 2 files changed, 9 insertions(+), 3 deletions(-) |
28 | 28 | ||
29 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 29 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
30 | index 0dec362..daf0269 100644 | 30 | index 0ce9d13..7669668 100644 |
31 | --- a/gcc/config/microblaze/microblaze.c | 31 | --- a/gcc/config/microblaze/microblaze.c |
32 | +++ b/gcc/config/microblaze/microblaze.c | 32 | +++ b/gcc/config/microblaze/microblaze.c |
33 | @@ -2531,7 +2531,7 @@ print_operand (FILE * file, rtx op, int letter) | 33 | @@ -2608,7 +2608,7 @@ print_operand (FILE * file, rtx op, int letter) |
34 | unsigned long value_long; | 34 | unsigned long value_long; |
35 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), | 35 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), |
36 | value_long); | 36 | value_long); |
@@ -40,10 +40,10 @@ index 0dec362..daf0269 100644 | |||
40 | else | 40 | else |
41 | { | 41 | { |
42 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 42 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
43 | index 949e103..bc675ca 100644 | 43 | index 216219b..4bc209c 100644 |
44 | --- a/gcc/config/microblaze/microblaze.md | 44 | --- a/gcc/config/microblaze/microblaze.md |
45 | +++ b/gcc/config/microblaze/microblaze.md | 45 | +++ b/gcc/config/microblaze/microblaze.md |
46 | @@ -1366,7 +1366,10 @@ | 46 | @@ -1368,7 +1368,10 @@ |
47 | (match_operand:SI 2 "immediate_operand" "I")))] | 47 | (match_operand:SI 2 "immediate_operand" "I")))] |
48 | "!TARGET_SOFT_MUL | 48 | "!TARGET_SOFT_MUL |
49 | && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" | 49 | && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)" |
@@ -55,7 +55,7 @@ index 949e103..bc675ca 100644 | |||
55 | ;; This MUL will not generate an imm. Can go into a delay slot. | 55 | ;; This MUL will not generate an imm. Can go into a delay slot. |
56 | [(set_attr "type" "arith") | 56 | [(set_attr "type" "arith") |
57 | (set_attr "mode" "SI") | 57 | (set_attr "mode" "SI") |
58 | @@ -1378,7 +1381,10 @@ | 58 | @@ -1380,7 +1383,10 @@ |
59 | (ashift:SI (match_operand:SI 1 "register_operand" "d") | 59 | (ashift:SI (match_operand:SI 1 "register_operand" "d") |
60 | (match_operand:SI 2 "immediate_operand" "I")))] | 60 | (match_operand:SI 2 "immediate_operand" "I")))] |
61 | "!TARGET_SOFT_MUL" | 61 | "!TARGET_SOFT_MUL" |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch index 506714bd..ba80ce45 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 64e76f3be6ad78044ea2b89b555a07758c2b2950 Mon Sep 17 00:00:00 2001 | 1 | From c3b633b0ee8d228a7d70a02b574822aba9a0fd93 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 17 Jan 2017 19:50:34 +0530 | 3 | Date: Tue, 17 Jan 2017 19:50:34 +0530 |
4 | Subject: [PATCH 26/54] [Patch, microblaze]: 8-stage pipeline for microblaze | 4 | Subject: [PATCH 26/63] [Patch, microblaze]: 8-stage pipeline for microblaze |
5 | This patch adds the support for the 8-stage pipeline. The new 8-stage | 5 | This patch adds the support for the 8-stage pipeline. The new 8-stage |
6 | pipeline reduces the latencies of float & integer division drastically | 6 | pipeline reduces the latencies of float & integer division drastically |
7 | 7 | ||
@@ -28,11 +28,11 @@ ChangeLog: | |||
28 | 4 files changed, 96 insertions(+), 3 deletions(-) | 28 | 4 files changed, 96 insertions(+), 3 deletions(-) |
29 | 29 | ||
30 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 30 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
31 | index daf0269..3832d16 100644 | 31 | index 7669668..ae7d5dd 100644 |
32 | --- a/gcc/config/microblaze/microblaze.c | 32 | --- a/gcc/config/microblaze/microblaze.c |
33 | +++ b/gcc/config/microblaze/microblaze.c | 33 | +++ b/gcc/config/microblaze/microblaze.c |
34 | @@ -1772,6 +1772,19 @@ microblaze_option_override (void) | 34 | @@ -1848,6 +1848,19 @@ microblaze_option_override (void) |
35 | warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a"); | 35 | "%<-mcpu=v8.30.a%>"); |
36 | TARGET_REORDER = 0; | 36 | TARGET_REORDER = 0; |
37 | } | 37 | } |
38 | + ver = ver_int - microblaze_version_to_int("v10.0"); | 38 | + ver = ver_int - microblaze_version_to_int("v10.0"); |
@@ -50,9 +50,9 @@ index daf0269..3832d16 100644 | |||
50 | + } | 50 | + } |
51 | 51 | ||
52 | if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) | 52 | if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) |
53 | error ("-mxl-multiply-high requires -mno-xl-soft-mul"); | 53 | error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>"); |
54 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 54 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
55 | index 9f74ec8..2ac5aeec 100644 | 55 | index 346e47b..bf7f3b4 100644 |
56 | --- a/gcc/config/microblaze/microblaze.h | 56 | --- a/gcc/config/microblaze/microblaze.h |
57 | +++ b/gcc/config/microblaze/microblaze.h | 57 | +++ b/gcc/config/microblaze/microblaze.h |
58 | @@ -27,7 +27,8 @@ | 58 | @@ -27,7 +27,8 @@ |
@@ -66,7 +66,7 @@ index 9f74ec8..2ac5aeec 100644 | |||
66 | 66 | ||
67 | #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 | 67 | #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 |
68 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 68 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
69 | index bc675ca..6395533 100644 | 69 | index 4bc209c..b7c16ac 100644 |
70 | --- a/gcc/config/microblaze/microblaze.md | 70 | --- a/gcc/config/microblaze/microblaze.md |
71 | +++ b/gcc/config/microblaze/microblaze.md | 71 | +++ b/gcc/config/microblaze/microblaze.md |
72 | @@ -35,6 +35,7 @@ | 72 | @@ -35,6 +35,7 @@ |
@@ -77,7 +77,7 @@ index bc675ca..6395533 100644 | |||
77 | (UNSPEC_SET_GOT 101) ;; | 77 | (UNSPEC_SET_GOT 101) ;; |
78 | (UNSPEC_GOTOFF 102) ;; GOT offset | 78 | (UNSPEC_GOTOFF 102) ;; GOT offset |
79 | (UNSPEC_PLT 103) ;; jump table | 79 | (UNSPEC_PLT 103) ;; jump table |
80 | @@ -80,7 +81,7 @@ | 80 | @@ -82,7 +83,7 @@ |
81 | ;; bshift Shift operations | 81 | ;; bshift Shift operations |
82 | 82 | ||
83 | (define_attr "type" | 83 | (define_attr "type" |
@@ -86,7 +86,7 @@ index bc675ca..6395533 100644 | |||
86 | (const_string "unknown")) | 86 | (const_string "unknown")) |
87 | 87 | ||
88 | ;; Main data type used by the insn | 88 | ;; Main data type used by the insn |
89 | @@ -222,6 +223,80 @@ | 89 | @@ -224,6 +225,80 @@ |
90 | ;;----------------------------------------------------------------- | 90 | ;;----------------------------------------------------------------- |
91 | 91 | ||
92 | 92 | ||
@@ -167,7 +167,7 @@ index bc675ca..6395533 100644 | |||
167 | ;;---------------------------------------------------------------- | 167 | ;;---------------------------------------------------------------- |
168 | ;; Microblaze 5-stage pipeline description (v5.00.a and later) | 168 | ;; Microblaze 5-stage pipeline description (v5.00.a and later) |
169 | ;;---------------------------------------------------------------- | 169 | ;;---------------------------------------------------------------- |
170 | @@ -468,7 +543,7 @@ | 170 | @@ -470,7 +545,7 @@ |
171 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] | 171 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] |
172 | "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | 172 | "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" |
173 | "fint\t%0,%1" | 173 | "fint\t%0,%1" |
@@ -177,10 +177,10 @@ index bc675ca..6395533 100644 | |||
177 | (set_attr "length" "4")]) | 177 | (set_attr "length" "4")]) |
178 | 178 | ||
179 | diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt | 179 | diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt |
180 | index 8242998..c8e6f00 100644 | 180 | index 2e46941..d23f376 100644 |
181 | --- a/gcc/config/microblaze/microblaze.opt | 181 | --- a/gcc/config/microblaze/microblaze.opt |
182 | +++ b/gcc/config/microblaze/microblaze.opt | 182 | +++ b/gcc/config/microblaze/microblaze.opt |
183 | @@ -129,3 +129,7 @@ Use hardware prefetch instruction | 183 | @@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE). |
184 | 184 | ||
185 | mxl-mode-xilkernel | 185 | mxl-mode-xilkernel |
186 | Target | 186 | Target |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch index 95b9b2aa..330b5494 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 5147c831c6a78d9b95138b679bb2ca7624abc3a1 Mon Sep 17 00:00:00 2001 | 1 | From 650cbdea7bc810e2bd0ebc5eb5647ed513498670 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 11:08:40 +0530 | 3 | Date: Wed, 18 Jan 2017 11:08:40 +0530 |
4 | Subject: [PATCH 27/54] [Patch,rtl Optimization]: Better register pressure | 4 | Subject: [PATCH 27/63] [Patch,rtl Optimization]: Better register pressure |
5 | estimate for loop . .invariant code motion | 5 | estimate for loop . .invariant code motion |
6 | 6 | ||
7 | Calculate the loop liveness used for regs for calculating the register pressure | 7 | Calculate the loop liveness used for regs for calculating the register pressure |
@@ -41,7 +41,7 @@ Signed-off-by:Ajit Agarwal ajitkum@xilinx.com. | |||
41 | 2 files changed, 50 insertions(+), 17 deletions(-) | 41 | 2 files changed, 50 insertions(+), 17 deletions(-) |
42 | 42 | ||
43 | diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c | 43 | diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c |
44 | index 3af0b2d..123dc6b 100644 | 44 | index 6dbe96f..ec5cba2 100644 |
45 | --- a/gcc/cfgloopanal.c | 45 | --- a/gcc/cfgloopanal.c |
46 | +++ b/gcc/cfgloopanal.c | 46 | +++ b/gcc/cfgloopanal.c |
47 | @@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, | 47 | @@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, |
@@ -56,10 +56,10 @@ index 3af0b2d..123dc6b 100644 | |||
56 | them. */ | 56 | them. */ |
57 | cost = target_reg_cost [speed] * n_new; | 57 | cost = target_reg_cost [speed] * n_new; |
58 | diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c | 58 | diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c |
59 | index 8e22ca0..c9ec8df 100644 | 59 | index fd7a019..ad54297 100644 |
60 | --- a/gcc/loop-invariant.c | 60 | --- a/gcc/loop-invariant.c |
61 | +++ b/gcc/loop-invariant.c | 61 | +++ b/gcc/loop-invariant.c |
62 | @@ -1520,7 +1520,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, | 62 | @@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, |
63 | size_cost = 0; | 63 | size_cost = 0; |
64 | } | 64 | } |
65 | 65 | ||
@@ -68,7 +68,7 @@ index 8e22ca0..c9ec8df 100644 | |||
68 | } | 68 | } |
69 | 69 | ||
70 | /* Finds invariant with best gain for moving. Returns the gain, stores | 70 | /* Finds invariant with best gain for moving. Returns the gain, stores |
71 | @@ -1614,22 +1614,53 @@ find_invariants_to_move (bool speed, bool call_p) | 71 | @@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p) |
72 | /* REGS_USED is actually never used when the flag is on. */ | 72 | /* REGS_USED is actually never used when the flag is on. */ |
73 | regs_used = 0; | 73 | regs_used = 0; |
74 | else | 74 | else |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch index 3643ff19..b5ee2c8c 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 2715b235b3db423bf35b9304a2ba5daa86b1680e Mon Sep 17 00:00:00 2001 | 1 | From 8f8c6cd35a2cf79449c0155fa865a665d730e541 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 11:25:48 +0530 | 3 | Date: Wed, 18 Jan 2017 11:25:48 +0530 |
4 | Subject: [PATCH 28/54] [Patch, microblaze]: Correct the const high double | 4 | Subject: [PATCH 28/63] [Patch, microblaze]: Correct the const high double |
5 | immediate value With this patch the loading of the DI mode immediate values | 5 | immediate value With this patch the loading of the DI mode immediate values |
6 | will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE | 6 | will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE |
7 | functions, as CONST_DOUBLE_HIGH was returning the sign extension value even | 7 | functions, as CONST_DOUBLE_HIGH was returning the sign extension value even |
@@ -24,10 +24,10 @@ ChangeLog: | |||
24 | create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c | 24 | create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c |
25 | 25 | ||
26 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 26 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
27 | index 3832d16..29cd54f 100644 | 27 | index ae7d5dd..002d7a5 100644 |
28 | --- a/gcc/config/microblaze/microblaze.c | 28 | --- a/gcc/config/microblaze/microblaze.c |
29 | +++ b/gcc/config/microblaze/microblaze.c | 29 | +++ b/gcc/config/microblaze/microblaze.c |
30 | @@ -2517,14 +2517,18 @@ print_operand (FILE * file, rtx op, int letter) | 30 | @@ -2594,14 +2594,18 @@ print_operand (FILE * file, rtx op, int letter) |
31 | else if (letter == 'h' || letter == 'j') | 31 | else if (letter == 'h' || letter == 'j') |
32 | { | 32 | { |
33 | long val[2]; | 33 | long val[2]; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch index b4b9d2ec..cbfc98de 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 7e025a0b22eee87bf9597267918bd16fc87c85c2 Mon Sep 17 00:00:00 2001 | 1 | From 30402c3bcfeb8a93656957b22558997b65d69cb8 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 11:49:58 +0530 | 3 | Date: Wed, 18 Jan 2017 11:49:58 +0530 |
4 | Subject: [PATCH 29/54] [Fix, microblaze]: Fix internal compiler error with | 4 | Subject: [PATCH 29/63] [Fix, microblaze]: Fix internal compiler error with |
5 | msmall-divides This patch will fix the internal error | 5 | msmall-divides This patch will fix the internal error |
6 | microblaze_expand_divide function which comes because of rtx PLUS where the | 6 | microblaze_expand_divide function which comes because of rtx PLUS where the |
7 | mem_rtx is of type SI and the operand is of type QImode. This patch modifies | 7 | mem_rtx is of type SI and the operand is of type QImode. This patch modifies |
@@ -19,10 +19,10 @@ ChangeLog: | |||
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | 19 | 1 file changed, 1 insertion(+), 1 deletion(-) |
20 | 20 | ||
21 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 21 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
22 | index 29cd54f..f8a417c 100644 | 22 | index 002d7a5..c662952 100644 |
23 | --- a/gcc/config/microblaze/microblaze.c | 23 | --- a/gcc/config/microblaze/microblaze.c |
24 | +++ b/gcc/config/microblaze/microblaze.c | 24 | +++ b/gcc/config/microblaze/microblaze.c |
25 | @@ -3769,7 +3769,7 @@ microblaze_expand_divide (rtx operands[]) | 25 | @@ -3909,7 +3909,7 @@ microblaze_expand_divide (rtx operands[]) |
26 | emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); | 26 | emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); |
27 | emit_insn (gen_addsi3 (regt1, regt1, operands[2])); | 27 | emit_insn (gen_addsi3 (regt1, regt1, operands[2])); |
28 | mem_rtx = gen_rtx_MEM (QImode, | 28 | mem_rtx = gen_rtx_MEM (QImode, |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch index 52fd4bea..fce06359 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 27a69d1873221747121360d0a1dffc4336a1d0cc Mon Sep 17 00:00:00 2001 | 1 | From 5ac80cf926c4dc96cbfd189f02c9250865b52dd3 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 12:03:39 +0530 | 3 | Date: Wed, 18 Jan 2017 12:03:39 +0530 |
4 | Subject: [PATCH 30/54] [patch,microblaze]: Fix the calculation of high word in | 4 | Subject: [PATCH 30/63] [patch,microblaze]: Fix the calculation of high word in |
5 | a long long 6. .4-bit | 5 | a long long 6. .4-bit |
6 | 6 | ||
7 | This patch will change the calculation of high word in a long long 64-bit. | 7 | This patch will change the calculation of high word in a long long 64-bit. |
@@ -27,10 +27,10 @@ ChangeLog: | |||
27 | 1 file changed, 3 deletions(-) | 27 | 1 file changed, 3 deletions(-) |
28 | 28 | ||
29 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 29 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
30 | index f8a417c..70d8d03 100644 | 30 | index c662952..8013a2c 100644 |
31 | --- a/gcc/config/microblaze/microblaze.c | 31 | --- a/gcc/config/microblaze/microblaze.c |
32 | +++ b/gcc/config/microblaze/microblaze.c | 32 | +++ b/gcc/config/microblaze/microblaze.c |
33 | @@ -2535,9 +2535,6 @@ print_operand (FILE * file, rtx op, int letter) | 33 | @@ -2612,9 +2612,6 @@ print_operand (FILE * file, rtx op, int letter) |
34 | { | 34 | { |
35 | val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; | 35 | val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; |
36 | val[1] = INTVAL (op) & 0x00000000ffffffffLL; | 36 | val[1] = INTVAL (op) & 0x00000000ffffffffLL; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch index 57144523..cbf64d97 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 35569bb20a5bb881f7f275d901a0be3408b16622 Mon Sep 17 00:00:00 2001 | 1 | From 45deb5bd3ae8c3db360ef181c9873e37d2288848 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 12:14:51 +0530 | 3 | Date: Wed, 18 Jan 2017 12:14:51 +0530 |
4 | Subject: [PATCH 31/54] [Patch, microblaze]: Add new bit-field instructions | 4 | Subject: [PATCH 31/63] [Patch, microblaze]: Add new bit-field instructions |
5 | This patches adds new bsefi and bsifi instructions. BSEFI- The instruction | 5 | This patches adds new bsefi and bsifi instructions. BSEFI- The instruction |
6 | shall extract a bit field from a register and place it right-adjusted in the | 6 | shall extract a bit field from a register and place it right-adjusted in the |
7 | destination register. The other bits in the destination register shall be set | 7 | destination register. The other bits in the destination register shall be set |
@@ -20,10 +20,10 @@ ChangeLog: | |||
20 | 1 file changed, 73 insertions(+) | 20 | 1 file changed, 73 insertions(+) |
21 | 21 | ||
22 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 22 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
23 | index 6395533..5a2dd13 100644 | 23 | index b7c16ac..67b298a 100644 |
24 | --- a/gcc/config/microblaze/microblaze.md | 24 | --- a/gcc/config/microblaze/microblaze.md |
25 | +++ b/gcc/config/microblaze/microblaze.md | 25 | +++ b/gcc/config/microblaze/microblaze.md |
26 | @@ -980,6 +980,8 @@ | 26 | @@ -982,6 +982,8 @@ |
27 | (set_attr "mode" "DI") | 27 | (set_attr "mode" "DI") |
28 | (set_attr "length" "20,20,20")]) | 28 | (set_attr "length" "20,20,20")]) |
29 | 29 | ||
@@ -32,7 +32,7 @@ index 6395533..5a2dd13 100644 | |||
32 | ;;---------------------------------------------------------------- | 32 | ;;---------------------------------------------------------------- |
33 | ;; Data movement | 33 | ;; Data movement |
34 | ;;---------------------------------------------------------------- | 34 | ;;---------------------------------------------------------------- |
35 | @@ -1774,6 +1776,7 @@ | 35 | @@ -1776,6 +1778,7 @@ |
36 | (set_attr "length" "28")] | 36 | (set_attr "length" "28")] |
37 | ) | 37 | ) |
38 | 38 | ||
@@ -40,7 +40,7 @@ index 6395533..5a2dd13 100644 | |||
40 | ;;---------------------------------------------------------------- | 40 | ;;---------------------------------------------------------------- |
41 | ;; Setting a register from an integer comparison. | 41 | ;; Setting a register from an integer comparison. |
42 | ;;---------------------------------------------------------------- | 42 | ;;---------------------------------------------------------------- |
43 | @@ -2473,4 +2476,74 @@ | 43 | @@ -2489,4 +2492,74 @@ |
44 | DONE; | 44 | DONE; |
45 | }") | 45 | }") |
46 | 46 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch index dce1bc58..86df58b3 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 3db8f0c3124d3001d3c10e6d400943f3ec57616b Mon Sep 17 00:00:00 2001 | 1 | From bc95cc12b2c4d96ea709eefc4b99181b8c40b19c Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 12:42:10 +0530 | 3 | Date: Wed, 18 Jan 2017 12:42:10 +0530 |
4 | Subject: [PATCH 32/54] [Patch, microblaze]: Fix bug in MB version calculation | 4 | Subject: [PATCH 32/63] [Patch, microblaze]: Fix bug in MB version calculation |
5 | This patch fixes the bug in microblaze_version_to_int function. Earlier the | 5 | This patch fixes the bug in microblaze_version_to_int function. Earlier the |
6 | conversion of vXX.YY.Z to int has a bug which is fixed now. | 6 | conversion of vXX.YY.Z to int has a bug which is fixed now. |
7 | 7 | ||
@@ -12,10 +12,10 @@ Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com> | |||
12 | 1 file changed, 70 insertions(+), 77 deletions(-) | 12 | 1 file changed, 70 insertions(+), 77 deletions(-) |
13 | 13 | ||
14 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 14 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
15 | index 70d8d03..30a0fcf 100644 | 15 | index 8013a2c..3f68ef0 100644 |
16 | --- a/gcc/config/microblaze/microblaze.c | 16 | --- a/gcc/config/microblaze/microblaze.c |
17 | +++ b/gcc/config/microblaze/microblaze.c | 17 | +++ b/gcc/config/microblaze/microblaze.c |
18 | @@ -238,6 +238,63 @@ section *sdata2_section; | 18 | @@ -239,6 +239,63 @@ section *sdata2_section; |
19 | #define TARGET_HAVE_TLS true | 19 | #define TARGET_HAVE_TLS true |
20 | #endif | 20 | #endif |
21 | 21 | ||
@@ -79,7 +79,7 @@ index 70d8d03..30a0fcf 100644 | |||
79 | /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ | 79 | /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ |
80 | static bool | 80 | static bool |
81 | microblaze_const_double_ok (rtx op, machine_mode mode) | 81 | microblaze_const_double_ok (rtx op, machine_mode mode) |
82 | @@ -1266,8 +1323,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, | 82 | @@ -1338,8 +1395,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, |
83 | { | 83 | { |
84 | if (TARGET_BARREL_SHIFT) | 84 | if (TARGET_BARREL_SHIFT) |
85 | { | 85 | { |
@@ -89,7 +89,7 @@ index 70d8d03..30a0fcf 100644 | |||
89 | *total = COSTS_N_INSNS (1); | 89 | *total = COSTS_N_INSNS (1); |
90 | else | 90 | else |
91 | *total = COSTS_N_INSNS (2); | 91 | *total = COSTS_N_INSNS (2); |
92 | @@ -1328,8 +1384,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, | 92 | @@ -1400,8 +1456,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, |
93 | } | 93 | } |
94 | else if (!TARGET_SOFT_MUL) | 94 | else if (!TARGET_SOFT_MUL) |
95 | { | 95 | { |
@@ -99,7 +99,7 @@ index 70d8d03..30a0fcf 100644 | |||
99 | *total = COSTS_N_INSNS (1); | 99 | *total = COSTS_N_INSNS (1); |
100 | else | 100 | else |
101 | *total = COSTS_N_INSNS (3); | 101 | *total = COSTS_N_INSNS (3); |
102 | @@ -1609,72 +1664,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, | 102 | @@ -1682,72 +1737,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, |
103 | return 0; | 103 | return 0; |
104 | } | 104 | } |
105 | 105 | ||
@@ -173,7 +173,7 @@ index 70d8d03..30a0fcf 100644 | |||
173 | 173 | ||
174 | microblaze_section_threshold = (global_options_set.x_g_switch_value | 174 | microblaze_section_threshold = (global_options_set.x_g_switch_value |
175 | ? g_switch_value | 175 | ? g_switch_value |
176 | @@ -1695,13 +1691,13 @@ microblaze_option_override (void) | 176 | @@ -1768,13 +1764,13 @@ microblaze_option_override (void) |
177 | /* Check the MicroBlaze CPU version for any special action to be done. */ | 177 | /* Check the MicroBlaze CPU version for any special action to be done. */ |
178 | if (microblaze_select_cpu == NULL) | 178 | if (microblaze_select_cpu == NULL) |
179 | microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; | 179 | microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; |
@@ -182,7 +182,7 @@ index 70d8d03..30a0fcf 100644 | |||
182 | + ver_int = microblaze_version_to_int (microblaze_select_cpu); | 182 | + ver_int = microblaze_version_to_int (microblaze_select_cpu); |
183 | + if (ver_int == -1) | 183 | + if (ver_int == -1) |
184 | { | 184 | { |
185 | error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu); | 185 | error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu); |
186 | } | 186 | } |
187 | 187 | ||
188 | - ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); | 188 | - ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a"); |
@@ -190,7 +190,7 @@ index 70d8d03..30a0fcf 100644 | |||
190 | if (ver < 0) | 190 | if (ver < 0) |
191 | { | 191 | { |
192 | /* No hardware exceptions in earlier versions. So no worries. */ | 192 | /* No hardware exceptions in earlier versions. So no worries. */ |
193 | @@ -1712,8 +1708,7 @@ microblaze_option_override (void) | 193 | @@ -1785,8 +1781,7 @@ microblaze_option_override (void) |
194 | microblaze_pipe = MICROBLAZE_PIPE_3; | 194 | microblaze_pipe = MICROBLAZE_PIPE_3; |
195 | } | 195 | } |
196 | else if (ver == 0 | 196 | else if (ver == 0 |
@@ -200,7 +200,7 @@ index 70d8d03..30a0fcf 100644 | |||
200 | { | 200 | { |
201 | #if 0 | 201 | #if 0 |
202 | microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); | 202 | microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); |
203 | @@ -1730,11 +1725,9 @@ microblaze_option_override (void) | 203 | @@ -1803,11 +1798,9 @@ microblaze_option_override (void) |
204 | #endif | 204 | #endif |
205 | microblaze_no_unsafe_delay = 0; | 205 | microblaze_no_unsafe_delay = 0; |
206 | microblaze_pipe = MICROBLAZE_PIPE_5; | 206 | microblaze_pipe = MICROBLAZE_PIPE_5; |
@@ -215,7 +215,7 @@ index 70d8d03..30a0fcf 100644 | |||
215 | { | 215 | { |
216 | /* Pattern compares are to be turned on by default only when | 216 | /* Pattern compares are to be turned on by default only when |
217 | compiling for MB v5.00.'z'. */ | 217 | compiling for MB v5.00.'z'. */ |
218 | @@ -1742,7 +1735,7 @@ microblaze_option_override (void) | 218 | @@ -1815,7 +1808,7 @@ microblaze_option_override (void) |
219 | } | 219 | } |
220 | } | 220 | } |
221 | 221 | ||
@@ -224,8 +224,8 @@ index 70d8d03..30a0fcf 100644 | |||
224 | if (ver < 0) | 224 | if (ver < 0) |
225 | { | 225 | { |
226 | if (TARGET_MULTIPLY_HIGH) | 226 | if (TARGET_MULTIPLY_HIGH) |
227 | @@ -1750,7 +1743,7 @@ microblaze_option_override (void) | 227 | @@ -1824,7 +1817,7 @@ microblaze_option_override (void) |
228 | "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater"); | 228 | "%<-mcpu=v6.00.a%> or greater"); |
229 | } | 229 | } |
230 | 230 | ||
231 | - ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); | 231 | - ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a"); |
@@ -233,7 +233,7 @@ index 70d8d03..30a0fcf 100644 | |||
233 | microblaze_has_clz = 1; | 233 | microblaze_has_clz = 1; |
234 | if (ver < 0) | 234 | if (ver < 0) |
235 | { | 235 | { |
236 | @@ -1759,7 +1752,7 @@ microblaze_option_override (void) | 236 | @@ -1833,7 +1826,7 @@ microblaze_option_override (void) |
237 | } | 237 | } |
238 | 238 | ||
239 | /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ | 239 | /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0033-Fixing-the-bug-in-the-bit-field-instruction.patch index 15111477..68f70ae8 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0033-Fixing-the-bug-in-the-bit-field-instruction.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From f3e259923788176ebb323155cc089e68c6de0895 Mon Sep 17 00:00:00 2001 | 1 | From 51da0572e0650378e422030b26d1258c8fc76df6 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 13:57:48 +0530 | 3 | Date: Wed, 18 Jan 2017 13:57:48 +0530 |
4 | Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field | 4 | Subject: [PATCH 33/63] Fixing the bug in the bit-field instruction. Bit field |
5 | instruction should be generated only if mcpu >10.0 | 5 | instruction should be generated only if mcpu >10.0 |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -10,10 +10,10 @@ Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field | |||
10 | 2 files changed, 5 insertions(+) | 10 | 2 files changed, 5 insertions(+) |
11 | 11 | ||
12 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 12 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
13 | index 30a0fcf..835e906 100644 | 13 | index 3f68ef0..a37f08eea 100644 |
14 | --- a/gcc/config/microblaze/microblaze.c | 14 | --- a/gcc/config/microblaze/microblaze.c |
15 | +++ b/gcc/config/microblaze/microblaze.c | 15 | +++ b/gcc/config/microblaze/microblaze.c |
16 | @@ -163,6 +163,9 @@ int microblaze_no_unsafe_delay; | 16 | @@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay; |
17 | /* Set to one if the targeted core has the CLZ insn. */ | 17 | /* Set to one if the targeted core has the CLZ insn. */ |
18 | int microblaze_has_clz = 0; | 18 | int microblaze_has_clz = 0; |
19 | 19 | ||
@@ -24,7 +24,7 @@ index 30a0fcf..835e906 100644 | |||
24 | version having only a particular type of pipeline. There can still be | 24 | version having only a particular type of pipeline. There can still be |
25 | options on the CPU to scale pipeline features up or down. :( | 25 | options on the CPU to scale pipeline features up or down. :( |
26 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 26 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
27 | index 2ac5aeec..991d0f7 100644 | 27 | index bf7f3b4..1d05e6e 100644 |
28 | --- a/gcc/config/microblaze/microblaze.h | 28 | --- a/gcc/config/microblaze/microblaze.h |
29 | +++ b/gcc/config/microblaze/microblaze.h | 29 | +++ b/gcc/config/microblaze/microblaze.h |
30 | @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; | 30 | @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch index f22f2f3f..04326205 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 52cf8e91f06ce9259d4d94bb8ea5cb327825b806 Mon Sep 17 00:00:00 2001 | 1 | From 132b913b721f66c5db17f62dd5559bbca11bb875 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 18 Jan 2017 20:57:10 +0530 | 3 | Date: Wed, 18 Jan 2017 20:57:10 +0530 |
4 | Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal | 4 | Subject: [PATCH 34/63] [Patch, microblaze]: Macros used in Xilinx internal |
5 | patches has been removed in gcc 6.2 version so modified the code accordingly. | 5 | patches has been removed in gcc 6.2 version so modified the code accordingly. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal | |||
9 | 1 file changed, 3 insertions(+), 5 deletions(-) | 9 | 1 file changed, 3 insertions(+), 5 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 11 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
12 | index 835e906..2e3b4c9 100644 | 12 | index a37f08eea..71640e5 100644 |
13 | --- a/gcc/config/microblaze/microblaze.c | 13 | --- a/gcc/config/microblaze/microblaze.c |
14 | +++ b/gcc/config/microblaze/microblaze.c | 14 | +++ b/gcc/config/microblaze/microblaze.c |
15 | @@ -2520,11 +2520,9 @@ print_operand (FILE * file, rtx op, int letter) | 15 | @@ -2597,11 +2597,9 @@ print_operand (FILE * file, rtx op, int letter) |
16 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); | 16 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); |
17 | else | 17 | else |
18 | { | 18 | { |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0035-Fixing-the-issue-with-the-builtin_alloc.patch index 00d67bcf..91ac0d02 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0035-Fixing-the-issue-with-the-builtin_alloc.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 727b0f7ae03279177559f5d85d8920352bd853b2 Mon Sep 17 00:00:00 2001 | 1 | From e672184af6a43b773131181270c7a8c5c5273bd8 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Thu, 23 Feb 2017 17:09:04 +0530 | 3 | Date: Thu, 23 Feb 2017 17:09:04 +0530 |
4 | Subject: [PATCH 35/54] Fixing the issue with the builtin_alloc. register r18 | 4 | Subject: [PATCH 35/63] Fixing the issue with the builtin_alloc. register r18 |
5 | was not properly handling the stack pattern which was resolved by using free | 5 | was not properly handling the stack pattern which was resolved by using free |
6 | available register | 6 | available register |
7 | 7 | ||
@@ -11,10 +11,10 @@ signed-off-by:nagaraju mekala <nmekala@xilinx.com> | |||
11 | 1 file changed, 4 insertions(+), 4 deletions(-) | 11 | 1 file changed, 4 insertions(+), 4 deletions(-) |
12 | 12 | ||
13 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 13 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
14 | index 5a2dd13..8072ffc 100644 | 14 | index 67b298a..7bae957 100644 |
15 | --- a/gcc/config/microblaze/microblaze.md | 15 | --- a/gcc/config/microblaze/microblaze.md |
16 | +++ b/gcc/config/microblaze/microblaze.md | 16 | +++ b/gcc/config/microblaze/microblaze.md |
17 | @@ -2076,10 +2076,10 @@ | 17 | @@ -2078,10 +2078,10 @@ |
18 | "" | 18 | "" |
19 | { | 19 | { |
20 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); | 20 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
@@ -27,7 +27,7 @@ index 5a2dd13..8072ffc 100644 | |||
27 | if (GET_CODE (operands[1]) != CONST_INT) | 27 | if (GET_CODE (operands[1]) != CONST_INT) |
28 | { | 28 | { |
29 | neg_op0 = gen_reg_rtx (Pmode); | 29 | neg_op0 = gen_reg_rtx (Pmode); |
30 | @@ -2088,9 +2088,9 @@ | 30 | @@ -2090,9 +2090,9 @@ |
31 | neg_op0 = GEN_INT (- INTVAL (operands[1])); | 31 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
32 | 32 | ||
33 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | 33 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch index 54ccd9a0..7079789f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 7156e379a67fa47a5fb9ede1448c0d528dbda65b Mon Sep 17 00:00:00 2001 | 1 | From ac30efb4a5f5b6d289fdd27b268c2095d60dcb42 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Thu, 2 Mar 2017 19:02:31 +0530 | 3 | Date: Thu, 2 Mar 2017 19:02:31 +0530 |
4 | Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before | 4 | Subject: [PATCH 36/63] [Patch,Microblaze]:reverting the cost check before |
5 | propagating constants. | 5 | propagating constants. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,7 +9,7 @@ Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before | |||
9 | 1 file changed, 4 insertions(+) | 9 | 1 file changed, 4 insertions(+) |
10 | 10 | ||
11 | diff --git a/gcc/cprop.c b/gcc/cprop.c | 11 | diff --git a/gcc/cprop.c b/gcc/cprop.c |
12 | index e4df509..deb706b 100644 | 12 | index 65c0130..42bcc81 100644 |
13 | --- a/gcc/cprop.c | 13 | --- a/gcc/cprop.c |
14 | +++ b/gcc/cprop.c | 14 | +++ b/gcc/cprop.c |
15 | @@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) | 15 | @@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch index 26b685a5..ba0f8e80 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001 | 1 | From f436198b817f33d56aaddb88ff629378498de489 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Mon, 19 Feb 2018 18:06:16 +0530 | 3 | Date: Mon, 19 Feb 2018 18:06:16 +0530 |
4 | Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield | 4 | Subject: [PATCH 37/63] [Patch,Microblaze]: update in constraints for bitfield |
5 | insert and extract instructions. | 5 | insert and extract instructions. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield | |||
9 | 1 file changed, 7 insertions(+), 36 deletions(-) | 9 | 1 file changed, 7 insertions(+), 36 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
12 | index 8072ffc..9bb87ec 100644 | 12 | index 7bae957..6101387 100644 |
13 | --- a/gcc/config/microblaze/microblaze.md | 13 | --- a/gcc/config/microblaze/microblaze.md |
14 | +++ b/gcc/config/microblaze/microblaze.md | 14 | +++ b/gcc/config/microblaze/microblaze.md |
15 | @@ -2476,33 +2476,17 @@ | 15 | @@ -2492,33 +2492,17 @@ |
16 | DONE; | 16 | DONE; |
17 | }") | 17 | }") |
18 | 18 | ||
@@ -51,7 +51,7 @@ index 8072ffc..9bb87ec 100644 | |||
51 | [(set (match_operand:SI 0 "register_operand" "=r") | 51 | [(set (match_operand:SI 0 "register_operand" "=r") |
52 | (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | 52 | (zero_extract:SI (match_operand:SI 1 "register_operand" "r") |
53 | (match_operand:SI 2 "immediate_operand" "I") | 53 | (match_operand:SI 2 "immediate_operand" "I") |
54 | @@ -2519,21 +2503,8 @@ | 54 | @@ -2535,21 +2519,8 @@ |
55 | (match_operand:SI 2 "immediate_operand" "I")) | 55 | (match_operand:SI 2 "immediate_operand" "I")) |
56 | (match_operand:SI 3 "register_operand" "r"))] | 56 | (match_operand:SI 3 "register_operand" "r"))] |
57 | "TARGET_HAS_BITFIELD" | 57 | "TARGET_HAS_BITFIELD" |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch index d8ae6c15..2b90880f 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 5494699756f8e1dba6848fcf09780a031139c232 Mon Sep 17 00:00:00 2001 | 1 | From 89aa1907ab0abad38e394f46f7e5f577bdb26498 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Mon, 4 Jun 2018 10:10:18 +0530 | 3 | Date: Mon, 4 Jun 2018 10:10:18 +0530 |
4 | Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for | 4 | Subject: [PATCH 38/63] [Patch,Microblaze] : Removed fsqrt generation for |
5 | double values. | 5 | double values. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for | |||
9 | 1 file changed, 14 deletions(-) | 9 | 1 file changed, 14 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
12 | index 9bb87ec..a93ddd0 100644 | 12 | index 6101387..eb01221 100644 |
13 | --- a/gcc/config/microblaze/microblaze.md | 13 | --- a/gcc/config/microblaze/microblaze.md |
14 | +++ b/gcc/config/microblaze/microblaze.md | 14 | +++ b/gcc/config/microblaze/microblaze.md |
15 | @@ -524,20 +524,6 @@ | 15 | @@ -526,20 +526,6 @@ |
16 | (set_attr "mode" "SF") | 16 | (set_attr "mode" "SF") |
17 | (set_attr "length" "4")]) | 17 | (set_attr "length" "4")]) |
18 | 18 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch index 88497a8e..f524cba2 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch | |||
@@ -1,22 +1,24 @@ | |||
1 | From 6e8b37bf54646c38fb4071d542a60ea92715df9b Mon Sep 17 00:00:00 2001 | 1 | From 68359cc8e82f63d01a77c39c68e782e6757cd71e Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Tue, 3 Apr 2018 16:48:39 +0530 | 3 | Date: Tue, 3 Apr 2018 16:48:39 +0530 |
4 | Subject: [PATCH 39/54] Intial commit of 64-bit Microblaze | 4 | Subject: [PATCH 39/63] Intial commit of 64-bit Microblaze |
5 | 5 | ||
6 | Conflicts: | ||
7 | gcc/config/microblaze/microblaze.opt | ||
6 | --- | 8 | --- |
7 | gcc/config/microblaze/microblaze-protos.h | 1 + | 9 | gcc/config/microblaze/microblaze-protos.h | 1 + |
8 | gcc/config/microblaze/microblaze.c | 109 +++++++-- | 10 | gcc/config/microblaze/microblaze.c | 109 +++++++-- |
9 | gcc/config/microblaze/microblaze.h | 4 +- | 11 | gcc/config/microblaze/microblaze.h | 4 +- |
10 | gcc/config/microblaze/microblaze.md | 370 +++++++++++++++++++++++++++++- | 12 | gcc/config/microblaze/microblaze.md | 370 +++++++++++++++++++++++++++++- |
11 | gcc/config/microblaze/microblaze.opt | 9 +- | 13 | gcc/config/microblaze/microblaze.opt | 7 +- |
12 | gcc/config/microblaze/t-microblaze | 7 +- | 14 | gcc/config/microblaze/t-microblaze | 7 +- |
13 | 6 files changed, 461 insertions(+), 39 deletions(-) | 15 | 6 files changed, 460 insertions(+), 38 deletions(-) |
14 | 16 | ||
15 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h | 17 | diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h |
16 | index c39e2e9..a5ed62e 100644 | 18 | index bdc9b69..7d6c189 100644 |
17 | --- a/gcc/config/microblaze/microblaze-protos.h | 19 | --- a/gcc/config/microblaze/microblaze-protos.h |
18 | +++ b/gcc/config/microblaze/microblaze-protos.h | 20 | +++ b/gcc/config/microblaze/microblaze-protos.h |
19 | @@ -35,6 +35,7 @@ extern void microblaze_expand_divide (rtx *); | 21 | @@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *); |
20 | extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); | 22 | extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); |
21 | extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); | 23 | extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); |
22 | extern void microblaze_expand_conditional_branch_sf (rtx *); | 24 | extern void microblaze_expand_conditional_branch_sf (rtx *); |
@@ -25,10 +27,10 @@ index c39e2e9..a5ed62e 100644 | |||
25 | extern void print_operand (FILE *, rtx, int); | 27 | extern void print_operand (FILE *, rtx, int); |
26 | extern void print_operand_address (FILE *, rtx); | 28 | extern void print_operand_address (FILE *, rtx); |
27 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 29 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
28 | index 2e3b4c9..2079ae9 100644 | 30 | index 71640e5..f740f5c 100644 |
29 | --- a/gcc/config/microblaze/microblaze.c | 31 | --- a/gcc/config/microblaze/microblaze.c |
30 | +++ b/gcc/config/microblaze/microblaze.c | 32 | +++ b/gcc/config/microblaze/microblaze.c |
31 | @@ -3457,11 +3457,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) | 33 | @@ -3570,11 +3570,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) |
32 | op0 = operands[0]; | 34 | op0 = operands[0]; |
33 | op1 = operands[1]; | 35 | op1 = operands[1]; |
34 | 36 | ||
@@ -43,7 +45,7 @@ index 2e3b4c9..2079ae9 100644 | |||
43 | emit_move_insn (op0, temp); | 45 | emit_move_insn (op0, temp); |
44 | return true; | 46 | return true; |
45 | } | 47 | } |
46 | @@ -3499,12 +3499,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) | 48 | @@ -3639,12 +3639,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) |
47 | && (flag_pic == 2 || microblaze_tls_symbol_p (p0) | 49 | && (flag_pic == 2 || microblaze_tls_symbol_p (p0) |
48 | || !SMALL_INT (p1))))) | 50 | || !SMALL_INT (p1))))) |
49 | { | 51 | { |
@@ -58,7 +60,7 @@ index 2e3b4c9..2079ae9 100644 | |||
58 | return true; | 60 | return true; |
59 | } | 61 | } |
60 | } | 62 | } |
61 | @@ -3635,7 +3635,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) | 63 | @@ -3775,7 +3775,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) |
62 | rtx cmp_op0 = operands[1]; | 64 | rtx cmp_op0 = operands[1]; |
63 | rtx cmp_op1 = operands[2]; | 65 | rtx cmp_op1 = operands[2]; |
64 | rtx label1 = operands[3]; | 66 | rtx label1 = operands[3]; |
@@ -67,7 +69,7 @@ index 2e3b4c9..2079ae9 100644 | |||
67 | rtx condition; | 69 | rtx condition; |
68 | 70 | ||
69 | gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); | 71 | gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); |
70 | @@ -3644,23 +3644,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) | 72 | @@ -3784,23 +3784,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) |
71 | if (cmp_op1 == const0_rtx) | 73 | if (cmp_op1 == const0_rtx) |
72 | { | 74 | { |
73 | comp_reg = cmp_op0; | 75 | comp_reg = cmp_op0; |
@@ -110,7 +112,7 @@ index 2e3b4c9..2079ae9 100644 | |||
110 | } | 112 | } |
111 | } | 113 | } |
112 | 114 | ||
113 | @@ -3671,7 +3684,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) | 115 | @@ -3811,7 +3824,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) |
114 | rtx cmp_op0 = operands[1]; | 116 | rtx cmp_op0 = operands[1]; |
115 | rtx cmp_op1 = operands[2]; | 117 | rtx cmp_op1 = operands[2]; |
116 | rtx label1 = operands[3]; | 118 | rtx label1 = operands[3]; |
@@ -119,7 +121,7 @@ index 2e3b4c9..2079ae9 100644 | |||
119 | rtx condition; | 121 | rtx condition; |
120 | 122 | ||
121 | gcc_assert ((GET_CODE (cmp_op0) == REG) | 123 | gcc_assert ((GET_CODE (cmp_op0) == REG) |
122 | @@ -3682,30 +3695,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) | 124 | @@ -3822,30 +3835,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) |
123 | { | 125 | { |
124 | comp_reg = cmp_op0; | 126 | comp_reg = cmp_op0; |
125 | condition = gen_rtx_fmt_ee (signed_condition (code), | 127 | condition = gen_rtx_fmt_ee (signed_condition (code), |
@@ -195,7 +197,7 @@ index 2e3b4c9..2079ae9 100644 | |||
195 | } | 197 | } |
196 | } | 198 | } |
197 | 199 | ||
198 | @@ -3722,6 +3768,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) | 200 | @@ -3862,6 +3908,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) |
199 | emit_jump_insn (gen_condjump (condition, operands[3])); | 201 | emit_jump_insn (gen_condjump (condition, operands[3])); |
200 | } | 202 | } |
201 | 203 | ||
@@ -216,7 +218,7 @@ index 2e3b4c9..2079ae9 100644 | |||
216 | 218 | ||
217 | static bool | 219 | static bool |
218 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 220 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
219 | index 991d0f7..72fbee5 100644 | 221 | index 1d05e6e..2ca44f5 100644 |
220 | --- a/gcc/config/microblaze/microblaze.h | 222 | --- a/gcc/config/microblaze/microblaze.h |
221 | +++ b/gcc/config/microblaze/microblaze.h | 223 | +++ b/gcc/config/microblaze/microblaze.h |
222 | @@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; | 224 | @@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; |
@@ -245,10 +247,10 @@ index 991d0f7..72fbee5 100644 | |||
245 | #define FLOAT_TYPE_SIZE 32 | 247 | #define FLOAT_TYPE_SIZE 32 |
246 | #define DOUBLE_TYPE_SIZE 64 | 248 | #define DOUBLE_TYPE_SIZE 64 |
247 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 249 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
248 | index a93ddd0..6976b37 100644 | 250 | index eb01221..dbb592e 100644 |
249 | --- a/gcc/config/microblaze/microblaze.md | 251 | --- a/gcc/config/microblaze/microblaze.md |
250 | +++ b/gcc/config/microblaze/microblaze.md | 252 | +++ b/gcc/config/microblaze/microblaze.md |
251 | @@ -495,7 +495,6 @@ | 253 | @@ -497,7 +497,6 @@ |
252 | (set_attr "mode" "SF") | 254 | (set_attr "mode" "SF") |
253 | (set_attr "length" "4")]) | 255 | (set_attr "length" "4")]) |
254 | 256 | ||
@@ -256,7 +258,7 @@ index a93ddd0..6976b37 100644 | |||
256 | (define_insn "divsf3" | 258 | (define_insn "divsf3" |
257 | [(set (match_operand:SF 0 "register_operand" "=d") | 259 | [(set (match_operand:SF 0 "register_operand" "=d") |
258 | (div:SF (match_operand:SF 1 "register_operand" "d") | 260 | (div:SF (match_operand:SF 1 "register_operand" "d") |
259 | @@ -506,6 +505,7 @@ | 261 | @@ -508,6 +507,7 @@ |
260 | (set_attr "mode" "SF") | 262 | (set_attr "mode" "SF") |
261 | (set_attr "length" "4")]) | 263 | (set_attr "length" "4")]) |
262 | 264 | ||
@@ -264,7 +266,7 @@ index a93ddd0..6976b37 100644 | |||
264 | (define_insn "sqrtsf2" | 266 | (define_insn "sqrtsf2" |
265 | [(set (match_operand:SF 0 "register_operand" "=d") | 267 | [(set (match_operand:SF 0 "register_operand" "=d") |
266 | (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] | 268 | (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] |
267 | @@ -560,6 +560,18 @@ | 269 | @@ -562,6 +562,18 @@ |
268 | 270 | ||
269 | ;; Adding 2 DI operands in register or reg/imm | 271 | ;; Adding 2 DI operands in register or reg/imm |
270 | 272 | ||
@@ -283,7 +285,7 @@ index a93ddd0..6976b37 100644 | |||
283 | (define_insn "adddi3" | 285 | (define_insn "adddi3" |
284 | [(set (match_operand:DI 0 "register_operand" "=d,d") | 286 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
285 | (plus:DI (match_operand:DI 1 "register_operand" "%d,d") | 287 | (plus:DI (match_operand:DI 1 "register_operand" "%d,d") |
286 | @@ -604,6 +616,18 @@ | 288 | @@ -606,6 +618,18 @@ |
287 | ;; Double Precision Subtraction | 289 | ;; Double Precision Subtraction |
288 | ;;---------------------------------------------------------------- | 290 | ;;---------------------------------------------------------------- |
289 | 291 | ||
@@ -302,7 +304,7 @@ index a93ddd0..6976b37 100644 | |||
302 | (define_insn "subdi3" | 304 | (define_insn "subdi3" |
303 | [(set (match_operand:DI 0 "register_operand" "=&d") | 305 | [(set (match_operand:DI 0 "register_operand" "=&d") |
304 | (minus:DI (match_operand:DI 1 "register_operand" "d") | 306 | (minus:DI (match_operand:DI 1 "register_operand" "d") |
305 | @@ -793,6 +817,15 @@ | 307 | @@ -795,6 +819,15 @@ |
306 | (set_attr "mode" "SI") | 308 | (set_attr "mode" "SI") |
307 | (set_attr "length" "4")]) | 309 | (set_attr "length" "4")]) |
308 | 310 | ||
@@ -318,7 +320,7 @@ index a93ddd0..6976b37 100644 | |||
318 | (define_insn "negdi2" | 320 | (define_insn "negdi2" |
319 | [(set (match_operand:DI 0 "register_operand" "=d") | 321 | [(set (match_operand:DI 0 "register_operand" "=d") |
320 | (neg:DI (match_operand:DI 1 "register_operand" "d")))] | 322 | (neg:DI (match_operand:DI 1 "register_operand" "d")))] |
321 | @@ -812,6 +845,15 @@ | 323 | @@ -814,6 +847,15 @@ |
322 | (set_attr "mode" "SI") | 324 | (set_attr "mode" "SI") |
323 | (set_attr "length" "4")]) | 325 | (set_attr "length" "4")]) |
324 | 326 | ||
@@ -334,7 +336,7 @@ index a93ddd0..6976b37 100644 | |||
334 | (define_insn "*one_cmpldi2" | 336 | (define_insn "*one_cmpldi2" |
335 | [(set (match_operand:DI 0 "register_operand" "=d") | 337 | [(set (match_operand:DI 0 "register_operand" "=d") |
336 | (not:DI (match_operand:DI 1 "register_operand" "d")))] | 338 | (not:DI (match_operand:DI 1 "register_operand" "d")))] |
337 | @@ -838,6 +880,20 @@ | 339 | @@ -840,6 +882,20 @@ |
338 | ;; Logical | 340 | ;; Logical |
339 | ;;---------------------------------------------------------------- | 341 | ;;---------------------------------------------------------------- |
340 | 342 | ||
@@ -355,7 +357,7 @@ index a93ddd0..6976b37 100644 | |||
355 | (define_insn "andsi3" | 357 | (define_insn "andsi3" |
356 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | 358 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
357 | (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") | 359 | (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") |
358 | @@ -853,6 +909,18 @@ | 360 | @@ -855,6 +911,18 @@ |
359 | (set_attr "length" "4,8,8,8")]) | 361 | (set_attr "length" "4,8,8,8")]) |
360 | 362 | ||
361 | 363 | ||
@@ -374,7 +376,7 @@ index a93ddd0..6976b37 100644 | |||
374 | (define_insn "iorsi3" | 376 | (define_insn "iorsi3" |
375 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | 377 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
376 | (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") | 378 | (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") |
377 | @@ -867,6 +935,19 @@ | 379 | @@ -869,6 +937,19 @@ |
378 | (set_attr "mode" "SI,SI,SI,SI") | 380 | (set_attr "mode" "SI,SI,SI,SI") |
379 | (set_attr "length" "4,8,8,8")]) | 381 | (set_attr "length" "4,8,8,8")]) |
380 | 382 | ||
@@ -394,7 +396,7 @@ index a93ddd0..6976b37 100644 | |||
394 | (define_insn "xorsi3" | 396 | (define_insn "xorsi3" |
395 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | 397 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
396 | (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") | 398 | (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") |
397 | @@ -935,6 +1016,26 @@ | 399 | @@ -937,6 +1018,26 @@ |
398 | (set_attr "mode" "SI") | 400 | (set_attr "mode" "SI") |
399 | (set_attr "length" "4")]) | 401 | (set_attr "length" "4")]) |
400 | 402 | ||
@@ -421,7 +423,7 @@ index a93ddd0..6976b37 100644 | |||
421 | (define_insn "extendhisi2" | 423 | (define_insn "extendhisi2" |
422 | [(set (match_operand:SI 0 "register_operand" "=d") | 424 | [(set (match_operand:SI 0 "register_operand" "=d") |
423 | (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] | 425 | (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] |
424 | @@ -944,6 +1045,16 @@ | 426 | @@ -946,6 +1047,16 @@ |
425 | (set_attr "mode" "SI") | 427 | (set_attr "mode" "SI") |
426 | (set_attr "length" "4")]) | 428 | (set_attr "length" "4")]) |
427 | 429 | ||
@@ -438,7 +440,7 @@ index a93ddd0..6976b37 100644 | |||
438 | ;; Those for integer source operand are ordered | 440 | ;; Those for integer source operand are ordered |
439 | ;; widest source type first. | 441 | ;; widest source type first. |
440 | 442 | ||
441 | @@ -1009,7 +1120,6 @@ | 443 | @@ -1011,7 +1122,6 @@ |
442 | ) | 444 | ) |
443 | 445 | ||
444 | 446 | ||
@@ -446,7 +448,7 @@ index a93ddd0..6976b37 100644 | |||
446 | (define_insn "*movdi_internal" | 448 | (define_insn "*movdi_internal" |
447 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") | 449 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") |
448 | (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] | 450 | (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] |
449 | @@ -1421,6 +1531,36 @@ | 451 | @@ -1423,6 +1533,36 @@ |
450 | (set_attr "length" "4,4")] | 452 | (set_attr "length" "4,4")] |
451 | ) | 453 | ) |
452 | 454 | ||
@@ -483,7 +485,7 @@ index a93ddd0..6976b37 100644 | |||
483 | ;; The following patterns apply when there is no barrel shifter present | 485 | ;; The following patterns apply when there is no barrel shifter present |
484 | 486 | ||
485 | (define_insn "*ashlsi3_with_mul_delay" | 487 | (define_insn "*ashlsi3_with_mul_delay" |
486 | @@ -1546,6 +1686,36 @@ | 488 | @@ -1548,6 +1688,36 @@ |
487 | ;;---------------------------------------------------------------- | 489 | ;;---------------------------------------------------------------- |
488 | ;; 32-bit right shifts | 490 | ;; 32-bit right shifts |
489 | ;;---------------------------------------------------------------- | 491 | ;;---------------------------------------------------------------- |
@@ -520,7 +522,7 @@ index a93ddd0..6976b37 100644 | |||
520 | (define_expand "ashrsi3" | 522 | (define_expand "ashrsi3" |
521 | [(set (match_operand:SI 0 "register_operand" "=&d") | 523 | [(set (match_operand:SI 0 "register_operand" "=&d") |
522 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | 524 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") |
523 | @@ -1655,6 +1825,36 @@ | 525 | @@ -1657,6 +1827,36 @@ |
524 | ;;---------------------------------------------------------------- | 526 | ;;---------------------------------------------------------------- |
525 | ;; 32-bit right shifts (logical) | 527 | ;; 32-bit right shifts (logical) |
526 | ;;---------------------------------------------------------------- | 528 | ;;---------------------------------------------------------------- |
@@ -557,7 +559,7 @@ index a93ddd0..6976b37 100644 | |||
557 | 559 | ||
558 | (define_expand "lshrsi3" | 560 | (define_expand "lshrsi3" |
559 | [(set (match_operand:SI 0 "register_operand" "=&d") | 561 | [(set (match_operand:SI 0 "register_operand" "=&d") |
560 | @@ -1801,6 +2001,8 @@ | 562 | @@ -1803,6 +2003,8 @@ |
561 | (set_attr "length" "4")] | 563 | (set_attr "length" "4")] |
562 | ) | 564 | ) |
563 | 565 | ||
@@ -566,7 +568,7 @@ index a93ddd0..6976b37 100644 | |||
566 | ;;---------------------------------------------------------------- | 568 | ;;---------------------------------------------------------------- |
567 | ;; Setting a register from an floating point comparison. | 569 | ;; Setting a register from an floating point comparison. |
568 | ;;---------------------------------------------------------------- | 570 | ;;---------------------------------------------------------------- |
569 | @@ -1816,6 +2018,18 @@ | 571 | @@ -1818,6 +2020,18 @@ |
570 | (set_attr "length" "4")] | 572 | (set_attr "length" "4")] |
571 | ) | 573 | ) |
572 | 574 | ||
@@ -585,7 +587,7 @@ index a93ddd0..6976b37 100644 | |||
585 | ;;---------------------------------------------------------------- | 587 | ;;---------------------------------------------------------------- |
586 | ;; Conditional branches | 588 | ;; Conditional branches |
587 | ;;---------------------------------------------------------------- | 589 | ;;---------------------------------------------------------------- |
588 | @@ -1928,6 +2142,115 @@ | 590 | @@ -1930,6 +2144,115 @@ |
589 | (set_attr "length" "12")] | 591 | (set_attr "length" "12")] |
590 | ) | 592 | ) |
591 | 593 | ||
@@ -701,7 +703,7 @@ index a93ddd0..6976b37 100644 | |||
701 | ;;---------------------------------------------------------------- | 703 | ;;---------------------------------------------------------------- |
702 | ;; Unconditional branches | 704 | ;; Unconditional branches |
703 | ;;---------------------------------------------------------------- | 705 | ;;---------------------------------------------------------------- |
704 | @@ -2462,17 +2785,33 @@ | 706 | @@ -2478,17 +2801,33 @@ |
705 | DONE; | 707 | DONE; |
706 | }") | 708 | }") |
707 | 709 | ||
@@ -740,7 +742,7 @@ index a93ddd0..6976b37 100644 | |||
740 | [(set (match_operand:SI 0 "register_operand" "=r") | 742 | [(set (match_operand:SI 0 "register_operand" "=r") |
741 | (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | 743 | (zero_extract:SI (match_operand:SI 1 "register_operand" "r") |
742 | (match_operand:SI 2 "immediate_operand" "I") | 744 | (match_operand:SI 2 "immediate_operand" "I") |
743 | @@ -2489,8 +2828,21 @@ | 745 | @@ -2505,8 +2844,21 @@ |
744 | (match_operand:SI 2 "immediate_operand" "I")) | 746 | (match_operand:SI 2 "immediate_operand" "I")) |
745 | (match_operand:SI 3 "register_operand" "r"))] | 747 | (match_operand:SI 3 "register_operand" "r"))] |
746 | "TARGET_HAS_BITFIELD" | 748 | "TARGET_HAS_BITFIELD" |
@@ -765,18 +767,10 @@ index a93ddd0..6976b37 100644 | |||
765 | (define_insn "insv_32" | 767 | (define_insn "insv_32" |
766 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") | 768 | [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") |
767 | diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt | 769 | diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt |
768 | index c8e6f00..cdcae00 100644 | 770 | index d23f376..f316e27 100644 |
769 | --- a/gcc/config/microblaze/microblaze.opt | 771 | --- a/gcc/config/microblaze/microblaze.opt |
770 | +++ b/gcc/config/microblaze/microblaze.opt | 772 | +++ b/gcc/config/microblaze/microblaze.opt |
771 | @@ -125,11 +125,16 @@ Description for mxl-mode-novectors. | 773 | @@ -136,4 +136,9 @@ Target |
772 | |||
773 | mxl-prefetch | ||
774 | Target Mask(PREFETCH) | ||
775 | -Use hardware prefetch instruction | ||
776 | +Use hardware prefetch instruction. | ||
777 | |||
778 | mxl-mode-xilkernel | ||
779 | Target | ||
780 | 774 | ||
781 | mxl-frequency | 775 | mxl-frequency |
782 | Target Mask(AREA_OPTIMIZED_2) | 776 | Target Mask(AREA_OPTIMIZED_2) |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch index 1157a82f..a973f4cd 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 5526d87787d61990be3187b230fae4d0591d0651 Mon Sep 17 00:00:00 2001 | 1 | From 95615e1bfae642dc4f5f1b03e1ffaea4f16aa99c Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Wed, 4 Apr 2018 16:41:41 +0530 | 3 | Date: Wed, 4 Apr 2018 16:41:41 +0530 |
4 | Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing | 4 | Subject: [PATCH 40/63] Added load store pattern movdi and also adding missing |
5 | files | 5 | files |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -11,7 +11,7 @@ Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing | |||
11 | 3 files changed, 33 insertions(+), 2 deletions(-) | 11 | 3 files changed, 33 insertions(+), 2 deletions(-) |
12 | 12 | ||
13 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md | 13 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md |
14 | index ae14944..a06b4d8 100644 | 14 | index 5e1d79a..69bcb24 100644 |
15 | --- a/gcc/config/microblaze/constraints.md | 15 | --- a/gcc/config/microblaze/constraints.md |
16 | +++ b/gcc/config/microblaze/constraints.md | 16 | +++ b/gcc/config/microblaze/constraints.md |
17 | @@ -52,6 +52,11 @@ | 17 | @@ -52,6 +52,11 @@ |
@@ -27,10 +27,10 @@ index ae14944..a06b4d8 100644 | |||
27 | 27 | ||
28 | (define_constraint "G" | 28 | (define_constraint "G" |
29 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 29 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
30 | index 6976b37..0cd0441 100644 | 30 | index dbb592e..eb52957 100644 |
31 | --- a/gcc/config/microblaze/microblaze.md | 31 | --- a/gcc/config/microblaze/microblaze.md |
32 | +++ b/gcc/config/microblaze/microblaze.md | 32 | +++ b/gcc/config/microblaze/microblaze.md |
33 | @@ -1120,6 +1120,32 @@ | 33 | @@ -1122,6 +1122,32 @@ |
34 | ) | 34 | ) |
35 | 35 | ||
36 | 36 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch index 411958e7..b022eb77 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From eee9b7f7423823b133d6a5e5382863502433bdc6 Mon Sep 17 00:00:00 2001 | 1 | From 7c68b1c9771f09f7cc53410248e8432c562d24bf Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Fri, 27 Jul 2018 15:23:41 +0530 | 3 | Date: Fri, 27 Jul 2018 15:23:41 +0530 |
4 | Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the | 4 | Subject: [PATCH 41/63] Intial commit for 64bit-MB sources. Need to cleanup the |
5 | code later. | 5 | code later. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -29,7 +29,7 @@ Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the | |||
29 | create mode 100644 libgcc/config/microblaze/umoddi3.S | 29 | create mode 100644 libgcc/config/microblaze/umoddi3.S |
30 | 30 | ||
31 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md | 31 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md |
32 | index a06b4d8..867a7b5 100644 | 32 | index 69bcb24..2fce91e 100644 |
33 | --- a/gcc/config/microblaze/constraints.md | 33 | --- a/gcc/config/microblaze/constraints.md |
34 | +++ b/gcc/config/microblaze/constraints.md | 34 | +++ b/gcc/config/microblaze/constraints.md |
35 | @@ -55,7 +55,7 @@ | 35 | @@ -55,7 +55,7 @@ |
@@ -42,7 +42,7 @@ index a06b4d8..867a7b5 100644 | |||
42 | ;; Define floating point constraints | 42 | ;; Define floating point constraints |
43 | 43 | ||
44 | diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c | 44 | diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c |
45 | index 7b020b5..d8a1d13 100644 | 45 | index cd21319..d2b0c76 100644 |
46 | --- a/gcc/config/microblaze/microblaze-c.c | 46 | --- a/gcc/config/microblaze/microblaze-c.c |
47 | +++ b/gcc/config/microblaze/microblaze-c.c | 47 | +++ b/gcc/config/microblaze/microblaze-c.c |
48 | @@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) | 48 | @@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) |
@@ -57,10 +57,10 @@ index 7b020b5..d8a1d13 100644 | |||
57 | + } | 57 | + } |
58 | } | 58 | } |
59 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 59 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
60 | index 2079ae9..ba7ade4 100644 | 60 | index f740f5c..d5ff7af 100644 |
61 | --- a/gcc/config/microblaze/microblaze.c | 61 | --- a/gcc/config/microblaze/microblaze.c |
62 | +++ b/gcc/config/microblaze/microblaze.c | 62 | +++ b/gcc/config/microblaze/microblaze.c |
63 | @@ -382,10 +382,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) | 63 | @@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) |
64 | { | 64 | { |
65 | return 1; | 65 | return 1; |
66 | } | 66 | } |
@@ -73,7 +73,7 @@ index 2079ae9..ba7ade4 100644 | |||
73 | else | 73 | else |
74 | return 0; | 74 | return 0; |
75 | 75 | ||
76 | @@ -433,7 +433,7 @@ double_memory_operand (rtx op, machine_mode mode) | 76 | @@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode) |
77 | return 1; | 77 | return 1; |
78 | 78 | ||
79 | return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT | 79 | return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT |
@@ -82,7 +82,7 @@ index 2079ae9..ba7ade4 100644 | |||
82 | plus_constant (Pmode, addr, 4)); | 82 | plus_constant (Pmode, addr, 4)); |
83 | } | 83 | } |
84 | 84 | ||
85 | @@ -680,7 +680,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) | 85 | @@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) |
86 | /* Load the addend. */ | 86 | /* Load the addend. */ |
87 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), | 87 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), |
88 | UNSPEC_TLS); | 88 | UNSPEC_TLS); |
@@ -91,7 +91,7 @@ index 2079ae9..ba7ade4 100644 | |||
91 | dest = gen_rtx_PLUS (Pmode, dest, addend); | 91 | dest = gen_rtx_PLUS (Pmode, dest, addend); |
92 | break; | 92 | break; |
93 | 93 | ||
94 | @@ -698,7 +698,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) | 94 | @@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) |
95 | 95 | ||
96 | if (XINT (x, 1) == UNSPEC_GOTOFF) | 96 | if (XINT (x, 1) == UNSPEC_GOTOFF) |
97 | { | 97 | { |
@@ -100,7 +100,7 @@ index 2079ae9..ba7ade4 100644 | |||
100 | info->type = ADDRESS_GOTOFF; | 100 | info->type = ADDRESS_GOTOFF; |
101 | } | 101 | } |
102 | else if (XINT (x, 1) == UNSPEC_PLT) | 102 | else if (XINT (x, 1) == UNSPEC_PLT) |
103 | @@ -1230,8 +1230,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) | 103 | @@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) |
104 | emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); | 104 | emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); |
105 | 105 | ||
106 | /* Emit the test & branch. */ | 106 | /* Emit the test & branch. */ |
@@ -118,7 +118,7 @@ index 2079ae9..ba7ade4 100644 | |||
118 | 118 | ||
119 | /* Mop up any left-over bytes. */ | 119 | /* Mop up any left-over bytes. */ |
120 | if (leftover) | 120 | if (leftover) |
121 | @@ -1561,14 +1569,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, | 121 | @@ -1634,14 +1642,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, |
122 | break; | 122 | break; |
123 | 123 | ||
124 | case E_DFmode: | 124 | case E_DFmode: |
@@ -141,7 +141,7 @@ index 2079ae9..ba7ade4 100644 | |||
141 | break; | 141 | break; |
142 | 142 | ||
143 | case E_QImode: | 143 | case E_QImode: |
144 | @@ -2219,7 +2233,7 @@ compute_frame_size (HOST_WIDE_INT size) | 144 | @@ -2295,7 +2309,7 @@ compute_frame_size (HOST_WIDE_INT size) |
145 | 145 | ||
146 | if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) | 146 | if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) |
147 | /* Don't account for link register. It is accounted specially below. */ | 147 | /* Don't account for link register. It is accounted specially below. */ |
@@ -150,7 +150,7 @@ index 2079ae9..ba7ade4 100644 | |||
150 | 150 | ||
151 | mask |= (1L << (regno - GP_REG_FIRST)); | 151 | mask |= (1L << (regno - GP_REG_FIRST)); |
152 | } | 152 | } |
153 | @@ -2487,7 +2501,7 @@ print_operand (FILE * file, rtx op, int letter) | 153 | @@ -2564,7 +2578,7 @@ print_operand (FILE * file, rtx op, int letter) |
154 | 154 | ||
155 | if ((letter == 'M' && !WORDS_BIG_ENDIAN) | 155 | if ((letter == 'M' && !WORDS_BIG_ENDIAN) |
156 | || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') | 156 | || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') |
@@ -159,7 +159,7 @@ index 2079ae9..ba7ade4 100644 | |||
159 | 159 | ||
160 | fprintf (file, "%s", reg_names[regnum]); | 160 | fprintf (file, "%s", reg_names[regnum]); |
161 | } | 161 | } |
162 | @@ -2513,6 +2527,7 @@ print_operand (FILE * file, rtx op, int letter) | 162 | @@ -2590,6 +2604,7 @@ print_operand (FILE * file, rtx op, int letter) |
163 | else if (letter == 'h' || letter == 'j') | 163 | else if (letter == 'h' || letter == 'j') |
164 | { | 164 | { |
165 | long val[2]; | 165 | long val[2]; |
@@ -167,7 +167,7 @@ index 2079ae9..ba7ade4 100644 | |||
167 | long l[2]; | 167 | long l[2]; |
168 | if (code == CONST_DOUBLE) | 168 | if (code == CONST_DOUBLE) |
169 | { | 169 | { |
170 | @@ -2525,12 +2540,12 @@ print_operand (FILE * file, rtx op, int letter) | 170 | @@ -2602,12 +2617,12 @@ print_operand (FILE * file, rtx op, int letter) |
171 | val[0] = l[WORDS_BIG_ENDIAN != 0]; | 171 | val[0] = l[WORDS_BIG_ENDIAN != 0]; |
172 | } | 172 | } |
173 | } | 173 | } |
@@ -184,7 +184,7 @@ index 2079ae9..ba7ade4 100644 | |||
184 | } | 184 | } |
185 | else if (code == CONST_DOUBLE) | 185 | else if (code == CONST_DOUBLE) |
186 | { | 186 | { |
187 | @@ -2713,7 +2728,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) | 187 | @@ -2801,7 +2816,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) |
188 | 188 | ||
189 | switch_to_section (get_section (section, 0, NULL)); | 189 | switch_to_section (get_section (section, 0, NULL)); |
190 | assemble_align (POINTER_SIZE); | 190 | assemble_align (POINTER_SIZE); |
@@ -196,7 +196,7 @@ index 2079ae9..ba7ade4 100644 | |||
196 | output_addr_const (asm_out_file, symbol); | 196 | output_addr_const (asm_out_file, symbol); |
197 | fputs ("\n", asm_out_file); | 197 | fputs ("\n", asm_out_file); |
198 | } | 198 | } |
199 | @@ -2736,7 +2754,10 @@ microblaze_asm_destructor (rtx symbol, int priority) | 199 | @@ -2824,7 +2842,10 @@ microblaze_asm_destructor (rtx symbol, int priority) |
200 | 200 | ||
201 | switch_to_section (get_section (section, 0, NULL)); | 201 | switch_to_section (get_section (section, 0, NULL)); |
202 | assemble_align (POINTER_SIZE); | 202 | assemble_align (POINTER_SIZE); |
@@ -208,7 +208,7 @@ index 2079ae9..ba7ade4 100644 | |||
208 | output_addr_const (asm_out_file, symbol); | 208 | output_addr_const (asm_out_file, symbol); |
209 | fputs ("\n", asm_out_file); | 209 | fputs ("\n", asm_out_file); |
210 | } | 210 | } |
211 | @@ -2802,7 +2823,7 @@ save_restore_insns (int prologue) | 211 | @@ -2890,7 +2911,7 @@ save_restore_insns (int prologue) |
212 | /* For interrupt_handlers, need to save/restore the MSR. */ | 212 | /* For interrupt_handlers, need to save/restore the MSR. */ |
213 | if (microblaze_is_interrupt_variant ()) | 213 | if (microblaze_is_interrupt_variant ()) |
214 | { | 214 | { |
@@ -217,7 +217,7 @@ index 2079ae9..ba7ade4 100644 | |||
217 | gen_rtx_PLUS (Pmode, base_reg_rtx, | 217 | gen_rtx_PLUS (Pmode, base_reg_rtx, |
218 | GEN_INT (current_frame_info. | 218 | GEN_INT (current_frame_info. |
219 | gp_offset - | 219 | gp_offset - |
220 | @@ -2810,8 +2831,8 @@ save_restore_insns (int prologue) | 220 | @@ -2898,8 +2919,8 @@ save_restore_insns (int prologue) |
221 | 221 | ||
222 | /* Do not optimize in flow analysis. */ | 222 | /* Do not optimize in flow analysis. */ |
223 | MEM_VOLATILE_P (isr_mem_rtx) = 1; | 223 | MEM_VOLATILE_P (isr_mem_rtx) = 1; |
@@ -228,7 +228,7 @@ index 2079ae9..ba7ade4 100644 | |||
228 | } | 228 | } |
229 | 229 | ||
230 | if (microblaze_is_interrupt_variant () && !prologue) | 230 | if (microblaze_is_interrupt_variant () && !prologue) |
231 | @@ -2819,8 +2840,8 @@ save_restore_insns (int prologue) | 231 | @@ -2907,8 +2928,8 @@ save_restore_insns (int prologue) |
232 | emit_move_insn (isr_reg_rtx, isr_mem_rtx); | 232 | emit_move_insn (isr_reg_rtx, isr_mem_rtx); |
233 | emit_move_insn (isr_msr_rtx, isr_reg_rtx); | 233 | emit_move_insn (isr_msr_rtx, isr_reg_rtx); |
234 | /* Do not optimize in flow analysis. */ | 234 | /* Do not optimize in flow analysis. */ |
@@ -239,7 +239,7 @@ index 2079ae9..ba7ade4 100644 | |||
239 | } | 239 | } |
240 | 240 | ||
241 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) | 241 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
242 | @@ -2831,9 +2852,9 @@ save_restore_insns (int prologue) | 242 | @@ -2919,9 +2940,9 @@ save_restore_insns (int prologue) |
243 | /* Don't handle here. Already handled as the first register. */ | 243 | /* Don't handle here. Already handled as the first register. */ |
244 | continue; | 244 | continue; |
245 | 245 | ||
@@ -251,7 +251,7 @@ index 2079ae9..ba7ade4 100644 | |||
251 | if (microblaze_is_interrupt_variant () || save_volatiles) | 251 | if (microblaze_is_interrupt_variant () || save_volatiles) |
252 | /* Do not optimize in flow analysis. */ | 252 | /* Do not optimize in flow analysis. */ |
253 | MEM_VOLATILE_P (mem_rtx) = 1; | 253 | MEM_VOLATILE_P (mem_rtx) = 1; |
254 | @@ -2848,7 +2869,7 @@ save_restore_insns (int prologue) | 254 | @@ -2936,7 +2957,7 @@ save_restore_insns (int prologue) |
255 | insn = emit_move_insn (reg_rtx, mem_rtx); | 255 | insn = emit_move_insn (reg_rtx, mem_rtx); |
256 | } | 256 | } |
257 | 257 | ||
@@ -260,7 +260,7 @@ index 2079ae9..ba7ade4 100644 | |||
260 | } | 260 | } |
261 | } | 261 | } |
262 | 262 | ||
263 | @@ -2858,8 +2879,8 @@ save_restore_insns (int prologue) | 263 | @@ -2946,8 +2967,8 @@ save_restore_insns (int prologue) |
264 | emit_move_insn (isr_mem_rtx, isr_reg_rtx); | 264 | emit_move_insn (isr_mem_rtx, isr_reg_rtx); |
265 | 265 | ||
266 | /* Do not optimize in flow analysis. */ | 266 | /* Do not optimize in flow analysis. */ |
@@ -271,7 +271,7 @@ index 2079ae9..ba7ade4 100644 | |||
271 | } | 271 | } |
272 | 272 | ||
273 | /* Done saving and restoring */ | 273 | /* Done saving and restoring */ |
274 | @@ -2949,7 +2970,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) | 274 | @@ -3037,7 +3058,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
275 | 275 | ||
276 | switch_to_section (s); | 276 | switch_to_section (s); |
277 | assemble_align (POINTER_SIZE); | 277 | assemble_align (POINTER_SIZE); |
@@ -283,7 +283,7 @@ index 2079ae9..ba7ade4 100644 | |||
283 | output_addr_const (asm_out_file, symbol); | 283 | output_addr_const (asm_out_file, symbol); |
284 | fputs ("\n", asm_out_file); | 284 | fputs ("\n", asm_out_file); |
285 | } | 285 | } |
286 | @@ -3095,10 +3119,10 @@ microblaze_expand_prologue (void) | 286 | @@ -3182,10 +3206,10 @@ microblaze_expand_prologue (void) |
287 | { | 287 | { |
288 | if (offset != 0) | 288 | if (offset != 0) |
289 | ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); | 289 | ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); |
@@ -295,9 +295,9 @@ index 2079ae9..ba7ade4 100644 | |||
295 | - offset += GET_MODE_SIZE (SImode); | 295 | - offset += GET_MODE_SIZE (SImode); |
296 | + offset += GET_MODE_SIZE (Pmode); | 296 | + offset += GET_MODE_SIZE (Pmode); |
297 | } | 297 | } |
298 | |||
299 | } | 298 | } |
300 | @@ -3108,15 +3132,23 @@ microblaze_expand_prologue (void) | 299 | |
300 | @@ -3194,15 +3218,23 @@ microblaze_expand_prologue (void) | ||
301 | rtx fsiz_rtx = GEN_INT (fsiz); | 301 | rtx fsiz_rtx = GEN_INT (fsiz); |
302 | 302 | ||
303 | rtx_insn *insn = NULL; | 303 | rtx_insn *insn = NULL; |
@@ -323,7 +323,7 @@ index 2079ae9..ba7ade4 100644 | |||
323 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | 323 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
324 | const0_rtx)); | 324 | const0_rtx)); |
325 | 325 | ||
326 | @@ -3124,7 +3156,7 @@ microblaze_expand_prologue (void) | 326 | @@ -3210,7 +3242,7 @@ microblaze_expand_prologue (void) |
327 | /* Do not optimize in flow analysis. */ | 327 | /* Do not optimize in flow analysis. */ |
328 | MEM_VOLATILE_P (mem_rtx) = 1; | 328 | MEM_VOLATILE_P (mem_rtx) = 1; |
329 | 329 | ||
@@ -332,7 +332,7 @@ index 2079ae9..ba7ade4 100644 | |||
332 | insn = emit_move_insn (mem_rtx, reg_rtx); | 332 | insn = emit_move_insn (mem_rtx, reg_rtx); |
333 | RTX_FRAME_RELATED_P (insn) = 1; | 333 | RTX_FRAME_RELATED_P (insn) = 1; |
334 | } | 334 | } |
335 | @@ -3224,12 +3256,12 @@ microblaze_expand_epilogue (void) | 335 | @@ -3320,12 +3352,12 @@ microblaze_expand_epilogue (void) |
336 | if (!crtl->is_leaf || interrupt_handler) | 336 | if (!crtl->is_leaf || interrupt_handler) |
337 | { | 337 | { |
338 | mem_rtx = | 338 | mem_rtx = |
@@ -347,7 +347,7 @@ index 2079ae9..ba7ade4 100644 | |||
347 | emit_move_insn (reg_rtx, mem_rtx); | 347 | emit_move_insn (reg_rtx, mem_rtx); |
348 | } | 348 | } |
349 | 349 | ||
350 | @@ -3245,15 +3277,25 @@ microblaze_expand_epilogue (void) | 350 | @@ -3341,15 +3373,25 @@ microblaze_expand_epilogue (void) |
351 | /* _restore_ registers for epilogue. */ | 351 | /* _restore_ registers for epilogue. */ |
352 | save_restore_insns (0); | 352 | save_restore_insns (0); |
353 | emit_insn (gen_blockage ()); | 353 | emit_insn (gen_blockage ()); |
@@ -377,7 +377,7 @@ index 2079ae9..ba7ade4 100644 | |||
377 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + | 377 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + |
378 | MB_ABI_SUB_RETURN_ADDR_REGNUM))); | 378 | MB_ABI_SUB_RETURN_ADDR_REGNUM))); |
379 | } | 379 | } |
380 | @@ -3402,9 +3444,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | 380 | @@ -3515,9 +3557,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
381 | else | 381 | else |
382 | this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); | 382 | this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); |
383 | 383 | ||
@@ -394,7 +394,7 @@ index 2079ae9..ba7ade4 100644 | |||
394 | 394 | ||
395 | /* Apply the offset from the vtable, if required. */ | 395 | /* Apply the offset from the vtable, if required. */ |
396 | if (vcall_offset) | 396 | if (vcall_offset) |
397 | @@ -3417,7 +3464,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | 397 | @@ -3530,7 +3577,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
398 | rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); | 398 | rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); |
399 | emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); | 399 | emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); |
400 | 400 | ||
@@ -406,7 +406,7 @@ index 2079ae9..ba7ade4 100644 | |||
406 | } | 406 | } |
407 | 407 | ||
408 | /* Generate a tail call to the target function. */ | 408 | /* Generate a tail call to the target function. */ |
409 | @@ -3564,7 +3614,7 @@ microblaze_eh_return (rtx op0) | 409 | @@ -3704,7 +3754,7 @@ microblaze_eh_return (rtx op0) |
410 | /* Queue an .ident string in the queue of top-level asm statements. | 410 | /* Queue an .ident string in the queue of top-level asm statements. |
411 | If the string size is below the threshold, put it into .sdata2. | 411 | If the string size is below the threshold, put it into .sdata2. |
412 | If the front-end is done, we must be being called from toplev.c. | 412 | If the front-end is done, we must be being called from toplev.c. |
@@ -415,7 +415,7 @@ index 2079ae9..ba7ade4 100644 | |||
415 | void | 415 | void |
416 | microblaze_asm_output_ident (const char *string) | 416 | microblaze_asm_output_ident (const char *string) |
417 | { | 417 | { |
418 | @@ -3619,9 +3669,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | 418 | @@ -3759,9 +3809,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) |
419 | emit_block_move (m_tramp, assemble_trampoline_template (), | 419 | emit_block_move (m_tramp, assemble_trampoline_template (), |
420 | GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); | 420 | GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); |
421 | 421 | ||
@@ -427,7 +427,7 @@ index 2079ae9..ba7ade4 100644 | |||
427 | emit_move_insn (mem, fnaddr); | 427 | emit_move_insn (mem, fnaddr); |
428 | } | 428 | } |
429 | 429 | ||
430 | @@ -3645,7 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) | 430 | @@ -3785,7 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) |
431 | { | 431 | { |
432 | comp_reg = cmp_op0; | 432 | comp_reg = cmp_op0; |
433 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); | 433 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); |
@@ -436,7 +436,7 @@ index 2079ae9..ba7ade4 100644 | |||
436 | emit_jump_insn (gen_condjump (condition, label1)); | 436 | emit_jump_insn (gen_condjump (condition, label1)); |
437 | else | 437 | else |
438 | emit_jump_insn (gen_long_condjump (condition, label1)); | 438 | emit_jump_insn (gen_long_condjump (condition, label1)); |
439 | @@ -3764,7 +3814,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) | 439 | @@ -3904,7 +3954,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) |
440 | rtx comp_reg = gen_reg_rtx (SImode); | 440 | rtx comp_reg = gen_reg_rtx (SImode); |
441 | 441 | ||
442 | emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); | 442 | emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); |
@@ -445,7 +445,7 @@ index 2079ae9..ba7ade4 100644 | |||
445 | emit_jump_insn (gen_condjump (condition, operands[3])); | 445 | emit_jump_insn (gen_condjump (condition, operands[3])); |
446 | } | 446 | } |
447 | 447 | ||
448 | @@ -3774,10 +3824,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) | 448 | @@ -3914,10 +3964,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) |
449 | rtx condition; | 449 | rtx condition; |
450 | rtx cmp_op0 = XEXP (operands[0], 0); | 450 | rtx cmp_op0 = XEXP (operands[0], 0); |
451 | rtx cmp_op1 = XEXP (operands[0], 1); | 451 | rtx cmp_op1 = XEXP (operands[0], 1); |
@@ -458,7 +458,7 @@ index 2079ae9..ba7ade4 100644 | |||
458 | emit_jump_insn (gen_long_condjump (condition, operands[3])); | 458 | emit_jump_insn (gen_long_condjump (condition, operands[3])); |
459 | } | 459 | } |
460 | 460 | ||
461 | @@ -3798,8 +3848,8 @@ microblaze_expand_divide (rtx operands[]) | 461 | @@ -3938,8 +3988,8 @@ microblaze_expand_divide (rtx operands[]) |
462 | { | 462 | { |
463 | /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ | 463 | /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ |
464 | 464 | ||
@@ -469,7 +469,7 @@ index 2079ae9..ba7ade4 100644 | |||
469 | rtx regqi = gen_reg_rtx (QImode); | 469 | rtx regqi = gen_reg_rtx (QImode); |
470 | rtx_code_label *div_label = gen_label_rtx (); | 470 | rtx_code_label *div_label = gen_label_rtx (); |
471 | rtx_code_label *div_end_label = gen_label_rtx (); | 471 | rtx_code_label *div_end_label = gen_label_rtx (); |
472 | @@ -3807,17 +3857,31 @@ microblaze_expand_divide (rtx operands[]) | 472 | @@ -3947,17 +3997,31 @@ microblaze_expand_divide (rtx operands[]) |
473 | rtx mem_rtx; | 473 | rtx mem_rtx; |
474 | rtx ret; | 474 | rtx ret; |
475 | rtx_insn *jump, *cjump, *insn; | 475 | rtx_insn *jump, *cjump, *insn; |
@@ -508,7 +508,7 @@ index 2079ae9..ba7ade4 100644 | |||
508 | mem_rtx = gen_rtx_MEM (QImode, | 508 | mem_rtx = gen_rtx_MEM (QImode, |
509 | gen_rtx_PLUS (QImode, regt1, div_table_rtx)); | 509 | gen_rtx_PLUS (QImode, regt1, div_table_rtx)); |
510 | 510 | ||
511 | @@ -3964,7 +4028,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) | 511 | @@ -4104,7 +4168,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) |
512 | { | 512 | { |
513 | insn = | 513 | insn = |
514 | emit_insn_before (gen_iprefetch | 514 | emit_insn_before (gen_iprefetch |
@@ -517,7 +517,7 @@ index 2079ae9..ba7ade4 100644 | |||
517 | before_4); | 517 | before_4); |
518 | recog_memoized (insn); | 518 | recog_memoized (insn); |
519 | INSN_LOCATION (insn) = INSN_LOCATION (before_4); | 519 | INSN_LOCATION (insn) = INSN_LOCATION (before_4); |
520 | @@ -3974,7 +4038,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) | 520 | @@ -4114,7 +4178,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) |
521 | } | 521 | } |
522 | } | 522 | } |
523 | } | 523 | } |
@@ -546,7 +546,7 @@ index 2079ae9..ba7ade4 100644 | |||
546 | /* Insert instruction prefetch instruction at the fall | 546 | /* Insert instruction prefetch instruction at the fall |
547 | through path of the function call. */ | 547 | through path of the function call. */ |
548 | 548 | ||
549 | @@ -4127,6 +4211,17 @@ microblaze_starting_frame_offset (void) | 549 | @@ -4267,6 +4351,17 @@ microblaze_starting_frame_offset (void) |
550 | #undef TARGET_LRA_P | 550 | #undef TARGET_LRA_P |
551 | #define TARGET_LRA_P hook_bool_void_false | 551 | #define TARGET_LRA_P hook_bool_void_false |
552 | 552 | ||
@@ -564,7 +564,7 @@ index 2079ae9..ba7ade4 100644 | |||
564 | #undef TARGET_FRAME_POINTER_REQUIRED | 564 | #undef TARGET_FRAME_POINTER_REQUIRED |
565 | #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required | 565 | #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required |
566 | 566 | ||
567 | @@ -4136,6 +4231,9 @@ microblaze_starting_frame_offset (void) | 567 | @@ -4276,6 +4371,9 @@ microblaze_starting_frame_offset (void) |
568 | #undef TARGET_TRAMPOLINE_INIT | 568 | #undef TARGET_TRAMPOLINE_INIT |
569 | #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init | 569 | #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init |
570 | 570 | ||
@@ -575,7 +575,7 @@ index 2079ae9..ba7ade4 100644 | |||
575 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | 575 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote |
576 | 576 | ||
577 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 577 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
578 | index 72fbee5..1e60513 100644 | 578 | index 2ca44f5..a23fd4e 100644 |
579 | --- a/gcc/config/microblaze/microblaze.h | 579 | --- a/gcc/config/microblaze/microblaze.h |
580 | +++ b/gcc/config/microblaze/microblaze.h | 580 | +++ b/gcc/config/microblaze/microblaze.h |
581 | @@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; | 581 | @@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; |
@@ -710,7 +710,7 @@ index 72fbee5..1e60513 100644 | |||
710 | 710 | ||
711 | #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) | 711 | #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) |
712 | 712 | ||
713 | @@ -533,13 +551,13 @@ typedef struct microblaze_args | 713 | @@ -529,13 +547,13 @@ typedef struct microblaze_args |
714 | addresses which require two reload registers. */ | 714 | addresses which require two reload registers. */ |
715 | #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) | 715 | #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) |
716 | 716 | ||
@@ -726,7 +726,7 @@ index 72fbee5..1e60513 100644 | |||
726 | #define MAX_MOVE_MAX 8 | 726 | #define MAX_MOVE_MAX 8 |
727 | 727 | ||
728 | #define SLOW_BYTE_ACCESS 1 | 728 | #define SLOW_BYTE_ACCESS 1 |
729 | @@ -549,7 +567,7 @@ typedef struct microblaze_args | 729 | @@ -545,7 +563,7 @@ typedef struct microblaze_args |
730 | 730 | ||
731 | #define SHIFT_COUNT_TRUNCATED 1 | 731 | #define SHIFT_COUNT_TRUNCATED 1 |
732 | 732 | ||
@@ -735,7 +735,7 @@ index 72fbee5..1e60513 100644 | |||
735 | 735 | ||
736 | #define FUNCTION_MODE SImode | 736 | #define FUNCTION_MODE SImode |
737 | 737 | ||
738 | @@ -711,6 +729,7 @@ do { \ | 738 | @@ -707,6 +725,7 @@ do { \ |
739 | 739 | ||
740 | #undef TARGET_ASM_OUTPUT_IDENT | 740 | #undef TARGET_ASM_OUTPUT_IDENT |
741 | #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident | 741 | #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident |
@@ -744,7 +744,7 @@ index 72fbee5..1e60513 100644 | |||
744 | /* Default to -G 8 */ | 744 | /* Default to -G 8 */ |
745 | #ifndef MICROBLAZE_DEFAULT_GVALUE | 745 | #ifndef MICROBLAZE_DEFAULT_GVALUE |
746 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 746 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
747 | index 0cd0441..0f41ac6 100644 | 747 | index eb52957..77627a7 100644 |
748 | --- a/gcc/config/microblaze/microblaze.md | 748 | --- a/gcc/config/microblaze/microblaze.md |
749 | +++ b/gcc/config/microblaze/microblaze.md | 749 | +++ b/gcc/config/microblaze/microblaze.md |
750 | @@ -26,6 +26,7 @@ | 750 | @@ -26,6 +26,7 @@ |
@@ -755,7 +755,7 @@ index 0cd0441..0f41ac6 100644 | |||
755 | (R_SP 1) ;; Stack pointer reg | 755 | (R_SP 1) ;; Stack pointer reg |
756 | (R_SR 15) ;; Sub-routine return addr reg | 756 | (R_SR 15) ;; Sub-routine return addr reg |
757 | (R_IR 14) ;; Interrupt return addr reg | 757 | (R_IR 14) ;; Interrupt return addr reg |
758 | @@ -539,6 +540,7 @@ | 758 | @@ -541,6 +542,7 @@ |
759 | 759 | ||
760 | ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] | 760 | ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] |
761 | ;; Leave carry as is | 761 | ;; Leave carry as is |
@@ -763,7 +763,7 @@ index 0cd0441..0f41ac6 100644 | |||
763 | (define_insn "addsi3" | 763 | (define_insn "addsi3" |
764 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | 764 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
765 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") | 765 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") |
766 | @@ -560,23 +562,38 @@ | 766 | @@ -562,23 +564,38 @@ |
767 | 767 | ||
768 | ;; Adding 2 DI operands in register or reg/imm | 768 | ;; Adding 2 DI operands in register or reg/imm |
769 | 769 | ||
@@ -810,7 +810,7 @@ index 0cd0441..0f41ac6 100644 | |||
810 | "@ | 810 | "@ |
811 | add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 | 811 | add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 |
812 | addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" | 812 | addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" |
813 | @@ -603,7 +620,7 @@ | 813 | @@ -605,7 +622,7 @@ |
814 | (define_insn "iprefetch" | 814 | (define_insn "iprefetch" |
815 | [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) | 815 | [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) |
816 | (clobber (mem:BLK (scratch)))] | 816 | (clobber (mem:BLK (scratch)))] |
@@ -819,7 +819,7 @@ index 0cd0441..0f41ac6 100644 | |||
819 | { | 819 | { |
820 | operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); | 820 | operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); |
821 | return "mfs\t%2,rpc\n\twic\t%2,r0"; | 821 | return "mfs\t%2,rpc\n\twic\t%2,r0"; |
822 | @@ -616,23 +633,33 @@ | 822 | @@ -618,23 +635,33 @@ |
823 | ;; Double Precision Subtraction | 823 | ;; Double Precision Subtraction |
824 | ;;---------------------------------------------------------------- | 824 | ;;---------------------------------------------------------------- |
825 | 825 | ||
@@ -863,7 +863,7 @@ index 0cd0441..0f41ac6 100644 | |||
863 | "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" | 863 | "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" |
864 | [(set_attr "type" "darith") | 864 | [(set_attr "type" "darith") |
865 | (set_attr "mode" "DI") | 865 | (set_attr "mode" "DI") |
866 | @@ -661,7 +688,7 @@ | 866 | @@ -663,7 +690,7 @@ |
867 | (mult:DI | 867 | (mult:DI |
868 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) | 868 | (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) |
869 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] | 869 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] |
@@ -872,7 +872,7 @@ index 0cd0441..0f41ac6 100644 | |||
872 | "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" | 872 | "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" |
873 | [(set_attr "type" "no_delay_arith") | 873 | [(set_attr "type" "no_delay_arith") |
874 | (set_attr "mode" "DI") | 874 | (set_attr "mode" "DI") |
875 | @@ -672,7 +699,7 @@ | 875 | @@ -674,7 +701,7 @@ |
876 | (mult:DI | 876 | (mult:DI |
877 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) | 877 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) |
878 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] | 878 | (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] |
@@ -881,7 +881,7 @@ index 0cd0441..0f41ac6 100644 | |||
881 | "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" | 881 | "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" |
882 | [(set_attr "type" "no_delay_arith") | 882 | [(set_attr "type" "no_delay_arith") |
883 | (set_attr "mode" "DI") | 883 | (set_attr "mode" "DI") |
884 | @@ -683,7 +710,7 @@ | 884 | @@ -685,7 +712,7 @@ |
885 | (mult:DI | 885 | (mult:DI |
886 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) | 886 | (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) |
887 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] | 887 | (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] |
@@ -890,7 +890,7 @@ index 0cd0441..0f41ac6 100644 | |||
890 | "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" | 890 | "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" |
891 | [(set_attr "type" "no_delay_arith") | 891 | [(set_attr "type" "no_delay_arith") |
892 | (set_attr "mode" "DI") | 892 | (set_attr "mode" "DI") |
893 | @@ -787,7 +814,7 @@ | 893 | @@ -789,7 +816,7 @@ |
894 | (match_operand:SI 4 "arith_operand")]) | 894 | (match_operand:SI 4 "arith_operand")]) |
895 | (label_ref (match_operand 5)) | 895 | (label_ref (match_operand 5)) |
896 | (pc)))] | 896 | (pc)))] |
@@ -899,7 +899,7 @@ index 0cd0441..0f41ac6 100644 | |||
899 | [(set (match_dup 1) (match_dup 3))] | 899 | [(set (match_dup 1) (match_dup 3))] |
900 | 900 | ||
901 | { | 901 | { |
902 | @@ -817,6 +844,15 @@ | 902 | @@ -819,6 +846,15 @@ |
903 | (set_attr "mode" "SI") | 903 | (set_attr "mode" "SI") |
904 | (set_attr "length" "4")]) | 904 | (set_attr "length" "4")]) |
905 | 905 | ||
@@ -915,7 +915,7 @@ index 0cd0441..0f41ac6 100644 | |||
915 | (define_insn "negdi2_long" | 915 | (define_insn "negdi2_long" |
916 | [(set (match_operand:DI 0 "register_operand" "=d") | 916 | [(set (match_operand:DI 0 "register_operand" "=d") |
917 | (neg:DI (match_operand:DI 1 "register_operand" "d")))] | 917 | (neg:DI (match_operand:DI 1 "register_operand" "d")))] |
918 | @@ -845,16 +881,24 @@ | 918 | @@ -847,16 +883,24 @@ |
919 | (set_attr "mode" "SI") | 919 | (set_attr "mode" "SI") |
920 | (set_attr "length" "4")]) | 920 | (set_attr "length" "4")]) |
921 | 921 | ||
@@ -944,7 +944,7 @@ index 0cd0441..0f41ac6 100644 | |||
944 | [(set (match_operand:DI 0 "register_operand" "=d") | 944 | [(set (match_operand:DI 0 "register_operand" "=d") |
945 | (not:DI (match_operand:DI 1 "register_operand" "d")))] | 945 | (not:DI (match_operand:DI 1 "register_operand" "d")))] |
946 | "" | 946 | "" |
947 | @@ -869,7 +913,8 @@ | 947 | @@ -871,7 +915,8 @@ |
948 | (not:DI (match_operand:DI 1 "register_operand" "")))] | 948 | (not:DI (match_operand:DI 1 "register_operand" "")))] |
949 | "reload_completed | 949 | "reload_completed |
950 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) | 950 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
@@ -954,7 +954,7 @@ index 0cd0441..0f41ac6 100644 | |||
954 | 954 | ||
955 | [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) | 955 | [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) |
956 | (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] | 956 | (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] |
957 | @@ -881,18 +926,17 @@ | 957 | @@ -883,18 +928,17 @@ |
958 | ;;---------------------------------------------------------------- | 958 | ;;---------------------------------------------------------------- |
959 | 959 | ||
960 | (define_insn "anddi3" | 960 | (define_insn "anddi3" |
@@ -981,7 +981,7 @@ index 0cd0441..0f41ac6 100644 | |||
981 | 981 | ||
982 | (define_insn "andsi3" | 982 | (define_insn "andsi3" |
983 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") | 983 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
984 | @@ -917,7 +961,7 @@ | 984 | @@ -919,7 +963,7 @@ |
985 | "@ | 985 | "@ |
986 | orl\t%0,%1,%2 | 986 | orl\t%0,%1,%2 |
987 | orli\t%0,%1,%2 #andl1" | 987 | orli\t%0,%1,%2 #andl1" |
@@ -990,7 +990,7 @@ index 0cd0441..0f41ac6 100644 | |||
990 | (set_attr "mode" "DI,DI") | 990 | (set_attr "mode" "DI,DI") |
991 | (set_attr "length" "4,4")]) | 991 | (set_attr "length" "4,4")]) |
992 | 992 | ||
993 | @@ -943,7 +987,7 @@ | 993 | @@ -945,7 +989,7 @@ |
994 | "@ | 994 | "@ |
995 | xorl\t%0,%1,%2 | 995 | xorl\t%0,%1,%2 |
996 | xorli\t%0,%1,%2 #andl1" | 996 | xorli\t%0,%1,%2 #andl1" |
@@ -999,7 +999,7 @@ index 0cd0441..0f41ac6 100644 | |||
999 | (set_attr "mode" "DI,DI") | 999 | (set_attr "mode" "DI,DI") |
1000 | (set_attr "length" "4,4")]) | 1000 | (set_attr "length" "4,4")]) |
1001 | 1001 | ||
1002 | @@ -1016,26 +1060,6 @@ | 1002 | @@ -1018,26 +1062,6 @@ |
1003 | (set_attr "mode" "SI") | 1003 | (set_attr "mode" "SI") |
1004 | (set_attr "length" "4")]) | 1004 | (set_attr "length" "4")]) |
1005 | 1005 | ||
@@ -1026,7 +1026,7 @@ index 0cd0441..0f41ac6 100644 | |||
1026 | (define_insn "extendhisi2" | 1026 | (define_insn "extendhisi2" |
1027 | [(set (match_operand:SI 0 "register_operand" "=d") | 1027 | [(set (match_operand:SI 0 "register_operand" "=d") |
1028 | (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] | 1028 | (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] |
1029 | @@ -1058,6 +1082,27 @@ | 1029 | @@ -1060,6 +1084,27 @@ |
1030 | ;; Those for integer source operand are ordered | 1030 | ;; Those for integer source operand are ordered |
1031 | ;; widest source type first. | 1031 | ;; widest source type first. |
1032 | 1032 | ||
@@ -1054,7 +1054,7 @@ index 0cd0441..0f41ac6 100644 | |||
1054 | (define_insn "extendsidi2" | 1054 | (define_insn "extendsidi2" |
1055 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | 1055 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
1056 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] | 1056 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] |
1057 | @@ -1088,68 +1133,117 @@ | 1057 | @@ -1090,68 +1135,117 @@ |
1058 | ;; Unlike most other insns, the move insns can't be split with | 1058 | ;; Unlike most other insns, the move insns can't be split with |
1059 | ;; different predicates, because register spilling and other parts of | 1059 | ;; different predicates, because register spilling and other parts of |
1060 | ;; the compiler, have memoized the insn number already. | 1060 | ;; the compiler, have memoized the insn number already. |
@@ -1208,7 +1208,7 @@ index 0cd0441..0f41ac6 100644 | |||
1208 | { | 1208 | { |
1209 | switch (which_alternative) | 1209 | switch (which_alternative) |
1210 | { | 1210 | { |
1211 | @@ -1181,7 +1275,8 @@ | 1211 | @@ -1183,7 +1277,8 @@ |
1212 | "reload_completed | 1212 | "reload_completed |
1213 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) | 1213 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
1214 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | 1214 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) |
@@ -1218,7 +1218,7 @@ index 0cd0441..0f41ac6 100644 | |||
1218 | 1218 | ||
1219 | [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) | 1219 | [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) |
1220 | (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] | 1220 | (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] |
1221 | @@ -1193,12 +1288,22 @@ | 1221 | @@ -1195,12 +1290,22 @@ |
1222 | "reload_completed | 1222 | "reload_completed |
1223 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) | 1223 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
1224 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | 1224 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) |
@@ -1242,7 +1242,7 @@ index 0cd0441..0f41ac6 100644 | |||
1242 | ;; Unlike most other insns, the move insns can't be split with | 1242 | ;; Unlike most other insns, the move insns can't be split with |
1243 | ;; different predicates, because register spilling and other parts of | 1243 | ;; different predicates, because register spilling and other parts of |
1244 | ;; the compiler, have memoized the insn number already. | 1244 | ;; the compiler, have memoized the insn number already. |
1245 | @@ -1270,6 +1375,8 @@ | 1245 | @@ -1272,6 +1377,8 @@ |
1246 | (set_attr "length" "4,4,8,4,8,4,8")]) | 1246 | (set_attr "length" "4,4,8,4,8,4,8")]) |
1247 | 1247 | ||
1248 | 1248 | ||
@@ -1251,7 +1251,7 @@ index 0cd0441..0f41ac6 100644 | |||
1251 | ;; 16-bit Integer moves | 1251 | ;; 16-bit Integer moves |
1252 | 1252 | ||
1253 | ;; Unlike most other insns, the move insns can't be split with | 1253 | ;; Unlike most other insns, the move insns can't be split with |
1254 | @@ -1302,8 +1409,8 @@ | 1254 | @@ -1304,8 +1411,8 @@ |
1255 | "@ | 1255 | "@ |
1256 | addik\t%0,r0,%1\t# %X1 | 1256 | addik\t%0,r0,%1\t# %X1 |
1257 | addk\t%0,%1,r0 | 1257 | addk\t%0,%1,r0 |
@@ -1262,7 +1262,7 @@ index 0cd0441..0f41ac6 100644 | |||
1262 | sh%i0\t%z1,%0 | 1262 | sh%i0\t%z1,%0 |
1263 | sh%i0\t%z1,%0" | 1263 | sh%i0\t%z1,%0" |
1264 | [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") | 1264 | [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") |
1265 | @@ -1346,7 +1453,7 @@ | 1265 | @@ -1348,7 +1455,7 @@ |
1266 | lbu%i1\t%0,%1 | 1266 | lbu%i1\t%0,%1 |
1267 | lbu%i1\t%0,%1 | 1267 | lbu%i1\t%0,%1 |
1268 | sb%i0\t%z1,%0 | 1268 | sb%i0\t%z1,%0 |
@@ -1271,7 +1271,7 @@ index 0cd0441..0f41ac6 100644 | |||
1271 | [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") | 1271 | [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") |
1272 | (set_attr "mode" "QI") | 1272 | (set_attr "mode" "QI") |
1273 | (set_attr "length" "4,4,8,4,8,4,8")]) | 1273 | (set_attr "length" "4,4,8,4,8,4,8")]) |
1274 | @@ -1419,7 +1526,7 @@ | 1274 | @@ -1421,7 +1528,7 @@ |
1275 | addik\t%0,r0,%F1 | 1275 | addik\t%0,r0,%F1 |
1276 | lw%i1\t%0,%1 | 1276 | lw%i1\t%0,%1 |
1277 | sw%i0\t%z1,%0 | 1277 | sw%i0\t%z1,%0 |
@@ -1280,7 +1280,7 @@ index 0cd0441..0f41ac6 100644 | |||
1280 | [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") | 1280 | [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") |
1281 | (set_attr "mode" "SF") | 1281 | (set_attr "mode" "SF") |
1282 | (set_attr "length" "4,4,4,4,4,4,4")]) | 1282 | (set_attr "length" "4,4,4,4,4,4,4")]) |
1283 | @@ -1458,6 +1565,33 @@ | 1283 | @@ -1460,6 +1567,33 @@ |
1284 | ;; movdf_internal | 1284 | ;; movdf_internal |
1285 | ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT | 1285 | ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT |
1286 | ;; | 1286 | ;; |
@@ -1314,7 +1314,7 @@ index 0cd0441..0f41ac6 100644 | |||
1314 | (define_insn "*movdf_internal" | 1314 | (define_insn "*movdf_internal" |
1315 | [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") | 1315 | [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") |
1316 | (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] | 1316 | (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] |
1317 | @@ -1492,7 +1626,8 @@ | 1317 | @@ -1494,7 +1628,8 @@ |
1318 | "reload_completed | 1318 | "reload_completed |
1319 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) | 1319 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
1320 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | 1320 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) |
@@ -1324,7 +1324,7 @@ index 0cd0441..0f41ac6 100644 | |||
1324 | [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) | 1324 | [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) |
1325 | (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] | 1325 | (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] |
1326 | "") | 1326 | "") |
1327 | @@ -1503,7 +1638,8 @@ | 1327 | @@ -1505,7 +1640,8 @@ |
1328 | "reload_completed | 1328 | "reload_completed |
1329 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) | 1329 | && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) |
1330 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) | 1330 | && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) |
@@ -1334,7 +1334,7 @@ index 0cd0441..0f41ac6 100644 | |||
1334 | [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) | 1334 | [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) |
1335 | (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] | 1335 | (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] |
1336 | "") | 1336 | "") |
1337 | @@ -2003,6 +2139,31 @@ else | 1337 | @@ -2005,6 +2141,31 @@ else |
1338 | " | 1338 | " |
1339 | ) | 1339 | ) |
1340 | 1340 | ||
@@ -1366,7 +1366,7 @@ index 0cd0441..0f41ac6 100644 | |||
1366 | (define_insn "seq_internal_pat" | 1366 | (define_insn "seq_internal_pat" |
1367 | [(set (match_operand:SI 0 "register_operand" "=d") | 1367 | [(set (match_operand:SI 0 "register_operand" "=d") |
1368 | (eq:SI | 1368 | (eq:SI |
1369 | @@ -2063,8 +2224,8 @@ else | 1369 | @@ -2065,8 +2226,8 @@ else |
1370 | (define_expand "cbranchsi4" | 1370 | (define_expand "cbranchsi4" |
1371 | [(set (pc) | 1371 | [(set (pc) |
1372 | (if_then_else (match_operator 0 "ordered_comparison_operator" | 1372 | (if_then_else (match_operator 0 "ordered_comparison_operator" |
@@ -1377,7 +1377,7 @@ index 0cd0441..0f41ac6 100644 | |||
1377 | (label_ref (match_operand 3 "")) | 1377 | (label_ref (match_operand 3 "")) |
1378 | (pc)))] | 1378 | (pc)))] |
1379 | "" | 1379 | "" |
1380 | @@ -2076,13 +2237,13 @@ else | 1380 | @@ -2078,13 +2239,13 @@ else |
1381 | (define_expand "cbranchsi4_reg" | 1381 | (define_expand "cbranchsi4_reg" |
1382 | [(set (pc) | 1382 | [(set (pc) |
1383 | (if_then_else (match_operator 0 "ordered_comparison_operator" | 1383 | (if_then_else (match_operator 0 "ordered_comparison_operator" |
@@ -1394,7 +1394,7 @@ index 0cd0441..0f41ac6 100644 | |||
1394 | DONE; | 1394 | DONE; |
1395 | }) | 1395 | }) |
1396 | 1396 | ||
1397 | @@ -2107,6 +2268,26 @@ else | 1397 | @@ -2109,6 +2270,26 @@ else |
1398 | (label_ref (match_operand 1)) | 1398 | (label_ref (match_operand 1)) |
1399 | (pc)))]) | 1399 | (pc)))]) |
1400 | 1400 | ||
@@ -1421,7 +1421,7 @@ index 0cd0441..0f41ac6 100644 | |||
1421 | (define_insn "branch_zero" | 1421 | (define_insn "branch_zero" |
1422 | [(set (pc) | 1422 | [(set (pc) |
1423 | (if_then_else (match_operator:SI 0 "ordered_comparison_operator" | 1423 | (if_then_else (match_operator:SI 0 "ordered_comparison_operator" |
1424 | @@ -2127,6 +2308,47 @@ else | 1424 | @@ -2129,6 +2310,47 @@ else |
1425 | (set_attr "length" "4")] | 1425 | (set_attr "length" "4")] |
1426 | ) | 1426 | ) |
1427 | 1427 | ||
@@ -1469,7 +1469,7 @@ index 0cd0441..0f41ac6 100644 | |||
1469 | (define_insn "branch_compare" | 1469 | (define_insn "branch_compare" |
1470 | [(set (pc) | 1470 | [(set (pc) |
1471 | (if_then_else (match_operator:SI 0 "cmp_op" | 1471 | (if_then_else (match_operator:SI 0 "cmp_op" |
1472 | @@ -2310,7 +2532,7 @@ else | 1472 | @@ -2312,7 +2534,7 @@ else |
1473 | ;; Indirect jumps. Jump to register values. Assuming absolute jumps | 1473 | ;; Indirect jumps. Jump to register values. Assuming absolute jumps |
1474 | 1474 | ||
1475 | (define_insn "indirect_jump_internal1" | 1475 | (define_insn "indirect_jump_internal1" |
@@ -1478,16 +1478,16 @@ index 0cd0441..0f41ac6 100644 | |||
1478 | "" | 1478 | "" |
1479 | "bra%?\t%0" | 1479 | "bra%?\t%0" |
1480 | [(set_attr "type" "jump") | 1480 | [(set_attr "type" "jump") |
1481 | @@ -2323,7 +2545,7 @@ else | 1481 | @@ -2325,7 +2547,7 @@ else |
1482 | (use (label_ref (match_operand 1 "" "")))] | 1482 | (use (label_ref (match_operand 1 "" "")))] |
1483 | "" | 1483 | "" |
1484 | { | 1484 | { |
1485 | - gcc_assert (GET_MODE (operands[0]) == Pmode); | 1485 | - gcc_assert (GET_MODE (operands[0]) == Pmode); |
1486 | + //gcc_assert (GET_MODE (operands[0]) == Pmode); | 1486 | + //gcc_assert (GET_MODE (operands[0]) == Pmode); |
1487 | 1487 | ||
1488 | if (!flag_pic) | 1488 | if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) |
1489 | emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | 1489 | emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); |
1490 | @@ -2335,7 +2557,7 @@ else | 1490 | @@ -2337,7 +2559,7 @@ else |
1491 | 1491 | ||
1492 | (define_insn "tablejump_internal1" | 1492 | (define_insn "tablejump_internal1" |
1493 | [(set (pc) | 1493 | [(set (pc) |
@@ -1496,7 +1496,7 @@ index 0cd0441..0f41ac6 100644 | |||
1496 | (use (label_ref (match_operand 1 "" "")))] | 1496 | (use (label_ref (match_operand 1 "" "")))] |
1497 | "" | 1497 | "" |
1498 | "bra%?\t%0 " | 1498 | "bra%?\t%0 " |
1499 | @@ -2345,9 +2567,9 @@ else | 1499 | @@ -2347,9 +2569,9 @@ else |
1500 | 1500 | ||
1501 | (define_expand "tablejump_internal3" | 1501 | (define_expand "tablejump_internal3" |
1502 | [(parallel [(set (pc) | 1502 | [(parallel [(set (pc) |
@@ -1509,7 +1509,7 @@ index 0cd0441..0f41ac6 100644 | |||
1509 | "" | 1509 | "" |
1510 | "" | 1510 | "" |
1511 | ) | 1511 | ) |
1512 | @@ -2408,7 +2630,7 @@ else | 1512 | @@ -2410,7 +2632,7 @@ else |
1513 | (minus (reg 1) (match_operand 1 "register_operand" ""))) | 1513 | (minus (reg 1) (match_operand 1 "register_operand" ""))) |
1514 | (set (reg 1) | 1514 | (set (reg 1) |
1515 | (minus (reg 1) (match_dup 1)))] | 1515 | (minus (reg 1) (match_dup 1)))] |
@@ -1518,7 +1518,7 @@ index 0cd0441..0f41ac6 100644 | |||
1518 | { | 1518 | { |
1519 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); | 1519 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
1520 | rtx reg = gen_reg_rtx (Pmode); | 1520 | rtx reg = gen_reg_rtx (Pmode); |
1521 | @@ -2433,7 +2655,7 @@ else | 1521 | @@ -2435,7 +2657,7 @@ else |
1522 | (define_expand "save_stack_block" | 1522 | (define_expand "save_stack_block" |
1523 | [(match_operand 0 "register_operand" "") | 1523 | [(match_operand 0 "register_operand" "") |
1524 | (match_operand 1 "register_operand" "")] | 1524 | (match_operand 1 "register_operand" "")] |
@@ -1527,7 +1527,7 @@ index 0cd0441..0f41ac6 100644 | |||
1527 | { | 1527 | { |
1528 | emit_move_insn (operands[0], operands[1]); | 1528 | emit_move_insn (operands[0], operands[1]); |
1529 | DONE; | 1529 | DONE; |
1530 | @@ -2443,7 +2665,7 @@ else | 1530 | @@ -2445,7 +2667,7 @@ else |
1531 | (define_expand "restore_stack_block" | 1531 | (define_expand "restore_stack_block" |
1532 | [(match_operand 0 "register_operand" "") | 1532 | [(match_operand 0 "register_operand" "") |
1533 | (match_operand 1 "register_operand" "")] | 1533 | (match_operand 1 "register_operand" "")] |
@@ -1536,7 +1536,7 @@ index 0cd0441..0f41ac6 100644 | |||
1536 | { | 1536 | { |
1537 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); | 1537 | rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
1538 | rtx rtmp = gen_rtx_REG (SImode, R_TMP); | 1538 | rtx rtmp = gen_rtx_REG (SImode, R_TMP); |
1539 | @@ -2490,7 +2712,7 @@ else | 1539 | @@ -2492,7 +2714,7 @@ else |
1540 | 1540 | ||
1541 | (define_insn "<optab>_internal" | 1541 | (define_insn "<optab>_internal" |
1542 | [(any_return) | 1542 | [(any_return) |
@@ -1545,7 +1545,7 @@ index 0cd0441..0f41ac6 100644 | |||
1545 | "" | 1545 | "" |
1546 | { | 1546 | { |
1547 | if (microblaze_is_break_handler ()) | 1547 | if (microblaze_is_break_handler ()) |
1548 | @@ -2523,7 +2745,7 @@ else | 1548 | @@ -2525,7 +2747,7 @@ else |
1549 | (define_expand "call" | 1549 | (define_expand "call" |
1550 | [(parallel [(call (match_operand 0 "memory_operand" "m") | 1550 | [(parallel [(call (match_operand 0 "memory_operand" "m") |
1551 | (match_operand 1 "" "i")) | 1551 | (match_operand 1 "" "i")) |
@@ -1554,7 +1554,7 @@ index 0cd0441..0f41ac6 100644 | |||
1554 | (use (match_operand 2 "" "")) | 1554 | (use (match_operand 2 "" "")) |
1555 | (use (match_operand 3 "" ""))])] | 1555 | (use (match_operand 3 "" ""))])] |
1556 | "" | 1556 | "" |
1557 | @@ -2543,12 +2765,12 @@ else | 1557 | @@ -2546,12 +2768,12 @@ else |
1558 | 1558 | ||
1559 | if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) | 1559 | if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) |
1560 | emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], | 1560 | emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], |
@@ -1569,7 +1569,7 @@ index 0cd0441..0f41ac6 100644 | |||
1569 | GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); | 1569 | GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); |
1570 | 1570 | ||
1571 | DONE; | 1571 | DONE; |
1572 | @@ -2558,7 +2780,7 @@ else | 1572 | @@ -2561,7 +2783,7 @@ else |
1573 | (define_expand "call_internal0" | 1573 | (define_expand "call_internal0" |
1574 | [(parallel [(call (match_operand 0 "" "") | 1574 | [(parallel [(call (match_operand 0 "" "") |
1575 | (match_operand 1 "" "")) | 1575 | (match_operand 1 "" "")) |
@@ -1578,7 +1578,7 @@ index 0cd0441..0f41ac6 100644 | |||
1578 | "" | 1578 | "" |
1579 | { | 1579 | { |
1580 | } | 1580 | } |
1581 | @@ -2567,18 +2789,34 @@ else | 1581 | @@ -2570,18 +2792,34 @@ else |
1582 | (define_expand "call_internal_plt0" | 1582 | (define_expand "call_internal_plt0" |
1583 | [(parallel [(call (match_operand 0 "" "") | 1583 | [(parallel [(call (match_operand 0 "" "") |
1584 | (match_operand 1 "" "")) | 1584 | (match_operand 1 "" "")) |
@@ -1619,7 +1619,7 @@ index 0cd0441..0f41ac6 100644 | |||
1619 | "flag_pic" | 1619 | "flag_pic" |
1620 | { | 1620 | { |
1621 | register rtx target2 = gen_rtx_REG (Pmode, | 1621 | register rtx target2 = gen_rtx_REG (Pmode, |
1622 | @@ -2590,10 +2828,41 @@ else | 1622 | @@ -2593,10 +2831,41 @@ else |
1623 | (set_attr "mode" "none") | 1623 | (set_attr "mode" "none") |
1624 | (set_attr "length" "4")]) | 1624 | (set_attr "length" "4")]) |
1625 | 1625 | ||
@@ -1663,7 +1663,7 @@ index 0cd0441..0f41ac6 100644 | |||
1663 | "" | 1663 | "" |
1664 | { | 1664 | { |
1665 | register rtx target = operands[0]; | 1665 | register rtx target = operands[0]; |
1666 | @@ -2627,7 +2896,7 @@ else | 1666 | @@ -2630,7 +2899,7 @@ else |
1667 | [(parallel [(set (match_operand 0 "register_operand" "=d") | 1667 | [(parallel [(set (match_operand 0 "register_operand" "=d") |
1668 | (call (match_operand 1 "memory_operand" "m") | 1668 | (call (match_operand 1 "memory_operand" "m") |
1669 | (match_operand 2 "" "i"))) | 1669 | (match_operand 2 "" "i"))) |
@@ -1672,7 +1672,7 @@ index 0cd0441..0f41ac6 100644 | |||
1672 | (use (match_operand 3 "" ""))])] ;; next_arg_reg | 1672 | (use (match_operand 3 "" ""))])] ;; next_arg_reg |
1673 | "" | 1673 | "" |
1674 | { | 1674 | { |
1675 | @@ -2647,13 +2916,13 @@ else | 1675 | @@ -2651,13 +2920,13 @@ else |
1676 | if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) | 1676 | if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) |
1677 | emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], | 1677 | emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], |
1678 | operands[2], | 1678 | operands[2], |
@@ -1688,7 +1688,7 @@ index 0cd0441..0f41ac6 100644 | |||
1688 | GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); | 1688 | GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); |
1689 | 1689 | ||
1690 | DONE; | 1690 | DONE; |
1691 | @@ -2665,7 +2934,7 @@ else | 1691 | @@ -2669,7 +2938,7 @@ else |
1692 | [(parallel [(set (match_operand 0 "" "") | 1692 | [(parallel [(set (match_operand 0 "" "") |
1693 | (call (match_operand 1 "" "") | 1693 | (call (match_operand 1 "" "") |
1694 | (match_operand 2 "" ""))) | 1694 | (match_operand 2 "" ""))) |
@@ -1697,7 +1697,7 @@ index 0cd0441..0f41ac6 100644 | |||
1697 | ])] | 1697 | ])] |
1698 | "" | 1698 | "" |
1699 | {} | 1699 | {} |
1700 | @@ -2675,18 +2944,35 @@ else | 1700 | @@ -2679,18 +2948,35 @@ else |
1701 | [(parallel[(set (match_operand 0 "" "") | 1701 | [(parallel[(set (match_operand 0 "" "") |
1702 | (call (match_operand 1 "" "") | 1702 | (call (match_operand 1 "" "") |
1703 | (match_operand 2 "" ""))) | 1703 | (match_operand 2 "" ""))) |
@@ -1739,7 +1739,7 @@ index 0cd0441..0f41ac6 100644 | |||
1739 | "flag_pic" | 1739 | "flag_pic" |
1740 | { | 1740 | { |
1741 | register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); | 1741 | register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); |
1742 | @@ -2698,11 +2984,46 @@ else | 1742 | @@ -2702,11 +2988,46 @@ else |
1743 | (set_attr "mode" "none") | 1743 | (set_attr "mode" "none") |
1744 | (set_attr "length" "4")]) | 1744 | (set_attr "length" "4")]) |
1745 | 1745 | ||
@@ -1788,7 +1788,7 @@ index 0cd0441..0f41ac6 100644 | |||
1788 | "" | 1788 | "" |
1789 | { | 1789 | { |
1790 | register rtx target = operands[1]; | 1790 | register rtx target = operands[1]; |
1791 | @@ -2864,7 +3185,6 @@ else | 1791 | @@ -2880,7 +3201,6 @@ else |
1792 | 1792 | ||
1793 | ;;if (!register_operand (operands[0], VOIDmode)) | 1793 | ;;if (!register_operand (operands[0], VOIDmode)) |
1794 | ;; FAIL; | 1794 | ;; FAIL; |
@@ -1816,7 +1816,7 @@ index 7671f63..9fc80b1 100644 | |||
1816 | # Extra files | 1816 | # Extra files |
1817 | microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ | 1817 | microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ |
1818 | diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S | 1818 | diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S |
1819 | index 2e15be4..3386520 100644 | 1819 | index ee380ee..1811327 100644 |
1820 | --- a/libgcc/config/microblaze/crti.S | 1820 | --- a/libgcc/config/microblaze/crti.S |
1821 | +++ b/libgcc/config/microblaze/crti.S | 1821 | +++ b/libgcc/config/microblaze/crti.S |
1822 | @@ -40,7 +40,7 @@ | 1822 | @@ -40,7 +40,7 @@ |
@@ -1836,7 +1836,7 @@ index 2e15be4..3386520 100644 | |||
1836 | + addik r1, r1, -16 | 1836 | + addik r1, r1, -16 |
1837 | sw r15, r0, r1 | 1837 | sw r15, r0, r1 |
1838 | diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S | 1838 | diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S |
1839 | index cd5fd9e..04e73d7 100644 | 1839 | index 00d398a..60a4648 100644 |
1840 | --- a/libgcc/config/microblaze/crtn.S | 1840 | --- a/libgcc/config/microblaze/crtn.S |
1841 | +++ b/libgcc/config/microblaze/crtn.S | 1841 | +++ b/libgcc/config/microblaze/crtn.S |
1842 | @@ -33,9 +33,9 @@ | 1842 | @@ -33,9 +33,9 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0042-re-arrangement-of-the-compare-branches.patch index c33b247b..3afb7629 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0042-re-arrangement-of-the-compare-branches.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001 | 1 | From 31062878a2c1773a1fc94242ad29e6d03e4828b1 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Fri, 3 Aug 2018 15:41:39 +0530 | 3 | Date: Fri, 3 Aug 2018 15:41:39 +0530 |
4 | Subject: [PATCH 42/54] re-arrangement of the compare branches | 4 | Subject: [PATCH 42/63] re-arrangement of the compare branches |
5 | 5 | ||
6 | --- | 6 | --- |
7 | gcc/config/microblaze/microblaze.c | 28 ++----- | 7 | gcc/config/microblaze/microblaze.c | 28 ++----- |
@@ -9,10 +9,10 @@ Subject: [PATCH 42/54] re-arrangement of the compare branches | |||
9 | 2 files changed, 73 insertions(+), 96 deletions(-) | 9 | 2 files changed, 73 insertions(+), 96 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 11 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
12 | index ba7ade4..fab79d9 100644 | 12 | index d5ff7af..dd46d93 100644 |
13 | --- a/gcc/config/microblaze/microblaze.c | 13 | --- a/gcc/config/microblaze/microblaze.c |
14 | +++ b/gcc/config/microblaze/microblaze.c | 14 | +++ b/gcc/config/microblaze/microblaze.c |
15 | @@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) | 15 | @@ -3835,11 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) |
16 | { | 16 | { |
17 | comp_reg = cmp_op0; | 17 | comp_reg = cmp_op0; |
18 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); | 18 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); |
@@ -25,7 +25,7 @@ index ba7ade4..fab79d9 100644 | |||
25 | } | 25 | } |
26 | 26 | ||
27 | else if (code == EQ || code == NE) | 27 | else if (code == EQ || code == NE) |
28 | @@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) | 28 | @@ -3850,10 +3846,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) |
29 | else | 29 | else |
30 | emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); | 30 | emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); |
31 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); | 31 | condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); |
@@ -37,7 +37,7 @@ index ba7ade4..fab79d9 100644 | |||
37 | } | 37 | } |
38 | else | 38 | else |
39 | { | 39 | { |
40 | @@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) | 40 | @@ -3886,10 +3879,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) |
41 | comp_reg = cmp_op0; | 41 | comp_reg = cmp_op0; |
42 | condition = gen_rtx_fmt_ee (signed_condition (code), | 42 | condition = gen_rtx_fmt_ee (signed_condition (code), |
43 | mode, comp_reg, const0_rtx); | 43 | mode, comp_reg, const0_rtx); |
@@ -49,7 +49,7 @@ index ba7ade4..fab79d9 100644 | |||
49 | } | 49 | } |
50 | else if (code == EQ) | 50 | else if (code == EQ) |
51 | { | 51 | { |
52 | @@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) | 52 | @@ -3904,10 +3894,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) |
53 | cmp_op1)); | 53 | cmp_op1)); |
54 | } | 54 | } |
55 | condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); | 55 | condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); |
@@ -61,7 +61,7 @@ index ba7ade4..fab79d9 100644 | |||
61 | 61 | ||
62 | } | 62 | } |
63 | else if (code == NE) | 63 | else if (code == NE) |
64 | @@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) | 64 | @@ -3923,10 +3910,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) |
65 | cmp_op1)); | 65 | cmp_op1)); |
66 | } | 66 | } |
67 | condition = gen_rtx_NE (mode, comp_reg, const0_rtx); | 67 | condition = gen_rtx_NE (mode, comp_reg, const0_rtx); |
@@ -73,7 +73,7 @@ index ba7ade4..fab79d9 100644 | |||
73 | } | 73 | } |
74 | else | 74 | else |
75 | { | 75 | { |
76 | @@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) | 76 | @@ -3968,7 +3952,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) |
77 | 77 | ||
78 | emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); | 78 | emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); |
79 | condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); | 79 | condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); |
@@ -83,10 +83,10 @@ index ba7ade4..fab79d9 100644 | |||
83 | 83 | ||
84 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ | 84 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
85 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 85 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
86 | index 0f41ac6..2213d6e 100644 | 86 | index 77627a7..edb7aab 100644 |
87 | --- a/gcc/config/microblaze/microblaze.md | 87 | --- a/gcc/config/microblaze/microblaze.md |
88 | +++ b/gcc/config/microblaze/microblaze.md | 88 | +++ b/gcc/config/microblaze/microblaze.md |
89 | @@ -2268,7 +2268,27 @@ else | 89 | @@ -2270,7 +2270,27 @@ else |
90 | (label_ref (match_operand 1)) | 90 | (label_ref (match_operand 1)) |
91 | (pc)))]) | 91 | (pc)))]) |
92 | 92 | ||
@@ -115,7 +115,7 @@ index 0f41ac6..2213d6e 100644 | |||
115 | [(set (pc) | 115 | [(set (pc) |
116 | (if_then_else (match_operator 0 "ordered_comparison_operator" | 116 | (if_then_else (match_operator 0 "ordered_comparison_operator" |
117 | [(match_operand 1 "register_operand" "d") | 117 | [(match_operand 1 "register_operand" "d") |
118 | @@ -2279,9 +2299,9 @@ else | 118 | @@ -2281,9 +2301,9 @@ else |
119 | "TARGET_MB_64" | 119 | "TARGET_MB_64" |
120 | { | 120 | { |
121 | if (operands[3] == pc_rtx) | 121 | if (operands[3] == pc_rtx) |
@@ -127,7 +127,7 @@ index 0f41ac6..2213d6e 100644 | |||
127 | } | 127 | } |
128 | [(set_attr "type" "branch") | 128 | [(set_attr "type" "branch") |
129 | (set_attr "mode" "none") | 129 | (set_attr "mode" "none") |
130 | @@ -2310,9 +2330,9 @@ else | 130 | @@ -2312,9 +2332,9 @@ else |
131 | 131 | ||
132 | (define_insn "branch_compare64" | 132 | (define_insn "branch_compare64" |
133 | [(set (pc) | 133 | [(set (pc) |
@@ -140,7 +140,7 @@ index 0f41ac6..2213d6e 100644 | |||
140 | ]) | 140 | ]) |
141 | (label_ref (match_operand 3)) | 141 | (label_ref (match_operand 3)) |
142 | (pc))) | 142 | (pc))) |
143 | @@ -2349,6 +2369,47 @@ else | 143 | @@ -2351,6 +2371,47 @@ else |
144 | (set_attr "length" "12")] | 144 | (set_attr "length" "12")] |
145 | ) | 145 | ) |
146 | 146 | ||
@@ -188,7 +188,7 @@ index 0f41ac6..2213d6e 100644 | |||
188 | (define_insn "branch_compare" | 188 | (define_insn "branch_compare" |
189 | [(set (pc) | 189 | [(set (pc) |
190 | (if_then_else (match_operator:SI 0 "cmp_op" | 190 | (if_then_else (match_operator:SI 0 "cmp_op" |
191 | @@ -2431,74 +2492,6 @@ else | 191 | @@ -2433,74 +2494,6 @@ else |
192 | 192 | ||
193 | }) | 193 | }) |
194 | 194 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch index d1cf4579..f4074899 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 0c132e74714d217108d65fca630ab497a0d8821a Mon Sep 17 00:00:00 2001 | 1 | From 7ab47599c2bec80d622883b3e220827dce89c598 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 8 Aug 2018 17:37:26 +0530 | 3 | Date: Wed, 8 Aug 2018 17:37:26 +0530 |
4 | Subject: [PATCH 43/54] [Patch,Microblaze] : previous commit broke the | 4 | Subject: [PATCH 43/63] [Patch,Microblaze] : previous commit broke the |
5 | handling of SI Branch compare for Microblaze 32-bit.. | 5 | handling of SI Branch compare for Microblaze 32-bit.. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 43/54] [Patch,Microblaze] : previous commit broke the | |||
9 | 1 file changed, 2 insertions(+), 2 deletions(-) | 9 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
12 | index 2213d6e..53ea401 100644 | 12 | index edb7aab..fb22edb 100644 |
13 | --- a/gcc/config/microblaze/microblaze.md | 13 | --- a/gcc/config/microblaze/microblaze.md |
14 | +++ b/gcc/config/microblaze/microblaze.md | 14 | +++ b/gcc/config/microblaze/microblaze.md |
15 | @@ -2224,8 +2224,8 @@ else | 15 | @@ -2226,8 +2226,8 @@ else |
16 | (define_expand "cbranchsi4" | 16 | (define_expand "cbranchsi4" |
17 | [(set (pc) | 17 | [(set (pc) |
18 | (if_then_else (match_operator 0 "ordered_comparison_operator" | 18 | (if_then_else (match_operator 0 "ordered_comparison_operator" |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch index 68791cb2..ad287e57 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 259ed1ee33625964f5bc394ae660103b6c35510f Mon Sep 17 00:00:00 2001 | 1 | From 23622921a153258de469ff10db4926b83ff0c432 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Tue, 11 Sep 2018 13:43:48 +0530 | 3 | Date: Tue, 11 Sep 2018 13:43:48 +0530 |
4 | Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ... | 4 | Subject: [PATCH 44/63] [Patch, Microblaze] : Support of multilibs with m64 ... |
5 | 5 | ||
6 | --- | 6 | --- |
7 | gcc/config/microblaze/microblaze-c.c | 1 + | 7 | gcc/config/microblaze/microblaze-c.c | 1 + |
@@ -10,7 +10,7 @@ Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ... | |||
10 | 3 files changed, 10 insertions(+), 17 deletions(-) | 10 | 3 files changed, 10 insertions(+), 17 deletions(-) |
11 | 11 | ||
12 | diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c | 12 | diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c |
13 | index d8a1d13..6586575 100644 | 13 | index d2b0c76..6670091 100644 |
14 | --- a/gcc/config/microblaze/microblaze-c.c | 14 | --- a/gcc/config/microblaze/microblaze-c.c |
15 | +++ b/gcc/config/microblaze/microblaze-c.c | 15 | +++ b/gcc/config/microblaze/microblaze-c.c |
16 | @@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) | 16 | @@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) |
@@ -22,7 +22,7 @@ index d8a1d13..6586575 100644 | |||
22 | builtin_define ("__microblaze64__"); | 22 | builtin_define ("__microblaze64__"); |
23 | builtin_define ("__MICROBLAZE64__"); | 23 | builtin_define ("__MICROBLAZE64__"); |
24 | diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze | 24 | diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze |
25 | index 9fc80b1..35ab965 100644 | 25 | index 9fc80b1..35ab9654 100644 |
26 | --- a/gcc/config/microblaze/t-microblaze | 26 | --- a/gcc/config/microblaze/t-microblaze |
27 | +++ b/gcc/config/microblaze/t-microblaze | 27 | +++ b/gcc/config/microblaze/t-microblaze |
28 | @@ -1,12 +1,9 @@ | 28 | @@ -1,12 +1,9 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0045-Fixed-issues-like.patch index 8c0bde71..3f5f7827 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0045-Fixed-issues-like.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 654582846ebf847b52e769eb6e015c8e486461d6 Mon Sep 17 00:00:00 2001 | 1 | From 6e6fcbe5fafcbebaf63ff071ad947966af0c1559 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Tue, 11 Sep 2018 14:58:00 +0530 | 3 | Date: Tue, 11 Sep 2018 14:58:00 +0530 |
4 | Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign | 4 | Subject: [PATCH 45/63] Fixed issues like: 1 Interrupt alignment issue 2 Sign |
5 | extension issue | 5 | extension issue |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -10,10 +10,10 @@ Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign | |||
10 | 2 files changed, 11 insertions(+), 7 deletions(-) | 10 | 2 files changed, 11 insertions(+), 7 deletions(-) |
11 | 11 | ||
12 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 12 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
13 | index fab79d9..6b6ca61 100644 | 13 | index dd46d93..bfa667b 100644 |
14 | --- a/gcc/config/microblaze/microblaze.c | 14 | --- a/gcc/config/microblaze/microblaze.c |
15 | +++ b/gcc/config/microblaze/microblaze.c | 15 | +++ b/gcc/config/microblaze/microblaze.c |
16 | @@ -2241,9 +2241,14 @@ compute_frame_size (HOST_WIDE_INT size) | 16 | @@ -2317,9 +2317,14 @@ compute_frame_size (HOST_WIDE_INT size) |
17 | 17 | ||
18 | total_size += gp_reg_size; | 18 | total_size += gp_reg_size; |
19 | 19 | ||
@@ -30,7 +30,7 @@ index fab79d9..6b6ca61 100644 | |||
30 | 30 | ||
31 | /* No space to be allocated for link register in leaf functions with no other | 31 | /* No space to be allocated for link register in leaf functions with no other |
32 | stack requirements. */ | 32 | stack requirements. */ |
33 | @@ -2527,7 +2532,6 @@ print_operand (FILE * file, rtx op, int letter) | 33 | @@ -2604,7 +2609,6 @@ print_operand (FILE * file, rtx op, int letter) |
34 | else if (letter == 'h' || letter == 'j') | 34 | else if (letter == 'h' || letter == 'j') |
35 | { | 35 | { |
36 | long val[2]; | 36 | long val[2]; |
@@ -38,7 +38,7 @@ index fab79d9..6b6ca61 100644 | |||
38 | long l[2]; | 38 | long l[2]; |
39 | if (code == CONST_DOUBLE) | 39 | if (code == CONST_DOUBLE) |
40 | { | 40 | { |
41 | @@ -2542,10 +2546,10 @@ print_operand (FILE * file, rtx op, int letter) | 41 | @@ -2619,10 +2623,10 @@ print_operand (FILE * file, rtx op, int letter) |
42 | } | 42 | } |
43 | else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) | 43 | else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) |
44 | { | 44 | { |
@@ -53,10 +53,10 @@ index fab79d9..6b6ca61 100644 | |||
53 | else if (code == CONST_DOUBLE) | 53 | else if (code == CONST_DOUBLE) |
54 | { | 54 | { |
55 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 55 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
56 | index 53ea401..3a6943b 100644 | 56 | index fb22edb..4a8fbab 100644 |
57 | --- a/gcc/config/microblaze/microblaze.md | 57 | --- a/gcc/config/microblaze/microblaze.md |
58 | +++ b/gcc/config/microblaze/microblaze.md | 58 | +++ b/gcc/config/microblaze/microblaze.md |
59 | @@ -1094,7 +1094,7 @@ | 59 | @@ -1096,7 +1096,7 @@ |
60 | case 1: | 60 | case 1: |
61 | case 2: | 61 | case 2: |
62 | { | 62 | { |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0046-Fixed-below-issues.patch index 22bb5b2f..fc2fe3b5 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0046-Fixed-below-issues.patch | |||
@@ -1,22 +1,27 @@ | |||
1 | From 48f9f9a1c6809b14e7cfdd2343df92c0de18d730 Mon Sep 17 00:00:00 2001 | 1 | From 7c911a5ae8cf4a7496c059374f170f1919c00f6d Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Fri, 28 Sep 2018 11:59:12 +0530 | 3 | Date: Tue, 26 Nov 2019 17:26:15 +0530 |
4 | Subject: [PATCH 46/54] Fixed below issues: - Floating point print issues in | 4 | Subject: [PATCH 46/63] Fixed below issues: |
5 | 64bit mode - Dejagnu Jump related issues - Added dbl instruction | ||
6 | 5 | ||
6 | - Floating point print issues in 64bit mode | ||
7 | - Dejagnu Jump related issues | ||
8 | - Added dbl instruction | ||
9 | |||
10 | Conflicts: | ||
11 | gcc/config/microblaze/microblaze.md | ||
7 | --- | 12 | --- |
8 | gcc/config/microblaze/microblaze.c | 12 ++++- | 13 | gcc/config/microblaze/microblaze.c | 12 +++++- |
9 | gcc/config/microblaze/microblaze.h | 7 +++ | 14 | gcc/config/microblaze/microblaze.h | 7 +++ |
10 | gcc/config/microblaze/microblaze.md | 89 ++++++++++++++++++++++++++++++------- | 15 | gcc/config/microblaze/microblaze.md | 86 +++++++++++++++++++++++++++++++------ |
11 | libgcc/config/microblaze/crti.S | 24 +++++++++- | 16 | libgcc/config/microblaze/crti.S | 24 ++++++++++- |
12 | libgcc/config/microblaze/crtn.S | 13 ++++++ | 17 | libgcc/config/microblaze/crtn.S | 13 ++++++ |
13 | 5 files changed, 127 insertions(+), 18 deletions(-) | 18 | 5 files changed, 125 insertions(+), 17 deletions(-) |
14 | 19 | ||
15 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | 20 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c |
16 | index 6b6ca61..33d183e 100644 | 21 | index bfa667b..220e03d 100644 |
17 | --- a/gcc/config/microblaze/microblaze.c | 22 | --- a/gcc/config/microblaze/microblaze.c |
18 | +++ b/gcc/config/microblaze/microblaze.c | 23 | +++ b/gcc/config/microblaze/microblaze.c |
19 | @@ -2536,7 +2536,12 @@ print_operand (FILE * file, rtx op, int letter) | 24 | @@ -2613,7 +2613,12 @@ print_operand (FILE * file, rtx op, int letter) |
20 | if (code == CONST_DOUBLE) | 25 | if (code == CONST_DOUBLE) |
21 | { | 26 | { |
22 | if (GET_MODE (op) == DFmode) | 27 | if (GET_MODE (op) == DFmode) |
@@ -30,7 +35,7 @@ index 6b6ca61..33d183e 100644 | |||
30 | else | 35 | else |
31 | { | 36 | { |
32 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); | 37 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); |
33 | @@ -3874,7 +3879,10 @@ microblaze_expand_divide (rtx operands[]) | 38 | @@ -4014,7 +4019,10 @@ microblaze_expand_divide (rtx operands[]) |
34 | gen_rtx_PLUS (QImode, regt1, div_table_rtx)); | 39 | gen_rtx_PLUS (QImode, regt1, div_table_rtx)); |
35 | 40 | ||
36 | insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); | 41 | insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); |
@@ -43,10 +48,10 @@ index 6b6ca61..33d183e 100644 | |||
43 | LABEL_NUSES (div_end_label) = 1; | 48 | LABEL_NUSES (div_end_label) = 1; |
44 | emit_barrier (); | 49 | emit_barrier (); |
45 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 50 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
46 | index 1e60513..e34f549 100644 | 51 | index a23fd4e..7497cfb 100644 |
47 | --- a/gcc/config/microblaze/microblaze.h | 52 | --- a/gcc/config/microblaze/microblaze.h |
48 | +++ b/gcc/config/microblaze/microblaze.h | 53 | +++ b/gcc/config/microblaze/microblaze.h |
49 | @@ -892,10 +892,17 @@ do { \ | 54 | @@ -888,10 +888,17 @@ do { \ |
50 | /* We do this to save a few 10s of code space that would be taken up | 55 | /* We do this to save a few 10s of code space that would be taken up |
51 | by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION | 56 | by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION |
52 | definition in crtstuff.c. */ | 57 | definition in crtstuff.c. */ |
@@ -65,10 +70,10 @@ index 1e60513..e34f549 100644 | |||
65 | /* We need to group -lm as well, since some Newlib math functions | 70 | /* We need to group -lm as well, since some Newlib math functions |
66 | reference __errno! */ | 71 | reference __errno! */ |
67 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 72 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
68 | index 3a6943b..2669a28 100644 | 73 | index 4a8fbab..65ec32c 100644 |
69 | --- a/gcc/config/microblaze/microblaze.md | 74 | --- a/gcc/config/microblaze/microblaze.md |
70 | +++ b/gcc/config/microblaze/microblaze.md | 75 | +++ b/gcc/config/microblaze/microblaze.md |
71 | @@ -525,6 +525,15 @@ | 76 | @@ -527,6 +527,15 @@ |
72 | (set_attr "mode" "SF") | 77 | (set_attr "mode" "SF") |
73 | (set_attr "length" "4")]) | 78 | (set_attr "length" "4")]) |
74 | 79 | ||
@@ -84,7 +89,7 @@ index 3a6943b..2669a28 100644 | |||
84 | (define_insn "fix_truncsfsi2" | 89 | (define_insn "fix_truncsfsi2" |
85 | [(set (match_operand:SI 0 "register_operand" "=d") | 90 | [(set (match_operand:SI 0 "register_operand" "=d") |
86 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] | 91 | (fix:SI (match_operand:SF 1 "register_operand" "d")))] |
87 | @@ -1298,7 +1307,7 @@ | 92 | @@ -1300,7 +1309,7 @@ |
88 | (define_insn "movdi_long_int" | 93 | (define_insn "movdi_long_int" |
89 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | 94 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") |
90 | (match_operand:DI 1 "general_operand" "i"))] | 95 | (match_operand:DI 1 "general_operand" "i"))] |
@@ -93,7 +98,7 @@ index 3a6943b..2669a28 100644 | |||
93 | "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | 98 | "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; |
94 | [(set_attr "type" "no_delay_arith") | 99 | [(set_attr "type" "no_delay_arith") |
95 | (set_attr "mode" "DI") | 100 | (set_attr "mode" "DI") |
96 | @@ -1581,7 +1590,7 @@ | 101 | @@ -1583,7 +1592,7 @@ |
97 | return "ll%i1\t%0,%1"; | 102 | return "ll%i1\t%0,%1"; |
98 | case 3: | 103 | case 3: |
99 | { | 104 | { |
@@ -102,7 +107,7 @@ index 3a6943b..2669a28 100644 | |||
102 | } | 107 | } |
103 | case 5: | 108 | case 5: |
104 | return "sl%i0\t%1,%0"; | 109 | return "sl%i0\t%1,%0"; |
105 | @@ -2371,9 +2380,9 @@ else | 110 | @@ -2373,9 +2382,9 @@ else |
106 | 111 | ||
107 | (define_insn "long_branch_compare" | 112 | (define_insn "long_branch_compare" |
108 | [(set (pc) | 113 | [(set (pc) |
@@ -115,7 +120,7 @@ index 3a6943b..2669a28 100644 | |||
115 | ]) | 120 | ]) |
116 | (label_ref (match_operand 3)) | 121 | (label_ref (match_operand 3)) |
117 | (pc))) | 122 | (pc))) |
118 | @@ -2495,6 +2504,20 @@ else | 123 | @@ -2497,6 +2506,20 @@ else |
119 | ;;---------------------------------------------------------------- | 124 | ;;---------------------------------------------------------------- |
120 | ;; Unconditional branches | 125 | ;; Unconditional branches |
121 | ;;---------------------------------------------------------------- | 126 | ;;---------------------------------------------------------------- |
@@ -136,28 +141,24 @@ index 3a6943b..2669a28 100644 | |||
136 | (define_insn "jump" | 141 | (define_insn "jump" |
137 | [(set (pc) | 142 | [(set (pc) |
138 | (label_ref (match_operand 0 "" "")))] | 143 | (label_ref (match_operand 0 "" "")))] |
139 | @@ -2538,19 +2561,28 @@ else | 144 | @@ -2542,17 +2565,25 @@ else |
140 | (use (label_ref (match_operand 1 "" "")))] | ||
141 | "" | ||
142 | { | 145 | { |
143 | - //gcc_assert (GET_MODE (operands[0]) == Pmode); | 146 | //gcc_assert (GET_MODE (operands[0]) == Pmode); |
144 | - | 147 | |
145 | + gcc_assert (GET_MODE (operands[0]) == Pmode); | 148 | - if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) |
146 | + | ||
147 | if (!flag_pic) | ||
148 | - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | 149 | - emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); |
149 | - else | 150 | - else |
150 | - emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); | 151 | - emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); |
151 | + { | 152 | + if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) { |
152 | + if (!TARGET_MB_64) | 153 | + if (!TARGET_MB_64) |
153 | + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | 154 | + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); |
154 | + else | 155 | + else |
155 | + emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); | 156 | + emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); |
156 | + } | 157 | + } |
157 | + else { | 158 | + else { |
158 | + if (!TARGET_MB_64) | 159 | + if (!TARGET_MB_64) |
159 | + emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); | 160 | + emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); |
160 | + else | 161 | + else |
161 | + emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); | 162 | + emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); |
162 | + } | 163 | + } |
163 | DONE; | 164 | DONE; |
@@ -171,7 +172,7 @@ index 3a6943b..2669a28 100644 | |||
171 | (use (label_ref (match_operand 1 "" "")))] | 172 | (use (label_ref (match_operand 1 "" "")))] |
172 | "" | 173 | "" |
173 | "bra%?\t%0 " | 174 | "bra%?\t%0 " |
174 | @@ -2558,11 +2590,21 @@ else | 175 | @@ -2560,11 +2591,21 @@ else |
175 | (set_attr "mode" "none") | 176 | (set_attr "mode" "none") |
176 | (set_attr "length" "4")]) | 177 | (set_attr "length" "4")]) |
177 | 178 | ||
@@ -196,7 +197,7 @@ index 3a6943b..2669a28 100644 | |||
196 | "" | 197 | "" |
197 | "" | 198 | "" |
198 | ) | 199 | ) |
199 | @@ -2593,6 +2635,23 @@ else | 200 | @@ -2595,6 +2636,23 @@ else |
200 | "" | 201 | "" |
201 | ) | 202 | ) |
202 | 203 | ||
@@ -220,7 +221,7 @@ index 3a6943b..2669a28 100644 | |||
220 | ;;---------------------------------------------------------------- | 221 | ;;---------------------------------------------------------------- |
221 | ;; Function prologue/epilogue and stack allocation | 222 | ;; Function prologue/epilogue and stack allocation |
222 | ;;---------------------------------------------------------------- | 223 | ;;---------------------------------------------------------------- |
223 | @@ -3097,7 +3156,7 @@ else | 224 | @@ -3101,7 +3159,7 @@ else |
224 | ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference | 225 | ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference |
225 | ;; between "mfs" and "addik" instructions. | 226 | ;; between "mfs" and "addik" instructions. |
226 | (define_insn "set_got" | 227 | (define_insn "set_got" |
@@ -230,7 +231,7 @@ index 3a6943b..2669a28 100644 | |||
230 | "" | 231 | "" |
231 | "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" | 232 | "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" |
232 | diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S | 233 | diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S |
233 | index 3386520..3d4cde2 100644 | 234 | index 1811327..a661319 100644 |
234 | --- a/libgcc/config/microblaze/crti.S | 235 | --- a/libgcc/config/microblaze/crti.S |
235 | +++ b/libgcc/config/microblaze/crti.S | 236 | +++ b/libgcc/config/microblaze/crti.S |
236 | @@ -33,11 +33,32 @@ | 237 | @@ -33,11 +33,32 @@ |
@@ -273,7 +274,7 @@ index 3386520..3d4cde2 100644 | |||
273 | sw r15, r0, r1 | 274 | sw r15, r0, r1 |
274 | +#endif | 275 | +#endif |
275 | diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S | 276 | diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S |
276 | index 04e73d7..c262ce0 100644 | 277 | index 60a4648..d72507b 100644 |
277 | --- a/libgcc/config/microblaze/crtn.S | 278 | --- a/libgcc/config/microblaze/crtn.S |
278 | +++ b/libgcc/config/microblaze/crtn.S | 279 | +++ b/libgcc/config/microblaze/crtn.S |
279 | @@ -29,7 +29,19 @@ | 280 | @@ -29,7 +29,19 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0047-Added-double-arith-instructions.patch index f28d9f51..1b7ac28b 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0047-Added-double-arith-instructions.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From b09721c830dd0831f50084e2e64920f83618e3f4 Mon Sep 17 00:00:00 2001 | 1 | From 0f310964ff1c19cbc3404ec7ceba286d6de315c0 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Tue, 9 Oct 2018 10:07:08 +0530 | 3 | Date: Tue, 9 Oct 2018 10:07:08 +0530 |
4 | Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack | 4 | Subject: [PATCH 47/63] -Added double arith instructions -Fixed prologue stack |
5 | pointer decrement issue | 5 | pointer decrement issue |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -10,10 +10,10 @@ Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack | |||
10 | 2 files changed, 76 insertions(+), 9 deletions(-) | 10 | 2 files changed, 76 insertions(+), 9 deletions(-) |
11 | 11 | ||
12 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 12 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
13 | index 2669a28..dca61d6 100644 | 13 | index 65ec32c..c199b27 100644 |
14 | --- a/gcc/config/microblaze/microblaze.md | 14 | --- a/gcc/config/microblaze/microblaze.md |
15 | +++ b/gcc/config/microblaze/microblaze.md | 15 | +++ b/gcc/config/microblaze/microblaze.md |
16 | @@ -525,6 +525,66 @@ | 16 | @@ -527,6 +527,66 @@ |
17 | (set_attr "mode" "SF") | 17 | (set_attr "mode" "SF") |
18 | (set_attr "length" "4")]) | 18 | (set_attr "length" "4")]) |
19 | 19 | ||
@@ -80,7 +80,7 @@ index 2669a28..dca61d6 100644 | |||
80 | (define_insn "floatdidf2" | 80 | (define_insn "floatdidf2" |
81 | [(set (match_operand:DF 0 "register_operand" "=d") | 81 | [(set (match_operand:DF 0 "register_operand" "=d") |
82 | (float:DF (match_operand:DI 1 "register_operand" "d")))] | 82 | (float:DF (match_operand:DI 1 "register_operand" "d")))] |
83 | @@ -534,13 +594,13 @@ | 83 | @@ -536,13 +596,13 @@ |
84 | (set_attr "mode" "DF") | 84 | (set_attr "mode" "DF") |
85 | (set_attr "length" "4")]) | 85 | (set_attr "length" "4")]) |
86 | 86 | ||
@@ -101,7 +101,7 @@ index 2669a28..dca61d6 100644 | |||
101 | (set_attr "length" "4")]) | 101 | (set_attr "length" "4")]) |
102 | 102 | ||
103 | ;;---------------------------------------------------------------- | 103 | ;;---------------------------------------------------------------- |
104 | @@ -658,8 +718,8 @@ | 104 | @@ -660,8 +720,8 @@ |
105 | "TARGET_MB_64" | 105 | "TARGET_MB_64" |
106 | "@ | 106 | "@ |
107 | rsubl\t%0,%2,%1 | 107 | rsubl\t%0,%2,%1 |
@@ -113,7 +113,7 @@ index 2669a28..dca61d6 100644 | |||
113 | (set_attr "mode" "DI") | 113 | (set_attr "mode" "DI") |
114 | (set_attr "length" "4,4,4")]) | 114 | (set_attr "length" "4,4,4")]) |
115 | diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze | 115 | diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze |
116 | index 35ab965..dfef45c 100644 | 116 | index 35ab9654..dfef45c 100644 |
117 | --- a/gcc/config/microblaze/t-microblaze | 117 | --- a/gcc/config/microblaze/t-microblaze |
118 | +++ b/gcc/config/microblaze/t-microblaze | 118 | +++ b/gcc/config/microblaze/t-microblaze |
119 | @@ -1,6 +1,13 @@ | 119 | @@ -1,6 +1,13 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch index 9a214d55..c00b0a2b 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 1ed548dd5993b8c3e58ef393467bdeea49c437be Mon Sep 17 00:00:00 2001 | 1 | From b63cd2a410b9350fa67ed3ca348dcca349da4e44 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Fri, 12 Oct 2018 16:07:36 +0530 | 3 | Date: Fri, 12 Oct 2018 16:07:36 +0530 |
4 | Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap | 4 | Subject: [PATCH 48/63] Fixed the issue in the delay slot with swap |
5 | instructions | 5 | instructions |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap | |||
9 | 1 file changed, 6 insertions(+) | 9 | 1 file changed, 6 insertions(+) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
12 | index dca61d6..d037843 100644 | 12 | index c199b27..d6370d8 100644 |
13 | --- a/gcc/config/microblaze/microblaze.md | 13 | --- a/gcc/config/microblaze/microblaze.md |
14 | +++ b/gcc/config/microblaze/microblaze.md | 14 | +++ b/gcc/config/microblaze/microblaze.md |
15 | @@ -441,6 +441,9 @@ | 15 | @@ -443,6 +443,9 @@ |
16 | (bswap:SI (match_operand:SI 1 "register_operand" "r")))] | 16 | (bswap:SI (match_operand:SI 1 "register_operand" "r")))] |
17 | "TARGET_REORDER" | 17 | "TARGET_REORDER" |
18 | "swapb %0, %1" | 18 | "swapb %0, %1" |
@@ -22,7 +22,7 @@ index dca61d6..d037843 100644 | |||
22 | ) | 22 | ) |
23 | 23 | ||
24 | (define_insn "bswaphi2" | 24 | (define_insn "bswaphi2" |
25 | @@ -449,6 +452,9 @@ | 25 | @@ -451,6 +454,9 @@ |
26 | "TARGET_REORDER" | 26 | "TARGET_REORDER" |
27 | "swapb %0, %1 | 27 | "swapb %0, %1 |
28 | swaph %0, %0" | 28 | swaph %0, %0" |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch index a682bc19..7e92df2e 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 1c889b64454f63f164f34d79d891d91b0bb4731f Mon Sep 17 00:00:00 2001 | 1 | From f39f36cb0f0466343ef4ead50261b58595af708c Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Sat, 13 Oct 2018 21:12:43 +0530 | 3 | Date: Sat, 13 Oct 2018 21:12:43 +0530 |
4 | Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith | 4 | Subject: [PATCH 49/63] Fixed the load store issue with the 32bit arith |
5 | libraries | 5 | libraries |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -13,7 +13,7 @@ Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith | |||
13 | 5 files changed, 98 insertions(+), 4 deletions(-) | 13 | 5 files changed, 98 insertions(+), 4 deletions(-) |
14 | 14 | ||
15 | diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S | 15 | diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S |
16 | index 663d398..7e7d875 100644 | 16 | index 24b94b9..2765e42 100644 |
17 | --- a/libgcc/config/microblaze/divsi3.S | 17 | --- a/libgcc/config/microblaze/divsi3.S |
18 | +++ b/libgcc/config/microblaze/divsi3.S | 18 | +++ b/libgcc/config/microblaze/divsi3.S |
19 | @@ -41,6 +41,17 @@ | 19 | @@ -41,6 +41,17 @@ |
@@ -70,7 +70,7 @@ index 663d398..7e7d875 100644 | |||
70 | .size __divsi3, . - __divsi3 | 70 | .size __divsi3, . - __divsi3 |
71 | 71 | ||
72 | diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S | 72 | diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S |
73 | index 71b56e30..7e85064 100644 | 73 | index 87372f5..7e61453 100644 |
74 | --- a/libgcc/config/microblaze/modsi3.S | 74 | --- a/libgcc/config/microblaze/modsi3.S |
75 | +++ b/libgcc/config/microblaze/modsi3.S | 75 | +++ b/libgcc/config/microblaze/modsi3.S |
76 | @@ -41,6 +41,17 @@ | 76 | @@ -41,6 +41,17 @@ |
@@ -128,7 +128,7 @@ index 71b56e30..7e85064 100644 | |||
128 | .size __modsi3, . - __modsi3 | 128 | .size __modsi3, . - __modsi3 |
129 | 129 | ||
130 | diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S | 130 | diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S |
131 | index 40b0b15..31a73c2 100644 | 131 | index 8c3f788..e28c69a 100644 |
132 | --- a/libgcc/config/microblaze/mulsi3.S | 132 | --- a/libgcc/config/microblaze/mulsi3.S |
133 | +++ b/libgcc/config/microblaze/mulsi3.S | 133 | +++ b/libgcc/config/microblaze/mulsi3.S |
134 | @@ -41,6 +41,9 @@ | 134 | @@ -41,6 +41,9 @@ |
@@ -142,7 +142,7 @@ index 40b0b15..31a73c2 100644 | |||
142 | .frame r1,0,r15 | 142 | .frame r1,0,r15 |
143 | add r3,r0,r0 | 143 | add r3,r0,r0 |
144 | diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S | 144 | diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S |
145 | index 2aef8ed..94adb6a 100644 | 145 | index 5d726ad..b1e44b6 100644 |
146 | --- a/libgcc/config/microblaze/udivsi3.S | 146 | --- a/libgcc/config/microblaze/udivsi3.S |
147 | +++ b/libgcc/config/microblaze/udivsi3.S | 147 | +++ b/libgcc/config/microblaze/udivsi3.S |
148 | @@ -41,6 +41,16 @@ | 148 | @@ -41,6 +41,16 @@ |
@@ -197,7 +197,7 @@ index 2aef8ed..94adb6a 100644 | |||
197 | .end __udivsi3 | 197 | .end __udivsi3 |
198 | .size __udivsi3, . - __udivsi3 | 198 | .size __udivsi3, . - __udivsi3 |
199 | diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S | 199 | diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S |
200 | index a2582d0..00b3bdf 100644 | 200 | index b29d7e1..8804b99 100644 |
201 | --- a/libgcc/config/microblaze/umodsi3.S | 201 | --- a/libgcc/config/microblaze/umodsi3.S |
202 | +++ b/libgcc/config/microblaze/umodsi3.S | 202 | +++ b/libgcc/config/microblaze/umodsi3.S |
203 | @@ -41,6 +41,16 @@ | 203 | @@ -41,6 +41,16 @@ |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch index 95a26db2..ba717327 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch | |||
@@ -1,14 +1,14 @@ | |||
1 | From 751a01ce1eeaffcd41c504b9bf44868345b45da0 Mon Sep 17 00:00:00 2001 | 1 | From 51886f40b6bccea22277f8dcc971706d7c24bdd0 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Mon, 15 Oct 2018 12:00:10 +0530 | 3 | Date: Mon, 15 Oct 2018 12:00:10 +0530 |
4 | Subject: [PATCH 50/54] extending the Dwarf support to 64bit Microblaze | 4 | Subject: [PATCH 50/63] extending the Dwarf support to 64bit Microblaze |
5 | 5 | ||
6 | --- | 6 | --- |
7 | gcc/config/microblaze/microblaze.h | 2 +- | 7 | gcc/config/microblaze/microblaze.h | 2 +- |
8 | 1 file changed, 1 insertion(+), 1 deletion(-) | 8 | 1 file changed, 1 insertion(+), 1 deletion(-) |
9 | 9 | ||
10 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 10 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
11 | index e34f549..0a5ff0a 100644 | 11 | index 7497cfb..bd5e216 100644 |
12 | --- a/gcc/config/microblaze/microblaze.h | 12 | --- a/gcc/config/microblaze/microblaze.h |
13 | +++ b/gcc/config/microblaze/microblaze.h | 13 | +++ b/gcc/config/microblaze/microblaze.h |
14 | @@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; | 14 | @@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch index 574037ec..a0758b31 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch | |||
@@ -1,14 +1,14 @@ | |||
1 | From 295046d0a63148fb5a685ae2bd7a06489274c72a Mon Sep 17 00:00:00 2001 | 1 | From a8978d71c8b5adfa59430443611bd785a4d54ef9 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Tue, 16 Oct 2018 07:55:46 +0530 | 3 | Date: Tue, 16 Oct 2018 07:55:46 +0530 |
4 | Subject: [PATCH 51/54] fixing the typo errors in umodsi3 file | 4 | Subject: [PATCH 51/63] fixing the typo errors in umodsi3 file |
5 | 5 | ||
6 | --- | 6 | --- |
7 | libgcc/config/microblaze/umodsi3.S | 6 +++--- | 7 | libgcc/config/microblaze/umodsi3.S | 6 +++--- |
8 | 1 file changed, 3 insertions(+), 3 deletions(-) | 8 | 1 file changed, 3 insertions(+), 3 deletions(-) |
9 | 9 | ||
10 | diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S | 10 | diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S |
11 | index 00b3bdf..9bf65c3 100644 | 11 | index 8804b99..1b3070e 100644 |
12 | --- a/libgcc/config/microblaze/umodsi3.S | 12 | --- a/libgcc/config/microblaze/umodsi3.S |
13 | +++ b/libgcc/config/microblaze/umodsi3.S | 13 | +++ b/libgcc/config/microblaze/umodsi3.S |
14 | @@ -47,9 +47,9 @@ __umodsi3: | 14 | @@ -47,9 +47,9 @@ __umodsi3: |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch index 95d39bb2..d0b534bc 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch | |||
@@ -1,14 +1,14 @@ | |||
1 | From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001 | 1 | From 328bd339c292b63d2068a132a245bdc037815d6b Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Wed, 17 Oct 2018 16:56:14 +0530 | 3 | Date: Wed, 17 Oct 2018 16:56:14 +0530 |
4 | Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024) | 4 | Subject: [PATCH 52/63] fixing the 32bit LTO related issue9(1014024) |
5 | 5 | ||
6 | --- | 6 | --- |
7 | gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- | 7 | gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- |
8 | 1 file changed, 14 insertions(+), 10 deletions(-) | 8 | 1 file changed, 14 insertions(+), 10 deletions(-) |
9 | 9 | ||
10 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h | 10 | diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h |
11 | index 0a5ff0a..740b8d9 100644 | 11 | index bd5e216..ab541f7 100644 |
12 | --- a/gcc/config/microblaze/microblaze.h | 12 | --- a/gcc/config/microblaze/microblaze.h |
13 | +++ b/gcc/config/microblaze/microblaze.h | 13 | +++ b/gcc/config/microblaze/microblaze.h |
14 | @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; | 14 | @@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch index e992075b..f8ac364c 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 3e7161218dc8b4dd84ad8d31f6dbaa7c256e7a82 Mon Sep 17 00:00:00 2001 | 1 | From 3f65f0432d42f4d469fbb10828f1683cd30a5d84 Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Fri, 19 Oct 2018 14:26:25 +0530 | 3 | Date: Fri, 19 Oct 2018 14:26:25 +0530 |
4 | Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of | 4 | Subject: [PATCH 53/63] Fixed the missing stack adjustment in prologue of |
5 | modsi3 function | 5 | modsi3 function |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,7 +9,7 @@ Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of | |||
9 | 1 file changed, 1 insertion(+) | 9 | 1 file changed, 1 insertion(+) |
10 | 10 | ||
11 | diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S | 11 | diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S |
12 | index 7e85064..46ff34a 100644 | 12 | index 7e61453..b0e6cad 100644 |
13 | --- a/libgcc/config/microblaze/modsi3.S | 13 | --- a/libgcc/config/microblaze/modsi3.S |
14 | +++ b/libgcc/config/microblaze/modsi3.S | 14 | +++ b/libgcc/config/microblaze/modsi3.S |
15 | @@ -119,6 +119,7 @@ $LaRETURN_HERE: | 15 | @@ -119,6 +119,7 @@ $LaRETURN_HERE: |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch index afb88d35..0e704506 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From a89b3e6902d7835129ad178f6af896eba15c5d5e Mon Sep 17 00:00:00 2001 | 1 | From 0dbb2b7bfe466c18d54aec680208fd1459619bc1 Mon Sep 17 00:00:00 2001 |
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | 2 | From: Mahesh Bodapati <mbodapat@xilinx.com> |
3 | Date: Wed, 24 Oct 2018 18:31:04 +0530 | 3 | Date: Wed, 24 Oct 2018 18:31:04 +0530 |
4 | Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong | 4 | Subject: [PATCH 54/63] [Patch,Microblaze] : corrected SPN for dlong |
5 | instruction mapping. | 5 | instruction mapping. |
6 | 6 | ||
7 | --- | 7 | --- |
@@ -9,10 +9,10 @@ Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong | |||
9 | 1 file changed, 2 insertions(+), 2 deletions(-) | 9 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
12 | index d037843..cbd7e77 100644 | 12 | index d6370d8..6b6b7c6 100644 |
13 | --- a/gcc/config/microblaze/microblaze.md | 13 | --- a/gcc/config/microblaze/microblaze.md |
14 | +++ b/gcc/config/microblaze/microblaze.md | 14 | +++ b/gcc/config/microblaze/microblaze.md |
15 | @@ -600,9 +600,9 @@ | 15 | @@ -602,9 +602,9 @@ |
16 | (set_attr "mode" "DF") | 16 | (set_attr "mode" "DF") |
17 | (set_attr "length" "4")]) | 17 | (set_attr "length" "4")]) |
18 | 18 | ||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch index 4c694723..28554722 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 76e231f92afd8fda13d6ae18ef3aef0ea6096489 Mon Sep 17 00:00:00 2001 | 1 | From a56b23ae244eee1da6d6595d3a6477085d77271e Mon Sep 17 00:00:00 2001 |
2 | From: Nagaraju Mekala <nmekala@xilix.com> | 2 | From: Nagaraju Mekala <nmekala@xilix.com> |
3 | Date: Thu, 29 Nov 2018 17:55:08 +0530 | 3 | Date: Thu, 29 Nov 2018 17:55:08 +0530 |
4 | Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue | 4 | Subject: [PATCH 55/63] fixing the long & long long mingw toolchain issue |
5 | 5 | ||
6 | --- | 6 | --- |
7 | gcc/config/microblaze/constraints.md | 2 +- | 7 | gcc/config/microblaze/constraints.md | 2 +- |
@@ -9,7 +9,7 @@ Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue | |||
9 | 2 files changed, 5 insertions(+), 5 deletions(-) | 9 | 2 files changed, 5 insertions(+), 5 deletions(-) |
10 | 10 | ||
11 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md | 11 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md |
12 | index 867a7b5..27c6bfc 100644 | 12 | index 2fce91e..9a5aa6b 100644 |
13 | --- a/gcc/config/microblaze/constraints.md | 13 | --- a/gcc/config/microblaze/constraints.md |
14 | +++ b/gcc/config/microblaze/constraints.md | 14 | +++ b/gcc/config/microblaze/constraints.md |
15 | @@ -55,7 +55,7 @@ | 15 | @@ -55,7 +55,7 @@ |
@@ -22,10 +22,10 @@ index 867a7b5..27c6bfc 100644 | |||
22 | ;; Define floating point constraints | 22 | ;; Define floating point constraints |
23 | 23 | ||
24 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | 24 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md |
25 | index cbd7e77..e03b835 100644 | 25 | index 6b6b7c6..a1dc41f 100644 |
26 | --- a/gcc/config/microblaze/microblaze.md | 26 | --- a/gcc/config/microblaze/microblaze.md |
27 | +++ b/gcc/config/microblaze/microblaze.md | 27 | +++ b/gcc/config/microblaze/microblaze.md |
28 | @@ -646,8 +646,8 @@ | 28 | @@ -648,8 +648,8 @@ |
29 | if (TARGET_MB_64) | 29 | if (TARGET_MB_64) |
30 | { | 30 | { |
31 | if (GET_CODE (operands[2]) == CONST_INT && | 31 | if (GET_CODE (operands[2]) == CONST_INT && |
@@ -36,7 +36,7 @@ index cbd7e77..e03b835 100644 | |||
36 | FAIL; | 36 | FAIL; |
37 | } | 37 | } |
38 | }) | 38 | }) |
39 | @@ -1264,7 +1264,7 @@ | 39 | @@ -1266,7 +1266,7 @@ |
40 | (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] | 40 | (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] |
41 | "TARGET_MB_64 && (register_operand (operands[0], DImode) && | 41 | "TARGET_MB_64 && (register_operand (operands[0], DImode) && |
42 | (GET_CODE (operands[1]) == CONST_INT && | 42 | (GET_CODE (operands[1]) == CONST_INT && |
@@ -45,7 +45,7 @@ index cbd7e77..e03b835 100644 | |||
45 | "@ | 45 | "@ |
46 | addlk\t%0,r0,r0\t | 46 | addlk\t%0,r0,r0\t |
47 | addlik\t%0,r0,%1\t #N1 %X1 | 47 | addlik\t%0,r0,%1\t #N1 %X1 |
48 | @@ -1298,7 +1298,7 @@ | 48 | @@ -1300,7 +1300,7 @@ |
49 | case 1: | 49 | case 1: |
50 | case 2: | 50 | case 2: |
51 | if (GET_CODE (operands[1]) == CONST_INT && | 51 | if (GET_CODE (operands[1]) == CONST_INT && |
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch index c009c92d..c009c92d 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch new file mode 100644 index 00000000..a419216c --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch | |||
@@ -0,0 +1,47 @@ | |||
1 | From e13b1b70972511a642512cbc7093ed21e5a9e141 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Thu, 14 Mar 2019 18:11:04 +0530 | ||
4 | Subject: [PATCH 56/63] Fix the MB-64 bug of handling QI objects | ||
5 | |||
6 | --- | ||
7 | gcc/config/microblaze/microblaze.md | 14 +++++++------- | ||
8 | 1 file changed, 7 insertions(+), 7 deletions(-) | ||
9 | |||
10 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
11 | index a1dc41f..bb96e2d 100644 | ||
12 | --- a/gcc/config/microblaze/microblaze.md | ||
13 | +++ b/gcc/config/microblaze/microblaze.md | ||
14 | @@ -2347,11 +2347,11 @@ else | ||
15 | |||
16 | (define_insn "branch_zero_64" | ||
17 | [(set (pc) | ||
18 | - (if_then_else (match_operator:SI 0 "ordered_comparison_operator" | ||
19 | + (if_then_else (match_operator 0 "ordered_comparison_operator" | ||
20 | [(match_operand:SI 1 "register_operand" "d") | ||
21 | (const_int 0)]) | ||
22 | - (match_operand:SI 2 "pc_or_label_operand" "") | ||
23 | - (match_operand:SI 3 "pc_or_label_operand" ""))) | ||
24 | + (match_operand 2 "pc_or_label_operand" "") | ||
25 | + (match_operand 3 "pc_or_label_operand" ""))) | ||
26 | ] | ||
27 | "TARGET_MB_64" | ||
28 | { | ||
29 | @@ -2367,11 +2367,11 @@ else | ||
30 | |||
31 | (define_insn "long_branch_zero" | ||
32 | [(set (pc) | ||
33 | - (if_then_else (match_operator 0 "ordered_comparison_operator" | ||
34 | - [(match_operand 1 "register_operand" "d") | ||
35 | + (if_then_else (match_operator:DI 0 "ordered_comparison_operator" | ||
36 | + [(match_operand:DI 1 "register_operand" "d") | ||
37 | (const_int 0)]) | ||
38 | - (match_operand 2 "pc_or_label_operand" "") | ||
39 | - (match_operand 3 "pc_or_label_operand" ""))) | ||
40 | + (match_operand:DI 2 "pc_or_label_operand" "") | ||
41 | + (match_operand:DI 3 "pc_or_label_operand" ""))) | ||
42 | ] | ||
43 | "TARGET_MB_64" | ||
44 | { | ||
45 | -- | ||
46 | 2.7.4 | ||
47 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch new file mode 100644 index 00000000..ff524770 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch | |||
@@ -0,0 +1,36 @@ | |||
1 | From f30b99b5b8d3f2a8d8e4973cd155a4b9f1849039 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Thu, 14 Mar 2019 18:08:06 +0530 | ||
4 | Subject: [PATCH 56/57] fix the lto-wrapper issue on windows | ||
5 | |||
6 | --- | ||
7 | libiberty/simple-object.c | 6 +++++- | ||
8 | 1 file changed, 5 insertions(+), 1 deletion(-) | ||
9 | |||
10 | diff --git a/libiberty/simple-object.c b/libiberty/simple-object.c | ||
11 | index 42aa6ac..d2465c6 100644 | ||
12 | --- a/libiberty/simple-object.c | ||
13 | +++ b/libiberty/simple-object.c | ||
14 | @@ -44,6 +44,10 @@ Boston, MA 02110-1301, USA. */ | ||
15 | #define SEEK_SET 0 | ||
16 | #endif | ||
17 | |||
18 | +#ifndef O_BINARY | ||
19 | +#define O_BINARY 0 | ||
20 | +#endif | ||
21 | + | ||
22 | #include "simple-object-common.h" | ||
23 | |||
24 | /* The known object file formats. */ | ||
25 | @@ -326,7 +330,7 @@ simple_object_copy_lto_debug_sections (simple_object_read *sobj, | ||
26 | return errmsg; | ||
27 | } | ||
28 | |||
29 | - outfd = creat (dest, 00777); | ||
30 | + outfd = open (dest, O_CREAT|O_WRONLY|O_TRUNC|O_BINARY, 00777); | ||
31 | if (outfd == -1) | ||
32 | { | ||
33 | *err = errno; | ||
34 | -- | ||
35 | 2.7.4 | ||
36 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch index a5a2039d..a5a2039d 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch new file mode 100644 index 00000000..940009de --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch | |||
@@ -0,0 +1,87 @@ | |||
1 | From 1387d4fedb397f78b08ad33204a3fcf2bd63f183 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Fri, 29 Mar 2019 12:08:39 +0530 | ||
4 | Subject: [PATCH 57/63] [Patch,Microblaze] : We will check the possibility of | ||
5 | peephole2 optimization,if we can then we will fix the compiler issue. | ||
6 | |||
7 | --- | ||
8 | gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++--------------- | ||
9 | 1 file changed, 38 insertions(+), 25 deletions(-) | ||
10 | |||
11 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
12 | index bb96e2d..830ef77 100644 | ||
13 | --- a/gcc/config/microblaze/microblaze.md | ||
14 | +++ b/gcc/config/microblaze/microblaze.md | ||
15 | @@ -882,31 +882,44 @@ | ||
16 | (set_attr "mode" "SI") | ||
17 | (set_attr "length" "4")]) | ||
18 | |||
19 | -(define_peephole2 | ||
20 | - [(set (match_operand:SI 0 "register_operand") | ||
21 | - (fix:SI (match_operand:SF 1 "register_operand"))) | ||
22 | - (set (pc) | ||
23 | - (if_then_else (match_operator 2 "ordered_comparison_operator" | ||
24 | - [(match_operand:SI 3 "register_operand") | ||
25 | - (match_operand:SI 4 "arith_operand")]) | ||
26 | - (label_ref (match_operand 5)) | ||
27 | - (pc)))] | ||
28 | - "TARGET_HARD_FLOAT && !TARGET_MB_64" | ||
29 | - [(set (match_dup 1) (match_dup 3))] | ||
30 | - | ||
31 | - { | ||
32 | - rtx condition; | ||
33 | - rtx cmp_op0 = operands[3]; | ||
34 | - rtx cmp_op1 = operands[4]; | ||
35 | - rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); | ||
36 | - | ||
37 | - emit_insn (gen_cstoresf4 (comp_reg, operands[2], | ||
38 | - gen_rtx_REG (SFmode, REGNO (cmp_op0)), | ||
39 | - gen_rtx_REG (SFmode, REGNO (cmp_op1)))); | ||
40 | - condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); | ||
41 | - emit_jump_insn (gen_condjump (condition, operands[5])); | ||
42 | - } | ||
43 | -) | ||
44 | +;; peephole2 optimization will be done only if fint and if-then-else | ||
45 | +;; are dependent.added condition for the same. | ||
46 | +;; if they are dependent then gcc is giving "flow control insn inside a basic block" | ||
47 | +;; testcase: | ||
48 | +;; volatile float vec = 1.0; | ||
49 | +;; volatile int ci = 2; | ||
50 | +;; register int cj = (int)(vec); | ||
51 | +;;// ci=cj; | ||
52 | +;;// if (ci <0) { | ||
53 | +;; if (cj < 0) { | ||
54 | +;; ci = 0; | ||
55 | +;; } | ||
56 | +;; commenting for now.we will check the possibility of this optimization later | ||
57 | + | ||
58 | +;;(define_peephole2 | ||
59 | +;; [(set (match_operand:SI 0 "register_operand") | ||
60 | +;; (fix:SI (match_operand:SF 1 "register_operand"))) | ||
61 | +;; (set (pc) | ||
62 | +;; (if_then_else (match_operator 2 "ordered_comparison_operator" | ||
63 | +;; [(match_operand:SI 3 "register_operand") | ||
64 | +;; (match_operand:SI 4 "arith_operand")]) | ||
65 | +;; (label_ref (match_operand 5)) | ||
66 | +;; (pc)))] | ||
67 | +;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" | ||
68 | +;; [(set (match_dup 1) (match_dup 3))] | ||
69 | +;; { | ||
70 | +;; rtx condition; | ||
71 | +;; rtx cmp_op0 = operands[3]; | ||
72 | +;; rtx cmp_op1 = operands[4]; | ||
73 | +;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); | ||
74 | +;; | ||
75 | +;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], | ||
76 | +;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), | ||
77 | +;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); | ||
78 | +;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); | ||
79 | +;; emit_jump_insn (gen_condjump (condition, operands[5])); | ||
80 | +;; } | ||
81 | +;;) | ||
82 | |||
83 | ;;---------------------------------------------------------------- | ||
84 | ;; Negation and one's complement | ||
85 | -- | ||
86 | 2.7.4 | ||
87 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch index 8bc47a43..8bc47a43 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch new file mode 100644 index 00000000..69b49898 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch | |||
@@ -0,0 +1,51 @@ | |||
1 | From 8e7d7f3d2e103c34bbb28afe1338107b9fd824f0 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Tue, 16 Apr 2019 17:20:24 +0530 | ||
4 | Subject: [PATCH 58/63] Reverting the patch as kernel boot is not working with | ||
5 | this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check | ||
6 | before propagating constants." | ||
7 | |||
8 | This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b. | ||
9 | --- | ||
10 | gcc/cprop.c | 4 ---- | ||
11 | 1 file changed, 4 deletions(-) | ||
12 | |||
13 | diff --git a/gcc/cprop.c b/gcc/cprop.c | ||
14 | index 42bcc81..65c0130 100644 | ||
15 | --- a/gcc/cprop.c | ||
16 | +++ b/gcc/cprop.c | ||
17 | @@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) | ||
18 | int success = 0; | ||
19 | rtx set = single_set (insn); | ||
20 | |||
21 | -#if 0 | ||
22 | bool check_rtx_costs = true; | ||
23 | bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); | ||
24 | int old_cost = set ? set_rtx_cost (set, speed) : 0; | ||
25 | @@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) | ||
26 | && (GET_CODE (XEXP (note, 0)) == CONST | ||
27 | || CONSTANT_P (XEXP (note, 0))))) | ||
28 | check_rtx_costs = false; | ||
29 | -#endif | ||
30 | |||
31 | /* Usually we substitute easy stuff, so we won't copy everything. | ||
32 | We however need to take care to not duplicate non-trivial CONST | ||
33 | @@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) | ||
34 | |||
35 | validate_replace_src_group (from, to, insn); | ||
36 | |||
37 | -#if 0 | ||
38 | /* If TO is a constant, check the cost of the set after propagation | ||
39 | to the cost of the set before the propagation. If the cost is | ||
40 | higher, then do not replace FROM with TO. */ | ||
41 | @@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) | ||
42 | return false; | ||
43 | } | ||
44 | |||
45 | -#endif | ||
46 | |||
47 | if (num_changes_pending () && apply_change_group ()) | ||
48 | success = 1; | ||
49 | -- | ||
50 | 2.7.4 | ||
51 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch new file mode 100644 index 00000000..2e570330 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch | |||
@@ -0,0 +1,466 @@ | |||
1 | From e1a10a708f209704a3921cf66dd3ff4d0814befc Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Wed, 17 Apr 2019 12:36:16 +0530 | ||
4 | Subject: [PATCH 59/63] [Patch,MicroBlaze]: fixed typos in mul,div and mod | ||
5 | assembly files. | ||
6 | |||
7 | --- | ||
8 | libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++---- | ||
9 | libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++--- | ||
10 | libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++- | ||
11 | libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++---- | ||
12 | libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++--- | ||
13 | 5 files changed, 212 insertions(+), 20 deletions(-) | ||
14 | |||
15 | diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S | ||
16 | index 2765e42..bd56522 100644 | ||
17 | --- a/libgcc/config/microblaze/divsi3.S | ||
18 | +++ b/libgcc/config/microblaze/divsi3.S | ||
19 | @@ -46,7 +46,7 @@ | ||
20 | __divsi3: | ||
21 | .frame r1,0,r15 | ||
22 | |||
23 | - ADDIK r1,r1,-32 | ||
24 | + ADDLIK r1,r1,-32 | ||
25 | SLI r28,r1,0 | ||
26 | SLI r29,r1,8 | ||
27 | SLI r30,r1,16 | ||
28 | @@ -61,13 +61,23 @@ __divsi3: | ||
29 | SWI r30,r1,8 | ||
30 | SWI r31,r1,12 | ||
31 | #endif | ||
32 | - BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
33 | - BEQI r5,$LaResult_Is_Zero # Result is Zero | ||
34 | - BGEID r5,$LaR5_Pos | ||
35 | +#ifdef __arch64__ | ||
36 | + BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
37 | + BEAEQI r5,$LaResult_Is_Zero # Result is Zero | ||
38 | + BEAGEID r5,$LaR5_Pos | ||
39 | +#else | ||
40 | + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
41 | + BEQI r5,$LaResult_Is_Zero # Result is Zero | ||
42 | + BGEID r5,$LaR5_Pos | ||
43 | +#endif | ||
44 | XOR r28,r5,r6 # Get the sign of the result | ||
45 | RSUBI r5,r5,0 # Make r5 positive | ||
46 | $LaR5_Pos: | ||
47 | - BGEI r6,$LaR6_Pos | ||
48 | +#ifdef __arch64__ | ||
49 | + BEAGEI r6,$LaR6_Pos | ||
50 | +#else | ||
51 | + BGEI r6,$LaR6_Pos | ||
52 | +#endif | ||
53 | RSUBI r6,r6,0 # Make r6 positive | ||
54 | $LaR6_Pos: | ||
55 | ADDIK r30,r0,0 # Clear mod | ||
56 | @@ -76,26 +86,51 @@ $LaR6_Pos: | ||
57 | |||
58 | # First part try to find the first '1' in the r5 | ||
59 | $LaDIV0: | ||
60 | - BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 | ||
61 | +#ifdef __arch64__ | ||
62 | + BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 | ||
63 | +#else | ||
64 | + BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 | ||
65 | +#endif | ||
66 | $LaDIV1: | ||
67 | ADD r5,r5,r5 # left shift logical r5 | ||
68 | +#ifdef __arch64__ | ||
69 | + BEAGTID r5,$LaDIV1 | ||
70 | +#else | ||
71 | BGTID r5,$LaDIV1 | ||
72 | +#endif | ||
73 | ADDIK r29,r29,-1 | ||
74 | $LaDIV2: | ||
75 | ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry | ||
76 | ADDC r30,r30,r30 # Move that bit into the Mod register | ||
77 | RSUB r31,r6,r30 # Try to subtract (r30 a r6) | ||
78 | +#ifdef __arch64__ | ||
79 | + BEALTI r31,$LaMOD_TOO_SMALL | ||
80 | +#else | ||
81 | BLTI r31,$LaMOD_TOO_SMALL | ||
82 | +#endif | ||
83 | OR r30,r0,r31 # Move the r31 to mod since the result was positive | ||
84 | ADDIK r3,r3,1 | ||
85 | $LaMOD_TOO_SMALL: | ||
86 | ADDIK r29,r29,-1 | ||
87 | +#ifdef __arch64__ | ||
88 | + BEAEQi r29,$LaLOOP_END | ||
89 | +#else | ||
90 | BEQi r29,$LaLOOP_END | ||
91 | +#endif | ||
92 | ADD r3,r3,r3 # Shift in the '1' into div | ||
93 | +#ifdef __arch64__ | ||
94 | + BREAI $LaDIV2 # Div2 | ||
95 | +#else | ||
96 | BRI $LaDIV2 # Div2 | ||
97 | +#endif | ||
98 | $LaLOOP_END: | ||
99 | +#ifdef __arch64__ | ||
100 | + BEAGEI r28,$LaRETURN_HERE | ||
101 | + BREAID $LaRETURN_HERE | ||
102 | +#else | ||
103 | BGEI r28,$LaRETURN_HERE | ||
104 | BRID $LaRETURN_HERE | ||
105 | +#endif | ||
106 | RSUBI r3,r3,0 # Negate the result | ||
107 | $LaDiv_By_Zero: | ||
108 | $LaResult_Is_Zero: | ||
109 | diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S | ||
110 | index b0e6cad..3632fad 100644 | ||
111 | --- a/libgcc/config/microblaze/modsi3.S | ||
112 | +++ b/libgcc/config/microblaze/modsi3.S | ||
113 | @@ -62,40 +62,72 @@ __modsi3: | ||
114 | swi r31,r1,12 | ||
115 | #endif | ||
116 | |||
117 | +#ifdef __arch64__ | ||
118 | + BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
119 | + BEAEQI r5,$LaResult_Is_Zero # Result is Zero | ||
120 | + BEAGEId r5,$LaR5_Pos | ||
121 | +#else | ||
122 | BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
123 | BEQI r5,$LaResult_Is_Zero # Result is Zero | ||
124 | BGEId r5,$LaR5_Pos | ||
125 | +#endif | ||
126 | ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] | ||
127 | RSUBI r5,r5,0 # Make r5 positive | ||
128 | $LaR5_Pos: | ||
129 | - BGEI r6,$LaR6_Pos | ||
130 | +#ifdef __arch64__ | ||
131 | + BEAGEI r6,$LaR6_Pos | ||
132 | +#else | ||
133 | + BGEI r6,$LaR6_Pos | ||
134 | +#endif | ||
135 | RSUBI r6,r6,0 # Make r6 positive | ||
136 | $LaR6_Pos: | ||
137 | ADDIK r3,r0,0 # Clear mod | ||
138 | ADDIK r30,r0,0 # clear div | ||
139 | - BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip | ||
140 | +#ifdef __arch64__ | ||
141 | + BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip | ||
142 | # the first bit search. | ||
143 | +#else | ||
144 | + BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip | ||
145 | + # the first bit search. | ||
146 | +#endif | ||
147 | ADDIK r29,r0,32 # Initialize the loop count | ||
148 | # First part try to find the first '1' in the r5 | ||
149 | $LaDIV1: | ||
150 | ADD r5,r5,r5 # left shift logical r5 | ||
151 | - BGEID r5,$LaDIV1 # | ||
152 | +#ifdef __arch64__ | ||
153 | + BEAGEID r5,$LaDIV1 # | ||
154 | +#else | ||
155 | + BGEID r5,$LaDIV1 # | ||
156 | +#endif | ||
157 | ADDIK r29,r29,-1 | ||
158 | $LaDIV2: | ||
159 | ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry | ||
160 | ADDC r3,r3,r3 # Move that bit into the Mod register | ||
161 | rSUB r31,r6,r3 # Try to subtract (r30 a r6) | ||
162 | +#ifdef __arch64__ | ||
163 | + BEALTi r31,$LaMOD_TOO_SMALL | ||
164 | +#else | ||
165 | BLTi r31,$LaMOD_TOO_SMALL | ||
166 | +#endif | ||
167 | OR r3,r0,r31 # Move the r31 to mod since the result was positive | ||
168 | ADDIK r30,r30,1 | ||
169 | $LaMOD_TOO_SMALL: | ||
170 | ADDIK r29,r29,-1 | ||
171 | +#ifdef __arch64__ | ||
172 | + BEAEQi r29,$LaLOOP_END | ||
173 | + ADD r30,r30,r30 # Shift in the '1' into div | ||
174 | + BREAI $LaDIV2 # Div2 | ||
175 | +$LaLOOP_END: | ||
176 | + BEAGEI r28,$LaRETURN_HERE | ||
177 | + BREAId $LaRETURN_HERE | ||
178 | +#else | ||
179 | BEQi r29,$LaLOOP_END | ||
180 | ADD r30,r30,r30 # Shift in the '1' into div | ||
181 | BRI $LaDIV2 # Div2 | ||
182 | $LaLOOP_END: | ||
183 | BGEI r28,$LaRETURN_HERE | ||
184 | BRId $LaRETURN_HERE | ||
185 | +#endif | ||
186 | rsubi r3,r3,0 # Negate the result | ||
187 | $LaDiv_By_Zero: | ||
188 | $LaResult_Is_Zero: | ||
189 | @@ -108,7 +140,7 @@ $LaRETURN_HERE: | ||
190 | lli r29,r1,8 | ||
191 | lli r30,r1,16 | ||
192 | lli r31,r1,24 | ||
193 | - addik r1,r1,32 | ||
194 | + addlik r1,r1,32 | ||
195 | rtsd r15,8 | ||
196 | nop | ||
197 | #else | ||
198 | diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S | ||
199 | index e28c69a..991dbcd 100644 | ||
200 | --- a/libgcc/config/microblaze/mulsi3.S | ||
201 | +++ b/libgcc/config/microblaze/mulsi3.S | ||
202 | @@ -43,7 +43,37 @@ | ||
203 | .type __mulsi3,@function | ||
204 | #ifdef __arch64__ | ||
205 | .align 3 | ||
206 | -#endif | ||
207 | +__mulsi3: | ||
208 | + .frame r1,0,r15 | ||
209 | + add r3,r0,r0 | ||
210 | + BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero | ||
211 | + BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero | ||
212 | + BEAGEId r5,$L_R5_Pos | ||
213 | + XOR r4,r5,r6 # Get the sign of the result | ||
214 | + RSUBI r5,r5,0 # Make r5 positive | ||
215 | +$L_R5_Pos: | ||
216 | + BEAGEI r6,$L_R6_Pos | ||
217 | + RSUBI r6,r6,0 # Make r6 positive | ||
218 | +$L_R6_Pos: | ||
219 | + breai $L1 | ||
220 | +$L2: | ||
221 | + add r5,r5,r5 | ||
222 | +$L1: | ||
223 | + srl r6,r6 | ||
224 | + addc r7,r0,r0 | ||
225 | + beaeqi r7,$L2 | ||
226 | + beaneid r6,$L2 | ||
227 | + add r3,r3,r5 | ||
228 | + bealti r4,$L_NegateResult | ||
229 | + rtsd r15,8 | ||
230 | + nop | ||
231 | +$L_NegateResult: | ||
232 | + rtsd r15,8 | ||
233 | + rsub r3,r3,r0 | ||
234 | +$L_Result_Is_Zero: | ||
235 | + rtsd r15,8 | ||
236 | + addi r3,r0,0 | ||
237 | +#else | ||
238 | __mulsi3: | ||
239 | .frame r1,0,r15 | ||
240 | add r3,r0,r0 | ||
241 | @@ -74,5 +104,6 @@ $L_NegateResult: | ||
242 | $L_Result_Is_Zero: | ||
243 | rtsd r15,8 | ||
244 | addi r3,r0,0 | ||
245 | +#endif | ||
246 | .end __mulsi3 | ||
247 | .size __mulsi3, . - __mulsi3 | ||
248 | diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S | ||
249 | index b1e44b6..42b086e 100644 | ||
250 | --- a/libgcc/config/microblaze/udivsi3.S | ||
251 | +++ b/libgcc/config/microblaze/udivsi3.S | ||
252 | @@ -59,52 +59,96 @@ __udivsi3: | ||
253 | SWI r30,r1,4 | ||
254 | SWI r31,r1,8 | ||
255 | #endif | ||
256 | +#ifdef __arch64__ | ||
257 | + BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
258 | + BEAEQID r5,$LaResult_Is_Zero # Result is Zero | ||
259 | +#else | ||
260 | BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
261 | BEQID r5,$LaResult_Is_Zero # Result is Zero | ||
262 | +#endif | ||
263 | ADDIK r30,r0,0 # Clear mod | ||
264 | ADDIK r29,r0,32 # Initialize the loop count | ||
265 | |||
266 | # Check if r6 and r5 are equal # if yes, return 1 | ||
267 | RSUB r18,r5,r6 | ||
268 | +#ifdef __arch64__ | ||
269 | + BEAEQID r18,$LaRETURN_HERE | ||
270 | +#else | ||
271 | BEQID r18,$LaRETURN_HERE | ||
272 | +#endif | ||
273 | ADDIK r3,r0,1 | ||
274 | |||
275 | # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 | ||
276 | XOR r18,r5,r6 | ||
277 | - BGEID r18,16 | ||
278 | +#ifdef __arch64__ | ||
279 | + BEAGEID r18,16 | ||
280 | +#else | ||
281 | + BGEID r18,16 | ||
282 | +#endif | ||
283 | ADD r3,r0,r0 # We would anyways clear r3 | ||
284 | +#ifdef __arch64__ | ||
285 | + BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater | ||
286 | + BREAI $LCheckr6 | ||
287 | + RSUB r18,r6,r5 # MICROBLAZEcmp | ||
288 | + BEALTI r18,$LaRETURN_HERE | ||
289 | +#else | ||
290 | BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater | ||
291 | BRI $LCheckr6 | ||
292 | RSUB r18,r6,r5 # MICROBLAZEcmp | ||
293 | BLTI r18,$LaRETURN_HERE | ||
294 | - | ||
295 | +#endif | ||
296 | # If r6 [bit 31] is set, then return result as 1 | ||
297 | $LCheckr6: | ||
298 | - BGTI r6,$LaDIV0 | ||
299 | - BRID $LaRETURN_HERE | ||
300 | +#ifdef __arch64__ | ||
301 | + BEAGTI r6,$LaDIV0 | ||
302 | + BREAID $LaRETURN_HERE | ||
303 | +#else | ||
304 | + BGTI r6,$LaDIV0 | ||
305 | + BRID $LaRETURN_HERE | ||
306 | +#endif | ||
307 | ADDIK r3,r0,1 | ||
308 | |||
309 | # First part try to find the first '1' in the r5 | ||
310 | $LaDIV0: | ||
311 | +#ifdef __arch64__ | ||
312 | + BEALTI r5,$LaDIV2 | ||
313 | +#else | ||
314 | BLTI r5,$LaDIV2 | ||
315 | +#endif | ||
316 | $LaDIV1: | ||
317 | ADD r5,r5,r5 # left shift logical r5 | ||
318 | +#ifdef __arch64__ | ||
319 | + BEAGTID r5,$LaDIV1 | ||
320 | +#else | ||
321 | BGTID r5,$LaDIV1 | ||
322 | +#endif | ||
323 | ADDIK r29,r29,-1 | ||
324 | $LaDIV2: | ||
325 | ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry | ||
326 | ADDC r30,r30,r30 # Move that bit into the Mod register | ||
327 | RSUB r31,r6,r30 # Try to subtract (r30 a r6) | ||
328 | +#ifdef __arch64__ | ||
329 | + BEALTI r31,$LaMOD_TOO_SMALL | ||
330 | +#else | ||
331 | BLTI r31,$LaMOD_TOO_SMALL | ||
332 | +#endif | ||
333 | OR r30,r0,r31 # Move the r31 to mod since the result was positive | ||
334 | ADDIK r3,r3,1 | ||
335 | $LaMOD_TOO_SMALL: | ||
336 | ADDIK r29,r29,-1 | ||
337 | +#ifdef __arch64__ | ||
338 | + BEAEQi r29,$LaLOOP_END | ||
339 | + ADD r3,r3,r3 # Shift in the '1' into div | ||
340 | + BREAI $LaDIV2 # Div2 | ||
341 | +$LaLOOP_END: | ||
342 | + BREAI $LaRETURN_HERE | ||
343 | +#else | ||
344 | BEQi r29,$LaLOOP_END | ||
345 | ADD r3,r3,r3 # Shift in the '1' into div | ||
346 | BRI $LaDIV2 # Div2 | ||
347 | $LaLOOP_END: | ||
348 | BRI $LaRETURN_HERE | ||
349 | +#endif | ||
350 | $LaDiv_By_Zero: | ||
351 | $LaResult_Is_Zero: | ||
352 | OR r3,r0,r0 # set result to 0 | ||
353 | @@ -115,7 +159,7 @@ $LaRETURN_HERE: | ||
354 | LLI r29,r1,0 | ||
355 | LLI r30,r1,8 | ||
356 | LLI r31,r1,16 | ||
357 | - ADDIK r1,r1,24 | ||
358 | + ADDLIK r1,r1,24 | ||
359 | RTSD r15,8 | ||
360 | NOP | ||
361 | #else | ||
362 | diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S | ||
363 | index 1b3070e..91430a6 100644 | ||
364 | --- a/libgcc/config/microblaze/umodsi3.S | ||
365 | +++ b/libgcc/config/microblaze/umodsi3.S | ||
366 | @@ -46,7 +46,7 @@ | ||
367 | __umodsi3: | ||
368 | .frame r1,0,r15 | ||
369 | |||
370 | - addik r1,r1,-24 | ||
371 | + addlik r1,r1,-24 | ||
372 | sli r29,r1,0 | ||
373 | sli r30,r1,8 | ||
374 | sli r31,r1,16 | ||
375 | @@ -59,27 +59,77 @@ __umodsi3: | ||
376 | swi r30,r1,4 | ||
377 | swi r31,r1,8 | ||
378 | #endif | ||
379 | +#ifdef __arch64__ | ||
380 | + BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
381 | + BEAEQId r5,$LaResult_Is_Zero # Result is Zero | ||
382 | +#else | ||
383 | BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error | ||
384 | BEQId r5,$LaResult_Is_Zero # Result is Zero | ||
385 | +#endif | ||
386 | ADDIK r3,r0,0 # Clear div | ||
387 | ADDIK r30,r0,0 # clear mod | ||
388 | ADDIK r29,r0,32 # Initialize the loop count | ||
389 | |||
390 | # Check if r6 and r5 are equal # if yes, return 0 | ||
391 | rsub r18,r5,r6 | ||
392 | - beqi r18,$LaRETURN_HERE | ||
393 | |||
394 | +#ifdef __arch64__ | ||
395 | + beaeqi r18,$LaRETURN_HERE | ||
396 | +#else | ||
397 | + beqi r18,$LaRETURN_HERE | ||
398 | +#endif | ||
399 | # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 | ||
400 | xor r18,r5,r6 | ||
401 | +#ifdef __arch64__ | ||
402 | + beageid r18,16 | ||
403 | + addik r3,r5,0 | ||
404 | + bealti r6,$LaRETURN_HERE | ||
405 | + breai $LCheckr6 | ||
406 | + rsub r18,r5,r6 # MICROBLAZEcmp | ||
407 | + beagti r18,$LaRETURN_HERE | ||
408 | +#else | ||
409 | bgeid r18,16 | ||
410 | addik r3,r5,0 | ||
411 | blti r6,$LaRETURN_HERE | ||
412 | bri $LCheckr6 | ||
413 | rsub r18,r5,r6 # MICROBLAZEcmp | ||
414 | bgti r18,$LaRETURN_HERE | ||
415 | - | ||
416 | +#endif | ||
417 | # If r6 [bit 31] is set, then return result as r5-r6 | ||
418 | $LCheckr6: | ||
419 | +#ifdef __arch64__ | ||
420 | + beagtid r6,$LaDIV0 | ||
421 | + addik r3,r0,0 | ||
422 | + addik r18,r0,0x7fffffff | ||
423 | + and r5,r5,r18 | ||
424 | + and r6,r6,r18 | ||
425 | + breaid $LaRETURN_HERE | ||
426 | + rsub r3,r6,r5 | ||
427 | +# First part: try to find the first '1' in the r5 | ||
428 | +$LaDIV0: | ||
429 | + BEALTI r5,$LaDIV2 | ||
430 | +$LaDIV1: | ||
431 | + ADD r5,r5,r5 # left shift logical r5 | ||
432 | + BEAGEID r5,$LaDIV1 # | ||
433 | + ADDIK r29,r29,-1 | ||
434 | +$LaDIV2: | ||
435 | + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry | ||
436 | + ADDC r3,r3,r3 # Move that bit into the Mod register | ||
437 | + rSUB r31,r6,r3 # Try to subtract (r3 a r6) | ||
438 | + BEALTi r31,$LaMOD_TOO_SMALL | ||
439 | + OR r3,r0,r31 # Move the r31 to mod since the result was positive | ||
440 | + ADDIK r30,r30,1 | ||
441 | +$LaMOD_TOO_SMALL: | ||
442 | + ADDIK r29,r29,-1 | ||
443 | + BEAEQi r29,$LaLOOP_END | ||
444 | + ADD r30,r30,r30 # Shift in the '1' into div | ||
445 | + BREAI $LaDIV2 # Div2 | ||
446 | +$LaLOOP_END: | ||
447 | + BREAI $LaRETURN_HERE | ||
448 | +$LaDiv_By_Zero: | ||
449 | +$LaResult_Is_Zero: | ||
450 | + or r3,r0,r0 # set result to 0 | ||
451 | +#else | ||
452 | bgtid r6,$LaDIV0 | ||
453 | addik r3,r0,0 | ||
454 | addik r18,r0,0x7fffffff | ||
455 | @@ -111,7 +161,7 @@ $LaLOOP_END: | ||
456 | $LaDiv_By_Zero: | ||
457 | $LaResult_Is_Zero: | ||
458 | or r3,r0,r0 # set result to 0 | ||
459 | - | ||
460 | +#endif | ||
461 | #ifdef __arch64__ | ||
462 | $LaRETURN_HERE: | ||
463 | # Restore values of CSRs and that of r3 and the divisor and the dividend | ||
464 | -- | ||
465 | 2.7.4 | ||
466 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch index be4dfad5..be4dfad5 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch new file mode 100644 index 00000000..9f878669 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch | |||
@@ -0,0 +1,479 @@ | |||
1 | From f0332f119c3cbe95886dae77c4b5a9b9907b4b17 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Thu, 18 Apr 2019 16:00:37 +0530 | ||
4 | Subject: [PATCH 60/63] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr | ||
5 | 17 14:11:00 2019 +0530 | ||
6 | |||
7 | [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default | ||
8 | By default MB-64 is generatting barrel-shift instructions. It has been | ||
9 | removed from default. Barrel-shift instructions will be generated only if | ||
10 | barrel-shifter is enabled. Similarly to double instructions as well. | ||
11 | |||
12 | Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> | ||
13 | --- | ||
14 | gcc/config/microblaze/microblaze.c | 2 +- | ||
15 | gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++--- | ||
16 | 2 files changed, 252 insertions(+), 19 deletions(-) | ||
17 | |||
18 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | ||
19 | index 220e03d..5c09452 100644 | ||
20 | --- a/gcc/config/microblaze/microblaze.c | ||
21 | +++ b/gcc/config/microblaze/microblaze.c | ||
22 | @@ -4008,7 +4008,7 @@ microblaze_expand_divide (rtx operands[]) | ||
23 | emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); | ||
24 | |||
25 | if (TARGET_MB_64) { | ||
26 | - emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); | ||
27 | + emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); | ||
28 | emit_insn (gen_adddi3 (regt1, regt1, operands[2])); | ||
29 | } | ||
30 | else { | ||
31 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
32 | index 830ef77..3e7c647 100644 | ||
33 | --- a/gcc/config/microblaze/microblaze.md | ||
34 | +++ b/gcc/config/microblaze/microblaze.md | ||
35 | @@ -547,7 +547,7 @@ | ||
36 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
37 | (plus:DF (match_operand:DF 1 "register_operand" "d") | ||
38 | (match_operand:DF 2 "register_operand" "d")))] | ||
39 | - "TARGET_MB_64" | ||
40 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
41 | "dadd\t%0,%1,%2" | ||
42 | [(set_attr "type" "fadd") | ||
43 | (set_attr "mode" "DF") | ||
44 | @@ -557,7 +557,7 @@ | ||
45 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
46 | (minus:DF (match_operand:DF 1 "register_operand" "d") | ||
47 | (match_operand:DF 2 "register_operand" "d")))] | ||
48 | - "TARGET_MB_64" | ||
49 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
50 | "drsub\t%0,%2,%1" | ||
51 | [(set_attr "type" "frsub") | ||
52 | (set_attr "mode" "DF") | ||
53 | @@ -567,7 +567,7 @@ | ||
54 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
55 | (mult:DF (match_operand:DF 1 "register_operand" "d") | ||
56 | (match_operand:DF 2 "register_operand" "d")))] | ||
57 | - "TARGET_MB_64" | ||
58 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
59 | "dmul\t%0,%1,%2" | ||
60 | [(set_attr "type" "fmul") | ||
61 | (set_attr "mode" "DF") | ||
62 | @@ -577,7 +577,7 @@ | ||
63 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
64 | (div:DF (match_operand:DF 1 "register_operand" "d") | ||
65 | (match_operand:DF 2 "register_operand" "d")))] | ||
66 | - "TARGET_MB_64" | ||
67 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
68 | "ddiv\t%0,%2,%1" | ||
69 | [(set_attr "type" "fdiv") | ||
70 | (set_attr "mode" "DF") | ||
71 | @@ -587,7 +587,7 @@ | ||
72 | (define_insn "sqrtdf2" | ||
73 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
74 | (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] | ||
75 | - "TARGET_MB_64" | ||
76 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
77 | "dsqrt\t%0,%1" | ||
78 | [(set_attr "type" "fsqrt") | ||
79 | (set_attr "mode" "DF") | ||
80 | @@ -596,7 +596,7 @@ | ||
81 | (define_insn "floatdidf2" | ||
82 | [(set (match_operand:DF 0 "register_operand" "=d") | ||
83 | (float:DF (match_operand:DI 1 "register_operand" "d")))] | ||
84 | - "TARGET_MB_64" | ||
85 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
86 | "dbl\t%0,%1" | ||
87 | [(set_attr "type" "fcvt") | ||
88 | (set_attr "mode" "DF") | ||
89 | @@ -605,7 +605,7 @@ | ||
90 | (define_insn "fix_truncdfdi2" | ||
91 | [(set (match_operand:DI 0 "register_operand" "=d") | ||
92 | (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] | ||
93 | - "TARGET_MB_64" | ||
94 | + "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" | ||
95 | "dlong\t%0,%1" | ||
96 | [(set_attr "type" "fcvt") | ||
97 | (set_attr "mode" "DI") | ||
98 | @@ -1301,6 +1301,34 @@ | ||
99 | (set_attr "mode" "DI") | ||
100 | (set_attr "length" "4")]) | ||
101 | |||
102 | +(define_insn "*movdi_internal2_bshift" | ||
103 | + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") | ||
104 | + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] | ||
105 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
106 | + { | ||
107 | + switch (which_alternative) | ||
108 | + { | ||
109 | + case 0: | ||
110 | + return "addlk\t%0,%1,r0"; | ||
111 | + case 1: | ||
112 | + case 2: | ||
113 | + if (GET_CODE (operands[1]) == CONST_INT && | ||
114 | + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) | ||
115 | + return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
116 | + else | ||
117 | + return "addlik\t%0,r0,%1"; | ||
118 | + case 3: | ||
119 | + case 4: | ||
120 | + return "ll%i1\t%0,%1"; | ||
121 | + case 5: | ||
122 | + case 6: | ||
123 | + return "sl%i0\t%z1,%0"; | ||
124 | + } | ||
125 | + } | ||
126 | + [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") | ||
127 | + (set_attr "mode" "DI") | ||
128 | + (set_attr "length" "4,4,12,4,8,4,8")]) | ||
129 | + | ||
130 | (define_insn "*movdi_internal2" | ||
131 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") | ||
132 | (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] | ||
133 | @@ -1314,7 +1342,15 @@ | ||
134 | case 2: | ||
135 | if (GET_CODE (operands[1]) == CONST_INT && | ||
136 | (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) | ||
137 | - return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
138 | + { | ||
139 | + operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
140 | + output_asm_insn ("addlik\t%0,r0,%h1", operands); | ||
141 | + output_asm_insn ("addlik\t%2,r0,32", operands); | ||
142 | + output_asm_insn ("addlik\t%2,%2,-1", operands); | ||
143 | + output_asm_insn ("beaneid\t%2,.-8", operands); | ||
144 | + output_asm_insn ("addlk\t%0,%0,%0", operands); | ||
145 | + return "addlik\t%0,%0,%j1 #li => la"; | ||
146 | + } | ||
147 | else | ||
148 | return "addlik\t%0,r0,%1"; | ||
149 | case 3: | ||
150 | @@ -1388,7 +1424,7 @@ | ||
151 | (define_insn "movdi_long_int" | ||
152 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | ||
153 | (match_operand:DI 1 "general_operand" "i"))] | ||
154 | - "TARGET_MB_64" | ||
155 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
156 | "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; | ||
157 | [(set_attr "type" "no_delay_arith") | ||
158 | (set_attr "mode" "DI") | ||
159 | @@ -1655,6 +1691,33 @@ | ||
160 | ;; movdf_internal | ||
161 | ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT | ||
162 | ;; | ||
163 | +(define_insn "*movdf_internal_64_bshift" | ||
164 | + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") | ||
165 | + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] | ||
166 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
167 | + { | ||
168 | + switch (which_alternative) | ||
169 | + { | ||
170 | + case 0: | ||
171 | + return "addlk\t%0,%1,r0"; | ||
172 | + case 1: | ||
173 | + return "addlk\t%0,r0,r0"; | ||
174 | + case 2: | ||
175 | + case 4: | ||
176 | + return "ll%i1\t%0,%1"; | ||
177 | + case 3: | ||
178 | + { | ||
179 | + return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; | ||
180 | + } | ||
181 | + case 5: | ||
182 | + return "sl%i0\t%1,%0"; | ||
183 | + } | ||
184 | + gcc_unreachable (); | ||
185 | + } | ||
186 | + [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") | ||
187 | + (set_attr "mode" "DF") | ||
188 | + (set_attr "length" "4,4,4,16,4,4")]) | ||
189 | + | ||
190 | (define_insn "*movdf_internal_64" | ||
191 | [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") | ||
192 | (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] | ||
193 | @@ -1671,7 +1734,13 @@ | ||
194 | return "ll%i1\t%0,%1"; | ||
195 | case 3: | ||
196 | { | ||
197 | - return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; | ||
198 | + operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
199 | + output_asm_insn ("addlik\t%0,r0,%h1", operands); | ||
200 | + output_asm_insn ("addlik\t%2,r0,32", operands); | ||
201 | + output_asm_insn ("addlik\t%2,%2,-1", operands); | ||
202 | + output_asm_insn ("beaneid\t%2,.-8", operands); | ||
203 | + output_asm_insn ("addlk\t%0,%0,%0", operands); | ||
204 | + return "addlik\t%0,%0,%j1 #li => la"; | ||
205 | } | ||
206 | case 5: | ||
207 | return "sl%i0\t%1,%0"; | ||
208 | @@ -1791,11 +1860,21 @@ | ||
209 | "TARGET_MB_64" | ||
210 | { | ||
211 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
212 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
213 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
214 | { | ||
215 | emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); | ||
216 | DONE; | ||
217 | } | ||
218 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
219 | + { | ||
220 | + emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); | ||
221 | + DONE; | ||
222 | + } | ||
223 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
224 | + { | ||
225 | + emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); | ||
226 | + DONE; | ||
227 | + } | ||
228 | else | ||
229 | FAIL; | ||
230 | } | ||
231 | @@ -1805,7 +1884,7 @@ else | ||
232 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
233 | (ashift:DI (match_operand:DI 1 "register_operand" "d,d") | ||
234 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
235 | - "TARGET_MB_64" | ||
236 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
237 | "@ | ||
238 | bsllli\t%0,%1,%2 | ||
239 | bslll\t%0,%1,%2" | ||
240 | @@ -1813,6 +1892,51 @@ else | ||
241 | (set_attr "mode" "DI,DI") | ||
242 | (set_attr "length" "4,4")] | ||
243 | ) | ||
244 | + | ||
245 | +(define_insn "ashldi3_const" | ||
246 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
247 | + (ashift:DI (match_operand:DI 1 "register_operand" "d") | ||
248 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
249 | + "TARGET_MB_64" | ||
250 | + { | ||
251 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
252 | + | ||
253 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
254 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
255 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
256 | + | ||
257 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
258 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
259 | + return "addlk\t%0,%0,%0"; | ||
260 | + } | ||
261 | + [(set_attr "type" "multi") | ||
262 | + (set_attr "mode" "DI") | ||
263 | + (set_attr "length" "20")] | ||
264 | +) | ||
265 | + | ||
266 | +(define_insn "ashldi3_reg" | ||
267 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
268 | + (ashift:DI (match_operand:DI 1 "register_operand" "d") | ||
269 | + (match_operand:DI 2 "register_operand" "d")))] | ||
270 | + "TARGET_MB_64" | ||
271 | + { | ||
272 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
273 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
274 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
275 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
276 | + /* Exit the loop if zero shift. */ | ||
277 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
278 | + /* Emit the loop. */ | ||
279 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
280 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
281 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
282 | + return "addlk\t%0,%0,%0"; | ||
283 | + } | ||
284 | + [(set_attr "type" "multi") | ||
285 | + (set_attr "mode" "DI") | ||
286 | + (set_attr "length" "28")] | ||
287 | +) | ||
288 | + | ||
289 | ;; The following patterns apply when there is no barrel shifter present | ||
290 | |||
291 | (define_insn "*ashlsi3_with_mul_delay" | ||
292 | @@ -1946,11 +2070,21 @@ else | ||
293 | "TARGET_MB_64" | ||
294 | { | ||
295 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
296 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
297 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
298 | { | ||
299 | emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); | ||
300 | DONE; | ||
301 | } | ||
302 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
303 | + { | ||
304 | + emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); | ||
305 | + DONE; | ||
306 | + } | ||
307 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
308 | + { | ||
309 | + emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); | ||
310 | + DONE; | ||
311 | + } | ||
312 | else | ||
313 | FAIL; | ||
314 | } | ||
315 | @@ -1960,7 +2094,7 @@ else | ||
316 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
317 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | ||
318 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
319 | - "TARGET_MB_64" | ||
320 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
321 | "@ | ||
322 | bslrai\t%0,%1,%2 | ||
323 | bslra\t%0,%1,%2" | ||
324 | @@ -1968,6 +2102,51 @@ else | ||
325 | (set_attr "mode" "DI,DI") | ||
326 | (set_attr "length" "4,4")] | ||
327 | ) | ||
328 | + | ||
329 | +(define_insn "ashrdi3_const" | ||
330 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
331 | + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
332 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
333 | + "TARGET_MB_64" | ||
334 | + { | ||
335 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
336 | + | ||
337 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
338 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
339 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
340 | + | ||
341 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
342 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
343 | + return "srla\t%0,%0"; | ||
344 | + } | ||
345 | + [(set_attr "type" "arith") | ||
346 | + (set_attr "mode" "DI") | ||
347 | + (set_attr "length" "20")] | ||
348 | +) | ||
349 | + | ||
350 | +(define_insn "ashrdi3_reg" | ||
351 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
352 | + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
353 | + (match_operand:DI 2 "register_operand" "d")))] | ||
354 | + "TARGET_MB_64" | ||
355 | + { | ||
356 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
357 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
358 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
359 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
360 | + /* Exit the loop if zero shift. */ | ||
361 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
362 | + /* Emit the loop. */ | ||
363 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
364 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
365 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
366 | + return "srla\t%0,%0"; | ||
367 | + } | ||
368 | + [(set_attr "type" "multi") | ||
369 | + (set_attr "mode" "DI") | ||
370 | + (set_attr "length" "28")] | ||
371 | +) | ||
372 | + | ||
373 | (define_expand "ashrsi3" | ||
374 | [(set (match_operand:SI 0 "register_operand" "=&d") | ||
375 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
376 | @@ -2085,11 +2264,21 @@ else | ||
377 | "TARGET_MB_64" | ||
378 | { | ||
379 | ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
380 | -if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) | ||
381 | +if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) | ||
382 | { | ||
383 | emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); | ||
384 | DONE; | ||
385 | } | ||
386 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) | ||
387 | + { | ||
388 | + emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); | ||
389 | + DONE; | ||
390 | + } | ||
391 | +else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) | ||
392 | + { | ||
393 | + emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); | ||
394 | + DONE; | ||
395 | + } | ||
396 | else | ||
397 | FAIL; | ||
398 | } | ||
399 | @@ -2099,7 +2288,7 @@ else | ||
400 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
401 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | ||
402 | (match_operand:DI 2 "arith_operand" "I,d")))] | ||
403 | - "TARGET_MB_64" | ||
404 | + "TARGET_MB_64 && TARGET_BARREL_SHIFT" | ||
405 | "@ | ||
406 | bslrli\t%0,%1,%2 | ||
407 | bslrl\t%0,%1,%2" | ||
408 | @@ -2108,6 +2297,50 @@ else | ||
409 | (set_attr "length" "4,4")] | ||
410 | ) | ||
411 | |||
412 | +(define_insn "lshrdi3_const" | ||
413 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
414 | + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
415 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
416 | + "TARGET_MB_64" | ||
417 | + { | ||
418 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
419 | + | ||
420 | + output_asm_insn ("orli\t%3,r0,%2", operands); | ||
421 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
422 | + output_asm_insn ("addlk\t%0,%1,r0", operands); | ||
423 | + | ||
424 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
425 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
426 | + return "srll\t%0,%0"; | ||
427 | + } | ||
428 | + [(set_attr "type" "multi") | ||
429 | + (set_attr "mode" "DI") | ||
430 | + (set_attr "length" "20")] | ||
431 | +) | ||
432 | + | ||
433 | +(define_insn "lshrdi3_reg" | ||
434 | + [(set (match_operand:DI 0 "register_operand" "=&d") | ||
435 | + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | ||
436 | + (match_operand:DI 2 "register_operand" "d")))] | ||
437 | + "TARGET_MB_64" | ||
438 | + { | ||
439 | + operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); | ||
440 | + output_asm_insn ("andli\t%3,%2,31", operands); | ||
441 | + if (REGNO (operands[0]) != REGNO (operands[1])) | ||
442 | + output_asm_insn ("addlk\t%0,r0,%1", operands); | ||
443 | + /* Exit the loop if zero shift. */ | ||
444 | + output_asm_insn ("beaeqid\t%3,.+24", operands); | ||
445 | + /* Emit the loop. */ | ||
446 | + output_asm_insn ("addlk\t%0,%0,r0", operands); | ||
447 | + output_asm_insn ("addlik\t%3,%3,-1", operands); | ||
448 | + output_asm_insn ("beaneid\t%3,.-8", operands); | ||
449 | + return "srll\t%0,%0"; | ||
450 | + } | ||
451 | + [(set_attr "type" "multi") | ||
452 | + (set_attr "mode" "SI") | ||
453 | + (set_attr "length" "28")] | ||
454 | +) | ||
455 | + | ||
456 | (define_expand "lshrsi3" | ||
457 | [(set (match_operand:SI 0 "register_operand" "=&d") | ||
458 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | ||
459 | @@ -2235,7 +2468,7 @@ else | ||
460 | (eq:DI | ||
461 | (match_operand:DI 1 "register_operand" "d") | ||
462 | (match_operand:DI 2 "register_operand" "d")))] | ||
463 | - "TARGET_MB_64" | ||
464 | + "TARGET_MB_64 && TARGET_PATTERN_COMPARE" | ||
465 | "pcmpleq\t%0,%1,%2" | ||
466 | [(set_attr "type" "arith") | ||
467 | (set_attr "mode" "DI") | ||
468 | @@ -2247,7 +2480,7 @@ else | ||
469 | (ne:DI | ||
470 | (match_operand:DI 1 "register_operand" "d") | ||
471 | (match_operand:DI 2 "register_operand" "d")))] | ||
472 | - "TARGET_MB_64" | ||
473 | + "TARGET_MB_64 && TARGET_PATTERN_COMPARE" | ||
474 | "pcmplne\t%0,%1,%2" | ||
475 | [(set_attr "type" "arith") | ||
476 | (set_attr "mode" "DI") | ||
477 | -- | ||
478 | 2.7.4 | ||
479 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch index 1548faad..1548faad 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch index 690bc727..690bc727 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch new file mode 100644 index 00000000..d3ed669c --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | |||
@@ -0,0 +1,41 @@ | |||
1 | From 11766e4f7aaad3f217944079335c71525b72201c Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Wed, 8 May 2019 14:12:03 +0530 | ||
4 | Subject: [PATCH 61/63] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and | ||
5 | disable fivopts by default | ||
6 | |||
7 | Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. | ||
8 | |||
9 | * gcc/common/config/microblaze/microblaze-common.c | ||
10 | (microblaze_option_optimization_table): Disable fivopts by default. | ||
11 | |||
12 | Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com> | ||
13 | --- | ||
14 | gcc/common/config/microblaze/microblaze-common.c | 6 ++++-- | ||
15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c | ||
18 | index 9b6ef21..3cae2a6 100644 | ||
19 | --- a/gcc/common/config/microblaze/microblaze-common.c | ||
20 | +++ b/gcc/common/config/microblaze/microblaze-common.c | ||
21 | @@ -27,13 +27,15 @@ | ||
22 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ | ||
23 | static const struct default_options microblaze_option_optimization_table[] = | ||
24 | { | ||
25 | - /* Turn off ivopts by default. It messes up cse. */ | ||
26 | + /* Turn off ivopts by default. It messes up cse. | ||
27 | + { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ | ||
28 | { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, | ||
29 | - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | ||
30 | { OPT_LEVELS_NONE, 0, NULL, 0 } | ||
31 | }; | ||
32 | |||
33 | #undef TARGET_DEFAULT_TARGET_FLAGS | ||
34 | #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | ||
35 | |||
36 | +#undef TARGET_OPTION_OPTIMIZATION_TABLE | ||
37 | +#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table | ||
38 | struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; | ||
39 | -- | ||
40 | 2.7.4 | ||
41 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch new file mode 100644 index 00000000..ca1a2b9f --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch | |||
@@ -0,0 +1,107 @@ | |||
1 | From bb65903ab6293a47d154764a585f6c53b5fcf853 Mon Sep 17 00:00:00 2001 | ||
2 | From: Nagaraju <nmekala@xilinx.com> | ||
3 | Date: Fri, 23 Aug 2019 16:16:53 +0530 | ||
4 | Subject: [PATCH 62/63] Added new MB-64 single register arithmetic instructions | ||
5 | |||
6 | --- | ||
7 | gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++++++++++ | ||
8 | 1 file changed, 56 insertions(+) | ||
9 | |||
10 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
11 | index 3e7c647..4d40cc5 100644 | ||
12 | --- a/gcc/config/microblaze/microblaze.md | ||
13 | +++ b/gcc/config/microblaze/microblaze.md | ||
14 | @@ -654,6 +654,18 @@ | ||
15 | } | ||
16 | }) | ||
17 | |||
18 | +(define_insn "adddi3_int" | ||
19 | + [(set (match_operand:DI 0 "register_operand" "=d") | ||
20 | + (plus:DI (match_operand:DI 1 "register_operand" "%0") | ||
21 | + (match_operand:DI 2 "immediate_operand" "I")))] | ||
22 | + "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" | ||
23 | + "@ | ||
24 | + addlik\t%0,%2" | ||
25 | + [(set_attr "type" "darith") | ||
26 | + (set_attr "mode" "DI") | ||
27 | + (set_attr "length" "4")] | ||
28 | +) | ||
29 | + | ||
30 | (define_insn "*adddi3_long" | ||
31 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
32 | (plus:DI (match_operand:DI 1 "register_operand" "%d,d") | ||
33 | @@ -719,6 +731,18 @@ | ||
34 | { | ||
35 | }") | ||
36 | |||
37 | +(define_insn "subdi316imm" | ||
38 | + [(set (match_operand:DI 0 "register_operand" "=d") | ||
39 | + (minus:DI (match_operand:DI 1 "register_operand" "d") | ||
40 | + (match_operand:DI 2 "arith_operand" "K")))] | ||
41 | + "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))" | ||
42 | + "@ | ||
43 | + addlik\t%0,-%2" | ||
44 | + [(set_attr "type" "darith") | ||
45 | + (set_attr "mode" "DI") | ||
46 | + (set_attr "length" "4")]) | ||
47 | + | ||
48 | + | ||
49 | (define_insn "subsidi3" | ||
50 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | ||
51 | (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") | ||
52 | @@ -1015,6 +1039,17 @@ | ||
53 | ;; Logical | ||
54 | ;;---------------------------------------------------------------- | ||
55 | |||
56 | +(define_insn "anddi3imm16" | ||
57 | + [(set (match_operand:DI 0 "register_operand" "=d") | ||
58 | + (and:DI (match_operand:DI 1 "arith_operand" "%0") | ||
59 | + (match_operand:DI 2 "arith_operand" "K")))] | ||
60 | + "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" | ||
61 | + "@ | ||
62 | + andli\t%0,%2" | ||
63 | + [(set_attr "type" "darith") | ||
64 | + (set_attr "mode" "DI") | ||
65 | + (set_attr "length" "4")]) | ||
66 | + | ||
67 | (define_insn "anddi3" | ||
68 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | ||
69 | (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") | ||
70 | @@ -1042,6 +1077,16 @@ | ||
71 | (set_attr "mode" "SI,SI,SI,SI") | ||
72 | (set_attr "length" "4,8,8,8")]) | ||
73 | |||
74 | +(define_insn "iordi3imm16" | ||
75 | + [(set (match_operand:DI 0 "register_operand" "=d") | ||
76 | + (ior:DI (match_operand:DI 1 "arith_operand" "%0") | ||
77 | + (match_operand:DI 2 "arith_operand" "K")))] | ||
78 | + "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" | ||
79 | + "@ | ||
80 | + orli\t%0,%2" | ||
81 | + [(set_attr "type" "darith") | ||
82 | + (set_attr "mode" "DI") | ||
83 | + (set_attr "length" "4")]) | ||
84 | |||
85 | (define_insn "iordi3" | ||
86 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
87 | @@ -1069,6 +1114,17 @@ | ||
88 | (set_attr "mode" "SI,SI,SI,SI") | ||
89 | (set_attr "length" "4,8,8,8")]) | ||
90 | |||
91 | +(define_insn "xordi3imm16" | ||
92 | + [(set (match_operand:DI 0 "register_operand" "=d") | ||
93 | + (xor:DI (match_operand:DI 1 "arith_operand" "%0") | ||
94 | + (match_operand:DI 2 "arith_operand" "K")))] | ||
95 | + "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)" | ||
96 | + "@ | ||
97 | + xorli\t%0,%2" | ||
98 | + [(set_attr "type" "darith") | ||
99 | + (set_attr "mode" "DI") | ||
100 | + (set_attr "length" "4")]) | ||
101 | + | ||
102 | (define_insn "xordi3" | ||
103 | [(set (match_operand:DI 0 "register_operand" "=d,d") | ||
104 | (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") | ||
105 | -- | ||
106 | 2.7.4 | ||
107 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch index e7dfa89c..e7dfa89c 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch new file mode 100644 index 00000000..edf6a0f3 --- /dev/null +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch | |||
@@ -0,0 +1,44 @@ | |||
1 | From d4b23a1dd0564bcf67b5b88a68d62eb49bdab15d Mon Sep 17 00:00:00 2001 | ||
2 | From: Mahesh Bodapati <mbodapat@xilinx.com> | ||
3 | Date: Mon, 26 Aug 2019 15:55:22 +0530 | ||
4 | Subject: [PATCH 63/63] [Patch,MicroBlaze] : Added support for 64 bit Immediate | ||
5 | values. | ||
6 | |||
7 | --- | ||
8 | gcc/config/microblaze/constraints.md | 4 ++-- | ||
9 | gcc/config/microblaze/microblaze.md | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md | ||
13 | index 9a5aa6b..e87a90f 100644 | ||
14 | --- a/gcc/config/microblaze/constraints.md | ||
15 | +++ b/gcc/config/microblaze/constraints.md | ||
16 | @@ -53,9 +53,9 @@ | ||
17 | (match_test "ival > 0 && ival < 0x10000"))) | ||
18 | |||
19 | (define_constraint "K" | ||
20 | - "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." | ||
21 | + "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)." | ||
22 | (and (match_code "const_int") | ||
23 | - (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) | ||
24 | + (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807"))) | ||
25 | |||
26 | ;; Define floating point constraints | ||
27 | |||
28 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
29 | index 4d40cc5..6e74503 100644 | ||
30 | --- a/gcc/config/microblaze/microblaze.md | ||
31 | +++ b/gcc/config/microblaze/microblaze.md | ||
32 | @@ -1334,8 +1334,7 @@ | ||
33 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") | ||
34 | (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] | ||
35 | "TARGET_MB_64 && (register_operand (operands[0], DImode) && | ||
36 | - (GET_CODE (operands[1]) == CONST_INT && | ||
37 | - (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" | ||
38 | + (GET_CODE (operands[1]) == CONST_INT))" | ||
39 | "@ | ||
40 | addlk\t%0,r0,r0\t | ||
41 | addlik\t%0,r0,%1\t #N1 %X1 | ||
42 | -- | ||
43 | 2.7.4 | ||
44 | |||
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend index d6a81912..f9a87dfb 100644 --- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend +++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend | |||
@@ -1,7 +1,7 @@ | |||
1 | # Add MicroBlaze Patches (only when using MicroBlaze) | 1 | # Add MicroBlaze Patches (only when using MicroBlaze) |
2 | FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-8:" | 2 | FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-9:" |
3 | SRC_URI_append_microblaze = " \ | 3 | SRC_URI_append_microblaze = " \ |
4 | file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ | 4 | file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ |
5 | file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ | 5 | file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ |
6 | file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \ | 6 | file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \ |
7 | file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ | 7 | file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ |
@@ -56,10 +56,12 @@ file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ | |||
56 | file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ | 56 | file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ |
57 | file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ | 57 | file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ |
58 | file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \ | 58 | file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \ |
59 | file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ | 59 | file://0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ |
60 | file://0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ | 60 | file://0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ |
61 | file://0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \ | 61 | file://0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \ |
62 | file://0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ | 62 | file://0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ |
63 | file://0061-Author-Nagaraju-nmekala-xilinx.com.patch \ | 63 | file://0060-Author-Nagaraju-nmekala-xilinx.com.patch \ |
64 | file://0055-microblaze_linker_script_xilinx_ld.patch \ | 64 | file://0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \ |
65 | file://0062-Added-new-MB-64-single-register-arithmetic-instructi.patch \ | ||
66 | file://0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \ | ||
65 | " | 67 | " |
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb index 3c13c697..4fe82bbe 100644 --- a/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb +++ b/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb | |||
@@ -5,14 +5,13 @@ LICENSE = "GPLv2" | |||
5 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" | 5 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a" |
6 | 6 | ||
7 | XILINX_VCU_VERSION = "1.0.0" | 7 | XILINX_VCU_VERSION = "1.0.0" |
8 | XILINX_RELEASE_VERSION = "v2019.1" | ||
9 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" | 8 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" |
10 | 9 | ||
11 | S = "${WORKDIR}/git" | 10 | S = "${WORKDIR}/git" |
12 | 11 | ||
13 | BRANCH ?= "master-rel-2019.1" | 12 | BRANCH ?= "release-2019.2" |
14 | REPO ?= "git://github.com/xilinx/vcu-modules.git;protocol=https" | 13 | REPO ?= "git://github.com/xilinx/vcu-modules.git;protocol=https" |
15 | SRCREV ?= "13a8e5b3f614d94081481a808aa8d4bd00b26d76" | 14 | SRCREV ?= "d4b46f2ee10e5d13609ca982d8d8bae662468837" |
16 | 15 | ||
17 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | 16 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" |
18 | SRC_URI = "${REPO};${BRANCHARG}" | 17 | SRC_URI = "${REPO};${BRANCHARG}" |
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb index 25bbffe9..dcef6610 100644 --- a/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb +++ b/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb | |||
@@ -4,12 +4,11 @@ LICENSE = "Proprietary" | |||
4 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" | 4 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" |
5 | 5 | ||
6 | XILINX_VCU_VERSION = "1.0.0" | 6 | XILINX_VCU_VERSION = "1.0.0" |
7 | XILINX_RELEASE_VERSION = "v2019.1" | ||
8 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" | 7 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" |
9 | 8 | ||
10 | BRANCH ?= "master-rel-2019.1" | 9 | BRANCH ?= "release-2019.2" |
11 | REPO ?= "git://github.com/xilinx/vcu-omx-il.git;protocol=https" | 10 | REPO ?= "git://github.com/xilinx/vcu-omx-il.git;protocol=https" |
12 | SRCREV ?= "b93cec02cd5da223fa965073dce130a08ffd6419" | 11 | SRCREV ?= "9bbb40e3ceddd9e166d1d97aa4ac380459166344" |
13 | 12 | ||
14 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | 13 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" |
15 | SRC_URI = "${REPO};${BRANCHARG}" | 14 | SRC_URI = "${REPO};${BRANCHARG}" |
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb index 8f8c0ef2..8b15fac7 100644 --- a/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb +++ b/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb | |||
@@ -4,12 +4,11 @@ LICENSE = "Proprietary" | |||
4 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" | 4 | LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493" |
5 | 5 | ||
6 | XILINX_VCU_VERSION = "1.0.0" | 6 | XILINX_VCU_VERSION = "1.0.0" |
7 | XILINX_RELEASE_VERSION = "v2019.1" | ||
8 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" | 7 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" |
9 | 8 | ||
10 | BRANCH ?= "master-rel-2019.1" | 9 | BRANCH ?= "release-2019.2" |
11 | REPO ?= "git://github.com/xilinx/vcu-ctrl-sw.git;protocol=https" | 10 | REPO ?= "git://github.com/xilinx/vcu-ctrl-sw.git;protocol=https" |
12 | SRCREV ?= "32b7be620987283f62e4469185da81dddad1071c" | 11 | SRCREV ?= "f3001b44eeaf770cbd9f95d2cfd0b02d3f65b2d3" |
13 | 12 | ||
14 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | 13 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" |
15 | SRC_URI = "${REPO};${BRANCHARG}" | 14 | SRC_URI = "${REPO};${BRANCHARG}" |
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb index 28bd0d37..9a617ef5 100644 --- a/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb +++ b/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb | |||
@@ -4,14 +4,13 @@ LICENSE = "Proprietary" | |||
4 | LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" | 4 | LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498" |
5 | 5 | ||
6 | XILINX_VCU_VERSION = "1.0.0" | 6 | XILINX_VCU_VERSION = "1.0.0" |
7 | XILINX_RELEASE_VERSION = "v2019.1" | ||
8 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" | 7 | PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}" |
9 | 8 | ||
10 | S = "${WORKDIR}/git" | 9 | S = "${WORKDIR}/git" |
11 | 10 | ||
12 | BRANCH ?= "master-rel-2019.1" | 11 | BRANCH ?= "release-2019.2" |
13 | REPO ?= "git://github.com/xilinx/vcu-firmware.git;protocol=https" | 12 | REPO ?= "git://github.com/xilinx/vcu-firmware.git;protocol=https" |
14 | SRCREV ?= "4078b74d16e5eccca5ae3132c3877d3aff7fb168" | 13 | SRCREV ?= "29ab982965b797b1c9b567faba47378578398f4a" |
15 | 14 | ||
16 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | 15 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" |
17 | SRC_URI = "${REPO};${BRANCHARG}" | 16 | SRC_URI = "${REPO};${BRANCHARG}" |
diff --git a/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb index 4bb41b7d..28992708 100644 --- a/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb +++ b/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb | |||
@@ -3,14 +3,18 @@ DESCRIPTION = "Xilinx Runtime User Space Libraries and headers" | |||
3 | 3 | ||
4 | LICENSE = "GPLv2 & Apache-2.0" | 4 | LICENSE = "GPLv2 & Apache-2.0" |
5 | LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSE;md5=fa343562af4b9b922b8d7fe7b0b6d000 \ | 5 | LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSE;md5=fa343562af4b9b922b8d7fe7b0b6d000 \ |
6 | file://runtime_src/driver/xclng/drm/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ | 6 | file://runtime_src/core/edge/drm/zocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ |
7 | file://runtime_src/driver/xclng/xrt/user_gem/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ | 7 | file://runtime_src/core/pcie/driver/linux/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ |
8 | file://runtime_src/driver/xclng/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87" | 8 | file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ |
9 | file://runtime_src/core/pcie/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 " | ||
9 | 10 | ||
10 | SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https;nobranch=1" | 11 | BRANCH ?= "2019.2" |
12 | REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" | ||
13 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | ||
14 | SRC_URI = "${REPO};${BRANCHARG}" | ||
11 | 15 | ||
12 | PV = "2.2.0+git${SRCPV}" | 16 | PV = "2.2.0+git${SRCPV}" |
13 | SRCREV = "da87ac894a037d7e11c0496361458efed4bab438" | 17 | SRCREV = "7e3540d2707443d8c824669ef4272b33ce2f9ba4" |
14 | 18 | ||
15 | S = "${WORKDIR}/git/src" | 19 | S = "${WORKDIR}/git/src" |
16 | 20 | ||
diff --git a/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb index b47f45fd..3d1972d4 100644 --- a/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb +++ b/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb | |||
@@ -4,10 +4,13 @@ DESCRIPTION = "Xilinx Runtime driver module provides memory management and compu | |||
4 | LICENSE = "GPLv2" | 4 | LICENSE = "GPLv2" |
5 | LIC_FILES_CHKSUM = "file://LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263" | 5 | LIC_FILES_CHKSUM = "file://LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263" |
6 | 6 | ||
7 | SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https" | 7 | BRANCH ?= "2019.2" |
8 | REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https" | ||
9 | BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" | ||
10 | SRC_URI = "${REPO};${BRANCHARG}" | ||
8 | 11 | ||
9 | PV = "2.2.0+git${SRCPV}" | 12 | PV = "2.2.0+git${SRCPV}" |
10 | SRCREV = "da87ac894a037d7e11c0496361458efed4bab438" | 13 | SRCREV = "7e3540d2707443d8c824669ef4272b33ce2f9ba4" |
11 | 14 | ||
12 | S = "${WORKDIR}/git/src/runtime_src/driver/zynq/drm/zocl" | 15 | S = "${WORKDIR}/git/src/runtime_src/driver/zynq/drm/zocl" |
13 | 16 | ||
diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf index 942925eb..93a4c69b 100644 --- a/meta-xilinx-contrib/conf/layer.conf +++ b/meta-xilinx-contrib/conf/layer.conf | |||
@@ -12,5 +12,6 @@ BBFILE_PRIORITY_xilinx-contrib = "5" | |||
12 | LAYERDEPENDS_xilinx-contrib = "core" | 12 | LAYERDEPENDS_xilinx-contrib = "core" |
13 | LAYERDEPENDS_xilinx-contrib = "xilinx" | 13 | LAYERDEPENDS_xilinx-contrib = "xilinx" |
14 | 14 | ||
15 | LAYERSERIES_COMPAT_xilinx-contrib = "warrior" | 15 | LAYERSERIES_COMPAT_xilinx-contrib = "zeus" |
16 | 16 | ||
17 | XILINX_RELEASE_VERSION = "v2019.2" | ||
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch index 660bc218..660bc218 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch | |||
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch index 9b6229db..9b6229db 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch | |||
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch index a98d84c5..a98d84c5 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch | |||
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg index f71e53ab..f71e53ab 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg | |||
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend index 535fbb26..535fbb26 100644 --- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend +++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend | |||
diff --git a/meta-xilinx-standalone/conf/layer.conf b/meta-xilinx-standalone/conf/layer.conf index 16bfb74a..db3c2853 100644 --- a/meta-xilinx-standalone/conf/layer.conf +++ b/meta-xilinx-standalone/conf/layer.conf | |||
@@ -11,4 +11,5 @@ BBFILE_PRIORITY_xilinx-standalone = "5" | |||
11 | 11 | ||
12 | LAYERDEPENDS_xilinx-standalone = "core xilinx" | 12 | LAYERDEPENDS_xilinx-standalone = "core xilinx" |
13 | 13 | ||
14 | LAYERSERIES_COMPAT_xilinx-standalone = "warrior" | 14 | LAYERSERIES_COMPAT_xilinx-standalone = "zeus" |
15 | XILINX_RELEASE_VERSION = "v2019.2" | ||
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend index fc4db884..fc4db884 100644 --- a/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend +++ b/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend | |||
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend index e5249ab0..e5249ab0 100644 --- a/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend +++ b/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend | |||
diff --git a/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb b/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb index 030de054..3d0142f8 100644 --- a/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb +++ b/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb | |||
@@ -1,10 +1,10 @@ | |||
1 | inherit deploy | 1 | inherit deploy |
2 | 2 | ||
3 | LICENSE = "Proprietary" | 3 | LICENSE = "Proprietary" |
4 | LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=e9b6d01d45faccfbf05d8caea53f0a35" | 4 | LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=39ab6ab638f4d1836ba994ec6852de94" |
5 | 5 | ||
6 | XILINX_RELEASE_VERSION = "v2019.1" | 6 | XILINX_RELEASE_VERSION = "v2019.2" |
7 | SRCREV = "26c14d9861010a0e3a55c73fb79efdb816eb42ca" | 7 | SRCREV = "e8db5fb118229fdc621e0ec7848641a23bf60998" |
8 | PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}" | 8 | PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}" |
9 | 9 | ||
10 | SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1" | 10 | SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1" |