From 2f7eeaadc25fc6e5e9deb9ebe5145e15bd631d1c Mon Sep 17 00:00:00 2001
From: Jaewon Lee <jaewon.lee@xilinx.com>
Date: Wed, 27 Mar 2019 10:50:40 -0700
Subject: Update recipes for 2019.2 release

Update u-boot, kernel, ATF, QEMU, pmu-firmware, multimedia recipes for
2019.2 release.

The patch also upgrades gcc microblaze, newlib and libgloss versions.

Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
---
 meta-xilinx-bsp/conf/layer.conf                    |    3 +-
 .../arm-trusted-firmware/arm-trusted-firmware.inc  |    5 +-
 .../arm-trusted-firmware_2019.1.bb                 |    7 -
 .../arm-trusted-firmware_2019.2.bb                 |    6 +
 .../reference-design/kc705-bitstream_2019.1.bb     |   48 -
 .../reference-design/kc705-bitstream_2019.2.bb     |   48 +
 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc |    1 +
 ...aze-kc705-Convert-microblaze-generic-to-k.patch | 1133 ---------
 ...aze-kc705-Convert-microblaze-generic-to-k.patch | 1133 +++++++++
 .../recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb       |   32 -
 .../recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb       |   31 +
 ....29.9000-6.fc31.x86_64-package-finally-in.patch |  105 +
 .../qemu/qemu-devicetrees_2019.1.bb                |    6 -
 .../qemu/qemu-devicetrees_2019.2.bb                |    4 +
 .../recipes-devtools/qemu/qemu-xilinx-native.inc   |    4 +-
 .../qemu/qemu-xilinx-native_2019.1.bb              |    7 -
 .../qemu/qemu-xilinx-native_2019.2.bb              |    6 +
 .../qemu/qemu-xilinx-system-native_2019.1.bb       |   16 -
 .../qemu/qemu-xilinx-system-native_2019.2.bb       |   17 +
 .../recipes-devtools/qemu/qemu-xilinx.inc          |   21 +-
 ...ure-Add-pkg-config-handling-for-libgcrypt.patch |   93 +
 .../recipes-devtools/qemu/qemu-xilinx_2019.1.bb    |   13 -
 .../recipes-devtools/qemu/qemu-xilinx_2019.2.bb    |   14 +
 .../recipes-kernel/linux/linux-xlnx_2019.1.bb      |    7 -
 .../recipes-kernel/linux/linux-xlnx_2019.2.bb      |    6 +
 ...CAL-Testsuite-builtins-tests-require-fpic.patch |   35 -
 ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch |   31 -
 ...uite-explicitly-add-fivopts-for-tests-tha.patch |  116 -
 ...ejagnu-static-testing-on-qemu-suppress-wa.patch |   35 -
 ...uite-Add-MicroBlaze-to-target-supports-fo.patch |   35 -
 ...xplicitly-add-fivopts-for-tests-that-depe.patch |  118 -
 ...-testsuite-Update-MicroBlaze-strings-test.patch |   43 -
 ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch |   67 -
 ...uite-Add-MicroBlaze-to-check_profiling_av.patch |   28 -
 ...-Patch-microblaze-Fix-atomic-side-effects.patch |   65 -
 ...icroblaze-Fix-atomic-boolean-return-value.patch |   40 -
 ...blaze-Fix-the-Microblaze-crash-with-msmal.patch |   33 -
 ...ch-microblaze-Added-ashrsi3_with_size_opt.patch |   48 -
 ...blaze-Fixed-missing-save-of-r18-in-fast_i.patch |   41 -
 ...-microblaze-Use-bralid-for-profiler-calls.patch |   26 -
 ...tch-microblaze-Disable-fivopts-by-default.patch |   42 -
 ...-Patch-microblaze-Removed-moddi3-routinue.patch |  157 --
 ...atch-microblaze-Add-INIT_PRIORITY-support.patch |  101 -
 ...18-Patch-microblaze-Add-optimized-lshrsi3.patch |   81 -
 ...atch-microblaze-Modified-trap-instruction.patch |   29 -
 ...oblaze-Reducing-Stack-space-for-arguments.patch |  206 --
 .../0021-Patch-microblaze-Add-cbranchsi4_reg.patch |  159 --
 ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch |   58 -
 ...pdate-heuristics-for-loop-invariant-for-a.patch |   47 -
 ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch |   63 -
 ...-microblaze-Update-ashlsi3-movsf-patterns.patch |   72 -
 ...icroblaze-8-stage-pipeline-for-microblaze.patch |  193 --
 ...ptimization-Better-register-pressure-esti.patch |  142 --
 ...blaze-Correct-the-const-high-double-immed.patch |   69 -
 ...aze-Fix-internal-compiler-error-with-msma.patch |   36 -
 ...blaze-Fix-the-calculation-of-high-word-in.patch |   45 -
 ...microblaze-Add-new-bit-field-instructions.patch |  120 -
 ...roblaze-Fix-bug-in-MB-version-calculation.patch |  247 --
 ...xing-the-bug-in-the-bit-field-instruction.patch |   48 -
 ...blaze-Macros-used-in-Xilinx-internal-patc.patch |   32 -
 ...5-Fixing-the-issue-with-the-builtin_alloc.patch |   44 -
 ...blaze-reverting-the-cost-check-before-pro.patch |   49 -
 ...blaze-update-in-constraints-for-bitfield-.patch |   80 -
 ...blaze-Removed-fsqrt-generation-for-double.patch |   38 -
 .../0039-Intial-commit-of-64-bit-Microblaze.patch  |  810 -------
 ...store-pattern-movdi-and-also-adding-missi.patch |   83 -
 .../0041-Intial-commit-for-64bit-MB-sources.patch  | 2463 --------------------
 ...42-re-arrangement-of-the-compare-branches.patch |  268 ---
 ...blaze-previous-commit-broke-the-handling-.patch |   28 -
 ...-Microblaze-Support-of-multilibs-with-m64.patch |   73 -
 .../gcc/gcc-8/0045-Fixed-issues-like.patch         |   70 -
 .../gcc/gcc-8/0046-Fixed-below-issues.patch        |  306 ---
 .../0047-Added-double-arith-instructions.patch     |  135 --
 ...ssue-in-the-delay-slot-with-swap-instruct.patch |   37 -
 ...oad-store-issue-with-the-32bit-arith-libr.patch |  256 --
 ...ing-the-Dwarf-support-to-64bit-Microblaze.patch |   25 -
 ...51-fixing-the-typo-errors-in-umodsi3-file.patch |   29 -
 ...xing-the-32bit-LTO-related-issue9-1014024.patch |   68 -
 ...issing-stack-adjustment-in-prologue-of-mo.patch |   25 -
 ...blaze-corrected-SPN-for-dlong-instruction.patch |   29 -
 ...-the-long-long-long-mingw-toolchain-issue.patch |   59 -
 .../0055-microblaze_linker_script_xilinx_ld.patch  |   16 -
 ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch |   47 -
 ...blaze-We-will-check-the-possibility-of-pe.patch |   87 -
 ...he-patch-as-kernel-boot-is-not-working-wi.patch |   51 -
 ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch |  466 ----
 .../0061-Author-Nagaraju-nmekala-xilinx.com.patch  |  479 ----
 ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch |   41 -
 ...CAL-Testsuite-builtins-tests-require-fpic.patch |   35 +
 ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch |   31 +
 ...uite-explicitly-add-fivopts-for-tests-tha.patch |  119 +
 ...ejagnu-static-testing-on-qemu-suppress-wa.patch |   35 +
 ...uite-Add-MicroBlaze-to-target-supports-fo.patch |   35 +
 ...xplicitly-add-fivopts-for-tests-that-depe.patch |  118 +
 ...-testsuite-Update-MicroBlaze-strings-test.patch |   43 +
 ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch |   67 +
 ...uite-Add-MicroBlaze-to-check_profiling_av.patch |   28 +
 ...-Patch-microblaze-Fix-atomic-side-effects.patch |   68 +
 ...icroblaze-Fix-atomic-boolean-return-value.patch |   40 +
 ...blaze-Fix-the-Microblaze-crash-with-msmal.patch |   33 +
 ...ch-microblaze-Added-ashrsi3_with_size_opt.patch |   48 +
 ...blaze-Fixed-missing-save-of-r18-in-fast_i.patch |   41 +
 ...-microblaze-Use-bralid-for-profiler-calls.patch |   26 +
 ...tch-microblaze-Disable-fivopts-by-default.patch |   42 +
 ...-Patch-microblaze-Removed-moddi3-routinue.patch |  160 ++
 ...atch-microblaze-Add-INIT_PRIORITY-support.patch |  101 +
 ...18-Patch-microblaze-Add-optimized-lshrsi3.patch |   81 +
 ...atch-microblaze-Modified-trap-instruction.patch |   29 +
 ...oblaze-Reducing-Stack-space-for-arguments.patch |  206 ++
 .../0021-Patch-microblaze-Add-cbranchsi4_reg.patch |  159 ++
 ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch |   58 +
 ...pdate-heuristics-for-loop-invariant-for-a.patch |   47 +
 ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch |   63 +
 ...-microblaze-Update-ashlsi3-movsf-patterns.patch |   72 +
 ...icroblaze-8-stage-pipeline-for-microblaze.patch |  193 ++
 ...ptimization-Better-register-pressure-esti.patch |  142 ++
 ...blaze-Correct-the-const-high-double-immed.patch |   69 +
 ...aze-Fix-internal-compiler-error-with-msma.patch |   36 +
 ...blaze-Fix-the-calculation-of-high-word-in.patch |   45 +
 ...microblaze-Add-new-bit-field-instructions.patch |  120 +
 ...roblaze-Fix-bug-in-MB-version-calculation.patch |  247 ++
 ...xing-the-bug-in-the-bit-field-instruction.patch |   48 +
 ...blaze-Macros-used-in-Xilinx-internal-patc.patch |   32 +
 ...5-Fixing-the-issue-with-the-builtin_alloc.patch |   44 +
 ...blaze-reverting-the-cost-check-before-pro.patch |   49 +
 ...blaze-update-in-constraints-for-bitfield-.patch |   80 +
 ...blaze-Removed-fsqrt-generation-for-double.patch |   38 +
 .../0039-Intial-commit-of-64-bit-Microblaze.patch  |  804 +++++++
 ...store-pattern-movdi-and-also-adding-missi.patch |   83 +
 .../0041-Intial-commit-for-64bit-MB-sources.patch  | 2463 ++++++++++++++++++++
 ...42-re-arrangement-of-the-compare-branches.patch |  268 +++
 ...blaze-previous-commit-broke-the-handling-.patch |   28 +
 ...-Microblaze-Support-of-multilibs-with-m64.patch |   73 +
 .../gcc/gcc-9/0045-Fixed-issues-like.patch         |   70 +
 .../gcc/gcc-9/0046-Fixed-below-issues.patch        |  307 +++
 .../0047-Added-double-arith-instructions.patch     |  135 ++
 ...ssue-in-the-delay-slot-with-swap-instruct.patch |   37 +
 ...oad-store-issue-with-the-32bit-arith-libr.patch |  256 ++
 ...ing-the-Dwarf-support-to-64bit-Microblaze.patch |   25 +
 ...51-fixing-the-typo-errors-in-umodsi3-file.patch |   29 +
 ...xing-the-32bit-LTO-related-issue9-1014024.patch |   68 +
 ...issing-stack-adjustment-in-prologue-of-mo.patch |   25 +
 ...blaze-corrected-SPN-for-dlong-instruction.patch |   29 +
 ...-the-long-long-long-mingw-toolchain-issue.patch |   59 +
 .../0055-microblaze_linker_script_xilinx_ld.patch  |   16 +
 ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch |   47 +
 ...0056-fix-the-lto-wrapper-issue-on-windows.patch |   36 +
 ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch |   47 +
 ...blaze-We-will-check-the-possibility-of-pe.patch |   87 +
 ...blaze-We-will-check-the-possibility-of-pe.patch |   87 +
 ...he-patch-as-kernel-boot-is-not-working-wi.patch |   51 +
 ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch |  466 ++++
 ...he-patch-as-kernel-boot-is-not-working-wi.patch |   51 +
 .../0060-Author-Nagaraju-nmekala-xilinx.com.patch  |  479 ++++
 ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch |  466 ++++
 .../0061-Author-Nagaraju-nmekala-xilinx.com.patch  |  479 ++++
 ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch |   41 +
 ...B-64-single-register-arithmetic-instructi.patch |  107 +
 ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch |   41 +
 ...Blaze-Added-support-for-64-bit-Immediate-.patch |   44 +
 .../recipes-microblaze/gcc/gcc-source_8.%.bbappend |   65 -
 .../recipes-microblaze/gcc/gcc-source_9.%.bbappend |   67 +
 .../recipes-multimedia/vcu/kernel-module-vcu.bb    |    5 +-
 .../recipes-multimedia/vcu/libomxil-xlnx.bb        |    5 +-
 .../recipes-multimedia/vcu/libvcu-xlnx.bb          |    5 +-
 .../recipes-multimedia/vcu/vcu-firmware.bb         |    5 +-
 meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb         |   14 +-
 meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb       |    7 +-
 meta-xilinx-contrib/conf/layer.conf                |    3 +-
 ...rm-xilinx-Add-encoder-for-Digilent-boards.patch |  305 ---
 ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch |  607 -----
 ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch |   54 -
 .../v2019.1/0004-minized-wifi-bluetooth.cfg        |   33 -
 ...rm-xilinx-Add-encoder-for-Digilent-boards.patch |  305 +++
 ...002-clk-Add-driver-for-axi_dynclk-IP-Core.patch |  607 +++++
 ...0003-drm-xilinx-Fix-DPMS-transition-to-on.patch |   54 +
 .../v2019.2/0004-minized-wifi-bluetooth.cfg        |   33 +
 .../linux/linux-xlnx_2019.1.bbappend               |    9 -
 .../linux/linux-xlnx_2019.2.bbappend               |    9 +
 meta-xilinx-standalone/conf/layer.conf             |    3 +-
 .../newlib/libgloss_3.0.0.bbappend                 |   10 -
 .../newlib/libgloss_3.1.0.bbappend                 |   10 +
 .../newlib/newlib_3.0.0.bbappend                   |    4 -
 .../newlib/newlib_3.1.0.bbappend                   |    4 +
 .../pmu-firmware/pmu-firmware_2019.1.bb            |   71 -
 .../pmu-firmware/pmu-firmware_2019.2.bb            |   71 +
 186 files changed, 12903 insertions(+), 11330 deletions(-)
 delete mode 100644 meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
 create mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch
 delete mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch
 delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch
 delete mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb
 create mode 100644 meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch
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 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch
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 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
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 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
 delete mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
 create mode 100644 meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend
 delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
 delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
 delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
 delete mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg
 create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
 create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
 create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
 create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg
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 create mode 100644 meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend
 delete mode 100644 meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend
 create mode 100644 meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend
 delete mode 100644 meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend
 create mode 100644 meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend
 delete mode 100644 meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb
 create mode 100644 meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb

diff --git a/meta-xilinx-bsp/conf/layer.conf b/meta-xilinx-bsp/conf/layer.conf
index 437616cf..2a0af10e 100644
--- a/meta-xilinx-bsp/conf/layer.conf
+++ b/meta-xilinx-bsp/conf/layer.conf
@@ -11,7 +11,8 @@ BBFILE_PRIORITY_xilinx = "5"
 
 LAYERDEPENDS_xilinx = "core"
 
-LAYERSERIES_COMPAT_xilinx = "warrior"
+LAYERSERIES_COMPAT_xilinx = "zeus"
 
 BB_DANGLINGAPPENDS_WARNONLY ?= "1"
 
+XILINX_RELEASE_VERSION = "v2019.2"
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
index 785f915e..8c4806bf 100644
--- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
+++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
@@ -12,6 +12,8 @@ DEPENDS += "u-boot-mkimage-native"
 S = "${WORKDIR}/git"
 B = "${WORKDIR}/build"
 
+SYSROOT_DIRS += "/boot"
+
 XILINX_RELEASE_VERSION ?= ""
 ATF_VERSION ?= "2.0"
 ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
@@ -72,7 +74,7 @@ do_compile() {
 }
 
 do_install() {
-	:
+	install -Dm 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${D}/boot/arm-trusted-firmware.elf
 }
 
 do_deploy() {
@@ -91,3 +93,4 @@ do_deploy() {
 	ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub
 }
 addtask deploy before do_build after do_compile
+FILES_${PN} = "/boot/arm-trusted-firmware.elf"
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb
deleted file mode 100644
index 64cbddc4..00000000
--- a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.1.bb
+++ /dev/null
@@ -1,7 +0,0 @@
-ATF_VERSION = "2.0"
-XILINX_RELEASE_VERSION = "v2019.1"
-BRANCH ?= "master"
-SRCREV ?= "80d1c79007fda42d4cc0be31b185a1da5799cd4d"
-
-include arm-trusted-firmware.inc
-
diff --git a/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb
new file mode 100644
index 00000000..a7ba1098
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2019.2.bb
@@ -0,0 +1,6 @@
+ATF_VERSION = "2.0"
+BRANCH ?= "master"
+SRCREV ?= "713dace94b259845fd8eede11061fbd8f039011e"
+
+include arm-trusted-firmware.inc
+
diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb
deleted file mode 100644
index 6a2ca7cc..00000000
--- a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.1.bb
+++ /dev/null
@@ -1,48 +0,0 @@
-SUMMARY = "KC705 Pre-built Bitstream"
-DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system."
-HOMEPAGE = "http://www.xilinx.com"
-SECTION = "bsp"
-
-# The BSP package does not include any license information.
-LICENSE = "Proprietary"
-LICENSE_FLAGS = "xilinx"
-LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
-
-COMPATIBLE_MACHINE = "kc705-microblazeel"
-
-inherit deploy
-inherit xilinx-fetch-restricted
-
-BSP_NAME = "xilinx-kc705"
-BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
-SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
-SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351"
-SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773"
-
-PROVIDES = "virtual/bitstream"
-
-FILES_${PN} += "/boot/download.bit"
-
-INHIBIT_DEFAULT_DEPS = "1"
-PACKAGE_ARCH = "${MACHINE_ARCH}"
-
-# deps needed to extract content from the .bsp file
-DEPENDS += "tar-native gzip-native"
-
-do_compile() {
-	# Extract the bitstream into workdir
-	tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S}
-	# move the bit file to ${S}/ as it is in a subdir in the tar file
-	for i in $(find -type f -name download.bit); do mv $i ${S}; done
-}
-
-do_install() {
-	install -D ${S}/download.bit ${D}/boot/download.bit
-}
-
-do_deploy () {
-	install -D ${S}/download.bit ${DEPLOYDIR}/download.bit
-}
-
-addtask deploy before do_build after do_install
-
diff --git a/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb
new file mode 100644
index 00000000..6a2ca7cc
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2019.2.bb
@@ -0,0 +1,48 @@
+SUMMARY = "KC705 Pre-built Bitstream"
+DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system."
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+# The BSP package does not include any license information.
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+COMPATIBLE_MACHINE = "kc705-microblazeel"
+
+inherit deploy
+inherit xilinx-fetch-restricted
+
+BSP_NAME = "xilinx-kc705"
+BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
+SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
+SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351"
+SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773"
+
+PROVIDES = "virtual/bitstream"
+
+FILES_${PN} += "/boot/download.bit"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+# deps needed to extract content from the .bsp file
+DEPENDS += "tar-native gzip-native"
+
+do_compile() {
+	# Extract the bitstream into workdir
+	tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S}
+	# move the bit file to ${S}/ as it is in a subdir in the tar file
+	for i in $(find -type f -name download.bit); do mv $i ${S}; done
+}
+
+do_install() {
+	install -D ${S}/download.bit ${D}/boot/download.bit
+}
+
+do_deploy () {
+	install -D ${S}/download.bit ${DEPLOYDIR}/download.bit
+}
+
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc
index 737f5f91..61ed1804 100644
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx.inc
@@ -18,3 +18,4 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot:"
 FILESEXTRAPATHS_prepend := "${THISDIR}/u-boot-xlnx:"
 FILESEXTRAPATHS_prepend := "${@'${THISDIR}/u-boot-xlnx/${XILINX_RELEASE_VERSION}:' if d.getVar('XILINX_RELEASE_VERSION') else ''}"
 
+SYSROOT_DIRS += "/boot"
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
deleted file mode 100644
index 7e25f87c..00000000
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
+++ /dev/null
@@ -1,1133 +0,0 @@
-From afe880f500cff7a9486379c5ad7a4f3379015a62 Mon Sep 17 00:00:00 2001
-From: Jaewon Lee <jaewon.lee@xilinx.com>
-Date: Mon, 14 Jan 2019 11:30:56 -0800
-Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to
- kc705-microblazeel
-
-This is an update to earlier kc705-trd patch done by Nathan Rossi.
-
-Change the microblaze-generic board to match the kc705-microblazeel.
-This patch is not intended for upstream and serves as an intermediate
-solution until OF support in upstream u-boot allows for easy support for
-custom microblaze boards.
-
-Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
-Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
----
- arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++-
- board/xilinx/microblaze-generic/config.mk  |  28 +-
- configs/microblaze-generic_defconfig       |  75 ++--
- include/configs/microblaze-generic.h       | 348 ++++++++---------
- 4 files changed, 782 insertions(+), 259 deletions(-)
-
-diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
-index 08a1396..f8e616b 100644
---- a/arch/microblaze/dts/microblaze-generic.dts
-+++ b/arch/microblaze/dts/microblaze-generic.dts
-@@ -1,9 +1,587 @@
- /dts-v1/;
-+
- / {
--	#address-cells = <1>;
--	#size-cells = <1>;
--	aliases {
--	} ;
-+	#address-cells = <0x1>;
-+	#size-cells = <0x1>;
-+	compatible = "xlnx,microblaze";
-+	model = "Xilinx MicroBlaze";
-+	hard-reset-gpios = <0x1 0x0 0x1>;
-+
-+	cpus {
-+		#address-cells = <0x1>;
-+		#cpus = <0x1>;
-+		#size-cells = <0x0>;
-+
-+		cpu@0 {
-+			bus-handle = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clocks = <0x3>;
-+			compatible = "xlnx,microblaze-10.0";
-+			d-cache-baseaddr = <0x80000000>;
-+			d-cache-highaddr = <0xbfffffff>;
-+			d-cache-line-size = <0x20>;
-+			d-cache-size = <0x4000>;
-+			device_type = "cpu";
-+			i-cache-baseaddr = <0x80000000>;
-+			i-cache-highaddr = <0xbfffffff>;
-+			i-cache-line-size = <0x10>;
-+			i-cache-size = <0x4000>;
-+			interrupt-handle = <0x4>;
-+			model = "microblaze,10.0";
-+			timebase-frequency = <0xbebc200>;
-+			xlnx,addr-size = <0x20>;
-+			xlnx,addr-tag-bits = <0x10>;
-+			xlnx,allow-dcache-wr = <0x1>;
-+			xlnx,allow-icache-wr = <0x1>;
-+			xlnx,area-optimized = <0x0>;
-+			xlnx,async-interrupt = <0x1>;
-+			xlnx,async-wakeup = <0x3>;
-+			xlnx,avoid-primitives = <0x0>;
-+			xlnx,base-vectors = <0x0>;
-+			xlnx,branch-target-cache-size = <0x0>;
-+			xlnx,cache-byte-size = <0x4000>;
-+			xlnx,d-axi = <0x1>;
-+			xlnx,d-lmb = <0x1>;
-+			xlnx,d-lmb-mon = <0x0>;
-+			xlnx,daddr-size = <0x20>;
-+			xlnx,data-size = <0x20>;
-+			xlnx,dc-axi-mon = <0x0>;
-+			xlnx,dcache-addr-tag = <0x10>;
-+			xlnx,dcache-always-used = <0x1>;
-+			xlnx,dcache-byte-size = <0x4000>;
-+			xlnx,dcache-data-width = <0x0>;
-+			xlnx,dcache-force-tag-lutram = <0x0>;
-+			xlnx,dcache-line-len = <0x8>;
-+			xlnx,dcache-use-writeback = <0x0>;
-+			xlnx,dcache-victims = <0x0>;
-+			xlnx,debug-counter-width = <0x20>;
-+			xlnx,debug-enabled = <0x1>;
-+			xlnx,debug-event-counters = <0x5>;
-+			xlnx,debug-external-trace = <0x0>;
-+			xlnx,debug-interface = <0x0>;
-+			xlnx,debug-latency-counters = <0x1>;
-+			xlnx,debug-profile-size = <0x0>;
-+			xlnx,debug-trace-async-reset = <0x0>;
-+			xlnx,debug-trace-size = <0x2000>;
-+			xlnx,div-zero-exception = <0x1>;
-+			xlnx,dp-axi-mon = <0x0>;
-+			xlnx,dynamic-bus-sizing = <0x0>;
-+			xlnx,ecc-use-ce-exception = <0x0>;
-+			xlnx,edge-is-positive = <0x1>;
-+			xlnx,enable-discrete-ports = <0x0>;
-+			xlnx,endianness = <0x1>;
-+			xlnx,fault-tolerant = <0x0>;
-+			xlnx,fpu-exception = <0x0>;
-+			xlnx,freq = <0xbebc200>;
-+			xlnx,fsl-exception = <0x0>;
-+			xlnx,fsl-links = <0x0>;
-+			xlnx,i-axi = <0x0>;
-+			xlnx,i-lmb = <0x1>;
-+			xlnx,i-lmb-mon = <0x0>;
-+			xlnx,iaddr-size = <0x20>;
-+			xlnx,ic-axi-mon = <0x0>;
-+			xlnx,icache-always-used = <0x1>;
-+			xlnx,icache-data-width = <0x0>;
-+			xlnx,icache-force-tag-lutram = <0x0>;
-+			xlnx,icache-line-len = <0x4>;
-+			xlnx,icache-streams = <0x1>;
-+			xlnx,icache-victims = <0x8>;
-+			xlnx,ill-opcode-exception = <0x1>;
-+			xlnx,imprecise-exceptions = <0x0>;
-+			xlnx,instr-size = <0x20>;
-+			xlnx,interconnect = <0x2>;
-+			xlnx,interrupt-is-edge = <0x0>;
-+			xlnx,interrupt-mon = <0x0>;
-+			xlnx,ip-axi-mon = <0x0>;
-+			xlnx,lockstep-master = <0x0>;
-+			xlnx,lockstep-select = <0x0>;
-+			xlnx,lockstep-slave = <0x0>;
-+			xlnx,mmu-dtlb-size = <0x4>;
-+			xlnx,mmu-itlb-size = <0x2>;
-+			xlnx,mmu-privileged-instr = <0x0>;
-+			xlnx,mmu-tlb-access = <0x3>;
-+			xlnx,mmu-zones = <0x2>;
-+			xlnx,num-sync-ff-clk = <0x2>;
-+			xlnx,num-sync-ff-clk-debug = <0x2>;
-+			xlnx,num-sync-ff-clk-irq = <0x1>;
-+			xlnx,num-sync-ff-dbg-clk = <0x1>;
-+			xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
-+			xlnx,number-of-pc-brk = <0x1>;
-+			xlnx,number-of-rd-addr-brk = <0x0>;
-+			xlnx,number-of-wr-addr-brk = <0x0>;
-+			xlnx,opcode-0x0-illegal = <0x1>;
-+			xlnx,optimization = <0x0>;
-+			xlnx,pc-width = <0x20>;
-+			xlnx,piaddr-size = <0x20>;
-+			xlnx,pvr = <0x2>;
-+			xlnx,pvr-user1 = <0x0>;
-+			xlnx,pvr-user2 = <0x0>;
-+			xlnx,reset-msr = <0x0>;
-+			xlnx,reset-msr-bip = <0x0>;
-+			xlnx,reset-msr-dce = <0x0>;
-+			xlnx,reset-msr-ee = <0x0>;
-+			xlnx,reset-msr-eip = <0x0>;
-+			xlnx,reset-msr-ice = <0x0>;
-+			xlnx,reset-msr-ie = <0x0>;
-+			xlnx,sco = <0x0>;
-+			xlnx,trace = <0x0>;
-+			xlnx,unaligned-exceptions = <0x1>;
-+			xlnx,use-barrel = <0x1>;
-+			xlnx,use-branch-target-cache = <0x0>;
-+			xlnx,use-config-reset = <0x0>;
-+			xlnx,use-dcache = <0x1>;
-+			xlnx,use-div = <0x1>;
-+			xlnx,use-ext-brk = <0x0>;
-+			xlnx,use-ext-nm-brk = <0x0>;
-+			xlnx,use-extended-fsl-instr = <0x0>;
-+			xlnx,use-fpu = <0x0>;
-+			xlnx,use-hw-mul = <0x2>;
-+			xlnx,use-icache = <0x1>;
-+			xlnx,use-interrupt = <0x2>;
-+			xlnx,use-mmu = <0x3>;
-+			xlnx,use-msr-instr = <0x1>;
-+			xlnx,use-non-secure = <0x0>;
-+			xlnx,use-pcmp-instr = <0x1>;
-+			xlnx,use-reorder-instr = <0x1>;
-+			xlnx,use-stack-protection = <0x0>;
-+		};
-+	};
-+
-+	clocks {
-+		#address-cells = <0x1>;
-+		#size-cells = <0x0>;
-+
-+		clk_cpu@0 {
-+			#clock-cells = <0x0>;
-+			clock-frequency = <0xbebc200>;
-+			clock-output-names = "clk_cpu";
-+			compatible = "fixed-clock";
-+			reg = <0x0>;
-+			linux,phandle = <0x3>;
-+			phandle = <0x3>;
-+		};
-+
-+		clk_bus_0@1 {
-+			#clock-cells = <0x0>;
-+			clock-frequency = <0xbebc200>;
-+			clock-output-names = "clk_bus_0";
-+			compatible = "fixed-clock";
-+			reg = <0x1>;
-+			linux,phandle = <0x8>;
-+			phandle = <0x8>;
-+		};
-+	};
-+
-+	amba_pl {
-+		#address-cells = <0x1>;
-+		#size-cells = <0x1>;
-+		compatible = "simple-bus";
-+		ranges;
-+		linux,phandle = <0x2>;
-+		phandle = <0x2>;
-+
-+		ethernet@40c00000 {
-+			axistream-connected = <0x5>;
-+			axistream-control-connected = <0x5>;
-+			clock-frequency = <0x5f5e100>;
-+			compatible = "xlnx,axi-ethernet-1.00.a";
-+			device_type = "network";
-+			interrupt-names = "interrupt";
-+			interrupt-parent = <0x4>;
-+			interrupts = <0x4 0x2>;
-+			phy-mode = "gmii";
-+			reg = <0x40c00000 0x40000>;
-+			xlnx = <0x0>;
-+			xlnx,axiliteclkrate = <0x0>;
-+			xlnx,axisclkrate = <0x0>;
-+			xlnx,clockselection = <0x0>;
-+			xlnx,enableasyncsgmii = <0x0>;
-+			xlnx,gt-type = <0x0>;
-+			xlnx,gtinex = <0x0>;
-+			xlnx,gtlocation = <0x0>;
-+			xlnx,gtrefclksrc = <0x0>;
-+			xlnx,include-dre;
-+			xlnx,instantiatebitslice0 = <0x0>;
-+			xlnx,phy-type = <0x1>;
-+			xlnx,phyaddr = <0x1>;
-+			xlnx,rable = <0x0>;
-+			xlnx,rxcsum = <0x0>;
-+			xlnx,rxlane0-placement = <0x0>;
-+			xlnx,rxlane1-placement = <0x0>;
-+			xlnx,rxmem = <0x1000>;
-+			xlnx,rxnibblebitslice0used = <0x0>;
-+			xlnx,tx-in-upper-nibble = <0x1>;
-+			xlnx,txcsum = <0x0>;
-+			xlnx,txlane0-placement = <0x0>;
-+			xlnx,txlane1-placement = <0x0>;
-+			phy-handle = <0x6>;
-+			local-mac-address = [00 0a 35 00 22 01];
-+			linux,phandle = <0x7>;
-+			phandle = <0x7>;
-+
-+			mdio {
-+				#address-cells = <0x1>;
-+				#size-cells = <0x0>;
-+
-+				phy@7 {
-+					device_type = "ethernet-phy";
-+					reg = <0x7>;
-+					linux,phandle = <0x6>;
-+					phandle = <0x6>;
-+				};
-+			};
-+		};
-+
-+		dma@41e00000 {
-+			#dma-cells = <0x1>;
-+			axistream-connected = <0x7>;
-+			axistream-control-connected = <0x7>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_lite_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,eth-dma";
-+			interrupt-names = "mm2s_introut", "s2mm_introut";
-+			interrupt-parent = <0x4>;
-+			interrupts = <0x3 0x2 0x2 0x2>;
-+			reg = <0x41e00000 0x10000>;
-+			xlnx,include-dre;
-+			linux,phandle = <0x5>;
-+			phandle = <0x5>;
-+		};
-+
-+		timer@41c00000 {
-+			clock-frequency = <0xbebc200>;
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-timer-1.00.a";
-+			interrupt-names = "interrupt";
-+			interrupt-parent = <0x4>;
-+			interrupts = <0x5 0x2>;
-+			reg = <0x41c00000 0x10000>;
-+			xlnx,count-width = <0x20>;
-+			xlnx,gen0-assert = <0x1>;
-+			xlnx,gen1-assert = <0x1>;
-+			xlnx,one-timer-only = <0x0>;
-+			xlnx,trig0-assert = <0x1>;
-+			xlnx,trig1-assert = <0x1>;
-+		};
-+
-+		gpio@40010000 {
-+			#gpio-cells = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-gpio-1.00.a";
-+			gpio-controller;
-+			reg = <0x40010000 0x10000>;
-+			xlnx,all-inputs = <0x1>;
-+			xlnx,all-inputs-2 = <0x0>;
-+			xlnx,all-outputs = <0x0>;
-+			xlnx,all-outputs-2 = <0x0>;
-+			xlnx,dout-default = <0x0>;
-+			xlnx,dout-default-2 = <0x0>;
-+			xlnx,gpio-width = <0x1>;
-+			xlnx,gpio2-width = <0x20>;
-+			xlnx,interrupt-present = <0x0>;
-+			xlnx,is-dual = <0x0>;
-+			xlnx,tri-default = <0xffffffff>;
-+			xlnx,tri-default-2 = <0xffffffff>;
-+		};
-+
-+		gpio@40020000 {
-+			#gpio-cells = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-gpio-1.00.a";
-+			gpio-controller;
-+			reg = <0x40020000 0x10000>;
-+			xlnx,all-inputs = <0x1>;
-+			xlnx,all-inputs-2 = <0x0>;
-+			xlnx,all-outputs = <0x0>;
-+			xlnx,all-outputs-2 = <0x0>;
-+			xlnx,dout-default = <0x0>;
-+			xlnx,dout-default-2 = <0x0>;
-+			xlnx,gpio-width = <0x4>;
-+			xlnx,gpio2-width = <0x20>;
-+			xlnx,interrupt-present = <0x0>;
-+			xlnx,is-dual = <0x0>;
-+			xlnx,tri-default = <0xffffffff>;
-+			xlnx,tri-default-2 = <0xffffffff>;
-+		};
-+
-+		i2c@40800000 {
-+			#address-cells = <0x1>;
-+			#size-cells = <0x0>;
-+			clock-frequency = <0xbebc200>;
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-iic-2.00.a";
-+			interrupt-names = "iic2intc_irpt";
-+			interrupt-parent = <0x4>;
-+			interrupts = <0x1 0x2>;
-+			reg = <0x40800000 0x10000>;
-+
-+			i2cswitch@74 {
-+				compatible = "nxp,pca9548";
-+				#address-cells = <0x1>;
-+				#size-cells = <0x0>;
-+				reg = <0x74>;
-+
-+				i2c@0 {
-+					#address-cells = <0x1>;
-+					#size-cells = <0x0>;
-+					reg = <0x0>;
-+
-+					clock-generator@5d {
-+						#clock-cells = <0x0>;
-+						compatible = "silabs,si570";
-+						temperature-stability = <0x32>;
-+						reg = <0x5d>;
-+						factory-fout = <0x9502f90>;
-+						clock-frequency = <0x8d9ee20>;
-+					};
-+				};
-+
-+				i2c@3 {
-+					#address-cells = <0x1>;
-+					#size-cells = <0x0>;
-+					reg = <0x3>;
-+
-+					eeprom@54 {
-+						compatible = "at,24c08";
-+						reg = <0x54>;
-+					};
-+				};
-+			};
-+		};
-+
-+		gpio@40030000 {
-+			#gpio-cells = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-gpio-1.00.a";
-+			gpio-controller;
-+			reg = <0x40030000 0x10000>;
-+			xlnx,all-inputs = <0x0>;
-+			xlnx,all-inputs-2 = <0x0>;
-+			xlnx,all-outputs = <0x1>;
-+			xlnx,all-outputs-2 = <0x0>;
-+			xlnx,dout-default = <0x0>;
-+			xlnx,dout-default-2 = <0x0>;
-+			xlnx,gpio-width = <0x8>;
-+			xlnx,gpio2-width = <0x20>;
-+			xlnx,interrupt-present = <0x0>;
-+			xlnx,is-dual = <0x0>;
-+			xlnx,tri-default = <0xffffffff>;
-+			xlnx,tri-default-2 = <0xffffffff>;
-+		};
-+
-+		flash@60000000 {
-+			bank-width = <0x2>;
-+			compatible = "cfi-flash";
-+			reg = <0x60000000 0x8000000>;
-+			xlnx,axi-clk-period-ps = <0x1388>;
-+			xlnx,include-datawidth-matching-0 = <0x1>;
-+			xlnx,include-datawidth-matching-1 = <0x1>;
-+			xlnx,include-datawidth-matching-2 = <0x1>;
-+			xlnx,include-datawidth-matching-3 = <0x1>;
-+			xlnx,include-negedge-ioregs = <0x0>;
-+			xlnx,lflash-period-ps = <0x1388>;
-+			xlnx,linear-flash-sync-burst = <0x0>;
-+			xlnx,max-mem-width = <0x10>;
-+			xlnx,mem-a-lsb = <0x0>;
-+			xlnx,mem-a-msb = <0x1f>;
-+			xlnx,mem0-type = <0x2>;
-+			xlnx,mem0-width = <0x10>;
-+			xlnx,mem1-type = <0x0>;
-+			xlnx,mem1-width = <0x10>;
-+			xlnx,mem2-type = <0x0>;
-+			xlnx,mem2-width = <0x10>;
-+			xlnx,mem3-type = <0x0>;
-+			xlnx,mem3-width = <0x10>;
-+			xlnx,num-banks-mem = <0x1>;
-+			xlnx,page-size = <0x10>;
-+			xlnx,parity-type-mem-0 = <0x0>;
-+			xlnx,parity-type-mem-1 = <0x0>;
-+			xlnx,parity-type-mem-2 = <0x0>;
-+			xlnx,parity-type-mem-3 = <0x0>;
-+			xlnx,port-diff = <0x0>;
-+			xlnx,s-axi-en-reg = <0x0>;
-+			xlnx,s-axi-mem-addr-width = <0x20>;
-+			xlnx,s-axi-mem-data-width = <0x20>;
-+			xlnx,s-axi-mem-id-width = <0x1>;
-+			xlnx,s-axi-reg-addr-width = <0x5>;
-+			xlnx,s-axi-reg-data-width = <0x20>;
-+			xlnx,synch-pipedelay-0 = <0x1>;
-+			xlnx,synch-pipedelay-1 = <0x1>;
-+			xlnx,synch-pipedelay-2 = <0x1>;
-+			xlnx,synch-pipedelay-3 = <0x1>;
-+			xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
-+			xlnx,tavdv-ps-mem-1 = <0x3a98>;
-+			xlnx,tavdv-ps-mem-2 = <0x3a98>;
-+			xlnx,tavdv-ps-mem-3 = <0x3a98>;
-+			xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
-+			xlnx,tcedv-ps-mem-1 = <0x3a98>;
-+			xlnx,tcedv-ps-mem-2 = <0x3a98>;
-+			xlnx,tcedv-ps-mem-3 = <0x3a98>;
-+			xlnx,thzce-ps-mem-0 = <0x88b8>;
-+			xlnx,thzce-ps-mem-1 = <0x1b58>;
-+			xlnx,thzce-ps-mem-2 = <0x1b58>;
-+			xlnx,thzce-ps-mem-3 = <0x1b58>;
-+			xlnx,thzoe-ps-mem-0 = <0x1b58>;
-+			xlnx,thzoe-ps-mem-1 = <0x1b58>;
-+			xlnx,thzoe-ps-mem-2 = <0x1b58>;
-+			xlnx,thzoe-ps-mem-3 = <0x1b58>;
-+			xlnx,tlzwe-ps-mem-0 = <0xc350>;
-+			xlnx,tlzwe-ps-mem-1 = <0x0>;
-+			xlnx,tlzwe-ps-mem-2 = <0x0>;
-+			xlnx,tlzwe-ps-mem-3 = <0x0>;
-+			xlnx,tpacc-ps-flash-0 = <0x61a8>;
-+			xlnx,tpacc-ps-flash-1 = <0x61a8>;
-+			xlnx,tpacc-ps-flash-2 = <0x61a8>;
-+			xlnx,tpacc-ps-flash-3 = <0x61a8>;
-+			xlnx,twc-ps-mem-0 = <0x11170>;
-+			xlnx,twc-ps-mem-1 = <0x3a98>;
-+			xlnx,twc-ps-mem-2 = <0x3a98>;
-+			xlnx,twc-ps-mem-3 = <0x3a98>;
-+			xlnx,twp-ps-mem-0 = <0x13880>;
-+			xlnx,twp-ps-mem-1 = <0x2ee0>;
-+			xlnx,twp-ps-mem-2 = <0x2ee0>;
-+			xlnx,twp-ps-mem-3 = <0x2ee0>;
-+			xlnx,twph-ps-mem-0 = <0x13880>;
-+			xlnx,twph-ps-mem-1 = <0x2ee0>;
-+			xlnx,twph-ps-mem-2 = <0x2ee0>;
-+			xlnx,twph-ps-mem-3 = <0x2ee0>;
-+			xlnx,use-startup = <0x0>;
-+			xlnx,use-startup-int = <0x0>;
-+			xlnx,wr-rec-time-mem-0 = <0x186a0>;
-+			xlnx,wr-rec-time-mem-1 = <0x6978>;
-+			xlnx,wr-rec-time-mem-2 = <0x6978>;
-+			xlnx,wr-rec-time-mem-3 = <0x6978>;
-+			#address-cells = <0x1>;
-+			#size-cells = <0x1>;
-+
-+			partition@0x00000000 {
-+				label = "fpga";
-+				reg = <0x0 0xb00000>;
-+			};
-+
-+			partition@0x00b00000 {
-+				label = "boot";
-+				reg = <0xb00000 0x80000>;
-+			};
-+
-+			partition@0x00b80000 {
-+				label = "bootenv";
-+				reg = <0xb80000 0x20000>;
-+			};
-+
-+			partition@0x00ba0000 {
-+				label = "kernel";
-+				reg = <0xba0000 0xc00000>;
-+			};
-+
-+			partition@0x017a0000 {
-+				label = "spare";
-+				reg = <0x17a0000 0x0>;
-+			};
-+		};
-+
-+		interrupt-controller@41200000 {
-+			#interrupt-cells = <0x2>;
-+			compatible = "xlnx,xps-intc-1.00.a";
-+			interrupt-controller;
-+			reg = <0x41200000 0x10000>;
-+			xlnx,kind-of-intr = <0x0>;
-+			xlnx,num-intr-inputs = <0x6>;
-+			linux,phandle = <0x4>;
-+			phandle = <0x4>;
-+		};
-+
-+		gpio@40040000 {
-+			#gpio-cells = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-gpio-1.00.a";
-+			gpio-controller;
-+			reg = <0x40040000 0x10000>;
-+			xlnx,all-inputs = <0x1>;
-+			xlnx,all-inputs-2 = <0x0>;
-+			xlnx,all-outputs = <0x0>;
-+			xlnx,all-outputs-2 = <0x0>;
-+			xlnx,dout-default = <0x0>;
-+			xlnx,dout-default-2 = <0x0>;
-+			xlnx,gpio-width = <0x5>;
-+			xlnx,gpio2-width = <0x20>;
-+			xlnx,interrupt-present = <0x0>;
-+			xlnx,is-dual = <0x0>;
-+			xlnx,tri-default = <0xffffffff>;
-+			xlnx,tri-default-2 = <0xffffffff>;
-+		};
-+
-+		gpio@40000000 {
-+			#gpio-cells = <0x2>;
-+			clock-frequency = <0xbebc200>;
-+			clock-names = "s_axi_aclk";
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-gpio-1.00.a";
-+			gpio-controller;
-+			reg = <0x40000000 0x10000>;
-+			xlnx,all-inputs = <0x0>;
-+			xlnx,all-inputs-2 = <0x0>;
-+			xlnx,all-outputs = <0x1>;
-+			xlnx,all-outputs-2 = <0x0>;
-+			xlnx,dout-default = <0x0>;
-+			xlnx,dout-default-2 = <0x0>;
-+			xlnx,gpio-width = <0x1>;
-+			xlnx,gpio2-width = <0x20>;
-+			xlnx,interrupt-present = <0x0>;
-+			xlnx,is-dual = <0x0>;
-+			xlnx,tri-default = <0xffffffff>;
-+			xlnx,tri-default-2 = <0xffffffff>;
-+			linux,phandle = <0x1>;
-+			phandle = <0x1>;
-+		};
-+
-+		serial@44a00000 {
-+			clock-frequency = <0xbebc200>;
-+			clocks = <0x8>;
-+			compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
-+			current-speed = <0x1c200>;
-+			device_type = "serial";
-+			interrupt-names = "ip2intc_irpt";
-+			interrupt-parent = <0x4>;
-+			interrupts = <0x0 0x2>;
-+			port-number = <0x0>;
-+			reg = <0x44a00000 0x10000>;
-+			reg-offset = <0x1000>;
-+			reg-shift = <0x2>;
-+			xlnx,external-xin-clk-hz = <0x17d7840>;
-+			xlnx,external-xin-clk-hz-d = <0x19>;
-+			xlnx,has-external-rclk = <0x0>;
-+			xlnx,has-external-xin = <0x0>;
-+			xlnx,is-a-16550 = <0x1>;
-+			xlnx,s-axi-aclk-freq-hz-d = "200.0";
-+			xlnx,use-modem-ports = <0x1>;
-+			xlnx,use-user-ports = <0x1>;
-+		};
-+	};
-+
- 	chosen {
--	} ;
--} ;
-+		bootargs = "console=ttyS0,115200 earlyprintk";
-+		stdout-path = "serial0:115200n8";
-+	};
-+
-+	aliases {
-+		ethernet0 = "/amba_pl/ethernet@40c00000";
-+		i2c0 = "/amba_pl/i2c@40800000";
-+		serial0 = "/amba_pl/serial@44a00000";
-+	};
-+
-+	memory {
-+		device_type = "memory";
-+		reg = <0x80000000 0x40000000>;
-+	};
-+};
-+
-diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
-index a953977..cb75fde 100644
---- a/board/xilinx/microblaze-generic/config.mk
-+++ b/board/xilinx/microblaze-generic/config.mk
-@@ -1,18 +1,10 @@
--# SPDX-License-Identifier: GPL-2.0+
--#
--# (C) Copyright 2007 - 2016 Michal Simek
--#
--# Michal SIMEK <monstr@monstr.eu>
--
--CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
--
--# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
--CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
--CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
--CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
--CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
--CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
--
--CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
--
--PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
-+TEXT_BASE = 0x80400000
-+CONFIG_SYS_TEXT_BASE = 0x80400000
-+
-+PLATFORM_CPPFLAGS += -mxl-barrel-shift
-+PLATFORM_CPPFLAGS += -mno-xl-soft-div
-+PLATFORM_CPPFLAGS += -mxl-pattern-compare
-+PLATFORM_CPPFLAGS += -mxl-multiply-high
-+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
-+PLATFORM_CPPFLAGS += -mcpu=v11.0
-+PLATFORM_CPPFLAGS += -fgnu89-inline
-diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
-index 02e62e2..8d64be4 100644
---- a/configs/microblaze-generic_defconfig
-+++ b/configs/microblaze-generic_defconfig
-@@ -1,73 +1,58 @@
- CONFIG_MICROBLAZE=y
--CONFIG_SYS_TEXT_BASE=0x29000000
- CONFIG_SPL_LIBCOMMON_SUPPORT=y
- CONFIG_SPL_LIBGENERIC_SUPPORT=y
- CONFIG_SPL_SERIAL_SUPPORT=y
--CONFIG_SPL=y
- CONFIG_TARGET_MICROBLAZE_GENERIC=y
- CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
- CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
- CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
- CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
--CONFIG_NR_DRAM_BANKS=1
-+CONFIG_SYS_TEXT_BASE=0x80400000
-+CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
- CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
--CONFIG_BOOTDELAY=-1
--CONFIG_USE_BOOTARGS=y
--CONFIG_BOOTARGS="root=romfs"
-+CONFIG_BOOTDELAY=4
- CONFIG_SYS_CONSOLE_IS_IN_ENV=y
--CONFIG_DISPLAY_BOARDINFO=y
--CONFIG_SPL_BOARD_INIT=y
--CONFIG_SPL_SYS_MALLOC_SIMPLE=y
- CONFIG_SPL_NOR_SUPPORT=y
- CONFIG_SPL_OS_BOOT=y
- CONFIG_SYS_OS_BASE=0x2c060000
- CONFIG_HUSH_PARSER=y
--# CONFIG_AUTO_COMPLETE is not set
--CONFIG_SYS_PROMPT="U-Boot-mONStR> "
--CONFIG_CMD_IMLS=y
--CONFIG_CMD_SPL=y
-+CONFIG_SYS_PROMPT="U-Boot> "
- CONFIG_CMD_ASKENV=y
--CONFIG_CMD_GPIO=y
- CONFIG_CMD_SAVES=y
- # CONFIG_CMD_SETEXPR is not set
-+CONFIG_SYS_ENET=y
-+CONFIG_NET=y
-+CONFIG_NETDEVICES=y
-+CONFIG_CMD_NET=y
- CONFIG_CMD_DHCP=y
--CONFIG_CMD_TFTPPUT=y
-+CONFIG_CMD_NFS=y
- CONFIG_CMD_MII=y
- CONFIG_CMD_PING=y
- CONFIG_CMD_JFFS2=y
--CONFIG_SPL_OF_CONTROL=y
- CONFIG_OF_EMBED=y
--CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
--CONFIG_NETCONSOLE=y
--CONFIG_SPL_DM=y
-+CONFIG_DM_ETH=y
-+CONFIG_SYS_MALLOC_F=y
-+CONFIG_SYS_GENERIC_BOARD=y
-+CONFIG_XILINX_AXIEMAC=y
-+CONFIG_SYS_NS16550=y
-+CONFIG_CMD_FLASH=y
-+CONFIG_MTD_NOR_FLASH=y
-+CONFIG_CMD_IMLS=y
-+CONFIG_CMD_GPIO=y
- CONFIG_DM_GPIO=y
- CONFIG_XILINX_GPIO=y
--CONFIG_LED=y
--CONFIG_LED_GPIO=y
--CONFIG_MTD_NOR_FLASH=y
--CONFIG_MTD_DEVICE=y
--CONFIG_FLASH_CFI_DRIVER=y
--CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
--CONFIG_FLASH_CFI_MTD=y
--CONFIG_SYS_FLASH_PROTECTION=y
--CONFIG_SYS_FLASH_CFI=y
--CONFIG_PHY_ATHEROS=y
--CONFIG_PHY_BROADCOM=y
--CONFIG_PHY_DAVICOM=y
--CONFIG_PHY_LXT=y
--CONFIG_PHY_MARVELL=y
-+CONFIG_CMD_TFTPPUT=y
-+CONFIG_NETCONSOLE=y
-+CONFIG_XILINX_FSL_LINKS=0
-+CONFIG_PHY_GIGE=y
-+CONFIG_ENV_IS_IN_FLASH=y
- CONFIG_PHY_MICREL=y
- CONFIG_PHY_MICREL_KSZ90X1=y
--CONFIG_PHY_NATSEMI=y
--CONFIG_PHY_REALTEK=y
--CONFIG_PHY_VITESSE=y
--CONFIG_DM_ETH=y
--CONFIG_XILINX_AXIEMAC=y
--CONFIG_XILINX_EMACLITE=y
--CONFIG_SYS_NS16550=y
--CONFIG_XILINX_UARTLITE=y
--CONFIG_SYSRESET_GPIO=y
--CONFIG_SYSRESET_MICROBLAZE=y
--CONFIG_WDT=y
--CONFIG_XILINX_TB_WATCHDOG=y
-+CONFIG_SPL_DM_SERIAL=y
-+CONFIG_SPL_OF_LIBFDT=y
-+CONFIG_PHY_XILINX=y
-+# CONFIG_SPL is not set
-+# CONFIG_CMD_EEPROM is not set
-+# CONFIG_BOOTARGS is not set
-+# CONFIG_USE_BOOTARGS is not set
-diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
-index ba0952c..fd1da2b 100644
---- a/include/configs/microblaze-generic.h
-+++ b/include/configs/microblaze-generic.h
-@@ -1,205 +1,173 @@
--/* SPDX-License-Identifier: GPL-2.0+ */
--/*
-- * (C) Copyright 2007-2010 Michal Simek
-- *
-- * Michal SIMEK <monstr@monstr.eu>
-- */
--
- #ifndef __CONFIG_H
- #define __CONFIG_H
- 
--#include "../board/xilinx/microblaze-generic/xparameters.h"
--
--/* MicroBlaze CPU */
--#define	MICROBLAZE_V5		1
--
--/* linear and spi flash memory */
--#ifdef XILINX_FLASH_START
--#define	FLASH
--#undef	SPIFLASH
--#undef	RAMENV	/* hold environment in flash */
--#else
--#undef	FLASH
--#undef	SPIFLASH
--#define	RAMENV	/* hold environment in RAM */
--#endif
-+#define CONFIG_SYS_BAUDRATE_TABLE  { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
-+
-+/* processor - microblaze_0 */
-+#define XILINX_USE_MSR_INSTR	1
-+#define XILINX_USE_ICACHE	1
-+#define XILINX_USE_DCACHE	1
-+#define XILINX_DCACHE_BYTE_SIZE	16384
-+#define XILINX_PVR	2
-+#define MICROBLAZE_V5
-+#define CONFIG_CMD_IRQ
-+#define CONFIG_DCACHE
-+#define CONFIG_ICACHE
-+
-+/* main_memory - ddr3_sdram */
-+
-+
-+/* uart - rs232_uart */
-+#define CONFIG_SYS_NS16550_COM1	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
-+#define CONFIG_SYS_NS16550_REG_SIZE	-4
-+#define CONSOLE_ARG	"console=console=ttyS0,115200\0"
-+#define CONFIG_SYS_NS16550_SERIAL
-+#define CONFIG_CONS_INDEX	1
-+#define ESERIAL0	"eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
-+#define SERIAL_MULTI  "serial=setenv stdout serial;setenv stdin serial\0"
-+#define CONFIG_SYS_NS16550_CLK	200000000
-+#define CONFIG_BAUDRATE	115200
-+
-+/* ethernet - axi_ethernet */
-+#define CONFIG_PHY_XILINX
-+#define CONFIG_MII
-+#define CONFIG_PHY_MARVELL
-+#define CONFIG_PHY_NATSEMI
-+#define CONFIG_NET_MULTI
-+#define CONFIG_PHY_REALTEK
-+#define CONFIG_NETCONSOLE	1
-+#define CONFIG_SERVERIP	172.25.229.115
-+#define CONFIG_IPADDR
-+
-+/* nor_flash - linear_flash */
-+#define CONFIG_SYS_FLASH_BASE	0x60000000
-+#define CONFIG_FLASH_END	0x68000000
-+#define CONFIG_SYS_MAX_FLASH_SECT	2048
-+#define CONFIG_SYS_FLASH_PROTECTION
-+#define CONFIG_SYS_FLASH_EMPTY_INFO
-+#define CONFIG_SYS_FLASH_CFI
-+#define CONFIG_FLASH_CFI_DRIVER
-+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-+#define CONFIG_SYS_MAX_FLASH_BANKS	1
-+
-+/* timer - axi_timer_0 */
-+
-+/* intc - microblaze_0_axi_intc */
-+
-+/* FPGA */
-+
-+/* Memory testing handling */
-+#define CONFIG_SYS_MEMTEST_START	0x80000000
-+#define CONFIG_SYS_MEMTEST_END	(0x80000000 + 0x1000)
-+#define CONFIG_SYS_LOAD_ADDR	0x80000000 /* default load address */
-+
-+/* global pointer options */
-+#define CONFIG_SYS_GBL_DATA_OFFSET	(0x40000000 - GENERATED_GBL_DATA_SIZE)
-+
-+/* Size of malloc() pool */
-+#define SIZE	0x100000
-+#define CONFIG_SYS_MALLOC_LEN	SIZE
-+#define CONFIG_SYS_MONITOR_LEN	SIZE
-+#define CONFIG_SYS_MONITOR_BASE	(0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
-+#define CONFIG_SYS_MALLOC_BASE	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-+
-+/* stack */
-+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
-+
-+/* No of_control support yet*/
-+
-+/* BOOTP options */
-+#define CONFIG_BOOTP_SERVERIP
-+#define CONFIG_BOOTP_BOOTFILESIZE
-+#define CONFIG_BOOTP_BOOTPATH
-+#define CONFIG_BOOTP_GATEWAY
-+#define CONFIG_BOOTP_HOSTNAME
-+#define CONFIG_BOOTP_MAY_FAIL
-+#define CONFIG_BOOTP_DNS
-+#define CONFIG_BOOTP_SUBNETMASK
-+#define CONFIG_BOOTP_PXE
- 
--/* uart */
--/* The following table includes the supported baudrates */
--# define CONFIG_SYS_BAUDRATE_TABLE \
--	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
--
--/* setting reset address */
--/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
--
--#define CONFIG_SYS_MALLOC_LEN	0xC0000
--
--/* Stack location before relocation */
--#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
--					 CONFIG_SYS_MALLOC_F_LEN)
--
--/*
-- * CFI flash memory layout - Example
-- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
-- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
-- *
-- * SECT_SIZE = 0x20000;			128kB is one sector
-- * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
-- *
-- * 0x2200_0000	CONFIG_SYS_FLASH_BASE
-- *					FREE		256kB
-- * 0x2204_0000	CONFIG_ENV_ADDR
-- *					ENV_AREA	128kB
-- * 0x2206_0000
-- *					FREE
-- * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
-- *
-- */
--
--#ifdef FLASH
--# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
--# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
--/* ?empty sector */
--# define CONFIG_SYS_FLASH_EMPTY_INFO	1
--/* max number of memory banks */
--# define CONFIG_SYS_MAX_FLASH_BANKS	1
--/* max number of sectors on one chip */
--# define CONFIG_SYS_MAX_FLASH_SECT	512
--/* hardware flash protection */
--/* use buffered writes (20x faster) */
--# ifdef	RAMENV
--#  define CONFIG_ENV_SIZE	0x1000
--#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
--
--# else	/* FLASH && !RAMENV */
--/* 128K(one sector) for env */
--#  define CONFIG_ENV_SECT_SIZE	0x20000
--#  define CONFIG_ENV_ADDR \
--			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
--#  define CONFIG_ENV_SIZE	0x20000
--# endif /* FLASH && !RAMBOOT */
--#else /* !FLASH */
--
--#ifdef SPIFLASH
--# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
--# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
--# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS
--
--# ifdef	RAMENV
--#  define CONFIG_ENV_SIZE	0x1000
--#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
--
--# else	/* SPIFLASH && !RAMENV */
--#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
--#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
--#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
--/* 128K(two sectors) for env */
--#  define CONFIG_ENV_SECT_SIZE	0x10000
--#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
--/* Warning: adjust the offset in respect of other flash content and size */
--#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
--# endif /* SPIFLASH && !RAMBOOT */
--#else /* !SPIFLASH */
--
--/* ENV in RAM */
--# define CONFIG_ENV_SIZE	0x1000
--# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
--#endif /* !SPIFLASH */
--#endif /* !FLASH */
--
--#if defined(XILINX_USE_ICACHE)
--# define CONFIG_ICACHE
--#else
--# undef CONFIG_ICACHE
--#endif
-+/*Command line configuration.*/
-+#define CONFIG_CMDLINE_EDITING
-+#define CONFIG_AUTO_COMPLETE
- 
--#if defined(XILINX_USE_DCACHE)
--# define CONFIG_DCACHE
--#else
--# undef CONFIG_DCACHE
--#endif
-+/* Miscellaneous configurable options */
-+#define CONFIG_SYS_CBSIZE	2048/* Console I/O Buffer Size      */
-+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- 
--#ifndef XILINX_DCACHE_BYTE_SIZE
--#define XILINX_DCACHE_BYTE_SIZE	32768
--#endif
- 
--/*
-- * BOOTP options
-- */
--#define CONFIG_BOOTP_BOOTFILESIZE
-+/* Use the HUSH parser */
-+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
- 
--#if defined(CONFIG_MTD_PARTITIONS)
--/* MTD partitions */
-+#define CONFIG_ENV_VARS_UBOOT_CONFIG
-+#define CONFIG_ENV_OVERWRITE	/* Allow to overwrite the u-boot environment variables */
- 
--/* default mtd partition table */
--#endif
-+#define CONFIG_LMB
- 
--/* size of console buffer */
--#define	CONFIG_SYS_CBSIZE	512
--/* max number of command args */
--#define	CONFIG_SYS_MAXARGS	15
--/* default load address */
--#define	CONFIG_SYS_LOAD_ADDR	0
-+/* FDT support */
-+#define CONFIG_DISPLAY_BOARDINFO_LATE
- 
--#define	CONFIG_HOSTNAME		"microblaze-generic"
--#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
- 
- /* architecture dependent code */
--#define	CONFIG_SYS_USR_EXCEP	/* user exception */
--
--#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
--
--#ifndef CONFIG_EXTRA_ENV_SETTINGS
--#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
--					"nor0=flash-0\0"\
--					"mtdparts=mtdparts=flash-0:"\
--					"256k(u-boot),256k(env),3m(kernel),"\
--					"1m(romfs),1m(cramfs),-(jffs2)\0"\
--					"nc=setenv stdout nc;"\
--					"setenv stdin nc\0" \
--					"serial=setenv stdout serial;"\
--					"setenv stdin serial\0"
--#endif
--
--/* Enable flat device tree support */
--#define CONFIG_LMB		1
-+#define CONFIG_SYS_USR_EXCEP    /* user exception */
-+#define CONFIG_SYS_HZ   1000
-+
-+/* Boot Argument Buffer Size */
-+#define CONFIG_SYS_MAXARGS     32      /* max number of command args */
-+#define CONFIG_SYS_LONGHELP
-+/* Initial memory map for Linux */
-+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
-+
-+/* Environment settings*/
-+#define CONFIG_ENV_ADDR	0x60b80000
-+#define CONFIG_ENV_SIZE	0x20000
-+#define CONFIG_ENV_SECT_SIZE	0x20000
-+/* PREBOOT */
-+#define CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
-+
-+/* Extra U-Boot Env settings */
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+	SERIAL_MULTI \ 
-+	CONSOLE_ARG \ 
-+	ESERIAL0 \ 
-+	"nc=setenv stdout nc;setenv stdin nc;\0" \ 
-+	"ethaddr=00:0a:35:00:22:01\0" \
-+	"autoload=no\0" \ 
-+	"sdbootdev=0\0" \ 
-+	"clobstart=0x81000000\0" \ 
-+	"netstart=0x81000000\0" \ 
-+	"dtbnetstart=0x82800000\0" \ 
-+	"loadaddr=0x81000000\0" \ 
-+	"bootsize=0x80000\0" \ 
-+	"bootstart=0x60b00000\0" \ 
-+	"boot_img=u-boot-s.bin\0" \ 
-+	"load_boot=tftpboot ${clobstart} ${boot_img}\0" \ 
-+	"update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \ 
-+	"install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && "  "cp.b ${clobstart} ${bootstart} ${filesize}\0" \ 
-+	"bootenvsize=0x20000\0" \ 
-+	"bootenvstart=0x60b80000\0" \ 
-+	"eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \ 
-+	"kernelsize=0xc00000\0" \ 
-+	"kernelstart=0x60ba0000\0" \ 
-+	"kernel_img=image.ub\0" \ 
-+	"load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ 
-+	"update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \ 
-+	"install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && "  "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \ 
-+	"cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \ 
-+	"fpgasize=0xb00000\0" \ 
-+	"fpgastart=0x60000000\0" \ 
-+	"fpga_img=system.bit.bin\0" \ 
-+	"load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \ 
-+	"update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \ 
-+	"install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && "  "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \ 
-+	"fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ 
-+	"test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ 
-+	"test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ 
-+	"netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ 
-+	"default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ 
-+""
-+/* BOOTCOMMAND */
-+#define CONFIG_BOOTCOMMAND	"run default_bootcmd"
- 
--#if defined(CONFIG_XILINX_AXIEMAC)
--# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
- #endif
--
--/* SPL part */
--
--#ifdef CONFIG_SYS_FLASH_BASE
--# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
--#endif
--
--/* for booting directly linux */
--
--#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
--					 0x40000)
--#define CONFIG_SYS_FDT_SIZE		(16 << 10)
--#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
--					 0x1000000)
--
--/* SP location before relocation, must use scratch RAM */
--/* BRAM start */
--#define CONFIG_SYS_INIT_RAM_ADDR	0x0
--/* BRAM size - will be generated */
--#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
--
--# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
--					 CONFIG_SYS_INIT_RAM_SIZE - \
--					 CONFIG_SYS_MALLOC_F_LEN)
--
--/* Just for sure that there is a space for stack */
--#define CONFIG_SPL_STACK_SIZE		0x100
--
--#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
--
--#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
--					 CONFIG_SYS_INIT_RAM_ADDR - \
--					 CONFIG_SYS_MALLOC_F_LEN - \
--					 CONFIG_SPL_STACK_SIZE)
--
--#endif	/* __CONFIG_H */
--- 
-2.7.5
-
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch
new file mode 100644
index 00000000..7e25f87c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2019.2/microblaze-kc705-Convert-microblaze-generic-to-k.patch
@@ -0,0 +1,1133 @@
+From afe880f500cff7a9486379c5ad7a4f3379015a62 Mon Sep 17 00:00:00 2001
+From: Jaewon Lee <jaewon.lee@xilinx.com>
+Date: Mon, 14 Jan 2019 11:30:56 -0800
+Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to
+ kc705-microblazeel
+
+This is an update to earlier kc705-trd patch done by Nathan Rossi.
+
+Change the microblaze-generic board to match the kc705-microblazeel.
+This patch is not intended for upstream and serves as an intermediate
+solution until OF support in upstream u-boot allows for easy support for
+custom microblaze boards.
+
+Signed-off-by: Jaewon Lee <jaewon.lee@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
+---
+ arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++-
+ board/xilinx/microblaze-generic/config.mk  |  28 +-
+ configs/microblaze-generic_defconfig       |  75 ++--
+ include/configs/microblaze-generic.h       | 348 ++++++++---------
+ 4 files changed, 782 insertions(+), 259 deletions(-)
+
+diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
+index 08a1396..f8e616b 100644
+--- a/arch/microblaze/dts/microblaze-generic.dts
++++ b/arch/microblaze/dts/microblaze-generic.dts
+@@ -1,9 +1,587 @@
+ /dts-v1/;
++
+ / {
+-	#address-cells = <1>;
+-	#size-cells = <1>;
+-	aliases {
+-	} ;
++	#address-cells = <0x1>;
++	#size-cells = <0x1>;
++	compatible = "xlnx,microblaze";
++	model = "Xilinx MicroBlaze";
++	hard-reset-gpios = <0x1 0x0 0x1>;
++
++	cpus {
++		#address-cells = <0x1>;
++		#cpus = <0x1>;
++		#size-cells = <0x0>;
++
++		cpu@0 {
++			bus-handle = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clocks = <0x3>;
++			compatible = "xlnx,microblaze-10.0";
++			d-cache-baseaddr = <0x80000000>;
++			d-cache-highaddr = <0xbfffffff>;
++			d-cache-line-size = <0x20>;
++			d-cache-size = <0x4000>;
++			device_type = "cpu";
++			i-cache-baseaddr = <0x80000000>;
++			i-cache-highaddr = <0xbfffffff>;
++			i-cache-line-size = <0x10>;
++			i-cache-size = <0x4000>;
++			interrupt-handle = <0x4>;
++			model = "microblaze,10.0";
++			timebase-frequency = <0xbebc200>;
++			xlnx,addr-size = <0x20>;
++			xlnx,addr-tag-bits = <0x10>;
++			xlnx,allow-dcache-wr = <0x1>;
++			xlnx,allow-icache-wr = <0x1>;
++			xlnx,area-optimized = <0x0>;
++			xlnx,async-interrupt = <0x1>;
++			xlnx,async-wakeup = <0x3>;
++			xlnx,avoid-primitives = <0x0>;
++			xlnx,base-vectors = <0x0>;
++			xlnx,branch-target-cache-size = <0x0>;
++			xlnx,cache-byte-size = <0x4000>;
++			xlnx,d-axi = <0x1>;
++			xlnx,d-lmb = <0x1>;
++			xlnx,d-lmb-mon = <0x0>;
++			xlnx,daddr-size = <0x20>;
++			xlnx,data-size = <0x20>;
++			xlnx,dc-axi-mon = <0x0>;
++			xlnx,dcache-addr-tag = <0x10>;
++			xlnx,dcache-always-used = <0x1>;
++			xlnx,dcache-byte-size = <0x4000>;
++			xlnx,dcache-data-width = <0x0>;
++			xlnx,dcache-force-tag-lutram = <0x0>;
++			xlnx,dcache-line-len = <0x8>;
++			xlnx,dcache-use-writeback = <0x0>;
++			xlnx,dcache-victims = <0x0>;
++			xlnx,debug-counter-width = <0x20>;
++			xlnx,debug-enabled = <0x1>;
++			xlnx,debug-event-counters = <0x5>;
++			xlnx,debug-external-trace = <0x0>;
++			xlnx,debug-interface = <0x0>;
++			xlnx,debug-latency-counters = <0x1>;
++			xlnx,debug-profile-size = <0x0>;
++			xlnx,debug-trace-async-reset = <0x0>;
++			xlnx,debug-trace-size = <0x2000>;
++			xlnx,div-zero-exception = <0x1>;
++			xlnx,dp-axi-mon = <0x0>;
++			xlnx,dynamic-bus-sizing = <0x0>;
++			xlnx,ecc-use-ce-exception = <0x0>;
++			xlnx,edge-is-positive = <0x1>;
++			xlnx,enable-discrete-ports = <0x0>;
++			xlnx,endianness = <0x1>;
++			xlnx,fault-tolerant = <0x0>;
++			xlnx,fpu-exception = <0x0>;
++			xlnx,freq = <0xbebc200>;
++			xlnx,fsl-exception = <0x0>;
++			xlnx,fsl-links = <0x0>;
++			xlnx,i-axi = <0x0>;
++			xlnx,i-lmb = <0x1>;
++			xlnx,i-lmb-mon = <0x0>;
++			xlnx,iaddr-size = <0x20>;
++			xlnx,ic-axi-mon = <0x0>;
++			xlnx,icache-always-used = <0x1>;
++			xlnx,icache-data-width = <0x0>;
++			xlnx,icache-force-tag-lutram = <0x0>;
++			xlnx,icache-line-len = <0x4>;
++			xlnx,icache-streams = <0x1>;
++			xlnx,icache-victims = <0x8>;
++			xlnx,ill-opcode-exception = <0x1>;
++			xlnx,imprecise-exceptions = <0x0>;
++			xlnx,instr-size = <0x20>;
++			xlnx,interconnect = <0x2>;
++			xlnx,interrupt-is-edge = <0x0>;
++			xlnx,interrupt-mon = <0x0>;
++			xlnx,ip-axi-mon = <0x0>;
++			xlnx,lockstep-master = <0x0>;
++			xlnx,lockstep-select = <0x0>;
++			xlnx,lockstep-slave = <0x0>;
++			xlnx,mmu-dtlb-size = <0x4>;
++			xlnx,mmu-itlb-size = <0x2>;
++			xlnx,mmu-privileged-instr = <0x0>;
++			xlnx,mmu-tlb-access = <0x3>;
++			xlnx,mmu-zones = <0x2>;
++			xlnx,num-sync-ff-clk = <0x2>;
++			xlnx,num-sync-ff-clk-debug = <0x2>;
++			xlnx,num-sync-ff-clk-irq = <0x1>;
++			xlnx,num-sync-ff-dbg-clk = <0x1>;
++			xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
++			xlnx,number-of-pc-brk = <0x1>;
++			xlnx,number-of-rd-addr-brk = <0x0>;
++			xlnx,number-of-wr-addr-brk = <0x0>;
++			xlnx,opcode-0x0-illegal = <0x1>;
++			xlnx,optimization = <0x0>;
++			xlnx,pc-width = <0x20>;
++			xlnx,piaddr-size = <0x20>;
++			xlnx,pvr = <0x2>;
++			xlnx,pvr-user1 = <0x0>;
++			xlnx,pvr-user2 = <0x0>;
++			xlnx,reset-msr = <0x0>;
++			xlnx,reset-msr-bip = <0x0>;
++			xlnx,reset-msr-dce = <0x0>;
++			xlnx,reset-msr-ee = <0x0>;
++			xlnx,reset-msr-eip = <0x0>;
++			xlnx,reset-msr-ice = <0x0>;
++			xlnx,reset-msr-ie = <0x0>;
++			xlnx,sco = <0x0>;
++			xlnx,trace = <0x0>;
++			xlnx,unaligned-exceptions = <0x1>;
++			xlnx,use-barrel = <0x1>;
++			xlnx,use-branch-target-cache = <0x0>;
++			xlnx,use-config-reset = <0x0>;
++			xlnx,use-dcache = <0x1>;
++			xlnx,use-div = <0x1>;
++			xlnx,use-ext-brk = <0x0>;
++			xlnx,use-ext-nm-brk = <0x0>;
++			xlnx,use-extended-fsl-instr = <0x0>;
++			xlnx,use-fpu = <0x0>;
++			xlnx,use-hw-mul = <0x2>;
++			xlnx,use-icache = <0x1>;
++			xlnx,use-interrupt = <0x2>;
++			xlnx,use-mmu = <0x3>;
++			xlnx,use-msr-instr = <0x1>;
++			xlnx,use-non-secure = <0x0>;
++			xlnx,use-pcmp-instr = <0x1>;
++			xlnx,use-reorder-instr = <0x1>;
++			xlnx,use-stack-protection = <0x0>;
++		};
++	};
++
++	clocks {
++		#address-cells = <0x1>;
++		#size-cells = <0x0>;
++
++		clk_cpu@0 {
++			#clock-cells = <0x0>;
++			clock-frequency = <0xbebc200>;
++			clock-output-names = "clk_cpu";
++			compatible = "fixed-clock";
++			reg = <0x0>;
++			linux,phandle = <0x3>;
++			phandle = <0x3>;
++		};
++
++		clk_bus_0@1 {
++			#clock-cells = <0x0>;
++			clock-frequency = <0xbebc200>;
++			clock-output-names = "clk_bus_0";
++			compatible = "fixed-clock";
++			reg = <0x1>;
++			linux,phandle = <0x8>;
++			phandle = <0x8>;
++		};
++	};
++
++	amba_pl {
++		#address-cells = <0x1>;
++		#size-cells = <0x1>;
++		compatible = "simple-bus";
++		ranges;
++		linux,phandle = <0x2>;
++		phandle = <0x2>;
++
++		ethernet@40c00000 {
++			axistream-connected = <0x5>;
++			axistream-control-connected = <0x5>;
++			clock-frequency = <0x5f5e100>;
++			compatible = "xlnx,axi-ethernet-1.00.a";
++			device_type = "network";
++			interrupt-names = "interrupt";
++			interrupt-parent = <0x4>;
++			interrupts = <0x4 0x2>;
++			phy-mode = "gmii";
++			reg = <0x40c00000 0x40000>;
++			xlnx = <0x0>;
++			xlnx,axiliteclkrate = <0x0>;
++			xlnx,axisclkrate = <0x0>;
++			xlnx,clockselection = <0x0>;
++			xlnx,enableasyncsgmii = <0x0>;
++			xlnx,gt-type = <0x0>;
++			xlnx,gtinex = <0x0>;
++			xlnx,gtlocation = <0x0>;
++			xlnx,gtrefclksrc = <0x0>;
++			xlnx,include-dre;
++			xlnx,instantiatebitslice0 = <0x0>;
++			xlnx,phy-type = <0x1>;
++			xlnx,phyaddr = <0x1>;
++			xlnx,rable = <0x0>;
++			xlnx,rxcsum = <0x0>;
++			xlnx,rxlane0-placement = <0x0>;
++			xlnx,rxlane1-placement = <0x0>;
++			xlnx,rxmem = <0x1000>;
++			xlnx,rxnibblebitslice0used = <0x0>;
++			xlnx,tx-in-upper-nibble = <0x1>;
++			xlnx,txcsum = <0x0>;
++			xlnx,txlane0-placement = <0x0>;
++			xlnx,txlane1-placement = <0x0>;
++			phy-handle = <0x6>;
++			local-mac-address = [00 0a 35 00 22 01];
++			linux,phandle = <0x7>;
++			phandle = <0x7>;
++
++			mdio {
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++
++				phy@7 {
++					device_type = "ethernet-phy";
++					reg = <0x7>;
++					linux,phandle = <0x6>;
++					phandle = <0x6>;
++				};
++			};
++		};
++
++		dma@41e00000 {
++			#dma-cells = <0x1>;
++			axistream-connected = <0x7>;
++			axistream-control-connected = <0x7>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_lite_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,eth-dma";
++			interrupt-names = "mm2s_introut", "s2mm_introut";
++			interrupt-parent = <0x4>;
++			interrupts = <0x3 0x2 0x2 0x2>;
++			reg = <0x41e00000 0x10000>;
++			xlnx,include-dre;
++			linux,phandle = <0x5>;
++			phandle = <0x5>;
++		};
++
++		timer@41c00000 {
++			clock-frequency = <0xbebc200>;
++			clocks = <0x8>;
++			compatible = "xlnx,xps-timer-1.00.a";
++			interrupt-names = "interrupt";
++			interrupt-parent = <0x4>;
++			interrupts = <0x5 0x2>;
++			reg = <0x41c00000 0x10000>;
++			xlnx,count-width = <0x20>;
++			xlnx,gen0-assert = <0x1>;
++			xlnx,gen1-assert = <0x1>;
++			xlnx,one-timer-only = <0x0>;
++			xlnx,trig0-assert = <0x1>;
++			xlnx,trig1-assert = <0x1>;
++		};
++
++		gpio@40010000 {
++			#gpio-cells = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,xps-gpio-1.00.a";
++			gpio-controller;
++			reg = <0x40010000 0x10000>;
++			xlnx,all-inputs = <0x1>;
++			xlnx,all-inputs-2 = <0x0>;
++			xlnx,all-outputs = <0x0>;
++			xlnx,all-outputs-2 = <0x0>;
++			xlnx,dout-default = <0x0>;
++			xlnx,dout-default-2 = <0x0>;
++			xlnx,gpio-width = <0x1>;
++			xlnx,gpio2-width = <0x20>;
++			xlnx,interrupt-present = <0x0>;
++			xlnx,is-dual = <0x0>;
++			xlnx,tri-default = <0xffffffff>;
++			xlnx,tri-default-2 = <0xffffffff>;
++		};
++
++		gpio@40020000 {
++			#gpio-cells = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,xps-gpio-1.00.a";
++			gpio-controller;
++			reg = <0x40020000 0x10000>;
++			xlnx,all-inputs = <0x1>;
++			xlnx,all-inputs-2 = <0x0>;
++			xlnx,all-outputs = <0x0>;
++			xlnx,all-outputs-2 = <0x0>;
++			xlnx,dout-default = <0x0>;
++			xlnx,dout-default-2 = <0x0>;
++			xlnx,gpio-width = <0x4>;
++			xlnx,gpio2-width = <0x20>;
++			xlnx,interrupt-present = <0x0>;
++			xlnx,is-dual = <0x0>;
++			xlnx,tri-default = <0xffffffff>;
++			xlnx,tri-default-2 = <0xffffffff>;
++		};
++
++		i2c@40800000 {
++			#address-cells = <0x1>;
++			#size-cells = <0x0>;
++			clock-frequency = <0xbebc200>;
++			clocks = <0x8>;
++			compatible = "xlnx,xps-iic-2.00.a";
++			interrupt-names = "iic2intc_irpt";
++			interrupt-parent = <0x4>;
++			interrupts = <0x1 0x2>;
++			reg = <0x40800000 0x10000>;
++
++			i2cswitch@74 {
++				compatible = "nxp,pca9548";
++				#address-cells = <0x1>;
++				#size-cells = <0x0>;
++				reg = <0x74>;
++
++				i2c@0 {
++					#address-cells = <0x1>;
++					#size-cells = <0x0>;
++					reg = <0x0>;
++
++					clock-generator@5d {
++						#clock-cells = <0x0>;
++						compatible = "silabs,si570";
++						temperature-stability = <0x32>;
++						reg = <0x5d>;
++						factory-fout = <0x9502f90>;
++						clock-frequency = <0x8d9ee20>;
++					};
++				};
++
++				i2c@3 {
++					#address-cells = <0x1>;
++					#size-cells = <0x0>;
++					reg = <0x3>;
++
++					eeprom@54 {
++						compatible = "at,24c08";
++						reg = <0x54>;
++					};
++				};
++			};
++		};
++
++		gpio@40030000 {
++			#gpio-cells = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,xps-gpio-1.00.a";
++			gpio-controller;
++			reg = <0x40030000 0x10000>;
++			xlnx,all-inputs = <0x0>;
++			xlnx,all-inputs-2 = <0x0>;
++			xlnx,all-outputs = <0x1>;
++			xlnx,all-outputs-2 = <0x0>;
++			xlnx,dout-default = <0x0>;
++			xlnx,dout-default-2 = <0x0>;
++			xlnx,gpio-width = <0x8>;
++			xlnx,gpio2-width = <0x20>;
++			xlnx,interrupt-present = <0x0>;
++			xlnx,is-dual = <0x0>;
++			xlnx,tri-default = <0xffffffff>;
++			xlnx,tri-default-2 = <0xffffffff>;
++		};
++
++		flash@60000000 {
++			bank-width = <0x2>;
++			compatible = "cfi-flash";
++			reg = <0x60000000 0x8000000>;
++			xlnx,axi-clk-period-ps = <0x1388>;
++			xlnx,include-datawidth-matching-0 = <0x1>;
++			xlnx,include-datawidth-matching-1 = <0x1>;
++			xlnx,include-datawidth-matching-2 = <0x1>;
++			xlnx,include-datawidth-matching-3 = <0x1>;
++			xlnx,include-negedge-ioregs = <0x0>;
++			xlnx,lflash-period-ps = <0x1388>;
++			xlnx,linear-flash-sync-burst = <0x0>;
++			xlnx,max-mem-width = <0x10>;
++			xlnx,mem-a-lsb = <0x0>;
++			xlnx,mem-a-msb = <0x1f>;
++			xlnx,mem0-type = <0x2>;
++			xlnx,mem0-width = <0x10>;
++			xlnx,mem1-type = <0x0>;
++			xlnx,mem1-width = <0x10>;
++			xlnx,mem2-type = <0x0>;
++			xlnx,mem2-width = <0x10>;
++			xlnx,mem3-type = <0x0>;
++			xlnx,mem3-width = <0x10>;
++			xlnx,num-banks-mem = <0x1>;
++			xlnx,page-size = <0x10>;
++			xlnx,parity-type-mem-0 = <0x0>;
++			xlnx,parity-type-mem-1 = <0x0>;
++			xlnx,parity-type-mem-2 = <0x0>;
++			xlnx,parity-type-mem-3 = <0x0>;
++			xlnx,port-diff = <0x0>;
++			xlnx,s-axi-en-reg = <0x0>;
++			xlnx,s-axi-mem-addr-width = <0x20>;
++			xlnx,s-axi-mem-data-width = <0x20>;
++			xlnx,s-axi-mem-id-width = <0x1>;
++			xlnx,s-axi-reg-addr-width = <0x5>;
++			xlnx,s-axi-reg-data-width = <0x20>;
++			xlnx,synch-pipedelay-0 = <0x1>;
++			xlnx,synch-pipedelay-1 = <0x1>;
++			xlnx,synch-pipedelay-2 = <0x1>;
++			xlnx,synch-pipedelay-3 = <0x1>;
++			xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
++			xlnx,tavdv-ps-mem-1 = <0x3a98>;
++			xlnx,tavdv-ps-mem-2 = <0x3a98>;
++			xlnx,tavdv-ps-mem-3 = <0x3a98>;
++			xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
++			xlnx,tcedv-ps-mem-1 = <0x3a98>;
++			xlnx,tcedv-ps-mem-2 = <0x3a98>;
++			xlnx,tcedv-ps-mem-3 = <0x3a98>;
++			xlnx,thzce-ps-mem-0 = <0x88b8>;
++			xlnx,thzce-ps-mem-1 = <0x1b58>;
++			xlnx,thzce-ps-mem-2 = <0x1b58>;
++			xlnx,thzce-ps-mem-3 = <0x1b58>;
++			xlnx,thzoe-ps-mem-0 = <0x1b58>;
++			xlnx,thzoe-ps-mem-1 = <0x1b58>;
++			xlnx,thzoe-ps-mem-2 = <0x1b58>;
++			xlnx,thzoe-ps-mem-3 = <0x1b58>;
++			xlnx,tlzwe-ps-mem-0 = <0xc350>;
++			xlnx,tlzwe-ps-mem-1 = <0x0>;
++			xlnx,tlzwe-ps-mem-2 = <0x0>;
++			xlnx,tlzwe-ps-mem-3 = <0x0>;
++			xlnx,tpacc-ps-flash-0 = <0x61a8>;
++			xlnx,tpacc-ps-flash-1 = <0x61a8>;
++			xlnx,tpacc-ps-flash-2 = <0x61a8>;
++			xlnx,tpacc-ps-flash-3 = <0x61a8>;
++			xlnx,twc-ps-mem-0 = <0x11170>;
++			xlnx,twc-ps-mem-1 = <0x3a98>;
++			xlnx,twc-ps-mem-2 = <0x3a98>;
++			xlnx,twc-ps-mem-3 = <0x3a98>;
++			xlnx,twp-ps-mem-0 = <0x13880>;
++			xlnx,twp-ps-mem-1 = <0x2ee0>;
++			xlnx,twp-ps-mem-2 = <0x2ee0>;
++			xlnx,twp-ps-mem-3 = <0x2ee0>;
++			xlnx,twph-ps-mem-0 = <0x13880>;
++			xlnx,twph-ps-mem-1 = <0x2ee0>;
++			xlnx,twph-ps-mem-2 = <0x2ee0>;
++			xlnx,twph-ps-mem-3 = <0x2ee0>;
++			xlnx,use-startup = <0x0>;
++			xlnx,use-startup-int = <0x0>;
++			xlnx,wr-rec-time-mem-0 = <0x186a0>;
++			xlnx,wr-rec-time-mem-1 = <0x6978>;
++			xlnx,wr-rec-time-mem-2 = <0x6978>;
++			xlnx,wr-rec-time-mem-3 = <0x6978>;
++			#address-cells = <0x1>;
++			#size-cells = <0x1>;
++
++			partition@0x00000000 {
++				label = "fpga";
++				reg = <0x0 0xb00000>;
++			};
++
++			partition@0x00b00000 {
++				label = "boot";
++				reg = <0xb00000 0x80000>;
++			};
++
++			partition@0x00b80000 {
++				label = "bootenv";
++				reg = <0xb80000 0x20000>;
++			};
++
++			partition@0x00ba0000 {
++				label = "kernel";
++				reg = <0xba0000 0xc00000>;
++			};
++
++			partition@0x017a0000 {
++				label = "spare";
++				reg = <0x17a0000 0x0>;
++			};
++		};
++
++		interrupt-controller@41200000 {
++			#interrupt-cells = <0x2>;
++			compatible = "xlnx,xps-intc-1.00.a";
++			interrupt-controller;
++			reg = <0x41200000 0x10000>;
++			xlnx,kind-of-intr = <0x0>;
++			xlnx,num-intr-inputs = <0x6>;
++			linux,phandle = <0x4>;
++			phandle = <0x4>;
++		};
++
++		gpio@40040000 {
++			#gpio-cells = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,xps-gpio-1.00.a";
++			gpio-controller;
++			reg = <0x40040000 0x10000>;
++			xlnx,all-inputs = <0x1>;
++			xlnx,all-inputs-2 = <0x0>;
++			xlnx,all-outputs = <0x0>;
++			xlnx,all-outputs-2 = <0x0>;
++			xlnx,dout-default = <0x0>;
++			xlnx,dout-default-2 = <0x0>;
++			xlnx,gpio-width = <0x5>;
++			xlnx,gpio2-width = <0x20>;
++			xlnx,interrupt-present = <0x0>;
++			xlnx,is-dual = <0x0>;
++			xlnx,tri-default = <0xffffffff>;
++			xlnx,tri-default-2 = <0xffffffff>;
++		};
++
++		gpio@40000000 {
++			#gpio-cells = <0x2>;
++			clock-frequency = <0xbebc200>;
++			clock-names = "s_axi_aclk";
++			clocks = <0x8>;
++			compatible = "xlnx,xps-gpio-1.00.a";
++			gpio-controller;
++			reg = <0x40000000 0x10000>;
++			xlnx,all-inputs = <0x0>;
++			xlnx,all-inputs-2 = <0x0>;
++			xlnx,all-outputs = <0x1>;
++			xlnx,all-outputs-2 = <0x0>;
++			xlnx,dout-default = <0x0>;
++			xlnx,dout-default-2 = <0x0>;
++			xlnx,gpio-width = <0x1>;
++			xlnx,gpio2-width = <0x20>;
++			xlnx,interrupt-present = <0x0>;
++			xlnx,is-dual = <0x0>;
++			xlnx,tri-default = <0xffffffff>;
++			xlnx,tri-default-2 = <0xffffffff>;
++			linux,phandle = <0x1>;
++			phandle = <0x1>;
++		};
++
++		serial@44a00000 {
++			clock-frequency = <0xbebc200>;
++			clocks = <0x8>;
++			compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
++			current-speed = <0x1c200>;
++			device_type = "serial";
++			interrupt-names = "ip2intc_irpt";
++			interrupt-parent = <0x4>;
++			interrupts = <0x0 0x2>;
++			port-number = <0x0>;
++			reg = <0x44a00000 0x10000>;
++			reg-offset = <0x1000>;
++			reg-shift = <0x2>;
++			xlnx,external-xin-clk-hz = <0x17d7840>;
++			xlnx,external-xin-clk-hz-d = <0x19>;
++			xlnx,has-external-rclk = <0x0>;
++			xlnx,has-external-xin = <0x0>;
++			xlnx,is-a-16550 = <0x1>;
++			xlnx,s-axi-aclk-freq-hz-d = "200.0";
++			xlnx,use-modem-ports = <0x1>;
++			xlnx,use-user-ports = <0x1>;
++		};
++	};
++
+ 	chosen {
+-	} ;
+-} ;
++		bootargs = "console=ttyS0,115200 earlyprintk";
++		stdout-path = "serial0:115200n8";
++	};
++
++	aliases {
++		ethernet0 = "/amba_pl/ethernet@40c00000";
++		i2c0 = "/amba_pl/i2c@40800000";
++		serial0 = "/amba_pl/serial@44a00000";
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x80000000 0x40000000>;
++	};
++};
++
+diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
+index a953977..cb75fde 100644
+--- a/board/xilinx/microblaze-generic/config.mk
++++ b/board/xilinx/microblaze-generic/config.mk
+@@ -1,18 +1,10 @@
+-# SPDX-License-Identifier: GPL-2.0+
+-#
+-# (C) Copyright 2007 - 2016 Michal Simek
+-#
+-# Michal SIMEK <monstr@monstr.eu>
+-
+-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+-
+-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+-
+-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+-
+-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
++TEXT_BASE = 0x80400000
++CONFIG_SYS_TEXT_BASE = 0x80400000
++
++PLATFORM_CPPFLAGS += -mxl-barrel-shift
++PLATFORM_CPPFLAGS += -mno-xl-soft-div
++PLATFORM_CPPFLAGS += -mxl-pattern-compare
++PLATFORM_CPPFLAGS += -mxl-multiply-high
++PLATFORM_CPPFLAGS += -mno-xl-soft-mul
++PLATFORM_CPPFLAGS += -mcpu=v11.0
++PLATFORM_CPPFLAGS += -fgnu89-inline
+diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
+index 02e62e2..8d64be4 100644
+--- a/configs/microblaze-generic_defconfig
++++ b/configs/microblaze-generic_defconfig
+@@ -1,73 +1,58 @@
+ CONFIG_MICROBLAZE=y
+-CONFIG_SYS_TEXT_BASE=0x29000000
+ CONFIG_SPL_LIBCOMMON_SUPPORT=y
+ CONFIG_SPL_LIBGENERIC_SUPPORT=y
+ CONFIG_SPL_SERIAL_SUPPORT=y
+-CONFIG_SPL=y
+ CONFIG_TARGET_MICROBLAZE_GENERIC=y
+ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+ CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+ CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+ CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
+-CONFIG_NR_DRAM_BANKS=1
++CONFIG_SYS_TEXT_BASE=0x80400000
++CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
+ CONFIG_FIT=y
+ CONFIG_FIT_VERBOSE=y
+-CONFIG_BOOTDELAY=-1
+-CONFIG_USE_BOOTARGS=y
+-CONFIG_BOOTARGS="root=romfs"
++CONFIG_BOOTDELAY=4
+ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+-CONFIG_DISPLAY_BOARDINFO=y
+-CONFIG_SPL_BOARD_INIT=y
+-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+ CONFIG_SPL_NOR_SUPPORT=y
+ CONFIG_SPL_OS_BOOT=y
+ CONFIG_SYS_OS_BASE=0x2c060000
+ CONFIG_HUSH_PARSER=y
+-# CONFIG_AUTO_COMPLETE is not set
+-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
+-CONFIG_CMD_IMLS=y
+-CONFIG_CMD_SPL=y
++CONFIG_SYS_PROMPT="U-Boot> "
+ CONFIG_CMD_ASKENV=y
+-CONFIG_CMD_GPIO=y
+ CONFIG_CMD_SAVES=y
+ # CONFIG_CMD_SETEXPR is not set
++CONFIG_SYS_ENET=y
++CONFIG_NET=y
++CONFIG_NETDEVICES=y
++CONFIG_CMD_NET=y
+ CONFIG_CMD_DHCP=y
+-CONFIG_CMD_TFTPPUT=y
++CONFIG_CMD_NFS=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_JFFS2=y
+-CONFIG_SPL_OF_CONTROL=y
+ CONFIG_OF_EMBED=y
+-CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
+-CONFIG_NETCONSOLE=y
+-CONFIG_SPL_DM=y
++CONFIG_DM_ETH=y
++CONFIG_SYS_MALLOC_F=y
++CONFIG_SYS_GENERIC_BOARD=y
++CONFIG_XILINX_AXIEMAC=y
++CONFIG_SYS_NS16550=y
++CONFIG_CMD_FLASH=y
++CONFIG_MTD_NOR_FLASH=y
++CONFIG_CMD_IMLS=y
++CONFIG_CMD_GPIO=y
+ CONFIG_DM_GPIO=y
+ CONFIG_XILINX_GPIO=y
+-CONFIG_LED=y
+-CONFIG_LED_GPIO=y
+-CONFIG_MTD_NOR_FLASH=y
+-CONFIG_MTD_DEVICE=y
+-CONFIG_FLASH_CFI_DRIVER=y
+-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+-CONFIG_FLASH_CFI_MTD=y
+-CONFIG_SYS_FLASH_PROTECTION=y
+-CONFIG_SYS_FLASH_CFI=y
+-CONFIG_PHY_ATHEROS=y
+-CONFIG_PHY_BROADCOM=y
+-CONFIG_PHY_DAVICOM=y
+-CONFIG_PHY_LXT=y
+-CONFIG_PHY_MARVELL=y
++CONFIG_CMD_TFTPPUT=y
++CONFIG_NETCONSOLE=y
++CONFIG_XILINX_FSL_LINKS=0
++CONFIG_PHY_GIGE=y
++CONFIG_ENV_IS_IN_FLASH=y
+ CONFIG_PHY_MICREL=y
+ CONFIG_PHY_MICREL_KSZ90X1=y
+-CONFIG_PHY_NATSEMI=y
+-CONFIG_PHY_REALTEK=y
+-CONFIG_PHY_VITESSE=y
+-CONFIG_DM_ETH=y
+-CONFIG_XILINX_AXIEMAC=y
+-CONFIG_XILINX_EMACLITE=y
+-CONFIG_SYS_NS16550=y
+-CONFIG_XILINX_UARTLITE=y
+-CONFIG_SYSRESET_GPIO=y
+-CONFIG_SYSRESET_MICROBLAZE=y
+-CONFIG_WDT=y
+-CONFIG_XILINX_TB_WATCHDOG=y
++CONFIG_SPL_DM_SERIAL=y
++CONFIG_SPL_OF_LIBFDT=y
++CONFIG_PHY_XILINX=y
++# CONFIG_SPL is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_BOOTARGS is not set
++# CONFIG_USE_BOOTARGS is not set
+diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
+index ba0952c..fd1da2b 100644
+--- a/include/configs/microblaze-generic.h
++++ b/include/configs/microblaze-generic.h
+@@ -1,205 +1,173 @@
+-/* SPDX-License-Identifier: GPL-2.0+ */
+-/*
+- * (C) Copyright 2007-2010 Michal Simek
+- *
+- * Michal SIMEK <monstr@monstr.eu>
+- */
+-
+ #ifndef __CONFIG_H
+ #define __CONFIG_H
+ 
+-#include "../board/xilinx/microblaze-generic/xparameters.h"
+-
+-/* MicroBlaze CPU */
+-#define	MICROBLAZE_V5		1
+-
+-/* linear and spi flash memory */
+-#ifdef XILINX_FLASH_START
+-#define	FLASH
+-#undef	SPIFLASH
+-#undef	RAMENV	/* hold environment in flash */
+-#else
+-#undef	FLASH
+-#undef	SPIFLASH
+-#define	RAMENV	/* hold environment in RAM */
+-#endif
++#define CONFIG_SYS_BAUDRATE_TABLE  { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
++
++/* processor - microblaze_0 */
++#define XILINX_USE_MSR_INSTR	1
++#define XILINX_USE_ICACHE	1
++#define XILINX_USE_DCACHE	1
++#define XILINX_DCACHE_BYTE_SIZE	16384
++#define XILINX_PVR	2
++#define MICROBLAZE_V5
++#define CONFIG_CMD_IRQ
++#define CONFIG_DCACHE
++#define CONFIG_ICACHE
++
++/* main_memory - ddr3_sdram */
++
++
++/* uart - rs232_uart */
++#define CONFIG_SYS_NS16550_COM1	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
++#define CONFIG_SYS_NS16550_REG_SIZE	-4
++#define CONSOLE_ARG	"console=console=ttyS0,115200\0"
++#define CONFIG_SYS_NS16550_SERIAL
++#define CONFIG_CONS_INDEX	1
++#define ESERIAL0	"eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
++#define SERIAL_MULTI  "serial=setenv stdout serial;setenv stdin serial\0"
++#define CONFIG_SYS_NS16550_CLK	200000000
++#define CONFIG_BAUDRATE	115200
++
++/* ethernet - axi_ethernet */
++#define CONFIG_PHY_XILINX
++#define CONFIG_MII
++#define CONFIG_PHY_MARVELL
++#define CONFIG_PHY_NATSEMI
++#define CONFIG_NET_MULTI
++#define CONFIG_PHY_REALTEK
++#define CONFIG_NETCONSOLE	1
++#define CONFIG_SERVERIP	172.25.229.115
++#define CONFIG_IPADDR
++
++/* nor_flash - linear_flash */
++#define CONFIG_SYS_FLASH_BASE	0x60000000
++#define CONFIG_FLASH_END	0x68000000
++#define CONFIG_SYS_MAX_FLASH_SECT	2048
++#define CONFIG_SYS_FLASH_PROTECTION
++#define CONFIG_SYS_FLASH_EMPTY_INFO
++#define CONFIG_SYS_FLASH_CFI
++#define CONFIG_FLASH_CFI_DRIVER
++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
++#define CONFIG_SYS_MAX_FLASH_BANKS	1
++
++/* timer - axi_timer_0 */
++
++/* intc - microblaze_0_axi_intc */
++
++/* FPGA */
++
++/* Memory testing handling */
++#define CONFIG_SYS_MEMTEST_START	0x80000000
++#define CONFIG_SYS_MEMTEST_END	(0x80000000 + 0x1000)
++#define CONFIG_SYS_LOAD_ADDR	0x80000000 /* default load address */
++
++/* global pointer options */
++#define CONFIG_SYS_GBL_DATA_OFFSET	(0x40000000 - GENERATED_GBL_DATA_SIZE)
++
++/* Size of malloc() pool */
++#define SIZE	0x100000
++#define CONFIG_SYS_MALLOC_LEN	SIZE
++#define CONFIG_SYS_MONITOR_LEN	SIZE
++#define CONFIG_SYS_MONITOR_BASE	(0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
++#define CONFIG_SYS_MALLOC_BASE	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
++
++/* stack */
++#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
++
++/* No of_control support yet*/
++
++/* BOOTP options */
++#define CONFIG_BOOTP_SERVERIP
++#define CONFIG_BOOTP_BOOTFILESIZE
++#define CONFIG_BOOTP_BOOTPATH
++#define CONFIG_BOOTP_GATEWAY
++#define CONFIG_BOOTP_HOSTNAME
++#define CONFIG_BOOTP_MAY_FAIL
++#define CONFIG_BOOTP_DNS
++#define CONFIG_BOOTP_SUBNETMASK
++#define CONFIG_BOOTP_PXE
+ 
+-/* uart */
+-/* The following table includes the supported baudrates */
+-# define CONFIG_SYS_BAUDRATE_TABLE \
+-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+-
+-/* setting reset address */
+-/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
+-
+-#define CONFIG_SYS_MALLOC_LEN	0xC0000
+-
+-/* Stack location before relocation */
+-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
+-					 CONFIG_SYS_MALLOC_F_LEN)
+-
+-/*
+- * CFI flash memory layout - Example
+- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
+- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
+- *
+- * SECT_SIZE = 0x20000;			128kB is one sector
+- * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
+- *
+- * 0x2200_0000	CONFIG_SYS_FLASH_BASE
+- *					FREE		256kB
+- * 0x2204_0000	CONFIG_ENV_ADDR
+- *					ENV_AREA	128kB
+- * 0x2206_0000
+- *					FREE
+- * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
+- *
+- */
+-
+-#ifdef FLASH
+-# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
+-# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
+-/* ?empty sector */
+-# define CONFIG_SYS_FLASH_EMPTY_INFO	1
+-/* max number of memory banks */
+-# define CONFIG_SYS_MAX_FLASH_BANKS	1
+-/* max number of sectors on one chip */
+-# define CONFIG_SYS_MAX_FLASH_SECT	512
+-/* hardware flash protection */
+-/* use buffered writes (20x faster) */
+-# ifdef	RAMENV
+-#  define CONFIG_ENV_SIZE	0x1000
+-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-
+-# else	/* FLASH && !RAMENV */
+-/* 128K(one sector) for env */
+-#  define CONFIG_ENV_SECT_SIZE	0x20000
+-#  define CONFIG_ENV_ADDR \
+-			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+-#  define CONFIG_ENV_SIZE	0x20000
+-# endif /* FLASH && !RAMBOOT */
+-#else /* !FLASH */
+-
+-#ifdef SPIFLASH
+-# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+-# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
+-# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS
+-
+-# ifdef	RAMENV
+-#  define CONFIG_ENV_SIZE	0x1000
+-#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-
+-# else	/* SPIFLASH && !RAMENV */
+-#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+-#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+-#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+-/* 128K(two sectors) for env */
+-#  define CONFIG_ENV_SECT_SIZE	0x10000
+-#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
+-/* Warning: adjust the offset in respect of other flash content and size */
+-#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
+-# endif /* SPIFLASH && !RAMBOOT */
+-#else /* !SPIFLASH */
+-
+-/* ENV in RAM */
+-# define CONFIG_ENV_SIZE	0x1000
+-# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+-#endif /* !SPIFLASH */
+-#endif /* !FLASH */
+-
+-#if defined(XILINX_USE_ICACHE)
+-# define CONFIG_ICACHE
+-#else
+-# undef CONFIG_ICACHE
+-#endif
++/*Command line configuration.*/
++#define CONFIG_CMDLINE_EDITING
++#define CONFIG_AUTO_COMPLETE
+ 
+-#if defined(XILINX_USE_DCACHE)
+-# define CONFIG_DCACHE
+-#else
+-# undef CONFIG_DCACHE
+-#endif
++/* Miscellaneous configurable options */
++#define CONFIG_SYS_CBSIZE	2048/* Console I/O Buffer Size      */
++#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ 
+-#ifndef XILINX_DCACHE_BYTE_SIZE
+-#define XILINX_DCACHE_BYTE_SIZE	32768
+-#endif
+ 
+-/*
+- * BOOTP options
+- */
+-#define CONFIG_BOOTP_BOOTFILESIZE
++/* Use the HUSH parser */
++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+ 
+-#if defined(CONFIG_MTD_PARTITIONS)
+-/* MTD partitions */
++#define CONFIG_ENV_VARS_UBOOT_CONFIG
++#define CONFIG_ENV_OVERWRITE	/* Allow to overwrite the u-boot environment variables */
+ 
+-/* default mtd partition table */
+-#endif
++#define CONFIG_LMB
+ 
+-/* size of console buffer */
+-#define	CONFIG_SYS_CBSIZE	512
+-/* max number of command args */
+-#define	CONFIG_SYS_MAXARGS	15
+-/* default load address */
+-#define	CONFIG_SYS_LOAD_ADDR	0
++/* FDT support */
++#define CONFIG_DISPLAY_BOARDINFO_LATE
+ 
+-#define	CONFIG_HOSTNAME		"microblaze-generic"
+-#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
+ 
+ /* architecture dependent code */
+-#define	CONFIG_SYS_USR_EXCEP	/* user exception */
+-
+-#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
+-
+-#ifndef CONFIG_EXTRA_ENV_SETTINGS
+-#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
+-					"nor0=flash-0\0"\
+-					"mtdparts=mtdparts=flash-0:"\
+-					"256k(u-boot),256k(env),3m(kernel),"\
+-					"1m(romfs),1m(cramfs),-(jffs2)\0"\
+-					"nc=setenv stdout nc;"\
+-					"setenv stdin nc\0" \
+-					"serial=setenv stdout serial;"\
+-					"setenv stdin serial\0"
+-#endif
+-
+-/* Enable flat device tree support */
+-#define CONFIG_LMB		1
++#define CONFIG_SYS_USR_EXCEP    /* user exception */
++#define CONFIG_SYS_HZ   1000
++
++/* Boot Argument Buffer Size */
++#define CONFIG_SYS_MAXARGS     32      /* max number of command args */
++#define CONFIG_SYS_LONGHELP
++/* Initial memory map for Linux */
++#define CONFIG_SYS_BOOTMAPSZ 0x8000000
++
++/* Environment settings*/
++#define CONFIG_ENV_ADDR	0x60b80000
++#define CONFIG_ENV_SIZE	0x20000
++#define CONFIG_ENV_SECT_SIZE	0x20000
++/* PREBOOT */
++#define CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
++
++/* Extra U-Boot Env settings */
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	SERIAL_MULTI \ 
++	CONSOLE_ARG \ 
++	ESERIAL0 \ 
++	"nc=setenv stdout nc;setenv stdin nc;\0" \ 
++	"ethaddr=00:0a:35:00:22:01\0" \
++	"autoload=no\0" \ 
++	"sdbootdev=0\0" \ 
++	"clobstart=0x81000000\0" \ 
++	"netstart=0x81000000\0" \ 
++	"dtbnetstart=0x82800000\0" \ 
++	"loadaddr=0x81000000\0" \ 
++	"bootsize=0x80000\0" \ 
++	"bootstart=0x60b00000\0" \ 
++	"boot_img=u-boot-s.bin\0" \ 
++	"load_boot=tftpboot ${clobstart} ${boot_img}\0" \ 
++	"update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \ 
++	"install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && "  "cp.b ${clobstart} ${bootstart} ${filesize}\0" \ 
++	"bootenvsize=0x20000\0" \ 
++	"bootenvstart=0x60b80000\0" \ 
++	"eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \ 
++	"kernelsize=0xc00000\0" \ 
++	"kernelstart=0x60ba0000\0" \ 
++	"kernel_img=image.ub\0" \ 
++	"load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ 
++	"update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \ 
++	"install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && "  "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \ 
++	"cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \ 
++	"fpgasize=0xb00000\0" \ 
++	"fpgastart=0x60000000\0" \ 
++	"fpga_img=system.bit.bin\0" \ 
++	"load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \ 
++	"update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \ 
++	"install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && "  "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \ 
++	"fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ 
++	"test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ 
++	"test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ 
++	"netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ 
++	"default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ 
++""
++/* BOOTCOMMAND */
++#define CONFIG_BOOTCOMMAND	"run default_bootcmd"
+ 
+-#if defined(CONFIG_XILINX_AXIEMAC)
+-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+ #endif
+-
+-/* SPL part */
+-
+-#ifdef CONFIG_SYS_FLASH_BASE
+-# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
+-#endif
+-
+-/* for booting directly linux */
+-
+-#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+-					 0x40000)
+-#define CONFIG_SYS_FDT_SIZE		(16 << 10)
+-#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
+-					 0x1000000)
+-
+-/* SP location before relocation, must use scratch RAM */
+-/* BRAM start */
+-#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+-/* BRAM size - will be generated */
+-#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+-
+-# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+-					 CONFIG_SYS_INIT_RAM_SIZE - \
+-					 CONFIG_SYS_MALLOC_F_LEN)
+-
+-/* Just for sure that there is a space for stack */
+-#define CONFIG_SPL_STACK_SIZE		0x100
+-
+-#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+-
+-#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
+-					 CONFIG_SYS_INIT_RAM_ADDR - \
+-					 CONFIG_SYS_MALLOC_F_LEN - \
+-					 CONFIG_SPL_STACK_SIZE)
+-
+-#endif	/* __CONFIG_H */
+-- 
+2.7.5
+
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb
deleted file mode 100644
index 3377635d..00000000
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.1.bb
+++ /dev/null
@@ -1,32 +0,0 @@
-UBOOT_VERSION = "v2019.01"
-XILINX_RELEASE_VERSION = "v2019.1"
-
-UBRANCH ?= "master"
-
-SRCREV ?= "d895ac5e94815d4b45dcf09d4752c5c2334a51db"
-
-include u-boot-xlnx.inc
-include u-boot-spl-zynq-init.inc
-
-SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
-
-LICENSE = "GPLv2+"
-LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
-
-# u-boot-xlnx has support for these
-HAS_PLATFORM_INIT ?= " \
-		zynq_microzed_config \
-		zynq_zed_config \
-		zynq_zc702_config \
-		zynq_zc706_config \
-		zynq_zybo_config \
-		xilinx_zynqmp_zcu102_rev1_0_config \
-		xilinx_zynqmp_zcu106_revA_config \
-		xilinx_zynqmp_zcu104_revC_config \
-		xilinx_zynqmp_zcu100_revC_config \
-		xilinx_zynqmp_zcu111_revA_config \
-		xilinx_zynqmp_zc1275_revA_config \
-		xilinx_zynqmp_zc1275_revB_config \
-		xilinx_zynqmp_zc1254_revA_config \
-		"
-
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb
new file mode 100644
index 00000000..712b2528
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2019.2.bb
@@ -0,0 +1,31 @@
+UBOOT_VERSION = "v2019.01"
+
+UBRANCH ?= "master"
+
+SRCREV ?= "dc61275b1d505f6a236de1c5b0f35485914d2bcc"
+
+include u-boot-xlnx.inc
+include u-boot-spl-zynq-init.inc
+
+SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
+
+# u-boot-xlnx has support for these
+HAS_PLATFORM_INIT ?= " \
+		zynq_microzed_config \
+		zynq_zed_config \
+		zynq_zc702_config \
+		zynq_zc706_config \
+		zynq_zybo_config \
+		xilinx_zynqmp_zcu102_rev1_0_config \
+		xilinx_zynqmp_zcu106_revA_config \
+		xilinx_zynqmp_zcu104_revC_config \
+		xilinx_zynqmp_zcu100_revC_config \
+		xilinx_zynqmp_zcu111_revA_config \
+		xilinx_zynqmp_zc1275_revA_config \
+		xilinx_zynqmp_zc1275_revB_config \
+		xilinx_zynqmp_zc1254_revA_config \
+		"
+
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch b/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch
new file mode 100644
index 00000000..97cf71d9
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/files/0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch
@@ -0,0 +1,105 @@
+From 4fdb6551ea8856cc2df25d33e4103bf1736d7935 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= <berrange@redhat.com>
+Date: Wed, 20 Nov 2019 13:53:16 -0800
+Subject: [PATCH] The glibc-2.29.9000-6.fc31.x86_64 package finally includes
+ the gettid() function as part of unistd.h when __USE_GNU is defined. This
+ clashes with linux-user code which unconditionally defines this function name
+ itself.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+/home/berrange/src/virt/qemu/linux-user/syscall.c:253:16: error: static
+declaration of ‘gettid’ follows non-static declaration
+  253 | _syscall0(int, gettid)
+      |                ^~~~~~
+/home/berrange/src/virt/qemu/linux-user/syscall.c:184:13: note: in
+definition of macro ‘_syscall0’
+  184 | static type name (void)   \
+      |             ^~~~
+In file included from /usr/include/unistd.h:1170,
+                 from
+/home/berrange/src/virt/qemu/include/qemu/osdep.h:107,
+                 from
+/home/berrange/src/virt/qemu/linux-user/syscall.c:20:
+/usr/include/bits/unistd_ext.h:34:16: note: previous declaration of
+‘gettid’ was here
+   34 | extern __pid_t gettid (void) __THROW;
+      |                ^~~~~~
+  CC      aarch64-linux-user/linux-user/signal.o
+make[1]: *** [/home/berrange/src/virt/qemu/rules.mak:69:
+linux-user/syscall.o] Error 1
+make[1]: *** Waiting for unfinished jobs....
+make: *** [Makefile:449: subdir-aarch64-linux-user] Error 2
+
+While we could make our definition conditional and rely on glibc's impl,
+this patch simply renames our definition to sys_gettid() which is a
+common pattern in this file.
+
+Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
+Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+---
+ linux-user/syscall.c | 15 ++++++++-------
+ 1 file changed, 8 insertions(+), 7 deletions(-)
+
+diff --git a/linux-user/syscall.c b/linux-user/syscall.c
+index 11c9116..464c3b9 100644
+--- a/linux-user/syscall.c
++++ b/linux-user/syscall.c
+@@ -34,6 +34,7 @@
+ #include <sys/resource.h>
+ #include <sys/swap.h>
+ #include <linux/capability.h>
++#include <linux/sockios.h>
+ #include <sched.h>
+ #include <sys/timex.h>
+ #ifdef __ia64__
+@@ -256,12 +257,12 @@ static type name (type1 arg1,type2 arg2,type3 arg3,type4 arg4,type5 arg5,	\
+ #define TARGET_NR__llseek TARGET_NR_llseek
+ #endif
+ 
+-#ifdef __NR_gettid
+-_syscall0(int, gettid)
++#ifdef __NR_sys_gettid
++_syscall0(int, sys_gettid)
+ #else
+ /* This is a replacement for the host gettid() and must return a host
+    errno. */
+-static int gettid(void) {
++static int sys_gettid(void) {
+     return -ENOSYS;
+ }
+ #endif
+@@ -6246,7 +6247,7 @@ static void *clone_func(void *arg)
+     cpu = ENV_GET_CPU(env);
+     thread_cpu = cpu;
+     ts = (TaskState *)cpu->opaque;
+-    info->tid = gettid();
++    info->tid = sys_gettid();
+     task_settid(ts);
+     if (info->child_tidptr)
+         put_user_u32(info->tid, info->child_tidptr);
+@@ -6390,9 +6391,9 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
+                mapping.  We can't repeat the spinlock hack used above because
+                the child process gets its own copy of the lock.  */
+             if (flags & CLONE_CHILD_SETTID)
+-                put_user_u32(gettid(), child_tidptr);
++                put_user_u32(sys_gettid(), child_tidptr);
+             if (flags & CLONE_PARENT_SETTID)
+-                put_user_u32(gettid(), parent_tidptr);
++                put_user_u32(sys_gettid(), parent_tidptr);
+             ts = (TaskState *)cpu->opaque;
+             if (flags & CLONE_SETTLS)
+                 cpu_set_tls (env, newtls);
+@@ -11454,7 +11455,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
+         break;
+ #endif
+     case TARGET_NR_gettid:
+-        ret = get_errno(gettid());
++        ret = get_errno(sys_gettid());
+         break;
+ #ifdef TARGET_NR_readahead
+     case TARGET_NR_readahead:
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb
deleted file mode 100644
index 06481660..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.1.bb
+++ /dev/null
@@ -1,6 +0,0 @@
-require qemu-devicetrees.inc
-
-XILINX_RELEASE_VERSION = "v2019.1"
-
-BRANCH ?= "branch/xilinx-v2019.1"
-SRCREV ?= "445406ef4d06303f00387f7d81e8718255336fd0"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb
new file mode 100644
index 00000000..22f19bfd
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-devicetrees_2019.2.bb
@@ -0,0 +1,4 @@
+require qemu-devicetrees.inc
+
+BRANCH ?= "branch/xilinx-v2019.2"
+SRCREV ?= "d119986a6dd800bc3e71ea171b5b6741e0128289"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc
index aae607f5..438b9246 100644
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native.inc
@@ -3,5 +3,5 @@ require qemu-xilinx.inc
 
 DEPENDS = "glib-2.0-native zlib-native"
 
-SRC_URI_remove = "file://0012-fix-libcap-header-issue-on-some-distro.patch"
-SRC_URI_remove = "file://0013-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch"
\ No newline at end of file
+SRC_URI_remove = "file://0010-fix-libcap-header-issue-on-some-distro.patch"
+SRC_URI_remove = "file://0011-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb
deleted file mode 100644
index bc5a3850..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.1.bb
+++ /dev/null
@@ -1,7 +0,0 @@
-require qemu-xilinx-native.inc
-BPN = "qemu-xilinx"
-
-EXTRA_OECONF_append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent"
-
-
-SRC_URI_append = "file://0001-linux-user-disable-qemu-bridge-helper-and-socket_scm.patch"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb
new file mode 100644
index 00000000..2814de0c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-native_2019.2.bb
@@ -0,0 +1,6 @@
+require qemu-xilinx-native.inc
+BPN = "qemu-xilinx"
+
+EXTRA_OECONF_append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent"
+
+SRC_URI_append = " file://0001-linux-user-disable-qemu-bridge-helper-and-socket_scm.patch"
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb
deleted file mode 100644
index a138704e..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.1.bb
+++ /dev/null
@@ -1,16 +0,0 @@
-require qemu-xilinx-native.inc
-
-EXTRA_OECONF_append = " --target-list=${@get_qemu_system_target_list(d)}"
-
-PACKAGECONFIG ??= "fdt alsa kvm"
-
-PACKAGECONFIG_remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}"
-
-DEPENDS += "pixman-native qemu-xilinx-native"
-
-do_install_append() {
-    # The following is also installed by qemu-native
-    rm -f ${D}${datadir}/${BPN}/trace-events-all
-    rm -rf ${D}${datadir}/${BPN}/keymaps
-}
-
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb
new file mode 100644
index 00000000..93afebed
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx-system-native_2019.2.bb
@@ -0,0 +1,17 @@
+require qemu-xilinx-native.inc
+
+EXTRA_OECONF_append = " --target-list=${@get_qemu_system_target_list(d)}"
+
+PACKAGECONFIG ??= "fdt alsa kvm"
+
+PACKAGECONFIG_remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}"
+
+DEPENDS += "pixman-native qemu-xilinx-native"
+
+do_install_append() {
+    # The following is also installed by qemu-native
+    rm -f ${D}${datadir}/${BPN}/trace-events-all
+    rm -rf ${D}${datadir}/${BPN}/keymaps
+    rm -rf ${D}${datadir}/icons
+}
+
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc
index ad44f098..657d6422 100644
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx.inc
@@ -3,18 +3,17 @@ HOMEPAGE = "https://github.com/xilinx/qemu/"
 
 QEMU_TARGETS = "aarch64 arm microblaze microblazeel"
 
-XILINX_RELEASE_VERSION = "v2019.1"
-XILINX_QEMU_VERSION ?= "v2.11.1"
-BRANCH ?= "branch/xilinx-v2019.1"
-SRCREV ?= "5f38ea92fb697b94ad43f01fe162f3ed6e6b0e16"
-
-
 LIC_FILES_CHKSUM = " \
 		file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \
 		file://COPYING.LIB;endline=24;md5=c04def7ae38850e7d3ef548588159913 \
 		"
 DEPENDS = "glib-2.0 zlib pixman"
 
+XILINX_RELEASE_VERSION = "v2019.2"
+XILINX_QEMU_VERSION ?= "v2.11.1"
+BRANCH ?= "branch/xilinx-v2019.2"
+SRCREV ?= "6617fbc8be3525ca524f7d4ef7fc7b14c5b0c822"
+
 FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
 
 PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
@@ -24,13 +23,19 @@ REPO ?= "git://github.com/Xilinx/qemu.git;protocol=https"
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
 
+SRC_URI_append = " file://0001-The-glibc-2.29.9000-6.fc31.x86_64-package-finally-in.patch"
+
 S = "${WORKDIR}/git"
 
+EXTRA_OECONF_append= " --python=python2.7"
+
 # Disable KVM completely
 PACKAGECONFIG_remove = "kvm"
+PACKAGECONFIG_append = " fdt"
+PACKAGECONFIG[ssh] = "--enable-libssh,,"
 
 # Enable libgcrypt
-PACKAGECONFIG_append = " gcrypt"
+PACKAGECONFIG_append = " gcrypt fdt alsa kvm"
 
 DISABLE_STATIC_pn-${PN} = ""
 
@@ -50,4 +55,4 @@ do_configure_prepend() {
 do_install_append() {
 	# Prevent QA warnings about installed ${localstatedir}/run
 	if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi
-}
\ No newline at end of file
+}
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch
new file mode 100644
index 00000000..a8ab7daa
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch
@@ -0,0 +1,93 @@
+From 5214dd4461f2090ef0965b4d2518f49927d61cbc Mon Sep 17 00:00:00 2001
+From: He Zhe <zhe.he@windriver.com>
+Date: Wed, 28 Aug 2019 19:56:28 +0800
+Subject: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
+
+libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
+handling for libgcrypt.
+
+Upstream-Status: Denied [https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg06333.html]
+
+Signed-off-by: He Zhe <zhe.he@windriver.com>
+---
+ configure | 48 ++++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 40 insertions(+), 8 deletions(-)
+
+diff --git a/configure b/configure
+index e44e454..0f362a7 100755
+--- a/configure
++++ b/configure
+@@ -2875,6 +2875,30 @@ has_libgcrypt() {
+     return 0
+ }
+ 
++has_libgcrypt_pkgconfig() {
++    if ! has $pkg_config ; then
++        return 1
++    fi
++
++    if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
++        return 1
++    fi
++
++    if test -n "$cross_prefix" ; then
++        host=$($pkg_config --variable=host libgcrypt)
++        if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
++            print_error "host($host) does not match cross_prefix($cross_prefix)"
++            return 1
++        fi
++    fi
++
++    if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
++        print_error "libgcrypt version is $($pkg_config --modversion libgcrypt)"
++        return 1
++    fi
++
++    return 0
++}
+ 
+ if test "$nettle" != "no"; then
+     pass="no"
+@@ -2902,7 +2926,14 @@ fi
+ 
+ if test "$gcrypt" != "no"; then
+     pass="no"
+-    if has_libgcrypt; then
++    if has_libgcrypt_pkgconfig; then
++        gcrypt_cflags=$($pkg_config --cflags libgcrypt)
++        if test "$static" = "yes" ; then
++            gcrypt_libs=$($pkg_config --libs --static libgcrypt)
++        else
++            gcrypt_libs=$($pkg_config --libs libgcrypt)
++        fi
++    elif has_libgcrypt; then
+         gcrypt_cflags=$(libgcrypt-config --cflags)
+         gcrypt_libs=$(libgcrypt-config --libs)
+         # Debian has removed -lgpg-error from libgcrypt-config
+@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
+         then
+             gcrypt_libs="$gcrypt_libs -lgpg-error"
+         fi
++    fi
+ 
+-        # Link test to make sure the given libraries work (e.g for static).
+-        write_c_skeleton
+-        if compile_prog "" "$gcrypt_libs" ; then
+-            LIBS="$gcrypt_libs $LIBS"
+-            QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+-            pass="yes"
+-        fi
++    # Link test to make sure the given libraries work (e.g for static).
++    write_c_skeleton
++    if compile_prog "" "$gcrypt_libs" ; then
++	    LIBS="$gcrypt_libs $LIBS"
++	    QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
++	    pass="yes"
+     fi
++
+     if test "$pass" = "yes"; then
+         gcrypt="yes"
+         cat > $TMPC << EOF
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb
deleted file mode 100644
index c158b185..00000000
--- a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.1.bb
+++ /dev/null
@@ -1,13 +0,0 @@
-require recipes-devtools/qemu/qemu.inc
-require qemu-xilinx.inc
-
-BBCLASSEXTEND = "nativesdk"
-
-RDEPENDS_${PN}_class-target += "bash"
-
-EXTRA_OECONF_append_class-target = " --target-list=${@get_qemu_target_list(d)}"
-EXTRA_OECONF_append_class-nativesdk = " --target-list=${@get_qemu_target_list(d)}"
-
-do_install_append_class-nativesdk() {
-    ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)}
-}
diff --git a/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb
new file mode 100644
index 00000000..d540f6c3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-devtools/qemu/qemu-xilinx_2019.2.bb
@@ -0,0 +1,14 @@
+require recipes-devtools/qemu/qemu.inc
+require qemu-xilinx.inc
+
+BBCLASSEXTEND = "nativesdk"
+
+RDEPENDS_${PN}_class-target += "bash"
+
+EXTRA_OECONF_append_class-target = " --target-list=${@get_qemu_target_list(d)}"
+EXTRA_OECONF_append_class-nativesdk = " --target-list=${@get_qemu_target_list(d)}"
+
+do_install_append_class-nativesdk() {
+    ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)}
+}
+
diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb
deleted file mode 100644
index 5bac31e9..00000000
--- a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.1.bb
+++ /dev/null
@@ -1,7 +0,0 @@
-LINUX_VERSION = "4.19"
-XILINX_RELEASE_VERSION = "v2019.1"
-KBRANCH ?= "xlnx_rebase_v4.19"
-SRCREV ?= "9811303824b66a8db9a8ec61b570879336a9fde5"
-
-include linux-xlnx.inc
-
diff --git a/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb
new file mode 100644
index 00000000..58f163c4
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2019.2.bb
@@ -0,0 +1,6 @@
+LINUX_VERSION = "4.19"
+KBRANCH ?= "xlnx_rebase_v4.19"
+SRCREV ?= "b983d5fd71d4feaf494cdbe0593ecc29ed471cb8"
+
+include linux-xlnx.inc
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
deleted file mode 100644
index 5d29531d..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 7fbf19ba660c72a1d4817780cad5c4ae52cbe0b5 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 13:13:57 +0530
-Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
- Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
-Conflicts:
-
-	gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
----
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 9f0b24a..1cb4f97 100644
---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
-    lappend additional_flags "-Wl,--allow-multiple-definition"
- }
- 
-+<<<<<<< HEAD
-+=======
-+if [istarget "microblaze*-*-linux*"] {
-+   lappend additional_flags "-Wl,-zmuldefs"
-+   lappend additional_flags "-fPIC"
-+}
-+
-+>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
- foreach src [lsort [find $srcdir/$subdir *.c]] {
-     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
- 	c-torture-execute [list $src \
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
deleted file mode 100644
index 503b1ecf..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 4b675eeabceea22ec51abfa7c37e11a631e58659 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 14:31:10 +0530
-Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
- particular testcase fails with a timeout. Instead, fail it at compile-time
- for microblaze. This speeds up the testsuite without removing it from the
- FAIL reports.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C
-index 66411cd..d951fee 100644
---- a/gcc/testsuite/g++.dg/opt/memcpy1.C
-+++ b/gcc/testsuite/g++.dg/opt/memcpy1.C
-@@ -4,6 +4,10 @@
- // { dg-do compile }
- // { dg-options "-O" }
- 
-+#if defined (__MICROBLAZE__)
-+#error "too slow on mb. Investigate."
-+#endif
-+
- typedef unsigned char uint8_t;
- typedef uint8_t uint8;
- __extension__ typedef __SIZE_TYPE__ size_t;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
deleted file mode 100644
index 39058496..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From 03d4d7335be2b2f72c199ab5177685b6dfd1a9d6 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:28:38 +0530
-Subject: [PATCH 03/54] [LOCAL]: Testsuite - explicitly add -fivopts for tests
- that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt
- exist in 4.6 branch)
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
- gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-index 438db88..ede883e 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
--/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
- 
- void test (int *b, int *e, int stride)
-   {
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-index 07ff1b7..a09710c 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-@@ -1,5 +1,5 @@
- // { dg-do compile }
--// { dg-options "-O2 -fdump-tree-ivopts-details" }
-+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
- 
- class MinimalVec3
- {
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-index bda2516..22c8a5d 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-index f0770ab..65d74c8 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-index 5f42857..9bc86ee 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-@@ -1,7 +1,7 @@
- /* A test for induction variable merging.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- 
- void foo(long);
- 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-index 0fa5600..94caa44 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */
-+/* { dg-options "-O2 -fivopts -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */
- extern void g(void);
- 
- void
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-index 2c6cfc6..648e6e6 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fdump-tree-ivopts" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
- 
- void vnum_test8(int *data) 
- { 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-index e911bfc..5d3e7e0 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-Os -fdump-tree-optimized" } */
-+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
- 
- /* Slightly changed testcase from PR middle-end/40815.  */
- void bar(char*, char*, int);
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
deleted file mode 100644
index e16528b6..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From a4c99f7f7775f105eb6f1dfbdf304e6b7e498e2e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:46:28 +0530
-Subject: [PATCH 04/54] [LOCAL]: For dejagnu static testing on qemu, suppress
- warnings about multiple definitions from the test function and libc in line
- with method used by powerpc. Dynamic linking and using a qemu binary which
- understands sysroot resolves all test failures with builtins
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
- 1 file changed, 4 deletions(-)
-
-diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 1cb4f97..bdfa08a 100644
---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
-    lappend additional_flags "-Wl,--allow-multiple-definition"
- }
- 
--<<<<<<< HEAD
--=======
- if [istarget "microblaze*-*-linux*"] {
-    lappend additional_flags "-Wl,-zmuldefs"
--   lappend additional_flags "-fPIC"
- }
- 
-->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
- foreach src [lsort [find $srcdir/$subdir *.c]] {
-     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
- 	c-torture-execute [list $src \
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
deleted file mode 100644
index 33688f14..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 6b0de6811796b6834d426263eaa855b65c9b3389 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:50:35 +0530
-Subject: [PATCH 05/54] [Patch, testsuite]: Add MicroBlaze to target-supports
- for atomic buil. .tin tests
-
-MicroBlaze added to supported targets for atomic builtin tests.
-
-Changelog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/lib/target-supports.exp: Add microblaze to
-   check_effective_target_sync_int_long.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/lib/target-supports.exp | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index c591acd..94353cc 100644
---- a/gcc/testsuite/lib/target-supports.exp
-+++ b/gcc/testsuite/lib/target-supports.exp
-@@ -7428,6 +7428,7 @@ proc check_effective_target_sync_int_long { } {
- 		 && [check_effective_target_arm_acq_rel])
- 	     || [istarget bfin*-*linux*]
- 	     || [istarget hppa*-*linux*]
-+	     || [istarget microblaze*-*linux*]
- 	     || [istarget s390*-*-*] 
- 	     || [istarget powerpc*-*-*]
- 	     || [istarget crisv32-*-*] || [istarget cris-*-*]
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
deleted file mode 100644
index b428d121..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Sat, 26 Aug 2017 19:21:18 -0700
-Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
- it
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
-Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
-Upstream-Status: Pending
----
- gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
- gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-index 438db88204..ede883eb28 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
--/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
- 
- void test (int *b, int *e, int stride)
-   {
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-index eb72581390..02f3ea4a7d 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-@@ -1,5 +1,5 @@
- // { dg-do compile }
--// { dg-options "-O2 -fdump-tree-ivopts-details" }
-+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
- 
- class MinimalVec3
- {
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-index bda2516735..22c8a5dcff 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-index f0770abdbb..65d74c8e62 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-index 5f42857fe1..9bc86ee0d2 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-@@ -1,7 +1,7 @@
- /* A test for induction variable merging.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- 
- void foo(long);
- 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-index 3c8ee06016..db192a657f 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
-+/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
- extern void g(void);
- 
- void
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-index 2c6cfc6f83..648e6e67e8 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fdump-tree-ivopts" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
- 
- void vnum_test8(int *data) 
- { 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-index e911bfcd52..5d3e7e0801 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-Os -fdump-tree-optimized" } */
-+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
- 
- /* Slightly changed testcase from PR middle-end/40815.  */
- void bar(char*, char*, int);
--- 
-2.14.2
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
deleted file mode 100644
index 3e2368f2..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 0d2cca275f3e85ae42dac7888d862975d65ffb36 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 16:20:01 +0530
-Subject: [PATCH 06/54] [Patch, testsuite]: Update MicroBlaze strings test for
- new scan-assembly output resulting in use of $LC label
-
-ChangeLog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
-   to include $LC label.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-index 7a63faf..0403b7b 100644
---- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-@@ -1,13 +1,15 @@
- /* { dg-options "-O3" } */
- 
-+/* { dg-final { scan-assembler "\.rodata*" } } */
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
-+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
-+
- #include <string.h>
- 
--/* { dg-final { scan-assembler "\.rodata*" } } */
- extern void somefunc (char *);
- int testfunc ()
- {
-     char string2[80];
--/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
-     strcpy (string2, "hello");
-     somefunc (string2);
- }
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
deleted file mode 100644
index bcd5dbad..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
+++ /dev/null
@@ -1,67 +0,0 @@
-From b6f828da3caa827d8ccc08bbf260a2a01b2b2613 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:14:15 +0530
-Subject: [PATCH 07/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
- in regex match Extend regex pattern to include optional ext at the end of
- .weak to match the MicroBlaze weak label .weakext
-
-ChangeLog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
-   pattern to take optional ext after .weak.
- * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
-Conflicts:
-
-	gcc/testsuite/g++.dg/abi/rtti3.C
----
- gcc/testsuite/g++.dg/abi/rtti3.C  | 4 ++--
- gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
- gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
- 3 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
-index 0cc7d3e..f284cd9 100644
---- a/gcc/testsuite/g++.dg/abi/rtti3.C
-+++ b/gcc/testsuite/g++.dg/abi/rtti3.C
-@@ -3,8 +3,8 @@
- 
- // { dg-require-weak "" }
- // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
--// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
--// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
- // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
- 
-diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
-index f2347f7..dcec8a7 100644
---- a/gcc/testsuite/g++.dg/abi/thunk3.C
-+++ b/gcc/testsuite/g++.dg/abi/thunk3.C
-@@ -1,5 +1,5 @@
- // { dg-require-weak "" }
--// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
- 
- struct Base 
-diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
-index 6e8f124..d1d34fe 100644
---- a/gcc/testsuite/g++.dg/abi/thunk4.C
-+++ b/gcc/testsuite/g++.dg/abi/thunk4.C
-@@ -1,6 +1,6 @@
- // { dg-require-weak "" }
- // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
--// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
- 
- struct Base 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
deleted file mode 100644
index 6232535d..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From d27a2545486da9c6a4d3d5ca06b4affb83f8d0a1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:34:27 +0530
-Subject: [PATCH 08/54] [Patch, testsuite]: Add MicroBlaze to
- check_profiling_available Testsuite, add microblaze*-*-* target in
- check_profiling_available inline with other archs setting
- profiling_available_saved to 0
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/lib/target-supports.exp | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 94353cc..ecfbe4d 100644
---- a/gcc/testsuite/lib/target-supports.exp
-+++ b/gcc/testsuite/lib/target-supports.exp
-@@ -676,6 +676,7 @@ proc check_profiling_available { test_what } {
- 	     || [istarget m68k-*-elf]
- 	     || [istarget m68k-*-uclinux*]
- 	     || [istarget mips*-*-elf*]
-+	     || [istarget microblaze*-*-*]
- 	     || [istarget mmix-*-*]
- 	     || [istarget mn10300-*-elf*]
- 	     || [istarget moxie-*-elf*]
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch
deleted file mode 100644
index db730f43..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 8711bdfe27bce04d35ba93a1d18ccccd61371829 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:41:43 +0530
-Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In
- atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
- during optimization. Previously, the outputs were considered unused; this
- generated assembly code with undefined side effects after invocation of the
- atomic.
-
-Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.md |  3 +++
- gcc/config/microblaze/sync.md       | 21 +++++++++++++--------
- 2 files changed, 16 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index f698e54..93f5fa2 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -41,6 +41,9 @@
-   (UNSPEC_CMP		104)    ;; signed compare
-   (UNSPEC_CMPU		105)    ;; unsigned compare
-   (UNSPEC_TLS           106)    ;; jump table
-+  (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
-+  (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
-+  (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
- ])
- 
- (define_c_enum "unspec" [
-diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index b34bd54..8e694e9 100644
---- a/gcc/config/microblaze/sync.md
-+++ b/gcc/config/microblaze/sync.md
-@@ -18,14 +18,19 @@
- ;; <http://www.gnu.org/licenses/>.
- 
- (define_insn "atomic_compare_and_swapsi"
--  [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
--   (match_operand:SI 1 "register_operand" "=&d")	;; val output
--   (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
--   (match_operand:SI 3 "register_operand" "d")		;; expected value
--   (match_operand:SI 4 "register_operand" "d")		;; desired value
--   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
--   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
--   (match_operand:SI 7 "const_int_operand" "")		;; mod_f
-+  [(set (match_operand:SI 0 "register_operand" "=&d")		;; bool output
-+        (unspec_volatile:SI
-+          [(match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
-+           (match_operand:SI 3 "register_operand" "d")		;; expected value
-+           (match_operand:SI 4 "register_operand" "d")]		;; desired value
-+          UNSPECV_CAS_BOOL))
-+   (set (match_operand:SI 1 "register_operand" "=&d")		;; val output
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
-+   (set (match_dup 2)
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
-+   (match_operand:SI 5 "const_int_operand" "")			;; is_weak
-+   (match_operand:SI 6 "const_int_operand" "")			;; mod_s
-+   (match_operand:SI 7 "const_int_operand" "")			;; mod_f
-    (clobber (match_scratch:SI 8 "=&d"))]
-   ""
-   {
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
deleted file mode 100644
index 5058529a..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 92015c19e5d1baabd62067bf1cfc4522e85d1b25 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:45:45 +0530
-Subject: [PATCH 10/54] [Patch, microblaze]: Fix atomic boolean return value.
- In atomic_compare_and_swapsi, fix boolean return value. Previously, it
- contained zero if successful and non-zero if unsuccessful.
-
-Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/sync.md | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 8e694e9..8ddb10d 100644
---- a/gcc/config/microblaze/sync.md
-+++ b/gcc/config/microblaze/sync.md
-@@ -34,15 +34,16 @@
-    (clobber (match_scratch:SI 8 "=&d"))]
-   ""
-   {
--    output_asm_insn ("addc \tr0,r0,r0", operands);
-+    output_asm_insn ("add  \t%0,r0,r0", operands);
-     output_asm_insn ("lwx  \t%1,%y2,r0", operands);
-     output_asm_insn ("addic\t%8,r0,0", operands);
-     output_asm_insn ("bnei \t%8,.-8", operands);
--    output_asm_insn ("cmp  \t%0,%1,%3", operands);
--    output_asm_insn ("bnei \t%0,.+16", operands);
-+    output_asm_insn ("cmp  \t%8,%1,%3", operands);
-+    output_asm_insn ("bnei \t%8,.+20", operands);
-     output_asm_insn ("swx  \t%4,%y2,r0", operands);
-     output_asm_insn ("addic\t%8,r0,0", operands);
-     output_asm_insn ("bnei \t%8,.-28", operands);
-+    output_asm_insn ("addi \t%0,r0,1", operands);
-     return "";
-   }
- )
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
deleted file mode 100644
index 2451c938..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 658476aef537c0c2d031eb1c7a001f00c1d9bf7b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:50:17 +0530
-Subject: [PATCH 11/54] [Patch, microblaze]: Fix the Microblaze crash with
- msmall-divides flag Compiler is crashing when we use msmall-divides and
- mxl-barrel-shift flag. This is because when use above flags
- microblaze_expand_divide function will be called for division operation. In
- microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't
- have subreg register due to this compiler was crashing. Changed the logic to
- avoid sub_reg call
-
-Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 9a4a287..cbe8cb7 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3575,8 +3575,7 @@ microblaze_expand_divide (rtx operands[])
-   mem_rtx = gen_rtx_MEM (QImode,
-                             gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
- 
--  insn = emit_insn (gen_movqi (regqi, mem_rtx)); 
--  insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
-+  insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
-   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-   JUMP_LABEL (jump) = div_end_label;
-   LABEL_NUSES (div_end_label) = 1; 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
deleted file mode 100644
index b58df873..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:52:56 +0530
-Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
- ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
- optimization is used. lshrsi3_with_size_opt is being removed as it has
- conflicts with unsigned int variables
-
-Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 93f5fa2..fe90a14 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1506,6 +1506,27 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+(define_insn "*ashrsi3_with_size_opt"
-+  [(set (match_operand:SI 0 "register_operand" "=&d")
-+       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-+                   (match_operand:SI 2 "immediate_operand" "I")))]
-+  "(INTVAL (operands[2]) > 5 && optimize_size)"
-+  {
-+    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("ori\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addik\t%3,%3,-1", operands);
-+    output_asm_insn ("bneid\t%3,.-4", operands);
-+    return "sra\t%0,%0";
-+  }
-+  [(set_attr "type"    "arith")
-+  (set_attr "mode"    "SI")
-+  (set_attr "length"  "20")]
-+)
-+
- (define_insn "*ashrsi_inline"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
deleted file mode 100644
index 6af0f10e..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From ed23e22fb25a2d3dc357c0743f51b2735fc46a6a Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 17:50:03 +0530
-Subject: [PATCH 13/54] [Patch, microblaze]: Fixed missing save of r18 in
- fast_interrupt. Register 18 is used as a clobber register, and must be stored
- when entering a fast_interrupt. Before this fix, register 18 was only saved
- if it was used directly in the interrupt function.
-
-However, if the fast_interrupt function called a function that used
-r18, the register would not be saved, and thus be mangled
-upon returning from the interrupt.
-
-Changelog
-
-2014-02-27  Klaus Petersen <klauspetersen@gmail.com>
-
- * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
-   microblaze_must_save_register.
-
-Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index cbe8cb7..6f0b4f4 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -1967,7 +1967,7 @@ microblaze_must_save_register (int regno)
-     {
-       if (df_regs_ever_live_p (regno) 
- 	  || regno == MB_ABI_MSR_SAVE_REG
--	  || (interrupt_handler
-+	  || ((interrupt_handler || fast_interrupt)
-               && (regno == MB_ABI_ASM_TEMP_REGNUM
- 	          || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
- 	return 1;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
deleted file mode 100644
index f47265b0..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 582558f3c18d096885ab24e645899f310b148b5c Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 10:57:19 +0530
-Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls
- Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-
----
- gcc/config/microblaze/microblaze.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0d3718f..88e0351 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -486,7 +486,7 @@ typedef struct microblaze_args
- 
- #define FUNCTION_PROFILER(FILE, LABELNO) { \
-   {                                        \
--    fprintf (FILE, "\tbrki\tr16,_mcount\n");           \
-+    fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n");         \
-   }                                                    \
-  }
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch
deleted file mode 100644
index acfa083f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From b60068cbdd3c830e541fbd35f2ed119245911461 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 11:10:21 +0530
-Subject: [PATCH 15/54] [Patch, microblaze]: Disable fivopts by default Turn
- off ivopts by default. Interferes with cse.
-
-Changelog
-
-2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-
- * gcc/common/config/microblaze/microblaze-common.c
-   (microblaze_option_optimization_table): Disable fivopts by default.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 3e75675..fe45f2e 100644
---- a/gcc/common/config/microblaze/microblaze-common.c
-+++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -24,6 +24,15 @@
- #include "common/common-target.h"
- #include "common/common-target-def.h"
- 
-+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
-+static const struct default_options microblaze_option_optimization_table[] =
-+  {
-+    /* Turn off ivopts by default. It messes up cse. */
-+    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
-+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-+    { OPT_LEVELS_NONE, 0, NULL, 0 }
-+  };
-+
- #undef TARGET_DEFAULT_TARGET_FLAGS
- #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch
deleted file mode 100644
index dbd7b2e2..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 640628680ff6f028ad6d5fef2e41da29664f036f Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 17:36:16 +0530
-Subject: [PATCH 16/54] [Patch, microblaze]: Removed moddi3 routinue Using the
- default moddi3 function as the existing implementation has many bugs
-
-Signed-off-by:Nagaraju <nmekala@xilix.com>
----
- libgcc/config/microblaze/moddi3.S     | 121 ----------------------------------
- libgcc/config/microblaze/t-microblaze |   3 +-
- 2 files changed, 1 insertion(+), 123 deletions(-)
- delete mode 100644 libgcc/config/microblaze/moddi3.S
-
-diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
-deleted file mode 100644
-index a8f17d7..0000000
---- a/libgcc/config/microblaze/moddi3.S
-+++ /dev/null
-@@ -1,121 +0,0 @@
--###################################
--# 
--#  Copyright (C) 2009-2018 Free Software Foundation, Inc.
--#
--#  Contributed by Michael Eager <eager@eagercon.com>.
--#
--#  This file is free software; you can redistribute it and/or modify it
--#  under the terms of the GNU General Public License as published by the
--#  Free Software Foundation; either version 3, or (at your option) any
--#  later version.
--#
--#  GCC is distributed in the hope that it will be useful, but WITHOUT
--#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
--#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
--#  License for more details.
--#
--#  Under Section 7 of GPL version 3, you are granted additional
--#  permissions described in the GCC Runtime Library Exception, version
--#  3.1, as published by the Free Software Foundation.
--#
--#  You should have received a copy of the GNU General Public License and
--#  a copy of the GCC Runtime Library Exception along with this program;
--#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
--#  <http://www.gnu.org/licenses/>. 
--#
--#  modsi3.S
--# 
--#  modulo operation for 64 bit integers.
--# 
--#######################################
--
--
--/* An executable stack is *not* required for these functions.  */
--#ifdef __linux__
--.section .note.GNU-stack,"",%progbits
--.previous
--#endif
--
--	.globl	__moddi3
--	.ent	__moddi3
--__moddi3:
--	.frame	r1,0,r15	
--
--#Change the stack pointer value and Save callee saved regs
--	addik	r1,r1,-24
--	swi	r25,r1,0
--	swi	r26,r1,4
--	swi	r27,r1,8	# used for sign
--	swi	r28,r1,12	# used for loop count
--	swi	r29,r1,16	# Used for div value High
--	swi	r30,r1,20	# Used for div value Low
--
--#Check for Zero Value in the divisor/dividend
--	OR	r9,r5,r6			# Check for the op1 being zero
--	BEQID	r9,$LaResult_Is_Zero		# Result is zero
--	OR	r9,r7,r8			# Check for the dividend being zero
--	BEQI	r9,$LaDiv_By_Zero	        # Div_by_Zero   # Division Error
--	BGEId	r5,$La1_Pos 
--	XOR	r27,r5,r7			# Get the sign of the result
--	RSUBI	r6,r6,0				# Make dividend positive
--	RSUBIC	r5,r5,0				# Make dividend positive
--$La1_Pos:
--	BGEI	r7,$La2_Pos
--	RSUBI	r8,r8,0				# Make Divisor Positive
--	RSUBIC	r9,r9,0				# Make Divisor Positive
--$La2_Pos:
--	ADDIK	r4,r0,0				# Clear mod low
--	ADDIK	r3,r0,0                	        # Clear mod high
--	ADDIK	r29,r0,0			# clear div high
--	ADDIK	r30,r0,0			# clear div low
--	ADDIK	r28,r0,64			# Initialize the loop count
--   # First part try to find the first '1' in the r5/r6
--$LaDIV1:
--	ADD	r6,r6,r6
--	ADDC	r5,r5,r5			# left shift logical r5
--	BGEID	r5,$LaDIV1			
--	ADDIK	r28,r28,-1
--$LaDIV2:
--	ADD	r6,r6,r6
--	ADDC	r5,r5,r5	# left shift logical r5/r6 get the '1' into the Carry
--	ADDC	r4,r4,r4	# Move that bit into the Mod register
--	ADDC	r3,r3,r3	# Move carry into high mod register
--	rsub	r18,r7,r3	# Compare the High Parts of Mod and Divisor
--	bnei	r18,$L_High_EQ
--	rsub	r18,r6,r4	# Compare Low Parts only if Mod[h] == Divisor[h]
--$L_High_EQ:	
--	rSUB	r26,r8,r4	# Subtract divisor[L] from Mod[L]
--	rsubc	r25,r7,r3	# Subtract divisor[H] from Mod[H]
--	BLTi	r25,$LaMOD_TOO_SMALL
--	OR	r3,r0,r25	# move r25 to mod [h]
--	OR	r4,r0,r26	# move r26 to mod [l]
--	ADDI	r30,r30,1
--	ADDC	r29,r29,r0
--$LaMOD_TOO_SMALL:
--	ADDIK	r28,r28,-1
--	BEQi	r28,$LaLOOP_END
--	ADD	r30,r30,r30		# Shift in the '1' into div [low]
--	ADDC	r29,r29,r29		# Move the carry generated into high
--	BRI	$LaDIV2   # Div2
--$LaLOOP_END:
--	BGEI	r27,$LaRETURN_HERE
--	rsubi	r30,r30,0
--	rsubc	r29,r29,r0
--	BRI	$LaRETURN_HERE
--$LaDiv_By_Zero:
--$LaResult_Is_Zero:
--	or	r29,r0,r0	# set result to 0 [High]
--	or	r30,r0,r0	# set result to 0 [Low]
--$LaRETURN_HERE:
--# Restore values of CSRs and that of r29 and the divisor and the dividend
--	
--	lwi	r25,r1,0
--	lwi	r26,r1,4
--	lwi	r27,r1,8
--	lwi	r28,r1,12
--	lwi	r29,r1,16
--	lwi	r30,r1,20
--	rtsd	r15,8
--	addik r1,r1,24
--        .end __moddi3
--	
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 96959f0..8d954a4 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,8 +1,7 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
--        $(srcdir)/config/microblaze/moddi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
-         $(srcdir)/config/microblaze/muldi3_hard.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
deleted file mode 100644
index 6fb1b32f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
+++ /dev/null
@@ -1,101 +0,0 @@
-From c0e74b79cc1db2f68dd560154225da1e5ddfd920 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 14:41:58 +0530
-Subject: [PATCH 17/54] [Patch, microblaze]: Add INIT_PRIORITY support Added
- TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
-
-These macros allows users to control the order of initialization
-of objects defined at namespace scope with the init_priority
-attribute by specifying a relative priority, a constant integral
-expression currently bounded between 101 and 65535 inclusive.
-
-Lower numbers indicate a higher priority.
-
-Changelog
-
-2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
- * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
-   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
-   TARGET_ASM_DESTRUCTOR.
-
-Signed-off-by:nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 53 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 6f0b4f4..53b44df 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2554,6 +2554,53 @@ print_operand_address (FILE * file, rtx addr)
-     }
- }
- 
-+/* Output an element in the table of global constructors. */
-+void
-+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
-+{
-+    const char *section = ".ctors";
-+    char buf[16];
-+
-+    if (priority != DEFAULT_INIT_PRIORITY)
-+      {
-+        sprintf (buf, ".ctors.%.5u",
-+                /* Invert the numbering so the linker puts us in the proper
-+                   order; constructors are run from right to left, and the
-+                   linker sorts in increasing order.  */
-+                MAX_INIT_PRIORITY - priority);
-+        section = buf;
-+      }
-+
-+    switch_to_section (get_section (section, 0, NULL));
-+    assemble_align (POINTER_SIZE);
-+    fputs ("\t.word\t", asm_out_file);
-+    output_addr_const (asm_out_file, symbol);
-+    fputs ("\n", asm_out_file);
-+}
-+
-+/* Output an element in the table of global destructors. */
-+void
-+microblaze_asm_destructor (rtx symbol, int priority)
-+{
-+    const char *section = ".dtors";
-+    char buf[16];
-+    if (priority != DEFAULT_INIT_PRIORITY)
-+      {
-+        sprintf (buf, ".dtors.%.5u",
-+                 /* Invert the numbering so the linker puts us in the proper
-+                    order; constructors are run from right to left, and the
-+                    linker sorts in increasing order.  */
-+                MAX_INIT_PRIORITY - priority);
-+        section = buf;
-+      }
-+
-+    switch_to_section (get_section (section, 0, NULL));
-+    assemble_align (POINTER_SIZE);
-+    fputs ("\t.word\t", asm_out_file);
-+    output_addr_const (asm_out_file, symbol);
-+    fputs ("\n", asm_out_file);
-+}
-+
- /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
-    is used, so that we don't emit an .extern for it in 
-    microblaze_asm_file_end.  */
-@@ -3841,6 +3888,12 @@ microblaze_starting_frame_offset (void)
- #undef TARGET_ATTRIBUTE_TABLE
- #define TARGET_ATTRIBUTE_TABLE          microblaze_attribute_table
- 
-+#undef TARGET_ASM_CONSTRUCTOR
-+#define TARGET_ASM_CONSTRUCTOR          microblaze_asm_constructor
-+
-+#undef TARGET_ASM_DESTRUCTOR
-+#define TARGET_ASM_DESTRUCTOR           microblaze_asm_destructor
-+
- #undef TARGET_IN_SMALL_DATA_P
- #define TARGET_IN_SMALL_DATA_P          microblaze_elf_in_small_data_p
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
deleted file mode 100644
index ab2473a3..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
+++ /dev/null
@@ -1,81 +0,0 @@
-From 2cba68c3e27ffaea77cc5469233cf4dcb9383142 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 15:23:57 +0530
-Subject: [PATCH 18/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel
- shifter is not present, the immediate value is greater than #5 and
- optimization is -OS, the compiler will generate shift operation using loop.
-
-Changelog
-
-2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
-
-ChangeLog/testsuite
-
-2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
-
-Signed-off-by:Nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.md                 | 21 +++++++++++++++++++++
- .../gcc.target/microblaze/others/lshrsi_Os_1.c      | 13 +++++++++++++
- 2 files changed, 34 insertions(+)
- create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fe90a14..c063ffc 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1616,6 +1616,27 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+(define_insn "*lshrsi3_with_size_opt"
-+  [(set (match_operand:SI 0 "register_operand" "=&d")
-+       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-+                   (match_operand:SI 2 "immediate_operand" "I")))]
-+  "(INTVAL (operands[2]) > 5 && optimize_size)"
-+  {
-+    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("ori\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addik\t%3,%3,-1", operands);
-+    output_asm_insn ("bneid\t%3,.-4", operands);
-+    return "srl\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"    "SI")
-+  (set_attr "length"  "20")]
-+)
-+
- (define_insn "*lshrsi_inline"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-new file mode 100644
-index 0000000..32a3be7
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-@@ -0,0 +1,13 @@
-+/* { dg-options "-Os -mno-xl-barrel-shift" } */
-+
-+void testfunc(void)
-+{
-+    unsigned volatile int z = 8192;
-+    z >>= 8;
-+}
-+/* { dg-final { scan-assembler-not "\bsrli" } } */
-+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
-+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
-+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
-+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
-+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch
deleted file mode 100644
index 5afcff43..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From e8b05b5105655d276c93864ab90e15bfbe46cf74 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 15:42:15 +0530
-Subject: [PATCH 19/54] [Patch, microblaze]: Modified trap instruction The
- instruction was wrongly written to brki r0,-1 it should be bri r0. Modified
- with the correct instruction
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-              :Ajit Agarwal  <ajitkum@xilinx.com>
----
- gcc/config/microblaze/microblaze.md | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index c063ffc..7bbdbe1 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2344,7 +2344,7 @@
- (define_insn "trap"
-   [(trap_if (const_int 1) (const_int 0))]
-   ""
--  "brki\tr0,-1"
-+  "bri\t0"
-  [(set_attr "type" "trap")]
- )
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
deleted file mode 100644
index 6e07ac4f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
+++ /dev/null
@@ -1,206 +0,0 @@
-From 0cc6aabbd3f7b331c3995f11efec545499297358 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 16:42:44 +0530
-Subject: [PATCH 20/54] [Patch, microblaze]: Reducing Stack space for arguments
- Currently in Microblaze target stack space for arguments in register is being
- allocated even if there are no arguments in the function. This patch will
- optimize the extra 24 bytes that are being allocated.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-              :Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2015-04-17 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-    *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
-    *microblaze.c (REG_PARM_STACK_SPACE): Modify
----
- gcc/config/microblaze/microblaze-protos.h |   1 +
- gcc/config/microblaze/microblaze.c        | 134 +++++++++++++++++++++++++++++-
- gcc/config/microblaze/microblaze.h        |   4 +-
- 3 files changed, 136 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 4cbba0c..f8a56f7 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -58,6 +58,7 @@ extern int symbol_mentioned_p (rtx);
- extern int label_mentioned_p (rtx);
- extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
- extern void microblaze_eh_return (rtx op0);
-+int  microblaze_reg_parm_stack_space(tree fun);
- #endif  /* RTX_CODE */
- 
- /* Declare functions in microblaze-c.c.  */
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 53b44df..0dec362 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -1989,6 +1989,138 @@ microblaze_must_save_register (int regno)
-   return 0;
- }
- 
-+static bool
-+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
-+{
-+  enum machine_mode mode;
-+  int unsignedp;
-+  rtx entry_parm;
-+
-+  /* Catch errors.  */
-+  if (type == NULL || type == error_mark_node)
-+    return true;
-+
-+  if (TREE_CODE (type) == POINTER_TYPE)
-+    return true;
-+
-+  /* Handle types with no storage requirement.  */
-+  if (TYPE_MODE (type) == VOIDmode)
-+    return false;
-+
-+   /* Handle complex types.  */
-+  if (TREE_CODE (type) == COMPLEX_TYPE)
-+    return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
-+             || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
-+
-+  /* Handle transparent aggregates.  */
-+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
-+     && TYPE_TRANSPARENT_AGGR (type))
-+  type = TREE_TYPE (first_field (type));
-+
-+  /* See if this arg was passed by invisible reference.  */
-+ if (pass_by_reference (get_cumulative_args (args_so_far),
-+                        TYPE_MODE (type), type, true))
-+    type = build_pointer_type (type);
-+
-+    /* Find mode as it is passed by the ABI.  */
-+    unsignedp = TYPE_UNSIGNED (type);
-+    mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
-+
-+/* If there is no incoming register, we need a stack.  */
-+ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
-+ if (entry_parm == NULL)
-+    return true;
-+
-+ /* Likewise if we need to pass both in registers and on the stack.  */
-+ if (GET_CODE (entry_parm) == PARALLEL
-+     && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
-+   return true;
-+
-+ /* Also true if we're partially in registers and partially not.  */
-+  if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
-+     return true;
-+
-+ /* Update info on where next arg arrives in registers.  */
-+ microblaze_function_arg_advance (args_so_far, mode, type, true);
-+ return false;
-+ }
-+
-+static bool
-+microblaze_function_parms_need_stack (tree fun, bool incoming)
-+{
-+  tree fntype, result;
-+  CUMULATIVE_ARGS args_so_far_v;
-+  cumulative_args_t args_so_far;
-+  int num_of_args = 0;
-+
-+  /* Must be a libcall, all of which only use reg parms.  */
-+  if (!fun)
-+    return true;
-+
-+  fntype = fun;
-+  if (!TYPE_P (fun))
-+    fntype = TREE_TYPE (fun);
-+
-+  /* Varargs functions need the parameter save area.  */
-+  if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
-+    return true;
-+
-+  INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
-+  args_so_far = pack_cumulative_args (&args_so_far_v);
-+
-+  /* When incoming, we will have been passed the function decl.
-+   *      It is necessary to use the decl to handle K&R style functions,
-+   *      where TYPE_ARG_TYPES may not be available.  */
-+  if (incoming)
-+    {
-+      gcc_assert (DECL_P (fun));
-+      result = DECL_RESULT (fun);
-+    }
-+  else
-+    result = TREE_TYPE (fntype);
-+
-+  if (result && aggregate_value_p (result, fntype))
-+    {
-+      if (!TYPE_P (result))
-+        result = build_pointer_type (result);
-+        microblaze_parm_needs_stack (args_so_far, result);
-+    }
-+
-+  if (incoming)
-+    {
-+      tree parm;
-+      for (parm = DECL_ARGUMENTS (fun);
-+           parm && parm != void_list_node;
-+           parm = TREE_CHAIN (parm))
-+         if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
-+           return true;
-+    }
-+  else
-+    {
-+      function_args_iterator args_iter;
-+      tree arg_type;
-+
-+      FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
-+      {
-+        num_of_args++;
-+        if (microblaze_parm_needs_stack (args_so_far, arg_type))
-+         return true;
-+      }
-+    }
-+
-+  if (num_of_args > 3) return true;
-+
-+  return false;
-+}
-+
-+int  microblaze_reg_parm_stack_space(tree fun)
-+{
-+  if (microblaze_function_parms_need_stack (fun,false))
-+    return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
-+  else
-+    return 0;
-+}
-+
- /* Return the bytes needed to compute the frame pointer from the current
-    stack pointer.
- 
-@@ -3298,7 +3430,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-   emit_insn (gen_indirect_jump (temp2));
- 
-   /* Run just enough of rest_of_compilation.  This sequence was
--     "borrowed" from rs6000.c.  */
-+     "borrowed" from microblaze.c.  */
-   insn = get_insns ();
-   shorten_branches (insn);
-   final_start_function (insn, file, 1);
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 88e0351..9f74ec8 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
- 
- #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
- 
--#define REG_PARM_STACK_SPACE(FNDECL)  		(MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
-+#define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
- 
--#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)	1
-+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
- 
- #define STACK_BOUNDARY				32
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
deleted file mode 100644
index b04ee580..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
+++ /dev/null
@@ -1,159 +0,0 @@
-From f846bd900d5277dd9defb5fe0625f97e3417ee61 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:04:37 +0530
-Subject: [PATCH 21/54] [Patch, microblaze]: Add cbranchsi4_reg This patch
- optimizes the generation of  pcmpne/pcmpeq instruction if the compare
- instruction has no immediate values.For the immediate values the xor
- instruction is generated
-
-Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
-Signed-off-by: Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2015-01-13 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-  *microblaze.md (cbranchsi4_reg): New
-  *microblaze.c (microblaze_expand_conditional_branch_reg): New
-
-Conflicts:
-
-	gcc/config/microblaze/microblaze-protos.h
----
- gcc/config/microblaze/microblaze-protos.h                 |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c           |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c           |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c           |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c           |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c          | 14 +++++++-------
- gcc/testsuite/gcc.target/microblaze/isa/vanilla.c         | 12 ++++++------
- gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c |  2 +-
- 8 files changed, 19 insertions(+), 19 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index f8a56f7..c39e2e9 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -32,7 +32,7 @@ extern int microblaze_expand_shift (rtx *);
- extern bool microblaze_expand_move (machine_mode, rtx *);
- extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
- extern void microblaze_expand_divide (rtx *);
--extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
-+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_sf (rtx *); 
- extern int microblaze_can_use_return_insn (void);
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-index 4041a24..ccc6a46 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 <= f3) 
--        print ("le");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-index 3902b83..1dd5fe6 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 < f3) 
--        print ("lt");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-index 8555974..d6f80fb 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 == f3) 
--        print ("eq");
-+        f1 = f2 + f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-index 79cc5f9..d117724 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
-   /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-   /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if(f1==f2 && f1<=f3)
--        print ("f1 eq f2 && f1 le f3");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-index ebfb170..7582297 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
- void float_func () 
- {
-     /* { dg-final { scan-assembler-not "fcmp" } } */
--    if (f2 <= f3) 
--        print ("le");
-+    if (f2 <= f3)
-+        f1 = f3;
-     else if (f2 == f3) 
--        print ("eq");
-+        f1 = f3;
-     else if (f2 < f3) 
--        print ("lt");
-+        f1 = f3;
-     else if (f2 > f3) 
--        print ("gt");
-+        f1 = f3;
-     else if (f2 >= f3) 
--        print ("ge");
-+        f1 = f3;
-     else if (f2 != f3) 
--        print ("ne");
-+        f1 = f3;
-     
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-index 1d6ba80..532c035 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-@@ -74,16 +74,16 @@ void float_cmp_func ()
- {
-     /* { dg-final { scan-assembler-not "fcmp" } } */
-     if (f2 <= f3) 
--        print ("le");
-+        f1 = f3;
-     else if (f2 == f3) 
--        print ("eq");
-+        f1 = f3;
-     else if (f2 < f3) 
--        print ("lt");
-+        f1 = f3;
-     else if (f2 > f3) 
--        print ("gt");
-+        f1 = f3;
-     else if (f2 >= f3) 
--        print ("ge");
-+        f1 = f3;
-     else if (f2 != f3) 
--        print ("ne");
-+        f1 = f3;
-     
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
-index fdcde1f..580b4db 100644
---- a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
-+++ b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
-@@ -5,4 +5,4 @@ void trap ()
-   __builtin_trap ();
- }
- 
--/* { dg-final { scan-assembler "brki\tr0,-1" } } */
-\ No newline at end of file
-+/* { dg-final { scan-assembler "bri\t0" } } */
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
deleted file mode 100644
index beeb80fd..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 7d70a287544dd915b66a5658a3857ebecb8b3583 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:11:04 +0530
-Subject: [PATCH 22/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
- The changes are made in the patch for the inline expansion of the fsqrt
- builtin with fqrt instruction. The sqrt math function takes double as
- argument and return double as argument. The pattern is selected while
- expanding the unary op through expand_unop which passes DFmode and the DFmode
- pattern was not there returning zero. Thus the sqrt math function is not
- inlined and expanded. The pattern with DFmode argument is added. Also the
- source and destination argument is not same the DF through two different
- consecutive registers with lower 32 bit is the argument passed to sqrt and
- the higher 32 bit is zero. If the source and destinations are different the
- DFmode 64 bits registers is not set properly giving the problem in runtime.
- Such changes are taken care in the implementation of the pattern for DFmode
- for inline expansion of the sqrt.
-
-ChangeLog:
-2015-06-16  Ajit Agarwal  <ajitkum@xilinx.com>
-            Nagaraju Mekala <nmekala@xilinx.com>
-
-	* config/microblaze/microblaze.md (sqrtdf2): New
-	pattern.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
-              Nagaraju Mekala nmekala@xilinx.com
----
- gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7bbdbe1..3a53e24 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -449,6 +449,20 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "sqrtdf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
-+  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
-+  {
-+    if (REGNO (operands[0]) == REGNO (operands[1]))
-+      return "fsqrt\t%0,%1";
-+    else
-+      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
-+  }
-+  [(set_attr "type"     "fsqrt")
-+   (set_attr "mode"      "SF")
-+   (set_attr "length"    "4")])
-+
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
deleted file mode 100644
index 8f5bed52..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From a28768eec0a9d5137196bed8e8c6d284cf4c3cbc Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:33:31 +0530
-Subject: [PATCH 23/54] [Patch] OPT: Update heuristics for loop-invariant for
- address arithme. .tic.
-
-The changes are made in the patch to update the heuristics
-for loop invariant for address arithmetic. The heuristics is
-changed to calculate the estimated register pressure cost when
-ira based register pressure is not enabled. The estimated
-register pressure cost modifies the existing calculation cost
-associated to perform the Loop invariant code motion for address
-arithmetic.
-
-ChangeLog:
-2015-06-17  Ajit Agarwal  <ajitkum@xilinx.com>
-            Nagaraju Mekala <nmekala@xilinx.com>
-
-	* loop-invariant.c (gain_for_invariant): update the
-	heuristics for estimate_reg_pressure_cost.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
-              Nagaraju Mekala nmekala@xilinx.com
----
- gcc/loop-invariant.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index bd31a51..8e22ca0 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1466,10 +1466,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- 
-   if (! flag_ira_loop_pressure)
-     {
--      size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
--					       regs_used, speed, call_p)
--		   - estimate_reg_pressure_cost (new_regs[0],
--						 regs_used, speed, call_p));
-+      size_cost = estimate_reg_pressure_cost (regs_needed[0],
-+					       regs_used, speed, call_p);
-     }
-   else if (ret < 0)
-     return -1;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
deleted file mode 100644
index 85a749e5..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
+++ /dev/null
@@ -1,63 +0,0 @@
-From be9c512be09fa4ef67870ab0456eb3781394dac3 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 18:07:24 +0530
-Subject: [PATCH 24/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
- insn definitions Change adddi3 to handle DI immediates as the second operand,
- this requires modification to the output template however reduces the need to
- specify seperate templates for 16-bit positive/negative immediate operands.
- The use of 32-bit immediates for the addi and addic instructions is handled
- by the assembler, which will emit the imm instructions when required. This
- conveniently handles the optimizable cases where the immediate constant value
- does not need the higher half words of the operands upper/lower words.
-
-Change the constraints of the subdi3 instruction definition such that it
-does not match the second operand as an immediate value. This is because
-there is no definition to handle this case nor is it possible to
-implement purely with instructions as microblaze does not provide an
-instruction to perform a forward arithmetic subtraction (it only
-provides reverse 'rD = IMM - rA').
-
-Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
----
- gcc/config/microblaze/microblaze.md | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 3a53e24..949e103 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -500,17 +500,16 @@
- ;; Adding 2 DI operands in register or reg/imm
- 
- (define_insn "adddi3"
--  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
--	(plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
--		 (match_operand:DI 2 "arith_operand32" "d,P,N")))]
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-+		 (match_operand:DI 2 "arith_operand" "d,i")))]
-   ""
-   "@
-   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
--  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
--  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
-+  addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
-   [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
--  (set_attr "length"	"8,8,12")])
-+  (set_attr "length"	"8,8")])
- 
- ;;----------------------------------------------------------------
- ;; Subtraction
-@@ -547,7 +546,7 @@
- (define_insn "subdi3"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
--		  (match_operand:DI 2 "arith_operand32" "d")))]
-+		  (match_operand:DI 2 "register_operand" "d")))]
-   ""
-   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
-   [(set_attr "type"	"darith")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
deleted file mode 100644
index 17f25448..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From c8ee051fa3e0ad05b19eb6141a7cb72245b412b7 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 18:18:41 +0530
-Subject: [PATCH 25/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns
- This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
- of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
- patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
- instruction doesn't support so using gen_int_mode function
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-              :Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-01-07 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-  *microblaze.md (ashlsi3_with_mul_nodelay,
-                  ashlsi3_with_mul_delay,
-                  movsf_internal):
-    Updated the patterns to use gen_int_mode function
-  *microblaze.c (print_operand):
-     updated the 'F' case to use "unsinged int" instead
-     of HOST_WIDE_INT_PRINT_HEX
----
- gcc/config/microblaze/microblaze.c  |  2 +-
- gcc/config/microblaze/microblaze.md | 10 ++++++++--
- 2 files changed, 9 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0dec362..daf0269 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2531,7 +2531,7 @@ print_operand (FILE * file, rtx op, int letter)
- 	  unsigned long value_long;
- 	  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
- 				       value_long);
--	  fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
-+	  fprintf (file, "0x%08x", (unsigned int) value_long);
- 	}
-       else
- 	{
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 949e103..bc675ca 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1366,7 +1366,10 @@
-                    (match_operand:SI 2 "immediate_operand" "I")))] 
-   "!TARGET_SOFT_MUL 
-    && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
--  "muli\t%0,%1,%m2"
-+  {
-+    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
-+    return "muli\t%0,%1,%2";
-+  }
-   ;; This MUL will not generate an imm. Can go into a delay slot.
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-@@ -1378,7 +1381,10 @@
- 	(ashift:SI (match_operand:SI 1 "register_operand"  "d")
-                    (match_operand:SI 2 "immediate_operand" "I")))] 
-   "!TARGET_SOFT_MUL"
--  "muli\t%0,%1,%m2"
-+  {
-+    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
-+    return "muli\t%0,%1,%2";
-+  }
-   ;; This MUL will generate an IMM. Cannot go into a delay slot
-   [(set_attr "type"	"no_delay_arith")
-    (set_attr "mode"	"SI")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
deleted file mode 100644
index 506714bd..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
+++ /dev/null
@@ -1,193 +0,0 @@
-From 64e76f3be6ad78044ea2b89b555a07758c2b2950 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 19:50:34 +0530
-Subject: [PATCH 26/54] [Patch, microblaze]: 8-stage pipeline for microblaze
- This patch adds the support for the 8-stage pipeline. The new 8-stage
- pipeline reduces the latencies of float & integer division drastically
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (define_automaton mbpipe_8): New
-
-  *microblaze.c (microblaze_option_override): Update
-    Updated the logic to generate only when MB version is 10.0
-
-  *microblaze.h (pipeline_type): Update
-          Update the enum with MICROBLAZE_PIPE_8
-
-  *microblaze.opt (mxl-frequency): New
-         New flag added for 8-stage pipeline
----
- gcc/config/microblaze/microblaze.c   | 13 ++++++
- gcc/config/microblaze/microblaze.h   |  3 +-
- gcc/config/microblaze/microblaze.md  | 79 +++++++++++++++++++++++++++++++++++-
- gcc/config/microblaze/microblaze.opt |  4 ++
- 4 files changed, 96 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index daf0269..3832d16 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -1772,6 +1772,19 @@ microblaze_option_override (void)
-           warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a");
-         TARGET_REORDER = 0;
-     }
-+  ver = ver_int - microblaze_version_to_int("v10.0");
-+  if (ver < 0)
-+    {
-+        if (TARGET_AREA_OPTIMIZED_2)
-+          warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
-+    }
-+  else
-+    {
-+        if (TARGET_AREA_OPTIMIZED_2)
-+          microblaze_pipe = MICROBLAZE_PIPE_8;
-+        if (TARGET_BARREL_SHIFT)
-+          microblaze_has_bitfield = 1;
-+    }
- 
-   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
-     error ("-mxl-multiply-high requires -mno-xl-soft-mul");
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 9f74ec8..2ac5aeec 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -27,7 +27,8 @@
- enum pipeline_type
- {
-   MICROBLAZE_PIPE_3 = 0,
--  MICROBLAZE_PIPE_5 = 1
-+  MICROBLAZE_PIPE_5 = 1,
-+  MICROBLAZE_PIPE_8 = 2
- };
- 
- #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bc675ca..6395533 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -35,6 +35,7 @@
-   (R_GOT      20)       ;; GOT ptr reg
-   (MB_PIPE_3   0)       ;; Microblaze 3-stage pipeline 
-   (MB_PIPE_5   1)       ;; Microblaze 5-stage pipeline 
-+  (MB_PIPE_8   2)       ;; Microblaze 8-stage pipeline
-   (UNSPEC_SET_GOT       101)    ;;
-   (UNSPEC_GOTOFF        102)    ;; GOT offset
-   (UNSPEC_PLT           103)    ;; jump table
-@@ -80,7 +81,7 @@
- ;; bshift 	Shift operations
- 
- (define_attr "type"
--  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
-+  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
-   (const_string "unknown"))
- 
- ;; Main data type used by the insn
-@@ -222,6 +223,80 @@
- ;;-----------------------------------------------------------------
- 
- 
-+
-+;;----------------------------------------------------------------
-+;; Microblaze 8-stage pipeline description (v10.0 and later)
-+;;----------------------------------------------------------------
-+
-+(define_automaton   "mbpipe_8")
-+(define_cpu_unit    "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
-+
-+(define_insn_reservation "mb8-integer" 1
-+  (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-special-move" 2
-+  (and (eq_attr "type" "move")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-mem-load" 3
-+  (and (eq_attr "type" "load,no_delay_load")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-mem-store" 1
-+  (and (eq_attr "type" "store,no_delay_store")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-mul" 3
-+  (and (eq_attr "type" "imul,no_delay_imul")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-div" 30
-+  (and (eq_attr "type" "idiv")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+    "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
-+
-+(define_insn_reservation "mb8-bs" 2
-+  (and (eq_attr "type" "bshift")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+   "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-add-sub-mul" 1
-+  (and (eq_attr "type" "fadd,frsub,fmul")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fcmp" 3
-+  (and (eq_attr "type" "fcmp")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-div" 24
-+  (and (eq_attr "type" "fdiv")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-sqrt" 23
-+  (and (eq_attr "type" "fsqrt")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fcvt" 1
-+  (and (eq_attr "type" "fcvt")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fint" 2
-+  (and (eq_attr "type" "fint")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+
- ;;----------------------------------------------------------------
- ;; Microblaze 5-stage pipeline description (v5.00.a and later)
- ;;----------------------------------------------------------------                 
-@@ -468,7 +543,7 @@
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-   "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "fint\t%0,%1"
--  [(set_attr "type"     "fcvt")
-+  [(set_attr "type"     "fint")
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index 8242998..c8e6f00 100644
---- a/gcc/config/microblaze/microblaze.opt
-+++ b/gcc/config/microblaze/microblaze.opt
-@@ -129,3 +129,7 @@ Use hardware prefetch instruction
- 
- mxl-mode-xilkernel
- Target
-+
-+mxl-frequency
-+Target Mask(AREA_OPTIMIZED_2)
-+Use 8 stage pipeline (frequency optimization)
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
deleted file mode 100644
index 95b9b2aa..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From 5147c831c6a78d9b95138b679bb2ca7624abc3a1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:08:40 +0530
-Subject: [PATCH 27/54] [Patch,rtl Optimization]: Better register pressure
- estimate for loop . .invariant code motion
-
-Calculate the loop liveness used for regs for calculating the register pressure
-in the cost estimation.  Loop liveness is based on the following properties.
-We only need to find the set of objects that are live at the birth or the header
-of the loop. We don't need to calculate the live through the loop by considering
-live in and live out of all the basic blocks of the loop. This is based on the
-point that the set of objects that are live-in at the birth or header of the loop
-will be live-in at every node in the loop.
-
-If a v live is out at the header of the loop then the variable is live-in at every node
-in the loop. To prove this, consider a loop L with header h such that the variable v
-defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i
-from the dominance property, i.e. h is strictly dominated by d. Furthermore, there
-exists a path from h to a use of v which does not go through d. For every node p in
-the loop, since the loop is strongly connected and node is a component of the CFG,
-there exists a path, consisting only of nodes of L from p to h. Concatenating these
-two paths proves that v is live-in and live-out of p.
-
-Calculate the live-out and live-in for the exit edge of the loop. This patch considers
-liveness for not only the loop latch but also the liveness outside the loops.
-
-ChangeLog:
-2016-01-22  Ajit Agarwal  <ajitkum@xilinx.com>
-
-	* loop-invariant.c
-	(find_invariants_to_move): Add the logic of regs_used based
-	on liveness.
-	* cfgloopanal.c
-	(estimate_reg_pressure_cost): Update the heuristics in presence
-	of call_p.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
----
- gcc/cfgloopanal.c    |  4 +++-
- gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++++++++-------------
- 2 files changed, 50 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
-index 3af0b2d..123dc6b 100644
---- a/gcc/cfgloopanal.c
-+++ b/gcc/cfgloopanal.c
-@@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
-   if (regs_needed + target_res_regs <= available_regs)
-     return 0;
- 
--  if (regs_needed <= available_regs)
-+  if ((regs_needed <= available_regs)
-+      || (call_p && (regs_needed <=
-+          (available_regs + target_clobbered_regs))))
-     /* If we are close to running out of registers, try to preserve
-        them.  */
-     cost = target_reg_cost [speed] * n_new;
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index 8e22ca0..c9ec8df 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1520,7 +1520,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- 	size_cost = 0;
-     }
- 
--  return comp_cost - size_cost;
-+  return comp_cost - size_cost + 1;
- }
- 
- /* Finds invariant with best gain for moving.  Returns the gain, stores
-@@ -1614,22 +1614,53 @@ find_invariants_to_move (bool speed, bool call_p)
-     /* REGS_USED is actually never used when the flag is on.  */
-     regs_used = 0;
-   else
--    /* We do not really do a good job in estimating number of
--       registers used; we put some initial bound here to stand for
--       induction variables etc.  that we do not detect.  */
-+    /* The logic used in estimating the number of regs_used is changed.
-+       Now it will be based on liveness of the loop. */
-     {
--      unsigned int n_regs = DF_REG_SIZE (df);
--
--      regs_used = 2;
--
--      for (i = 0; i < n_regs; i++)
--	{
--	  if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i))
--	    {
--	      /* This is a value that is used but not changed inside loop.  */
--	      regs_used++;
--	    }
--	}
-+      int  i;
-+      edge e;
-+      vec<edge> edges;
-+      bitmap_head regs_live;
-+
-+      bitmap_initialize (&regs_live, &reg_obstack);
-+      edges = get_loop_exit_edges (curr_loop);
-+
-+      /* Loop liveness is based on the following properties.
-+         We only need to find the set of objects that are live at the
-+         birth or the header of the loop.
-+         We don't need to calculate the live through the loop considering
-+         live-in and live-out of all the basic blocks of the loop. This is
-+         based on the point that the set of objects that are live-in at the
-+         birth or header of the loop will be live-in at every block in the
-+         loop.
-+
-+         If a v live out at the header of the loop then the variable is
-+         live-in at every node in the Loop. To prove this, consider a loop
-+         L with header h such that the variable v defined at d is live-in
-+         at h. Since v is live at h, d is not part of L. This follows from
-+         the dominance property, i.e. h is strictly dominated by d. Furthermore,
-+         there exists a path from h to a use of v which does not go through d.
-+         For every node of the loop, p, since the loop is strongly connected
-+         component of the CFG, there exists a path, consisting only of nodes
-+         of L from p to h. Concatenating these two paths prove that v is
-+         live-in and live-out of p.  */
-+
-+       bitmap_ior_into (&regs_live, DF_LR_IN (curr_loop->header));
-+       bitmap_ior_into (&regs_live, DF_LR_OUT (curr_loop->header));
-+
-+       /* Calculate the live-out and live-in for the exit edge of the loop.
-+          This considers liveness for not only the loop latch but also the
-+          liveness outside the loops.  */
-+
-+       FOR_EACH_VEC_ELT (edges, i, e)
-+         {
-+           bitmap_ior_into (&regs_live, DF_LR_OUT (e->src));
-+           bitmap_ior_into (&regs_live, DF_LR_IN (e->dest));
-+         }
-+
-+       regs_used = bitmap_count_bits (&regs_live) + 2;
-+       bitmap_clear (&regs_live);
-+       edges.release ();
-     }
- 
-   if (! flag_ira_loop_pressure)
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
deleted file mode 100644
index 3643ff19..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 2715b235b3db423bf35b9304a2ba5daa86b1680e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:25:48 +0530
-Subject: [PATCH 28/54] [Patch, microblaze]: Correct the const high double
- immediate value With this patch the loading of the DI mode immediate values
- will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
- functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
- of the unsigned long long constants also
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
- *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
-        REAL_VALUE_TO_TARGET_DOUBLE
- *long.c (new): Added new testcase
----
- gcc/config/microblaze/microblaze.c         |  8 ++++++--
- gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
- 2 files changed, 16 insertions(+), 2 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 3832d16..29cd54f 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2517,14 +2517,18 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
-+      long l[2];
-       if (code == CONST_DOUBLE)
- 	{
- 	  if (GET_MODE (op) == DFmode)
- 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
- 	  else
- 	    {
--	      val[0] = CONST_DOUBLE_HIGH (op);
--	      val[1] = CONST_DOUBLE_LOW (op);
-+	      REAL_VALUE_TYPE rv;
-+	      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
-+	      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
-+	      val[1] = l[WORDS_BIG_ENDIAN == 0];
-+	      val[0] = l[WORDS_BIG_ENDIAN != 0];
- 	    }
- 	}
-       else if (code == CONST_INT)
-diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
-new file mode 100644
-index 0000000..4d45186
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/microblaze/long.c
-@@ -0,0 +1,10 @@
-+/* { dg-options "-O0" } */
-+#define BASEADDR 0xF0000000ULL
-+int main ()
-+{
-+  unsigned long long start;
-+  start = (unsigned long long) BASEADDR;
-+  return 0;
-+}
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
deleted file mode 100644
index b4b9d2ec..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 7e025a0b22eee87bf9597267918bd16fc87c85c2 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:49:58 +0530
-Subject: [PATCH 29/54] [Fix, microblaze]: Fix internal compiler error with
- msmall-divides This patch will fix the internal error
- microblaze_expand_divide function which comes because of rtx PLUS where the
- mem_rtx is of type SI and the operand is of type QImode. This patch modifies
- the mem_rtx as QImode and Plus as QImode to fix the error.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-ChangeLog:
-  2016-02-23 Nagaraju Mekala <nmekala@xilix.com>
-             Ajit Agarwal  <ajitkum@xilinx.com>
-
-                                  *microblaze.c (microblaze_expand_divide): Update
----
- gcc/config/microblaze/microblaze.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 29cd54f..f8a417c 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3769,7 +3769,7 @@ microblaze_expand_divide (rtx operands[])
-   emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
-   emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-   mem_rtx = gen_rtx_MEM (QImode,
--                            gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
-+                            gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
-   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
deleted file mode 100644
index 52fd4bea..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 27a69d1873221747121360d0a1dffc4336a1d0cc Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:03:39 +0530
-Subject: [PATCH 30/54] [patch,microblaze]: Fix the calculation of high word in
- a long long 6. .4-bit
-
-This patch will change the calculation of high word in a long long 64-bit.
-Earlier to this patch the high word of long long word (0xF0000000ULL) is
-coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
-should be 0x00000000 and the low word should be 0xF0000000. This patch
-removes the condition of checking high word = 0 & low word < 0.
-This check is not required for the correctness of calculating 32-bit high
-and low words in a 64-bit long long.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-03-01 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-    *config/microblaze/microblaze.c (print_operand): Remove the condition of checking
-    high word = 0 & low word < 0.
-    *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
----
- gcc/config/microblaze/microblaze.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index f8a417c..70d8d03 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2535,9 +2535,6 @@ print_operand (FILE * file, rtx op, int letter)
-         {
- 	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
- 	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
--	  if (val[0] == 0 && val[1] < 0)
--	    val[0] = -1;
--	    
-         }
-       fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-     }
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
deleted file mode 100644
index 57144523..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
+++ /dev/null
@@ -1,120 +0,0 @@
-From 35569bb20a5bb881f7f275d901a0be3408b16622 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:14:51 +0530
-Subject: [PATCH 31/54] [Patch, microblaze]: Add new bit-field instructions
- This patches adds new bsefi and bsifi instructions. BSEFI- The instruction
- shall extract a bit field from a register and place it right-adjusted in the
- destination register. The other bits in the destination register shall be set
- to zero BSIFI- The instruction shall insert a right-adjusted bit field from a
- register at another position in the destination register. The rest of the
- bits in the destination register shall be unchanged
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-  2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (Update): Added new patterns
----
- gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
- 1 file changed, 73 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6395533..5a2dd13 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -980,6 +980,8 @@
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"20,20,20")])
- 
-+
-+
- ;;----------------------------------------------------------------
- ;; Data movement
- ;;----------------------------------------------------------------
-@@ -1774,6 +1776,7 @@
-   (set_attr "length"   "28")]
- )
- 
-+
- ;;----------------------------------------------------------------
- ;; Setting a register from an integer comparison. 
- ;;----------------------------------------------------------------
-@@ -2473,4 +2476,74 @@
-   DONE;
- }")
- 
-+(define_expand "extvsi"
-+  [(set (match_operand:SI 0 "register_operand" "r")
-+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+			 (match_operand:SI 2 "immediate_operand" "I")
-+			 (match_operand:SI 3 "immediate_operand" "I")))]
-+"TARGET_HAS_BITFIELD"
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "extv_32"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+			 (match_operand:SI 2 "immediate_operand" "I")
-+			 (match_operand:SI 3 "immediate_operand" "I")))]
-+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
-+   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
-+  "bsefi %0,%1,%2,%3"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
-+(define_expand "insvsi"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+			 (match_operand:SI 1 "immediate_operand" "I")
-+			 (match_operand:SI 2 "immediate_operand" "I"))
-+	(match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD"
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "insv_32"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+			 (match_operand:SI 1 "immediate_operand" "I")
-+			 (match_operand:SI 2 "immediate_operand" "I"))
-+	(match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
-+   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
-+  "bsifi %0, %3, %1, %2"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
- (include "sync.md")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
deleted file mode 100644
index dce1bc58..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
+++ /dev/null
@@ -1,247 +0,0 @@
-From 3db8f0c3124d3001d3c10e6d400943f3ec57616b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:42:10 +0530
-Subject: [PATCH 32/54] [Patch, microblaze]: Fix bug in MB version calculation
- This patch fixes the bug in microblaze_version_to_int function. Earlier the
- conversion of vXX.YY.Z to int has a bug which is fixed now.
-
-Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
-                Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
- 1 file changed, 70 insertions(+), 77 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 70d8d03..30a0fcf 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -238,6 +238,63 @@ section *sdata2_section;
- #define TARGET_HAVE_TLS true
- #endif
- 
-+/*  Convert a version number of the form "vX.YY.Z" to an integer encoding
-+    for easier range comparison.  */
-+static int
-+microblaze_version_to_int (const char *version)
-+{
-+  const char *p, *v;
-+  const char *tmpl = "vXX.YY.Z";
-+  int iver1 =0, iver2 =0, iver3 =0;
-+
-+  p = version;
-+  v = tmpl;
-+
-+  while (*p)
-+    {
-+      if (*v == 'X')
-+	{			/* Looking for major  */
-+          if (*p == '.')
-+            {
-+              *v++;
-+            }
-+          else
-+            {
-+	      if (!(*p >= '0' && *p <= '9'))
-+	        return -1;
-+	      iver1 += (int) (*p - '0');
-+              iver1 *= 1000;
-+	     }
-+        }
-+      else if (*v == 'Y')
-+	{			/* Looking for minor  */
-+	  if (!(*p >= '0' && *p <= '9'))
-+	    return -1;
-+	  iver2 += (int) (*p - '0');
-+	  iver2 *= 10;
-+	}
-+      else if (*v == 'Z')
-+	{			/* Looking for compat  */
-+	  if (!(*p >= 'a' && *p <= 'z'))
-+	    return -1;
-+      iver3 = ((int) (*p)) - 96;
-+	}
-+      else
-+	{
-+	  if (*p != *v)
-+	    return -1;
-+	}
-+
-+      v++;
-+      p++;
-+    }
-+
-+  if (*p)
-+    return -1;
-+
-+  return iver1 + iver2 + iver3;
-+}
-+
- /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
- static bool
- microblaze_const_double_ok (rtx op, machine_mode mode)
-@@ -1266,8 +1323,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
-       {
- 	if (TARGET_BARREL_SHIFT)
- 	  {
--	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
--		>= 0)
-+	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
- 	      *total = COSTS_N_INSNS (1);
- 	    else
- 	      *total = COSTS_N_INSNS (2);
-@@ -1328,8 +1384,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
- 	  }
- 	else if (!TARGET_SOFT_MUL)
- 	  {
--	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
--		>= 0)
-+	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
- 	      *total = COSTS_N_INSNS (1);
- 	    else
- 	      *total = COSTS_N_INSNS (3);
-@@ -1609,72 +1664,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
-   return 0;
- }
- 
--/*  Convert a version number of the form "vX.YY.Z" to an integer encoding 
--    for easier range comparison.  */
--static int
--microblaze_version_to_int (const char *version)
--{
--  const char *p, *v;
--  const char *tmpl = "vXX.YY.Z";
--  int iver = 0;
--
--  p = version;
--  v = tmpl;
--
--  while (*p)
--    {
--      if (*v == 'X')
--	{			/* Looking for major  */
--          if (*p == '.')
--            {
--              v++;
--            }
--          else
--            {
--	      if (!(*p >= '0' && *p <= '9'))
--	        return -1;
--	      iver += (int) (*p - '0');
--              iver *= 10;
--	     }
--        }
--      else if (*v == 'Y')
--	{			/* Looking for minor  */
--	  if (!(*p >= '0' && *p <= '9'))
--	    return -1;
--	  iver += (int) (*p - '0');
--	  iver *= 10;
--	}
--      else if (*v == 'Z')
--	{			/* Looking for compat  */
--	  if (!(*p >= 'a' && *p <= 'z'))
--	    return -1;
--	  iver *= 10;
--	  iver += (int) (*p - 'a');
--	}
--      else
--	{
--	  if (*p != *v)
--	    return -1;
--	}
--
--      v++;
--      p++;
--    }
--
--  if (*p)
--    return -1;
--
--  return iver;
--}
--
--
- static void
- microblaze_option_override (void)
- {
-   register int i, start;
-   register int regno;
-   register machine_mode mode;
--  int ver;
-+  int ver,ver_int;
- 
-   microblaze_section_threshold = (global_options_set.x_g_switch_value
- 				  ? g_switch_value
-@@ -1695,13 +1691,13 @@ microblaze_option_override (void)
-   /* Check the MicroBlaze CPU version for any special action to be done.  */
-   if (microblaze_select_cpu == NULL)
-     microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
--  ver = microblaze_version_to_int (microblaze_select_cpu);
--  if (ver == -1)
-+  ver_int = microblaze_version_to_int (microblaze_select_cpu);
-+  if (ver_int == -1)
-     {
-       error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu);
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
-+  ver = ver_int - microblaze_version_to_int("v3.00.a");
-   if (ver < 0)
-     {
-       /* No hardware exceptions in earlier versions. So no worries.  */
-@@ -1712,8 +1708,7 @@ microblaze_option_override (void)
-       microblaze_pipe = MICROBLAZE_PIPE_3;
-     }
-   else if (ver == 0
--	   || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
--	       == 0))
-+	   || (ver_int ==  microblaze_version_to_int("v4.00.b")))
-     {
- #if 0
-       microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
-@@ -1730,11 +1725,9 @@ microblaze_option_override (void)
- #endif
-       microblaze_no_unsafe_delay = 0;
-       microblaze_pipe = MICROBLAZE_PIPE_5;
--      if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
--	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
--					 "v5.00.b") == 0
--	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
--					 "v5.00.c") == 0)
-+      if ((ver_int == microblaze_version_to_int("v5.00.a"))
-+	  || (ver_int == microblaze_version_to_int("v5.00.b"))
-+	  || (ver_int == microblaze_version_to_int("v5.00.c")))
- 	{
- 	  /* Pattern compares are to be turned on by default only when 
-  	     compiling for MB v5.00.'z'.  */
-@@ -1742,7 +1735,7 @@ microblaze_option_override (void)
- 	}
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
-+  ver = ver_int - microblaze_version_to_int("v6.00.a");
-   if (ver < 0)
-     {
-       if (TARGET_MULTIPLY_HIGH)
-@@ -1750,7 +1743,7 @@ microblaze_option_override (void)
- 		 "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater");
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
-+  ver = ver_int - microblaze_version_to_int("v8.10.a");
-   microblaze_has_clz = 1;
-   if (ver < 0)
-     {
-@@ -1759,7 +1752,7 @@ microblaze_option_override (void)
-     }
- 
-   /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
-+  ver = ver_int - microblaze_version_to_int("v8.30.a");
-   if (ver < 0)
-     {
-         if (TARGET_REORDER == 1)
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
deleted file mode 100644
index 15111477..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
+++ /dev/null
@@ -1,48 +0,0 @@
-From f3e259923788176ebb323155cc089e68c6de0895 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 13:57:48 +0530
-Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field
- instruction should be generated only if mcpu >10.0
-
----
- gcc/config/microblaze/microblaze.c | 3 +++
- gcc/config/microblaze/microblaze.h | 2 ++
- 2 files changed, 5 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 30a0fcf..835e906 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -163,6 +163,9 @@ int microblaze_no_unsafe_delay;
- /* Set to one if the targeted core has the CLZ insn.  */
- int microblaze_has_clz = 0;
- 
-+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
-+int microblaze_has_bitfield = 0;
-+
- /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
-    version having only a particular type of pipeline. There can still be 
-    options on the CPU to scale pipeline features up or down. :( 
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 2ac5aeec..991d0f7 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
- 
- extern int microblaze_no_unsafe_delay;
- extern int microblaze_has_clz;
-+extern int microblaze_has_bitfield;
- extern enum pipeline_type microblaze_pipe;
- 
- #define OBJECT_FORMAT_ELF
-@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
- 
- /* Do we have CLZ?  */
- #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
-+#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
- 
- /* The default is to support PIC.  */
- #define TARGET_SUPPORTS_PIC 1
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
deleted file mode 100644
index f22f2f3f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 52cf8e91f06ce9259d4d94bb8ea5cb327825b806 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 20:57:10 +0530
-Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal
- patches has been removed in gcc 6.2 version so modified the code accordingly.
-
----
- gcc/config/microblaze/microblaze.c | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 835e906..2e3b4c9 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2520,11 +2520,9 @@ print_operand (FILE * file, rtx op, int letter)
- 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
- 	  else
- 	    {
--	      REAL_VALUE_TYPE rv;
--	      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
--	      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
--	      val[1] = l[WORDS_BIG_ENDIAN == 0];
--	      val[0] = l[WORDS_BIG_ENDIAN != 0];
-+              REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-+              val[1] = l[WORDS_BIG_ENDIAN == 0];
-+              val[0] = l[WORDS_BIG_ENDIAN != 0];
- 	    }
- 	}
-       else if (code == CONST_INT)
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch
deleted file mode 100644
index 00d67bcf..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 727b0f7ae03279177559f5d85d8920352bd853b2 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 23 Feb 2017 17:09:04 +0530
-Subject: [PATCH 35/54] Fixing the issue with the builtin_alloc. register r18
- was not properly handling the stack pattern which was resolved by using free
- available register
-
-signed-off-by:nagaraju mekala <nmekala@xilinx.com>
----
- gcc/config/microblaze/microblaze.md | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 5a2dd13..8072ffc 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2076,10 +2076,10 @@
-   ""
-   { 
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
--    rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-+    rtx reg = gen_reg_rtx (Pmode);
-     rtx neg_op0;
- 
--    emit_move_insn (rtmp, retaddr);
-+    emit_move_insn (reg, retaddr);
-     if (GET_CODE (operands[1]) != CONST_INT)
-     {
-         neg_op0 = gen_reg_rtx (Pmode);
-@@ -2088,9 +2088,9 @@
-         neg_op0 = GEN_INT (- INTVAL (operands[1]));
- 
-     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
--    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
-+    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
-     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
--    emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
-+    emit_insn (gen_rtx_CLOBBER (SImode, reg));
-     DONE;
-   }
- )
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
deleted file mode 100644
index 54ccd9a0..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 7156e379a67fa47a5fb9ede1448c0d528dbda65b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 2 Mar 2017 19:02:31 +0530
-Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before
- propagating constants.
-
----
- gcc/cprop.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/gcc/cprop.c b/gcc/cprop.c
-index e4df509..deb706b 100644
---- a/gcc/cprop.c
-+++ b/gcc/cprop.c
-@@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
-   int success = 0;
-   rtx set = single_set (insn);
- 
-+#if 0
-   bool check_rtx_costs = true;
-   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
-   int old_cost = set ? set_rtx_cost (set, speed) : 0;
-@@ -744,6 +745,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
- 	  && (GET_CODE (XEXP (note, 0)) == CONST
- 	      || CONSTANT_P (XEXP (note, 0)))))
-     check_rtx_costs = false;
-+#endif
- 
-   /* Usually we substitute easy stuff, so we won't copy everything.
-      We however need to take care to not duplicate non-trivial CONST
-@@ -752,6 +754,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
- 
-   validate_replace_src_group (from, to, insn);
- 
-+#if 0
-   /* If TO is a constant, check the cost of the set after propagation
-      to the cost of the set before the propagation.  If the cost is
-      higher, then do not replace FROM with TO.  */
-@@ -764,6 +767,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
-       return false;
-     }
- 
-+#endif
- 
-   if (num_changes_pending () && apply_change_group ())
-     success = 1;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
deleted file mode 100644
index 26b685a5..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 19 Feb 2018 18:06:16 +0530
-Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield
- insert and extract instructions.
-
----
- gcc/config/microblaze/microblaze.md | 43 ++++++-------------------------------
- 1 file changed, 7 insertions(+), 36 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8072ffc..9bb87ec 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2476,33 +2476,17 @@
-   DONE;
- }")
- 
--(define_expand "extvsi"
-+(define_expand "extzvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
- 			 (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
--"
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
--
--  if ((len == 0) || (pos + len > 32) )
--    FAIL;
--
--  ;;if (!register_operand (operands[1], VOIDmode))
--  ;;  FAIL;
--  if (operands[0] == operands[1])
--  FAIL;
--  if (GET_CODE (operands[1]) == ASHIFT)
--  FAIL;
--;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-- emit_insn (gen_extv_32 (operands[0], operands[1],
--			  operands[2], operands[3]));
--  DONE;
--}")
-+""
-+)
- 
--(define_insn "extv_32"
-+
-+(define_insn "extzv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2519,21 +2503,8 @@
- 			 (match_operand:SI 2 "immediate_operand" "I"))
- 	(match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
--  "
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
--
--  if (len <= 0 || pos + len > 32)
--    FAIL;
--
--  ;;if (!register_operand (operands[0], VOIDmode))
--  ;;  FAIL;
--
--  emit_insn (gen_insv_32 (operands[0], operands[1],
--			  operands[2], operands[3]));
--  DONE;
--}")
-+""
-+)
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
deleted file mode 100644
index d8ae6c15..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 5494699756f8e1dba6848fcf09780a031139c232 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 4 Jun 2018 10:10:18 +0530
-Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for
- double values.
-
----
- gcc/config/microblaze/microblaze.md | 14 --------------
- 1 file changed, 14 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 9bb87ec..a93ddd0 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -524,20 +524,6 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
--(define_insn "sqrtdf2"
--  [(set (match_operand:DF 0 "register_operand" "=d")
--        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
--  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
--  {
--    if (REGNO (operands[0]) == REGNO (operands[1]))
--      return "fsqrt\t%0,%1";
--    else
--      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
--  }
--  [(set_attr "type"     "fsqrt")
--   (set_attr "mode"      "SF")
--   (set_attr "length"    "4")])
--
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch
deleted file mode 100644
index 88497a8e..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch
+++ /dev/null
@@ -1,810 +0,0 @@
-From 6e8b37bf54646c38fb4071d542a60ea92715df9b Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 3 Apr 2018 16:48:39 +0530
-Subject: [PATCH 39/54] Intial commit of 64-bit Microblaze
-
----
- gcc/config/microblaze/microblaze-protos.h |   1 +
- gcc/config/microblaze/microblaze.c        | 109 +++++++--
- gcc/config/microblaze/microblaze.h        |   4 +-
- gcc/config/microblaze/microblaze.md       | 370 +++++++++++++++++++++++++++++-
- gcc/config/microblaze/microblaze.opt      |   9 +-
- gcc/config/microblaze/t-microblaze        |   7 +-
- 6 files changed, 461 insertions(+), 39 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index c39e2e9..a5ed62e 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -35,6 +35,7 @@ extern void microblaze_expand_divide (rtx *);
- extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_sf (rtx *); 
-+extern void microblaze_expand_conditional_branch_df (rtx *); 
- extern int microblaze_can_use_return_insn (void);
- extern void print_operand (FILE *, rtx, int);
- extern void print_operand_address (FILE *, rtx);
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 2e3b4c9..2079ae9 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3457,11 +3457,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
-   op0 = operands[0];
-   op1 = operands[1];
- 
--  if (!register_operand (op0, SImode)
--      && !register_operand (op1, SImode)
-+  if (!register_operand (op0, mode)
-+      && !register_operand (op1, mode)
-       && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
-     {
--      rtx temp = force_reg (SImode, op1);
-+      rtx temp = force_reg (mode, op1);
-       emit_move_insn (op0, temp);
-       return true;
-     }
-@@ -3499,12 +3499,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
- 	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
- 		      || !SMALL_INT (p1)))))
- 	{
--	  rtx temp = force_reg (SImode, p0);
-+	  rtx temp = force_reg (mode, p0);
- 	  rtx temp2 = p1;
- 
- 	  if (flag_pic && reload_in_progress)
- 	    df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
--	  emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
-+	  emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
- 	  return true;
- 	}
-     }
-@@ -3635,7 +3635,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-   rtx cmp_op0 = operands[1];
-   rtx cmp_op1 = operands[2];
-   rtx label1 = operands[3];
--  rtx comp_reg = gen_reg_rtx (SImode);
-+  rtx comp_reg = gen_reg_rtx (mode);
-   rtx condition;
- 
-   gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
-@@ -3644,23 +3644,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-   if (cmp_op1 == const0_rtx)
-     {
-       comp_reg = cmp_op0;
--      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-+
-     }
- 
-   else if (code == EQ || code == NE)
-     {
-       /* Use xor for equal/not-equal comparison.  */
--      emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
--      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
-+      else
-+        emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
-+      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else
-     {
-       /* Generate compare and branch in single instruction. */
-       cmp_op1 = force_reg (mode, cmp_op1);
-       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
--      emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
-+      if (mode == SImode)
-+        emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
-+      else
-+        emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
-     }
- }
- 
-@@ -3671,7 +3684,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-   rtx cmp_op0 = operands[1];
-   rtx cmp_op1 = operands[2];
-   rtx label1 = operands[3];
--  rtx comp_reg = gen_reg_rtx (SImode);
-+  rtx comp_reg = gen_reg_rtx (mode);
-   rtx condition;
- 
-   gcc_assert ((GET_CODE (cmp_op0) == REG)
-@@ -3682,30 +3695,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code),
--                                  SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+                                  mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else if (code == EQ)
-     {
--      emit_insn (gen_seq_internal_pat (comp_reg,
--                                       cmp_op0, cmp_op1));
--      condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        {
-+          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      else
-+        {
-+          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-+ 
-     }
-   else if (code == NE)
-     {
--      emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
--                                       cmp_op1));
--      condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        {
-+          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      else
-+        {
-+          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else
-     {
-       /* Generate compare and branch in single instruction. */
-       cmp_op1 = force_reg (mode, cmp_op1);
-       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
--      emit_jump_insn (gen_branch_compare (condition, cmp_op0,
--                                         cmp_op1, label1));
-+      if (mode == SImode)
-+        emit_jump_insn (gen_branch_compare (condition, cmp_op0,
-+                                           cmp_op1, label1));
-+      else 
-+	{
-+          emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
-+                                             cmp_op1, label1));
-+        }	
-+
-     }
- }
- 
-@@ -3722,6 +3768,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
-   emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
-+void
-+microblaze_expand_conditional_branch_df (rtx operands[])
-+{
-+  rtx condition;
-+  rtx cmp_op0 = XEXP (operands[0], 0);
-+  rtx cmp_op1 = XEXP (operands[0], 1);
-+  rtx comp_reg = gen_reg_rtx (DImode);
-+
-+  emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
-+  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
-+  emit_jump_insn (gen_long_condjump (condition, operands[3]));
-+}
-+
- /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
- 
- static bool
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 991d0f7..72fbee5 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
- #define ASM_SPEC "\
- %(target_asm_spec) \
- %{mbig-endian:-EB} \
-+%{m64:-m64} \
- %{mlittle-endian:-EL}"
- 
- /* Extra switches sometimes passed to the linker.  */
-@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
- #define LINK_SPEC "%{shared:-shared} -N -relax \
-   %{mbig-endian:-EB --oformat=elf32-microblaze} \
-   %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
-+  %{m64:-EL --oformat=elf64-microblazeel} \
-   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
-   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
-   %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
-@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
- #define MIN_UNITS_PER_WORD      4
- #define INT_TYPE_SIZE           32
- #define SHORT_TYPE_SIZE         16
--#define LONG_TYPE_SIZE          32
-+#define LONG_TYPE_SIZE          64
- #define LONG_LONG_TYPE_SIZE     64
- #define FLOAT_TYPE_SIZE         32
- #define DOUBLE_TYPE_SIZE        64
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a93ddd0..6976b37 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -495,7 +495,6 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
--
- (define_insn "divsf3"
-   [(set (match_operand:SF 0 "register_operand" "=d")
-         (div:SF (match_operand:SF 1 "register_operand" "d")
-@@ -506,6 +505,7 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+
- (define_insn "sqrtsf2"
-   [(set (match_operand:SF 0 "register_operand" "=d")
-         (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
-@@ -560,6 +560,18 @@
- 
- ;; Adding 2 DI operands in register or reg/imm
- 
-+(define_insn "adddi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
-+		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   addlk\t%0,%z1,%2
-+   addlik\t%0,%z1,%2"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "adddi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-@@ -604,6 +616,18 @@
- ;; Double Precision Subtraction
- ;;----------------------------------------------------------------
- 
-+(define_insn "subdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
-+		  (match_operand:DI 2 "register_operand" "d,n")))]
-+  "TARGET_MB_64"
-+  "@
-+   rsubl\t%0,%2,%1
-+   addlik\t%0,%z1,-%2"
-+  [(set_attr "type"	"darith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "subdi3"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
-@@ -793,6 +817,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "negdi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "rsubl\t%0,%1,r0"
-+  [(set_attr "type"	"darith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "negdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -812,6 +845,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "one_cmpldi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "xorli\t%0,%1,-1"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "*one_cmpldi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -838,6 +880,20 @@
- ;; Logical
- ;;----------------------------------------------------------------
- 
-+(define_insn "anddi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   andl\t%0,%1,%2
-+   andli\t%0,%1,%2 #andl1"
-+  ;; andli\t%0,%1,%2 #andl3
-+  ;; andli\t%0,%1,%2 #andl2
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "andsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- 	(and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -853,6 +909,18 @@
-   (set_attr "length"	"4,8,8,8")])
- 
- 
-+(define_insn "iordi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ior:DI (match_operand:DI 1 "arith_operand" "d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   orl\t%0,%1,%2
-+   orli\t%0,%1,%2 #andl1"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "iorsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- 	(ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -867,6 +935,19 @@
-   (set_attr "mode"	"SI,SI,SI,SI")
-   (set_attr "length"	"4,8,8,8")])
- 
-+(define_insn "xordi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   xorl\t%0,%1,%2
-+   xorli\t%0,%1,%2 #andl1"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
-+
- (define_insn "xorsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- 	(xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
-@@ -935,6 +1016,26 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+;;(define_expand "extendqidi2"
-+;;  [(set (match_operand:DI 0 "register_operand" "=d")
-+;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
-+;;  "TARGET_MB_64"
-+;;  {
-+;;	if (GET_CODE (operands[1]) != REG)
-+;;	FAIL;
-+;;   }
-+;;)
-+    
-+
-+;;(define_insn "extendqidi2"
-+;;  [(set (match_operand:DI 0 "register_operand" "=d")
-+;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
-+;;  "TARGET_MB_64"
-+;;  "sextl8\t%0,%1"
-+;;  [(set_attr "type"	"arith")
-+;;  (set_attr "mode"	"DI")
-+;;  (set_attr "length"	"4")])
-+
- (define_insn "extendhisi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -944,6 +1045,16 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "extendhidi2"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "sextl16\t%0,%1"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+
- ;; Those for integer source operand are ordered
- ;; widest source type first.
- 
-@@ -1009,7 +1120,6 @@
- )
- 
- 
--
- (define_insn "*movdi_internal"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
- 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
-@@ -1421,6 +1531,36 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+;; Barrel shift left
-+(define_expand "ashldi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "ashldi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+  bsllli\t%0,%1,%2
-+  bslll\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+)
- ;; The following patterns apply when there is no barrel shifter present
- 
- (define_insn "*ashlsi3_with_mul_delay"
-@@ -1546,6 +1686,36 @@
- ;;----------------------------------------------------------------
- ;; 32-bit right shifts
- ;;----------------------------------------------------------------
-+;; Barrel shift left
-+(define_expand "ashrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "ashrdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+   bslrai\t%0,%1,%2
-+   bslra\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+  )
- (define_expand "ashrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -1655,6 +1825,36 @@
- ;;----------------------------------------------------------------
- ;; 32-bit right shifts (logical)
- ;;----------------------------------------------------------------
-+;; Barrel shift left
-+(define_expand "lshrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "lshrdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+   bslrli\t%0,%1,%2
-+   bslrl\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+  )
- 
- (define_expand "lshrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-@@ -1801,6 +2001,8 @@
-   (set_attr "length"	"4")]
- )              
- 
-+
-+
- ;;----------------------------------------------------------------
- ;; Setting a register from an floating point comparison. 
- ;;----------------------------------------------------------------
-@@ -1816,6 +2018,18 @@
-    (set_attr "length"    "4")]
- )
- 
-+(define_insn "cstoredf4"
-+   [(set (match_operand:DI 0 "register_operand" "=r")
-+        (match_operator:DI 1 "ordered_comparison_operator"
-+	      [(match_operand:DF 2 "register_operand" "r")
-+	       (match_operand:DF 3 "register_operand" "r")]))]
-+  "TARGET_MB_64"
-+  "dcmp.%C1\t%0,%3,%2"
-+  [(set_attr "type"     "fcmp")
-+   (set_attr "mode"      "DF")
-+   (set_attr "length"    "4")]
-+)
-+
- ;;----------------------------------------------------------------
- ;; Conditional branches
- ;;----------------------------------------------------------------
-@@ -1928,6 +2142,115 @@
-    (set_attr "length"   "12")]
- )
- 
-+
-+(define_expand "cbranchdi4"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "ordered_comparison_operator"
-+                       [(match_operand:DI 1 "register_operand")
-+                        (match_operand:DI 2 "arith_operand" "I,i")])
-+                      (label_ref (match_operand 3 ""))
-+                      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch (DImode, operands);
-+  DONE;
-+})
-+
-+(define_expand "cbranchdi4_reg"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "ordered_comparison_operator"
-+                       [(match_operand:DI 1 "register_operand")
-+                        (match_operand:DI 2 "register_operand")])
-+                      (label_ref (match_operand 3 ""))
-+                      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch_reg (DImode, operands);
-+  DONE;
-+})
-+
-+(define_expand "cbranchdf4"
-+  [(set (pc)
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-+		       [(match_operand:DF 1 "register_operand")
-+		        (match_operand:DF 2 "register_operand")])
-+		      (label_ref (match_operand 3 ""))
-+		      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch_df (operands);
-+  DONE;
-+
-+})
-+
-+;; Used to implement comparison instructions
-+(define_expand "long_condjump"
-+  [(set (pc)
-+	(if_then_else (match_operand 0)
-+		      (label_ref (match_operand 1))
-+		      (pc)))])
-+
-+(define_insn "long_branch_zero"
-+  [(set (pc)
-+	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
-+  				 [(match_operand:DI 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand:DI 2 "pc_or_label_operand" "")
-+                      (match_operand:DI 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "beal%C0i%?\t%z1,%2";
-+    else 
-+      return "beal%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
-+(define_insn "long_branch_compare"
-+  [(set (pc)
-+        (if_then_else (match_operator:DI 0 "cmp_op"
-+                                         [(match_operand:DI 1 "register_operand" "d")
-+                                          (match_operand:DI 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:DI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
-+    return "beal%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
-@@ -2462,17 +2785,33 @@
-   DONE;
- }")
- 
--(define_expand "extzvsi"
-+(define_expand "extvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
- 			 (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
--""
--)
--
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
- 
--(define_insn "extzv_32"
-+(define_insn "extv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2489,8 +2828,21 @@
- 			 (match_operand:SI 2 "immediate_operand" "I"))
- 	(match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
--""
--)
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index c8e6f00..cdcae00 100644
---- a/gcc/config/microblaze/microblaze.opt
-+++ b/gcc/config/microblaze/microblaze.opt
-@@ -125,11 +125,16 @@ Description for mxl-mode-novectors.
- 
- mxl-prefetch
- Target Mask(PREFETCH)
--Use hardware prefetch instruction
-+Use hardware prefetch instruction.
- 
- mxl-mode-xilkernel
- Target
- 
- mxl-frequency
- Target Mask(AREA_OPTIMIZED_2)
--Use 8 stage pipeline (frequency optimization)
-+Use 8 stage pipeline (frequency optimization).
-+
-+m64
-+Target Mask(MB_64)
-+MicroBlaze 64-bit mode.
-+
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 41fa9a9..e9a1921 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,8 +1,11 @@
--MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
--MULTILIB_DIRNAMES = bs m mh le
-+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
-+MULTILIB_DIRNAMES = bs m mh le m64
- MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
- MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
-+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
deleted file mode 100644
index 1157a82f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 5526d87787d61990be3187b230fae4d0591d0651 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Wed, 4 Apr 2018 16:41:41 +0530
-Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing
- files
-
----
- gcc/config/microblaze/constraints.md |  5 +++++
- gcc/config/microblaze/microblaze.md  | 26 ++++++++++++++++++++++++++
- gcc/config/microblaze/t-microblaze   |  4 ++--
- 3 files changed, 33 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index ae14944..a06b4d8 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -52,6 +52,11 @@
-   (and (match_code "const_int")
-        (match_test "ival > 0 && ival < 0x10000")))
- 
-+(define_constraint "K"
-+  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-+  (and (match_code "const_int")
-+       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
-+
- ;; Define floating point constraints
- 
- (define_constraint "G"
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6976b37..0cd0441 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1120,6 +1120,32 @@
- )
- 
- 
-+(define_insn "*movdi_internal_64"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
-+	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
-+  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
-+  { 
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "addlk\t%0,%1";
-+      case 1:
-+	return "addlik\t%0,r0,%1";
-+      case 2:
-+	  return "addlk\t%0,r0,r0";
-+      case 3:
-+      case 4:
-+	  return "lli\t%0,%1";
-+      case 5:
-+      case 6:
-+        return "sli\t%1,%0";
-+    }
-+    return "unreachable";
-+  }
-+  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"   "8,8,8,8,12,8,12")])
-+
- (define_insn "*movdi_internal"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
- 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index e9a1921..7671f63 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -4,8 +4,8 @@ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
- MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch
deleted file mode 100644
index 411958e7..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch
+++ /dev/null
@@ -1,2463 +0,0 @@
-From eee9b7f7423823b133d6a5e5382863502433bdc6 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 27 Jul 2018 15:23:41 +0530
-Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the
- code later.
-
----
- gcc/config/microblaze/constraints.md    |   2 +-
- gcc/config/microblaze/microblaze-c.c    |   6 +
- gcc/config/microblaze/microblaze.c      | 218 ++++++++----
- gcc/config/microblaze/microblaze.h      |  63 ++--
- gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++++++++--------
- gcc/config/microblaze/t-microblaze      |   7 +-
- libgcc/config/microblaze/crti.S         |   4 +-
- libgcc/config/microblaze/crtn.S         |   4 +-
- libgcc/config/microblaze/divdi3.S       |  98 ++++++
- libgcc/config/microblaze/divdi3_table.c |  62 ++++
- libgcc/config/microblaze/moddi3.S       |  97 +++++
- libgcc/config/microblaze/muldi3.S       |  73 ++++
- libgcc/config/microblaze/t-microblaze   |  11 +-
- libgcc/config/microblaze/udivdi3.S      | 107 ++++++
- libgcc/config/microblaze/umoddi3.S      | 110 ++++++
- 15 files changed, 1232 insertions(+), 236 deletions(-)
- create mode 100644 libgcc/config/microblaze/divdi3.S
- create mode 100644 libgcc/config/microblaze/divdi3_table.c
- create mode 100644 libgcc/config/microblaze/moddi3.S
- create mode 100644 libgcc/config/microblaze/muldi3.S
- create mode 100644 libgcc/config/microblaze/udivdi3.S
- create mode 100644 libgcc/config/microblaze/umoddi3.S
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index a06b4d8..867a7b5 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -55,7 +55,7 @@
- (define_constraint "K"
-   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-   (and (match_code "const_int")
--       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
-+       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
- 
- ;; Define floating point constraints
- 
-diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index 7b020b5..d8a1d13 100644
---- a/gcc/config/microblaze/microblaze-c.c
-+++ b/gcc/config/microblaze/microblaze-c.c
-@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
-         builtin_define ("HAVE_HW_FPU_SQRT");
-       builtin_define ("__HAVE_HW_FPU_SQRT__");
-     }
-+  if (TARGET_MB_64)
-+    {
-+      builtin_define ("__arch64__");
-+      builtin_define ("__microblaze64__");
-+      builtin_define ("__MICROBLAZE64__");
-+    }
- }  
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 2079ae9..ba7ade4 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -382,10 +382,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
- 	{
- 	  return 1;
- 	}
--      else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
-+      /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
- 	{
- 	  return 1;
--	}
-+	}*/
-       else
- 	return 0;
- 
-@@ -433,7 +433,7 @@ double_memory_operand (rtx op, machine_mode mode)
-     return 1;
- 
-   return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
--			    ? E_SImode : E_SFmode),
-+			    ? Pmode : E_SFmode),
- 			   plus_constant (Pmode, addr, 4));
- }
- 
-@@ -680,7 +680,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
-          /* Load the addend.  */
-          addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
- 				  UNSPEC_TLS);
--         addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
-+         addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
-          dest = gen_rtx_PLUS (Pmode, dest, addend);
-          break;
- 
-@@ -698,7 +698,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
- 
-   if (XINT (x, 1) == UNSPEC_GOTOFF)
-     {
--      info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
-+      info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
-       info->type = ADDRESS_GOTOFF;
-     }
-   else if (XINT (x, 1) == UNSPEC_PLT)
-@@ -1230,8 +1230,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
-   emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
- 
-   /* Emit the test & branch.  */
--  emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
-+
-+  if (TARGET_MB_64) {
-+    emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
-+			     src_reg, final_src, label));
-+    }
-+  else {
-+    emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
- 			     src_reg, final_src, label));
-+  
-+    }
- 
-   /* Mop up any left-over bytes.  */
-   if (leftover)
-@@ -1561,14 +1569,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
-       break;
- 
-     case E_DFmode:
--      cum->arg_words += 2;
-+      if (TARGET_MB_64)
-+       cum->arg_words++;
-+      else
-+       cum->arg_words += 2;
-       if (!cum->gp_reg_found && cum->arg_number <= 2)
- 	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
-       break;
- 
-     case E_DImode:
-       cum->gp_reg_found = 1;
--      cum->arg_words += 2;
-+      if (TARGET_MB_64)
-+       cum->arg_words++;
-+      else
-+       cum->arg_words += 2;
-       break;
- 
-     case E_QImode:
-@@ -2219,7 +2233,7 @@ compute_frame_size (HOST_WIDE_INT size)
- 
- 	  if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
- 	    /* Don't account for link register. It is accounted specially below.  */
--	    gp_reg_size += GET_MODE_SIZE (SImode);
-+	    gp_reg_size += GET_MODE_SIZE (Pmode);
- 
- 	  mask |= (1L << (regno - GP_REG_FIRST));
- 	}
-@@ -2487,7 +2501,7 @@ print_operand (FILE * file, rtx op, int letter)
- 
-       if ((letter == 'M' && !WORDS_BIG_ENDIAN)
- 	  || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
--	regnum++;
-+	regnum++; 
- 
-       fprintf (file, "%s", reg_names[regnum]);
-     }
-@@ -2513,6 +2527,7 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
-+      int val1[2];
-       long l[2];
-       if (code == CONST_DOUBLE)
- 	{
-@@ -2525,12 +2540,12 @@ print_operand (FILE * file, rtx op, int letter)
-               val[0] = l[WORDS_BIG_ENDIAN != 0];
- 	    }
- 	}
--      else if (code == CONST_INT)
-+      else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
-         {
--	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
--	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
-+	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
-+	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
-         }
--      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-+      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
-     }
-   else if (code == CONST_DOUBLE)
-     {
-@@ -2713,7 +2728,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
- 
-     switch_to_section (get_section (section, 0, NULL));
-     assemble_align (POINTER_SIZE);
--    fputs ("\t.word\t", asm_out_file);
-+    if (TARGET_MB_64)
-+      fputs ("\t.dword\t", asm_out_file);
-+    else
-+      fputs ("\t.word\t", asm_out_file);
-     output_addr_const (asm_out_file, symbol);
-     fputs ("\n", asm_out_file);
- }
-@@ -2736,7 +2754,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
- 
-     switch_to_section (get_section (section, 0, NULL));
-     assemble_align (POINTER_SIZE);
--    fputs ("\t.word\t", asm_out_file);
-+    if (TARGET_MB_64)
-+      fputs ("\t.dword\t", asm_out_file);
-+    else
-+     fputs ("\t.word\t", asm_out_file);
-     output_addr_const (asm_out_file, symbol);
-     fputs ("\n", asm_out_file);
- }
-@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue)
-   /* For interrupt_handlers, need to save/restore the MSR.  */
-   if (microblaze_is_interrupt_variant ())
-     {
--      isr_mem_rtx = gen_rtx_MEM (SImode,
-+      isr_mem_rtx = gen_rtx_MEM (Pmode,
- 				 gen_rtx_PLUS (Pmode, base_reg_rtx,
- 					       GEN_INT (current_frame_info.
- 							gp_offset -
-@@ -2810,8 +2831,8 @@ save_restore_insns (int prologue)
- 
-       /* Do not optimize in flow analysis.  */
-       MEM_VOLATILE_P (isr_mem_rtx) = 1;
--      isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
--      isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
-+      isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
-+      isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
-     }
- 
-   if (microblaze_is_interrupt_variant () && !prologue)
-@@ -2819,8 +2840,8 @@ save_restore_insns (int prologue)
-       emit_move_insn (isr_reg_rtx, isr_mem_rtx);
-       emit_move_insn (isr_msr_rtx, isr_reg_rtx);
-       /* Do not optimize in flow analysis.  */
--      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
--      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
-     }
- 
-   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-@@ -2831,9 +2852,9 @@ save_restore_insns (int prologue)
- 	    /* Don't handle here. Already handled as the first register.  */
- 	    continue;
- 
--	  reg_rtx = gen_rtx_REG (SImode, regno);
-+	  reg_rtx = gen_rtx_REG (Pmode, regno);
- 	  insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
--	  mem_rtx = gen_rtx_MEM (SImode, insn);
-+	  mem_rtx = gen_rtx_MEM (Pmode, insn);
- 	  if (microblaze_is_interrupt_variant () || save_volatiles)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
-@@ -2848,7 +2869,7 @@ save_restore_insns (int prologue)
- 	      insn = emit_move_insn (reg_rtx, mem_rtx);
- 	    }
- 
--	  gp_offset += GET_MODE_SIZE (SImode);
-+	  gp_offset += GET_MODE_SIZE (Pmode);
- 	}
-     }
- 
-@@ -2858,8 +2879,8 @@ save_restore_insns (int prologue)
-       emit_move_insn (isr_mem_rtx, isr_reg_rtx);
- 
-       /* Do not optimize in flow analysis.  */
--      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
--      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
-     }
- 
-   /* Done saving and restoring */
-@@ -2949,7 +2970,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
- 
-   switch_to_section (s);
-   assemble_align (POINTER_SIZE);
--  fputs ("\t.word\t", asm_out_file);
-+  if (TARGET_MB_64)
-+    fputs ("\t.dword\t", asm_out_file);
-+  else
-+    fputs ("\t.word\t", asm_out_file);
-   output_addr_const (asm_out_file, symbol);
-   fputs ("\n", asm_out_file);
- }
-@@ -3095,10 +3119,10 @@ microblaze_expand_prologue (void)
- 	{
- 	  if (offset != 0)
- 	    ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
--	  emit_move_insn (gen_rtx_MEM (SImode, ptr),
--			  gen_rtx_REG (SImode, regno));
-+	  emit_move_insn (gen_rtx_MEM (Pmode, ptr),
-+			  gen_rtx_REG (Pmode, regno));
- 
--	  offset += GET_MODE_SIZE (SImode);
-+	  offset += GET_MODE_SIZE (Pmode);
- 	}
- 
-     }
-@@ -3108,15 +3132,23 @@ microblaze_expand_prologue (void)
-       rtx fsiz_rtx = GEN_INT (fsiz);
- 
-       rtx_insn *insn = NULL;
--      insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-+         if (TARGET_MB_64)
-+           {
-+              
-+             insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
- 				    fsiz_rtx));
-+           }
-+         else { 
-+             insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-+				    fsiz_rtx));
-+           }
-       if (insn)
- 	RTX_FRAME_RELATED_P (insn) = 1;
- 
-       /* Handle SUB_RETURN_ADDR_REGNUM specially at first.  */
-       if (!crtl->is_leaf || interrupt_handler)
- 	{
--	  mem_rtx = gen_rtx_MEM (SImode,
-+	  mem_rtx = gen_rtx_MEM (Pmode,
- 				 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
- 					       const0_rtx));
- 
-@@ -3124,7 +3156,7 @@ microblaze_expand_prologue (void)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
- 
--	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
- 	  insn = emit_move_insn (mem_rtx, reg_rtx);
- 	  RTX_FRAME_RELATED_P (insn) = 1;
- 	}
-@@ -3224,12 +3256,12 @@ microblaze_expand_epilogue (void)
-       if (!crtl->is_leaf || interrupt_handler)
- 	{
- 	  mem_rtx =
--	    gen_rtx_MEM (SImode,
-+	    gen_rtx_MEM (Pmode,
- 			 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
- 	  if (interrupt_handler)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
--	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
- 	  emit_move_insn (reg_rtx, mem_rtx);
- 	}
- 
-@@ -3245,15 +3277,25 @@ microblaze_expand_epilogue (void)
-       /* _restore_ registers for epilogue.  */
-       save_restore_insns (0);
-       emit_insn (gen_blockage ());
--      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-+      if (TARGET_MB_64)
-+        emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-+      else
-+        emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-     }
- 
-   if (crtl->calls_eh_return)
--    emit_insn (gen_addsi3 (stack_pointer_rtx,
-+      if (TARGET_MB_64) {
-+          emit_insn (gen_adddi3 (stack_pointer_rtx,
-                            stack_pointer_rtx,
--                           gen_raw_REG (SImode,
-+                           gen_raw_REG (Pmode,
- 					MB_EH_STACKADJ_REGNUM)));
--
-+        }
-+      else {
-+          emit_insn (gen_addsi3 (stack_pointer_rtx,
-+                           stack_pointer_rtx,
-+                           gen_raw_REG (Pmode,
-+					MB_EH_STACKADJ_REGNUM)));
-+        }
-   emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
- 						    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- }
-@@ -3402,9 +3444,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-   else
-     this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
- 
--  /* Apply the constant offset, if required.  */
-+  /* Apply the constant offset, if required. */ 
-   if (delta)
--    emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
-+    {
-+      if (TARGET_MB_64)
-+        emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); 
-+      else
-+        emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
-+    } 
- 
-   /* Apply the offset from the vtable, if required.  */
-   if (vcall_offset)
-@@ -3417,7 +3464,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-     rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
-     emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
- 
--    emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
-+    if (TARGET_MB_64)
-+      emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
-+    else
-+      emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
-   }
- 
-   /* Generate a tail call to the target function.  */
-@@ -3564,7 +3614,7 @@ microblaze_eh_return (rtx op0)
- /* Queue an .ident string in the queue of top-level asm statements.
-    If the string size is below the threshold, put it into .sdata2.
-    If the front-end is done, we must be being called from toplev.c.
--   In that case, do nothing.  */
-+   In that case, do nothing. */ 
- void 
- microblaze_asm_output_ident (const char *string)
- {
-@@ -3619,9 +3669,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
-   emit_block_move (m_tramp, assemble_trampoline_template (),
- 		   GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
- 
--  mem = adjust_address (m_tramp, SImode, 16);
-+  mem = adjust_address (m_tramp, Pmode, 16);
-   emit_move_insn (mem, chain_value);
--  mem = adjust_address (m_tramp, SImode, 20);
-+  mem = adjust_address (m_tramp, Pmode, 20);
-   emit_move_insn (mem, fnaddr);
- }
- 
-@@ -3645,7 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == SImode)
-+      if (mode == Pmode)
-         emit_jump_insn (gen_condjump (condition, label1));
-       else
-         emit_jump_insn (gen_long_condjump (condition, label1));
-@@ -3764,7 +3814,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
-   rtx comp_reg = gen_reg_rtx (SImode);
- 
-   emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
--  condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
-+  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
-   emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
-@@ -3774,10 +3824,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
-   rtx condition;
-   rtx cmp_op0 = XEXP (operands[0], 0);
-   rtx cmp_op1 = XEXP (operands[0], 1);
--  rtx comp_reg = gen_reg_rtx (DImode);
-+  rtx comp_reg = gen_reg_rtx (Pmode);
- 
-   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
--  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
-+  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
-   emit_jump_insn (gen_long_condjump (condition, operands[3]));
- }
- 
-@@ -3798,8 +3848,8 @@ microblaze_expand_divide (rtx operands[])
- {
-   /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
- 
--  rtx regt1 = gen_reg_rtx (SImode); 
--  rtx reg18 = gen_rtx_REG (SImode, R_TMP);
-+  rtx regt1 = gen_reg_rtx (Pmode); 
-+  rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
-   rtx regqi = gen_reg_rtx (QImode);
-   rtx_code_label *div_label = gen_label_rtx ();
-   rtx_code_label *div_end_label = gen_label_rtx ();
-@@ -3807,17 +3857,31 @@ microblaze_expand_divide (rtx operands[])
-   rtx mem_rtx;
-   rtx ret;
-   rtx_insn *jump, *cjump, *insn;
--
--  insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
--  cjump = emit_jump_insn_after (gen_cbranchsi4 (
--					gen_rtx_GTU (SImode, regt1, GEN_INT (15)), 
-+ 
-+  if (TARGET_MB_64) {
-+      insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
-+      cjump = emit_jump_insn_after (gen_cbranchdi4 (
-+					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
-+					regt1, GEN_INT (15), div_label), insn);
-+    }
-+  else {
-+      insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
-+      cjump = emit_jump_insn_after (gen_cbranchsi4 (
-+					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
- 					regt1, GEN_INT (15), div_label), insn);
-+    }
-   LABEL_NUSES (div_label) = 1; 
-   JUMP_LABEL (cjump) = div_label;
--  emit_insn (gen_rtx_CLOBBER (SImode, reg18));
-+  emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
- 
--  emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
--  emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-+  if (TARGET_MB_64) {
-+      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
-+    }
-+  else  {
-+      emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-+    }
-   mem_rtx = gen_rtx_MEM (QImode,
-                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-@@ -3964,7 +4028,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
-               {
-                 insn =
-                   emit_insn_before (gen_iprefetch
--                                    (gen_int_mode (addr_offset, SImode)),
-+                                    (gen_int_mode (addr_offset, Pmode)),
-                                     before_4);
-                 recog_memoized (insn);
-                 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
-@@ -3974,7 +4038,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
-            }
-        }
- }
--
-+  
-+/* Set the names for various arithmetic operations according to the
-+ *    MICROBLAZE ABI.  */
-+static void
-+microblaze_init_libfuncs (void)
-+{ 
-+  set_optab_libfunc (smod_optab,     SImode, "__modsi3");
-+  set_optab_libfunc (sdiv_optab,     SImode, "__divsi3");
-+  set_optab_libfunc (smul_optab,     SImode, "__mulsi3");
-+  set_optab_libfunc (umod_optab,     SImode, "__umodsi3");
-+  set_optab_libfunc (udiv_optab,     SImode, "__udivsi3");
-+  
-+  if (TARGET_MB_64)
-+    {
-+      set_optab_libfunc (smod_optab,     DImode, "__moddi3");
-+      set_optab_libfunc (sdiv_optab,     DImode, "__divdi3");
-+      set_optab_libfunc (smul_optab,     DImode, "__muldi3");
-+      set_optab_libfunc (umod_optab,     DImode, "__umoddi3");
-+      set_optab_libfunc (udiv_optab,     DImode, "__udivdi3");
-+    }
-+}       
- /* Insert instruction prefetch instruction at the fall
-    through path of the function call.  */
- 
-@@ -4127,6 +4211,17 @@ microblaze_starting_frame_offset (void)
- #undef TARGET_LRA_P
- #define TARGET_LRA_P hook_bool_void_false
- 
-+#ifdef TARGET_MB_64
-+#undef TARGET_ASM_ALIGNED_DI_OP
-+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
-+
-+#undef TARGET_ASM_ALIGNED_HI_OP
-+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
-+
-+#undef TARGET_ASM_ALIGNED_SI_OP
-+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-+#endif
-+
- #undef TARGET_FRAME_POINTER_REQUIRED
- #define TARGET_FRAME_POINTER_REQUIRED	microblaze_frame_pointer_required
- 
-@@ -4136,6 +4231,9 @@ microblaze_starting_frame_offset (void)
- #undef  TARGET_TRAMPOLINE_INIT
- #define TARGET_TRAMPOLINE_INIT		microblaze_trampoline_init
- 
-+#undef TARGET_INIT_LIBFUNCS
-+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
-+
- #undef  TARGET_PROMOTE_FUNCTION_MODE
- #define TARGET_PROMOTE_FUNCTION_MODE 	default_promote_function_mode_always_promote
- 
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 72fbee5..1e60513 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
- 
- /* Generate DWARF exception handling info.  */
- #define DWARF2_UNWIND_INFO 1
--
- /* Don't generate .loc operations.  */
- #define DWARF2_ASM_LINE_DEBUG_INFO 0
- 
-@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
-   ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
- 
- /* Use DWARF 2 debugging information by default.  */
--#define DWARF2_DEBUGGING_INFO
-+#define DWARF2_DEBUGGING_INFO 1
- #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-+#define DWARF2_ADDR_SIZE 4
- 
- /* Target machine storage layout */
- 
- #define BITS_BIG_ENDIAN 0
- #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
- #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
--#define BITS_PER_WORD           32
--#define UNITS_PER_WORD          4
-+//#define BITS_PER_WORD           64
-+//Revisit
-+#define MAX_BITS_PER_WORD	64
-+#define UNITS_PER_WORD          (TARGET_MB_64 ? 8 : 4)
-+//#define MIN_UNITS_PER_WORD      (TARGET_MB_64 ? 8 : 4)
-+//#define UNITS_PER_WORD          4
- #define MIN_UNITS_PER_WORD      4
- #define INT_TYPE_SIZE           32
- #define SHORT_TYPE_SIZE         16
--#define LONG_TYPE_SIZE          64
-+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
- #define LONG_LONG_TYPE_SIZE     64
- #define FLOAT_TYPE_SIZE         32
- #define DOUBLE_TYPE_SIZE        64
- #define LONG_DOUBLE_TYPE_SIZE   64
--#define POINTER_SIZE            32
--#define PARM_BOUNDARY           32
--#define FUNCTION_BOUNDARY       32
--#define EMPTY_FIELD_BOUNDARY    32
-+#define POINTER_SIZE            (TARGET_MB_64 ? 64 : 32)
-+//#define WIDEST_HARDWARE_FP_SIZE 64
-+//#define POINTERS_EXTEND_UNSIGNED 1
-+#define PARM_BOUNDARY           (TARGET_MB_64 ? 64 : 32)
-+#define FUNCTION_BOUNDARY       (TARGET_MB_64 ? 64 : 32)
-+#define EMPTY_FIELD_BOUNDARY    (TARGET_MB_64 ? 64 : 32)
- #define STRUCTURE_SIZE_BOUNDARY 8
--#define BIGGEST_ALIGNMENT       32
-+#define BIGGEST_ALIGNMENT       (TARGET_MB_64 ? 64 : 32) 
- #define STRICT_ALIGNMENT        1
- #define PCC_BITFIELD_TYPE_MATTERS 1
- 
-+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
- #undef SIZE_TYPE
--#define SIZE_TYPE "unsigned int"
-+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
- 
- #undef PTRDIFF_TYPE
--#define PTRDIFF_TYPE "int"
-+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
-+
-+/*#undef INTPTR_TYPE
-+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
-+#undef UINTPTR_TYPE
-+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
- 
- #define DATA_ALIGNMENT(TYPE, ALIGN)					\
-   ((((ALIGN) < BITS_PER_WORD)						\
-@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
- #define WORD_REGISTER_OPERATIONS 1
- 
- #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
--
-+/*
- #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
-   if (GET_MODE_CLASS (MODE) == MODE_INT		\
--      && GET_MODE_SIZE (MODE) < 4)		\
--    (MODE) = SImode;
--
-+      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
-+    (MODE) = TARGET_MB_64 ? DImode : SImode;
-+*/
- /* Standard register usage.  */
- 
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
- #define FIRST_PARM_OFFSET(FNDECL)		(UNITS_PER_WORD)
- 
- #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
-+#define DWARF_CIE_DATA_ALIGNMENT -1
- 
- #define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
- 
- #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
- 
--#define STACK_BOUNDARY				32
-+#define STACK_BOUNDARY				(TARGET_MB_64 ? 64 : 32)
- 
-+#define PREFERRED_STACK_BOUNDARY		(TARGET_MB_64 ? 64 : 32)
-+ 
- #define NUM_OF_ARGS				6
- 
- #define GP_RETURN				(GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
-@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
- #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
- 
- #define LIBCALL_VALUE(MODE)						\
-+  gen_rtx_REG (MODE,GP_RETURN)
-+								
-+/*#define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (								\
- 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
- 	     || GET_MODE_SIZE (MODE) >= 4)				\
- 	    ? (MODE)							\
- 	    : SImode), GP_RETURN)
--
-+*/
- /* 1 if N is a possible register number for a function value.
-    On the MicroBlaze, R2 R3 are the only register thus used.
-    Currently, R2 are only implemented  here (C has no complex type)  */
-@@ -500,7 +518,7 @@ typedef struct microblaze_args
- /* 4 insns + 2 words of data.  */
- #define TRAMPOLINE_SIZE				(6 * 4)
- 
--#define TRAMPOLINE_ALIGNMENT			32
-+#define TRAMPOLINE_ALIGNMENT			64
- 
- #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
- 
-@@ -533,13 +551,13 @@ typedef struct microblaze_args
-    addresses which require two reload registers.  */
- #define LEGITIMATE_PIC_OPERAND_P(X)  microblaze_legitimate_pic_operand (X)
- 
--#define CASE_VECTOR_MODE			(SImode)
-+#define CASE_VECTOR_MODE			(TARGET_MB_64? DImode:SImode)
- 
- #ifndef DEFAULT_SIGNED_CHAR
- #define DEFAULT_SIGNED_CHAR			1
- #endif
- 
--#define MOVE_MAX				4
-+#define MOVE_MAX				(TARGET_MB_64 ? 8 : 4)
- #define MAX_MOVE_MAX				8
- 
- #define SLOW_BYTE_ACCESS			1
-@@ -549,7 +567,7 @@ typedef struct microblaze_args
- 
- #define SHIFT_COUNT_TRUNCATED			1
- 
--#define Pmode SImode
-+#define Pmode (TARGET_MB_64? DImode:SImode)
- 
- #define FUNCTION_MODE   SImode
- 
-@@ -711,6 +729,7 @@ do {									\
- 
- #undef TARGET_ASM_OUTPUT_IDENT
- #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
-+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
- 
- /* Default to -G 8 */
- #ifndef MICROBLAZE_DEFAULT_GVALUE
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 0cd0441..0f41ac6 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -26,6 +26,7 @@
- ;; Constants
- ;;----------------------------------------------------
- (define_constants [
-+  (R_Z         0)       ;; For reg r0
-   (R_SP        1)       ;; Stack pointer reg
-   (R_SR       15)       ;; Sub-routine return addr reg
-   (R_IR       14)       ;; Interrupt return addr reg
-@@ -539,6 +540,7 @@
- 
- ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
- ;; Leave carry as is
-+
- (define_insn "addsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
-@@ -560,23 +562,38 @@
- 
- ;; Adding 2 DI operands in register or reg/imm
- 
--(define_insn "adddi3_long"
-+(define_expand "adddi3"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(plus:DI (match_operand:DI 1 "register_operand" "")
-+		 (match_operand:DI 2 "arith_plus_operand" "")))]
-+""
-+{
-+  if (TARGET_MB_64) 
-+   {
-+     if (GET_CODE (operands[2]) == CONST_INT &&
-+       INTVAL(operands[2]) < (long)-549755813888 &&
-+	INTVAL(operands[2]) > (long)549755813887)
-+      FAIL;
-+   }
-+})
-+
-+(define_insn "*adddi3_long"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
-+	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
- 		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
-   "TARGET_MB_64"
-   "@
--   addlk\t%0,%z1,%2
--   addlik\t%0,%z1,%2"
--  [(set_attr "type"	"arith,arith")
--  (set_attr "mode"	"DI,DI")
-+   addlk\t%0,%1,%2
-+   addlik\t%0,%1,%2 #N10"
-+  [(set_attr "type"	"darith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-   (set_attr "length"	"4,4")])
- 
--(define_insn "adddi3"
-+(define_insn "*adddi3_all"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
- 		 (match_operand:DI 2 "arith_operand" "d,i")))]
--  ""
-+  "!TARGET_MB_64"
-   "@
-   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
-   addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
-@@ -603,7 +620,7 @@
- (define_insn "iprefetch"
-   [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
-    (clobber (mem:BLK (scratch)))]
--   "TARGET_PREFETCH"
-+   "TARGET_PREFETCH && !TARGET_MB_64"
-   {
-     operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-     return "mfs\t%2,rpc\n\twic\t%2,r0";
-@@ -616,23 +633,33 @@
- ;; Double Precision Subtraction
- ;;----------------------------------------------------------------
- 
--(define_insn "subdi3_long"
--  [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
--		  (match_operand:DI 2 "register_operand" "d,n")))]
-+(define_expand "subdi3"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(minus:DI (match_operand:DI 1 "register_operand" "")
-+		  (match_operand:DI 2 "arith_operand" "")))]
-+""
-+"
-+{
-+}")
-+
-+(define_insn "subsidi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
-+		  (match_operand:DI 2 "arith_operand" "d,K,n")))]
-   "TARGET_MB_64"
-   "@
-    rsubl\t%0,%2,%1
--   addlik\t%0,%z1,-%2"
--  [(set_attr "type"	"darith")
--  (set_attr "mode"	"DI,DI")
--  (set_attr "length"	"4,4")])
-+   addik\t%0,%z1,-%2
-+   addik\t%0,%z1,-%2"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,4,4")])
- 
--(define_insn "subdi3"
-+(define_insn "subdi3_small"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
- 		  (match_operand:DI 2 "register_operand" "d")))]
--  ""
-+  "!TARGET_MB_64"
-   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
-   [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-@@ -661,7 +688,7 @@
-         (mult:DI
-          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -672,7 +699,7 @@
-         (mult:DI
-          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -683,7 +710,7 @@
-         (mult:DI
-          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -787,7 +814,7 @@
-                         (match_operand:SI 4 "arith_operand")])
-                       (label_ref (match_operand 5))
-                       (pc)))]
--   "TARGET_HARD_FLOAT"
-+   "TARGET_HARD_FLOAT && !TARGET_MB_64"
-    [(set (match_dup 1) (match_dup 3))]
- 
-   {
-@@ -817,6 +844,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "negsi_long"
-+  [(set (match_operand:SI 0 "register_operand" "=d")
-+	(neg:SI (match_operand:DI 1 "register_operand" "d")))]
-+  ""
-+  "rsubk\t%0,%1,r0"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"SI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "negdi2_long"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -845,16 +881,24 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--(define_insn "one_cmpldi2_long"
-+(define_expand "one_cmpldi2"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(not:DI (match_operand:DI 1 "register_operand" "")))]
-+  ""
-+  "
-+{
-+}")
-+
-+(define_insn ""
-   [(set (match_operand:DI 0 "register_operand" "=d")
--	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-+	(not:DI (match_operand:DI 1 "arith_operand" "d")))]
-   "TARGET_MB_64"
-   "xorli\t%0,%1,-1"
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
- 
--(define_insn "*one_cmpldi2"
-+(define_insn ""
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-   ""
-@@ -869,7 +913,8 @@
- 	(not:DI (match_operand:DI 1 "register_operand" "")))]
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
--   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-+   && !TARGET_MB_64"
- 
-   [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
-   (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
-@@ -881,18 +926,17 @@
- ;;----------------------------------------------------------------
- 
- (define_insn "anddi3"
--  [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
--		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K,I")))]
-   "TARGET_MB_64"
-   "@
-    andl\t%0,%1,%2
--   andli\t%0,%1,%2 #andl1"
--  ;; andli\t%0,%1,%2 #andl3
--  ;; andli\t%0,%1,%2 #andl2
--  [(set_attr "type"	"arith,arith")
--  (set_attr "mode"	"DI,DI")
--  (set_attr "length"	"4,4")])
-+   andli\t%0,%1,%2 #andl2
-+   andli\t%0,%1,%2 #andl3"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI,DI,DI")
-+  (set_attr "length"	"4,4,4")])
- 
- (define_insn "andsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-@@ -917,7 +961,7 @@
-   "@
-    orl\t%0,%1,%2
-    orli\t%0,%1,%2 #andl1"
--  [(set_attr "type"	"arith,arith")
-+  [(set_attr "type"	"arith,no_delay_arith")
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")])
- 
-@@ -943,7 +987,7 @@
-   "@
-    xorl\t%0,%1,%2
-    xorli\t%0,%1,%2 #andl1"
--  [(set_attr "type"	"arith,arith")
-+  [(set_attr "type"	"arith,no_delay_arith")
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")])
- 
-@@ -1016,26 +1060,6 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--;;(define_expand "extendqidi2"
--;;  [(set (match_operand:DI 0 "register_operand" "=d")
--;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
--;;  "TARGET_MB_64"
--;;  {
--;;	if (GET_CODE (operands[1]) != REG)
--;;	FAIL;
--;;   }
--;;)
--    
--
--;;(define_insn "extendqidi2"
--;;  [(set (match_operand:DI 0 "register_operand" "=d")
--;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
--;;  "TARGET_MB_64"
--;;  "sextl8\t%0,%1"
--;;  [(set_attr "type"	"arith")
--;;  (set_attr "mode"	"DI")
--;;  (set_attr "length"	"4")])
--
- (define_insn "extendhisi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -1058,6 +1082,27 @@
- ;; Those for integer source operand are ordered
- ;; widest source type first.
- 
-+(define_insn "extendsidi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-+  "TARGET_MB_64"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "sextl32\t%0,%1";
-+      case 1:
-+      case 2:
-+        {
-+          output_asm_insn ("ll%i1\t%0,%1", operands);
-+          return "sextl32\t%0,%0";
-+        }
-+    } 
-+  }
-+  [(set_attr "type"	"multi,multi,multi")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,8,8")])
-+
- (define_insn "extendsidi2"
-   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-@@ -1088,68 +1133,117 @@
- ;; Unlike most other insns, the move insns can't be split with
- ;; different predicates, because register spilling and other parts of
- ;; the compiler, have memoized the insn number already.
-+;;    //}
- 
- (define_expand "movdi"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "")
- 	(match_operand:DI 1 "general_operand" ""))]
-   ""
-   {
--    /* If operands[1] is a constant address illegal for pic, then we need to
--       handle it just like microblaze_legitimize_address does.  */
--    if (flag_pic && pic_address_needs_scratch (operands[1]))
-+    if (TARGET_MB_64)
-+    {
-+      if (microblaze_expand_move (DImode, operands)) DONE;
-+    }
-+    else
-     {
-+      /* If operands[1] is a constant address illegal for pic, then we need to
-+         handle it just like microblaze_legitimize_address does. */ 
-+      if (flag_pic && pic_address_needs_scratch (operands[1]))
-+      {
-         rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
-         rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-         emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
-         DONE;
--    }
--
--
--    if ((reload_in_progress | reload_completed) == 0
--        && !register_operand (operands[0], DImode)
--        && !register_operand (operands[1], DImode)
--        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
--	       && operands[1] != CONST0_RTX (DImode))))
--    {
-+      }
- 
--      rtx temp = force_reg (DImode, operands[1]);
--      emit_move_insn (operands[0], temp);
--      DONE;
-+      if ((reload_in_progress | reload_completed) == 0
-+          && !register_operand (operands[0], DImode)
-+          && !register_operand (operands[1], DImode)
-+          && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-+  	       && operands[1] != CONST0_RTX (DImode))))
-+      {
-+        rtx temp = force_reg (DImode, operands[1]);
-+        emit_move_insn (operands[0], temp);
-+        DONE;
-+      }
-     }
-   }
- )
- 
-+;; Added for status registers
-+(define_insn "movdi_status"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,z")
-+        (match_operand:DI 1 "register_operand" "z,d,d"))]
-+  "microblaze_is_interrupt_variant () && TARGET_MB_64"
-+  "@
-+	mfs\t%0,%1  #mfs
-+	addlk\t%0,%1,r0 #add movdi
-+	mts\t%0,%1  #mts"	
-+  [(set_attr "type" "move")
-+  (set_attr "mode" "DI")
-+  (set_attr "length" "12")])
- 
--(define_insn "*movdi_internal_64"
--  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
--	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
--  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
-+;; This move will be not be moved to delay slot.	
-+(define_insn "*movdi_internal3"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
-+	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
-+  "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
-+           (GET_CODE (operands[1]) == CONST_INT && 
-+                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
-+  "@
-+   addlk\t%0,r0,r0\t
-+   addlik\t%0,r0,%1\t #N1 %X1
-+   addlik\t%0,r0,%1\t #N2 %X1"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+;; This move may be used for PLT label operand
-+(define_insn "*movdi_internal5_pltop"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(match_operand:DI 1 "call_insn_operand" ""))]
-+  "TARGET_MB_64 && (register_operand (operands[0], Pmode) && 
-+           PLT_ADDR_P (operands[1]))"
-+  { 
-+     gcc_unreachable ();
-+  }
-+  [(set_attr "type"	"load")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+(define_insn "*movdi_internal2"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
-+	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-+  "TARGET_MB_64"
-   { 
-     switch (which_alternative)
-     {
-       case 0:
--        return "addlk\t%0,%1";
--      case 1:
--	return "addlik\t%0,r0,%1";
--      case 2:
--	  return "addlk\t%0,r0,r0";
--      case 3:
--      case 4:
--	  return "lli\t%0,%1";
--      case 5:
--      case 6:
--        return "sli\t%1,%0";
--    }
--    return "unreachable";
--  }
--  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+        return "addlk\t%0,%1,r0";
-+     case 1:
-+     case 2:
-+        if (GET_CODE (operands[1]) == CONST_INT && 
-+	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
-+ 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+        else	
-+	  return "addlik\t%0,r0,%1";
-+     case 3:
-+     case 4:
-+       return "ll%i1\t%0,%1";
-+     case 5:
-+     case 6:
-+       return "sl%i0\t%z1,%0";
-+     }
-+   }
-+  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-   (set_attr "mode"	"DI")
--  (set_attr "length"   "8,8,8,8,12,8,12")])
-+  (set_attr "length"	"4,4,12,4,8,4,8")])
-+
- 
- (define_insn "*movdi_internal"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
- 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
--  ""
-+  "!TARGET_MB_64"
-   { 
-     switch (which_alternative)
-     {
-@@ -1181,7 +1275,8 @@
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
--   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
-+   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
-+   && !(TARGET_MB_64)"
- 
-   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
-   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-@@ -1193,12 +1288,22 @@
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
--   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
-+   && !(TARGET_MB_64)"
- 
-   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
-   "")
- 
-+(define_insn "movdi_long_int"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
-+	(match_operand:DI 1 "general_operand"      "i"))]
-+  ""
-+  "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+  [(set_attr "type"	"no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"12")])
-+
- ;; Unlike most other insns, the move insns can't be split with
- ;; different predicates, because register spilling and other parts of
- ;; the compiler, have memoized the insn number already.
-@@ -1270,6 +1375,8 @@
-   (set_attr "length"	"4,4,8,4,8,4,8")])
- 
- 
-+
-+
- ;; 16-bit Integer moves
- 
- ;; Unlike most other insns, the move insns can't be split with
-@@ -1302,8 +1409,8 @@
-   "@
-    addik\t%0,r0,%1\t# %X1
-    addk\t%0,%1,r0
--   lhui\t%0,%1
--   lhui\t%0,%1
-+   lhu%i1\t%0,%1
-+   lhu%i1\t%0,%1
-    sh%i0\t%z1,%0
-    sh%i0\t%z1,%0"
-   [(set_attr "type"	"arith,move,load,no_delay_load,store,no_delay_store")
-@@ -1346,7 +1453,7 @@
-    lbu%i1\t%0,%1
-    lbu%i1\t%0,%1
-    sb%i0\t%z1,%0
--   sbi\t%z1,%0"
-+   sb%i0\t%z1,%0"
-   [(set_attr "type"	"arith,arith,move,load,no_delay_load,store,no_delay_store")
-   (set_attr "mode"	"QI")
-   (set_attr "length"	"4,4,8,4,8,4,8")])
-@@ -1419,7 +1526,7 @@
-    addik\t%0,r0,%F1
-    lw%i1\t%0,%1
-    sw%i0\t%z1,%0
--   swi\t%z1,%0"
-+   sw%i0\t%z1,%0"
-   [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4,4,4,4,4,4,4")])
-@@ -1458,6 +1565,33 @@
- ;; movdf_internal
- ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
- ;;
-+(define_insn "*movdf_internal_64"
-+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-+        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-+  "TARGET_MB_64"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+	return "addlk\t%0,%1,r0";
-+      case 1:
-+	return "addlk\t%0,r0,r0";
-+      case 2:
-+      case 4:
-+          return "ll%i1\t%0,%1";
-+      case 3:
-+      {
-+	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
-+      }
-+      case 5:
-+	return "sl%i0\t%1,%0";
-+    }
-+    gcc_unreachable ();
-+  }
-+  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4,4,4,16,4,4")])
-+
- (define_insn "*movdf_internal"
-   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
-         (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
-@@ -1492,7 +1626,8 @@
-   "reload_completed
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
--   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
-+   && !TARGET_MB_64"
-   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
-   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-   "")
-@@ -1503,7 +1638,8 @@
-   "reload_completed
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
--   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
-+   && !TARGET_MB_64"
-   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
-   "")
-@@ -2003,6 +2139,31 @@ else
-   "
- )
- 
-+
-+(define_insn "seq_internal_pat_long" 
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(eq:DI 
-+	       (match_operand:DI 1 "register_operand" "d")
-+	       (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "pcmpleq\t%0,%1,%2"
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"DI")
-+   (set_attr "length"	"4")]
-+)              
-+
-+(define_insn "sne_internal_pat_long" 
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(ne:DI 
-+	       (match_operand:DI 1 "register_operand" "d")
-+	       (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "pcmplne\t%0,%1,%2"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")]
-+)              
-+
- (define_insn "seq_internal_pat" 
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(eq:SI 
-@@ -2063,8 +2224,8 @@ else
- (define_expand "cbranchsi4"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand:SI 1 "register_operand")
--                        (match_operand:SI 2 "arith_operand" "I,i")])
-+                       [(match_operand 1 "register_operand")
-+                        (match_operand 2 "arith_operand" "I,i")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
-@@ -2076,13 +2237,13 @@ else
- (define_expand "cbranchsi4_reg"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand:SI 1 "register_operand")
--                        (match_operand:SI 2 "register_operand")])
-+                       [(match_operand 1 "register_operand")
-+                        (match_operand 2 "register_operand")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
- {
--  microblaze_expand_conditional_branch_reg (SImode, operands);
-+  microblaze_expand_conditional_branch_reg (Pmode, operands);
-   DONE;
- })
- 
-@@ -2107,6 +2268,26 @@ else
- 		      (label_ref (match_operand 1))
- 		      (pc)))])
- 
-+(define_insn "branch_zero64"
-+  [(set (pc)
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-+  				 [(match_operand 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand 2 "pc_or_label_operand" "")
-+                      (match_operand 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "bea%C0i%?\t%z1,%2";
-+    else 
-+      return "bea%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
- (define_insn "branch_zero"
-   [(set (pc)
- 	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-@@ -2127,6 +2308,47 @@ else
-    (set_attr "length"	"4")]
- )
- 
-+(define_insn "branch_compare64"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "cmp_op"
-+                                         [(match_operand 1 "register_operand" "d")
-+                                          (match_operand 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:SI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmp\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmp\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
-+    return "bea%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- (define_insn "branch_compare"
-   [(set (pc)
-         (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2310,7 +2532,7 @@ else
- ;; Indirect jumps. Jump to register values. Assuming absolute jumps
- 
- (define_insn "indirect_jump_internal1"
--  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
-+  [(set (pc) (match_operand 0 "register_operand" "d"))]
-   ""
-   "bra%?\t%0"
-   [(set_attr "type"	"jump")
-@@ -2323,7 +2545,7 @@ else
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   {
--    gcc_assert (GET_MODE (operands[0]) == Pmode);
-+    //gcc_assert (GET_MODE (operands[0]) == Pmode);
- 
-     if (!flag_pic)
-       emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-@@ -2335,7 +2557,7 @@ else
- 
- (define_insn "tablejump_internal1"
-   [(set (pc)
--	(match_operand:SI 0 "register_operand" "d"))
-+	(match_operand 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   "bra%?\t%0 "
-@@ -2345,9 +2567,9 @@ else
- 
- (define_expand "tablejump_internal3"
-   [(parallel [(set (pc)
--		   (plus:SI (match_operand:SI 0 "register_operand" "d")
--			    (label_ref:SI (match_operand:SI 1 "" ""))))
--             (use (label_ref:SI (match_dup 1)))])]
-+		   (plus (match_operand 0 "register_operand" "d")
-+			    (label_ref (match_operand:SI 1 "" ""))))
-+             (use (label_ref (match_dup 1)))])]
-   ""
-   ""
- )
-@@ -2408,7 +2630,7 @@ else
- 	(minus (reg 1) (match_operand 1 "register_operand" "")))
-    (set (reg 1)
- 	(minus (reg 1) (match_dup 1)))]
--  ""
-+  "!TARGET_MB_64"
-   { 
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
-     rtx reg = gen_reg_rtx (Pmode);
-@@ -2433,7 +2655,7 @@ else
- (define_expand "save_stack_block"
-   [(match_operand 0 "register_operand" "")
-    (match_operand 1 "register_operand" "")]
--  ""
-+  "!TARGET_MB_64"
-   {
-     emit_move_insn (operands[0], operands[1]);
-     DONE;
-@@ -2443,7 +2665,7 @@ else
- (define_expand "restore_stack_block"
-   [(match_operand 0 "register_operand" "")
-    (match_operand 1 "register_operand" "")]
--  ""
-+  "!TARGET_MB_64"
-   {
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
-     rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-@@ -2490,7 +2712,7 @@ else
- 
- (define_insn "<optab>_internal"
-   [(any_return)
--   (use (match_operand:SI 0 "register_operand" ""))]
-+   (use (match_operand 0 "register_operand" ""))]
-   ""
-   {
-     if (microblaze_is_break_handler ())
-@@ -2523,7 +2745,7 @@ else
- (define_expand "call"
-   [(parallel [(call (match_operand 0 "memory_operand" "m")
- 		    (match_operand 1 "" "i"))
--             (clobber (reg:SI R_SR))
-+             (clobber (reg R_SR))
-              (use (match_operand 2 "" ""))
-              (use (match_operand 3 "" ""))])]
-   ""
-@@ -2543,12 +2765,12 @@ else
- 
-     if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
-       emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
-                                	     pic_offset_table_rtx));
-     else
-       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- 
-         DONE;
-@@ -2558,7 +2780,7 @@ else
- (define_expand "call_internal0"
-   [(parallel [(call (match_operand 0 "" "")
- 		    (match_operand 1 "" ""))
--             (clobber (match_operand:SI 2 "" ""))])]
-+             (clobber (match_operand 2 "" ""))])]
-   ""
-   {
-   }
-@@ -2567,18 +2789,34 @@ else
- (define_expand "call_internal_plt0"
-   [(parallel [(call (match_operand 0 "" "")
- 		    (match_operand 1 "" ""))
--             (clobber (match_operand:SI 2 "" ""))
--             (use (match_operand:SI 3 "" ""))])]
-+             (clobber (match_operand 2 "" ""))
-+             (use (match_operand 3 "" ""))])]
-   ""
-   {
-   }
- )
-  
-+(define_insn "call_internal_plt_64"
-+  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))
-+  (use (reg R_GOT))]
-+  "flag_pic && TARGET_MB_64"
-+  {
-+    register rtx target2 = gen_rtx_REG (Pmode, 
-+			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+    gen_rtx_CLOBBER (VOIDmode, target2);
-+    return "brealid\tr15,%0\;%#";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_internal_plt"
--  [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
--	 (match_operand:SI 1 "" "i"))
--  (clobber (reg:SI R_SR))
--  (use (reg:SI R_GOT))]
-+  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))
-+  (use (reg R_GOT))]
-   "flag_pic"
-   {
-     register rtx target2 = gen_rtx_REG (Pmode, 
-@@ -2590,10 +2828,41 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "call_internal1_64"
-+  [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))]
-+  "TARGET_MB_64"
-+  {
-+    register rtx target = operands[0];
-+    register rtx target2 = gen_rtx_REG (Pmode,
-+			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+    if (GET_CODE (target) == SYMBOL_REF) {
-+        if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
-+            gen_rtx_CLOBBER (VOIDmode, target2);
-+            return "breaki\tr16,%0\;%#";
-+        }
-+        else {
-+            gen_rtx_CLOBBER (VOIDmode, target2);
-+            return "brealid\tr15,%0\;%#";
-+        }
-+    } else if (GET_CODE (target) == CONST_INT)
-+        return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
-+    else if (GET_CODE (target) == REG)
-+        return "brald\tr15,%0\;%#";	
-+    else {
-+        fprintf (stderr,"Unsupported call insn\n");
-+        return NULL;
-+    }
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_internal1"
-   [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
--	 (match_operand:SI 1 "" "i"))
--  (clobber (reg:SI R_SR))]
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))]
-   ""
-   {
-     register rtx target = operands[0];
-@@ -2627,7 +2896,7 @@ else
-   [(parallel [(set (match_operand 0 "register_operand" "=d")
- 		   (call (match_operand 1 "memory_operand" "m")
- 			 (match_operand 2 "" "i")))
--             (clobber (reg:SI R_SR))
-+             (clobber (reg R_SR))
-              (use (match_operand 3 "" ""))])] ;; next_arg_reg
-   ""
-   {
-@@ -2647,13 +2916,13 @@ else
-     if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
-       emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
- 			operands[2],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
- 				     pic_offset_table_rtx));
-     else
-       emit_call_insn (gen_call_value_internal (operands[0], operands[1], 
- 			operands[2],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- 
-     DONE;
-@@ -2665,7 +2934,7 @@ else
-   [(parallel [(set (match_operand 0 "" "")
- 		   (call (match_operand 1 "" "")
- 			 (match_operand 2 "" "")))
--             (clobber (match_operand:SI 3 "" ""))
-+             (clobber (match_operand 3 "" ""))
-              ])]
-   ""
-   {}
-@@ -2675,18 +2944,35 @@ else
-   [(parallel[(set (match_operand 0 "" "")
-                   (call (match_operand 1 "" "")
-                         (match_operand 2 "" "")))
--             (clobber (match_operand:SI 3 "" ""))
--             (use (match_operand:SI 4 "" ""))])]
-+             (clobber (match_operand 3 "" ""))
-+             (use (match_operand 4 "" ""))])]
-   "flag_pic"
-   {}
- )
- 
-+(define_insn "call_value_intern_plt_64"
-+  [(set (match_operand:VOID 0 "register_operand" "=d")
-+        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))
-+   (use (match_operand 4 "register_operand"))]
-+  "flag_pic && TARGET_MB_64"
-+  { 
-+    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+
-+    gen_rtx_CLOBBER (VOIDmode,target2);
-+    return "brealid\tr15,%1\;%#";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_value_intern_plt"
-   [(set (match_operand:VOID 0 "register_operand" "=d")
--        (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
--              (match_operand:SI 2 "" "i")))
--   (clobber (match_operand:SI 3 "register_operand" "=d"))
--   (use (match_operand:SI 4 "register_operand"))]
-+        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))
-+   (use (match_operand 4 "register_operand"))]
-   "flag_pic"
-   { 
-     register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-@@ -2698,11 +2984,46 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "call_value_intern_64"
-+  [(set (match_operand:VOID 0 "register_operand" "=d")
-+        (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))]
-+  "TARGET_MB_64"
-+  { 
-+    register rtx target = operands[1];
-+    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+
-+    if (GET_CODE (target) == SYMBOL_REF)
-+    {
-+      gen_rtx_CLOBBER (VOIDmode,target2);
-+      if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
-+        return "breaki\tr16,%1\;%#";
-+      else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
-+        {
-+	  return "brealid\tr15,%1\;%#";
-+        }
-+      else
-+        {
-+	    return "bralid\tr15,%1\;%#";
-+        }
-+    }
-+    else if (GET_CODE (target) == CONST_INT)
-+        return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
-+    else if (GET_CODE (target) == REG)
-+        return "brald\tr15,%1\;%#";	
-+    else 
-+        return "Unsupported call insn\n";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_value_intern"
-   [(set (match_operand:VOID 0 "register_operand" "=d")
-         (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
--              (match_operand:SI 2 "" "i")))
--   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))]
-   ""
-   { 
-     register rtx target = operands[1];
-@@ -2864,7 +3185,6 @@ else
- 
-   ;;if (!register_operand (operands[0], VOIDmode))
-   ;;  FAIL;
--
-   emit_insn (gen_insv_32 (operands[0], operands[1],
- 			  operands[2], operands[3]));
-   DONE;
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 7671f63..9fc80b1 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
- MULTILIB_DIRNAMES = bs m mh le m64
- MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
- MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
-diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 2e15be4..3386520 100644
---- a/libgcc/config/microblaze/crti.S
-+++ b/libgcc/config/microblaze/crti.S
-@@ -40,7 +40,7 @@
- 
-     .align 2
- __init: 
--    addik   r1, r1, -8
-+    addik   r1, r1, -16
-     sw      r15, r0, r1
-     la      r11, r0, _stack
-     mts     rshr, r11
-@@ -51,5 +51,5 @@ __init:
-     .global __fini
-     .align 2
- __fini: 
--    addik   r1, r1, -8
-+    addik   r1, r1, -16
-     sw      r15, r0, r1
-diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index cd5fd9e..04e73d7 100644
---- a/libgcc/config/microblaze/crtn.S
-+++ b/libgcc/config/microblaze/crtn.S
-@@ -33,9 +33,9 @@
-     .section .init, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
--    addik   r1, r1, 8
-+    addik   r1, r1, 16
- 
-     .section .fini, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
--    addik   r1, r1, 8    
-+    addik   r1, r1, 16   
-diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
-new file mode 100644
-index 0000000..d37bf51
---- /dev/null
-+++ b/libgcc/config/microblaze/divdi3.S
-@@ -0,0 +1,98 @@
-+###################################-
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+#
-+#  divdi3.S
-+# 
-+#  Divide operation for 32 bit integers.
-+#	Input :	Dividend in Reg r5
-+#		Divisor in Reg r6
-+#	Output: Result in Reg r3
-+# 
-+#######################################
-+
-+#ifdef __arch64__	
-+	.globl	__divdi3
-+	.ent	__divdi3
-+	.type	__divdi3,@function
-+__divdi3:
-+	.frame	r1,0,r15	
-+
-+	ADDLIK   r1,r1,-32
-+	SLI     r28,r1,0
-+	SLI     r29,r1,8
-+	SLI     r30,r1,16
-+	SLI     r31,r1,24
-+
-+	BEALEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEALEQI    r5,$LaResult_Is_Zero    # Result is Zero 
-+	XORL     r28,r5,r6               # Get the sign of the result
-+	BEALGEI   r5,$LaR5_Pos 
-+	RSUBLI   r5,r5,0                 # Make r5 positive
-+$LaR5_Pos:
-+	BEALGEI    r6,$LaR6_Pos
-+	RSUBLI   r6,r6,0                 # Make r6 positive
-+$LaR6_Pos:
-+	ADDLIK   r30,r0,0                # Clear mod
-+	ADDLIK   r3,r0,0                 # clear div
-+	ADDLIK   r29,r0,64               # Initialize the loop count
-+
-+        # First part try to find the first '1' in the r5
-+$LaDIV0: 
-+        BEALLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
-+$LaDIV1:
-+	ADDL     r5,r5,r5                # left shift logical r5
-+	ADDLIK   r29,r29,-1
-+	BEALGTI   r5,$LaDIV1       
-+$LaDIV2:
-+	ADDL     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
-+	ADDLC    r30,r30,r30             # Move that bit into the Mod register
-+	RSUBL    r31,r6,r30              # Try to subtract (r30 a r6)
-+	BEALLTI    r31,$LaMOD_TOO_SMALL
-+	ORL      r30,r0,r31              # Move the r31 to mod since the result was positive
-+	ADDLIK   r3,r3,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK   r29,r29,-1
-+	BEALEQi    r29,$LaLOOP_END
-+	ADDL     r3,r3,r3                # Shift in the '1' into div
-+	BREAI     $LaDIV2                 # Div2
-+$LaLOOP_END:
-+	BEALGEI    r28,$LaRETURN_HERE
-+	RSUBLI   r3,r3,0                 # Negate the result
-+	BREAI    $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	ORL      r3,r0,r0 # set result to 0
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r28,r1,0
-+	LLI     r29,r1,8
-+	LLI     r30,r1,16
-+	LLI     r31,r1,24
-+	ADDLIK   r1,r1,32
-+	RTSD    r15,8
-+        nop
-+.end __divdi3
-+	.size	__divdi3, . - __divdi3
-+#endif
-diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
-new file mode 100644
-index 0000000..8096259
---- /dev/null
-+++ b/libgcc/config/microblaze/divdi3_table.c
-@@ -0,0 +1,62 @@
-+/*  Table for software lookup divide for Xilinx MicroBlaze.
-+ 
-+   Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+
-+   Contributed by Michael Eager <eager@eagercon.com>.
-+
-+   This file is free software; you can redistribute it and/or modify it
-+   under the terms of the GNU General Public License as published by the
-+   Free Software Foundation; either version 3, or (at your option) any
-+   later version.
-+
-+   GCC is distributed in the hope that it will be useful, but WITHOUT
-+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+   License for more details.
-+
-+   Under Section 7 of GPL version 3, you are granted additional
-+   permissions described in the GCC Runtime Library Exception, version
-+   3.1, as published by the Free Software Foundation.
-+
-+   You should have received a copy of the GNU General Public License and
-+   a copy of the GCC Runtime Library Exception along with this program;
-+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+   <http://www.gnu.org/licenses/>.  */
-+
-+ 
-+unsigned char _divdi3_table[] =
-+{
-+       0,   0/1,   0/2,   0/3,   0/4,   0/5,   0/6,   0/7, 
-+     0/8,   0/9,  0/10,  0/11,  0/12,  0/13,  0/14,  0/15,
-+       0,   1/1,   1/2,   1/3,   1/4,   1/5,   1/6,   1/7, 
-+     1/8,   1/9,  1/10,  1/11,  1/12,  1/13,  1/14,  1/15,
-+       0,   2/1,   2/2,   2/3,   2/4,   2/5,   2/6,   2/7, 
-+     2/8,   2/9,  2/10,  2/11,  2/12,  2/13,  2/14,  2/15,
-+       0,   3/1,   3/2,   3/3,   3/4,   3/5,   3/6,   3/7, 
-+     3/8,   3/9,  3/10,  3/11,  3/12,  3/13,  3/14,  3/15,
-+       0,   4/1,   4/2,   4/3,   4/4,   4/5,   4/6,   4/7, 
-+     4/8,   4/9,  4/10,  4/11,  4/12,  4/13,  4/14,  4/15,
-+       0,   5/1,   5/2,   5/3,   5/4,   5/5,   5/6,   5/7, 
-+     5/8,   5/9,  5/10,  5/11,  5/12,  5/13,  5/14,  5/15,
-+       0,   6/1,   6/2,   6/3,   6/4,   6/5,   6/6,   6/7, 
-+     6/8,   6/9,  6/10,  6/11,  6/12,  6/13,  6/14,  6/15,
-+       0,   7/1,   7/2,   7/3,   7/4,   7/5,   7/6,   7/7, 
-+     7/8,   7/9,  7/10,  7/11,  7/12,  7/13,  7/14,  7/15,
-+       0,   8/1,   8/2,   8/3,   8/4,   8/5,   8/6,   8/7, 
-+     8/8,   8/9,  8/10,  8/11,  8/12,  8/13,  8/14,  8/15,
-+       0,   9/1,   9/2,   9/3,   9/4,   9/5,   9/6,   9/7, 
-+     9/8,   9/9,  9/10,  9/11,  9/12,  9/13,  9/14,  9/15,
-+       0,  10/1,  10/2,  10/3,  10/4,  10/5,  10/6,  10/7, 
-+    10/8,  10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
-+       0,  11/1,  11/2,  11/3,  11/4,  11/5,  11/6,  11/7, 
-+    11/8,  11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
-+       0,  12/1,  12/2,  12/3,  12/4,  12/5,  12/6,  12/7, 
-+    12/8,  12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
-+       0,  13/1,  13/2,  13/3,  13/4,  13/5,  13/6,  13/7, 
-+    13/8,  13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
-+       0,  14/1,  14/2,  14/3,  14/4,  14/5,  14/6,  14/7, 
-+    14/8,  14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
-+       0,  15/1,  15/2,  15/3,  15/4,  15/5,  15/6,  15/7, 
-+    15/8,  15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
-+};
-+
-diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
-new file mode 100644
-index 0000000..5d3f7c0
---- /dev/null
-+++ b/libgcc/config/microblaze/moddi3.S
-@@ -0,0 +1,97 @@
-+###################################
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  moddi3.S
-+# 
-+#  modulo operation for 32 bit integers.
-+#	Input :	op1 in Reg r5
-+#		op2 in Reg r6
-+#	Output: op1 mod op2 in Reg r3
-+# 
-+#######################################
-+
-+#ifdef __arch64__
-+	.globl	__moddi3
-+	.ent	__moddi3
-+	.type	__moddi3,@function
-+__moddi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-32
-+	sli	r28,r1,0
-+	sli	r29,r1,8
-+	sli	r30,r1,16
-+	sli	r31,r1,32
-+
-+	BEALEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEALEQI	r5,$LaResult_Is_Zero    # Result is Zero 
-+	ADDL	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
-+	BEALGEI	r5,$LaR5_Pos 
-+	RSUBLI	r5,r5,0	                # Make r5 positive
-+$LaR5_Pos:
-+	BEALGEI	r6,$LaR6_Pos
-+	RSUBLI	r6,r6,0	    # Make r6 positive
-+$LaR6_Pos:
-+	ADDLIK	r3,r0,0      # Clear mod
-+	ADDLIK	r30,r0,0     # clear div
-+	ADDLIK	r29,r0,64    # Initialize the loop count
-+	BEALLTI	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+			     # the first bit search.
-+   # First part try to find the first '1' in the r5
-+$LaDIV1:
-+	ADDL	r5,r5,r5         # left shift logical r5
-+	ADDLIK	r29,r29,-1
-+	BEALGEI	r5,$LaDIV1       #
-+$LaDIV2:
-+	ADDL	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
-+	ADDLC	r3,r3,r3         # Move that bit into the Mod register
-+	rSUBL	r31,r6,r3        # Try to subtract (r30 a r6)
-+	BEALLTi	r31,$LaMOD_TOO_SMALL
-+	ORL	r3,r0,r31       # Move the r31 to mod since the result was positive
-+	ADDLIK	r30,r30,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK	r29,r29,-1
-+	BEALEQi	r29,$LaLOOP_END
-+	ADDL	r30,r30,r30         # Shift in the '1' into div
-+	BREAI	$LaDIV2          # Div2
-+$LaLOOP_END:
-+	BEALGEI	r28,$LaRETURN_HERE
-+	rsubli	r3,r3,0 # Negate the result
-+	BREAI	$LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	orl	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli	r28,r1,0
-+	lli	r29,r1,8
-+	lli	r30,r1,16
-+	lli	r31,r1,24
-+	addlik	r1,r1,32
-+	rtsd	r15,8
-+        nop
-+        .end __moddi3
-+	.size	__moddi3, . - __moddi3
-+#endif
-diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
-new file mode 100644
-index 0000000..5677841
---- /dev/null
-+++ b/libgcc/config/microblaze/muldi3.S
-@@ -0,0 +1,73 @@
-+/*###################################-*-asm*- 
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  muldi3.S
-+# 
-+#  Multiply operation for 32 bit integers.
-+#	Input :	Operand1 in Reg r5
-+#		Operand2 in Reg r6
-+#	Output: Result [op1 * op2] in Reg r3
-+# 
-+#######################################*/
-+
-+#ifdef __arch64__
-+	.globl	__muldi3
-+	.ent	__muldi3
-+	.type	__muldi3,@function
-+__muldi3:
-+	.frame	r1,0,r15
-+	addl	r3,r0,r0
-+	BEALEQI	r5,$L_Result_Is_Zero      # Multiply by Zero
-+	BEALEQI	r6,$L_Result_Is_Zero      # Multiply by Zero
-+	XORL	r4,r5,r6                  # Get the sign of the result
-+	BEALGEI	r5,$L_R5_Pos 
-+	RSUBLI	r5,r5,0	                  # Make r5 positive
-+$L_R5_Pos:
-+	BEALGEI	r6,$L_R6_Pos
-+	RSUBLI	r6,r6,0	                  # Make r6 positive
-+$L_R6_Pos:	
-+	breai	$L1
-+$L2:	
-+	addl	r5,r5,r5
-+$L1:	
-+	srll	r6,r6
-+	addlc	r7,r0,r0
-+	bealeqi	r7,$L2
-+	addl	r3,r3,r5	
-+	bealnei	r6,$L2
-+	beallti	r4,$L_NegateResult			
-+	rtsd	r15,8
-+	nop
-+$L_NegateResult:
-+	rsubl	r3,r3,r0
-+	rtsd	r15,8
-+	nop
-+$L_Result_Is_Zero:
-+	addli	r3,r0,0
-+	rtsd	r15,8
-+	nop
-+	.end __muldi3
-+	.size	__muldi3, . - __muldi3
-+#endif
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 8d954a4..35021b2 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,11 +1,16 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
-+			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
-+        $(srcdir)/config/microblaze/divdi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
--        $(srcdir)/config/microblaze/muldi3_hard.S \
-+        $(srcdir)/config/microblaze/moddi3.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
-+        $(srcdir)/config/microblaze/muldi3.S \
-         $(srcdir)/config/microblaze/stack_overflow_exit.S \
-         $(srcdir)/config/microblaze/udivsi3.S \
-+        $(srcdir)/config/microblaze/udivdi3.S \
-         $(srcdir)/config/microblaze/umodsi3.S \
--        $(srcdir)/config/microblaze/divsi3_table.c
-+        $(srcdir)/config/microblaze/umoddi3.S \
-+        $(srcdir)/config/microblaze/divsi3_table.c \
-diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
-new file mode 100644
-index 0000000..c210fbc
---- /dev/null
-+++ b/libgcc/config/microblaze/udivdi3.S
-@@ -0,0 +1,107 @@
-+###################################-
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  udivdi3.S
-+# 
-+#  Unsigned divide operation.
-+#	Input :	Divisor in Reg r5
-+#		Dividend in Reg r6
-+#	Output: Result in Reg r3
-+# 
-+#######################################
-+	
-+#ifdef __arch64__
-+	.globl	__udivdi3
-+	.ent	__udivdi3
-+	.type	__udivdi3,@function
-+__udivdi3:
-+	.frame	r1,0,r15	
-+
-+	ADDlIK   r1,r1,-24
-+    	SLI     r29,r1,0
-+	SLI     r30,r1,8
-+	SLI     r31,r1,16
-+
-+	BEALEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
-+	ADDLIK   r30,r0,0                    # Clear mod
-+	BEALEQI   r5,$LaResult_Is_Zero        # Result is Zero 
-+	ADDLIK   r29,r0,64                   # Initialize the loop count
-+
-+        # Check if r6 and r5 are equal # if yes, return 1
-+	RSUBL 	r18,r5,r6
-+	ADDLIK	r3,r0,1
-+	BEALEQI	r18,$LaRETURN_HERE
-+
-+        # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
-+	XORL	r18,r5,r6
-+	ADDL	r3,r0,r0                    # We would anyways clear r3
-+	BEALGEI	r18,$LRSUBL
-+	BEALLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
-+	BREAI	$LCheckr6
-+$LRSUBL:
-+	RSUBL	r18,r6,r5                   # MICROBLAZEcmp
-+	BEALLTI	r18,$LaRETURN_HERE
-+
-+        # If r6 [bit 31] is set, then return result as 1
-+$LCheckr6:
-+	BEALGTI	r6,$LaDIV0
-+	ADDLIK	r3,r0,1
-+	BREAI	$LaRETURN_HERE
-+
-+        # First part try to find the first '1' in the r5
-+$LaDIV0:
-+	BEALLTI    r5,$LaDIV2	
-+$LaDIV1:
-+	ADDL     r5,r5,r5                    # left shift logical r5
-+	ADDLIK   r29,r29,-1
-+	BEALGTI   r5,$LaDIV1       
-+$LaDIV2:
-+	ADDL     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
-+	ADDLC    r30,r30,r30                 # Move that bit into the Mod register
-+	RSUBL    r31,r6,r30                  # Try to subtract (r30 a r6)
-+    	BEALLTI    r31,$LaMOD_TOO_SMALL
-+	ORL      r30,r0,r31                  # Move the r31 to mod since the result was positive
-+	ADDLIK   r3,r3,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK   r29,r29,-1
-+	BEALEQi    r29,$LaLOOP_END
-+	ADDL     r3,r3,r3 # Shift in the '1' into div
-+	BREAI     $LaDIV2   # Div2
-+$LaLOOP_END:
-+	BREAI     $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	ORL      r3,r0,r0 # set result to 0
-+$LaRETURN_HERE:
-+        # Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r29,r1,0
-+	LLI     r30,r1,8
-+	LLI     r31,r1,16
-+	ADDLIK   r1,r1,24
-+	RTSD    r15,8
-+        NOP
-+        .end __udivdi3
-+	.size	__udivdi3, . - __udivdi3
-+#endif
-diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
-new file mode 100644
-index 0000000..7f5cd23
---- /dev/null
-+++ b/libgcc/config/microblaze/umoddi3.S
-@@ -0,0 +1,110 @@
-+###################################
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  umoddi3.S
-+#
-+#  Unsigned modulo operation for 32 bit integers.
-+#	Input :	op1 in Reg r5
-+#		op2 in Reg r6
-+#	Output: op1 mod op2 in Reg r3
-+# 
-+#######################################
-+	
-+#ifdef __arch64__
-+	.globl	__umoddi3
-+	.ent	__umoddi3
-+	.type	__umoddi3,@function
-+__umoddi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-24
-+	sli	r29,r1,0
-+	sli	r30,r1,8
-+	sli	r31,r1,16
-+
-+	BEALEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
-+	ADDLIK 	r3,r0,0                  # Clear div
-+	BEALEQI	r5,$LaResult_Is_Zero     # Result is Zero 
-+	ADDLIK 	r30,r0,0     	# clear mod
-+	ADDLIK 	r29,r0,64       # Initialize the loop count
-+
-+# Check if r6 and r5 are equal # if yes, return 0
-+	rsubl 	r18,r5,r6
-+	bealeqi	r18,$LaRETURN_HERE
-+
-+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
-+	xorl	r18,r5,r6
-+	addlik	r3,r5,0
-+	bealgei	r18,$LRSUB
-+	beallti	r6,$LaRETURN_HERE
-+	breai	$LCheckr6
-+$LRSUB:
-+	rsubl	r18,r5,r6 # MICROBLAZEcmp
-+	bealgti	r18,$LaRETURN_HERE
-+
-+# If r6 [bit 31] is set, then return result as r5-r6
-+$LCheckr6:
-+	addlik	r3,r0,0
-+	bealgti	r6,$LaDIV0
-+	addlik	r18,r0,0x7fffffff
-+	andl	r5,r5,r18
-+	andl 	r6,r6,r18
-+	breaid	$LaRETURN_HERE
-+	rsubl	r3,r6,r5
-+# First part: try to find the first '1' in the r5
-+$LaDIV0:
-+	BEALLTI	r5,$LaDIV2
-+$LaDIV1:
-+	ADDL 	r5,r5,r5     # left shift logical r5
-+	ADDLIK 	r29,r29,-1
-+	BEALGEI 	r5,$LaDIV1   #
-+$LaDIV2:
-+	ADDL 	r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
-+	ADDLC 	r3,r3,r3     # Move that bit into the Mod register
-+	rSUBL 	r31,r6,r3    # Try to subtract (r3 a r6)
-+	BEALLTi 	r31,$LaMOD_TOO_SMALL
-+	ORL  	r3,r0,r31    # Move the r31 to mod since the result was positive
-+	ADDLIK 	r30,r30,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK 	r29,r29,-1
-+	BEALEQi 	r29,$LaLOOP_END
-+	ADDL 	r30,r30,r30 # Shift in the '1' into div
-+	BREAI 	$LaDIV2     # Div2
-+$LaLOOP_END:
-+	BREAI 	$LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	orl 	r3,r0,r0   # set result to 0
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli 	r29,r1,0
-+	lli 	r30,r1,8
-+	lli 	r31,r1,16
-+	addlik 	r1,r1,24
-+	rtsd 	r15,8
-+        nop
-+.end __umoddi3
-+	.size	__umoddi3, . - __umoddi3
-+#endif
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch
deleted file mode 100644
index c33b247b..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch
+++ /dev/null
@@ -1,268 +0,0 @@
-From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 3 Aug 2018 15:41:39 +0530
-Subject: [PATCH 42/54] re-arrangement of the compare branches
-
----
- gcc/config/microblaze/microblaze.c  |  28 ++-----
- gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++-------------------
- 2 files changed, 73 insertions(+), 96 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index ba7ade4..fab79d9 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == Pmode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
--
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
- 
-   else if (code == EQ || code == NE)
-@@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-       else
-         emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else
-     {
-@@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code),
-                                   mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else if (code == EQ)
-     {
-@@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-                                            cmp_op1));
- 	}
-       condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-  
-     }
-   else if (code == NE)
-@@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-                                            cmp_op1));
- 	}
-       condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else
-     {
-@@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
- 
-   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
-   condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
--  emit_jump_insn (gen_long_condjump (condition, operands[3]));
-+  emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
- /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 0f41ac6..2213d6e 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2268,7 +2268,27 @@ else
- 		      (label_ref (match_operand 1))
- 		      (pc)))])
- 
--(define_insn "branch_zero64"
-+(define_insn "branch_zero_64"
-+  [(set (pc)
-+	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-+  				 [(match_operand:SI 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand:SI 2 "pc_or_label_operand" "")
-+                      (match_operand:SI 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "bea%C0i%?\t%z1,%2";
-+    else 
-+      return "bea%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
-+(define_insn "long_branch_zero"
-   [(set (pc)
- 	(if_then_else (match_operator 0 "ordered_comparison_operator"
-   				 [(match_operand 1 "register_operand" "d")
-@@ -2279,9 +2299,9 @@ else
-   "TARGET_MB_64"
-   {
-     if (operands[3] == pc_rtx) 
--      return "bea%C0i%?\t%z1,%2";
-+      return "beal%C0i%?\t%z1,%2";
-     else 
--      return "bea%N0i%?\t%z1,%3";
-+      return "beal%N0i%?\t%z1,%3";
-   }
-   [(set_attr "type"	"branch")
-    (set_attr "mode"	"none")
-@@ -2310,9 +2330,9 @@ else
- 
- (define_insn "branch_compare64"
-   [(set (pc)
--        (if_then_else (match_operator 0 "cmp_op"
--                                         [(match_operand 1 "register_operand" "d")
--                                          (match_operand 2 "register_operand" "d")
-+        (if_then_else (match_operator:SI 0 "cmp_op"
-+                                         [(match_operand:SI 1 "register_operand" "d")
-+                                          (match_operand:SI 2 "register_operand" "d")
-                                          ])
-                       (label_ref (match_operand 3))
-                       (pc)))
-@@ -2349,6 +2369,47 @@ else
-    (set_attr "length"   "12")]
- )
- 
-+(define_insn "long_branch_compare"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "cmp_op"
-+                                         [(match_operand 1 "register_operand" "d")
-+                                          (match_operand 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:DI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
-+    return "beal%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- (define_insn "branch_compare"
-   [(set (pc)
-         (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2431,74 +2492,6 @@ else
- 
- })
- 
--;; Used to implement comparison instructions
--(define_expand "long_condjump"
--  [(set (pc)
--	(if_then_else (match_operand 0)
--		      (label_ref (match_operand 1))
--		      (pc)))])
--
--(define_insn "long_branch_zero"
--  [(set (pc)
--	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
--  				 [(match_operand:DI 1 "register_operand" "d")
--                                  (const_int 0)])
--                      (match_operand:DI 2 "pc_or_label_operand" "")
--                      (match_operand:DI 3 "pc_or_label_operand" "")))
--  ]
--  "TARGET_MB_64"
--  {
--    if (operands[3] == pc_rtx) 
--      return "beal%C0i%?\t%z1,%2";
--    else 
--      return "beal%N0i%?\t%z1,%3";
--  }
--  [(set_attr "type"	"branch")
--   (set_attr "mode"	"none")
--   (set_attr "length"	"4")]
--)
--
--(define_insn "long_branch_compare"
--  [(set (pc)
--        (if_then_else (match_operator:DI 0 "cmp_op"
--                                         [(match_operand:DI 1 "register_operand" "d")
--                                          (match_operand:DI 2 "register_operand" "d")
--                                         ])
--                      (label_ref (match_operand 3))
--                      (pc)))
--  (clobber(reg:DI R_TMP))]
--  "TARGET_MB_64"
--  {
--    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
--    enum rtx_code code = GET_CODE (operands[0]);
--
--    if (code == GT || code == LE)
--      {
--        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
--        code = swap_condition (code);
--      }
--    else if (code == GTU || code == LEU)
--      {
--        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
--        code = swap_condition (code);
--      }
--    else if (code == GE || code == LT)
--      {
--        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
--      }
--    else if (code == GEU || code == LTU)
--      {
--        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
--      }
--
--    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
--    return "beal%C0i%?\tr18,%3";
--  }
--  [(set_attr "type"     "branch")
--   (set_attr "mode"     "none")
--   (set_attr "length"   "12")]
--)
--
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
deleted file mode 100644
index d1cf4579..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 0c132e74714d217108d65fca630ab497a0d8821a Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 8 Aug 2018 17:37:26 +0530
-Subject: [PATCH 43/54] [Patch,Microblaze] :  previous commit broke the
- handling of SI Branch compare for Microblaze 32-bit..
-
----
- gcc/config/microblaze/microblaze.md | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 2213d6e..53ea401 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2224,8 +2224,8 @@ else
- (define_expand "cbranchsi4"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand 1 "register_operand")
--                        (match_operand 2 "arith_operand" "I,i")])
-+                       [(match_operand:SI 1 "register_operand")
-+                        (match_operand:SI 2 "arith_operand" "I,i")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
deleted file mode 100644
index 68791cb2..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From 259ed1ee33625964f5bc394ae660103b6c35510f Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 11 Sep 2018 13:43:48 +0530
-Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ...
-
----
- gcc/config/microblaze/microblaze-c.c  |  1 +
- gcc/config/microblaze/t-microblaze    | 15 ++++++---------
- libgcc/config/microblaze/t-microblaze | 11 +++--------
- 3 files changed, 10 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index d8a1d13..6586575 100644
---- a/gcc/config/microblaze/microblaze-c.c
-+++ b/gcc/config/microblaze/microblaze-c.c
-@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
-     }
-   if (TARGET_MB_64)
-     {
-+      builtin_define ("__microblaze64");
-       builtin_define ("__arch64__");
-       builtin_define ("__microblaze64__");
-       builtin_define ("__MICROBLAZE64__");
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 9fc80b1..35ab965 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,12 +1,9 @@
--MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
--MULTILIB_DIRNAMES = bs m mh le m64
--MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
--MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
-+MULTILIB_DIRNAMES = m64 bs le m mh
-+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 35021b2..8d954a4 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,16 +1,11 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
--			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
--        $(srcdir)/config/microblaze/divdi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
--        $(srcdir)/config/microblaze/moddi3.S \
-+        $(srcdir)/config/microblaze/muldi3_hard.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
--        $(srcdir)/config/microblaze/muldi3.S \
-         $(srcdir)/config/microblaze/stack_overflow_exit.S \
-         $(srcdir)/config/microblaze/udivsi3.S \
--        $(srcdir)/config/microblaze/udivdi3.S \
-         $(srcdir)/config/microblaze/umodsi3.S \
--        $(srcdir)/config/microblaze/umoddi3.S \
--        $(srcdir)/config/microblaze/divsi3_table.c \
-+        $(srcdir)/config/microblaze/divsi3_table.c
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch
deleted file mode 100644
index 8c0bde71..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From 654582846ebf847b52e769eb6e015c8e486461d6 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 11 Sep 2018 14:58:00 +0530
-Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
- extension issue
-
----
- gcc/config/microblaze/microblaze.c  | 16 ++++++++++------
- gcc/config/microblaze/microblaze.md |  2 +-
- 2 files changed, 11 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index fab79d9..6b6ca61 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2241,9 +2241,14 @@ compute_frame_size (HOST_WIDE_INT size)
- 
-   total_size += gp_reg_size;
- 
--  /* Add 4 bytes for MSR.  */
-+  /* Add 4/8 bytes for MSR.  */
-   if (microblaze_is_interrupt_variant ())
--    total_size += 4;
-+    {
-+      if (TARGET_MB_64)
-+        total_size += 8;
-+      else
-+        total_size += 4;
-+    }
- 
-   /* No space to be allocated for link register in leaf functions with no other
-      stack requirements.  */
-@@ -2527,7 +2532,6 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
--      int val1[2];
-       long l[2];
-       if (code == CONST_DOUBLE)
- 	{
-@@ -2542,10 +2546,10 @@ print_operand (FILE * file, rtx op, int letter)
- 	}
-       else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
-         {
--	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
--	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
-+	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
-+	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
-         }
--      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
-+      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-     }
-   else if (code == CONST_DOUBLE)
-     {
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 53ea401..3a6943b 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1094,7 +1094,7 @@
-       case 1:
-       case 2:
-         {
--          output_asm_insn ("ll%i1\t%0,%1", operands);
-+          output_asm_insn ("lw%i1\t%0,%1", operands);
-           return "sextl32\t%0,%0";
-         }
-     } 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch
deleted file mode 100644
index 22bb5b2f..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch
+++ /dev/null
@@ -1,306 +0,0 @@
-From 48f9f9a1c6809b14e7cfdd2343df92c0de18d730 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 28 Sep 2018 11:59:12 +0530
-Subject: [PATCH 46/54] Fixed below issues: - Floating point print issues in
- 64bit mode - Dejagnu Jump related issues - Added dbl instruction
-
----
- gcc/config/microblaze/microblaze.c  | 12 ++++-
- gcc/config/microblaze/microblaze.h  |  7 +++
- gcc/config/microblaze/microblaze.md | 89 ++++++++++++++++++++++++++++++-------
- libgcc/config/microblaze/crti.S     | 24 +++++++++-
- libgcc/config/microblaze/crtn.S     | 13 ++++++
- 5 files changed, 127 insertions(+), 18 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 6b6ca61..33d183e 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2536,7 +2536,12 @@ print_operand (FILE * file, rtx op, int letter)
-       if (code == CONST_DOUBLE)
- 	{
- 	  if (GET_MODE (op) == DFmode)
--	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+            {
-+  	      if (TARGET_MB_64)
-+	        REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+	      else
-+	        REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+	    }
- 	  else
- 	    {
-               REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-@@ -3874,7 +3879,10 @@ microblaze_expand_divide (rtx operands[])
-                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
--  jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-+  if (TARGET_MB_64) 
-+    jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
-+  else 
-+    jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-   JUMP_LABEL (jump) = div_end_label;
-   LABEL_NUSES (div_end_label) = 1; 
-   emit_barrier ();
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1e60513..e34f549 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -892,10 +892,17 @@ do {									 \
- /* We do this to save a few 10s of code space that would be taken up
-    by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
-    definition in crtstuff.c.  */
-+#ifdef __arch64__
-+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
-+    asm ( SECTION_OP "\n"                               \
-+          "\tbrealid   r15, " #FUNC "\n\t nop\n"         \
-+          TEXT_SECTION_ASM_OP);
-+#else
- #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
-     asm ( SECTION_OP "\n"                               \
-           "\tbrlid   r15, " #FUNC "\n\t nop\n"         \
-           TEXT_SECTION_ASM_OP);
-+#endif
- 
- /* We need to group -lm as well, since some Newlib math functions 
-    reference __errno!  */
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 3a6943b..2669a28 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -525,6 +525,15 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "floatdidf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (float:DF (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dbl\t%0,%1"
-+  [(set_attr "type"     "fcvt")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-@@ -1298,7 +1307,7 @@
- (define_insn "movdi_long_int"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- 	(match_operand:DI 1 "general_operand"      "i"))]
--  ""
-+  "TARGET_MB_64"
-   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-   [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-@@ -1581,7 +1590,7 @@
-           return "ll%i1\t%0,%1";
-       case 3:
-       {
--	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
-+	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-       }
-       case 5:
- 	return "sl%i0\t%1,%0";
-@@ -2371,9 +2380,9 @@ else
- 
- (define_insn "long_branch_compare"
-   [(set (pc)
--        (if_then_else (match_operator 0 "cmp_op"
--                                         [(match_operand 1 "register_operand" "d")
--                                          (match_operand 2 "register_operand" "d")
-+        (if_then_else (match_operator:DI 0 "cmp_op"
-+                                         [(match_operand:DI 1 "register_operand" "d")
-+                                          (match_operand:DI 2 "register_operand" "d")
-                                          ])
-                       (label_ref (match_operand 3))
-                       (pc)))
-@@ -2495,6 +2504,20 @@ else
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
-+(define_insn "jump_64"
-+  [(set (pc)
-+	(label_ref (match_operand 0 "" "")))]
-+  "TARGET_MB_64"
-+  {
-+    if (GET_CODE (operands[0]) == REG)
-+        return "brea%?\t%0";
-+    else	
-+        return "breai%?\t%l0";
-+  }
-+  [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "jump"
-   [(set (pc)
- 	(label_ref (match_operand 0 "" "")))]
-@@ -2538,19 +2561,28 @@ else
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   {
--    //gcc_assert (GET_MODE (operands[0]) == Pmode);
--
-+    gcc_assert (GET_MODE (operands[0]) == Pmode);
-+    
-     if (!flag_pic)
--      emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
--    else
--      emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+      {
-+ 	if (!TARGET_MB_64)
-+          emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-+	else
-+          emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
-+      }
-+    else {
-+ 	if (!TARGET_MB_64)
-+          emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+	else
-+          emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
-+      }
-     DONE;
-   }
- )
- 
- (define_insn "tablejump_internal1"
-   [(set (pc)
--	(match_operand 0 "register_operand" "d"))
-+	(match_operand:SI 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   "bra%?\t%0 "
-@@ -2558,11 +2590,21 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "tablejump_internal2"
-+  [(set (pc)
-+	(match_operand:DI 0 "register_operand" "d"))
-+  (use (label_ref (match_operand 1 "" "")))]
-+  "TARGET_MB_64"
-+  "bra%?\t%0 "
-+  [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_expand "tablejump_internal3"
-   [(parallel [(set (pc)
--		   (plus (match_operand 0 "register_operand" "d")
--			    (label_ref (match_operand:SI 1 "" ""))))
--             (use (label_ref (match_dup 1)))])]
-+		   (plus:SI (match_operand:SI 0 "register_operand" "d")
-+			    (label_ref:SI (match_operand:SI 1 "" ""))))
-+             (use (label_ref:SI (match_dup 1)))])]
-   ""
-   ""
- )
-@@ -2593,6 +2635,23 @@ else
-   ""
- )
- 
-+(define_insn ""
-+ [(set (pc)
-+	(plus:DI (match_operand:DI 0 "register_operand" "d")
-+		 (label_ref:DI (match_operand 1 "" ""))))
-+  (use (label_ref:DI (match_dup 1)))]
-+ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
-+  && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
-+  && flag_pic"
-+  {
-+    output_asm_insn ("addlk\t%0,%0,r20",operands);
-+    return "bra%?\t%0";
-+}
-+ [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
-+
- ;;----------------------------------------------------------------
- ;; Function prologue/epilogue and stack allocation
- ;;----------------------------------------------------------------
-@@ -3097,7 +3156,7 @@ else
- ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
- ;; between "mfs" and "addik" instructions.
- (define_insn "set_got"
--  [(set (match_operand:SI 0 "register_operand" "=r")
-+  [(set (match_operand 0 "register_operand" "=r")
-     (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
-   ""
-   "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
-diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 3386520..3d4cde2 100644
---- a/libgcc/config/microblaze/crti.S
-+++ b/libgcc/config/microblaze/crti.S
-@@ -33,11 +33,32 @@
-     .section .init, "ax"
-     .global __init
- 
-+#ifdef __arch64__
-     .weak _stack
--    .set  _stack, 0xffffffff
-+    .set  _stack, 0xffffffffffffffff
-     .weak _stack_end
-     .set  _stack_end, 0
- 
-+    .align 3
-+__init: 
-+    addlik  r1, r1, -32
-+    sl      r15, r0, r1
-+    addlik  r11, r0, _stack
-+    mts     rshr, r11
-+    addlik  r11, r0, _stack_end
-+    mts     rslr, r11
-+
-+    .section .fini, "ax"
-+    .global __fini
-+    .align 3
-+__fini: 
-+    addlik   r1, r1, -32
-+    sl       r15, r0, r1
-+#else
-+    .weak _stack
-+    .set  _stack, 0xffffffff
-+    .weak _stack_end
-+    .set  _stack_end, 0
-     .align 2
- __init: 
-     addik   r1, r1, -16
-@@ -53,3 +74,4 @@ __init:
- __fini: 
-     addik   r1, r1, -16
-     sw      r15, r0, r1
-+#endif
-diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 04e73d7..c262ce0 100644
---- a/libgcc/config/microblaze/crtn.S
-+++ b/libgcc/config/microblaze/crtn.S
-@@ -29,7 +29,19 @@
- .section .note.GNU-stack,"",%progbits
- .previous
- #endif
-+#ifdef __arch64__
-+    .section .init, "ax"
-+    ll      r15, r0, r1
-+    addlik   r1, r1, 32
-+    rtsd    r15, 8
-+    nop 
- 
-+    .section .fini, "ax"
-+    ll      r15, r0, r1
-+    addlik   r1, r1, 32   
-+    rtsd    r15, 8
-+    nop 
-+#else
-     .section .init, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
-@@ -39,3 +51,4 @@
-     lw      r15, r0, r1
-     rtsd    r15, 8 
-     addik   r1, r1, 16   
-+#endif
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch
deleted file mode 100644
index f28d9f51..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch
+++ /dev/null
@@ -1,135 +0,0 @@
-From b09721c830dd0831f50084e2e64920f83618e3f4 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 9 Oct 2018 10:07:08 +0530
-Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack
- pointer decrement issue
-
----
- gcc/config/microblaze/microblaze.md | 78 ++++++++++++++++++++++++++++++++-----
- gcc/config/microblaze/t-microblaze  |  7 ++++
- 2 files changed, 76 insertions(+), 9 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 2669a28..dca61d6 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -525,6 +525,66 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "fix_truncsfsi2"
-+  [(set (match_operand:SI 0 "register_operand" "=d")
-+        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-+  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-+  "fint\t%0,%1"
-+  [(set_attr "type"     "fint")
-+  (set_attr "mode"      "SF")
-+  (set_attr "length"    "4")])
-+
-+
-+(define_insn "adddf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (plus:DF (match_operand:DF 1 "register_operand" "d")
-+                 (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dadd\t%0,%1,%2"
-+  [(set_attr "type"     "fadd")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "subdf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (minus:DF (match_operand:DF 1 "register_operand" "d")
-+                  (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "drsub\t%0,%2,%1"
-+  [(set_attr "type"     "frsub")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "muldf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (mult:DF (match_operand:DF 1 "register_operand" "d")
-+                 (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dmul\t%0,%1,%2"
-+  [(set_attr "type"     "fmul")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "divdf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (div:DF (match_operand:DF 1 "register_operand" "d")
-+                (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "ddiv\t%0,%2,%1"
-+  [(set_attr "type"     "fdiv")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+
-+(define_insn "sqrtdf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dsqrt\t%0,%1"
-+  [(set_attr "type"     "fsqrt")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
- (define_insn "floatdidf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (float:DF (match_operand:DI 1 "register_operand" "d")))]
-@@ -534,13 +594,13 @@
-   (set_attr "mode"      "DF")
-   (set_attr "length"    "4")])
- 
--(define_insn "fix_truncsfsi2"
--  [(set (match_operand:SI 0 "register_operand" "=d")
--        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
--  "fint\t%0,%1"
--  [(set_attr "type"     "fint")
--  (set_attr "mode"      "SF")
-+(define_insn "floatdfdi2"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (float:DI (match_operand:DF 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dlong\t%0,%1"
-+  [(set_attr "type"     "fcvt")
-+  (set_attr "mode"      "DI")
-   (set_attr "length"    "4")])
- 
- ;;----------------------------------------------------------------
-@@ -658,8 +718,8 @@
-   "TARGET_MB_64"
-   "@
-    rsubl\t%0,%2,%1
--   addik\t%0,%z1,-%2
--   addik\t%0,%z1,-%2"
-+   addlik\t%0,%z1,-%2
-+   addlik\t%0,%z1,-%2"
-   [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4,4,4")])
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 35ab965..dfef45c 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,6 +1,13 @@
- MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
- MULTILIB_DIRNAMES = m64 bs le m mh
- MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
deleted file mode 100644
index 9a214d55..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 1ed548dd5993b8c3e58ef393467bdeea49c437be Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 12 Oct 2018 16:07:36 +0530
-Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap
- instructions
-
----
- gcc/config/microblaze/microblaze.md | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index dca61d6..d037843 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -441,6 +441,9 @@
-         (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
-   "TARGET_REORDER"
-   "swapb %0, %1"
-+  [(set_attr "type"	"no_delay_arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"4")]
- )
- 
- (define_insn "bswaphi2"
-@@ -449,6 +452,9 @@
-   "TARGET_REORDER"
-   "swapb %0, %1
-    swaph %0, %0"
-+  [(set_attr "type"	"no_delay_arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"8")]
- )
- 
- ;;----------------------------------------------------------------
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
deleted file mode 100644
index a682bc19..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From 1c889b64454f63f164f34d79d891d91b0bb4731f Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sat, 13 Oct 2018 21:12:43 +0530
-Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith
- libraries
-
----
- libgcc/config/microblaze/divsi3.S  | 25 ++++++++++++++++++++++++-
- libgcc/config/microblaze/modsi3.S  | 26 +++++++++++++++++++++++++-
- libgcc/config/microblaze/mulsi3.S  |  3 +++
- libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
- libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
- 5 files changed, 98 insertions(+), 4 deletions(-)
-
-diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index 663d398..7e7d875 100644
---- a/libgcc/config/microblaze/divsi3.S
-+++ b/libgcc/config/microblaze/divsi3.S
-@@ -41,6 +41,17 @@
- 	.globl	__divsi3
- 	.ent	__divsi3
- 	.type	__divsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__divsi3:
-+	.frame	r1,0,r15	
-+
-+	ADDIK   r1,r1,-32
-+	SLI     r28,r1,0
-+	SLI     r29,r1,8
-+	SLI     r30,r1,16
-+	SLI     r31,r1,24
-+#else
- __divsi3:
- 	.frame	r1,0,r15	
- 
-@@ -49,7 +60,7 @@ __divsi3:
- 	SWI     r29,r1,4
- 	SWI     r30,r1,8
- 	SWI     r31,r1,12
--
-+#endif
- 	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
- 	BGEID   r5,$LaR5_Pos 
-@@ -89,6 +100,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r28,r1,0
-+	LLI     r29,r1,8
-+	LLI     r30,r1,16
-+	LLI     r31,r1,24
-+	ADDLIK  r1,r1,32
-+	RTSD    r15,8
-+	NOP
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	LWI     r28,r1,0
-@@ -97,6 +119,7 @@ $LaRETURN_HERE:
- 	LWI     r31,r1,12
- 	RTSD    r15,8
- 	ADDIK   r1,r1,16
-+#endif
- .end __divsi3
- 	.size	__divsi3, . - __divsi3
- 
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 71b56e30..7e85064 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -41,6 +41,17 @@
- 	.globl	__modsi3
- 	.ent	__modsi3
- 	.type	__modsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__modsi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-32
-+	sli	r28,r1,0
-+	sli	r29,r1,8
-+	sli	r30,r1,16
-+	sli	r31,r1,24
-+#else
- __modsi3:
- 	.frame	r1,0,r15	
- 
-@@ -49,6 +60,7 @@ __modsi3:
- 	swi	r29,r1,4
- 	swi	r30,r1,8
- 	swi	r31,r1,12
-+#endif
- 
- 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
-@@ -88,6 +100,18 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli	r28,r1,0
-+	lli	r29,r1,8
-+	lli	r30,r1,16
-+	lli	r31,r1,24
-+	addik	r1,r1,32
-+	rtsd	r15,8
-+	nop
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	lwi	r28,r1,0
-@@ -95,7 +119,7 @@ $LaRETURN_HERE:
- 	lwi	r30,r1,8
- 	lwi	r31,r1,12
- 	rtsd	r15,8
--	addik	r1,r1,16
-+#endif
-         .end __modsi3
- 	.size	__modsi3, . - __modsi3
- 
-diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index 40b0b15..31a73c2 100644
---- a/libgcc/config/microblaze/mulsi3.S
-+++ b/libgcc/config/microblaze/mulsi3.S
-@@ -41,6 +41,9 @@
- 	.globl	__mulsi3
- 	.ent	__mulsi3
- 	.type	__mulsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+#endif
- __mulsi3:
- 	.frame	r1,0,r15
- 	add	r3,r0,r0
-diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index 2aef8ed..94adb6a 100644
---- a/libgcc/config/microblaze/udivsi3.S
-+++ b/libgcc/config/microblaze/udivsi3.S
-@@ -41,6 +41,16 @@
- 	.globl	__udivsi3
- 	.ent	__udivsi3
- 	.type	__udivsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__udivsi3:
-+	.frame	r1,0,r15	
-+
-+	ADDLIK   r1,r1,-24
-+    	SLI     r29,r1,0
-+	SLI     r30,r1,8
-+	SLI     r31,r1,16
-+#else
- __udivsi3:
- 	.frame	r1,0,r15	
- 
-@@ -48,7 +58,7 @@ __udivsi3:
-     	SWI     r29,r1,0
- 	SWI     r30,r1,4
- 	SWI     r31,r1,8
--
-+#endif
- 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
- 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
- 	ADDIK   r30,r0,0                    # Clear mod
-@@ -98,6 +108,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+        # Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r29,r1,0
-+	LLI     r30,r1,8
-+	LLI     r31,r1,16
-+	ADDIK   r1,r1,24
-+	RTSD    r15,8
-+	NOP
-+#else
- $LaRETURN_HERE:
-         # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	LWI     r29,r1,0
-@@ -105,5 +126,6 @@ $LaRETURN_HERE:
- 	LWI     r31,r1,8
- 	RTSD    r15,8
- 	ADDIK   r1,r1,12
-+#endif
-         .end __udivsi3
- 	.size	__udivsi3, . - __udivsi3
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index a2582d0..00b3bdf 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -41,6 +41,16 @@
- 	.globl	__umodsi3
- 	.ent	__umodsi3
- 	.type	__umodsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__umodsi3:
-+	.frame	r1,0,r15	
-+
-+	addik	r1,r1,-24
-+	swi	r29,r1,0
-+	swi	r30,r1,8
-+	swi	r31,r1,16
-+#else
- __umodsi3:
- 	.frame	r1,0,r15	
- 
-@@ -48,7 +58,7 @@ __umodsi3:
- 	swi	r29,r1,0
- 	swi	r30,r1,4
- 	swi	r31,r1,8
--
-+#endif
- 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
- 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
- 	ADDIK 	r3,r0,0                  # Clear div
-@@ -101,6 +111,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or 	r3,r0,r0   # set result to 0
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli 	r29,r1,0
-+	lli 	r30,r1,8
-+	lli 	r31,r1,16
-+	addlik 	r1,r1,24
-+	rtsd 	r15,8
-+	nop
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	lwi 	r29,r1,0
-@@ -108,5 +129,6 @@ $LaRETURN_HERE:
- 	lwi 	r31,r1,8
- 	rtsd 	r15,8
- 	addik 	r1,r1,12
-+#endif
- .end __umodsi3
- 	.size	__umodsi3, . - __umodsi3
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
deleted file mode 100644
index 95a26db2..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 751a01ce1eeaffcd41c504b9bf44868345b45da0 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 15 Oct 2018 12:00:10 +0530
-Subject: [PATCH 50/54] extending the Dwarf support to 64bit Microblaze
-
----
- gcc/config/microblaze/microblaze.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index e34f549..0a5ff0a 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
- /* Use DWARF 2 debugging information by default.  */
- #define DWARF2_DEBUGGING_INFO 1
- #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
--#define DWARF2_ADDR_SIZE 4
-+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
- 
- /* Target machine storage layout */
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch
deleted file mode 100644
index 574037ec..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From 295046d0a63148fb5a685ae2bd7a06489274c72a Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 16 Oct 2018 07:55:46 +0530
-Subject: [PATCH 51/54] fixing the typo errors in umodsi3 file
-
----
- libgcc/config/microblaze/umodsi3.S | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 00b3bdf..9bf65c3 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -47,9 +47,9 @@ __umodsi3:
- 	.frame	r1,0,r15	
- 
- 	addik	r1,r1,-24
--	swi	r29,r1,0
--	swi	r30,r1,8
--	swi	r31,r1,16
-+	sli	r29,r1,0
-+	sli	r30,r1,8
-+	sli	r31,r1,16
- #else
- __umodsi3:
- 	.frame	r1,0,r15	
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
deleted file mode 100644
index 95d39bb2..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024)
-
----
- gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
- 1 file changed, 14 insertions(+), 10 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0a5ff0a..740b8d9 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
- #define WORD_REGISTER_OPERATIONS 1
- 
- #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
--/*
--#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
--  if (GET_MODE_CLASS (MODE) == MODE_INT		\
--      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
--    (MODE) = TARGET_MB_64 ? DImode : SImode;
--*/
-+
-+#ifndef __arch64__
-+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
-+  if (GET_MODE_CLASS (MODE) == MODE_INT         \
-+      && GET_MODE_SIZE (MODE) < 4)              \
-+    (MODE) = SImode;
-+#endif
-+
- /* Standard register usage.  */
- 
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
- 
- #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
- 
-+#ifdef __aarch64__
- #define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (MODE,GP_RETURN)
--								
--/*#define LIBCALL_VALUE(MODE)						\
-+#else								
-+#define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (								\
- 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
- 	     || GET_MODE_SIZE (MODE) >= 4)				\
- 	    ? (MODE)							\
- 	    : SImode), GP_RETURN)
--*/
-+#endif
-+
- /* 1 if N is a possible register number for a function value.
-    On the MicroBlaze, R2 R3 are the only register thus used.
-    Currently, R2 are only implemented  here (C has no complex type)  */
-@@ -518,7 +522,7 @@ typedef struct microblaze_args
- /* 4 insns + 2 words of data.  */
- #define TRAMPOLINE_SIZE				(6 * 4)
- 
--#define TRAMPOLINE_ALIGNMENT			64
-+#define TRAMPOLINE_ALIGNMENT		(TARGET_MB_64 ? 64 : 32)
- 
- #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
- 
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
deleted file mode 100644
index e992075b..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 3e7161218dc8b4dd84ad8d31f6dbaa7c256e7a82 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 19 Oct 2018 14:26:25 +0530
-Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of
- modsi3 function
-
----
- libgcc/config/microblaze/modsi3.S | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 7e85064..46ff34a 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -119,6 +119,7 @@ $LaRETURN_HERE:
- 	lwi	r30,r1,8
- 	lwi	r31,r1,12
- 	rtsd	r15,8
-+	addik	r1,r1,16
- #endif
-         .end __modsi3
- 	.size	__modsi3, . - __modsi3
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
deleted file mode 100644
index afb88d35..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From a89b3e6902d7835129ad178f6af896eba15c5d5e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 24 Oct 2018 18:31:04 +0530
-Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong
- instruction mapping.
-
----
- gcc/config/microblaze/microblaze.md | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index d037843..cbd7e77 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -600,9 +600,9 @@
-   (set_attr "mode"      "DF")
-   (set_attr "length"    "4")])
- 
--(define_insn "floatdfdi2"
-+(define_insn "fix_truncdfdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
--        (float:DI (match_operand:DF 1 "register_operand" "d")))]
-+        (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
-   "TARGET_MB_64"
-   "dlong\t%0,%1"
-   [(set_attr "type"     "fcvt")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
deleted file mode 100644
index 4c694723..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 76e231f92afd8fda13d6ae18ef3aef0ea6096489 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 29 Nov 2018 17:55:08 +0530
-Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue
-
----
- gcc/config/microblaze/constraints.md | 2 +-
- gcc/config/microblaze/microblaze.md  | 8 ++++----
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 867a7b5..27c6bfc 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -55,7 +55,7 @@
- (define_constraint "K"
-   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-   (and (match_code "const_int")
--       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
-+       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
- 
- ;; Define floating point constraints
- 
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index cbd7e77..e03b835 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -646,8 +646,8 @@
-   if (TARGET_MB_64) 
-    {
-      if (GET_CODE (operands[2]) == CONST_INT &&
--       INTVAL(operands[2]) < (long)-549755813888 &&
--	INTVAL(operands[2]) > (long)549755813887)
-+       INTVAL(operands[2]) < (long long)-549755813888 &&
-+	INTVAL(operands[2]) > (long long)549755813887)
-       FAIL;
-    }
- })
-@@ -1264,7 +1264,7 @@
- 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
-   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
-            (GET_CODE (operands[1]) == CONST_INT && 
--                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
-+                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
-   "@
-    addlk\t%0,r0,r0\t
-    addlik\t%0,r0,%1\t #N1 %X1
-@@ -1298,7 +1298,7 @@
-      case 1:
-      case 2:
-         if (GET_CODE (operands[1]) == CONST_INT && 
--	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
-+	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-  	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-         else	
- 	  return "addlik\t%0,r0,%1";
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch
deleted file mode 100644
index c009c92d..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch
+++ /dev/null
@@ -1,16 +0,0 @@
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 740b8d9..4bda9c2 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -114,8 +114,9 @@ extern enum pipeline_type microblaze_pipe;
-   %{m64:-EL --oformat=elf64-microblazeel} \
-   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
-   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
--  %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
--  %{!T*: -dT xilinx.ld%s}"
-+  %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0}"
-+
-+//  %{!T*: -dT xilinx.ld%s}"
- 
- /* Specs for the compiler proper  */
- 
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
deleted file mode 100644
index a5a2039d..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6c58973f1cc1e37773aeab583aa3ac6331489106 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 14 Mar 2019 18:11:04 +0530
-Subject: [PATCH 57/57] Fix the MB-64 bug of handling QI objects
-
----
- gcc/config/microblaze/microblaze.md | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index e03b835..88aee9e 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2345,11 +2345,11 @@ else
- 
- (define_insn "branch_zero_64"
-   [(set (pc)
--	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-   				 [(match_operand:SI 1 "register_operand" "d")
-                                   (const_int 0)])
--                      (match_operand:SI 2 "pc_or_label_operand" "")
--                      (match_operand:SI 3 "pc_or_label_operand" "")))
-+                      (match_operand 2 "pc_or_label_operand" "")
-+                      (match_operand 3 "pc_or_label_operand" "")))
-   ]
-   "TARGET_MB_64"
-   {
-@@ -2365,11 +2365,11 @@ else
- 
- (define_insn "long_branch_zero"
-   [(set (pc)
--	(if_then_else (match_operator 0 "ordered_comparison_operator"
--  				 [(match_operand 1 "register_operand" "d")
-+	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
-+				 [(match_operand:DI 1 "register_operand" "d")
-                                   (const_int 0)])
--                      (match_operand 2 "pc_or_label_operand" "")
--                      (match_operand 3 "pc_or_label_operand" "")))
-+                      (match_operand:DI 2 "pc_or_label_operand" "")
-+                      (match_operand:DI 3 "pc_or_label_operand" "")))
-   ]
-   "TARGET_MB_64"
-   {
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
deleted file mode 100644
index 8bc47a43..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Fri, 29 Mar 2019 12:08:39 +0530
-Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of
- peephole2 optimization,if we can then we will fix the compiler issue.
-
----
- gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
- 1 file changed, 38 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 88aee9e..8bd175f 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -880,31 +880,44 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--(define_peephole2
--  [(set (match_operand:SI 0 "register_operand")
--        (fix:SI (match_operand:SF 1 "register_operand")))
--   (set (pc)
--        (if_then_else (match_operator 2 "ordered_comparison_operator"
--                       [(match_operand:SI 3 "register_operand")
--                        (match_operand:SI 4 "arith_operand")])
--                      (label_ref (match_operand 5))
--                      (pc)))]
--   "TARGET_HARD_FLOAT && !TARGET_MB_64"
--   [(set (match_dup 1) (match_dup 3))]
--
--  {
--    rtx condition;
--    rtx cmp_op0 = operands[3];
--    rtx cmp_op1 = operands[4];
--    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
--
--    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
--                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
--                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
--    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
--    emit_jump_insn (gen_condjump (condition, operands[5]));
--  }
--)
-+;; peephole2 optimization will be done only if fint and if-then-else
-+;; are dependent.added condition for the same.
-+;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
-+;; testcase:
-+;;        volatile float vec = 1.0;
-+;;        volatile int ci = 2;
-+;;        register int cj = (int)(vec);
-+;;//        ci=cj;
-+;;//      if (ci <0) {
-+;;        if (cj < 0) {
-+;;                ci = 0;
-+;;        }
-+;; commenting for now.we will check the possibility of this optimization later
-+
-+;;(define_peephole2
-+;;  [(set (match_operand:SI 0 "register_operand")
-+;;        (fix:SI (match_operand:SF 1 "register_operand")))
-+;;   (set (pc)
-+;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
-+;;                       [(match_operand:SI 3 "register_operand")
-+;;                        (match_operand:SI 4 "arith_operand")])
-+;;                      (label_ref (match_operand 5))
-+;;                      (pc)))]
-+;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
-+;;  [(set (match_dup 1) (match_dup 3))]
-+;;  {
-+;;    rtx condition;
-+;;    rtx cmp_op0 = operands[3];
-+;;    rtx cmp_op1 = operands[4];
-+;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+;;
-+;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
-+;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
-+;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
-+;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
-+;;    emit_jump_insn (gen_condjump (condition, operands[5]));
-+;;  }
-+;;)
- 
- ;;----------------------------------------------------------------
- ;; Negation and one's complement
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
deleted file mode 100644
index be4dfad5..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
+++ /dev/null
@@ -1,51 +0,0 @@
-From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 16 Apr 2019 17:20:24 +0530
-Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with
- this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
- before propagating constants."
-
-This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
----
- gcc/cprop.c | 4 ----
- 1 file changed, 4 deletions(-)
-
-diff --git a/gcc/cprop.c b/gcc/cprop.c
-index deb706b..e4df509 100644
---- a/gcc/cprop.c
-+++ b/gcc/cprop.c
-@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
-   int success = 0;
-   rtx set = single_set (insn);
- 
--#if 0
-   bool check_rtx_costs = true;
-   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
-   int old_cost = set ? set_rtx_cost (set, speed) : 0;
-@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
- 	  && (GET_CODE (XEXP (note, 0)) == CONST
- 	      || CONSTANT_P (XEXP (note, 0)))))
-     check_rtx_costs = false;
--#endif
- 
-   /* Usually we substitute easy stuff, so we won't copy everything.
-      We however need to take care to not duplicate non-trivial CONST
-@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
- 
-   validate_replace_src_group (from, to, insn);
- 
--#if 0
-   /* If TO is a constant, check the cost of the set after propagation
-      to the cost of the set before the propagation.  If the cost is
-      higher, then do not replace FROM with TO.  */
-@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
-       return false;
-     }
- 
--#endif
- 
-   if (num_changes_pending () && apply_change_group ())
-     success = 1;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
deleted file mode 100644
index 1548faad..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
+++ /dev/null
@@ -1,466 +0,0 @@
-From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 17 Apr 2019 12:36:16 +0530
-Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod
- assembly files.
-
----
- libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++++++++----
- libgcc/config/microblaze/modsi3.S  | 40 +++++++++++++++++++++++---
- libgcc/config/microblaze/mulsi3.S  | 33 +++++++++++++++++++++-
- libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
- libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
- 5 files changed, 212 insertions(+), 20 deletions(-)
-
-diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index 7e7d875..cfb4c05 100644
---- a/libgcc/config/microblaze/divsi3.S
-+++ b/libgcc/config/microblaze/divsi3.S
-@@ -46,7 +46,7 @@
- __divsi3:
- 	.frame	r1,0,r15	
- 
--	ADDIK   r1,r1,-32
-+	ADDLIK   r1,r1,-32
- 	SLI     r28,r1,0
- 	SLI     r29,r1,8
- 	SLI     r30,r1,16
-@@ -61,13 +61,23 @@ __divsi3:
- 	SWI     r30,r1,8
- 	SWI     r31,r1,12
- #endif
--	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
--	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
--	BGEID   r5,$LaR5_Pos 
-+#ifdef __arch64__
-+	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+	BEAGEID   r5,$LaR5_Pos
-+#else
-+        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+        BGEID   r5,$LaR5_Pos
-+#endif
- 	XOR     r28,r5,r6               # Get the sign of the result
- 	RSUBI   r5,r5,0                 # Make r5 positive
- $LaR5_Pos:
--	BGEI    r6,$LaR6_Pos
-+#ifdef __arch64__
-+	BEAGEI    r6,$LaR6_Pos
-+#else
-+        BGEI    r6,$LaR6_Pos
-+#endif
- 	RSUBI   r6,r6,0                 # Make r6 positive
- $LaR6_Pos:
- 	ADDIK   r30,r0,0                # Clear mod
-@@ -76,26 +86,51 @@ $LaR6_Pos:
- 
-         # First part try to find the first '1' in the r5
- $LaDIV0: 
--        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
-+#ifdef __arch64__
-+        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
-+#else
-+        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
-+#endif
- $LaDIV1:
- 	ADD     r5,r5,r5                # left shift logical r5
-+#ifdef __arch64__
-+        BEAGTID   r5,$LaDIV1
-+#else
- 	BGTID   r5,$LaDIV1       
-+#endif
- 	ADDIK   r29,r29,-1
- $LaDIV2:
- 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
- 	ADDC    r30,r30,r30             # Move that bit into the Mod register
- 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTI    r31,$LaMOD_TOO_SMALL
-+#else
- 	BLTI    r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
- 	ADDIK   r3,r3,1
- $LaMOD_TOO_SMALL:
- 	ADDIK   r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+#else
- 	BEQi    r29,$LaLOOP_END
-+#endif
- 	ADD     r3,r3,r3                # Shift in the '1' into div
-+#ifdef __arch64__
-+        BREAI     $LaDIV2                 # Div2
-+#else
- 	BRI     $LaDIV2                 # Div2
-+#endif
- $LaLOOP_END:
-+#ifdef __arch64__
-+        BEAGEI    r28,$LaRETURN_HERE
-+        BREAID    $LaRETURN_HERE
-+#else
- 	BGEI    r28,$LaRETURN_HERE
- 	BRID    $LaRETURN_HERE
-+#endif
- 	RSUBI   r3,r3,0                 # Negate the result
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 46ff34a..49618dd 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -62,40 +62,72 @@ __modsi3:
- 	swi	r31,r1,12
- #endif
- 
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+        BEAGEId   r5,$LaR5_Pos
-+#else
- 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
- 	BGEId	r5,$LaR5_Pos 
-+#endif
- 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
- 	RSUBI	r5,r5,0	                # Make r5 positive
- $LaR5_Pos:
--	BGEI	r6,$LaR6_Pos
-+#ifdef __arch64__
-+	BEAGEI	r6,$LaR6_Pos
-+#else
-+        BGEI    r6,$LaR6_Pos
-+#endif
- 	RSUBI	r6,r6,0	    # Make r6 positive
- $LaR6_Pos:
- 	ADDIK	r3,r0,0      # Clear mod
- 	ADDIK	r30,r0,0     # clear div
--	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+#ifdef __arch64__
-+	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
- 			     # the first bit search.
-+#else
-+        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+                             # the first bit search.
-+#endif
- 	ADDIK	r29,r0,32    # Initialize the loop count
-    # First part try to find the first '1' in the r5
- $LaDIV1:
- 	ADD	r5,r5,r5         # left shift logical r5
--	BGEID	r5,$LaDIV1       #
-+#ifdef __arch64__
-+	BEAGEID	r5,$LaDIV1       #
-+#else
-+        BGEID   r5,$LaDIV1       #
-+#endif
- 	ADDIK	r29,r29,-1
- $LaDIV2:
- 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
- 	ADDC	r3,r3,r3         # Move that bit into the Mod register
- 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTi    r31,$LaMOD_TOO_SMALL
-+#else
- 	BLTi	r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
- 	ADDIK	r30,r30,1
- $LaMOD_TOO_SMALL:
- 	ADDIK	r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r30,r30,r30         # Shift in the '1' into div
-+        BREAI     $LaDIV2          # Div2
-+$LaLOOP_END:
-+        BEAGEI    r28,$LaRETURN_HERE
-+        BREAId    $LaRETURN_HERE
-+#else
- 	BEQi	r29,$LaLOOP_END
- 	ADD	r30,r30,r30         # Shift in the '1' into div
- 	BRI	$LaDIV2          # Div2
- $LaLOOP_END:
- 	BGEI	r28,$LaRETURN_HERE
- 	BRId	$LaRETURN_HERE
-+#endif
- 	rsubi	r3,r3,0 # Negate the result
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
-@@ -108,7 +140,7 @@ $LaRETURN_HERE:
- 	lli	r29,r1,8
- 	lli	r30,r1,16
- 	lli	r31,r1,24
--	addik	r1,r1,32
-+	addlik	r1,r1,32
- 	rtsd	r15,8
- 	nop
- #else
-diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index 31a73c2..39951be 100644
---- a/libgcc/config/microblaze/mulsi3.S
-+++ b/libgcc/config/microblaze/mulsi3.S
-@@ -43,7 +43,37 @@
- 	.type	__mulsi3,@function
- #ifdef __arch64__
-         .align 3
--#endif
-+__mulsi3:
-+        .frame  r1,0,r15
-+        add     r3,r0,r0
-+        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
-+        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
-+        BEAGEId   r5,$L_R5_Pos
-+        XOR     r4,r5,r6                  # Get the sign of the result
-+        RSUBI   r5,r5,0                   # Make r5 positive
-+$L_R5_Pos:
-+        BEAGEI    r6,$L_R6_Pos
-+        RSUBI   r6,r6,0                   # Make r6 positive
-+$L_R6_Pos:
-+        breai     $L1
-+$L2:
-+        add     r5,r5,r5
-+$L1:
-+        srl     r6,r6
-+        addc    r7,r0,r0
-+        beaeqi    r7,$L2
-+        beaneid   r6,$L2
-+        add     r3,r3,r5
-+        bealti    r4,$L_NegateResult
-+        rtsd    r15,8
-+        nop
-+$L_NegateResult:
-+        rtsd    r15,8
-+        rsub    r3,r3,r0
-+$L_Result_Is_Zero:
-+        rtsd    r15,8
-+        addi    r3,r0,0
-+#else
- __mulsi3:
- 	.frame	r1,0,r15
- 	add	r3,r0,r0
-@@ -74,5 +104,6 @@ $L_NegateResult:
- $L_Result_Is_Zero:
- 	rtsd	r15,8
- 	addi	r3,r0,0
-+#endif
- 	.end __mulsi3
- 	.size	__mulsi3, . - __mulsi3
-diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index 94adb6a..d4fe285 100644
---- a/libgcc/config/microblaze/udivsi3.S
-+++ b/libgcc/config/microblaze/udivsi3.S
-@@ -59,52 +59,96 @@ __udivsi3:
- 	SWI     r30,r1,4
- 	SWI     r31,r1,8
- #endif
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
-+        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
-+#else
- 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
- 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
-+#endif
- 	ADDIK   r30,r0,0                    # Clear mod
- 	ADDIK   r29,r0,32                   # Initialize the loop count
- 
-         # Check if r6 and r5 are equal # if yes, return 1
- 	RSUB 	r18,r5,r6
-+#ifdef __arch64__
-+        BEAEQID   r18,$LaRETURN_HERE
-+#else
- 	BEQID	r18,$LaRETURN_HERE
-+#endif
- 	ADDIK	r3,r0,1
- 
-         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
- 	XOR	r18,r5,r6
--	BGEID	r18,16
-+#ifdef __arch64__
-+	BEAGEID	r18,16
-+#else
-+        BGEID   r18,16
-+#endif
- 	ADD	r3,r0,r0                    # We would anyways clear r3
-+#ifdef __arch64__
-+        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
-+        BREAI     $LCheckr6
-+        RSUB    r18,r6,r5                   # MICROBLAZEcmp
-+        BEALTI    r18,$LaRETURN_HERE
-+#else
- 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
- 	BRI	$LCheckr6
- 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
- 	BLTI	r18,$LaRETURN_HERE
--
-+#endif
-         # If r6 [bit 31] is set, then return result as 1
- $LCheckr6:
--	BGTI	r6,$LaDIV0
--	BRID	$LaRETURN_HERE
-+#ifdef __arch64__
-+	BEAGTI	r6,$LaDIV0
-+	BREAID	$LaRETURN_HERE
-+#else
-+        BGTI    r6,$LaDIV0
-+        BRID    $LaRETURN_HERE
-+#endif
- 	ADDIK	r3,r0,1
- 
-         # First part try to find the first '1' in the r5
- $LaDIV0:
-+#ifdef __arch64__
-+        BEALTI    r5,$LaDIV2
-+#else
- 	BLTI    r5,$LaDIV2	
-+#endif
- $LaDIV1:
- 	ADD     r5,r5,r5                    # left shift logical r5
-+#ifdef __arch64__
-+        BEAGTID   r5,$LaDIV1
-+#else
- 	BGTID   r5,$LaDIV1       
-+#endif
- 	ADDIK   r29,r29,-1
- $LaDIV2:
- 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
- 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
- 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTI    r31,$LaMOD_TOO_SMALL
-+#else
-     	BLTI    r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
- 	ADDIK   r3,r3,1
- $LaMOD_TOO_SMALL:
- 	ADDIK   r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r3,r3,r3 # Shift in the '1' into div
-+        BREAI     $LaDIV2   # Div2
-+$LaLOOP_END:
-+        BREAI     $LaRETURN_HERE
-+#else
- 	BEQi    r29,$LaLOOP_END
- 	ADD     r3,r3,r3 # Shift in the '1' into div
- 	BRI     $LaDIV2   # Div2
- $LaLOOP_END:
- 	BRI     $LaRETURN_HERE
-+#endif
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-@@ -115,7 +159,7 @@ $LaRETURN_HERE:
- 	LLI     r29,r1,0
- 	LLI     r30,r1,8
- 	LLI     r31,r1,16
--	ADDIK   r1,r1,24
-+	ADDLIK   r1,r1,24
- 	RTSD    r15,8
- 	NOP
- #else
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 9bf65c3..3bd5d48 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -46,7 +46,7 @@
- __umodsi3:
- 	.frame	r1,0,r15	
- 
--	addik	r1,r1,-24
-+	addlik	r1,r1,-24
- 	sli	r29,r1,0
- 	sli	r30,r1,8
- 	sli	r31,r1,16
-@@ -59,27 +59,77 @@ __umodsi3:
- 	swi	r30,r1,4
- 	swi	r31,r1,8
- #endif
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
-+        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
-+#else
- 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
- 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
-+#endif
- 	ADDIK 	r3,r0,0                  # Clear div
- 	ADDIK 	r30,r0,0     	# clear mod
- 	ADDIK 	r29,r0,32       # Initialize the loop count
- 
- # Check if r6 and r5 are equal # if yes, return 0
- 	rsub 	r18,r5,r6
--	beqi	r18,$LaRETURN_HERE
- 
-+#ifdef __arch64__
-+	beaeqi    r18,$LaRETURN_HERE
-+#else
-+	beqi	r18,$LaRETURN_HERE
-+#endif
- # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
- 	xor	r18,r5,r6
-+#ifdef __arch64__
-+        beageid   r18,16
-+        addik   r3,r5,0
-+        bealti    r6,$LaRETURN_HERE
-+        breai     $LCheckr6
-+        rsub    r18,r5,r6 # MICROBLAZEcmp
-+        beagti    r18,$LaRETURN_HERE
-+#else
- 	bgeid	r18,16
- 	addik	r3,r5,0
- 	blti	r6,$LaRETURN_HERE
- 	bri	$LCheckr6
- 	rsub	r18,r5,r6 # MICROBLAZEcmp
- 	bgti	r18,$LaRETURN_HERE
--
-+#endif
- # If r6 [bit 31] is set, then return result as r5-r6
- $LCheckr6:
-+#ifdef __arch64__
-+        beagtid   r6,$LaDIV0
-+        addik   r3,r0,0
-+        addik   r18,r0,0x7fffffff
-+        and     r5,r5,r18
-+        and     r6,r6,r18
-+        breaid    $LaRETURN_HERE
-+        rsub    r3,r6,r5
-+# First part: try to find the first '1' in the r5
-+$LaDIV0:
-+        BEALTI    r5,$LaDIV2
-+$LaDIV1:
-+        ADD     r5,r5,r5     # left shift logical r5
-+        BEAGEID   r5,$LaDIV1   #
-+        ADDIK   r29,r29,-1
-+$LaDIV2:
-+        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
-+        ADDC    r3,r3,r3     # Move that bit into the Mod register
-+        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
-+        BEALTi    r31,$LaMOD_TOO_SMALL
-+        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
-+        ADDIK   r30,r30,1
-+$LaMOD_TOO_SMALL:
-+        ADDIK   r29,r29,-1
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r30,r30,r30 # Shift in the '1' into div
-+        BREAI     $LaDIV2     # Div2
-+$LaLOOP_END:
-+        BREAI     $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+        or      r3,r0,r0   # set result to 0
-+#else
- 	bgtid	r6,$LaDIV0
- 	addik	r3,r0,0
- 	addik	r18,r0,0x7fffffff
-@@ -111,7 +161,7 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or 	r3,r0,r0   # set result to 0
--
-+#endif
- #ifdef __arch64__
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch
deleted file mode 100644
index 690bc727..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch
+++ /dev/null
@@ -1,479 +0,0 @@
-From e1b8cfe6c0b4a0bd90ecbd3e85ae7114df21b6cc Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 18 Apr 2019 16:00:37 +0530
-Subject: [PATCH 61/62] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
- 17 14:11:00 2019 +0530
-
-    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
-    By default MB-64 is generatting barrel-shift instructions. It has been
-    removed from default. Barrel-shift instructions will be generated only if
-    barrel-shifter is enabled. Similarly to double instructions as well.
-
-    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c  |   2 +-
- gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
- 2 files changed, 252 insertions(+), 19 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 33d183e..c321b03 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[])
-   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
- 
-   if (TARGET_MB_64) {
--      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
-       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
-     }
-   else  {
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8bd175f..b5b60fb 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -545,7 +545,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (plus:DF (match_operand:DF 1 "register_operand" "d")
-                  (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dadd\t%0,%1,%2"
-   [(set_attr "type"     "fadd")
-   (set_attr "mode"      "DF")
-@@ -555,7 +555,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (minus:DF (match_operand:DF 1 "register_operand" "d")
-                   (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "drsub\t%0,%2,%1"
-   [(set_attr "type"     "frsub")
-   (set_attr "mode"      "DF")
-@@ -565,7 +565,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (mult:DF (match_operand:DF 1 "register_operand" "d")
-                  (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dmul\t%0,%1,%2"
-   [(set_attr "type"     "fmul")
-   (set_attr "mode"      "DF")
-@@ -575,7 +575,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (div:DF (match_operand:DF 1 "register_operand" "d")
-                 (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "ddiv\t%0,%2,%1"
-   [(set_attr "type"     "fdiv")
-   (set_attr "mode"      "DF")
-@@ -585,7 +585,7 @@
- (define_insn "sqrtdf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dsqrt\t%0,%1"
-   [(set_attr "type"     "fsqrt")
-   (set_attr "mode"      "DF")
-@@ -594,7 +594,7 @@
- (define_insn "floatdidf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (float:DF (match_operand:DI 1 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dbl\t%0,%1"
-   [(set_attr "type"     "fcvt")
-   (set_attr "mode"      "DF")
-@@ -603,7 +603,7 @@
- (define_insn "fix_truncdfdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
-         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dlong\t%0,%1"
-   [(set_attr "type"     "fcvt")
-   (set_attr "mode"      "DI")
-@@ -1299,6 +1299,34 @@
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "*movdi_internal2_bshift"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
-+	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "addlk\t%0,%1,r0";
-+     case 1:
-+     case 2:
-+        if (GET_CODE (operands[1]) == CONST_INT &&
-+	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-+	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+        else
-+	  return "addlik\t%0,r0,%1";
-+     case 3:
-+     case 4:
-+       return "ll%i1\t%0,%1";
-+     case 5:
-+     case 6:
-+       return "sl%i0\t%z1,%0";
-+     }
-+   }
-+  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,4,12,4,8,4,8")])
-+
- (define_insn "*movdi_internal2"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
- 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-@@ -1312,7 +1340,15 @@
-      case 2:
-         if (GET_CODE (operands[1]) == CONST_INT && 
- 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+          {
-+            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+            output_asm_insn ("addlik\t%0,r0,%h1", operands);
-+            output_asm_insn ("addlik\t%2,r0,32", operands);
-+            output_asm_insn ("addlik\t%2,%2,-1", operands);
-+            output_asm_insn ("beaneid\t%2,.-8", operands);
-+            output_asm_insn ("addlk\t%0,%0,%0", operands);
-+            return "addlik\t%0,%0,%j1 #li => la";
-+          }
-         else	
- 	  return "addlik\t%0,r0,%1";
-      case 3:
-@@ -1386,7 +1422,7 @@
- (define_insn "movdi_long_int"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- 	(match_operand:DI 1 "general_operand"      "i"))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-   [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-@@ -1653,6 +1689,33 @@
- ;; movdf_internal
- ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
- ;;
-+(define_insn "*movdf_internal_64_bshift"
-+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-+        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+	return "addlk\t%0,%1,r0";
-+      case 1:
-+	return "addlk\t%0,r0,r0";
-+      case 2:
-+      case 4:
-+          return "ll%i1\t%0,%1";
-+      case 3:
-+      {
-+	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-+      }
-+      case 5:
-+	return "sl%i0\t%1,%0";
-+    }
-+    gcc_unreachable ();
-+  }
-+  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4,4,4,16,4,4")])
-+
- (define_insn "*movdf_internal_64"
-   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-@@ -1669,7 +1732,13 @@
-           return "ll%i1\t%0,%1";
-       case 3:
-       {
--	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-+	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+	output_asm_insn ("addlik\t%0,r0,%h1", operands);
-+	output_asm_insn ("addlik\t%2,r0,32", operands);
-+	output_asm_insn ("addlik\t%2,%2,-1", operands);
-+	output_asm_insn ("beaneid\t%2,.-8", operands);
-+	output_asm_insn ("addlk\t%0,%0,%0", operands);
-+	return "addlik\t%0,%0,%j1 #li => la";
-       }
-       case 5:
- 	return "sl%i0\t%1,%0";
-@@ -1789,11 +1858,21 @@
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -1803,7 +1882,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-   bsllli\t%0,%1,%2
-   bslll\t%0,%1,%2"
-@@ -1811,6 +1890,51 @@ else
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")]
- )
-+
-+(define_insn "ashldi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "addlk\t%0,%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+   (set_attr "mode"    "DI")
-+   (set_attr "length"  "20")]
-+)
-+
-+(define_insn "ashldi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1])) 
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "addlk\t%0,%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "DI")
-+  (set_attr "length"   "28")]
-+)
-+
- ;; The following patterns apply when there is no barrel shifter present
- 
- (define_insn "*ashlsi3_with_mul_delay"
-@@ -1944,11 +2068,21 @@ else
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -1958,7 +2092,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-    bslrai\t%0,%1,%2
-    bslra\t%0,%1,%2"
-@@ -1966,6 +2100,51 @@ else
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")]
-   )
-+
-+(define_insn "ashrdi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srla\t%0,%0";
-+  }
-+  [(set_attr "type"    "arith")
-+  (set_attr "mode"    "DI")
-+  (set_attr "length"  "20")]
-+)
-+
-+(define_insn "ashrdi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1])) 
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srla\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "DI")
-+  (set_attr "length"   "28")]
-+)
-+
- (define_expand "ashrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2083,11 +2262,21 @@ else
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -2097,7 +2286,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-    bslrli\t%0,%1,%2
-    bslrl\t%0,%1,%2"
-@@ -2106,6 +2295,50 @@ else
-   (set_attr "length"	"4,4")]
-   )
- 
-+(define_insn "lshrdi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srll\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"    "DI")
-+  (set_attr "length"  "20")]
-+)
-+
-+(define_insn "lshrdi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srll\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "SI")
-+  (set_attr "length"   "28")]
-+)
-+
- (define_expand "lshrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2233,7 +2466,7 @@ else
- 	(eq:DI 
- 	       (match_operand:DI 1 "register_operand" "d")
- 	       (match_operand:DI 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
-   "pcmpleq\t%0,%1,%2"
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"DI")
-@@ -2245,7 +2478,7 @@ else
- 	(ne:DI 
- 	       (match_operand:DI 1 "register_operand" "d")
- 	       (match_operand:DI 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
-   "pcmplne\t%0,%1,%2"
-   [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
deleted file mode 100644
index e7dfa89c..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 612e6579116e6714417ea21e6c13b0968bb6aac2 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Wed, 8 May 2019 14:12:03 +0530
-Subject: [PATCH 62/62] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
- disable fivopts by default
-
-Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
-
- * gcc/common/config/microblaze/microblaze-common.c
-   (microblaze_option_optimization_table): Disable fivopts by default.
-
-Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
----
- gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index fe45f2e..2873d4b 100644
---- a/gcc/common/config/microblaze/microblaze-common.c
-+++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -27,13 +27,15 @@
- /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
- static const struct default_options microblaze_option_optimization_table[] =
-   {
--    /* Turn off ivopts by default. It messes up cse. */
-+    /* Turn off ivopts by default. It messes up cse. 
-+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
-     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
--    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-     { OPT_LEVELS_NONE, 0, NULL, 0 }
-   };
- 
- #undef TARGET_DEFAULT_TARGET_FLAGS
- #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
- 
-+#undef TARGET_OPTION_OPTIMIZATION_TABLE
-+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
- struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
--- 
-2.7.4
-
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
new file mode 100644
index 00000000..28247daa
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -0,0 +1,35 @@
+From 23e6126392ab228c1d6483c02ffc32b15f00777e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 13:13:57 +0530
+Subject: [PATCH 01/63] LOCAL]: Testsuite - builtins tests require fpic
+ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+
+	gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index acb9eac..363ce07 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
+    lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+ 
++<<<<<<< HEAD
++=======
++if [istarget "microblaze*-*-linux*"] {
++   lappend additional_flags "-Wl,-zmuldefs"
++   lappend additional_flags "-fPIC"
++}
++
++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+ 	c-torture-execute [list $src \
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
new file mode 100644
index 00000000..8e4a2a32
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -0,0 +1,31 @@
+From e9c8884f473eae307945ceabaa1ff03278236c23 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 14:31:10 +0530
+Subject: [PATCH 02/63] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
+ particular testcase fails with a timeout. Instead, fail it at compile-time
+ for microblaze. This speeds up the testsuite without removing it from the
+ FAIL reports.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+---
+ gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C
+index 3862756..db9f990 100644
+--- a/gcc/testsuite/g++.dg/opt/memcpy1.C
++++ b/gcc/testsuite/g++.dg/opt/memcpy1.C
+@@ -4,6 +4,10 @@
+ // { dg-do compile }
+ // { dg-options "-O" }
+ 
++#if defined (__MICROBLAZE__)
++#error "too slow on mb. Investigate."
++#endif
++
+ typedef unsigned char uint8_t;
+ typedef uint8_t uint8;
+ __extension__ typedef __SIZE_TYPE__ size_t;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
new file mode 100644
index 00000000..ef994457
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
@@ -0,0 +1,119 @@
+From fb4b4d4ecba04859d52a653d7c453df92014dc38 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:28:38 +0530
+Subject: [PATCH 03/63] [LOCAL]: Testsuite - explicitly add -fivopts for tests
+ that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt
+ exist in 4.6 branch)
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+Conflicts:
+	gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+---
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
+ 8 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+index 438db88..ede883e 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
+-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
+ 
+ void test (int *b, int *e, int stride)
+   {
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+index 07ff1b7..a09710c 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+@@ -1,5 +1,5 @@
+ // { dg-do compile }
+-// { dg-options "-O2 -fdump-tree-ivopts-details" }
++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
+ 
+ class MinimalVec3
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+index bda2516..22c8a5d 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+ 
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+index f0770ab..65d74c8 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+ 
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+index 5f42857..9bc86ee 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+@@ -1,7 +1,7 @@
+ /* A test for induction variable merging.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ 
+ void foo(long);
+ 
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+index 50d86a0..1e3eacd 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fopt-info-loop-missed" } */
++/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */
+ extern void g(void);
+ 
+ void
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+index 2c6cfc6..648e6e6 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-ivopts" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
+ 
+ void vnum_test8(int *data) 
+ { 
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+index e911bfc..5d3e7e0 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-Os -fdump-tree-optimized" } */
++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
+ 
+ /* Slightly changed testcase from PR middle-end/40815.  */
+ void bar(char*, char*, int);
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
new file mode 100644
index 00000000..a575b518
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -0,0 +1,35 @@
+From 38022a87b01cf2e36b605d4f6d0faab22a0d2f44 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:46:28 +0530
+Subject: [PATCH 04/63] [LOCAL]: For dejagnu static testing on qemu, suppress
+ warnings about multiple definitions from the test function and libc in line
+ with method used by powerpc. Dynamic linking and using a qemu binary which
+ understands sysroot resolves all test failures with builtins
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index 363ce07..56b1a9a 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
+    lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+ 
+-<<<<<<< HEAD
+-=======
+ if [istarget "microblaze*-*-linux*"] {
+    lappend additional_flags "-Wl,-zmuldefs"
+-   lappend additional_flags "-fPIC"
+ }
+ 
+->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+ 	c-torture-execute [list $src \
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
new file mode 100644
index 00000000..18fd6dec
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -0,0 +1,35 @@
+From a7dfb5f158f16f88b30aabe903c4fb088889eeef Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:50:35 +0530
+Subject: [PATCH 05/63] [Patch, testsuite]: Add MicroBlaze to target-supports
+ for atomic buil. .tin tests
+
+MicroBlaze added to supported targets for atomic builtin tests.
+
+Changelog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/lib/target-supports.exp: Add microblaze to
+   check_effective_target_sync_int_long.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index cda0f3d..0a69659e 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -6829,6 +6829,7 @@ proc check_effective_target_sync_int_long { } {
+ 		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget bfin*-*linux*]
+ 	     || [istarget hppa*-*linux*]
++	     || [istarget microblaze*-*linux*]
+ 	     || [istarget s390*-*-*] 
+ 	     || [istarget powerpc*-*-*]
+ 	     || [istarget crisv32-*-*] || [istarget cris-*-*]
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
new file mode 100644
index 00000000..b428d121
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
@@ -0,0 +1,118 @@
+From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Sat, 26 Aug 2017 19:21:18 -0700
+Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
+ it
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Upstream-Status: Pending
+---
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
+ gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
+ gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
+ 8 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+index 438db88204..ede883eb28 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
+@@ -1,5 +1,5 @@
+ /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
+-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
+ 
+ void test (int *b, int *e, int stride)
+   {
+diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+index eb72581390..02f3ea4a7d 100644
+--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
+@@ -1,5 +1,5 @@
+ // { dg-do compile }
+-// { dg-options "-O2 -fdump-tree-ivopts-details" }
++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
+ 
+ class MinimalVec3
+ {
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+index bda2516735..22c8a5dcff 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+ 
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+index f0770abdbb..65d74c8e62 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
+@@ -1,7 +1,7 @@
+ /* A test for strength reduction and induction variable elimination.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ /* { dg-require-effective-target size32plus } */
+ 
+ /* Size of this structure should be sufficiently weird so that no memory
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+index 5f42857fe1..9bc86ee0d2 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
+@@ -1,7 +1,7 @@
+ /* A test for induction variable merging.  */
+ 
+ /* { dg-do compile } */
+-/* { dg-options "-O1 -fdump-tree-optimized" } */
++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
+ 
+ void foo(long);
+ 
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+index 3c8ee06016..db192a657f 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
++/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
+ extern void g(void);
+ 
+ void
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+index 2c6cfc6f83..648e6e67e8 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-O2 -fdump-tree-ivopts" } */
++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
+ 
+ void vnum_test8(int *data) 
+ { 
+diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+index e911bfcd52..5d3e7e0801 100644
+--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
+@@ -1,5 +1,5 @@
+ /* { dg-do compile } */
+-/* { dg-options "-Os -fdump-tree-optimized" } */
++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
+ 
+ /* Slightly changed testcase from PR middle-end/40815.  */
+ void bar(char*, char*, int);
+-- 
+2.14.2
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
new file mode 100644
index 00000000..e4a86dc4
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -0,0 +1,43 @@
+From e23b1a424cfd852f7a33f29c0b80d867ca533c3b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 16:20:01 +0530
+Subject: [PATCH 06/63] [Patch, testsuite]: Update MicroBlaze strings test for
+ new scan-assembly output resulting in use of $LC label
+
+ChangeLog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
+   to include $LC label.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+index 7a63faf..0403b7b 100644
+--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+@@ -1,13 +1,15 @@
+ /* { dg-options "-O3" } */
+ 
++/* { dg-final { scan-assembler "\.rodata*" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
++
+ #include <string.h>
+ 
+-/* { dg-final { scan-assembler "\.rodata*" } } */
+ extern void somefunc (char *);
+ int testfunc ()
+ {
+     char string2[80];
+-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
+     strcpy (string2, "hello");
+     somefunc (string2);
+ }
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
new file mode 100644
index 00000000..8c43de05
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -0,0 +1,67 @@
+From c210044f15df2433438b6b74e5c2bcf79458c2e4 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:14:15 +0530
+Subject: [PATCH 07/63] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
+ in regex match Extend regex pattern to include optional ext at the end of
+ .weak to match the MicroBlaze weak label .weakext
+
+ChangeLog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
+   pattern to take optional ext after .weak.
+ * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+
+	gcc/testsuite/g++.dg/abi/rtti3.C
+---
+ gcc/testsuite/g++.dg/abi/rtti3.C  | 4 ++--
+ gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
+ gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
+index 0cc7d3e..f284cd9 100644
+--- a/gcc/testsuite/g++.dg/abi/rtti3.C
++++ b/gcc/testsuite/g++.dg/abi/rtti3.C
+@@ -3,8 +3,8 @@
+ 
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
+-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
+ 
+diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
+index f2347f7..dcec8a7 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk3.C
++++ b/gcc/testsuite/g++.dg/abi/thunk3.C
+@@ -1,5 +1,5 @@
+ // { dg-require-weak "" }
+-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+ 
+ struct Base 
+diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
+index 6e8f124..d1d34fe 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk4.C
++++ b/gcc/testsuite/g++.dg/abi/thunk4.C
+@@ -1,6 +1,6 @@
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+ 
+ struct Base 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
new file mode 100644
index 00000000..d02be316
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -0,0 +1,28 @@
+From 283d8576d2599b3c38814e7c70e3f36ed51df9da Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:34:27 +0530
+Subject: [PATCH 08/63] [Patch, testsuite]: Add MicroBlaze to
+ check_profiling_available Testsuite, add microblaze*-*-* target in
+ check_profiling_available inline with other archs setting
+ profiling_available_saved to 0
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 0a69659e..d47819c 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -678,6 +678,7 @@ proc check_profiling_available { test_what } {
+ 	     || [istarget m68k-*-elf]
+ 	     || [istarget m68k-*-uclinux*]
+ 	     || [istarget mips*-*-elf*]
++	     || [istarget microblaze*-*-*]
+ 	     || [istarget mmix-*-*]
+ 	     || [istarget mn10300-*-elf*]
+ 	     || [istarget moxie-*-elf*]
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch
new file mode 100644
index 00000000..ae24c080
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0009-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -0,0 +1,68 @@
+From 1905061b279e6fe5fd9861fc490fd4075edac4a8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:41:43 +0530
+Subject: [PATCH 09/63] [Patch, microblaze]: Fix atomic side effects. In
+ atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
+ during optimization. Previously, the outputs were considered unused; this
+ generated assembly code with undefined side effects after invocation of the
+ atomic.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
+---
+ gcc/config/microblaze/microblaze.md |  3 +++
+ gcc/config/microblaze/sync.md       | 21 +++++++++++++--------
+ 2 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 183afff..7a40c53 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -43,6 +43,9 @@
+   (UNSPEC_TLS           106)    ;; jump table
+   (UNSPEC_SET_TEXT      107)    ;; set text start
+   (UNSPEC_TEXT          108)    ;; data text relative
++  (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
++  (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
++  (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
+ ])
+ 
+ (define_c_enum "unspec" [
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 6f16ca6..bebab5c 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -18,14 +18,19 @@
+ ;; <http://www.gnu.org/licenses/>.
+ 
+ (define_insn "atomic_compare_and_swapsi"
+-  [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
+-   (match_operand:SI 1 "register_operand" "=&d")	;; val output
+-   (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
+-   (match_operand:SI 3 "register_operand" "d")		;; expected value
+-   (match_operand:SI 4 "register_operand" "d")		;; desired value
+-   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
+-   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
+-   (match_operand:SI 7 "const_int_operand" "")		;; mod_f
++  [(set (match_operand:SI 0 "register_operand" "=&d")		;; bool output
++        (unspec_volatile:SI
++          [(match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
++           (match_operand:SI 3 "register_operand" "d")		;; expected value
++           (match_operand:SI 4 "register_operand" "d")]		;; desired value
++          UNSPECV_CAS_BOOL))
++   (set (match_operand:SI 1 "register_operand" "=&d")		;; val output
++        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
++   (set (match_dup 2)
++        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
++   (match_operand:SI 5 "const_int_operand" "")			;; is_weak
++   (match_operand:SI 6 "const_int_operand" "")			;; mod_s
++   (match_operand:SI 7 "const_int_operand" "")			;; mod_f
+    (clobber (match_scratch:SI 8 "=&d"))]
+   ""
+   {
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 00000000..07a43177
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,40 @@
+From 65bc1969bd652df4bf9d01d30547a947da293550 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:45:45 +0530
+Subject: [PATCH 10/63] [Patch, microblaze]: Fix atomic boolean return value.
+ In atomic_compare_and_swapsi, fix boolean return value. Previously, it
+ contained zero if successful and non-zero if unsuccessful.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/sync.md | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index bebab5c..72eac09 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -34,15 +34,16 @@
+    (clobber (match_scratch:SI 8 "=&d"))]
+   ""
+   {
+-    output_asm_insn ("addc \tr0,r0,r0", operands);
++    output_asm_insn ("add  \t%0,r0,r0", operands);
+     output_asm_insn ("lwx  \t%1,%y2,r0", operands);
+     output_asm_insn ("addic\t%8,r0,0", operands);
+     output_asm_insn ("bnei \t%8,.-8", operands);
+-    output_asm_insn ("cmp  \t%0,%1,%3", operands);
+-    output_asm_insn ("bnei \t%0,.+16", operands);
++    output_asm_insn ("cmp  \t%8,%1,%3", operands);
++    output_asm_insn ("bnei \t%8,.+20", operands);
+     output_asm_insn ("swx  \t%4,%y2,r0", operands);
+     output_asm_insn ("addic\t%8,r0,0", operands);
+     output_asm_insn ("bnei \t%8,.-28", operands);
++    output_asm_insn ("addi \t%0,r0,1", operands);
+     return "";
+   }
+ )
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
new file mode 100644
index 00000000..b9ba239f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -0,0 +1,33 @@
+From 4e4409f10b450ec9254e69445ffeb8d116906d16 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:50:17 +0530
+Subject: [PATCH 11/63] [Patch, microblaze]: Fix the Microblaze crash with
+ msmall-divides flag Compiler is crashing when we use msmall-divides and
+ mxl-barrel-shift flag. This is because when use above flags
+ microblaze_expand_divide function will be called for division operation. In
+ microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't
+ have subreg register due to this compiler was crashing. Changed the logic to
+ avoid sub_reg call
+
+Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 55c1bec..ae45038 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3715,8 +3715,7 @@ microblaze_expand_divide (rtx operands[])
+   mem_rtx = gen_rtx_MEM (QImode,
+                             gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
+ 
+-  insn = emit_insn (gen_movqi (regqi, mem_rtx)); 
+-  insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
++  insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+   JUMP_LABEL (jump) = div_end_label;
+   LABEL_NUSES (div_end_label) = 1; 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
new file mode 100644
index 00000000..fc47bae6
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -0,0 +1,48 @@
+From 6dbeb53f0185dd587ece39d624d193768633a7ab Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:52:56 +0530
+Subject: [PATCH 12/63] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
+ ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
+ optimization is used. lshrsi3_with_size_opt is being removed as it has
+ conflicts with unsigned int variables
+
+Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7a40c53..3d2636e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1508,6 +1508,27 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++(define_insn "*ashrsi3_with_size_opt"
++  [(set (match_operand:SI 0 "register_operand" "=&d")
++       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
++                   (match_operand:SI 2 "immediate_operand" "I")))]
++  "(INTVAL (operands[2]) > 5 && optimize_size)"
++  {
++    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("ori\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addik\t%3,%3,-1", operands);
++    output_asm_insn ("bneid\t%3,.-4", operands);
++    return "sra\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "SI")
++  (set_attr "length"  "20")]
++)
++
+ (define_insn "*ashrsi_inline"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
new file mode 100644
index 00000000..3b4b4c70
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch
@@ -0,0 +1,41 @@
+From 53ab5a3fec283aeb9d2efeb632d423b774192e65 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 17:50:03 +0530
+Subject: [PATCH 13/63] [Patch, microblaze]: Fixed missing save of r18 in
+ fast_interrupt. Register 18 is used as a clobber register, and must be stored
+ when entering a fast_interrupt. Before this fix, register 18 was only saved
+ if it was used directly in the interrupt function.
+
+However, if the fast_interrupt function called a function that used
+r18, the register would not be saved, and thus be mangled
+upon returning from the interrupt.
+
+Changelog
+
+2014-02-27  Klaus Petersen <klauspetersen@gmail.com>
+
+ * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
+   microblaze_must_save_register.
+
+Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index ae45038..c834b49 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2043,7 +2043,7 @@ microblaze_must_save_register (int regno)
+     {
+       if (df_regs_ever_live_p (regno) 
+ 	  || regno == MB_ABI_MSR_SAVE_REG
+-	  || (interrupt_handler
++	  || ((interrupt_handler || fast_interrupt)
+               && (regno == MB_ABI_ASM_TEMP_REGNUM
+ 	          || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
+ 	return 1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
new file mode 100644
index 00000000..889a1e69
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -0,0 +1,26 @@
+From cbf1854e3569122ee1143e6716ff68275c26aced Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 10:57:19 +0530
+Subject: [PATCH 14/63] [Patch, microblaze]: Use bralid for profiler calls
+ Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index fa0806e..0a435b8 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -486,7 +486,7 @@ typedef struct microblaze_args
+ 
+ #define FUNCTION_PROFILER(FILE, LABELNO) { \
+   {                                        \
+-    fprintf (FILE, "\tbrki\tr16,_mcount\n");           \
++    fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n");         \
+   }                                                    \
+  }
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0015-Patch-microblaze-Disable-fivopts-by-default.patch
new file mode 100644
index 00000000..0ada80eb
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0015-Patch-microblaze-Disable-fivopts-by-default.patch
@@ -0,0 +1,42 @@
+From 604cae83ce9d2942568178966f69614acbbcbefd Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 11:10:21 +0530
+Subject: [PATCH 15/63] [Patch, microblaze]: Disable fivopts by default Turn
+ off ivopts by default. Interferes with cse.
+
+Changelog
+
+2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+ * gcc/common/config/microblaze/microblaze-common.c
+   (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index c30bdef..9b6ef21 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -24,6 +24,15 @@
+ #include "common/common-target.h"
+ #include "common/common-target-def.h"
+ 
++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
++static const struct default_options microblaze_option_optimization_table[] =
++  {
++    /* Turn off ivopts by default. It messes up cse. */
++    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
++    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
++    { OPT_LEVELS_NONE, 0, NULL, 0 }
++  };
++
+ #undef TARGET_DEFAULT_TARGET_FLAGS
+ #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch
new file mode 100644
index 00000000..87bc1668
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0016-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -0,0 +1,160 @@
+From 14ddb3217fbb84c48903124ec6a3614b4707630d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 17:36:16 +0530
+Subject: [PATCH 16/63] [Patch, microblaze]: Removed moddi3 routinue Using the
+ default moddi3 function as the existing implementation has many bugs
+
+Signed-off-by:Nagaraju <nmekala@xilix.com>
+
+Conflicts:
+	libgcc/config/microblaze/moddi3.S
+---
+ libgcc/config/microblaze/moddi3.S     | 121 ----------------------------------
+ libgcc/config/microblaze/t-microblaze |   3 +-
+ 2 files changed, 1 insertion(+), 123 deletions(-)
+ delete mode 100644 libgcc/config/microblaze/moddi3.S
+
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+deleted file mode 100644
+index abfe4fc..0000000
+--- a/libgcc/config/microblaze/moddi3.S
++++ /dev/null
+@@ -1,121 +0,0 @@
+-###################################
+-# 
+-#  Copyright (C) 2009-2019 Free Software Foundation, Inc.
+-#
+-#  Contributed by Michael Eager <eager@eagercon.com>.
+-#
+-#  This file is free software; you can redistribute it and/or modify it
+-#  under the terms of the GNU General Public License as published by the
+-#  Free Software Foundation; either version 3, or (at your option) any
+-#  later version.
+-#
+-#  GCC is distributed in the hope that it will be useful, but WITHOUT
+-#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+-#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+-#  License for more details.
+-#
+-#  Under Section 7 of GPL version 3, you are granted additional
+-#  permissions described in the GCC Runtime Library Exception, version
+-#  3.1, as published by the Free Software Foundation.
+-#
+-#  You should have received a copy of the GNU General Public License and
+-#  a copy of the GCC Runtime Library Exception along with this program;
+-#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+-#  <http://www.gnu.org/licenses/>. 
+-#
+-#  modsi3.S
+-# 
+-#  modulo operation for 64 bit integers.
+-# 
+-#######################################
+-
+-
+-/* An executable stack is *not* required for these functions.  */
+-#ifdef __linux__
+-.section .note.GNU-stack,"",%progbits
+-.previous
+-#endif
+-
+-	.globl	__moddi3
+-	.ent	__moddi3
+-__moddi3:
+-	.frame	r1,0,r15	
+-
+-#Change the stack pointer value and Save callee saved regs
+-	addik	r1,r1,-24
+-	swi	r25,r1,0
+-	swi	r26,r1,4
+-	swi	r27,r1,8	# used for sign
+-	swi	r28,r1,12	# used for loop count
+-	swi	r29,r1,16	# Used for div value High
+-	swi	r30,r1,20	# Used for div value Low
+-
+-#Check for Zero Value in the divisor/dividend
+-	OR	r9,r5,r6			# Check for the op1 being zero
+-	BEQID	r9,$LaResult_Is_Zero		# Result is zero
+-	OR	r9,r7,r8			# Check for the dividend being zero
+-	BEQI	r9,$LaDiv_By_Zero	        # Div_by_Zero   # Division Error
+-	BGEId	r5,$La1_Pos 
+-	XOR	r27,r5,r7			# Get the sign of the result
+-	RSUBI	r6,r6,0				# Make dividend positive
+-	RSUBIC	r5,r5,0				# Make dividend positive
+-$La1_Pos:
+-	BGEI	r7,$La2_Pos
+-	RSUBI	r8,r8,0				# Make Divisor Positive
+-	RSUBIC	r9,r9,0				# Make Divisor Positive
+-$La2_Pos:
+-	ADDIK	r4,r0,0				# Clear mod low
+-	ADDIK	r3,r0,0                	        # Clear mod high
+-	ADDIK	r29,r0,0			# clear div high
+-	ADDIK	r30,r0,0			# clear div low
+-	ADDIK	r28,r0,64			# Initialize the loop count
+-   # First part try to find the first '1' in the r5/r6
+-$LaDIV1:
+-	ADD	r6,r6,r6
+-	ADDC	r5,r5,r5			# left shift logical r5
+-	BGEID	r5,$LaDIV1			
+-	ADDIK	r28,r28,-1
+-$LaDIV2:
+-	ADD	r6,r6,r6
+-	ADDC	r5,r5,r5	# left shift logical r5/r6 get the '1' into the Carry
+-	ADDC	r4,r4,r4	# Move that bit into the Mod register
+-	ADDC	r3,r3,r3	# Move carry into high mod register
+-	rsub	r18,r7,r3	# Compare the High Parts of Mod and Divisor
+-	bnei	r18,$L_High_EQ
+-	rsub	r18,r6,r4	# Compare Low Parts only if Mod[h] == Divisor[h]
+-$L_High_EQ:	
+-	rSUB	r26,r8,r4	# Subtract divisor[L] from Mod[L]
+-	rsubc	r25,r7,r3	# Subtract divisor[H] from Mod[H]
+-	BLTi	r25,$LaMOD_TOO_SMALL
+-	OR	r3,r0,r25	# move r25 to mod [h]
+-	OR	r4,r0,r26	# move r26 to mod [l]
+-	ADDI	r30,r30,1
+-	ADDC	r29,r29,r0
+-$LaMOD_TOO_SMALL:
+-	ADDIK	r28,r28,-1
+-	BEQi	r28,$LaLOOP_END
+-	ADD	r30,r30,r30		# Shift in the '1' into div [low]
+-	ADDC	r29,r29,r29		# Move the carry generated into high
+-	BRI	$LaDIV2   # Div2
+-$LaLOOP_END:
+-	BGEI	r27,$LaRETURN_HERE
+-	rsubi	r30,r30,0
+-	rsubc	r29,r29,r0
+-	BRI	$LaRETURN_HERE
+-$LaDiv_By_Zero:
+-$LaResult_Is_Zero:
+-	or	r29,r0,r0	# set result to 0 [High]
+-	or	r30,r0,r0	# set result to 0 [Low]
+-$LaRETURN_HERE:
+-# Restore values of CSRs and that of r29 and the divisor and the dividend
+-	
+-	lwi	r25,r1,0
+-	lwi	r26,r1,4
+-	lwi	r27,r1,8
+-	lwi	r28,r1,12
+-	lwi	r29,r1,16
+-	lwi	r30,r1,20
+-	rtsd	r15,8
+-	addik r1,r1,24
+-        .end __moddi3
+-	
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 96959f0..8d954a4 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,8 +1,7 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
+-        $(srcdir)/config/microblaze/moddi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+         $(srcdir)/config/microblaze/muldi3_hard.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
new file mode 100644
index 00000000..ca1c2d1c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -0,0 +1,101 @@
+From 032e50c1b267306338cff4d136db88f08350de72 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 14:41:58 +0530
+Subject: [PATCH 17/63] [Patch, microblaze]: Add INIT_PRIORITY support Added
+ TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
+
+These macros allows users to control the order of initialization
+of objects defined at namespace scope with the init_priority
+attribute by specifying a relative priority, a constant integral
+expression currently bounded between 101 and 65535 inclusive.
+
+Lower numbers indicate a higher priority.
+
+Changelog
+
+2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
+   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
+   TARGET_ASM_DESTRUCTOR.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c834b49..c54b96b 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2642,6 +2642,53 @@ print_operand_address (FILE * file, rtx addr)
+     }
+ }
+ 
++/* Output an element in the table of global constructors. */
++void
++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
++{
++    const char *section = ".ctors";
++    char buf[16];
++
++    if (priority != DEFAULT_INIT_PRIORITY)
++      {
++        sprintf (buf, ".ctors.%.5u",
++                /* Invert the numbering so the linker puts us in the proper
++                   order; constructors are run from right to left, and the
++                   linker sorts in increasing order.  */
++                MAX_INIT_PRIORITY - priority);
++        section = buf;
++      }
++
++    switch_to_section (get_section (section, 0, NULL));
++    assemble_align (POINTER_SIZE);
++    fputs ("\t.word\t", asm_out_file);
++    output_addr_const (asm_out_file, symbol);
++    fputs ("\n", asm_out_file);
++}
++
++/* Output an element in the table of global destructors. */
++void
++microblaze_asm_destructor (rtx symbol, int priority)
++{
++    const char *section = ".dtors";
++    char buf[16];
++    if (priority != DEFAULT_INIT_PRIORITY)
++      {
++        sprintf (buf, ".dtors.%.5u",
++                 /* Invert the numbering so the linker puts us in the proper
++                    order; constructors are run from right to left, and the
++                    linker sorts in increasing order.  */
++                MAX_INIT_PRIORITY - priority);
++        section = buf;
++      }
++
++    switch_to_section (get_section (section, 0, NULL));
++    assemble_align (POINTER_SIZE);
++    fputs ("\t.word\t", asm_out_file);
++    output_addr_const (asm_out_file, symbol);
++    fputs ("\n", asm_out_file);
++}
++
+ /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
+    is used, so that we don't emit an .extern for it in 
+    microblaze_asm_file_end.  */
+@@ -3981,6 +4028,12 @@ microblaze_starting_frame_offset (void)
+ #undef TARGET_ATTRIBUTE_TABLE
+ #define TARGET_ATTRIBUTE_TABLE          microblaze_attribute_table
+ 
++#undef TARGET_ASM_CONSTRUCTOR
++#define TARGET_ASM_CONSTRUCTOR          microblaze_asm_constructor
++
++#undef TARGET_ASM_DESTRUCTOR
++#define TARGET_ASM_DESTRUCTOR           microblaze_asm_destructor
++
+ #undef TARGET_IN_SMALL_DATA_P
+ #define TARGET_IN_SMALL_DATA_P          microblaze_elf_in_small_data_p
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
new file mode 100644
index 00000000..de35f286
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0018-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -0,0 +1,81 @@
+From 6db9d068e32a424ac04c27e963d1e58cb3ef8bdf Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 15:23:57 +0530
+Subject: [PATCH 18/63] [Patch, microblaze]: Add optimized lshrsi3 When barrel
+ shifter is not present, the immediate value is greater than #5 and
+ optimization is -OS, the compiler will generate shift operation using loop.
+
+Changelog
+
+2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
+
+ChangeLog/testsuite
+
+2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
+
+Signed-off-by:Nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.md                 | 21 +++++++++++++++++++++
+ .../gcc.target/microblaze/others/lshrsi_Os_1.c      | 13 +++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3d2636e..aa2eda3 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1618,6 +1618,27 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++(define_insn "*lshrsi3_with_size_opt"
++  [(set (match_operand:SI 0 "register_operand" "=&d")
++       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
++                   (match_operand:SI 2 "immediate_operand" "I")))]
++  "(INTVAL (operands[2]) > 5 && optimize_size)"
++  {
++    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("ori\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addik\t%3,%3,-1", operands);
++    output_asm_insn ("bneid\t%3,.-4", operands);
++    return "srl\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "SI")
++  (set_attr "length"  "20")]
++)
++
+ (define_insn "*lshrsi_inline"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+new file mode 100644
+index 0000000..32a3be7
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-Os -mno-xl-barrel-shift" } */
++
++void testfunc(void)
++{
++    unsigned volatile int z = 8192;
++    z >>= 8;
++}
++/* { dg-final { scan-assembler-not "\bsrli" } } */
++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch
new file mode 100644
index 00000000..dc9b61cf
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0019-Patch-microblaze-Modified-trap-instruction.patch
@@ -0,0 +1,29 @@
+From 614bacc058b94c7b12cd40fde1b19b4709870f3b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 15:42:15 +0530
+Subject: [PATCH 19/63] [Patch, microblaze]: Modified trap instruction The
+ instruction was wrongly written to brki r0,-1 it should be bri r0. Modified
+ with the correct instruction
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+              :Ajit Agarwal  <ajitkum@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.md | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index aa2eda3..3c80760 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2348,7 +2348,7 @@
+ (define_insn "trap"
+   [(trap_if (const_int 1) (const_int 0))]
+   ""
+-  "brki\tr0,-1"
++  "bri\t0"
+  [(set_attr "type" "trap")]
+ )
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
new file mode 100644
index 00000000..b60a4e95
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -0,0 +1,206 @@
+From 372bbc75146166df9b82ca5e8f236971b7cef16e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 16:42:44 +0530
+Subject: [PATCH 20/63] [Patch, microblaze]: Reducing Stack space for arguments
+ Currently in Microblaze target stack space for arguments in register is being
+ allocated even if there are no arguments in the function. This patch will
+ optimize the extra 24 bytes that are being allocated.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+              :Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2015-04-17 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+    *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
+    *microblaze.c (REG_PARM_STACK_SPACE): Modify
+---
+ gcc/config/microblaze/microblaze-protos.h |   1 +
+ gcc/config/microblaze/microblaze.c        | 134 +++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.h        |   4 +-
+ 3 files changed, 136 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index 1f5ca80..6647cbc 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx);
+ extern int label_mentioned_p (rtx);
+ extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
+ extern void microblaze_eh_return (rtx op0);
++int  microblaze_reg_parm_stack_space(tree fun);
+ #endif  /* RTX_CODE */
+ 
+ /* Declare functions in microblaze-c.c.  */
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c54b96b..0ce9d13 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2065,6 +2065,138 @@ microblaze_must_save_register (int regno)
+   return 0;
+ }
+ 
++static bool
++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
++{
++  enum machine_mode mode;
++  int unsignedp;
++  rtx entry_parm;
++
++  /* Catch errors.  */
++  if (type == NULL || type == error_mark_node)
++    return true;
++
++  if (TREE_CODE (type) == POINTER_TYPE)
++    return true;
++
++  /* Handle types with no storage requirement.  */
++  if (TYPE_MODE (type) == VOIDmode)
++    return false;
++
++   /* Handle complex types.  */
++  if (TREE_CODE (type) == COMPLEX_TYPE)
++    return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
++             || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
++
++  /* Handle transparent aggregates.  */
++ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
++     && TYPE_TRANSPARENT_AGGR (type))
++  type = TREE_TYPE (first_field (type));
++
++  /* See if this arg was passed by invisible reference.  */
++ if (pass_by_reference (get_cumulative_args (args_so_far),
++                        TYPE_MODE (type), type, true))
++    type = build_pointer_type (type);
++
++    /* Find mode as it is passed by the ABI.  */
++    unsignedp = TYPE_UNSIGNED (type);
++    mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
++
++/* If there is no incoming register, we need a stack.  */
++ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
++ if (entry_parm == NULL)
++    return true;
++
++ /* Likewise if we need to pass both in registers and on the stack.  */
++ if (GET_CODE (entry_parm) == PARALLEL
++     && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
++   return true;
++
++ /* Also true if we're partially in registers and partially not.  */
++  if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
++     return true;
++
++ /* Update info on where next arg arrives in registers.  */
++ microblaze_function_arg_advance (args_so_far, mode, type, true);
++ return false;
++ }
++
++static bool
++microblaze_function_parms_need_stack (tree fun, bool incoming)
++{
++  tree fntype, result;
++  CUMULATIVE_ARGS args_so_far_v;
++  cumulative_args_t args_so_far;
++  int num_of_args = 0;
++
++  /* Must be a libcall, all of which only use reg parms.  */
++  if (!fun)
++    return true;
++
++  fntype = fun;
++  if (!TYPE_P (fun))
++    fntype = TREE_TYPE (fun);
++
++  /* Varargs functions need the parameter save area.  */
++  if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
++    return true;
++
++  INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
++  args_so_far = pack_cumulative_args (&args_so_far_v);
++
++  /* When incoming, we will have been passed the function decl.
++   *      It is necessary to use the decl to handle K&R style functions,
++   *      where TYPE_ARG_TYPES may not be available.  */
++  if (incoming)
++    {
++      gcc_assert (DECL_P (fun));
++      result = DECL_RESULT (fun);
++    }
++  else
++    result = TREE_TYPE (fntype);
++
++  if (result && aggregate_value_p (result, fntype))
++    {
++      if (!TYPE_P (result))
++        result = build_pointer_type (result);
++        microblaze_parm_needs_stack (args_so_far, result);
++    }
++
++  if (incoming)
++    {
++      tree parm;
++      for (parm = DECL_ARGUMENTS (fun);
++           parm && parm != void_list_node;
++           parm = TREE_CHAIN (parm))
++         if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
++           return true;
++    }
++  else
++    {
++      function_args_iterator args_iter;
++      tree arg_type;
++
++      FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++      {
++        num_of_args++;
++        if (microblaze_parm_needs_stack (args_so_far, arg_type))
++         return true;
++      }
++    }
++
++  if (num_of_args > 3) return true;
++
++  return false;
++}
++
++int  microblaze_reg_parm_stack_space(tree fun)
++{
++  if (microblaze_function_parms_need_stack (fun,false))
++    return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
++  else
++    return 0;
++}
++
+ /* Return the bytes needed to compute the frame pointer from the current
+    stack pointer.
+ 
+@@ -3411,7 +3543,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+   emit_insn (gen_indirect_jump (temp2));
+ 
+   /* Run just enough of rest_of_compilation.  This sequence was
+-     "borrowed" from rs6000.c.  */
++     "borrowed" from microblaze.c.  */
+   insn = get_insns ();
+   shorten_branches (insn);
+   final_start_function (insn, file, 1);
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 0a435b8..346e47b 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
+ 
+ #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
+ 
+-#define REG_PARM_STACK_SPACE(FNDECL)  		(MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
++#define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
+ 
+-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)	1
++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
+ 
+ #define STACK_BOUNDARY				32
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
new file mode 100644
index 00000000..c79f9552
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0021-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -0,0 +1,159 @@
+From 1c226901aec38e2e824177418dcd82b6cd49ffca Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 17:04:37 +0530
+Subject: [PATCH 21/63] [Patch, microblaze]: Add cbranchsi4_reg This patch
+ optimizes the generation of  pcmpne/pcmpeq instruction if the compare
+ instruction has no immediate values.For the immediate values the xor
+ instruction is generated
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
+Signed-off-by: Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2015-01-13 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+  *microblaze.md (cbranchsi4_reg): New
+  *microblaze.c (microblaze_expand_conditional_branch_reg): New
+
+Conflicts:
+
+	gcc/config/microblaze/microblaze-protos.h
+---
+ gcc/config/microblaze/microblaze-protos.h                 |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c           |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c           |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c           |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c           |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c          | 14 +++++++-------
+ gcc/testsuite/gcc.target/microblaze/isa/vanilla.c         | 12 ++++++------
+ gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c |  2 +-
+ 8 files changed, 19 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index 6647cbc..bdc9b69 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
+ extern bool microblaze_expand_move (machine_mode, rtx *);
+ extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
+ extern void microblaze_expand_divide (rtx *);
+-extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_sf (rtx *); 
+ extern int microblaze_can_use_return_insn (void);
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
+index 4041a24..ccc6a46 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 <= f3) 
+-        print ("le");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
+index 3902b83..1dd5fe6 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 < f3) 
+-        print ("lt");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
+index 8555974..d6f80fb 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 == f3) 
+-        print ("eq");
++        f1 = f2 + f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
+index 79cc5f9..d117724 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
+@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
+   /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if(f1==f2 && f1<=f3)
+-        print ("f1 eq f2 && f1 le f3");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
+index ebfb170..7582297 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
+@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
+ void float_func () 
+ {
+     /* { dg-final { scan-assembler-not "fcmp" } } */
+-    if (f2 <= f3) 
+-        print ("le");
++    if (f2 <= f3)
++        f1 = f3;
+     else if (f2 == f3) 
+-        print ("eq");
++        f1 = f3;
+     else if (f2 < f3) 
+-        print ("lt");
++        f1 = f3;
+     else if (f2 > f3) 
+-        print ("gt");
++        f1 = f3;
+     else if (f2 >= f3) 
+-        print ("ge");
++        f1 = f3;
+     else if (f2 != f3) 
+-        print ("ne");
++        f1 = f3;
+     
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
+index 1d6ba80..532c035 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
+@@ -74,16 +74,16 @@ void float_cmp_func ()
+ {
+     /* { dg-final { scan-assembler-not "fcmp" } } */
+     if (f2 <= f3) 
+-        print ("le");
++        f1 = f3;
+     else if (f2 == f3) 
+-        print ("eq");
++        f1 = f3;
+     else if (f2 < f3) 
+-        print ("lt");
++        f1 = f3;
+     else if (f2 > f3) 
+-        print ("gt");
++        f1 = f3;
+     else if (f2 >= f3) 
+-        print ("ge");
++        f1 = f3;
+     else if (f2 != f3) 
+-        print ("ne");
++        f1 = f3;
+     
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
+index fdcde1f..580b4db 100644
+--- a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
++++ b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
+@@ -5,4 +5,4 @@ void trap ()
+   __builtin_trap ();
+ }
+ 
+-/* { dg-final { scan-assembler "brki\tr0,-1" } } */
+\ No newline at end of file
++/* { dg-final { scan-assembler "bri\t0" } } */
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 00000000..c3822d06
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,58 @@
+From 791d65feae4f3cab47833579bc6f523e54194cbd Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 17:11:04 +0530
+Subject: [PATCH 22/63] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
+ The changes are made in the patch for the inline expansion of the fsqrt
+ builtin with fqrt instruction. The sqrt math function takes double as
+ argument and return double as argument. The pattern is selected while
+ expanding the unary op through expand_unop which passes DFmode and the DFmode
+ pattern was not there returning zero. Thus the sqrt math function is not
+ inlined and expanded. The pattern with DFmode argument is added. Also the
+ source and destination argument is not same the DF through two different
+ consecutive registers with lower 32 bit is the argument passed to sqrt and
+ the higher 32 bit is zero. If the source and destinations are different the
+ DFmode 64 bits registers is not set properly giving the problem in runtime.
+ Such changes are taken care in the implementation of the pattern for DFmode
+ for inline expansion of the sqrt.
+
+ChangeLog:
+2015-06-16  Ajit Agarwal  <ajitkum@xilinx.com>
+            Nagaraju Mekala <nmekala@xilinx.com>
+
+	* config/microblaze/microblaze.md (sqrtdf2): New
+	pattern.
+
+Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
+              Nagaraju Mekala nmekala@xilinx.com
+---
+ gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3c80760..1fb5582 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -451,6 +451,20 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "sqrtdf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
++  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
++  {
++    if (REGNO (operands[0]) == REGNO (operands[1]))
++      return "fsqrt\t%0,%1";
++    else
++      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
++  }
++  [(set_attr "type"     "fsqrt")
++   (set_attr "mode"      "SF")
++   (set_attr "length"    "4")])
++
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
new file mode 100644
index 00000000..a314170f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
@@ -0,0 +1,47 @@
+From 2c4a1d46e4f1b2342f899d6741d09dbf7cc87aa2 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 17:33:31 +0530
+Subject: [PATCH 23/63] [Patch] OPT: Update heuristics for loop-invariant for
+ address arithme. .tic.
+
+The changes are made in the patch to update the heuristics
+for loop invariant for address arithmetic. The heuristics is
+changed to calculate the estimated register pressure cost when
+ira based register pressure is not enabled. The estimated
+register pressure cost modifies the existing calculation cost
+associated to perform the Loop invariant code motion for address
+arithmetic.
+
+ChangeLog:
+2015-06-17  Ajit Agarwal  <ajitkum@xilinx.com>
+            Nagaraju Mekala <nmekala@xilinx.com>
+
+	* loop-invariant.c (gain_for_invariant): update the
+	heuristics for estimate_reg_pressure_cost.
+
+Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
+              Nagaraju Mekala nmekala@xilinx.com
+---
+ gcc/loop-invariant.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
+index b880ead..fd7a019 100644
+--- a/gcc/loop-invariant.c
++++ b/gcc/loop-invariant.c
+@@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+ 
+   if (! flag_ira_loop_pressure)
+     {
+-      size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
+-					       regs_used, speed, call_p)
+-		   - estimate_reg_pressure_cost (new_regs[0],
+-						 regs_used, speed, call_p));
++      size_cost = estimate_reg_pressure_cost (regs_needed[0],
++					       regs_used, speed, call_p);
+     }
+   else if (ret < 0)
+     return -1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
new file mode 100644
index 00000000..a786ba09
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -0,0 +1,63 @@
+From c2b64f2f7a06231d8da0a53c6761939583ac56da Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 18:07:24 +0530
+Subject: [PATCH 24/63] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
+ insn definitions Change adddi3 to handle DI immediates as the second operand,
+ this requires modification to the output template however reduces the need to
+ specify seperate templates for 16-bit positive/negative immediate operands.
+ The use of 32-bit immediates for the addi and addic instructions is handled
+ by the assembler, which will emit the imm instructions when required. This
+ conveniently handles the optimizable cases where the immediate constant value
+ does not need the higher half words of the operands upper/lower words.
+
+Change the constraints of the subdi3 instruction definition such that it
+does not match the second operand as an immediate value. This is because
+there is no definition to handle this case nor is it possible to
+implement purely with instructions as microblaze does not provide an
+instruction to perform a forward arithmetic subtraction (it only
+provides reverse 'rD = IMM - rA').
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+---
+ gcc/config/microblaze/microblaze.md | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 1fb5582..216219b 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -502,17 +502,16 @@
+ ;; Adding 2 DI operands in register or reg/imm
+ 
+ (define_insn "adddi3"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+-	(plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
+-		 (match_operand:DI 2 "arith_operand32" "d,P,N")))]
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
++		 (match_operand:DI 2 "arith_operand" "d,i")))]
+   ""
+   "@
+   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+-  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
+-  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
++  addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+   [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+-  (set_attr "length"	"8,8,12")])
++  (set_attr "length"	"8,8")])
+ 
+ ;;----------------------------------------------------------------
+ ;; Subtraction
+@@ -549,7 +548,7 @@
+ (define_insn "subdi3"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+-		  (match_operand:DI 2 "arith_operand32" "d")))]
++		  (match_operand:DI 2 "register_operand" "d")))]
+   ""
+   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+   [(set_attr "type"	"darith")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
new file mode 100644
index 00000000..98310b36
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,72 @@
+From c7e5c253b1e7800bc5ec8cc69850118ed938e22f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 18:18:41 +0530
+Subject: [PATCH 25/63] [Patch, microblaze]: Update ashlsi3 & movsf patterns
+ This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
+ of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
+ patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
+ instruction doesn't support so using gen_int_mode function
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+              :Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2016-01-07 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+  *microblaze.md (ashlsi3_with_mul_nodelay,
+                  ashlsi3_with_mul_delay,
+                  movsf_internal):
+    Updated the patterns to use gen_int_mode function
+  *microblaze.c (print_operand):
+     updated the 'F' case to use "unsinged int" instead
+     of HOST_WIDE_INT_PRINT_HEX
+---
+ gcc/config/microblaze/microblaze.c  |  2 +-
+ gcc/config/microblaze/microblaze.md | 10 ++++++++--
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 0ce9d13..7669668 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2608,7 +2608,7 @@ print_operand (FILE * file, rtx op, int letter)
+ 	  unsigned long value_long;
+ 	  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
+ 				       value_long);
+-	  fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
++	  fprintf (file, "0x%08x", (unsigned int) value_long);
+ 	}
+       else
+ 	{
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 216219b..4bc209c 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1368,7 +1368,10 @@
+                    (match_operand:SI 2 "immediate_operand" "I")))] 
+   "!TARGET_SOFT_MUL 
+    && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
+-  "muli\t%0,%1,%m2"
++  {
++    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++    return "muli\t%0,%1,%2";
++  }
+   ;; This MUL will not generate an imm. Can go into a delay slot.
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+@@ -1380,7 +1383,10 @@
+ 	(ashift:SI (match_operand:SI 1 "register_operand"  "d")
+                    (match_operand:SI 2 "immediate_operand" "I")))] 
+   "!TARGET_SOFT_MUL"
+-  "muli\t%0,%1,%m2"
++  {
++    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++    return "muli\t%0,%1,%2";
++  }
+   ;; This MUL will generate an IMM. Cannot go into a delay slot
+   [(set_attr "type"	"no_delay_arith")
+    (set_attr "mode"	"SI")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 00000000..ba80ce45
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,193 @@
+From c3b633b0ee8d228a7d70a02b574822aba9a0fd93 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 19:50:34 +0530
+Subject: [PATCH 26/63] [Patch, microblaze]: 8-stage pipeline for microblaze
+ This patch adds the support for the 8-stage pipeline. The new 8-stage
+ pipeline reduces the latencies of float & integer division drastically
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
+
+  *microblaze.md (define_automaton mbpipe_8): New
+
+  *microblaze.c (microblaze_option_override): Update
+    Updated the logic to generate only when MB version is 10.0
+
+  *microblaze.h (pipeline_type): Update
+          Update the enum with MICROBLAZE_PIPE_8
+
+  *microblaze.opt (mxl-frequency): New
+         New flag added for 8-stage pipeline
+---
+ gcc/config/microblaze/microblaze.c   | 13 ++++++
+ gcc/config/microblaze/microblaze.h   |  3 +-
+ gcc/config/microblaze/microblaze.md  | 79 +++++++++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt |  4 ++
+ 4 files changed, 96 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 7669668..ae7d5dd 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1848,6 +1848,19 @@ microblaze_option_override (void)
+ 		   "%<-mcpu=v8.30.a%>");
+         TARGET_REORDER = 0;
+     }
++  ver = ver_int - microblaze_version_to_int("v10.0");
++  if (ver < 0)
++    {
++        if (TARGET_AREA_OPTIMIZED_2)
++          warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
++    }
++  else
++    {
++        if (TARGET_AREA_OPTIMIZED_2)
++          microblaze_pipe = MICROBLAZE_PIPE_8;
++        if (TARGET_BARREL_SHIFT)
++          microblaze_has_bitfield = 1;
++    }
+ 
+   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+     error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 346e47b..bf7f3b4 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -27,7 +27,8 @@
+ enum pipeline_type
+ {
+   MICROBLAZE_PIPE_3 = 0,
+-  MICROBLAZE_PIPE_5 = 1
++  MICROBLAZE_PIPE_5 = 1,
++  MICROBLAZE_PIPE_8 = 2
+ };
+ 
+ #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4bc209c..b7c16ac 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -35,6 +35,7 @@
+   (R_GOT      20)       ;; GOT ptr reg
+   (MB_PIPE_3   0)       ;; Microblaze 3-stage pipeline 
+   (MB_PIPE_5   1)       ;; Microblaze 5-stage pipeline 
++  (MB_PIPE_8   2)       ;; Microblaze 8-stage pipeline
+   (UNSPEC_SET_GOT       101)    ;;
+   (UNSPEC_GOTOFF        102)    ;; GOT offset
+   (UNSPEC_PLT           103)    ;; jump table
+@@ -82,7 +83,7 @@
+ ;; bshift 	Shift operations
+ 
+ (define_attr "type"
+-  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
++  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
+   (const_string "unknown"))
+ 
+ ;; Main data type used by the insn
+@@ -224,6 +225,80 @@
+ ;;-----------------------------------------------------------------
+ 
+ 
++
++;;----------------------------------------------------------------
++;; Microblaze 8-stage pipeline description (v10.0 and later)
++;;----------------------------------------------------------------
++
++(define_automaton   "mbpipe_8")
++(define_cpu_unit    "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
++
++(define_insn_reservation "mb8-integer" 1
++  (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-special-move" 2
++  (and (eq_attr "type" "move")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu*2,mb8_wb")
++
++(define_insn_reservation "mb8-mem-load" 3
++  (and (eq_attr "type" "load,no_delay_load")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mem-store" 1
++  (and (eq_attr "type" "store,no_delay_store")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mul" 3
++  (and (eq_attr "type" "imul,no_delay_imul")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
++
++(define_insn_reservation "mb8-div" 30
++  (and (eq_attr "type" "idiv")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++    "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
++
++(define_insn_reservation "mb8-bs" 2
++  (and (eq_attr "type" "bshift")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++   "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-add-sub-mul" 1
++  (and (eq_attr "type" "fadd,frsub,fmul")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcmp" 3
++  (and (eq_attr "type" "fcmp")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-div" 24
++  (and (eq_attr "type" "fdiv")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-sqrt" 23
++  (and (eq_attr "type" "fsqrt")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcvt" 1
++  (and (eq_attr "type" "fcvt")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fint" 2
++  (and (eq_attr "type" "fint")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++
+ ;;----------------------------------------------------------------
+ ;; Microblaze 5-stage pipeline description (v5.00.a and later)
+ ;;----------------------------------------------------------------                 
+@@ -470,7 +545,7 @@
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+   "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "fint\t%0,%1"
+-  [(set_attr "type"     "fcvt")
++  [(set_attr "type"     "fint")
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index 2e46941..d23f376 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
+ 
+ mxl-mode-xilkernel
+ Target
++
++mxl-frequency
++Target Mask(AREA_OPTIMIZED_2)
++Use 8 stage pipeline (frequency optimization)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
new file mode 100644
index 00000000..330b5494
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch
@@ -0,0 +1,142 @@
+From 650cbdea7bc810e2bd0ebc5eb5647ed513498670 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 11:08:40 +0530
+Subject: [PATCH 27/63] [Patch,rtl Optimization]: Better register pressure
+ estimate for loop . .invariant code motion
+
+Calculate the loop liveness used for regs for calculating the register pressure
+in the cost estimation.  Loop liveness is based on the following properties.
+We only need to find the set of objects that are live at the birth or the header
+of the loop. We don't need to calculate the live through the loop by considering
+live in and live out of all the basic blocks of the loop. This is based on the
+point that the set of objects that are live-in at the birth or header of the loop
+will be live-in at every node in the loop.
+
+If a v live is out at the header of the loop then the variable is live-in at every node
+in the loop. To prove this, consider a loop L with header h such that the variable v
+defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i
+from the dominance property, i.e. h is strictly dominated by d. Furthermore, there
+exists a path from h to a use of v which does not go through d. For every node p in
+the loop, since the loop is strongly connected and node is a component of the CFG,
+there exists a path, consisting only of nodes of L from p to h. Concatenating these
+two paths proves that v is live-in and live-out of p.
+
+Calculate the live-out and live-in for the exit edge of the loop. This patch considers
+liveness for not only the loop latch but also the liveness outside the loops.
+
+ChangeLog:
+2016-01-22  Ajit Agarwal  <ajitkum@xilinx.com>
+
+	* loop-invariant.c
+	(find_invariants_to_move): Add the logic of regs_used based
+	on liveness.
+	* cfgloopanal.c
+	(estimate_reg_pressure_cost): Update the heuristics in presence
+	of call_p.
+
+Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
+---
+ gcc/cfgloopanal.c    |  4 +++-
+ gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++++++++-------------
+ 2 files changed, 50 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
+index 6dbe96f..ec5cba2 100644
+--- a/gcc/cfgloopanal.c
++++ b/gcc/cfgloopanal.c
+@@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
+   if (regs_needed + target_res_regs <= available_regs)
+     return 0;
+ 
+-  if (regs_needed <= available_regs)
++  if ((regs_needed <= available_regs)
++      || (call_p && (regs_needed <=
++          (available_regs + target_clobbered_regs))))
+     /* If we are close to running out of registers, try to preserve
+        them.  */
+     cost = target_reg_cost [speed] * n_new;
+diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
+index fd7a019..ad54297 100644
+--- a/gcc/loop-invariant.c
++++ b/gcc/loop-invariant.c
+@@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
+ 	size_cost = 0;
+     }
+ 
+-  return comp_cost - size_cost;
++  return comp_cost - size_cost + 1;
+ }
+ 
+ /* Finds invariant with best gain for moving.  Returns the gain, stores
+@@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p)
+     /* REGS_USED is actually never used when the flag is on.  */
+     regs_used = 0;
+   else
+-    /* We do not really do a good job in estimating number of
+-       registers used; we put some initial bound here to stand for
+-       induction variables etc.  that we do not detect.  */
++    /* The logic used in estimating the number of regs_used is changed.
++       Now it will be based on liveness of the loop. */
+     {
+-      unsigned int n_regs = DF_REG_SIZE (df);
+-
+-      regs_used = 2;
+-
+-      for (i = 0; i < n_regs; i++)
+-	{
+-	  if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i))
+-	    {
+-	      /* This is a value that is used but not changed inside loop.  */
+-	      regs_used++;
+-	    }
+-	}
++      int  i;
++      edge e;
++      vec<edge> edges;
++      bitmap_head regs_live;
++
++      bitmap_initialize (&regs_live, &reg_obstack);
++      edges = get_loop_exit_edges (curr_loop);
++
++      /* Loop liveness is based on the following properties.
++         We only need to find the set of objects that are live at the
++         birth or the header of the loop.
++         We don't need to calculate the live through the loop considering
++         live-in and live-out of all the basic blocks of the loop. This is
++         based on the point that the set of objects that are live-in at the
++         birth or header of the loop will be live-in at every block in the
++         loop.
++
++         If a v live out at the header of the loop then the variable is
++         live-in at every node in the Loop. To prove this, consider a loop
++         L with header h such that the variable v defined at d is live-in
++         at h. Since v is live at h, d is not part of L. This follows from
++         the dominance property, i.e. h is strictly dominated by d. Furthermore,
++         there exists a path from h to a use of v which does not go through d.
++         For every node of the loop, p, since the loop is strongly connected
++         component of the CFG, there exists a path, consisting only of nodes
++         of L from p to h. Concatenating these two paths prove that v is
++         live-in and live-out of p.  */
++
++       bitmap_ior_into (&regs_live, DF_LR_IN (curr_loop->header));
++       bitmap_ior_into (&regs_live, DF_LR_OUT (curr_loop->header));
++
++       /* Calculate the live-out and live-in for the exit edge of the loop.
++          This considers liveness for not only the loop latch but also the
++          liveness outside the loops.  */
++
++       FOR_EACH_VEC_ELT (edges, i, e)
++         {
++           bitmap_ior_into (&regs_live, DF_LR_OUT (e->src));
++           bitmap_ior_into (&regs_live, DF_LR_IN (e->dest));
++         }
++
++       regs_used = bitmap_count_bits (&regs_live) + 2;
++       bitmap_clear (&regs_live);
++       edges.release ();
+     }
+ 
+   if (! flag_ira_loop_pressure)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
new file mode 100644
index 00000000..b5ee2c8c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -0,0 +1,69 @@
+From 8f8c6cd35a2cf79449c0155fa865a665d730e541 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 11:25:48 +0530
+Subject: [PATCH 28/63] [Patch, microblaze]: Correct the const high double
+ immediate value With this patch the loading of the DI mode immediate values
+ will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
+ functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
+ of the unsigned long long constants also
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+ *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
+        REAL_VALUE_TO_TARGET_DOUBLE
+ *long.c (new): Added new testcase
+---
+ gcc/config/microblaze/microblaze.c         |  8 ++++++--
+ gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
+ 2 files changed, 16 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index ae7d5dd..002d7a5 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2594,14 +2594,18 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
++      long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+ 	  if (GET_MODE (op) == DFmode)
+ 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+ 	  else
+ 	    {
+-	      val[0] = CONST_DOUBLE_HIGH (op);
+-	      val[1] = CONST_DOUBLE_LOW (op);
++	      REAL_VALUE_TYPE rv;
++	      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
++	      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
++	      val[1] = l[WORDS_BIG_ENDIAN == 0];
++	      val[0] = l[WORDS_BIG_ENDIAN != 0];
+ 	    }
+ 	}
+       else if (code == CONST_INT)
+diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
+new file mode 100644
+index 0000000..4d45186
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/long.c
+@@ -0,0 +1,10 @@
++/* { dg-options "-O0" } */
++#define BASEADDR 0xF0000000ULL
++int main ()
++{
++  unsigned long long start;
++  start = (unsigned long long) BASEADDR;
++  return 0;
++}
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
new file mode 100644
index 00000000..cbfc98de
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -0,0 +1,36 @@
+From 30402c3bcfeb8a93656957b22558997b65d69cb8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 11:49:58 +0530
+Subject: [PATCH 29/63] [Fix, microblaze]: Fix internal compiler error with
+ msmall-divides This patch will fix the internal error
+ microblaze_expand_divide function which comes because of rtx PLUS where the
+ mem_rtx is of type SI and the operand is of type QImode. This patch modifies
+ the mem_rtx as QImode and Plus as QImode to fix the error.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+ChangeLog:
+  2016-02-23 Nagaraju Mekala <nmekala@xilix.com>
+             Ajit Agarwal  <ajitkum@xilinx.com>
+
+                                  *microblaze.c (microblaze_expand_divide): Update
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 002d7a5..c662952 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3909,7 +3909,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+   emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
+   mem_rtx = gen_rtx_MEM (QImode,
+-                            gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
++                            gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
new file mode 100644
index 00000000..fce06359
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -0,0 +1,45 @@
+From 5ac80cf926c4dc96cbfd189f02c9250865b52dd3 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 12:03:39 +0530
+Subject: [PATCH 30/63] [patch,microblaze]: Fix the calculation of high word in
+ a long long 6. .4-bit
+
+This patch will change the calculation of high word in a long long 64-bit.
+Earlier to this patch the high word of long long word (0xF0000000ULL) is
+coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
+should be 0x00000000 and the low word should be 0xF0000000. This patch
+removes the condition of checking high word = 0 & low word < 0.
+This check is not required for the correctness of calculating 32-bit high
+and low words in a 64-bit long long.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2016-03-01 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+    *config/microblaze/microblaze.c (print_operand): Remove the condition of checking
+    high word = 0 & low word < 0.
+    *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
+---
+ gcc/config/microblaze/microblaze.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index c662952..8013a2c 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2612,9 +2612,6 @@ print_operand (FILE * file, rtx op, int letter)
+         {
+ 	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+ 	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+-	  if (val[0] == 0 && val[1] < 0)
+-	    val[0] = -1;
+-	    
+         }
+       fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+     }
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..cbf64d97
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0031-Patch-microblaze-Add-new-bit-field-instructions.patch
@@ -0,0 +1,120 @@
+From 45deb5bd3ae8c3db360ef181c9873e37d2288848 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 12:14:51 +0530
+Subject: [PATCH 31/63] [Patch, microblaze]: Add new bit-field instructions
+ This patches adds new bsefi and bsifi instructions. BSEFI- The instruction
+ shall extract a bit field from a register and place it right-adjusted in the
+ destination register. The other bits in the destination register shall be set
+ to zero BSIFI- The instruction shall insert a right-adjusted bit field from a
+ register at another position in the destination register. The rest of the
+ bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+  2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
+
+  *microblaze.md (Update): Added new patterns
+---
+ gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index b7c16ac..67b298a 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -982,6 +982,8 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"20,20,20")])
+ 
++
++
+ ;;----------------------------------------------------------------
+ ;; Data movement
+ ;;----------------------------------------------------------------
+@@ -1776,6 +1778,7 @@
+   (set_attr "length"   "28")]
+ )
+ 
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an integer comparison. 
+ ;;----------------------------------------------------------------
+@@ -2489,4 +2492,74 @@
+   DONE;
+ }")
+ 
++(define_expand "extvsi"
++  [(set (match_operand:SI 0 "register_operand" "r")
++	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++			 (match_operand:SI 2 "immediate_operand" "I")
++			 (match_operand:SI 3 "immediate_operand" "I")))]
++"TARGET_HAS_BITFIELD"
++"
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++  if ((len == 0) || (pos + len > 32) )
++    FAIL;
++
++  ;;if (!register_operand (operands[1], VOIDmode))
++  ;;  FAIL;
++  if (operands[0] == operands[1])
++  FAIL;
++  if (GET_CODE (operands[1]) == ASHIFT)
++  FAIL;
++;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "extv_32"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++			 (match_operand:SI 2 "immediate_operand" "I")
++			 (match_operand:SI 3 "immediate_operand" "I")))]
++ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
++   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
++  "bsefi %0,%1,%2,%3"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
++(define_expand "insvsi"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++			 (match_operand:SI 1 "immediate_operand" "I")
++			 (match_operand:SI 2 "immediate_operand" "I"))
++	(match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD"
++  "
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++  if (len <= 0 || pos + len > 32)
++    FAIL;
++
++  ;;if (!register_operand (operands[0], VOIDmode))
++  ;;  FAIL;
++
++  emit_insn (gen_insv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "insv_32"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++			 (match_operand:SI 1 "immediate_operand" "I")
++			 (match_operand:SI 2 "immediate_operand" "I"))
++	(match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
++   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
++  "bsifi %0, %3, %1, %2"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
+ (include "sync.md")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 00000000..86df58b3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,247 @@
+From bc95cc12b2c4d96ea709eefc4b99181b8c40b19c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 12:42:10 +0530
+Subject: [PATCH 32/63] [Patch, microblaze]: Fix bug in MB version calculation
+ This patch fixes the bug in microblaze_version_to_int function. Earlier the
+ conversion of vXX.YY.Z to int has a bug which is fixed now.
+
+Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
+                Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
+ 1 file changed, 70 insertions(+), 77 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 8013a2c..3f68ef0 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -239,6 +239,63 @@ section *sdata2_section;
+ #define TARGET_HAVE_TLS true
+ #endif
+ 
++/*  Convert a version number of the form "vX.YY.Z" to an integer encoding
++    for easier range comparison.  */
++static int
++microblaze_version_to_int (const char *version)
++{
++  const char *p, *v;
++  const char *tmpl = "vXX.YY.Z";
++  int iver1 =0, iver2 =0, iver3 =0;
++
++  p = version;
++  v = tmpl;
++
++  while (*p)
++    {
++      if (*v == 'X')
++	{			/* Looking for major  */
++          if (*p == '.')
++            {
++              *v++;
++            }
++          else
++            {
++	      if (!(*p >= '0' && *p <= '9'))
++	        return -1;
++	      iver1 += (int) (*p - '0');
++              iver1 *= 1000;
++	     }
++        }
++      else if (*v == 'Y')
++	{			/* Looking for minor  */
++	  if (!(*p >= '0' && *p <= '9'))
++	    return -1;
++	  iver2 += (int) (*p - '0');
++	  iver2 *= 10;
++	}
++      else if (*v == 'Z')
++	{			/* Looking for compat  */
++	  if (!(*p >= 'a' && *p <= 'z'))
++	    return -1;
++      iver3 = ((int) (*p)) - 96;
++	}
++      else
++	{
++	  if (*p != *v)
++	    return -1;
++	}
++
++      v++;
++      p++;
++    }
++
++  if (*p)
++    return -1;
++
++  return iver1 + iver2 + iver3;
++}
++
+ /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
+ static bool
+ microblaze_const_double_ok (rtx op, machine_mode mode)
+@@ -1338,8 +1395,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+       {
+ 	if (TARGET_BARREL_SHIFT)
+ 	  {
+-	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+-		>= 0)
++	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ 	      *total = COSTS_N_INSNS (1);
+ 	    else
+ 	      *total = COSTS_N_INSNS (2);
+@@ -1400,8 +1456,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ 	  }
+ 	else if (!TARGET_SOFT_MUL)
+ 	  {
+-	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+-		>= 0)
++	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ 	      *total = COSTS_N_INSNS (1);
+ 	    else
+ 	      *total = COSTS_N_INSNS (3);
+@@ -1682,72 +1737,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
+   return 0;
+ }
+ 
+-/*  Convert a version number of the form "vX.YY.Z" to an integer encoding 
+-    for easier range comparison.  */
+-static int
+-microblaze_version_to_int (const char *version)
+-{
+-  const char *p, *v;
+-  const char *tmpl = "vXX.YY.Z";
+-  int iver = 0;
+-
+-  p = version;
+-  v = tmpl;
+-
+-  while (*p)
+-    {
+-      if (*v == 'X')
+-	{			/* Looking for major  */
+-          if (*p == '.')
+-            {
+-              v++;
+-            }
+-          else
+-            {
+-	      if (!(*p >= '0' && *p <= '9'))
+-	        return -1;
+-	      iver += (int) (*p - '0');
+-              iver *= 10;
+-	     }
+-        }
+-      else if (*v == 'Y')
+-	{			/* Looking for minor  */
+-	  if (!(*p >= '0' && *p <= '9'))
+-	    return -1;
+-	  iver += (int) (*p - '0');
+-	  iver *= 10;
+-	}
+-      else if (*v == 'Z')
+-	{			/* Looking for compat  */
+-	  if (!(*p >= 'a' && *p <= 'z'))
+-	    return -1;
+-	  iver *= 10;
+-	  iver += (int) (*p - 'a');
+-	}
+-      else
+-	{
+-	  if (*p != *v)
+-	    return -1;
+-	}
+-
+-      v++;
+-      p++;
+-    }
+-
+-  if (*p)
+-    return -1;
+-
+-  return iver;
+-}
+-
+-
+ static void
+ microblaze_option_override (void)
+ {
+   register int i, start;
+   register int regno;
+   register machine_mode mode;
+-  int ver;
++  int ver,ver_int;
+ 
+   microblaze_section_threshold = (global_options_set.x_g_switch_value
+ 				  ? g_switch_value
+@@ -1768,13 +1764,13 @@ microblaze_option_override (void)
+   /* Check the MicroBlaze CPU version for any special action to be done.  */
+   if (microblaze_select_cpu == NULL)
+     microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
+-  ver = microblaze_version_to_int (microblaze_select_cpu);
+-  if (ver == -1)
++  ver_int = microblaze_version_to_int (microblaze_select_cpu);
++  if (ver_int == -1)
+     {
+       error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
++  ver = ver_int - microblaze_version_to_int("v3.00.a");
+   if (ver < 0)
+     {
+       /* No hardware exceptions in earlier versions. So no worries.  */
+@@ -1785,8 +1781,7 @@ microblaze_option_override (void)
+       microblaze_pipe = MICROBLAZE_PIPE_3;
+     }
+   else if (ver == 0
+-	   || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
+-	       == 0))
++	   || (ver_int ==  microblaze_version_to_int("v4.00.b")))
+     {
+ #if 0
+       microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
+@@ -1803,11 +1798,9 @@ microblaze_option_override (void)
+ #endif
+       microblaze_no_unsafe_delay = 0;
+       microblaze_pipe = MICROBLAZE_PIPE_5;
+-      if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
+-	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+-					 "v5.00.b") == 0
+-	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+-					 "v5.00.c") == 0)
++      if ((ver_int == microblaze_version_to_int("v5.00.a"))
++	  || (ver_int == microblaze_version_to_int("v5.00.b"))
++	  || (ver_int == microblaze_version_to_int("v5.00.c")))
+ 	{
+ 	  /* Pattern compares are to be turned on by default only when 
+  	     compiling for MB v5.00.'z'.  */
+@@ -1815,7 +1808,7 @@ microblaze_option_override (void)
+ 	}
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
++  ver = ver_int - microblaze_version_to_int("v6.00.a");
+   if (ver < 0)
+     {
+       if (TARGET_MULTIPLY_HIGH)
+@@ -1824,7 +1817,7 @@ microblaze_option_override (void)
+ 		 "%<-mcpu=v6.00.a%> or greater");
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
++  ver = ver_int - microblaze_version_to_int("v8.10.a");
+   microblaze_has_clz = 1;
+   if (ver < 0)
+     {
+@@ -1833,7 +1826,7 @@ microblaze_option_override (void)
+     }
+ 
+   /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
++  ver = ver_int - microblaze_version_to_int("v8.30.a");
+   if (ver < 0)
+     {
+         if (TARGET_REORDER == 1)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0033-Fixing-the-bug-in-the-bit-field-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
new file mode 100644
index 00000000..68f70ae8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0033-Fixing-the-bug-in-the-bit-field-instruction.patch
@@ -0,0 +1,48 @@
+From 51da0572e0650378e422030b26d1258c8fc76df6 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 13:57:48 +0530
+Subject: [PATCH 33/63] Fixing the bug in the bit-field instruction. Bit field
+ instruction should be generated only if mcpu >10.0
+
+---
+ gcc/config/microblaze/microblaze.c | 3 +++
+ gcc/config/microblaze/microblaze.h | 2 ++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 3f68ef0..a37f08eea 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn.  */
+ int microblaze_has_clz = 0;
+ 
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
+    version having only a particular type of pipeline. There can still be 
+    options on the CPU to scale pipeline features up or down. :( 
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index bf7f3b4..1d05e6e 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
+ 
+ extern int microblaze_no_unsafe_delay;
+ extern int microblaze_has_clz;
++extern int microblaze_has_bitfield;
+ extern enum pipeline_type microblaze_pipe;
+ 
+ #define OBJECT_FORMAT_ELF
+@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
+ 
+ /* Do we have CLZ?  */
+ #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
++#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
+ 
+ /* The default is to support PIC.  */
+ #define TARGET_SUPPORTS_PIC 1
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
new file mode 100644
index 00000000..04326205
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch
@@ -0,0 +1,32 @@
+From 132b913b721f66c5db17f62dd5559bbca11bb875 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 20:57:10 +0530
+Subject: [PATCH 34/63] [Patch, microblaze]: Macros used in Xilinx internal
+ patches has been removed in gcc 6.2 version so modified the code accordingly.
+
+---
+ gcc/config/microblaze/microblaze.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index a37f08eea..71640e5 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2597,11 +2597,9 @@ print_operand (FILE * file, rtx op, int letter)
+ 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+ 	  else
+ 	    {
+-	      REAL_VALUE_TYPE rv;
+-	      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
+-	      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
+-	      val[1] = l[WORDS_BIG_ENDIAN == 0];
+-	      val[0] = l[WORDS_BIG_ENDIAN != 0];
++              REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
++              val[1] = l[WORDS_BIG_ENDIAN == 0];
++              val[0] = l[WORDS_BIG_ENDIAN != 0];
+ 	    }
+ 	}
+       else if (code == CONST_INT)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0035-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0035-Fixing-the-issue-with-the-builtin_alloc.patch
new file mode 100644
index 00000000..91ac0d02
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0035-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -0,0 +1,44 @@
+From e672184af6a43b773131181270c7a8c5c5273bd8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 23 Feb 2017 17:09:04 +0530
+Subject: [PATCH 35/63] Fixing the issue with the builtin_alloc. register r18
+ was not properly handling the stack pattern which was resolved by using free
+ available register
+
+signed-off-by:nagaraju mekala <nmekala@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.md | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 67b298a..7bae957 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2078,10 +2078,10 @@
+   ""
+   { 
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+-    rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
++    rtx reg = gen_reg_rtx (Pmode);
+     rtx neg_op0;
+ 
+-    emit_move_insn (rtmp, retaddr);
++    emit_move_insn (reg, retaddr);
+     if (GET_CODE (operands[1]) != CONST_INT)
+     {
+         neg_op0 = gen_reg_rtx (Pmode);
+@@ -2090,9 +2090,9 @@
+         neg_op0 = GEN_INT (- INTVAL (operands[1]));
+ 
+     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+-    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
++    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
+     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+-    emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
++    emit_insn (gen_rtx_CLOBBER (SImode, reg));
+     DONE;
+   }
+ )
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
new file mode 100644
index 00000000..7079789f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch
@@ -0,0 +1,49 @@
+From ac30efb4a5f5b6d289fdd27b268c2095d60dcb42 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 2 Mar 2017 19:02:31 +0530
+Subject: [PATCH 36/63] [Patch,Microblaze]:reverting the cost check before
+ propagating constants.
+
+---
+ gcc/cprop.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/gcc/cprop.c b/gcc/cprop.c
+index 65c0130..42bcc81 100644
+--- a/gcc/cprop.c
++++ b/gcc/cprop.c
+@@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+   int success = 0;
+   rtx set = single_set (insn);
+ 
++#if 0
+   bool check_rtx_costs = true;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int old_cost = set ? set_rtx_cost (set, speed) : 0;
+@@ -744,6 +745,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 	  && (GET_CODE (XEXP (note, 0)) == CONST
+ 	      || CONSTANT_P (XEXP (note, 0)))))
+     check_rtx_costs = false;
++#endif
+ 
+   /* Usually we substitute easy stuff, so we won't copy everything.
+      We however need to take care to not duplicate non-trivial CONST
+@@ -752,6 +754,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 
+   validate_replace_src_group (from, to, insn);
+ 
++#if 0
+   /* If TO is a constant, check the cost of the set after propagation
+      to the cost of the set before the propagation.  If the cost is
+      higher, then do not replace FROM with TO.  */
+@@ -764,6 +767,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+       return false;
+     }
+ 
++#endif
+ 
+   if (num_changes_pending () && apply_change_group ())
+     success = 1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
new file mode 100644
index 00000000..ba0f8e80
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
@@ -0,0 +1,80 @@
+From f436198b817f33d56aaddb88ff629378498de489 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 19 Feb 2018 18:06:16 +0530
+Subject: [PATCH 37/63] [Patch,Microblaze]: update in constraints for bitfield
+ insert and extract instructions.
+
+---
+ gcc/config/microblaze/microblaze.md | 43 ++++++-------------------------------
+ 1 file changed, 7 insertions(+), 36 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7bae957..6101387 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2492,33 +2492,17 @@
+   DONE;
+ }")
+ 
+-(define_expand "extvsi"
++(define_expand "extzvsi"
+   [(set (match_operand:SI 0 "register_operand" "r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+ 			 (match_operand:SI 3 "immediate_operand" "I")))]
+ "TARGET_HAS_BITFIELD"
+-"
+-{
+-  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
+-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
+-
+-  if ((len == 0) || (pos + len > 32) )
+-    FAIL;
+-
+-  ;;if (!register_operand (operands[1], VOIDmode))
+-  ;;  FAIL;
+-  if (operands[0] == operands[1])
+-  FAIL;
+-  if (GET_CODE (operands[1]) == ASHIFT)
+-  FAIL;
+-;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
+- emit_insn (gen_extv_32 (operands[0], operands[1],
+-			  operands[2], operands[3]));
+-  DONE;
+-}")
++""
++)
+ 
+-(define_insn "extv_32"
++
++(define_insn "extzv_32"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+@@ -2535,21 +2519,8 @@
+ 			 (match_operand:SI 2 "immediate_operand" "I"))
+ 	(match_operand:SI 3 "register_operand" "r"))]
+  "TARGET_HAS_BITFIELD"
+-  "
+-{
+-  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
+-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
+-
+-  if (len <= 0 || pos + len > 32)
+-    FAIL;
+-
+-  ;;if (!register_operand (operands[0], VOIDmode))
+-  ;;  FAIL;
+-
+-  emit_insn (gen_insv_32 (operands[0], operands[1],
+-			  operands[2], operands[3]));
+-  DONE;
+-}")
++""
++)
+ 
+ (define_insn "insv_32"
+   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
new file mode 100644
index 00000000..2b90880f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -0,0 +1,38 @@
+From 89aa1907ab0abad38e394f46f7e5f577bdb26498 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 4 Jun 2018 10:10:18 +0530
+Subject: [PATCH 38/63] [Patch,Microblaze] : Removed fsqrt generation for
+ double values.
+
+---
+ gcc/config/microblaze/microblaze.md | 14 --------------
+ 1 file changed, 14 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 6101387..eb01221 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -526,20 +526,6 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "sqrtdf2"
+-  [(set (match_operand:DF 0 "register_operand" "=d")
+-        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
+-  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
+-  {
+-    if (REGNO (operands[0]) == REGNO (operands[1]))
+-      return "fsqrt\t%0,%1";
+-    else
+-      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
+-  }
+-  [(set_attr "type"     "fsqrt")
+-   (set_attr "mode"      "SF")
+-   (set_attr "length"    "4")])
+-
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch
new file mode 100644
index 00000000..f524cba2
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0039-Intial-commit-of-64-bit-Microblaze.patch
@@ -0,0 +1,804 @@
+From 68359cc8e82f63d01a77c39c68e782e6757cd71e Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 3 Apr 2018 16:48:39 +0530
+Subject: [PATCH 39/63] Intial commit of 64-bit Microblaze
+
+Conflicts:
+	gcc/config/microblaze/microblaze.opt
+---
+ gcc/config/microblaze/microblaze-protos.h |   1 +
+ gcc/config/microblaze/microblaze.c        | 109 +++++++--
+ gcc/config/microblaze/microblaze.h        |   4 +-
+ gcc/config/microblaze/microblaze.md       | 370 +++++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt      |   7 +-
+ gcc/config/microblaze/t-microblaze        |   7 +-
+ 6 files changed, 460 insertions(+), 38 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index bdc9b69..7d6c189 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
+ extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_sf (rtx *); 
++extern void microblaze_expand_conditional_branch_df (rtx *); 
+ extern int microblaze_can_use_return_insn (void);
+ extern void print_operand (FILE *, rtx, int);
+ extern void print_operand_address (FILE *, rtx);
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 71640e5..f740f5c 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3570,11 +3570,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+   op0 = operands[0];
+   op1 = operands[1];
+ 
+-  if (!register_operand (op0, SImode)
+-      && !register_operand (op1, SImode)
++  if (!register_operand (op0, mode)
++      && !register_operand (op1, mode)
+       && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
+     {
+-      rtx temp = force_reg (SImode, op1);
++      rtx temp = force_reg (mode, op1);
+       emit_move_insn (op0, temp);
+       return true;
+     }
+@@ -3639,12 +3639,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+ 	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
+ 		      || !SMALL_INT (p1)))))
+ 	{
+-	  rtx temp = force_reg (SImode, p0);
++	  rtx temp = force_reg (mode, p0);
+ 	  rtx temp2 = p1;
+ 
+ 	  if (flag_pic && reload_in_progress)
+ 	    df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
+-	  emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
++	  emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
+ 	  return true;
+ 	}
+     }
+@@ -3775,7 +3775,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+   rtx cmp_op0 = operands[1];
+   rtx cmp_op1 = operands[2];
+   rtx label1 = operands[3];
+-  rtx comp_reg = gen_reg_rtx (SImode);
++  rtx comp_reg = gen_reg_rtx (mode);
+   rtx condition;
+ 
+   gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
+@@ -3784,23 +3784,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+   if (cmp_op1 == const0_rtx)
+     {
+       comp_reg = cmp_op0;
+-      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
++
+     }
+ 
+   else if (code == EQ || code == NE)
+     {
+       /* Use xor for equal/not-equal comparison.  */
+-      emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
+-      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
++      else
++        emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
++      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else
+     {
+       /* Generate compare and branch in single instruction. */
+       cmp_op1 = force_reg (mode, cmp_op1);
+       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
+-      emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
++      if (mode == SImode)
++        emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
++      else
++        emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
+     }
+ }
+ 
+@@ -3811,7 +3824,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+   rtx cmp_op0 = operands[1];
+   rtx cmp_op1 = operands[2];
+   rtx label1 = operands[3];
+-  rtx comp_reg = gen_reg_rtx (SImode);
++  rtx comp_reg = gen_reg_rtx (mode);
+   rtx condition;
+ 
+   gcc_assert ((GET_CODE (cmp_op0) == REG)
+@@ -3822,30 +3835,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code),
+-                                  SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++                                  mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else if (code == EQ)
+     {
+-      emit_insn (gen_seq_internal_pat (comp_reg,
+-                                       cmp_op0, cmp_op1));
+-      condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        {
++          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      else
++        {
++          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
++ 
+     }
+   else if (code == NE)
+     {
+-      emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
+-                                       cmp_op1));
+-      condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        {
++          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      else
++        {
++          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else
+     {
+       /* Generate compare and branch in single instruction. */
+       cmp_op1 = force_reg (mode, cmp_op1);
+       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
+-      emit_jump_insn (gen_branch_compare (condition, cmp_op0,
+-                                         cmp_op1, label1));
++      if (mode == SImode)
++        emit_jump_insn (gen_branch_compare (condition, cmp_op0,
++                                           cmp_op1, label1));
++      else 
++	{
++          emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
++                                             cmp_op1, label1));
++        }	
++
+     }
+ }
+ 
+@@ -3862,6 +3908,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+   emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
++void
++microblaze_expand_conditional_branch_df (rtx operands[])
++{
++  rtx condition;
++  rtx cmp_op0 = XEXP (operands[0], 0);
++  rtx cmp_op1 = XEXP (operands[0], 1);
++  rtx comp_reg = gen_reg_rtx (DImode);
++
++  emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
++  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
++  emit_jump_insn (gen_long_condjump (condition, operands[3]));
++}
++
+ /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
+ 
+ static bool
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 1d05e6e..2ca44f5 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define ASM_SPEC "\
+ %(target_asm_spec) \
+ %{mbig-endian:-EB} \
++%{m64:-m64} \
+ %{mlittle-endian:-EL}"
+ 
+ /* Extra switches sometimes passed to the linker.  */
+@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define LINK_SPEC "%{shared:-shared} -N -relax \
+   %{mbig-endian:-EB --oformat=elf32-microblaze} \
+   %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
++  %{m64:-EL --oformat=elf64-microblazeel} \
+   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+   %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
+@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define MIN_UNITS_PER_WORD      4
+ #define INT_TYPE_SIZE           32
+ #define SHORT_TYPE_SIZE         16
+-#define LONG_TYPE_SIZE          32
++#define LONG_TYPE_SIZE          64
+ #define LONG_LONG_TYPE_SIZE     64
+ #define FLOAT_TYPE_SIZE         32
+ #define DOUBLE_TYPE_SIZE        64
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index eb01221..dbb592e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -497,7 +497,6 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+-
+ (define_insn "divsf3"
+   [(set (match_operand:SF 0 "register_operand" "=d")
+         (div:SF (match_operand:SF 1 "register_operand" "d")
+@@ -508,6 +507,7 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++
+ (define_insn "sqrtsf2"
+   [(set (match_operand:SF 0 "register_operand" "=d")
+         (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
+@@ -562,6 +562,18 @@
+ 
+ ;; Adding 2 DI operands in register or reg/imm
+ 
++(define_insn "adddi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
++		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   addlk\t%0,%z1,%2
++   addlik\t%0,%z1,%2"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "adddi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+@@ -606,6 +618,18 @@
+ ;; Double Precision Subtraction
+ ;;----------------------------------------------------------------
+ 
++(define_insn "subdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
++		  (match_operand:DI 2 "register_operand" "d,n")))]
++  "TARGET_MB_64"
++  "@
++   rsubl\t%0,%2,%1
++   addlik\t%0,%z1,-%2"
++  [(set_attr "type"	"darith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "subdi3"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+@@ -795,6 +819,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "negdi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "rsubl\t%0,%1,r0"
++  [(set_attr "type"	"darith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
+ (define_insn "negdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -814,6 +847,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "one_cmpldi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(not:DI (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "xorli\t%0,%1,-1"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
+ (define_insn "*one_cmpldi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -840,6 +882,20 @@
+ ;; Logical
+ ;;----------------------------------------------------------------
+ 
++(define_insn "anddi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   andl\t%0,%1,%2
++   andli\t%0,%1,%2 #andl1"
++  ;; andli\t%0,%1,%2 #andl3
++  ;; andli\t%0,%1,%2 #andl2
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "andsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ 	(and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
+@@ -855,6 +911,18 @@
+   (set_attr "length"	"4,8,8,8")])
+ 
+ 
++(define_insn "iordi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ior:DI (match_operand:DI 1 "arith_operand" "d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   orl\t%0,%1,%2
++   orli\t%0,%1,%2 #andl1"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "iorsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ 	(ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
+@@ -869,6 +937,19 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "xordi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   xorl\t%0,%1,%2
++   xorli\t%0,%1,%2 #andl1"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
++
+ (define_insn "xorsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ 	(xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
+@@ -937,6 +1018,26 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++;;(define_expand "extendqidi2"
++;;  [(set (match_operand:DI 0 "register_operand" "=d")
++;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
++;;  "TARGET_MB_64"
++;;  {
++;;	if (GET_CODE (operands[1]) != REG)
++;;	FAIL;
++;;   }
++;;)
++    
++
++;;(define_insn "extendqidi2"
++;;  [(set (match_operand:DI 0 "register_operand" "=d")
++;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
++;;  "TARGET_MB_64"
++;;  "sextl8\t%0,%1"
++;;  [(set_attr "type"	"arith")
++;;  (set_attr "mode"	"DI")
++;;  (set_attr "length"	"4")])
++
+ (define_insn "extendhisi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
+@@ -946,6 +1047,16 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "extendhidi2"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "sextl16\t%0,%1"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++
+ ;; Those for integer source operand are ordered
+ ;; widest source type first.
+ 
+@@ -1011,7 +1122,6 @@
+ )
+ 
+ 
+-
+ (define_insn "*movdi_internal"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+ 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
+@@ -1423,6 +1533,36 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++;; Barrel shift left
++(define_expand "ashldi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(ashift:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "ashldi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++  bsllli\t%0,%1,%2
++  bslll\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++)
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1548,6 +1688,36 @@
+ ;;----------------------------------------------------------------
+ ;; 32-bit right shifts
+ ;;----------------------------------------------------------------
++;; Barrel shift left
++(define_expand "ashrdi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "ashrdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++   bslrai\t%0,%1,%2
++   bslra\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++  )
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -1657,6 +1827,36 @@
+ ;;----------------------------------------------------------------
+ ;; 32-bit right shifts (logical)
+ ;;----------------------------------------------------------------
++;; Barrel shift left
++(define_expand "lshrdi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "lshrdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++   bslrli\t%0,%1,%2
++   bslrl\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++  )
+ 
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+@@ -1803,6 +2003,8 @@
+   (set_attr "length"	"4")]
+ )              
+ 
++
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an floating point comparison. 
+ ;;----------------------------------------------------------------
+@@ -1818,6 +2020,18 @@
+    (set_attr "length"    "4")]
+ )
+ 
++(define_insn "cstoredf4"
++   [(set (match_operand:DI 0 "register_operand" "=r")
++        (match_operator:DI 1 "ordered_comparison_operator"
++	      [(match_operand:DF 2 "register_operand" "r")
++	       (match_operand:DF 3 "register_operand" "r")]))]
++  "TARGET_MB_64"
++  "dcmp.%C1\t%0,%3,%2"
++  [(set_attr "type"     "fcmp")
++   (set_attr "mode"      "DF")
++   (set_attr "length"    "4")]
++)
++
+ ;;----------------------------------------------------------------
+ ;; Conditional branches
+ ;;----------------------------------------------------------------
+@@ -1930,6 +2144,115 @@
+    (set_attr "length"   "12")]
+ )
+ 
++
++(define_expand "cbranchdi4"
++  [(set (pc)
++        (if_then_else (match_operator 0 "ordered_comparison_operator"
++                       [(match_operand:DI 1 "register_operand")
++                        (match_operand:DI 2 "arith_operand" "I,i")])
++                      (label_ref (match_operand 3 ""))
++                      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch (DImode, operands);
++  DONE;
++})
++
++(define_expand "cbranchdi4_reg"
++  [(set (pc)
++        (if_then_else (match_operator 0 "ordered_comparison_operator"
++                       [(match_operand:DI 1 "register_operand")
++                        (match_operand:DI 2 "register_operand")])
++                      (label_ref (match_operand 3 ""))
++                      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch_reg (DImode, operands);
++  DONE;
++})
++
++(define_expand "cbranchdf4"
++  [(set (pc)
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
++		       [(match_operand:DF 1 "register_operand")
++		        (match_operand:DF 2 "register_operand")])
++		      (label_ref (match_operand 3 ""))
++		      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch_df (operands);
++  DONE;
++
++})
++
++;; Used to implement comparison instructions
++(define_expand "long_condjump"
++  [(set (pc)
++	(if_then_else (match_operand 0)
++		      (label_ref (match_operand 1))
++		      (pc)))])
++
++(define_insn "long_branch_zero"
++  [(set (pc)
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++  				 [(match_operand:DI 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "beal%C0i%?\t%z1,%2";
++    else 
++      return "beal%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
++(define_insn "long_branch_compare"
++  [(set (pc)
++        (if_then_else (match_operator:DI 0 "cmp_op"
++                                         [(match_operand:DI 1 "register_operand" "d")
++                                          (match_operand:DI 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:DI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
++    return "beal%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
+@@ -2478,17 +2801,33 @@
+   DONE;
+ }")
+ 
+-(define_expand "extzvsi"
++(define_expand "extvsi"
+   [(set (match_operand:SI 0 "register_operand" "r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+ 			 (match_operand:SI 3 "immediate_operand" "I")))]
+ "TARGET_HAS_BITFIELD"
+-""
+-)
+-
++"
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++  if ((len == 0) || (pos + len > 32) )
++    FAIL;
++
++  ;;if (!register_operand (operands[1], VOIDmode))
++  ;;  FAIL;
++  if (operands[0] == operands[1])
++  FAIL;
++  if (GET_CODE (operands[1]) == ASHIFT)
++  FAIL;
++;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
+ 
+-(define_insn "extzv_32"
++(define_insn "extv_32"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+@@ -2505,8 +2844,21 @@
+ 			 (match_operand:SI 2 "immediate_operand" "I"))
+ 	(match_operand:SI 3 "register_operand" "r"))]
+  "TARGET_HAS_BITFIELD"
+-""
+-)
++  "
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++  if (len <= 0 || pos + len > 32)
++    FAIL;
++
++  ;;if (!register_operand (operands[0], VOIDmode))
++  ;;  FAIL;
++
++  emit_insn (gen_insv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
+ 
+ (define_insn "insv_32"
+   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index d23f376..f316e27 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -136,4 +136,9 @@ Target
+ 
+ mxl-frequency
+ Target Mask(AREA_OPTIMIZED_2)
+-Use 8 stage pipeline (frequency optimization)
++Use 8 stage pipeline (frequency optimization).
++
++m64
++Target Mask(MB_64)
++MicroBlaze 64-bit mode.
++
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 41fa9a9..e9a1921 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,8 +1,11 @@
+-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
+-MULTILIB_DIRNAMES = bs m mh le
++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
++MULTILIB_DIRNAMES = bs m mh le m64
+ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
new file mode 100644
index 00000000..a973f4cd
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch
@@ -0,0 +1,83 @@
+From 95615e1bfae642dc4f5f1b03e1ffaea4f16aa99c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Wed, 4 Apr 2018 16:41:41 +0530
+Subject: [PATCH 40/63] Added load store pattern movdi and also adding missing
+ files
+
+---
+ gcc/config/microblaze/constraints.md |  5 +++++
+ gcc/config/microblaze/microblaze.md  | 26 ++++++++++++++++++++++++++
+ gcc/config/microblaze/t-microblaze   |  4 ++--
+ 3 files changed, 33 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 5e1d79a..69bcb24 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -52,6 +52,11 @@
+   (and (match_code "const_int")
+        (match_test "ival > 0 && ival < 0x10000")))
+ 
++(define_constraint "K"
++  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
++  (and (match_code "const_int")
++       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
++
+ ;; Define floating point constraints
+ 
+ (define_constraint "G"
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index dbb592e..eb52957 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1122,6 +1122,32 @@
+ )
+ 
+ 
++(define_insn "*movdi_internal_64"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
++	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
++  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
++  { 
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1";
++      case 1:
++	return "addlik\t%0,r0,%1";
++      case 2:
++	  return "addlk\t%0,r0,r0";
++      case 3:
++      case 4:
++	  return "lli\t%0,%1";
++      case 5:
++      case 6:
++        return "sli\t%1,%0";
++    }
++    return "unreachable";
++  }
++  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"   "8,8,8,8,12,8,12")])
++
+ (define_insn "*movdi_internal"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+ 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index e9a1921..7671f63 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -4,8 +4,8 @@ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
++#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
++#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch
new file mode 100644
index 00000000..b022eb77
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0041-Intial-commit-for-64bit-MB-sources.patch
@@ -0,0 +1,2463 @@
+From 7c68b1c9771f09f7cc53410248e8432c562d24bf Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 27 Jul 2018 15:23:41 +0530
+Subject: [PATCH 41/63] Intial commit for 64bit-MB sources. Need to cleanup the
+ code later.
+
+---
+ gcc/config/microblaze/constraints.md    |   2 +-
+ gcc/config/microblaze/microblaze-c.c    |   6 +
+ gcc/config/microblaze/microblaze.c      | 218 ++++++++----
+ gcc/config/microblaze/microblaze.h      |  63 ++--
+ gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++++++++--------
+ gcc/config/microblaze/t-microblaze      |   7 +-
+ libgcc/config/microblaze/crti.S         |   4 +-
+ libgcc/config/microblaze/crtn.S         |   4 +-
+ libgcc/config/microblaze/divdi3.S       |  98 ++++++
+ libgcc/config/microblaze/divdi3_table.c |  62 ++++
+ libgcc/config/microblaze/moddi3.S       |  97 +++++
+ libgcc/config/microblaze/muldi3.S       |  73 ++++
+ libgcc/config/microblaze/t-microblaze   |  11 +-
+ libgcc/config/microblaze/udivdi3.S      | 107 ++++++
+ libgcc/config/microblaze/umoddi3.S      | 110 ++++++
+ 15 files changed, 1232 insertions(+), 236 deletions(-)
+ create mode 100644 libgcc/config/microblaze/divdi3.S
+ create mode 100644 libgcc/config/microblaze/divdi3_table.c
+ create mode 100644 libgcc/config/microblaze/moddi3.S
+ create mode 100644 libgcc/config/microblaze/muldi3.S
+ create mode 100644 libgcc/config/microblaze/udivdi3.S
+ create mode 100644 libgcc/config/microblaze/umoddi3.S
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 69bcb24..2fce91e 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -55,7 +55,7 @@
+ (define_constraint "K"
+   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
++       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
+ 
+ ;; Define floating point constraints
+ 
+diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
+index cd21319..d2b0c76 100644
+--- a/gcc/config/microblaze/microblaze-c.c
++++ b/gcc/config/microblaze/microblaze-c.c
+@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
+         builtin_define ("HAVE_HW_FPU_SQRT");
+       builtin_define ("__HAVE_HW_FPU_SQRT__");
+     }
++  if (TARGET_MB_64)
++    {
++      builtin_define ("__arch64__");
++      builtin_define ("__microblaze64__");
++      builtin_define ("__MICROBLAZE64__");
++    }
+ }  
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index f740f5c..d5ff7af 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
+ 	{
+ 	  return 1;
+ 	}
+-      else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
++      /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
+ 	{
+ 	  return 1;
+-	}
++	}*/
+       else
+ 	return 0;
+ 
+@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode)
+     return 1;
+ 
+   return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
+-			    ? E_SImode : E_SFmode),
++			    ? Pmode : E_SFmode),
+ 			   plus_constant (Pmode, addr, 4));
+ }
+ 
+@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
+          /* Load the addend.  */
+          addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
+ 				  UNSPEC_TLS);
+-         addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
++         addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
+          dest = gen_rtx_PLUS (Pmode, dest, addend);
+          break;
+ 
+@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
+ 
+   if (XINT (x, 1) == UNSPEC_GOTOFF)
+     {
+-      info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
++      info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
+       info->type = ADDRESS_GOTOFF;
+     }
+   else if (XINT (x, 1) == UNSPEC_PLT)
+@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
+   emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
+ 
+   /* Emit the test & branch.  */
+-  emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
++
++  if (TARGET_MB_64) {
++    emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
++			     src_reg, final_src, label));
++    }
++  else {
++    emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
+ 			     src_reg, final_src, label));
++  
++    }
+ 
+   /* Mop up any left-over bytes.  */
+   if (leftover)
+@@ -1634,14 +1642,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
+       break;
+ 
+     case E_DFmode:
+-      cum->arg_words += 2;
++      if (TARGET_MB_64)
++       cum->arg_words++;
++      else
++       cum->arg_words += 2;
+       if (!cum->gp_reg_found && cum->arg_number <= 2)
+ 	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
+       break;
+ 
+     case E_DImode:
+       cum->gp_reg_found = 1;
+-      cum->arg_words += 2;
++      if (TARGET_MB_64)
++       cum->arg_words++;
++      else
++       cum->arg_words += 2;
+       break;
+ 
+     case E_QImode:
+@@ -2295,7 +2309,7 @@ compute_frame_size (HOST_WIDE_INT size)
+ 
+ 	  if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
+ 	    /* Don't account for link register. It is accounted specially below.  */
+-	    gp_reg_size += GET_MODE_SIZE (SImode);
++	    gp_reg_size += GET_MODE_SIZE (Pmode);
+ 
+ 	  mask |= (1L << (regno - GP_REG_FIRST));
+ 	}
+@@ -2564,7 +2578,7 @@ print_operand (FILE * file, rtx op, int letter)
+ 
+       if ((letter == 'M' && !WORDS_BIG_ENDIAN)
+ 	  || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
+-	regnum++;
++	regnum++; 
+ 
+       fprintf (file, "%s", reg_names[regnum]);
+     }
+@@ -2590,6 +2604,7 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
++      int val1[2];
+       long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+@@ -2602,12 +2617,12 @@ print_operand (FILE * file, rtx op, int letter)
+               val[0] = l[WORDS_BIG_ENDIAN != 0];
+ 	    }
+ 	}
+-      else if (code == CONST_INT)
++      else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
+         {
+-	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+-	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
++	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
++	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
+         }
+-      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
++      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
+     }
+   else if (code == CONST_DOUBLE)
+     {
+@@ -2801,7 +2816,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
+ 
+     switch_to_section (get_section (section, 0, NULL));
+     assemble_align (POINTER_SIZE);
+-    fputs ("\t.word\t", asm_out_file);
++    if (TARGET_MB_64)
++      fputs ("\t.dword\t", asm_out_file);
++    else
++      fputs ("\t.word\t", asm_out_file);
+     output_addr_const (asm_out_file, symbol);
+     fputs ("\n", asm_out_file);
+ }
+@@ -2824,7 +2842,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
+ 
+     switch_to_section (get_section (section, 0, NULL));
+     assemble_align (POINTER_SIZE);
+-    fputs ("\t.word\t", asm_out_file);
++    if (TARGET_MB_64)
++      fputs ("\t.dword\t", asm_out_file);
++    else
++     fputs ("\t.word\t", asm_out_file);
+     output_addr_const (asm_out_file, symbol);
+     fputs ("\n", asm_out_file);
+ }
+@@ -2890,7 +2911,7 @@ save_restore_insns (int prologue)
+   /* For interrupt_handlers, need to save/restore the MSR.  */
+   if (microblaze_is_interrupt_variant ())
+     {
+-      isr_mem_rtx = gen_rtx_MEM (SImode,
++      isr_mem_rtx = gen_rtx_MEM (Pmode,
+ 				 gen_rtx_PLUS (Pmode, base_reg_rtx,
+ 					       GEN_INT (current_frame_info.
+ 							gp_offset -
+@@ -2898,8 +2919,8 @@ save_restore_insns (int prologue)
+ 
+       /* Do not optimize in flow analysis.  */
+       MEM_VOLATILE_P (isr_mem_rtx) = 1;
+-      isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
+-      isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
++      isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
++      isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
+     }
+ 
+   if (microblaze_is_interrupt_variant () && !prologue)
+@@ -2907,8 +2928,8 @@ save_restore_insns (int prologue)
+       emit_move_insn (isr_reg_rtx, isr_mem_rtx);
+       emit_move_insn (isr_msr_rtx, isr_reg_rtx);
+       /* Do not optimize in flow analysis.  */
+-      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
+-      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
+     }
+ 
+   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+@@ -2919,9 +2940,9 @@ save_restore_insns (int prologue)
+ 	    /* Don't handle here. Already handled as the first register.  */
+ 	    continue;
+ 
+-	  reg_rtx = gen_rtx_REG (SImode, regno);
++	  reg_rtx = gen_rtx_REG (Pmode, regno);
+ 	  insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
+-	  mem_rtx = gen_rtx_MEM (SImode, insn);
++	  mem_rtx = gen_rtx_MEM (Pmode, insn);
+ 	  if (microblaze_is_interrupt_variant () || save_volatiles)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+@@ -2936,7 +2957,7 @@ save_restore_insns (int prologue)
+ 	      insn = emit_move_insn (reg_rtx, mem_rtx);
+ 	    }
+ 
+-	  gp_offset += GET_MODE_SIZE (SImode);
++	  gp_offset += GET_MODE_SIZE (Pmode);
+ 	}
+     }
+ 
+@@ -2946,8 +2967,8 @@ save_restore_insns (int prologue)
+       emit_move_insn (isr_mem_rtx, isr_reg_rtx);
+ 
+       /* Do not optimize in flow analysis.  */
+-      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
+-      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
+     }
+ 
+   /* Done saving and restoring */
+@@ -3037,7 +3058,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
+ 
+   switch_to_section (s);
+   assemble_align (POINTER_SIZE);
+-  fputs ("\t.word\t", asm_out_file);
++  if (TARGET_MB_64)
++    fputs ("\t.dword\t", asm_out_file);
++  else
++    fputs ("\t.word\t", asm_out_file);
+   output_addr_const (asm_out_file, symbol);
+   fputs ("\n", asm_out_file);
+ }
+@@ -3182,10 +3206,10 @@ microblaze_expand_prologue (void)
+ 	{
+ 	  if (offset != 0)
+ 	    ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
+-	  emit_move_insn (gen_rtx_MEM (SImode, ptr),
+-			  gen_rtx_REG (SImode, regno));
++	  emit_move_insn (gen_rtx_MEM (Pmode, ptr),
++			  gen_rtx_REG (Pmode, regno));
+ 
+-	  offset += GET_MODE_SIZE (SImode);
++	  offset += GET_MODE_SIZE (Pmode);
+ 	}
+     }
+ 
+@@ -3194,15 +3218,23 @@ microblaze_expand_prologue (void)
+       rtx fsiz_rtx = GEN_INT (fsiz);
+ 
+       rtx_insn *insn = NULL;
+-      insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
++         if (TARGET_MB_64)
++           {
++              
++             insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
+ 				    fsiz_rtx));
++           }
++         else { 
++             insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
++				    fsiz_rtx));
++           }
+       if (insn)
+ 	RTX_FRAME_RELATED_P (insn) = 1;
+ 
+       /* Handle SUB_RETURN_ADDR_REGNUM specially at first.  */
+       if (!crtl->is_leaf || interrupt_handler)
+ 	{
+-	  mem_rtx = gen_rtx_MEM (SImode,
++	  mem_rtx = gen_rtx_MEM (Pmode,
+ 				 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ 					       const0_rtx));
+ 
+@@ -3210,7 +3242,7 @@ microblaze_expand_prologue (void)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+ 
+-	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
++	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ 	  insn = emit_move_insn (mem_rtx, reg_rtx);
+ 	  RTX_FRAME_RELATED_P (insn) = 1;
+ 	}
+@@ -3320,12 +3352,12 @@ microblaze_expand_epilogue (void)
+       if (!crtl->is_leaf || interrupt_handler)
+ 	{
+ 	  mem_rtx =
+-	    gen_rtx_MEM (SImode,
++	    gen_rtx_MEM (Pmode,
+ 			 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
+ 	  if (interrupt_handler)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+-	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
++	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ 	  emit_move_insn (reg_rtx, mem_rtx);
+ 	}
+ 
+@@ -3341,15 +3373,25 @@ microblaze_expand_epilogue (void)
+       /* _restore_ registers for epilogue.  */
+       save_restore_insns (0);
+       emit_insn (gen_blockage ());
+-      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
++      if (TARGET_MB_64)
++        emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
++      else
++        emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
+     }
+ 
+   if (crtl->calls_eh_return)
+-    emit_insn (gen_addsi3 (stack_pointer_rtx,
++      if (TARGET_MB_64) {
++          emit_insn (gen_adddi3 (stack_pointer_rtx,
+                            stack_pointer_rtx,
+-                           gen_raw_REG (SImode,
++                           gen_raw_REG (Pmode,
+ 					MB_EH_STACKADJ_REGNUM)));
+-
++        }
++      else {
++          emit_insn (gen_addsi3 (stack_pointer_rtx,
++                           stack_pointer_rtx,
++                           gen_raw_REG (Pmode,
++					MB_EH_STACKADJ_REGNUM)));
++        }
+   emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
+ 						    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ }
+@@ -3515,9 +3557,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+   else
+     this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
+ 
+-  /* Apply the constant offset, if required.  */
++  /* Apply the constant offset, if required. */ 
+   if (delta)
+-    emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
++    {
++      if (TARGET_MB_64)
++        emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); 
++      else
++        emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
++    } 
+ 
+   /* Apply the offset from the vtable, if required.  */
+   if (vcall_offset)
+@@ -3530,7 +3577,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+     rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
+     emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
+ 
+-    emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
++    if (TARGET_MB_64)
++      emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
++    else
++      emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
+   }
+ 
+   /* Generate a tail call to the target function.  */
+@@ -3704,7 +3754,7 @@ microblaze_eh_return (rtx op0)
+ /* Queue an .ident string in the queue of top-level asm statements.
+    If the string size is below the threshold, put it into .sdata2.
+    If the front-end is done, we must be being called from toplev.c.
+-   In that case, do nothing.  */
++   In that case, do nothing. */ 
+ void 
+ microblaze_asm_output_ident (const char *string)
+ {
+@@ -3759,9 +3809,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+   emit_block_move (m_tramp, assemble_trampoline_template (),
+ 		   GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
+ 
+-  mem = adjust_address (m_tramp, SImode, 16);
++  mem = adjust_address (m_tramp, Pmode, 16);
+   emit_move_insn (mem, chain_value);
+-  mem = adjust_address (m_tramp, SImode, 20);
++  mem = adjust_address (m_tramp, Pmode, 20);
+   emit_move_insn (mem, fnaddr);
+ }
+ 
+@@ -3785,7 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
++      if (mode == Pmode)
+         emit_jump_insn (gen_condjump (condition, label1));
+       else
+         emit_jump_insn (gen_long_condjump (condition, label1));
+@@ -3904,7 +3954,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+   rtx comp_reg = gen_reg_rtx (SImode);
+ 
+   emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+-  condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+   emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
+@@ -3914,10 +3964,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+   rtx condition;
+   rtx cmp_op0 = XEXP (operands[0], 0);
+   rtx cmp_op1 = XEXP (operands[0], 1);
+-  rtx comp_reg = gen_reg_rtx (DImode);
++  rtx comp_reg = gen_reg_rtx (Pmode);
+ 
+   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+-  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
++  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+   emit_jump_insn (gen_long_condjump (condition, operands[3]));
+ }
+ 
+@@ -3938,8 +3988,8 @@ microblaze_expand_divide (rtx operands[])
+ {
+   /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
+ 
+-  rtx regt1 = gen_reg_rtx (SImode); 
+-  rtx reg18 = gen_rtx_REG (SImode, R_TMP);
++  rtx regt1 = gen_reg_rtx (Pmode); 
++  rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
+   rtx regqi = gen_reg_rtx (QImode);
+   rtx_code_label *div_label = gen_label_rtx ();
+   rtx_code_label *div_end_label = gen_label_rtx ();
+@@ -3947,17 +3997,31 @@ microblaze_expand_divide (rtx operands[])
+   rtx mem_rtx;
+   rtx ret;
+   rtx_insn *jump, *cjump, *insn;
+-
+-  insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
+-  cjump = emit_jump_insn_after (gen_cbranchsi4 (
+-					gen_rtx_GTU (SImode, regt1, GEN_INT (15)), 
++ 
++  if (TARGET_MB_64) {
++      insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
++      cjump = emit_jump_insn_after (gen_cbranchdi4 (
++					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
++					regt1, GEN_INT (15), div_label), insn);
++    }
++  else {
++      insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
++      cjump = emit_jump_insn_after (gen_cbranchsi4 (
++					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
+ 					regt1, GEN_INT (15), div_label), insn);
++    }
+   LABEL_NUSES (div_label) = 1; 
+   JUMP_LABEL (cjump) = div_label;
+-  emit_insn (gen_rtx_CLOBBER (SImode, reg18));
++  emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+-  emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+-  emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
++  if (TARGET_MB_64) {
++      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
++    }
++  else  {
++      emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
++    }
+   mem_rtx = gen_rtx_MEM (QImode,
+                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+@@ -4104,7 +4168,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+               {
+                 insn =
+                   emit_insn_before (gen_iprefetch
+-                                    (gen_int_mode (addr_offset, SImode)),
++                                    (gen_int_mode (addr_offset, Pmode)),
+                                     before_4);
+                 recog_memoized (insn);
+                 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
+@@ -4114,7 +4178,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+            }
+        }
+ }
+-
++  
++/* Set the names for various arithmetic operations according to the
++ *    MICROBLAZE ABI.  */
++static void
++microblaze_init_libfuncs (void)
++{ 
++  set_optab_libfunc (smod_optab,     SImode, "__modsi3");
++  set_optab_libfunc (sdiv_optab,     SImode, "__divsi3");
++  set_optab_libfunc (smul_optab,     SImode, "__mulsi3");
++  set_optab_libfunc (umod_optab,     SImode, "__umodsi3");
++  set_optab_libfunc (udiv_optab,     SImode, "__udivsi3");
++  
++  if (TARGET_MB_64)
++    {
++      set_optab_libfunc (smod_optab,     DImode, "__moddi3");
++      set_optab_libfunc (sdiv_optab,     DImode, "__divdi3");
++      set_optab_libfunc (smul_optab,     DImode, "__muldi3");
++      set_optab_libfunc (umod_optab,     DImode, "__umoddi3");
++      set_optab_libfunc (udiv_optab,     DImode, "__udivdi3");
++    }
++}       
+ /* Insert instruction prefetch instruction at the fall
+    through path of the function call.  */
+ 
+@@ -4267,6 +4351,17 @@ microblaze_starting_frame_offset (void)
+ #undef TARGET_LRA_P
+ #define TARGET_LRA_P hook_bool_void_false
+ 
++#ifdef TARGET_MB_64
++#undef TARGET_ASM_ALIGNED_DI_OP
++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
++
++#undef TARGET_ASM_ALIGNED_HI_OP
++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
++
++#undef TARGET_ASM_ALIGNED_SI_OP
++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
++#endif
++
+ #undef TARGET_FRAME_POINTER_REQUIRED
+ #define TARGET_FRAME_POINTER_REQUIRED	microblaze_frame_pointer_required
+ 
+@@ -4276,6 +4371,9 @@ microblaze_starting_frame_offset (void)
+ #undef  TARGET_TRAMPOLINE_INIT
+ #define TARGET_TRAMPOLINE_INIT		microblaze_trampoline_init
+ 
++#undef TARGET_INIT_LIBFUNCS
++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
++
+ #undef  TARGET_PROMOTE_FUNCTION_MODE
+ #define TARGET_PROMOTE_FUNCTION_MODE 	default_promote_function_mode_always_promote
+ 
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 2ca44f5..a23fd4e 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
+ 
+ /* Generate DWARF exception handling info.  */
+ #define DWARF2_UNWIND_INFO 1
+-
+ /* Don't generate .loc operations.  */
+ #define DWARF2_ASM_LINE_DEBUG_INFO 0
+ 
+@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
+   ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
+ 
+ /* Use DWARF 2 debugging information by default.  */
+-#define DWARF2_DEBUGGING_INFO
++#define DWARF2_DEBUGGING_INFO 1
+ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
++#define DWARF2_ADDR_SIZE 4
+ 
+ /* Target machine storage layout */
+ 
+ #define BITS_BIG_ENDIAN 0
+ #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+ #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
+-#define BITS_PER_WORD           32
+-#define UNITS_PER_WORD          4
++//#define BITS_PER_WORD           64
++//Revisit
++#define MAX_BITS_PER_WORD	64
++#define UNITS_PER_WORD          (TARGET_MB_64 ? 8 : 4)
++//#define MIN_UNITS_PER_WORD      (TARGET_MB_64 ? 8 : 4)
++//#define UNITS_PER_WORD          4
+ #define MIN_UNITS_PER_WORD      4
+ #define INT_TYPE_SIZE           32
+ #define SHORT_TYPE_SIZE         16
+-#define LONG_TYPE_SIZE          64
++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
+ #define LONG_LONG_TYPE_SIZE     64
+ #define FLOAT_TYPE_SIZE         32
+ #define DOUBLE_TYPE_SIZE        64
+ #define LONG_DOUBLE_TYPE_SIZE   64
+-#define POINTER_SIZE            32
+-#define PARM_BOUNDARY           32
+-#define FUNCTION_BOUNDARY       32
+-#define EMPTY_FIELD_BOUNDARY    32
++#define POINTER_SIZE            (TARGET_MB_64 ? 64 : 32)
++//#define WIDEST_HARDWARE_FP_SIZE 64
++//#define POINTERS_EXTEND_UNSIGNED 1
++#define PARM_BOUNDARY           (TARGET_MB_64 ? 64 : 32)
++#define FUNCTION_BOUNDARY       (TARGET_MB_64 ? 64 : 32)
++#define EMPTY_FIELD_BOUNDARY    (TARGET_MB_64 ? 64 : 32)
+ #define STRUCTURE_SIZE_BOUNDARY 8
+-#define BIGGEST_ALIGNMENT       32
++#define BIGGEST_ALIGNMENT       (TARGET_MB_64 ? 64 : 32) 
+ #define STRICT_ALIGNMENT        1
+ #define PCC_BITFIELD_TYPE_MATTERS 1
+ 
++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
+ #undef SIZE_TYPE
+-#define SIZE_TYPE "unsigned int"
++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
+ 
+ #undef PTRDIFF_TYPE
+-#define PTRDIFF_TYPE "int"
++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
++
++/*#undef INTPTR_TYPE
++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
++#undef UINTPTR_TYPE
++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
+ 
+ #define DATA_ALIGNMENT(TYPE, ALIGN)					\
+   ((((ALIGN) < BITS_PER_WORD)						\
+@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
+ #define WORD_REGISTER_OPERATIONS 1
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+-
++/*
+ #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+   if (GET_MODE_CLASS (MODE) == MODE_INT		\
+-      && GET_MODE_SIZE (MODE) < 4)		\
+-    (MODE) = SImode;
+-
++      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
++    (MODE) = TARGET_MB_64 ? DImode : SImode;
++*/
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
+ #define FIRST_PARM_OFFSET(FNDECL)		(UNITS_PER_WORD)
+ 
+ #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
++#define DWARF_CIE_DATA_ALIGNMENT -1
+ 
+ #define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
+ 
+ #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
+ 
+-#define STACK_BOUNDARY				32
++#define STACK_BOUNDARY				(TARGET_MB_64 ? 64 : 32)
+ 
++#define PREFERRED_STACK_BOUNDARY		(TARGET_MB_64 ? 64 : 32)
++ 
+ #define NUM_OF_ARGS				6
+ 
+ #define GP_RETURN				(GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
+@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
+ #define LIBCALL_VALUE(MODE)						\
++  gen_rtx_REG (MODE,GP_RETURN)
++								
++/*#define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (								\
+ 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+ 	     || GET_MODE_SIZE (MODE) >= 4)				\
+ 	    ? (MODE)							\
+ 	    : SImode), GP_RETURN)
+-
++*/
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+@@ -500,7 +518,7 @@ typedef struct microblaze_args
+ /* 4 insns + 2 words of data.  */
+ #define TRAMPOLINE_SIZE				(6 * 4)
+ 
+-#define TRAMPOLINE_ALIGNMENT			32
++#define TRAMPOLINE_ALIGNMENT			64
+ 
+ #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
+ 
+@@ -529,13 +547,13 @@ typedef struct microblaze_args
+    addresses which require two reload registers.  */
+ #define LEGITIMATE_PIC_OPERAND_P(X)  microblaze_legitimate_pic_operand (X)
+ 
+-#define CASE_VECTOR_MODE			(SImode)
++#define CASE_VECTOR_MODE			(TARGET_MB_64? DImode:SImode)
+ 
+ #ifndef DEFAULT_SIGNED_CHAR
+ #define DEFAULT_SIGNED_CHAR			1
+ #endif
+ 
+-#define MOVE_MAX				4
++#define MOVE_MAX				(TARGET_MB_64 ? 8 : 4)
+ #define MAX_MOVE_MAX				8
+ 
+ #define SLOW_BYTE_ACCESS			1
+@@ -545,7 +563,7 @@ typedef struct microblaze_args
+ 
+ #define SHIFT_COUNT_TRUNCATED			1
+ 
+-#define Pmode SImode
++#define Pmode (TARGET_MB_64? DImode:SImode)
+ 
+ #define FUNCTION_MODE   SImode
+ 
+@@ -707,6 +725,7 @@ do {									\
+ 
+ #undef TARGET_ASM_OUTPUT_IDENT
+ #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
+ 
+ /* Default to -G 8 */
+ #ifndef MICROBLAZE_DEFAULT_GVALUE
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index eb52957..77627a7 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -26,6 +26,7 @@
+ ;; Constants
+ ;;----------------------------------------------------
+ (define_constants [
++  (R_Z         0)       ;; For reg r0
+   (R_SP        1)       ;; Stack pointer reg
+   (R_SR       15)       ;; Sub-routine return addr reg
+   (R_IR       14)       ;; Interrupt return addr reg
+@@ -541,6 +542,7 @@
+ 
+ ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
+ ;; Leave carry as is
++
+ (define_insn "addsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
+@@ -562,23 +564,38 @@
+ 
+ ;; Adding 2 DI operands in register or reg/imm
+ 
+-(define_insn "adddi3_long"
++(define_expand "adddi3"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(plus:DI (match_operand:DI 1 "register_operand" "")
++		 (match_operand:DI 2 "arith_plus_operand" "")))]
++""
++{
++  if (TARGET_MB_64) 
++   {
++     if (GET_CODE (operands[2]) == CONST_INT &&
++       INTVAL(operands[2]) < (long)-549755813888 &&
++	INTVAL(operands[2]) > (long)549755813887)
++      FAIL;
++   }
++})
++
++(define_insn "*adddi3_long"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
++	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+ 		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
+   "TARGET_MB_64"
+   "@
+-   addlk\t%0,%z1,%2
+-   addlik\t%0,%z1,%2"
+-  [(set_attr "type"	"arith,arith")
+-  (set_attr "mode"	"DI,DI")
++   addlk\t%0,%1,%2
++   addlik\t%0,%1,%2 #N10"
++  [(set_attr "type"	"darith,no_delay_arith")
++  (set_attr "mode"	"DI")
+   (set_attr "length"	"4,4")])
+ 
+-(define_insn "adddi3"
++(define_insn "*adddi3_all"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+ 		 (match_operand:DI 2 "arith_operand" "d,i")))]
+-  ""
++  "!TARGET_MB_64"
+   "@
+   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+   addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+@@ -605,7 +622,7 @@
+ (define_insn "iprefetch"
+   [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
+    (clobber (mem:BLK (scratch)))]
+-   "TARGET_PREFETCH"
++   "TARGET_PREFETCH && !TARGET_MB_64"
+   {
+     operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+     return "mfs\t%2,rpc\n\twic\t%2,r0";
+@@ -618,23 +635,33 @@
+ ;; Double Precision Subtraction
+ ;;----------------------------------------------------------------
+ 
+-(define_insn "subdi3_long"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
+-		  (match_operand:DI 2 "register_operand" "d,n")))]
++(define_expand "subdi3"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(minus:DI (match_operand:DI 1 "register_operand" "")
++		  (match_operand:DI 2 "arith_operand" "")))]
++""
++"
++{
++}")
++
++(define_insn "subsidi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
++		  (match_operand:DI 2 "arith_operand" "d,K,n")))]
+   "TARGET_MB_64"
+   "@
+    rsubl\t%0,%2,%1
+-   addlik\t%0,%z1,-%2"
+-  [(set_attr "type"	"darith")
+-  (set_attr "mode"	"DI,DI")
+-  (set_attr "length"	"4,4")])
++   addik\t%0,%z1,-%2
++   addik\t%0,%z1,-%2"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,4")])
+ 
+-(define_insn "subdi3"
++(define_insn "subdi3_small"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+ 		  (match_operand:DI 2 "register_operand" "d")))]
+-  ""
++  "!TARGET_MB_64"
+   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+   [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+@@ -663,7 +690,7 @@
+         (mult:DI
+          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -674,7 +701,7 @@
+         (mult:DI
+          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -685,7 +712,7 @@
+         (mult:DI
+          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -789,7 +816,7 @@
+                         (match_operand:SI 4 "arith_operand")])
+                       (label_ref (match_operand 5))
+                       (pc)))]
+-   "TARGET_HARD_FLOAT"
++   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+    [(set (match_dup 1) (match_dup 3))]
+ 
+   {
+@@ -819,6 +846,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "negsi_long"
++  [(set (match_operand:SI 0 "register_operand" "=d")
++	(neg:SI (match_operand:DI 1 "register_operand" "d")))]
++  ""
++  "rsubk\t%0,%1,r0"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"SI")
++  (set_attr "length"	"4")])
++
+ (define_insn "negdi2_long"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -847,16 +883,24 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_insn "one_cmpldi2_long"
++(define_expand "one_cmpldi2"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(not:DI (match_operand:DI 1 "register_operand" "")))]
++  ""
++  "
++{
++}")
++
++(define_insn ""
+   [(set (match_operand:DI 0 "register_operand" "=d")
+-	(not:DI (match_operand:DI 1 "register_operand" "d")))]
++	(not:DI (match_operand:DI 1 "arith_operand" "d")))]
+   "TARGET_MB_64"
+   "xorli\t%0,%1,-1"
+-  [(set_attr "type"	"arith")
++  [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
+-(define_insn "*one_cmpldi2"
++(define_insn ""
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
+   ""
+@@ -871,7 +915,8 @@
+ 	(not:DI (match_operand:DI 1 "register_operand" "")))]
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
++   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
++   && !TARGET_MB_64"
+ 
+   [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
+   (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
+@@ -883,18 +928,17 @@
+ ;;----------------------------------------------------------------
+ 
+ (define_insn "anddi3"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
+-		(match_operand:DI 2 "arith_operand" "d,K")))]
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
++		(match_operand:DI 2 "arith_operand" "d,K,I")))]
+   "TARGET_MB_64"
+   "@
+    andl\t%0,%1,%2
+-   andli\t%0,%1,%2 #andl1"
+-  ;; andli\t%0,%1,%2 #andl3
+-  ;; andli\t%0,%1,%2 #andl2
+-  [(set_attr "type"	"arith,arith")
+-  (set_attr "mode"	"DI,DI")
+-  (set_attr "length"	"4,4")])
++   andli\t%0,%1,%2 #andl2
++   andli\t%0,%1,%2 #andl3"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI,DI,DI")
++  (set_attr "length"	"4,4,4")])
+ 
+ (define_insn "andsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+@@ -919,7 +963,7 @@
+   "@
+    orl\t%0,%1,%2
+    orli\t%0,%1,%2 #andl1"
+-  [(set_attr "type"	"arith,arith")
++  [(set_attr "type"	"arith,no_delay_arith")
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")])
+ 
+@@ -945,7 +989,7 @@
+   "@
+    xorl\t%0,%1,%2
+    xorli\t%0,%1,%2 #andl1"
+-  [(set_attr "type"	"arith,arith")
++  [(set_attr "type"	"arith,no_delay_arith")
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")])
+ 
+@@ -1018,26 +1062,6 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-;;(define_expand "extendqidi2"
+-;;  [(set (match_operand:DI 0 "register_operand" "=d")
+-;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
+-;;  "TARGET_MB_64"
+-;;  {
+-;;	if (GET_CODE (operands[1]) != REG)
+-;;	FAIL;
+-;;   }
+-;;)
+-    
+-
+-;;(define_insn "extendqidi2"
+-;;  [(set (match_operand:DI 0 "register_operand" "=d")
+-;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
+-;;  "TARGET_MB_64"
+-;;  "sextl8\t%0,%1"
+-;;  [(set_attr "type"	"arith")
+-;;  (set_attr "mode"	"DI")
+-;;  (set_attr "length"	"4")])
+-
+ (define_insn "extendhisi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
+@@ -1060,6 +1084,27 @@
+ ;; Those for integer source operand are ordered
+ ;; widest source type first.
+ 
++(define_insn "extendsidi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
++  "TARGET_MB_64"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "sextl32\t%0,%1";
++      case 1:
++      case 2:
++        {
++          output_asm_insn ("ll%i1\t%0,%1", operands);
++          return "sextl32\t%0,%0";
++        }
++    } 
++  }
++  [(set_attr "type"	"multi,multi,multi")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,8,8")])
++
+ (define_insn "extendsidi2"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+@@ -1090,68 +1135,117 @@
+ ;; Unlike most other insns, the move insns can't be split with
+ ;; different predicates, because register spilling and other parts of
+ ;; the compiler, have memoized the insn number already.
++;;    //}
+ 
+ (define_expand "movdi"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ 	(match_operand:DI 1 "general_operand" ""))]
+   ""
+   {
+-    /* If operands[1] is a constant address illegal for pic, then we need to
+-       handle it just like microblaze_legitimize_address does.  */
+-    if (flag_pic && pic_address_needs_scratch (operands[1]))
++    if (TARGET_MB_64)
++    {
++      if (microblaze_expand_move (DImode, operands)) DONE;
++    }
++    else
+     {
++      /* If operands[1] is a constant address illegal for pic, then we need to
++         handle it just like microblaze_legitimize_address does. */ 
++      if (flag_pic && pic_address_needs_scratch (operands[1]))
++      {
+         rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
+         rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
+         emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
+         DONE;
+-    }
+-
+-
+-    if ((reload_in_progress | reload_completed) == 0
+-        && !register_operand (operands[0], DImode)
+-        && !register_operand (operands[1], DImode)
+-        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+-	       && operands[1] != CONST0_RTX (DImode))))
+-    {
++      }
+ 
+-      rtx temp = force_reg (DImode, operands[1]);
+-      emit_move_insn (operands[0], temp);
+-      DONE;
++      if ((reload_in_progress | reload_completed) == 0
++          && !register_operand (operands[0], DImode)
++          && !register_operand (operands[1], DImode)
++          && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
++  	       && operands[1] != CONST0_RTX (DImode))))
++      {
++        rtx temp = force_reg (DImode, operands[1]);
++        emit_move_insn (operands[0], temp);
++        DONE;
++      }
+     }
+   }
+ )
+ 
++;; Added for status registers
++(define_insn "movdi_status"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,z")
++        (match_operand:DI 1 "register_operand" "z,d,d"))]
++  "microblaze_is_interrupt_variant () && TARGET_MB_64"
++  "@
++	mfs\t%0,%1  #mfs
++	addlk\t%0,%1,r0 #add movdi
++	mts\t%0,%1  #mts"	
++  [(set_attr "type" "move")
++  (set_attr "mode" "DI")
++  (set_attr "length" "12")])
+ 
+-(define_insn "*movdi_internal_64"
+-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+-	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
+-  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
++;; This move will be not be moved to delay slot.	
++(define_insn "*movdi_internal3"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
++	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
++  "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
++           (GET_CODE (operands[1]) == CONST_INT && 
++                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
++  "@
++   addlk\t%0,r0,r0\t
++   addlik\t%0,r0,%1\t #N1 %X1
++   addlik\t%0,r0,%1\t #N2 %X1"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++;; This move may be used for PLT label operand
++(define_insn "*movdi_internal5_pltop"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(match_operand:DI 1 "call_insn_operand" ""))]
++  "TARGET_MB_64 && (register_operand (operands[0], Pmode) && 
++           PLT_ADDR_P (operands[1]))"
++  { 
++     gcc_unreachable ();
++  }
++  [(set_attr "type"	"load")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++(define_insn "*movdi_internal2"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64"
+   { 
+     switch (which_alternative)
+     {
+       case 0:
+-        return "addlk\t%0,%1";
+-      case 1:
+-	return "addlik\t%0,r0,%1";
+-      case 2:
+-	  return "addlk\t%0,r0,r0";
+-      case 3:
+-      case 4:
+-	  return "lli\t%0,%1";
+-      case 5:
+-      case 6:
+-        return "sli\t%1,%0";
+-    }
+-    return "unreachable";
+-  }
+-  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT && 
++	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
++ 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else	
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
+   (set_attr "mode"	"DI")
+-  (set_attr "length"   "8,8,8,8,12,8,12")])
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ 
+ (define_insn "*movdi_internal"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+ 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
+-  ""
++  "!TARGET_MB_64"
+   { 
+     switch (which_alternative)
+     {
+@@ -1183,7 +1277,8 @@
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
+-   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
++   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
++   && !(TARGET_MB_64)"
+ 
+   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
+   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
+@@ -1195,12 +1290,22 @@
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
+-   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
++   && !(TARGET_MB_64)"
+ 
+   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
+   "")
+ 
++(define_insn "movdi_long_int"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
++	(match_operand:DI 1 "general_operand"      "i"))]
++  ""
++  "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++  [(set_attr "type"	"no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"12")])
++
+ ;; Unlike most other insns, the move insns can't be split with
+ ;; different predicates, because register spilling and other parts of
+ ;; the compiler, have memoized the insn number already.
+@@ -1272,6 +1377,8 @@
+   (set_attr "length"	"4,4,8,4,8,4,8")])
+ 
+ 
++
++
+ ;; 16-bit Integer moves
+ 
+ ;; Unlike most other insns, the move insns can't be split with
+@@ -1304,8 +1411,8 @@
+   "@
+    addik\t%0,r0,%1\t# %X1
+    addk\t%0,%1,r0
+-   lhui\t%0,%1
+-   lhui\t%0,%1
++   lhu%i1\t%0,%1
++   lhu%i1\t%0,%1
+    sh%i0\t%z1,%0
+    sh%i0\t%z1,%0"
+   [(set_attr "type"	"arith,move,load,no_delay_load,store,no_delay_store")
+@@ -1348,7 +1455,7 @@
+    lbu%i1\t%0,%1
+    lbu%i1\t%0,%1
+    sb%i0\t%z1,%0
+-   sbi\t%z1,%0"
++   sb%i0\t%z1,%0"
+   [(set_attr "type"	"arith,arith,move,load,no_delay_load,store,no_delay_store")
+   (set_attr "mode"	"QI")
+   (set_attr "length"	"4,4,8,4,8,4,8")])
+@@ -1421,7 +1528,7 @@
+    addik\t%0,r0,%F1
+    lw%i1\t%0,%1
+    sw%i0\t%z1,%0
+-   swi\t%z1,%0"
++   sw%i0\t%z1,%0"
+   [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4,4,4,4,4,4,4")])
+@@ -1460,6 +1567,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
+         (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
+@@ -1494,7 +1628,8 @@
+   "reload_completed
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+-   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
++   && !TARGET_MB_64"
+   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
+   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
+   "")
+@@ -1505,7 +1640,8 @@
+   "reload_completed
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+-   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
++   && !TARGET_MB_64"
+   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
+   "")
+@@ -2005,6 +2141,31 @@ else
+   "
+ )
+ 
++
++(define_insn "seq_internal_pat_long" 
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(eq:DI 
++	       (match_operand:DI 1 "register_operand" "d")
++	       (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "pcmpleq\t%0,%1,%2"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"DI")
++   (set_attr "length"	"4")]
++)              
++
++(define_insn "sne_internal_pat_long" 
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(ne:DI 
++	       (match_operand:DI 1 "register_operand" "d")
++	       (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "pcmplne\t%0,%1,%2"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")]
++)              
++
+ (define_insn "seq_internal_pat" 
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(eq:SI 
+@@ -2065,8 +2226,8 @@ else
+ (define_expand "cbranchsi4"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand:SI 1 "register_operand")
+-                        (match_operand:SI 2 "arith_operand" "I,i")])
++                       [(match_operand 1 "register_operand")
++                        (match_operand 2 "arith_operand" "I,i")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+@@ -2078,13 +2239,13 @@ else
+ (define_expand "cbranchsi4_reg"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand:SI 1 "register_operand")
+-                        (match_operand:SI 2 "register_operand")])
++                       [(match_operand 1 "register_operand")
++                        (match_operand 2 "register_operand")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+ {
+-  microblaze_expand_conditional_branch_reg (SImode, operands);
++  microblaze_expand_conditional_branch_reg (Pmode, operands);
+   DONE;
+ })
+ 
+@@ -2109,6 +2270,26 @@ else
+ 		      (label_ref (match_operand 1))
+ 		      (pc)))])
+ 
++(define_insn "branch_zero64"
++  [(set (pc)
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
++  				 [(match_operand 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "bea%C0i%?\t%z1,%2";
++    else 
++      return "bea%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
+ (define_insn "branch_zero"
+   [(set (pc)
+ 	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
+@@ -2129,6 +2310,47 @@ else
+    (set_attr "length"	"4")]
+ )
+ 
++(define_insn "branch_compare64"
++  [(set (pc)
++        (if_then_else (match_operator 0 "cmp_op"
++                                         [(match_operand 1 "register_operand" "d")
++                                          (match_operand 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:SI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmp\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmp\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
++    return "bea%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ (define_insn "branch_compare"
+   [(set (pc)
+         (if_then_else (match_operator:SI 0 "cmp_op"
+@@ -2312,7 +2534,7 @@ else
+ ;; Indirect jumps. Jump to register values. Assuming absolute jumps
+ 
+ (define_insn "indirect_jump_internal1"
+-  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
++  [(set (pc) (match_operand 0 "register_operand" "d"))]
+   ""
+   "bra%?\t%0"
+   [(set_attr "type"	"jump")
+@@ -2325,7 +2547,7 @@ else
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   {
+-    gcc_assert (GET_MODE (operands[0]) == Pmode);
++    //gcc_assert (GET_MODE (operands[0]) == Pmode);
+ 
+     if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
+       emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+@@ -2337,7 +2559,7 @@ else
+ 
+ (define_insn "tablejump_internal1"
+   [(set (pc)
+-	(match_operand:SI 0 "register_operand" "d"))
++	(match_operand 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   "bra%?\t%0 "
+@@ -2347,9 +2569,9 @@ else
+ 
+ (define_expand "tablejump_internal3"
+   [(parallel [(set (pc)
+-		   (plus:SI (match_operand:SI 0 "register_operand" "d")
+-			    (label_ref:SI (match_operand:SI 1 "" ""))))
+-             (use (label_ref:SI (match_dup 1)))])]
++		   (plus (match_operand 0 "register_operand" "d")
++			    (label_ref (match_operand:SI 1 "" ""))))
++             (use (label_ref (match_dup 1)))])]
+   ""
+   ""
+ )
+@@ -2410,7 +2632,7 @@ else
+ 	(minus (reg 1) (match_operand 1 "register_operand" "")))
+    (set (reg 1)
+ 	(minus (reg 1) (match_dup 1)))]
+-  ""
++  "!TARGET_MB_64"
+   { 
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+     rtx reg = gen_reg_rtx (Pmode);
+@@ -2435,7 +2657,7 @@ else
+ (define_expand "save_stack_block"
+   [(match_operand 0 "register_operand" "")
+    (match_operand 1 "register_operand" "")]
+-  ""
++  "!TARGET_MB_64"
+   {
+     emit_move_insn (operands[0], operands[1]);
+     DONE;
+@@ -2445,7 +2667,7 @@ else
+ (define_expand "restore_stack_block"
+   [(match_operand 0 "register_operand" "")
+    (match_operand 1 "register_operand" "")]
+-  ""
++  "!TARGET_MB_64"
+   {
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+     rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
+@@ -2492,7 +2714,7 @@ else
+ 
+ (define_insn "<optab>_internal"
+   [(any_return)
+-   (use (match_operand:SI 0 "register_operand" ""))]
++   (use (match_operand 0 "register_operand" ""))]
+   ""
+   {
+     if (microblaze_is_break_handler ())
+@@ -2525,7 +2747,7 @@ else
+ (define_expand "call"
+   [(parallel [(call (match_operand 0 "memory_operand" "m")
+ 		    (match_operand 1 "" "i"))
+-             (clobber (reg:SI R_SR))
++             (clobber (reg R_SR))
+              (use (match_operand 2 "" ""))
+              (use (match_operand 3 "" ""))])]
+   ""
+@@ -2546,12 +2768,12 @@ else
+ 
+     if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
+       emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
+                                	     pic_offset_table_rtx));
+     else
+       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ 
+         DONE;
+@@ -2561,7 +2783,7 @@ else
+ (define_expand "call_internal0"
+   [(parallel [(call (match_operand 0 "" "")
+ 		    (match_operand 1 "" ""))
+-             (clobber (match_operand:SI 2 "" ""))])]
++             (clobber (match_operand 2 "" ""))])]
+   ""
+   {
+   }
+@@ -2570,18 +2792,34 @@ else
+ (define_expand "call_internal_plt0"
+   [(parallel [(call (match_operand 0 "" "")
+ 		    (match_operand 1 "" ""))
+-             (clobber (match_operand:SI 2 "" ""))
+-             (use (match_operand:SI 3 "" ""))])]
++             (clobber (match_operand 2 "" ""))
++             (use (match_operand 3 "" ""))])]
+   ""
+   {
+   }
+ )
+  
++(define_insn "call_internal_plt_64"
++  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))
++  (use (reg R_GOT))]
++  "flag_pic && TARGET_MB_64"
++  {
++    register rtx target2 = gen_rtx_REG (Pmode, 
++			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++    gen_rtx_CLOBBER (VOIDmode, target2);
++    return "brealid\tr15,%0\;%#";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_internal_plt"
+-  [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
+-	 (match_operand:SI 1 "" "i"))
+-  (clobber (reg:SI R_SR))
+-  (use (reg:SI R_GOT))]
++  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))
++  (use (reg R_GOT))]
+   "flag_pic"
+   {
+     register rtx target2 = gen_rtx_REG (Pmode, 
+@@ -2593,10 +2831,41 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "call_internal1_64"
++  [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))]
++  "TARGET_MB_64"
++  {
++    register rtx target = operands[0];
++    register rtx target2 = gen_rtx_REG (Pmode,
++			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++    if (GET_CODE (target) == SYMBOL_REF) {
++        if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
++            gen_rtx_CLOBBER (VOIDmode, target2);
++            return "breaki\tr16,%0\;%#";
++        }
++        else {
++            gen_rtx_CLOBBER (VOIDmode, target2);
++            return "brealid\tr15,%0\;%#";
++        }
++    } else if (GET_CODE (target) == CONST_INT)
++        return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
++    else if (GET_CODE (target) == REG)
++        return "brald\tr15,%0\;%#";	
++    else {
++        fprintf (stderr,"Unsupported call insn\n");
++        return NULL;
++    }
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_internal1"
+   [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
+-	 (match_operand:SI 1 "" "i"))
+-  (clobber (reg:SI R_SR))]
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))]
+   ""
+   {
+     register rtx target = operands[0];
+@@ -2630,7 +2899,7 @@ else
+   [(parallel [(set (match_operand 0 "register_operand" "=d")
+ 		   (call (match_operand 1 "memory_operand" "m")
+ 			 (match_operand 2 "" "i")))
+-             (clobber (reg:SI R_SR))
++             (clobber (reg R_SR))
+              (use (match_operand 3 "" ""))])] ;; next_arg_reg
+   ""
+   {
+@@ -2651,13 +2920,13 @@ else
+     if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
+       emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
+ 			operands[2],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
+ 				     pic_offset_table_rtx));
+     else
+       emit_call_insn (gen_call_value_internal (operands[0], operands[1], 
+ 			operands[2],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ 
+     DONE;
+@@ -2669,7 +2938,7 @@ else
+   [(parallel [(set (match_operand 0 "" "")
+ 		   (call (match_operand 1 "" "")
+ 			 (match_operand 2 "" "")))
+-             (clobber (match_operand:SI 3 "" ""))
++             (clobber (match_operand 3 "" ""))
+              ])]
+   ""
+   {}
+@@ -2679,18 +2948,35 @@ else
+   [(parallel[(set (match_operand 0 "" "")
+                   (call (match_operand 1 "" "")
+                         (match_operand 2 "" "")))
+-             (clobber (match_operand:SI 3 "" ""))
+-             (use (match_operand:SI 4 "" ""))])]
++             (clobber (match_operand 3 "" ""))
++             (use (match_operand 4 "" ""))])]
+   "flag_pic"
+   {}
+ )
+ 
++(define_insn "call_value_intern_plt_64"
++  [(set (match_operand:VOID 0 "register_operand" "=d")
++        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))
++   (use (match_operand 4 "register_operand"))]
++  "flag_pic && TARGET_MB_64"
++  { 
++    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++
++    gen_rtx_CLOBBER (VOIDmode,target2);
++    return "brealid\tr15,%1\;%#";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_value_intern_plt"
+   [(set (match_operand:VOID 0 "register_operand" "=d")
+-        (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
+-              (match_operand:SI 2 "" "i")))
+-   (clobber (match_operand:SI 3 "register_operand" "=d"))
+-   (use (match_operand:SI 4 "register_operand"))]
++        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))
++   (use (match_operand 4 "register_operand"))]
+   "flag_pic"
+   { 
+     register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
+@@ -2702,11 +2988,46 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "call_value_intern_64"
++  [(set (match_operand:VOID 0 "register_operand" "=d")
++        (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))]
++  "TARGET_MB_64"
++  { 
++    register rtx target = operands[1];
++    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++
++    if (GET_CODE (target) == SYMBOL_REF)
++    {
++      gen_rtx_CLOBBER (VOIDmode,target2);
++      if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
++        return "breaki\tr16,%1\;%#";
++      else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
++        {
++	  return "brealid\tr15,%1\;%#";
++        }
++      else
++        {
++	    return "bralid\tr15,%1\;%#";
++        }
++    }
++    else if (GET_CODE (target) == CONST_INT)
++        return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
++    else if (GET_CODE (target) == REG)
++        return "brald\tr15,%1\;%#";	
++    else 
++        return "Unsupported call insn\n";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_value_intern"
+   [(set (match_operand:VOID 0 "register_operand" "=d")
+         (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
+-              (match_operand:SI 2 "" "i")))
+-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))]
+   ""
+   { 
+     register rtx target = operands[1];
+@@ -2880,7 +3201,6 @@ else
+ 
+   ;;if (!register_operand (operands[0], VOIDmode))
+   ;;  FAIL;
+-
+   emit_insn (gen_insv_32 (operands[0], operands[1],
+ 			  operands[2], operands[3]));
+   DONE;
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 7671f63..9fc80b1 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
+ MULTILIB_DIRNAMES = bs m mh le m64
+ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
+-#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+-#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
+index ee380ee..1811327 100644
+--- a/libgcc/config/microblaze/crti.S
++++ b/libgcc/config/microblaze/crti.S
+@@ -40,7 +40,7 @@
+ 
+     .align 2
+ __init: 
+-    addik   r1, r1, -8
++    addik   r1, r1, -16
+     sw      r15, r0, r1
+     la      r11, r0, _stack
+     mts     rshr, r11
+@@ -51,5 +51,5 @@ __init:
+     .global __fini
+     .align 2
+ __fini: 
+-    addik   r1, r1, -8
++    addik   r1, r1, -16
+     sw      r15, r0, r1
+diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
+index 00d398a..60a4648 100644
+--- a/libgcc/config/microblaze/crtn.S
++++ b/libgcc/config/microblaze/crtn.S
+@@ -33,9 +33,9 @@
+     .section .init, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+-    addik   r1, r1, 8
++    addik   r1, r1, 16
+ 
+     .section .fini, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+-    addik   r1, r1, 8    
++    addik   r1, r1, 16   
+diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
+new file mode 100644
+index 0000000..d37bf51
+--- /dev/null
++++ b/libgcc/config/microblaze/divdi3.S
+@@ -0,0 +1,98 @@
++###################################-
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++#
++#  divdi3.S
++# 
++#  Divide operation for 32 bit integers.
++#	Input :	Dividend in Reg r5
++#		Divisor in Reg r6
++#	Output: Result in Reg r3
++# 
++#######################################
++
++#ifdef __arch64__	
++	.globl	__divdi3
++	.ent	__divdi3
++	.type	__divdi3,@function
++__divdi3:
++	.frame	r1,0,r15	
++
++	ADDLIK   r1,r1,-32
++	SLI     r28,r1,0
++	SLI     r29,r1,8
++	SLI     r30,r1,16
++	SLI     r31,r1,24
++
++	BEALEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEALEQI    r5,$LaResult_Is_Zero    # Result is Zero 
++	XORL     r28,r5,r6               # Get the sign of the result
++	BEALGEI   r5,$LaR5_Pos 
++	RSUBLI   r5,r5,0                 # Make r5 positive
++$LaR5_Pos:
++	BEALGEI    r6,$LaR6_Pos
++	RSUBLI   r6,r6,0                 # Make r6 positive
++$LaR6_Pos:
++	ADDLIK   r30,r0,0                # Clear mod
++	ADDLIK   r3,r0,0                 # clear div
++	ADDLIK   r29,r0,64               # Initialize the loop count
++
++        # First part try to find the first '1' in the r5
++$LaDIV0: 
++        BEALLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++$LaDIV1:
++	ADDL     r5,r5,r5                # left shift logical r5
++	ADDLIK   r29,r29,-1
++	BEALGTI   r5,$LaDIV1       
++$LaDIV2:
++	ADDL     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
++	ADDLC    r30,r30,r30             # Move that bit into the Mod register
++	RSUBL    r31,r6,r30              # Try to subtract (r30 a r6)
++	BEALLTI    r31,$LaMOD_TOO_SMALL
++	ORL      r30,r0,r31              # Move the r31 to mod since the result was positive
++	ADDLIK   r3,r3,1
++$LaMOD_TOO_SMALL:
++	ADDLIK   r29,r29,-1
++	BEALEQi    r29,$LaLOOP_END
++	ADDL     r3,r3,r3                # Shift in the '1' into div
++	BREAI     $LaDIV2                 # Div2
++$LaLOOP_END:
++	BEALGEI    r28,$LaRETURN_HERE
++	RSUBLI   r3,r3,0                 # Negate the result
++	BREAI    $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	ORL      r3,r0,r0 # set result to 0
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r28,r1,0
++	LLI     r29,r1,8
++	LLI     r30,r1,16
++	LLI     r31,r1,24
++	ADDLIK   r1,r1,32
++	RTSD    r15,8
++        nop
++.end __divdi3
++	.size	__divdi3, . - __divdi3
++#endif
+diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
+new file mode 100644
+index 0000000..8096259
+--- /dev/null
++++ b/libgcc/config/microblaze/divdi3_table.c
+@@ -0,0 +1,62 @@
++/*  Table for software lookup divide for Xilinx MicroBlaze.
++ 
++   Copyright (C) 2009-2017 Free Software Foundation, Inc.
++
++   Contributed by Michael Eager <eager@eagercon.com>.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++ 
++unsigned char _divdi3_table[] =
++{
++       0,   0/1,   0/2,   0/3,   0/4,   0/5,   0/6,   0/7, 
++     0/8,   0/9,  0/10,  0/11,  0/12,  0/13,  0/14,  0/15,
++       0,   1/1,   1/2,   1/3,   1/4,   1/5,   1/6,   1/7, 
++     1/8,   1/9,  1/10,  1/11,  1/12,  1/13,  1/14,  1/15,
++       0,   2/1,   2/2,   2/3,   2/4,   2/5,   2/6,   2/7, 
++     2/8,   2/9,  2/10,  2/11,  2/12,  2/13,  2/14,  2/15,
++       0,   3/1,   3/2,   3/3,   3/4,   3/5,   3/6,   3/7, 
++     3/8,   3/9,  3/10,  3/11,  3/12,  3/13,  3/14,  3/15,
++       0,   4/1,   4/2,   4/3,   4/4,   4/5,   4/6,   4/7, 
++     4/8,   4/9,  4/10,  4/11,  4/12,  4/13,  4/14,  4/15,
++       0,   5/1,   5/2,   5/3,   5/4,   5/5,   5/6,   5/7, 
++     5/8,   5/9,  5/10,  5/11,  5/12,  5/13,  5/14,  5/15,
++       0,   6/1,   6/2,   6/3,   6/4,   6/5,   6/6,   6/7, 
++     6/8,   6/9,  6/10,  6/11,  6/12,  6/13,  6/14,  6/15,
++       0,   7/1,   7/2,   7/3,   7/4,   7/5,   7/6,   7/7, 
++     7/8,   7/9,  7/10,  7/11,  7/12,  7/13,  7/14,  7/15,
++       0,   8/1,   8/2,   8/3,   8/4,   8/5,   8/6,   8/7, 
++     8/8,   8/9,  8/10,  8/11,  8/12,  8/13,  8/14,  8/15,
++       0,   9/1,   9/2,   9/3,   9/4,   9/5,   9/6,   9/7, 
++     9/8,   9/9,  9/10,  9/11,  9/12,  9/13,  9/14,  9/15,
++       0,  10/1,  10/2,  10/3,  10/4,  10/5,  10/6,  10/7, 
++    10/8,  10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
++       0,  11/1,  11/2,  11/3,  11/4,  11/5,  11/6,  11/7, 
++    11/8,  11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
++       0,  12/1,  12/2,  12/3,  12/4,  12/5,  12/6,  12/7, 
++    12/8,  12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
++       0,  13/1,  13/2,  13/3,  13/4,  13/5,  13/6,  13/7, 
++    13/8,  13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
++       0,  14/1,  14/2,  14/3,  14/4,  14/5,  14/6,  14/7, 
++    14/8,  14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
++       0,  15/1,  15/2,  15/3,  15/4,  15/5,  15/6,  15/7, 
++    15/8,  15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
++};
++
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+new file mode 100644
+index 0000000..5d3f7c0
+--- /dev/null
++++ b/libgcc/config/microblaze/moddi3.S
+@@ -0,0 +1,97 @@
++###################################
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  moddi3.S
++# 
++#  modulo operation for 32 bit integers.
++#	Input :	op1 in Reg r5
++#		op2 in Reg r6
++#	Output: op1 mod op2 in Reg r3
++# 
++#######################################
++
++#ifdef __arch64__
++	.globl	__moddi3
++	.ent	__moddi3
++	.type	__moddi3,@function
++__moddi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-32
++	sli	r28,r1,0
++	sli	r29,r1,8
++	sli	r30,r1,16
++	sli	r31,r1,32
++
++	BEALEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEALEQI	r5,$LaResult_Is_Zero    # Result is Zero 
++	ADDL	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
++	BEALGEI	r5,$LaR5_Pos 
++	RSUBLI	r5,r5,0	                # Make r5 positive
++$LaR5_Pos:
++	BEALGEI	r6,$LaR6_Pos
++	RSUBLI	r6,r6,0	    # Make r6 positive
++$LaR6_Pos:
++	ADDLIK	r3,r0,0      # Clear mod
++	ADDLIK	r30,r0,0     # clear div
++	ADDLIK	r29,r0,64    # Initialize the loop count
++	BEALLTI	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++			     # the first bit search.
++   # First part try to find the first '1' in the r5
++$LaDIV1:
++	ADDL	r5,r5,r5         # left shift logical r5
++	ADDLIK	r29,r29,-1
++	BEALGEI	r5,$LaDIV1       #
++$LaDIV2:
++	ADDL	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
++	ADDLC	r3,r3,r3         # Move that bit into the Mod register
++	rSUBL	r31,r6,r3        # Try to subtract (r30 a r6)
++	BEALLTi	r31,$LaMOD_TOO_SMALL
++	ORL	r3,r0,r31       # Move the r31 to mod since the result was positive
++	ADDLIK	r30,r30,1
++$LaMOD_TOO_SMALL:
++	ADDLIK	r29,r29,-1
++	BEALEQi	r29,$LaLOOP_END
++	ADDL	r30,r30,r30         # Shift in the '1' into div
++	BREAI	$LaDIV2          # Div2
++$LaLOOP_END:
++	BEALGEI	r28,$LaRETURN_HERE
++	rsubli	r3,r3,0 # Negate the result
++	BREAI	$LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	orl	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli	r28,r1,0
++	lli	r29,r1,8
++	lli	r30,r1,16
++	lli	r31,r1,24
++	addlik	r1,r1,32
++	rtsd	r15,8
++        nop
++        .end __moddi3
++	.size	__moddi3, . - __moddi3
++#endif
+diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
+new file mode 100644
+index 0000000..5677841
+--- /dev/null
++++ b/libgcc/config/microblaze/muldi3.S
+@@ -0,0 +1,73 @@
++/*###################################-*-asm*- 
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  muldi3.S
++# 
++#  Multiply operation for 32 bit integers.
++#	Input :	Operand1 in Reg r5
++#		Operand2 in Reg r6
++#	Output: Result [op1 * op2] in Reg r3
++# 
++#######################################*/
++
++#ifdef __arch64__
++	.globl	__muldi3
++	.ent	__muldi3
++	.type	__muldi3,@function
++__muldi3:
++	.frame	r1,0,r15
++	addl	r3,r0,r0
++	BEALEQI	r5,$L_Result_Is_Zero      # Multiply by Zero
++	BEALEQI	r6,$L_Result_Is_Zero      # Multiply by Zero
++	XORL	r4,r5,r6                  # Get the sign of the result
++	BEALGEI	r5,$L_R5_Pos 
++	RSUBLI	r5,r5,0	                  # Make r5 positive
++$L_R5_Pos:
++	BEALGEI	r6,$L_R6_Pos
++	RSUBLI	r6,r6,0	                  # Make r6 positive
++$L_R6_Pos:	
++	breai	$L1
++$L2:	
++	addl	r5,r5,r5
++$L1:	
++	srll	r6,r6
++	addlc	r7,r0,r0
++	bealeqi	r7,$L2
++	addl	r3,r3,r5	
++	bealnei	r6,$L2
++	beallti	r4,$L_NegateResult			
++	rtsd	r15,8
++	nop
++$L_NegateResult:
++	rsubl	r3,r3,r0
++	rtsd	r15,8
++	nop
++$L_Result_Is_Zero:
++	addli	r3,r0,0
++	rtsd	r15,8
++	nop
++	.end __muldi3
++	.size	__muldi3, . - __muldi3
++#endif
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 8d954a4..35021b2 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,11 +1,16 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
++			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
++        $(srcdir)/config/microblaze/divdi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+-        $(srcdir)/config/microblaze/muldi3_hard.S \
++        $(srcdir)/config/microblaze/moddi3.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
++        $(srcdir)/config/microblaze/muldi3.S \
+         $(srcdir)/config/microblaze/stack_overflow_exit.S \
+         $(srcdir)/config/microblaze/udivsi3.S \
++        $(srcdir)/config/microblaze/udivdi3.S \
+         $(srcdir)/config/microblaze/umodsi3.S \
+-        $(srcdir)/config/microblaze/divsi3_table.c
++        $(srcdir)/config/microblaze/umoddi3.S \
++        $(srcdir)/config/microblaze/divsi3_table.c \
+diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
+new file mode 100644
+index 0000000..c210fbc
+--- /dev/null
++++ b/libgcc/config/microblaze/udivdi3.S
+@@ -0,0 +1,107 @@
++###################################-
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  udivdi3.S
++# 
++#  Unsigned divide operation.
++#	Input :	Divisor in Reg r5
++#		Dividend in Reg r6
++#	Output: Result in Reg r3
++# 
++#######################################
++	
++#ifdef __arch64__
++	.globl	__udivdi3
++	.ent	__udivdi3
++	.type	__udivdi3,@function
++__udivdi3:
++	.frame	r1,0,r15	
++
++	ADDlIK   r1,r1,-24
++    	SLI     r29,r1,0
++	SLI     r30,r1,8
++	SLI     r31,r1,16
++
++	BEALEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++	ADDLIK   r30,r0,0                    # Clear mod
++	BEALEQI   r5,$LaResult_Is_Zero        # Result is Zero 
++	ADDLIK   r29,r0,64                   # Initialize the loop count
++
++        # Check if r6 and r5 are equal # if yes, return 1
++	RSUBL 	r18,r5,r6
++	ADDLIK	r3,r0,1
++	BEALEQI	r18,$LaRETURN_HERE
++
++        # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
++	XORL	r18,r5,r6
++	ADDL	r3,r0,r0                    # We would anyways clear r3
++	BEALGEI	r18,$LRSUBL
++	BEALLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++	BREAI	$LCheckr6
++$LRSUBL:
++	RSUBL	r18,r6,r5                   # MICROBLAZEcmp
++	BEALLTI	r18,$LaRETURN_HERE
++
++        # If r6 [bit 31] is set, then return result as 1
++$LCheckr6:
++	BEALGTI	r6,$LaDIV0
++	ADDLIK	r3,r0,1
++	BREAI	$LaRETURN_HERE
++
++        # First part try to find the first '1' in the r5
++$LaDIV0:
++	BEALLTI    r5,$LaDIV2	
++$LaDIV1:
++	ADDL     r5,r5,r5                    # left shift logical r5
++	ADDLIK   r29,r29,-1
++	BEALGTI   r5,$LaDIV1       
++$LaDIV2:
++	ADDL     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
++	ADDLC    r30,r30,r30                 # Move that bit into the Mod register
++	RSUBL    r31,r6,r30                  # Try to subtract (r30 a r6)
++    	BEALLTI    r31,$LaMOD_TOO_SMALL
++	ORL      r30,r0,r31                  # Move the r31 to mod since the result was positive
++	ADDLIK   r3,r3,1
++$LaMOD_TOO_SMALL:
++	ADDLIK   r29,r29,-1
++	BEALEQi    r29,$LaLOOP_END
++	ADDL     r3,r3,r3 # Shift in the '1' into div
++	BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++	BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	ORL      r3,r0,r0 # set result to 0
++$LaRETURN_HERE:
++        # Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r29,r1,0
++	LLI     r30,r1,8
++	LLI     r31,r1,16
++	ADDLIK   r1,r1,24
++	RTSD    r15,8
++        NOP
++        .end __udivdi3
++	.size	__udivdi3, . - __udivdi3
++#endif
+diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
+new file mode 100644
+index 0000000..7f5cd23
+--- /dev/null
++++ b/libgcc/config/microblaze/umoddi3.S
+@@ -0,0 +1,110 @@
++###################################
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  umoddi3.S
++#
++#  Unsigned modulo operation for 32 bit integers.
++#	Input :	op1 in Reg r5
++#		op2 in Reg r6
++#	Output: op1 mod op2 in Reg r3
++# 
++#######################################
++	
++#ifdef __arch64__
++	.globl	__umoddi3
++	.ent	__umoddi3
++	.type	__umoddi3,@function
++__umoddi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-24
++	sli	r29,r1,0
++	sli	r30,r1,8
++	sli	r31,r1,16
++
++	BEALEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++	ADDLIK 	r3,r0,0                  # Clear div
++	BEALEQI	r5,$LaResult_Is_Zero     # Result is Zero 
++	ADDLIK 	r30,r0,0     	# clear mod
++	ADDLIK 	r29,r0,64       # Initialize the loop count
++
++# Check if r6 and r5 are equal # if yes, return 0
++	rsubl 	r18,r5,r6
++	bealeqi	r18,$LaRETURN_HERE
++
++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
++	xorl	r18,r5,r6
++	addlik	r3,r5,0
++	bealgei	r18,$LRSUB
++	beallti	r6,$LaRETURN_HERE
++	breai	$LCheckr6
++$LRSUB:
++	rsubl	r18,r5,r6 # MICROBLAZEcmp
++	bealgti	r18,$LaRETURN_HERE
++
++# If r6 [bit 31] is set, then return result as r5-r6
++$LCheckr6:
++	addlik	r3,r0,0
++	bealgti	r6,$LaDIV0
++	addlik	r18,r0,0x7fffffff
++	andl	r5,r5,r18
++	andl 	r6,r6,r18
++	breaid	$LaRETURN_HERE
++	rsubl	r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++	BEALLTI	r5,$LaDIV2
++$LaDIV1:
++	ADDL 	r5,r5,r5     # left shift logical r5
++	ADDLIK 	r29,r29,-1
++	BEALGEI 	r5,$LaDIV1   #
++$LaDIV2:
++	ADDL 	r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++	ADDLC 	r3,r3,r3     # Move that bit into the Mod register
++	rSUBL 	r31,r6,r3    # Try to subtract (r3 a r6)
++	BEALLTi 	r31,$LaMOD_TOO_SMALL
++	ORL  	r3,r0,r31    # Move the r31 to mod since the result was positive
++	ADDLIK 	r30,r30,1
++$LaMOD_TOO_SMALL:
++	ADDLIK 	r29,r29,-1
++	BEALEQi 	r29,$LaLOOP_END
++	ADDL 	r30,r30,r30 # Shift in the '1' into div
++	BREAI 	$LaDIV2     # Div2
++$LaLOOP_END:
++	BREAI 	$LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	orl 	r3,r0,r0   # set result to 0
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli 	r29,r1,0
++	lli 	r30,r1,8
++	lli 	r31,r1,16
++	addlik 	r1,r1,24
++	rtsd 	r15,8
++        nop
++.end __umoddi3
++	.size	__umoddi3, . - __umoddi3
++#endif
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0042-re-arrangement-of-the-compare-branches.patch
new file mode 100644
index 00000000..3afb7629
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0042-re-arrangement-of-the-compare-branches.patch
@@ -0,0 +1,268 @@
+From 31062878a2c1773a1fc94242ad29e6d03e4828b1 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 3 Aug 2018 15:41:39 +0530
+Subject: [PATCH 42/63] re-arrangement of the compare branches
+
+---
+ gcc/config/microblaze/microblaze.c  |  28 ++-----
+ gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++-------------------
+ 2 files changed, 73 insertions(+), 96 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index d5ff7af..dd46d93 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3835,11 +3835,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == Pmode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
+-
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+ 
+   else if (code == EQ || code == NE)
+@@ -3850,10 +3846,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+       else
+         emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else
+     {
+@@ -3886,10 +3879,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code),
+                                   mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else if (code == EQ)
+     {
+@@ -3904,10 +3894,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+                                            cmp_op1));
+ 	}
+       condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+  
+     }
+   else if (code == NE)
+@@ -3923,10 +3910,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+                                            cmp_op1));
+ 	}
+       condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else
+     {
+@@ -3968,7 +3952,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+ 
+   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+   condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+-  emit_jump_insn (gen_long_condjump (condition, operands[3]));
++  emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
+ /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 77627a7..edb7aab 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2270,7 +2270,27 @@ else
+ 		      (label_ref (match_operand 1))
+ 		      (pc)))])
+ 
+-(define_insn "branch_zero64"
++(define_insn "branch_zero_64"
++  [(set (pc)
++	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++  				 [(match_operand:SI 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand:SI 2 "pc_or_label_operand" "")
++                      (match_operand:SI 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "bea%C0i%?\t%z1,%2";
++    else 
++      return "bea%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
++(define_insn "long_branch_zero"
+   [(set (pc)
+ 	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand 1 "register_operand" "d")
+@@ -2281,9 +2301,9 @@ else
+   "TARGET_MB_64"
+   {
+     if (operands[3] == pc_rtx) 
+-      return "bea%C0i%?\t%z1,%2";
++      return "beal%C0i%?\t%z1,%2";
+     else 
+-      return "bea%N0i%?\t%z1,%3";
++      return "beal%N0i%?\t%z1,%3";
+   }
+   [(set_attr "type"	"branch")
+    (set_attr "mode"	"none")
+@@ -2312,9 +2332,9 @@ else
+ 
+ (define_insn "branch_compare64"
+   [(set (pc)
+-        (if_then_else (match_operator 0 "cmp_op"
+-                                         [(match_operand 1 "register_operand" "d")
+-                                          (match_operand 2 "register_operand" "d")
++        (if_then_else (match_operator:SI 0 "cmp_op"
++                                         [(match_operand:SI 1 "register_operand" "d")
++                                          (match_operand:SI 2 "register_operand" "d")
+                                          ])
+                       (label_ref (match_operand 3))
+                       (pc)))
+@@ -2351,6 +2371,47 @@ else
+    (set_attr "length"   "12")]
+ )
+ 
++(define_insn "long_branch_compare"
++  [(set (pc)
++        (if_then_else (match_operator 0 "cmp_op"
++                                         [(match_operand 1 "register_operand" "d")
++                                          (match_operand 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:DI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
++    return "beal%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ (define_insn "branch_compare"
+   [(set (pc)
+         (if_then_else (match_operator:SI 0 "cmp_op"
+@@ -2433,74 +2494,6 @@ else
+ 
+ })
+ 
+-;; Used to implement comparison instructions
+-(define_expand "long_condjump"
+-  [(set (pc)
+-	(if_then_else (match_operand 0)
+-		      (label_ref (match_operand 1))
+-		      (pc)))])
+-
+-(define_insn "long_branch_zero"
+-  [(set (pc)
+-	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
+-  				 [(match_operand:DI 1 "register_operand" "d")
+-                                  (const_int 0)])
+-                      (match_operand:DI 2 "pc_or_label_operand" "")
+-                      (match_operand:DI 3 "pc_or_label_operand" "")))
+-  ]
+-  "TARGET_MB_64"
+-  {
+-    if (operands[3] == pc_rtx) 
+-      return "beal%C0i%?\t%z1,%2";
+-    else 
+-      return "beal%N0i%?\t%z1,%3";
+-  }
+-  [(set_attr "type"	"branch")
+-   (set_attr "mode"	"none")
+-   (set_attr "length"	"4")]
+-)
+-
+-(define_insn "long_branch_compare"
+-  [(set (pc)
+-        (if_then_else (match_operator:DI 0 "cmp_op"
+-                                         [(match_operand:DI 1 "register_operand" "d")
+-                                          (match_operand:DI 2 "register_operand" "d")
+-                                         ])
+-                      (label_ref (match_operand 3))
+-                      (pc)))
+-  (clobber(reg:DI R_TMP))]
+-  "TARGET_MB_64"
+-  {
+-    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
+-    enum rtx_code code = GET_CODE (operands[0]);
+-
+-    if (code == GT || code == LE)
+-      {
+-        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
+-        code = swap_condition (code);
+-      }
+-    else if (code == GTU || code == LEU)
+-      {
+-        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
+-        code = swap_condition (code);
+-      }
+-    else if (code == GE || code == LT)
+-      {
+-        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
+-      }
+-    else if (code == GEU || code == LTU)
+-      {
+-        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
+-      }
+-
+-    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
+-    return "beal%C0i%?\tr18,%3";
+-  }
+-  [(set_attr "type"     "branch")
+-   (set_attr "mode"     "none")
+-   (set_attr "length"   "12")]
+-)
+-
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
new file mode 100644
index 00000000..f4074899
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -0,0 +1,28 @@
+From 7ab47599c2bec80d622883b3e220827dce89c598 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 8 Aug 2018 17:37:26 +0530
+Subject: [PATCH 43/63] [Patch,Microblaze] :  previous commit broke the
+ handling of SI Branch compare for Microblaze 32-bit..
+
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index edb7aab..fb22edb 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2226,8 +2226,8 @@ else
+ (define_expand "cbranchsi4"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand 1 "register_operand")
+-                        (match_operand 2 "arith_operand" "I,i")])
++                       [(match_operand:SI 1 "register_operand")
++                        (match_operand:SI 2 "arith_operand" "I,i")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
new file mode 100644
index 00000000..ad287e57
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -0,0 +1,73 @@
+From 23622921a153258de469ff10db4926b83ff0c432 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 11 Sep 2018 13:43:48 +0530
+Subject: [PATCH 44/63] [Patch, Microblaze] : Support of multilibs with m64 ...
+
+---
+ gcc/config/microblaze/microblaze-c.c  |  1 +
+ gcc/config/microblaze/t-microblaze    | 15 ++++++---------
+ libgcc/config/microblaze/t-microblaze | 11 +++--------
+ 3 files changed, 10 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
+index d2b0c76..6670091 100644
+--- a/gcc/config/microblaze/microblaze-c.c
++++ b/gcc/config/microblaze/microblaze-c.c
+@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
+     }
+   if (TARGET_MB_64)
+     {
++      builtin_define ("__microblaze64");
+       builtin_define ("__arch64__");
+       builtin_define ("__microblaze64__");
+       builtin_define ("__MICROBLAZE64__");
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 9fc80b1..35ab9654 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,12 +1,9 @@
+-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
+-MULTILIB_DIRNAMES = bs m mh le m64
+-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
+-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
++MULTILIB_DIRNAMES = m64 bs le m mh
++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 35021b2..8d954a4 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,16 +1,11 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
+-			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
+-        $(srcdir)/config/microblaze/divdi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+-        $(srcdir)/config/microblaze/moddi3.S \
++        $(srcdir)/config/microblaze/muldi3_hard.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
+-        $(srcdir)/config/microblaze/muldi3.S \
+         $(srcdir)/config/microblaze/stack_overflow_exit.S \
+         $(srcdir)/config/microblaze/udivsi3.S \
+-        $(srcdir)/config/microblaze/udivdi3.S \
+         $(srcdir)/config/microblaze/umodsi3.S \
+-        $(srcdir)/config/microblaze/umoddi3.S \
+-        $(srcdir)/config/microblaze/divsi3_table.c \
++        $(srcdir)/config/microblaze/divsi3_table.c
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0045-Fixed-issues-like.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0045-Fixed-issues-like.patch
new file mode 100644
index 00000000..3f5f7827
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0045-Fixed-issues-like.patch
@@ -0,0 +1,70 @@
+From 6e6fcbe5fafcbebaf63ff071ad947966af0c1559 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 14:58:00 +0530
+Subject: [PATCH 45/63] Fixed issues like: 1 Interrupt alignment issue 2 Sign
+ extension issue
+
+---
+ gcc/config/microblaze/microblaze.c  | 16 ++++++++++------
+ gcc/config/microblaze/microblaze.md |  2 +-
+ 2 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index dd46d93..bfa667b 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2317,9 +2317,14 @@ compute_frame_size (HOST_WIDE_INT size)
+ 
+   total_size += gp_reg_size;
+ 
+-  /* Add 4 bytes for MSR.  */
++  /* Add 4/8 bytes for MSR.  */
+   if (microblaze_is_interrupt_variant ())
+-    total_size += 4;
++    {
++      if (TARGET_MB_64)
++        total_size += 8;
++      else
++        total_size += 4;
++    }
+ 
+   /* No space to be allocated for link register in leaf functions with no other
+      stack requirements.  */
+@@ -2604,7 +2609,6 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
+-      int val1[2];
+       long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+@@ -2619,10 +2623,10 @@ print_operand (FILE * file, rtx op, int letter)
+ 	}
+       else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
+         {
+-	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+-	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
++	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
++	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+         }
+-      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
++      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+     }
+   else if (code == CONST_DOUBLE)
+     {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index fb22edb..4a8fbab 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1096,7 +1096,7 @@
+       case 1:
+       case 2:
+         {
+-          output_asm_insn ("ll%i1\t%0,%1", operands);
++          output_asm_insn ("lw%i1\t%0,%1", operands);
+           return "sextl32\t%0,%0";
+         }
+     } 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0046-Fixed-below-issues.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0046-Fixed-below-issues.patch
new file mode 100644
index 00000000..fc2fe3b5
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0046-Fixed-below-issues.patch
@@ -0,0 +1,307 @@
+From 7c911a5ae8cf4a7496c059374f170f1919c00f6d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 26 Nov 2019 17:26:15 +0530
+Subject: [PATCH 46/63] Fixed below issues:
+
+- Floating point print issues in 64bit mode
+- Dejagnu Jump related issues
+- Added dbl instruction
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
+---
+ gcc/config/microblaze/microblaze.c  | 12 +++++-
+ gcc/config/microblaze/microblaze.h  |  7 +++
+ gcc/config/microblaze/microblaze.md | 86 +++++++++++++++++++++++++++++++------
+ libgcc/config/microblaze/crti.S     | 24 ++++++++++-
+ libgcc/config/microblaze/crtn.S     | 13 ++++++
+ 5 files changed, 125 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index bfa667b..220e03d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2613,7 +2613,12 @@ print_operand (FILE * file, rtx op, int letter)
+       if (code == CONST_DOUBLE)
+ 	{
+ 	  if (GET_MODE (op) == DFmode)
+-	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++            {
++  	      if (TARGET_MB_64)
++	        REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++	      else
++	        REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++	    }
+ 	  else
+ 	    {
+               REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
+@@ -4014,7 +4019,10 @@ microblaze_expand_divide (rtx operands[])
+                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+-  jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
++  if (TARGET_MB_64) 
++    jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
++  else 
++    jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+   JUMP_LABEL (jump) = div_end_label;
+   LABEL_NUSES (div_end_label) = 1; 
+   emit_barrier ();
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index a23fd4e..7497cfb 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -888,10 +888,17 @@ do {									 \
+ /* We do this to save a few 10s of code space that would be taken up
+    by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
+    definition in crtstuff.c.  */
++#ifdef __arch64__
++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
++    asm ( SECTION_OP "\n"                               \
++          "\tbrealid   r15, " #FUNC "\n\t nop\n"         \
++          TEXT_SECTION_ASM_OP);
++#else
+ #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
+     asm ( SECTION_OP "\n"                               \
+           "\tbrlid   r15, " #FUNC "\n\t nop\n"         \
+           TEXT_SECTION_ASM_OP);
++#endif
+ 
+ /* We need to group -lm as well, since some Newlib math functions 
+    reference __errno!  */
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4a8fbab..65ec32c 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -527,6 +527,15 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "floatdidf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (float:DF (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dbl\t%0,%1"
++  [(set_attr "type"     "fcvt")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+@@ -1300,7 +1309,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  ""
++  "TARGET_MB_64"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1583,7 +1592,7 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -2373,9 +2382,9 @@ else
+ 
+ (define_insn "long_branch_compare"
+   [(set (pc)
+-        (if_then_else (match_operator 0 "cmp_op"
+-                                         [(match_operand 1 "register_operand" "d")
+-                                          (match_operand 2 "register_operand" "d")
++        (if_then_else (match_operator:DI 0 "cmp_op"
++                                         [(match_operand:DI 1 "register_operand" "d")
++                                          (match_operand:DI 2 "register_operand" "d")
+                                          ])
+                       (label_ref (match_operand 3))
+                       (pc)))
+@@ -2497,6 +2506,20 @@ else
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
++(define_insn "jump_64"
++  [(set (pc)
++	(label_ref (match_operand 0 "" "")))]
++  "TARGET_MB_64"
++  {
++    if (GET_CODE (operands[0]) == REG)
++        return "brea%?\t%0";
++    else	
++        return "breai%?\t%l0";
++  }
++  [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "jump"
+   [(set (pc)
+ 	(label_ref (match_operand 0 "" "")))]
+@@ -2542,17 +2565,25 @@ else
+   {
+     //gcc_assert (GET_MODE (operands[0]) == Pmode);
+ 
+-    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
+-      emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+-    else
+-      emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
++    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
++        if (!TARGET_MB_64)
++          emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
++        else
++          emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
++      }
++    else {
++        if (!TARGET_MB_64)
++          emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
++        else
++          emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
++      }
+     DONE;
+   }
+ )
+ 
+ (define_insn "tablejump_internal1"
+   [(set (pc)
+-	(match_operand 0 "register_operand" "d"))
++	(match_operand:SI 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   "bra%?\t%0 "
+@@ -2560,11 +2591,21 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "tablejump_internal2"
++  [(set (pc)
++	(match_operand:DI 0 "register_operand" "d"))
++  (use (label_ref (match_operand 1 "" "")))]
++  "TARGET_MB_64"
++  "bra%?\t%0 "
++  [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_expand "tablejump_internal3"
+   [(parallel [(set (pc)
+-		   (plus (match_operand 0 "register_operand" "d")
+-			    (label_ref (match_operand:SI 1 "" ""))))
+-             (use (label_ref (match_dup 1)))])]
++		   (plus:SI (match_operand:SI 0 "register_operand" "d")
++			    (label_ref:SI (match_operand:SI 1 "" ""))))
++             (use (label_ref:SI (match_dup 1)))])]
+   ""
+   ""
+ )
+@@ -2595,6 +2636,23 @@ else
+   ""
+ )
+ 
++(define_insn ""
++ [(set (pc)
++	(plus:DI (match_operand:DI 0 "register_operand" "d")
++		 (label_ref:DI (match_operand 1 "" ""))))
++  (use (label_ref:DI (match_dup 1)))]
++ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
++  && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
++  && flag_pic"
++  {
++    output_asm_insn ("addlk\t%0,%0,r20",operands);
++    return "bra%?\t%0";
++}
++ [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
++
+ ;;----------------------------------------------------------------
+ ;; Function prologue/epilogue and stack allocation
+ ;;----------------------------------------------------------------
+@@ -3101,7 +3159,7 @@ else
+ ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
+ ;; between "mfs" and "addik" instructions.
+ (define_insn "set_got"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
++  [(set (match_operand 0 "register_operand" "=r")
+     (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
+   ""
+   "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
+diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
+index 1811327..a661319 100644
+--- a/libgcc/config/microblaze/crti.S
++++ b/libgcc/config/microblaze/crti.S
+@@ -33,11 +33,32 @@
+     .section .init, "ax"
+     .global __init
+ 
++#ifdef __arch64__
+     .weak _stack
+-    .set  _stack, 0xffffffff
++    .set  _stack, 0xffffffffffffffff
+     .weak _stack_end
+     .set  _stack_end, 0
+ 
++    .align 3
++__init: 
++    addlik  r1, r1, -32
++    sl      r15, r0, r1
++    addlik  r11, r0, _stack
++    mts     rshr, r11
++    addlik  r11, r0, _stack_end
++    mts     rslr, r11
++
++    .section .fini, "ax"
++    .global __fini
++    .align 3
++__fini: 
++    addlik   r1, r1, -32
++    sl       r15, r0, r1
++#else
++    .weak _stack
++    .set  _stack, 0xffffffff
++    .weak _stack_end
++    .set  _stack_end, 0
+     .align 2
+ __init: 
+     addik   r1, r1, -16
+@@ -53,3 +74,4 @@ __init:
+ __fini: 
+     addik   r1, r1, -16
+     sw      r15, r0, r1
++#endif
+diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
+index 60a4648..d72507b 100644
+--- a/libgcc/config/microblaze/crtn.S
++++ b/libgcc/config/microblaze/crtn.S
+@@ -29,7 +29,19 @@
+ .section .note.GNU-stack,"",%progbits
+ .previous
+ #endif
++#ifdef __arch64__
++    .section .init, "ax"
++    ll      r15, r0, r1
++    addlik   r1, r1, 32
++    rtsd    r15, 8
++    nop 
+ 
++    .section .fini, "ax"
++    ll      r15, r0, r1
++    addlik   r1, r1, 32   
++    rtsd    r15, 8
++    nop 
++#else
+     .section .init, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+@@ -39,3 +51,4 @@
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+     addik   r1, r1, 16   
++#endif
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0047-Added-double-arith-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0047-Added-double-arith-instructions.patch
new file mode 100644
index 00000000..1b7ac28b
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0047-Added-double-arith-instructions.patch
@@ -0,0 +1,135 @@
+From 0f310964ff1c19cbc3404ec7ceba286d6de315c0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:07:08 +0530
+Subject: [PATCH 47/63] -Added double arith instructions -Fixed prologue stack
+ pointer decrement issue
+
+---
+ gcc/config/microblaze/microblaze.md | 78 ++++++++++++++++++++++++++++++++-----
+ gcc/config/microblaze/t-microblaze  |  7 ++++
+ 2 files changed, 76 insertions(+), 9 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 65ec32c..c199b27 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -527,6 +527,66 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "fix_truncsfsi2"
++  [(set (match_operand:SI 0 "register_operand" "=d")
++        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
++  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
++  "fint\t%0,%1"
++  [(set_attr "type"     "fint")
++  (set_attr "mode"      "SF")
++  (set_attr "length"    "4")])
++
++
++(define_insn "adddf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (plus:DF (match_operand:DF 1 "register_operand" "d")
++                 (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dadd\t%0,%1,%2"
++  [(set_attr "type"     "fadd")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "subdf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (minus:DF (match_operand:DF 1 "register_operand" "d")
++                  (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "drsub\t%0,%2,%1"
++  [(set_attr "type"     "frsub")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "muldf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (mult:DF (match_operand:DF 1 "register_operand" "d")
++                 (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dmul\t%0,%1,%2"
++  [(set_attr "type"     "fmul")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "divdf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (div:DF (match_operand:DF 1 "register_operand" "d")
++                (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "ddiv\t%0,%2,%1"
++  [(set_attr "type"     "fdiv")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++
++(define_insn "sqrtdf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dsqrt\t%0,%1"
++  [(set_attr "type"     "fsqrt")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+@@ -536,13 +596,13 @@
+   (set_attr "mode"      "DF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "fix_truncsfsi2"
+-  [(set (match_operand:SI 0 "register_operand" "=d")
+-        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+-  "fint\t%0,%1"
+-  [(set_attr "type"     "fint")
+-  (set_attr "mode"      "SF")
++(define_insn "floatdfdi2"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (float:DI (match_operand:DF 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dlong\t%0,%1"
++  [(set_attr "type"     "fcvt")
++  (set_attr "mode"      "DI")
+   (set_attr "length"    "4")])
+ 
+ ;;----------------------------------------------------------------
+@@ -660,8 +720,8 @@
+   "TARGET_MB_64"
+   "@
+    rsubl\t%0,%2,%1
+-   addik\t%0,%z1,-%2
+-   addik\t%0,%z1,-%2"
++   addlik\t%0,%z1,-%2
++   addlik\t%0,%z1,-%2"
+   [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4,4,4")])
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 35ab9654..dfef45c 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,6 +1,13 @@
+ MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
+ MULTILIB_DIRNAMES = m64 bs le m mh
+ MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
new file mode 100644
index 00000000..c00b0a2b
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -0,0 +1,37 @@
+From b63cd2a410b9350fa67ed3ca348dcca349da4e44 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 12 Oct 2018 16:07:36 +0530
+Subject: [PATCH 48/63] Fixed the issue in the delay slot with swap
+ instructions
+
+---
+ gcc/config/microblaze/microblaze.md | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index c199b27..d6370d8 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -443,6 +443,9 @@
+         (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+   "TARGET_REORDER"
+   "swapb %0, %1"
++  [(set_attr "type"	"no_delay_arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"4")]
+ )
+ 
+ (define_insn "bswaphi2"
+@@ -451,6 +454,9 @@
+   "TARGET_REORDER"
+   "swapb %0, %1
+    swaph %0, %0"
++  [(set_attr "type"	"no_delay_arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"8")]
+ )
+ 
+ ;;----------------------------------------------------------------
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
new file mode 100644
index 00000000..7e92df2e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -0,0 +1,256 @@
+From f39f36cb0f0466343ef4ead50261b58595af708c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sat, 13 Oct 2018 21:12:43 +0530
+Subject: [PATCH 49/63] Fixed the load store issue with the 32bit arith
+ libraries
+
+---
+ libgcc/config/microblaze/divsi3.S  | 25 ++++++++++++++++++++++++-
+ libgcc/config/microblaze/modsi3.S  | 26 +++++++++++++++++++++++++-
+ libgcc/config/microblaze/mulsi3.S  |  3 +++
+ libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
+ libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
+ 5 files changed, 98 insertions(+), 4 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index 24b94b9..2765e42 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -41,6 +41,17 @@
+ 	.globl	__divsi3
+ 	.ent	__divsi3
+ 	.type	__divsi3,@function
++#ifdef __arch64__
++        .align 3
++__divsi3:
++	.frame	r1,0,r15	
++
++	ADDIK   r1,r1,-32
++	SLI     r28,r1,0
++	SLI     r29,r1,8
++	SLI     r30,r1,16
++	SLI     r31,r1,24
++#else
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -49,7 +60,7 @@ __divsi3:
+ 	SWI     r29,r1,4
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+-
++#endif
+ 	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEID   r5,$LaR5_Pos 
+@@ -89,6 +100,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r28,r1,0
++	LLI     r29,r1,8
++	LLI     r30,r1,16
++	LLI     r31,r1,24
++	ADDLIK  r1,r1,32
++	RTSD    r15,8
++	NOP
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	LWI     r28,r1,0
+@@ -97,6 +119,7 @@ $LaRETURN_HERE:
+ 	LWI     r31,r1,12
+ 	RTSD    r15,8
+ 	ADDIK   r1,r1,16
++#endif
+ .end __divsi3
+ 	.size	__divsi3, . - __divsi3
+ 
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 87372f5..7e61453 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -41,6 +41,17 @@
+ 	.globl	__modsi3
+ 	.ent	__modsi3
+ 	.type	__modsi3,@function
++#ifdef __arch64__
++        .align 3
++__modsi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-32
++	sli	r28,r1,0
++	sli	r29,r1,8
++	sli	r30,r1,16
++	sli	r31,r1,24
++#else
+ __modsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -49,6 +60,7 @@ __modsi3:
+ 	swi	r29,r1,4
+ 	swi	r30,r1,8
+ 	swi	r31,r1,12
++#endif
+ 
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+@@ -88,6 +100,18 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli	r28,r1,0
++	lli	r29,r1,8
++	lli	r30,r1,16
++	lli	r31,r1,24
++	addik	r1,r1,32
++	rtsd	r15,8
++	nop
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	lwi	r28,r1,0
+@@ -95,7 +119,7 @@ $LaRETURN_HERE:
+ 	lwi	r30,r1,8
+ 	lwi	r31,r1,12
+ 	rtsd	r15,8
+-	addik	r1,r1,16
++#endif
+         .end __modsi3
+ 	.size	__modsi3, . - __modsi3
+ 
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index 8c3f788..e28c69a 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -41,6 +41,9 @@
+ 	.globl	__mulsi3
+ 	.ent	__mulsi3
+ 	.type	__mulsi3,@function
++#ifdef __arch64__
++        .align 3
++#endif
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index 5d726ad..b1e44b6 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -41,6 +41,16 @@
+ 	.globl	__udivsi3
+ 	.ent	__udivsi3
+ 	.type	__udivsi3,@function
++#ifdef __arch64__
++        .align 3
++__udivsi3:
++	.frame	r1,0,r15	
++
++	ADDLIK   r1,r1,-24
++    	SLI     r29,r1,0
++	SLI     r30,r1,8
++	SLI     r31,r1,16
++#else
+ __udivsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -48,7 +58,7 @@ __udivsi3:
+     	SWI     r29,r1,0
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+-
++#endif
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
+ 	ADDIK   r30,r0,0                    # Clear mod
+@@ -98,6 +108,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++        # Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r29,r1,0
++	LLI     r30,r1,8
++	LLI     r31,r1,16
++	ADDIK   r1,r1,24
++	RTSD    r15,8
++	NOP
++#else
+ $LaRETURN_HERE:
+         # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	LWI     r29,r1,0
+@@ -105,5 +126,6 @@ $LaRETURN_HERE:
+ 	LWI     r31,r1,8
+ 	RTSD    r15,8
+ 	ADDIK   r1,r1,12
++#endif
+         .end __udivsi3
+ 	.size	__udivsi3, . - __udivsi3
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index b29d7e1..8804b99 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -41,6 +41,16 @@
+ 	.globl	__umodsi3
+ 	.ent	__umodsi3
+ 	.type	__umodsi3,@function
++#ifdef __arch64__
++        .align 3
++__umodsi3:
++	.frame	r1,0,r15	
++
++	addik	r1,r1,-24
++	swi	r29,r1,0
++	swi	r30,r1,8
++	swi	r31,r1,16
++#else
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -48,7 +58,7 @@ __umodsi3:
+ 	swi	r29,r1,0
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+-
++#endif
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
+ 	ADDIK 	r3,r0,0                  # Clear div
+@@ -101,6 +111,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli 	r29,r1,0
++	lli 	r30,r1,8
++	lli 	r31,r1,16
++	addlik 	r1,r1,24
++	rtsd 	r15,8
++	nop
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	lwi 	r29,r1,0
+@@ -108,5 +129,6 @@ $LaRETURN_HERE:
+ 	lwi 	r31,r1,8
+ 	rtsd 	r15,8
+ 	addik 	r1,r1,12
++#endif
+ .end __umodsi3
+ 	.size	__umodsi3, . - __umodsi3
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
new file mode 100644
index 00000000..ba717327
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -0,0 +1,25 @@
+From 51886f40b6bccea22277f8dcc971706d7c24bdd0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 15 Oct 2018 12:00:10 +0530
+Subject: [PATCH 50/63] extending the Dwarf support to 64bit Microblaze
+
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 7497cfb..bd5e216 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
+ /* Use DWARF 2 debugging information by default.  */
+ #define DWARF2_DEBUGGING_INFO 1
+ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+-#define DWARF2_ADDR_SIZE 4
++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
+ 
+ /* Target machine storage layout */
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch
new file mode 100644
index 00000000..a0758b31
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0051-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -0,0 +1,29 @@
+From a8978d71c8b5adfa59430443611bd785a4d54ef9 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 16 Oct 2018 07:55:46 +0530
+Subject: [PATCH 51/63] fixing the typo errors in umodsi3 file
+
+---
+ libgcc/config/microblaze/umodsi3.S | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 8804b99..1b3070e 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -47,9 +47,9 @@ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+ 	addik	r1,r1,-24
+-	swi	r29,r1,0
+-	swi	r30,r1,8
+-	swi	r31,r1,16
++	sli	r29,r1,0
++	sli	r30,r1,8
++	sli	r31,r1,16
+ #else
+ __umodsi3:
+ 	.frame	r1,0,r15	
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
new file mode 100644
index 00000000..d0b534bc
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -0,0 +1,68 @@
+From 328bd339c292b63d2068a132a245bdc037815d6b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Wed, 17 Oct 2018 16:56:14 +0530
+Subject: [PATCH 52/63] fixing the 32bit LTO related issue9(1014024)
+
+---
+ gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
+ 1 file changed, 14 insertions(+), 10 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index bd5e216..ab541f7 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
+ #define WORD_REGISTER_OPERATIONS 1
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+-/*
+-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
+-      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
+-    (MODE) = TARGET_MB_64 ? DImode : SImode;
+-*/
++
++#ifndef __arch64__
++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
++  if (GET_MODE_CLASS (MODE) == MODE_INT         \
++      && GET_MODE_SIZE (MODE) < 4)              \
++    (MODE) = SImode;
++#endif
++
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
+ 
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
++#ifdef __aarch64__
+ #define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (MODE,GP_RETURN)
+-								
+-/*#define LIBCALL_VALUE(MODE)						\
++#else								
++#define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (								\
+ 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+ 	     || GET_MODE_SIZE (MODE) >= 4)				\
+ 	    ? (MODE)							\
+ 	    : SImode), GP_RETURN)
+-*/
++#endif
++
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+@@ -518,7 +522,7 @@ typedef struct microblaze_args
+ /* 4 insns + 2 words of data.  */
+ #define TRAMPOLINE_SIZE				(6 * 4)
+ 
+-#define TRAMPOLINE_ALIGNMENT			64
++#define TRAMPOLINE_ALIGNMENT		(TARGET_MB_64 ? 64 : 32)
+ 
+ #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
new file mode 100644
index 00000000..f8ac364c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -0,0 +1,25 @@
+From 3f65f0432d42f4d469fbb10828f1683cd30a5d84 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 19 Oct 2018 14:26:25 +0530
+Subject: [PATCH 53/63] Fixed the missing stack adjustment in prologue of
+ modsi3 function
+
+---
+ libgcc/config/microblaze/modsi3.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 7e61453..b0e6cad 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -119,6 +119,7 @@ $LaRETURN_HERE:
+ 	lwi	r30,r1,8
+ 	lwi	r31,r1,12
+ 	rtsd	r15,8
++	addik	r1,r1,16
+ #endif
+         .end __modsi3
+ 	.size	__modsi3, . - __modsi3
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
new file mode 100644
index 00000000..0e704506
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -0,0 +1,29 @@
+From 0dbb2b7bfe466c18d54aec680208fd1459619bc1 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 24 Oct 2018 18:31:04 +0530
+Subject: [PATCH 54/63] [Patch,Microblaze] : corrected SPN for dlong
+ instruction mapping.
+
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index d6370d8..6b6b7c6 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -602,9 +602,9 @@
+   (set_attr "mode"      "DF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "floatdfdi2"
++(define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+-        (float:DI (match_operand:DF 1 "register_operand" "d")))]
++        (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+   "TARGET_MB_64"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 00000000..28554722
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,59 @@
+From a56b23ae244eee1da6d6595d3a6477085d77271e Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:55:08 +0530
+Subject: [PATCH 55/63] fixing the long & long long mingw toolchain issue
+
+---
+ gcc/config/microblaze/constraints.md | 2 +-
+ gcc/config/microblaze/microblaze.md  | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 2fce91e..9a5aa6b 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -55,7 +55,7 @@
+ (define_constraint "K"
+   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
++       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
+ 
+ ;; Define floating point constraints
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 6b6b7c6..a1dc41f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -648,8 +648,8 @@
+   if (TARGET_MB_64) 
+    {
+      if (GET_CODE (operands[2]) == CONST_INT &&
+-       INTVAL(operands[2]) < (long)-549755813888 &&
+-	INTVAL(operands[2]) > (long)549755813887)
++       INTVAL(operands[2]) < (long long)-549755813888 &&
++	INTVAL(operands[2]) > (long long)549755813887)
+       FAIL;
+    }
+ })
+@@ -1266,7 +1266,7 @@
+ 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
+   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
+            (GET_CODE (operands[1]) == CONST_INT && 
+-                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
++                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
+   "@
+    addlk\t%0,r0,r0\t
+    addlik\t%0,r0,%1\t #N1 %X1
+@@ -1300,7 +1300,7 @@
+      case 1:
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+-	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+  	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+         else	
+ 	  return "addlik\t%0,r0,%1";
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch
new file mode 100644
index 00000000..c009c92d
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0055-microblaze_linker_script_xilinx_ld.patch
@@ -0,0 +1,16 @@
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 740b8d9..4bda9c2 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -114,8 +114,9 @@ extern enum pipeline_type microblaze_pipe;
+   %{m64:-EL --oformat=elf64-microblazeel} \
+   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+-  %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
+-  %{!T*: -dT xilinx.ld%s}"
++  %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0}"
++
++//  %{!T*: -dT xilinx.ld%s}"
+ 
+ /* Specs for the compiler proper  */
+ 
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 00000000..a419216c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
+From e13b1b70972511a642512cbc7093ed21e5a9e141 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:11:04 +0530
+Subject: [PATCH 56/63] Fix the MB-64 bug of handling QI objects
+
+---
+ gcc/config/microblaze/microblaze.md | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index a1dc41f..bb96e2d 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2347,11 +2347,11 @@ else
+ 
+ (define_insn "branch_zero_64"
+   [(set (pc)
+-	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand:SI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand:SI 2 "pc_or_label_operand" "")
+-                      (match_operand:SI 3 "pc_or_label_operand" "")))
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+@@ -2367,11 +2367,11 @@ else
+ 
+ (define_insn "long_branch_zero"
+   [(set (pc)
+-	(if_then_else (match_operator 0 "ordered_comparison_operator"
+-  				 [(match_operand 1 "register_operand" "d")
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++				 [(match_operand:DI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand 2 "pc_or_label_operand" "")
+-                      (match_operand 3 "pc_or_label_operand" "")))
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch
new file mode 100644
index 00000000..ff524770
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0056-fix-the-lto-wrapper-issue-on-windows.patch
@@ -0,0 +1,36 @@
+From f30b99b5b8d3f2a8d8e4973cd155a4b9f1849039 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:08:06 +0530
+Subject: [PATCH 56/57] fix the lto-wrapper issue on windows
+
+---
+ libiberty/simple-object.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/libiberty/simple-object.c b/libiberty/simple-object.c
+index 42aa6ac..d2465c6 100644
+--- a/libiberty/simple-object.c
++++ b/libiberty/simple-object.c
+@@ -44,6 +44,10 @@ Boston, MA 02110-1301, USA.  */
+ #define SEEK_SET 0
+ #endif
+ 
++#ifndef O_BINARY
++#define O_BINARY 0
++#endif
++
+ #include "simple-object-common.h"
+ 
+ /* The known object file formats.  */
+@@ -326,7 +330,7 @@ simple_object_copy_lto_debug_sections (simple_object_read *sobj,
+       return errmsg;
+     }
+ 
+-  outfd = creat (dest, 00777);
++  outfd = open (dest, O_CREAT|O_WRONLY|O_TRUNC|O_BINARY, 00777);
+   if (outfd == -1)
+     {
+       *err = errno;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 00000000..a5a2039d
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
+From 6c58973f1cc1e37773aeab583aa3ac6331489106 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:11:04 +0530
+Subject: [PATCH 57/57] Fix the MB-64 bug of handling QI objects
+
+---
+ gcc/config/microblaze/microblaze.md | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index e03b835..88aee9e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2345,11 +2345,11 @@ else
+ 
+ (define_insn "branch_zero_64"
+   [(set (pc)
+-	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand:SI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand:SI 2 "pc_or_label_operand" "")
+-                      (match_operand:SI 3 "pc_or_label_operand" "")))
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+@@ -2365,11 +2365,11 @@ else
+ 
+ (define_insn "long_branch_zero"
+   [(set (pc)
+-	(if_then_else (match_operator 0 "ordered_comparison_operator"
+-  				 [(match_operand 1 "register_operand" "d")
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++				 [(match_operand:DI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand 2 "pc_or_label_operand" "")
+-                      (match_operand 3 "pc_or_label_operand" "")))
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 00000000..940009de
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
+From 1387d4fedb397f78b08ad33204a3fcf2bd63f183 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Mar 2019 12:08:39 +0530
+Subject: [PATCH 57/63] [Patch,Microblaze] : We will check the possibility of
+ peephole2 optimization,if we can then we will fix the compiler issue.
+
+---
+ gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
+ 1 file changed, 38 insertions(+), 25 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index bb96e2d..830ef77 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -882,31 +882,44 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_peephole2
+-  [(set (match_operand:SI 0 "register_operand")
+-        (fix:SI (match_operand:SF 1 "register_operand")))
+-   (set (pc)
+-        (if_then_else (match_operator 2 "ordered_comparison_operator"
+-                       [(match_operand:SI 3 "register_operand")
+-                        (match_operand:SI 4 "arith_operand")])
+-                      (label_ref (match_operand 5))
+-                      (pc)))]
+-   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+-   [(set (match_dup 1) (match_dup 3))]
+-
+-  {
+-    rtx condition;
+-    rtx cmp_op0 = operands[3];
+-    rtx cmp_op1 = operands[4];
+-    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+-
+-    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
+-    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-    emit_jump_insn (gen_condjump (condition, operands[5]));
+-  }
+-)
++;; peephole2 optimization will be done only if fint and if-then-else
++;; are dependent.added condition for the same.
++;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
++;; testcase:
++;;        volatile float vec = 1.0;
++;;        volatile int ci = 2;
++;;        register int cj = (int)(vec);
++;;//        ci=cj;
++;;//      if (ci <0) {
++;;        if (cj < 0) {
++;;                ci = 0;
++;;        }
++;; commenting for now.we will check the possibility of this optimization later
++
++;;(define_peephole2
++;;  [(set (match_operand:SI 0 "register_operand")
++;;        (fix:SI (match_operand:SF 1 "register_operand")))
++;;   (set (pc)
++;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
++;;                       [(match_operand:SI 3 "register_operand")
++;;                        (match_operand:SI 4 "arith_operand")])
++;;                      (label_ref (match_operand 5))
++;;                      (pc)))]
++;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
++;;  [(set (match_dup 1) (match_dup 3))]
++;;  {
++;;    rtx condition;
++;;    rtx cmp_op0 = operands[3];
++;;    rtx cmp_op1 = operands[4];
++;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++;;
++;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
++;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++;;    emit_jump_insn (gen_condjump (condition, operands[5]));
++;;  }
++;;)
+ 
+ ;;----------------------------------------------------------------
+ ;; Negation and one's complement
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 00000000..8bc47a43
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
+From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Mar 2019 12:08:39 +0530
+Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of
+ peephole2 optimization,if we can then we will fix the compiler issue.
+
+---
+ gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++---------------
+ 1 file changed, 38 insertions(+), 25 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 88aee9e..8bd175f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -880,31 +880,44 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_peephole2
+-  [(set (match_operand:SI 0 "register_operand")
+-        (fix:SI (match_operand:SF 1 "register_operand")))
+-   (set (pc)
+-        (if_then_else (match_operator 2 "ordered_comparison_operator"
+-                       [(match_operand:SI 3 "register_operand")
+-                        (match_operand:SI 4 "arith_operand")])
+-                      (label_ref (match_operand 5))
+-                      (pc)))]
+-   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+-   [(set (match_dup 1) (match_dup 3))]
+-
+-  {
+-    rtx condition;
+-    rtx cmp_op0 = operands[3];
+-    rtx cmp_op1 = operands[4];
+-    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+-
+-    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
+-    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-    emit_jump_insn (gen_condjump (condition, operands[5]));
+-  }
+-)
++;; peephole2 optimization will be done only if fint and if-then-else
++;; are dependent.added condition for the same.
++;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
++;; testcase:
++;;        volatile float vec = 1.0;
++;;        volatile int ci = 2;
++;;        register int cj = (int)(vec);
++;;//        ci=cj;
++;;//      if (ci <0) {
++;;        if (cj < 0) {
++;;                ci = 0;
++;;        }
++;; commenting for now.we will check the possibility of this optimization later
++
++;;(define_peephole2
++;;  [(set (match_operand:SI 0 "register_operand")
++;;        (fix:SI (match_operand:SF 1 "register_operand")))
++;;   (set (pc)
++;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
++;;                       [(match_operand:SI 3 "register_operand")
++;;                        (match_operand:SI 4 "arith_operand")])
++;;                      (label_ref (match_operand 5))
++;;                      (pc)))]
++;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
++;;  [(set (match_dup 1) (match_dup 3))]
++;;  {
++;;    rtx condition;
++;;    rtx cmp_op0 = operands[3];
++;;    rtx cmp_op1 = operands[4];
++;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++;;
++;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
++;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++;;    emit_jump_insn (gen_condjump (condition, operands[5]));
++;;  }
++;;)
+ 
+ ;;----------------------------------------------------------------
+ ;; Negation and one's complement
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 00000000..69b49898
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
+From 8e7d7f3d2e103c34bbb28afe1338107b9fd824f0 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 16 Apr 2019 17:20:24 +0530
+Subject: [PATCH 58/63] Reverting the patch as kernel boot is not working with
+ this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
+ before propagating constants."
+
+This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
+---
+ gcc/cprop.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/cprop.c b/gcc/cprop.c
+index 42bcc81..65c0130 100644
+--- a/gcc/cprop.c
++++ b/gcc/cprop.c
+@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+   int success = 0;
+   rtx set = single_set (insn);
+ 
+-#if 0
+   bool check_rtx_costs = true;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int old_cost = set ? set_rtx_cost (set, speed) : 0;
+@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 	  && (GET_CODE (XEXP (note, 0)) == CONST
+ 	      || CONSTANT_P (XEXP (note, 0)))))
+     check_rtx_costs = false;
+-#endif
+ 
+   /* Usually we substitute easy stuff, so we won't copy everything.
+      We however need to take care to not duplicate non-trivial CONST
+@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 
+   validate_replace_src_group (from, to, insn);
+ 
+-#if 0
+   /* If TO is a constant, check the cost of the set after propagation
+      to the cost of the set before the propagation.  If the cost is
+      higher, then do not replace FROM with TO.  */
+@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+       return false;
+     }
+ 
+-#endif
+ 
+   if (num_changes_pending () && apply_change_group ())
+     success = 1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 00000000..2e570330
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
+From e1a10a708f209704a3921cf66dd3ff4d0814befc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 17 Apr 2019 12:36:16 +0530
+Subject: [PATCH 59/63] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+ assembly files.
+
+---
+ libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++++++++----
+ libgcc/config/microblaze/modsi3.S  | 40 +++++++++++++++++++++++---
+ libgcc/config/microblaze/mulsi3.S  | 33 +++++++++++++++++++++-
+ libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
+ libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
+ 5 files changed, 212 insertions(+), 20 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index 2765e42..bd56522 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -46,7 +46,7 @@
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+-	ADDIK   r1,r1,-32
++	ADDLIK   r1,r1,-32
+ 	SLI     r28,r1,0
+ 	SLI     r29,r1,8
+ 	SLI     r30,r1,16
+@@ -61,13 +61,23 @@ __divsi3:
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+ #endif
+-	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+-	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+-	BGEID   r5,$LaR5_Pos 
++#ifdef __arch64__
++	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++	BEAGEID   r5,$LaR5_Pos
++#else
++        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BGEID   r5,$LaR5_Pos
++#endif
+ 	XOR     r28,r5,r6               # Get the sign of the result
+ 	RSUBI   r5,r5,0                 # Make r5 positive
+ $LaR5_Pos:
+-	BGEI    r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI    r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI   r6,r6,0                 # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK   r30,r0,0                # Clear mod
+@@ -76,26 +86,51 @@ $LaR6_Pos:
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0: 
+-        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#else
++        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30             # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++#else
+ 	BEQi    r29,$LaLOOP_END
++#endif
+ 	ADD     r3,r3,r3                # Shift in the '1' into div
++#ifdef __arch64__
++        BREAI     $LaDIV2                 # Div2
++#else
+ 	BRI     $LaDIV2                 # Div2
++#endif
+ $LaLOOP_END:
++#ifdef __arch64__
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAID    $LaRETURN_HERE
++#else
+ 	BGEI    r28,$LaRETURN_HERE
+ 	BRID    $LaRETURN_HERE
++#endif
+ 	RSUBI   r3,r3,0                 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index b0e6cad..3632fad 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -62,40 +62,72 @@ __modsi3:
+ 	swi	r31,r1,12
+ #endif
+ 
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BEAGEId   r5,$LaR5_Pos
++#else
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEId	r5,$LaR5_Pos 
++#endif
+ 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
+ 	RSUBI	r5,r5,0	                # Make r5 positive
+ $LaR5_Pos:
+-	BGEI	r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI	r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI	r6,r6,0	    # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK	r3,r0,0      # Clear mod
+ 	ADDIK	r30,r0,0     # clear div
+-	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++#ifdef __arch64__
++	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
+ 			     # the first bit search.
++#else
++        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++                             # the first bit search.
++#endif
+ 	ADDIK	r29,r0,32    # Initialize the loop count
+    # First part try to find the first '1' in the r5
+ $LaDIV1:
+ 	ADD	r5,r5,r5         # left shift logical r5
+-	BGEID	r5,$LaDIV1       #
++#ifdef __arch64__
++	BEAGEID	r5,$LaDIV1       #
++#else
++        BGEID   r5,$LaDIV1       #
++#endif
+ 	ADDIK	r29,r29,-1
+ $LaDIV2:
+ 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
+ 	ADDC	r3,r3,r3         # Move that bit into the Mod register
+ 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTi    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTi	r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
+ 	ADDIK	r30,r30,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK	r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30         # Shift in the '1' into div
++        BREAI     $LaDIV2          # Div2
++$LaLOOP_END:
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAId    $LaRETURN_HERE
++#else
+ 	BEQi	r29,$LaLOOP_END
+ 	ADD	r30,r30,r30         # Shift in the '1' into div
+ 	BRI	$LaDIV2          # Div2
+ $LaLOOP_END:
+ 	BGEI	r28,$LaRETURN_HERE
+ 	BRId	$LaRETURN_HERE
++#endif
+ 	rsubi	r3,r3,0 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+@@ -108,7 +140,7 @@ $LaRETURN_HERE:
+ 	lli	r29,r1,8
+ 	lli	r30,r1,16
+ 	lli	r31,r1,24
+-	addik	r1,r1,32
++	addlik	r1,r1,32
+ 	rtsd	r15,8
+ 	nop
+ #else
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index e28c69a..991dbcd 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -43,7 +43,37 @@
+ 	.type	__mulsi3,@function
+ #ifdef __arch64__
+         .align 3
+-#endif
++__mulsi3:
++        .frame  r1,0,r15
++        add     r3,r0,r0
++        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
++        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
++        BEAGEId   r5,$L_R5_Pos
++        XOR     r4,r5,r6                  # Get the sign of the result
++        RSUBI   r5,r5,0                   # Make r5 positive
++$L_R5_Pos:
++        BEAGEI    r6,$L_R6_Pos
++        RSUBI   r6,r6,0                   # Make r6 positive
++$L_R6_Pos:
++        breai     $L1
++$L2:
++        add     r5,r5,r5
++$L1:
++        srl     r6,r6
++        addc    r7,r0,r0
++        beaeqi    r7,$L2
++        beaneid   r6,$L2
++        add     r3,r3,r5
++        bealti    r4,$L_NegateResult
++        rtsd    r15,8
++        nop
++$L_NegateResult:
++        rtsd    r15,8
++        rsub    r3,r3,r0
++$L_Result_Is_Zero:
++        rtsd    r15,8
++        addi    r3,r0,0
++#else
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+@@ -74,5 +104,6 @@ $L_NegateResult:
+ $L_Result_Is_Zero:
+ 	rtsd	r15,8
+ 	addi	r3,r0,0
++#endif
+ 	.end __mulsi3
+ 	.size	__mulsi3, . - __mulsi3
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index b1e44b6..42b086e 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -59,52 +59,96 @@ __udivsi3:
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
++#else
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
++#endif
+ 	ADDIK   r30,r0,0                    # Clear mod
+ 	ADDIK   r29,r0,32                   # Initialize the loop count
+ 
+         # Check if r6 and r5 are equal # if yes, return 1
+ 	RSUB 	r18,r5,r6
++#ifdef __arch64__
++        BEAEQID   r18,$LaRETURN_HERE
++#else
+ 	BEQID	r18,$LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
+ 	XOR	r18,r5,r6
+-	BGEID	r18,16
++#ifdef __arch64__
++	BEAGEID	r18,16
++#else
++        BGEID   r18,16
++#endif
+ 	ADD	r3,r0,r0                    # We would anyways clear r3
++#ifdef __arch64__
++        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++        BREAI     $LCheckr6
++        RSUB    r18,r6,r5                   # MICROBLAZEcmp
++        BEALTI    r18,$LaRETURN_HERE
++#else
+ 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
+ 	BRI	$LCheckr6
+ 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
+ 	BLTI	r18,$LaRETURN_HERE
+-
++#endif
+         # If r6 [bit 31] is set, then return result as 1
+ $LCheckr6:
+-	BGTI	r6,$LaDIV0
+-	BRID	$LaRETURN_HERE
++#ifdef __arch64__
++	BEAGTI	r6,$LaDIV0
++	BREAID	$LaRETURN_HERE
++#else
++        BGTI    r6,$LaDIV0
++        BRID    $LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0:
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2
++#else
+ 	BLTI    r5,$LaDIV2	
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                    # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+     	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r3,r3,r3 # Shift in the '1' into div
++        BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++#else
+ 	BEQi    r29,$LaLOOP_END
+ 	ADD     r3,r3,r3 # Shift in the '1' into div
+ 	BRI     $LaDIV2   # Div2
+ $LaLOOP_END:
+ 	BRI     $LaRETURN_HERE
++#endif
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
+@@ -115,7 +159,7 @@ $LaRETURN_HERE:
+ 	LLI     r29,r1,0
+ 	LLI     r30,r1,8
+ 	LLI     r31,r1,16
+-	ADDIK   r1,r1,24
++	ADDLIK   r1,r1,24
+ 	RTSD    r15,8
+ 	NOP
+ #else
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 1b3070e..91430a6 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -46,7 +46,7 @@
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+-	addik	r1,r1,-24
++	addlik	r1,r1,-24
+ 	sli	r29,r1,0
+ 	sli	r30,r1,8
+ 	sli	r31,r1,16
+@@ -59,27 +59,77 @@ __umodsi3:
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
++#else
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
++#endif
+ 	ADDIK 	r3,r0,0                  # Clear div
+ 	ADDIK 	r30,r0,0     	# clear mod
+ 	ADDIK 	r29,r0,32       # Initialize the loop count
+ 
+ # Check if r6 and r5 are equal # if yes, return 0
+ 	rsub 	r18,r5,r6
+-	beqi	r18,$LaRETURN_HERE
+ 
++#ifdef __arch64__
++	beaeqi    r18,$LaRETURN_HERE
++#else
++	beqi	r18,$LaRETURN_HERE
++#endif
+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
+ 	xor	r18,r5,r6
++#ifdef __arch64__
++        beageid   r18,16
++        addik   r3,r5,0
++        bealti    r6,$LaRETURN_HERE
++        breai     $LCheckr6
++        rsub    r18,r5,r6 # MICROBLAZEcmp
++        beagti    r18,$LaRETURN_HERE
++#else
+ 	bgeid	r18,16
+ 	addik	r3,r5,0
+ 	blti	r6,$LaRETURN_HERE
+ 	bri	$LCheckr6
+ 	rsub	r18,r5,r6 # MICROBLAZEcmp
+ 	bgti	r18,$LaRETURN_HERE
+-
++#endif
+ # If r6 [bit 31] is set, then return result as r5-r6
+ $LCheckr6:
++#ifdef __arch64__
++        beagtid   r6,$LaDIV0
++        addik   r3,r0,0
++        addik   r18,r0,0x7fffffff
++        and     r5,r5,r18
++        and     r6,r6,r18
++        breaid    $LaRETURN_HERE
++        rsub    r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++        BEALTI    r5,$LaDIV2
++$LaDIV1:
++        ADD     r5,r5,r5     # left shift logical r5
++        BEAGEID   r5,$LaDIV1   #
++        ADDIK   r29,r29,-1
++$LaDIV2:
++        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++        ADDC    r3,r3,r3     # Move that bit into the Mod register
++        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
++        BEALTi    r31,$LaMOD_TOO_SMALL
++        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
++        ADDIK   r30,r30,1
++$LaMOD_TOO_SMALL:
++        ADDIK   r29,r29,-1
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30 # Shift in the '1' into div
++        BREAI     $LaDIV2     # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++        or      r3,r0,r0   # set result to 0
++#else
+ 	bgtid	r6,$LaDIV0
+ 	addik	r3,r0,0
+ 	addik	r18,r0,0x7fffffff
+@@ -111,7 +161,7 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
+-
++#endif
+ #ifdef __arch64__
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
new file mode 100644
index 00000000..be4dfad5
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch
@@ -0,0 +1,51 @@
+From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 16 Apr 2019 17:20:24 +0530
+Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with
+ this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check
+ before propagating constants."
+
+This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b.
+---
+ gcc/cprop.c | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/cprop.c b/gcc/cprop.c
+index deb706b..e4df509 100644
+--- a/gcc/cprop.c
++++ b/gcc/cprop.c
+@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+   int success = 0;
+   rtx set = single_set (insn);
+ 
+-#if 0
+   bool check_rtx_costs = true;
+   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+   int old_cost = set ? set_rtx_cost (set, speed) : 0;
+@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 	  && (GET_CODE (XEXP (note, 0)) == CONST
+ 	      || CONSTANT_P (XEXP (note, 0)))))
+     check_rtx_costs = false;
+-#endif
+ 
+   /* Usually we substitute easy stuff, so we won't copy everything.
+      We however need to take care to not duplicate non-trivial CONST
+@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+ 
+   validate_replace_src_group (from, to, insn);
+ 
+-#if 0
+   /* If TO is a constant, check the cost of the set after propagation
+      to the cost of the set before the propagation.  If the cost is
+      higher, then do not replace FROM with TO.  */
+@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
+       return false;
+     }
+ 
+-#endif
+ 
+   if (num_changes_pending () && apply_change_group ())
+     success = 1;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 00000000..9f878669
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
+From f0332f119c3cbe95886dae77c4b5a9b9907b4b17 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 18 Apr 2019 16:00:37 +0530
+Subject: [PATCH 60/63] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+ 17 14:11:00 2019 +0530
+
+    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
+    By default MB-64 is generatting barrel-shift instructions. It has been
+    removed from default. Barrel-shift instructions will be generated only if
+    barrel-shifter is enabled. Similarly to double instructions as well.
+
+    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c  |   2 +-
+ gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
+ 2 files changed, 252 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 220e03d..5c09452 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -4008,7 +4008,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+   if (TARGET_MB_64) {
+-      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
+       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
+     }
+   else  {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 830ef77..3e7c647 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -547,7 +547,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (plus:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dadd\t%0,%1,%2"
+   [(set_attr "type"     "fadd")
+   (set_attr "mode"      "DF")
+@@ -557,7 +557,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (minus:DF (match_operand:DF 1 "register_operand" "d")
+                   (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "drsub\t%0,%2,%1"
+   [(set_attr "type"     "frsub")
+   (set_attr "mode"      "DF")
+@@ -567,7 +567,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (mult:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dmul\t%0,%1,%2"
+   [(set_attr "type"     "fmul")
+   (set_attr "mode"      "DF")
+@@ -577,7 +577,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (div:DF (match_operand:DF 1 "register_operand" "d")
+                 (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "ddiv\t%0,%2,%1"
+   [(set_attr "type"     "fdiv")
+   (set_attr "mode"      "DF")
+@@ -587,7 +587,7 @@
+ (define_insn "sqrtdf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dsqrt\t%0,%1"
+   [(set_attr "type"     "fsqrt")
+   (set_attr "mode"      "DF")
+@@ -596,7 +596,7 @@
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dbl\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DF")
+@@ -605,7 +605,7 @@
+ (define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DI")
+@@ -1301,6 +1301,34 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "*movdi_internal2_bshift"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT &&
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
++	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ (define_insn "*movdi_internal2"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
+ 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
+@@ -1314,7 +1342,15 @@
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+ 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++          {
++            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++            output_asm_insn ("addlik\t%0,r0,%h1", operands);
++            output_asm_insn ("addlik\t%2,r0,32", operands);
++            output_asm_insn ("addlik\t%2,%2,-1", operands);
++            output_asm_insn ("beaneid\t%2,.-8", operands);
++            output_asm_insn ("addlk\t%0,%0,%0", operands);
++            return "addlik\t%0,%0,%j1 #li => la";
++          }
+         else	
+ 	  return "addlik\t%0,r0,%1";
+      case 3:
+@@ -1388,7 +1424,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1655,6 +1691,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64_bshift"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal_64"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
+         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
+@@ -1671,7 +1734,13 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++	output_asm_insn ("addlik\t%0,r0,%h1", operands);
++	output_asm_insn ("addlik\t%2,r0,32", operands);
++	output_asm_insn ("addlik\t%2,%2,-1", operands);
++	output_asm_insn ("beaneid\t%2,.-8", operands);
++	output_asm_insn ("addlk\t%0,%0,%0", operands);
++	return "addlik\t%0,%0,%j1 #li => la";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -1791,11 +1860,21 @@
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1805,7 +1884,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+   bsllli\t%0,%1,%2
+   bslll\t%0,%1,%2"
+@@ -1813,6 +1892,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+ )
++
++(define_insn "ashldi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++   (set_attr "mode"    "DI")
++   (set_attr "length"  "20")]
++)
++
++(define_insn "ashldi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1946,11 +2070,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1960,7 +2094,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrai\t%0,%1,%2
+    bslra\t%0,%1,%2"
+@@ -1968,6 +2102,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+   )
++
++(define_insn "ashrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "ashrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2085,11 +2264,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -2099,7 +2288,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrli\t%0,%1,%2
+    bslrl\t%0,%1,%2"
+@@ -2108,6 +2297,50 @@ else
+   (set_attr "length"	"4,4")]
+   )
+ 
++(define_insn "lshrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "lshrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "SI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2235,7 +2468,7 @@ else
+ 	(eq:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmpleq\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"DI")
+@@ -2247,7 +2480,7 @@ else
+ 	(ne:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmplne\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 00000000..1548faad
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
+From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 17 Apr 2019 12:36:16 +0530
+Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+ assembly files.
+
+---
+ libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++++++++----
+ libgcc/config/microblaze/modsi3.S  | 40 +++++++++++++++++++++++---
+ libgcc/config/microblaze/mulsi3.S  | 33 +++++++++++++++++++++-
+ libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++----
+ libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++---
+ 5 files changed, 212 insertions(+), 20 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index 7e7d875..cfb4c05 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -46,7 +46,7 @@
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+-	ADDIK   r1,r1,-32
++	ADDLIK   r1,r1,-32
+ 	SLI     r28,r1,0
+ 	SLI     r29,r1,8
+ 	SLI     r30,r1,16
+@@ -61,13 +61,23 @@ __divsi3:
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+ #endif
+-	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+-	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+-	BGEID   r5,$LaR5_Pos 
++#ifdef __arch64__
++	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++	BEAGEID   r5,$LaR5_Pos
++#else
++        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BGEID   r5,$LaR5_Pos
++#endif
+ 	XOR     r28,r5,r6               # Get the sign of the result
+ 	RSUBI   r5,r5,0                 # Make r5 positive
+ $LaR5_Pos:
+-	BGEI    r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI    r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI   r6,r6,0                 # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK   r30,r0,0                # Clear mod
+@@ -76,26 +86,51 @@ $LaR6_Pos:
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0: 
+-        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#else
++        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30             # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++#else
+ 	BEQi    r29,$LaLOOP_END
++#endif
+ 	ADD     r3,r3,r3                # Shift in the '1' into div
++#ifdef __arch64__
++        BREAI     $LaDIV2                 # Div2
++#else
+ 	BRI     $LaDIV2                 # Div2
++#endif
+ $LaLOOP_END:
++#ifdef __arch64__
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAID    $LaRETURN_HERE
++#else
+ 	BGEI    r28,$LaRETURN_HERE
+ 	BRID    $LaRETURN_HERE
++#endif
+ 	RSUBI   r3,r3,0                 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 46ff34a..49618dd 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -62,40 +62,72 @@ __modsi3:
+ 	swi	r31,r1,12
+ #endif
+ 
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BEAGEId   r5,$LaR5_Pos
++#else
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEId	r5,$LaR5_Pos 
++#endif
+ 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
+ 	RSUBI	r5,r5,0	                # Make r5 positive
+ $LaR5_Pos:
+-	BGEI	r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI	r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI	r6,r6,0	    # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK	r3,r0,0      # Clear mod
+ 	ADDIK	r30,r0,0     # clear div
+-	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++#ifdef __arch64__
++	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
+ 			     # the first bit search.
++#else
++        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++                             # the first bit search.
++#endif
+ 	ADDIK	r29,r0,32    # Initialize the loop count
+    # First part try to find the first '1' in the r5
+ $LaDIV1:
+ 	ADD	r5,r5,r5         # left shift logical r5
+-	BGEID	r5,$LaDIV1       #
++#ifdef __arch64__
++	BEAGEID	r5,$LaDIV1       #
++#else
++        BGEID   r5,$LaDIV1       #
++#endif
+ 	ADDIK	r29,r29,-1
+ $LaDIV2:
+ 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
+ 	ADDC	r3,r3,r3         # Move that bit into the Mod register
+ 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTi    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTi	r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
+ 	ADDIK	r30,r30,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK	r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30         # Shift in the '1' into div
++        BREAI     $LaDIV2          # Div2
++$LaLOOP_END:
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAId    $LaRETURN_HERE
++#else
+ 	BEQi	r29,$LaLOOP_END
+ 	ADD	r30,r30,r30         # Shift in the '1' into div
+ 	BRI	$LaDIV2          # Div2
+ $LaLOOP_END:
+ 	BGEI	r28,$LaRETURN_HERE
+ 	BRId	$LaRETURN_HERE
++#endif
+ 	rsubi	r3,r3,0 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+@@ -108,7 +140,7 @@ $LaRETURN_HERE:
+ 	lli	r29,r1,8
+ 	lli	r30,r1,16
+ 	lli	r31,r1,24
+-	addik	r1,r1,32
++	addlik	r1,r1,32
+ 	rtsd	r15,8
+ 	nop
+ #else
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index 31a73c2..39951be 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -43,7 +43,37 @@
+ 	.type	__mulsi3,@function
+ #ifdef __arch64__
+         .align 3
+-#endif
++__mulsi3:
++        .frame  r1,0,r15
++        add     r3,r0,r0
++        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
++        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
++        BEAGEId   r5,$L_R5_Pos
++        XOR     r4,r5,r6                  # Get the sign of the result
++        RSUBI   r5,r5,0                   # Make r5 positive
++$L_R5_Pos:
++        BEAGEI    r6,$L_R6_Pos
++        RSUBI   r6,r6,0                   # Make r6 positive
++$L_R6_Pos:
++        breai     $L1
++$L2:
++        add     r5,r5,r5
++$L1:
++        srl     r6,r6
++        addc    r7,r0,r0
++        beaeqi    r7,$L2
++        beaneid   r6,$L2
++        add     r3,r3,r5
++        bealti    r4,$L_NegateResult
++        rtsd    r15,8
++        nop
++$L_NegateResult:
++        rtsd    r15,8
++        rsub    r3,r3,r0
++$L_Result_Is_Zero:
++        rtsd    r15,8
++        addi    r3,r0,0
++#else
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+@@ -74,5 +104,6 @@ $L_NegateResult:
+ $L_Result_Is_Zero:
+ 	rtsd	r15,8
+ 	addi	r3,r0,0
++#endif
+ 	.end __mulsi3
+ 	.size	__mulsi3, . - __mulsi3
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index 94adb6a..d4fe285 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -59,52 +59,96 @@ __udivsi3:
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
++#else
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
++#endif
+ 	ADDIK   r30,r0,0                    # Clear mod
+ 	ADDIK   r29,r0,32                   # Initialize the loop count
+ 
+         # Check if r6 and r5 are equal # if yes, return 1
+ 	RSUB 	r18,r5,r6
++#ifdef __arch64__
++        BEAEQID   r18,$LaRETURN_HERE
++#else
+ 	BEQID	r18,$LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
+ 	XOR	r18,r5,r6
+-	BGEID	r18,16
++#ifdef __arch64__
++	BEAGEID	r18,16
++#else
++        BGEID   r18,16
++#endif
+ 	ADD	r3,r0,r0                    # We would anyways clear r3
++#ifdef __arch64__
++        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++        BREAI     $LCheckr6
++        RSUB    r18,r6,r5                   # MICROBLAZEcmp
++        BEALTI    r18,$LaRETURN_HERE
++#else
+ 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
+ 	BRI	$LCheckr6
+ 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
+ 	BLTI	r18,$LaRETURN_HERE
+-
++#endif
+         # If r6 [bit 31] is set, then return result as 1
+ $LCheckr6:
+-	BGTI	r6,$LaDIV0
+-	BRID	$LaRETURN_HERE
++#ifdef __arch64__
++	BEAGTI	r6,$LaDIV0
++	BREAID	$LaRETURN_HERE
++#else
++        BGTI    r6,$LaDIV0
++        BRID    $LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0:
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2
++#else
+ 	BLTI    r5,$LaDIV2	
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                    # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+     	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r3,r3,r3 # Shift in the '1' into div
++        BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++#else
+ 	BEQi    r29,$LaLOOP_END
+ 	ADD     r3,r3,r3 # Shift in the '1' into div
+ 	BRI     $LaDIV2   # Div2
+ $LaLOOP_END:
+ 	BRI     $LaRETURN_HERE
++#endif
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
+@@ -115,7 +159,7 @@ $LaRETURN_HERE:
+ 	LLI     r29,r1,0
+ 	LLI     r30,r1,8
+ 	LLI     r31,r1,16
+-	ADDIK   r1,r1,24
++	ADDLIK   r1,r1,24
+ 	RTSD    r15,8
+ 	NOP
+ #else
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 9bf65c3..3bd5d48 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -46,7 +46,7 @@
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+-	addik	r1,r1,-24
++	addlik	r1,r1,-24
+ 	sli	r29,r1,0
+ 	sli	r30,r1,8
+ 	sli	r31,r1,16
+@@ -59,27 +59,77 @@ __umodsi3:
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
++#else
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
++#endif
+ 	ADDIK 	r3,r0,0                  # Clear div
+ 	ADDIK 	r30,r0,0     	# clear mod
+ 	ADDIK 	r29,r0,32       # Initialize the loop count
+ 
+ # Check if r6 and r5 are equal # if yes, return 0
+ 	rsub 	r18,r5,r6
+-	beqi	r18,$LaRETURN_HERE
+ 
++#ifdef __arch64__
++	beaeqi    r18,$LaRETURN_HERE
++#else
++	beqi	r18,$LaRETURN_HERE
++#endif
+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
+ 	xor	r18,r5,r6
++#ifdef __arch64__
++        beageid   r18,16
++        addik   r3,r5,0
++        bealti    r6,$LaRETURN_HERE
++        breai     $LCheckr6
++        rsub    r18,r5,r6 # MICROBLAZEcmp
++        beagti    r18,$LaRETURN_HERE
++#else
+ 	bgeid	r18,16
+ 	addik	r3,r5,0
+ 	blti	r6,$LaRETURN_HERE
+ 	bri	$LCheckr6
+ 	rsub	r18,r5,r6 # MICROBLAZEcmp
+ 	bgti	r18,$LaRETURN_HERE
+-
++#endif
+ # If r6 [bit 31] is set, then return result as r5-r6
+ $LCheckr6:
++#ifdef __arch64__
++        beagtid   r6,$LaDIV0
++        addik   r3,r0,0
++        addik   r18,r0,0x7fffffff
++        and     r5,r5,r18
++        and     r6,r6,r18
++        breaid    $LaRETURN_HERE
++        rsub    r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++        BEALTI    r5,$LaDIV2
++$LaDIV1:
++        ADD     r5,r5,r5     # left shift logical r5
++        BEAGEID   r5,$LaDIV1   #
++        ADDIK   r29,r29,-1
++$LaDIV2:
++        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++        ADDC    r3,r3,r3     # Move that bit into the Mod register
++        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
++        BEALTi    r31,$LaMOD_TOO_SMALL
++        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
++        ADDIK   r30,r30,1
++$LaMOD_TOO_SMALL:
++        ADDIK   r29,r29,-1
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30 # Shift in the '1' into div
++        BREAI     $LaDIV2     # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++        or      r3,r0,r0   # set result to 0
++#else
+ 	bgtid	r6,$LaDIV0
+ 	addik	r3,r0,0
+ 	addik	r18,r0,0x7fffffff
+@@ -111,7 +161,7 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
+-
++#endif
+ #ifdef __arch64__
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 00000000..690bc727
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
+From e1b8cfe6c0b4a0bd90ecbd3e85ae7114df21b6cc Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 18 Apr 2019 16:00:37 +0530
+Subject: [PATCH 61/62] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+ 17 14:11:00 2019 +0530
+
+    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
+    By default MB-64 is generatting barrel-shift instructions. It has been
+    removed from default. Barrel-shift instructions will be generated only if
+    barrel-shifter is enabled. Similarly to double instructions as well.
+
+    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c  |   2 +-
+ gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++---
+ 2 files changed, 252 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 33d183e..c321b03 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+   if (TARGET_MB_64) {
+-      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
+       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
+     }
+   else  {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8bd175f..b5b60fb 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -545,7 +545,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (plus:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dadd\t%0,%1,%2"
+   [(set_attr "type"     "fadd")
+   (set_attr "mode"      "DF")
+@@ -555,7 +555,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (minus:DF (match_operand:DF 1 "register_operand" "d")
+                   (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "drsub\t%0,%2,%1"
+   [(set_attr "type"     "frsub")
+   (set_attr "mode"      "DF")
+@@ -565,7 +565,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (mult:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dmul\t%0,%1,%2"
+   [(set_attr "type"     "fmul")
+   (set_attr "mode"      "DF")
+@@ -575,7 +575,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (div:DF (match_operand:DF 1 "register_operand" "d")
+                 (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "ddiv\t%0,%2,%1"
+   [(set_attr "type"     "fdiv")
+   (set_attr "mode"      "DF")
+@@ -585,7 +585,7 @@
+ (define_insn "sqrtdf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dsqrt\t%0,%1"
+   [(set_attr "type"     "fsqrt")
+   (set_attr "mode"      "DF")
+@@ -594,7 +594,7 @@
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dbl\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DF")
+@@ -603,7 +603,7 @@
+ (define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DI")
+@@ -1299,6 +1299,34 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "*movdi_internal2_bshift"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT &&
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
++	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ (define_insn "*movdi_internal2"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
+ 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
+@@ -1312,7 +1340,15 @@
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+ 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++          {
++            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++            output_asm_insn ("addlik\t%0,r0,%h1", operands);
++            output_asm_insn ("addlik\t%2,r0,32", operands);
++            output_asm_insn ("addlik\t%2,%2,-1", operands);
++            output_asm_insn ("beaneid\t%2,.-8", operands);
++            output_asm_insn ("addlk\t%0,%0,%0", operands);
++            return "addlik\t%0,%0,%j1 #li => la";
++          }
+         else	
+ 	  return "addlik\t%0,r0,%1";
+      case 3:
+@@ -1386,7 +1422,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1653,6 +1689,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64_bshift"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal_64"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
+         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
+@@ -1669,7 +1732,13 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++	output_asm_insn ("addlik\t%0,r0,%h1", operands);
++	output_asm_insn ("addlik\t%2,r0,32", operands);
++	output_asm_insn ("addlik\t%2,%2,-1", operands);
++	output_asm_insn ("beaneid\t%2,.-8", operands);
++	output_asm_insn ("addlk\t%0,%0,%0", operands);
++	return "addlik\t%0,%0,%j1 #li => la";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -1789,11 +1858,21 @@
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1803,7 +1882,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+   bsllli\t%0,%1,%2
+   bslll\t%0,%1,%2"
+@@ -1811,6 +1890,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+ )
++
++(define_insn "ashldi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++   (set_attr "mode"    "DI")
++   (set_attr "length"  "20")]
++)
++
++(define_insn "ashldi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1944,11 +2068,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1958,7 +2092,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrai\t%0,%1,%2
+    bslra\t%0,%1,%2"
+@@ -1966,6 +2100,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+   )
++
++(define_insn "ashrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "ashrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2083,11 +2262,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -2097,7 +2286,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrli\t%0,%1,%2
+    bslrl\t%0,%1,%2"
+@@ -2106,6 +2295,50 @@ else
+   (set_attr "length"	"4,4")]
+   )
+ 
++(define_insn "lshrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "lshrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "SI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2233,7 +2466,7 @@ else
+ 	(eq:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmpleq\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"DI")
+@@ -2245,7 +2478,7 @@ else
+ 	(ne:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmplne\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 00000000..d3ed669c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,41 @@
+From 11766e4f7aaad3f217944079335c71525b72201c Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 8 May 2019 14:12:03 +0530
+Subject: [PATCH 61/63] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+ disable fivopts by default
+
+Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
+
+ * gcc/common/config/microblaze/microblaze-common.c
+   (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+---
+ gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 9b6ef21..3cae2a6 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -27,13 +27,15 @@
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
+ static const struct default_options microblaze_option_optimization_table[] =
+   {
+-    /* Turn off ivopts by default. It messes up cse. */
++    /* Turn off ivopts by default. It messes up cse. 
++    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
+     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
+-    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+     { OPT_LEVELS_NONE, 0, NULL, 0 }
+   };
+ 
+ #undef TARGET_DEFAULT_TARGET_FLAGS
+ #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
+ 
++#undef TARGET_OPTION_OPTIMIZATION_TABLE
++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
+ struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
new file mode 100644
index 00000000..ca1a2b9f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -0,0 +1,107 @@
+From bb65903ab6293a47d154764a585f6c53b5fcf853 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:16:53 +0530
+Subject: [PATCH 62/63] Added new MB-64 single register arithmetic instructions
+
+---
+ gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3e7c647..4d40cc5 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -654,6 +654,18 @@
+    }
+ })
+ 
++(define_insn "adddi3_int"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++  (plus:DI (match_operand:DI 1 "register_operand" "%0")
++                 (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++  addlik\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")]
++)
++
+ (define_insn "*adddi3_long"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+@@ -719,6 +731,18 @@
+ {
+ }")
+ 
++(define_insn "subdi316imm"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (minus:DI (match_operand:DI 1 "register_operand" "d")
++                  (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
++  "@
++   addlik\t%0,-%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
++
+ (define_insn "subsidi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
+@@ -1015,6 +1039,17 @@
+ ;; Logical
+ ;;----------------------------------------------------------------
+ 
++(define_insn "anddi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (and:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   andli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "anddi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
+@@ -1042,6 +1077,16 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "iordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (ior:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   orli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
+ 
+ (define_insn "iordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+@@ -1069,6 +1114,17 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "xordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (xor:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   xorli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "xordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 00000000..e7dfa89c
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,41 @@
+From 612e6579116e6714417ea21e6c13b0968bb6aac2 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 8 May 2019 14:12:03 +0530
+Subject: [PATCH 62/62] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+ disable fivopts by default
+
+Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
+
+ * gcc/common/config/microblaze/microblaze-common.c
+   (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+---
+ gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index fe45f2e..2873d4b 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -27,13 +27,15 @@
+ /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
+ static const struct default_options microblaze_option_optimization_table[] =
+   {
+-    /* Turn off ivopts by default. It messes up cse. */
++    /* Turn off ivopts by default. It messes up cse. 
++    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
+     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
+-    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+     { OPT_LEVELS_NONE, 0, NULL, 0 }
+   };
+ 
+ #undef TARGET_DEFAULT_TARGET_FLAGS
+ #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
+ 
++#undef TARGET_OPTION_OPTIMIZATION_TABLE
++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
+ struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
new file mode 100644
index 00000000..edf6a0f3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -0,0 +1,44 @@
+From d4b23a1dd0564bcf67b5b88a68d62eb49bdab15d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:55:22 +0530
+Subject: [PATCH 63/63] [Patch,MicroBlaze] : Added support for 64 bit Immediate
+ values.
+
+---
+ gcc/config/microblaze/constraints.md | 4 ++--
+ gcc/config/microblaze/microblaze.md  | 3 +--
+ 2 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 9a5aa6b..e87a90f 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -53,9 +53,9 @@
+        (match_test "ival > 0 && ival < 0x10000")))
+ 
+ (define_constraint "K"
+-  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
++  "A constant in the range  -9223372036854775808 to 9223372036854775807 (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
++       (match_test "ival > (long long)-9223372036854775808  && ival < (long long)9223372036854775807")))
+ 
+ ;; Define floating point constraints
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4d40cc5..6e74503 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1334,8 +1334,7 @@
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
+ 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
+   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
+-           (GET_CODE (operands[1]) == CONST_INT && 
+-                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
++           (GET_CODE (operands[1]) == CONST_INT))"
+   "@
+    addlk\t%0,r0,r0\t
+    addlik\t%0,r0,%1\t #N1 %X1
+-- 
+2.7.4
+
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
deleted file mode 100644
index d6a81912..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend
+++ /dev/null
@@ -1,65 +0,0 @@
-# Add MicroBlaze Patches (only when using MicroBlaze)
-FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-8:"
-SRC_URI_append_microblaze = " \
-file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
-        file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \
-        file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \
-        file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
-        file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
-        file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
-        file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
-        file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
-        file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \
-        file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
-        file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
-        file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
-        file://0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch \
-        file://0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
-        file://0015-Patch-microblaze-Disable-fivopts-by-default.patch \
-        file://0016-Patch-microblaze-Removed-moddi3-routinue.patch \
-        file://0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
-        file://0018-Patch-microblaze-Add-optimized-lshrsi3.patch \
-        file://0019-Patch-microblaze-Modified-trap-instruction.patch \
-        file://0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
-        file://0021-Patch-microblaze-Add-cbranchsi4_reg.patch \
-        file://0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
-        file://0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \
-        file://0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
-        file://0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
-        file://0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
-        file://0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch \
-        file://0028-Patch-microblaze-Correct-the-const-high-double-immed.patch \
-        file://0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
-        file://0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
-        file://0031-Patch-microblaze-Add-new-bit-field-instructions.patch \
-        file://0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
-        file://0033-Fixing-the-bug-in-the-bit-field-instruction.patch \
-        file://0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch \
-        file://0035-Fixing-the-issue-with-the-builtin_alloc.patch \
-        file://0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch \
-        file://0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
-        file://0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
-        file://0039-Intial-commit-of-64-bit-Microblaze.patch \
-        file://0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch \
-        file://0041-Intial-commit-for-64bit-MB-sources.patch \
-        file://0042-re-arrangement-of-the-compare-branches.patch \
-        file://0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
-        file://0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
-        file://0045-Fixed-issues-like.patch \
-        file://0046-Fixed-below-issues.patch \
-        file://0047-Added-double-arith-instructions.patch \
-        file://0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
-        file://0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
-        file://0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
-        file://0051-fixing-the-typo-errors-in-umodsi3-file.patch \
-        file://0052-fixing-the-32bit-LTO-related-issue9-1014024.patch \
-        file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
-        file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
-        file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-        file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
-        file://0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
-        file://0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \
-        file://0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
-        file://0061-Author-Nagaraju-nmekala-xilinx.com.patch \
-        file://0055-microblaze_linker_script_xilinx_ld.patch \
-"
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend
new file mode 100644
index 00000000..f9a87dfb
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_9.%.bbappend
@@ -0,0 +1,67 @@
+# Add MicroBlaze Patches (only when using MicroBlaze)
+FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-9:"
+SRC_URI_append_microblaze = " \
+        file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
+        file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \
+        file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \
+        file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
+        file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
+        file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
+        file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
+        file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
+        file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \
+        file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
+        file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
+        file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
+        file://0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch \
+        file://0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
+        file://0015-Patch-microblaze-Disable-fivopts-by-default.patch \
+        file://0016-Patch-microblaze-Removed-moddi3-routinue.patch \
+        file://0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
+        file://0018-Patch-microblaze-Add-optimized-lshrsi3.patch \
+        file://0019-Patch-microblaze-Modified-trap-instruction.patch \
+        file://0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
+        file://0021-Patch-microblaze-Add-cbranchsi4_reg.patch \
+        file://0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
+        file://0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \
+        file://0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
+        file://0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
+        file://0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
+        file://0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch \
+        file://0028-Patch-microblaze-Correct-the-const-high-double-immed.patch \
+        file://0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
+        file://0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
+        file://0031-Patch-microblaze-Add-new-bit-field-instructions.patch \
+        file://0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
+        file://0033-Fixing-the-bug-in-the-bit-field-instruction.patch \
+        file://0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch \
+        file://0035-Fixing-the-issue-with-the-builtin_alloc.patch \
+        file://0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch \
+        file://0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
+        file://0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
+        file://0039-Intial-commit-of-64-bit-Microblaze.patch \
+        file://0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch \
+        file://0041-Intial-commit-for-64bit-MB-sources.patch \
+        file://0042-re-arrangement-of-the-compare-branches.patch \
+        file://0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
+        file://0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
+        file://0045-Fixed-issues-like.patch \
+        file://0046-Fixed-below-issues.patch \
+        file://0047-Added-double-arith-instructions.patch \
+        file://0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
+        file://0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
+        file://0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
+        file://0051-fixing-the-typo-errors-in-umodsi3-file.patch \
+        file://0052-fixing-the-32bit-LTO-related-issue9-1014024.patch \
+        file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
+        file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
+        file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+        file://0056-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
+        file://0057-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
+        file://0058-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \
+        file://0059-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
+        file://0060-Author-Nagaraju-nmekala-xilinx.com.patch \
+        file://0061-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
+        file://0062-Added-new-MB-64-single-register-arithmetic-instructi.patch \
+        file://0063-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
+"
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb
index 3c13c697..4fe82bbe 100644
--- a/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb
+++ b/meta-xilinx-bsp/recipes-multimedia/vcu/kernel-module-vcu.bb
@@ -5,14 +5,13 @@ LICENSE = "GPLv2"
 LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a"
 
 XILINX_VCU_VERSION = "1.0.0"
-XILINX_RELEASE_VERSION = "v2019.1"
 PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
 
 S = "${WORKDIR}/git"
 
-BRANCH ?= "master-rel-2019.1"
+BRANCH ?= "release-2019.2"
 REPO ?= "git://github.com/xilinx/vcu-modules.git;protocol=https"
-SRCREV ?= "13a8e5b3f614d94081481a808aa8d4bd00b26d76"
+SRCREV ?= "d4b46f2ee10e5d13609ca982d8d8bae662468837"
 
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb
index 25bbffe9..dcef6610 100644
--- a/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb
+++ b/meta-xilinx-bsp/recipes-multimedia/vcu/libomxil-xlnx.bb
@@ -4,12 +4,11 @@ LICENSE = "Proprietary"
 LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
 
 XILINX_VCU_VERSION = "1.0.0"
-XILINX_RELEASE_VERSION = "v2019.1"
 PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
 
-BRANCH ?= "master-rel-2019.1"
+BRANCH ?= "release-2019.2"
 REPO   ?= "git://github.com/xilinx/vcu-omx-il.git;protocol=https"
-SRCREV ?= "b93cec02cd5da223fa965073dce130a08ffd6419"
+SRCREV ?= "9bbb40e3ceddd9e166d1d97aa4ac380459166344"
 
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb
index 8f8c0ef2..8b15fac7 100644
--- a/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb
+++ b/meta-xilinx-bsp/recipes-multimedia/vcu/libvcu-xlnx.bb
@@ -4,12 +4,11 @@ LICENSE = "Proprietary"
 LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
 
 XILINX_VCU_VERSION = "1.0.0"
-XILINX_RELEASE_VERSION = "v2019.1"
 PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
 
-BRANCH ?= "master-rel-2019.1"
+BRANCH ?= "release-2019.2"
 REPO   ?= "git://github.com/xilinx/vcu-ctrl-sw.git;protocol=https"
-SRCREV ?= "32b7be620987283f62e4469185da81dddad1071c"
+SRCREV ?= "f3001b44eeaf770cbd9f95d2cfd0b02d3f65b2d3"
 
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb
index 28bd0d37..9a617ef5 100644
--- a/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb
+++ b/meta-xilinx-bsp/recipes-multimedia/vcu/vcu-firmware.bb
@@ -4,14 +4,13 @@ LICENSE = "Proprietary"
 LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498"
 
 XILINX_VCU_VERSION = "1.0.0"
-XILINX_RELEASE_VERSION = "v2019.1"
 PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
 
 S  = "${WORKDIR}/git"
 
-BRANCH ?= "master-rel-2019.1"
+BRANCH ?= "release-2019.2"
 REPO ?= "git://github.com/xilinx/vcu-firmware.git;protocol=https"
-SRCREV ?= "4078b74d16e5eccca5ae3132c3877d3aff7fb168"
+SRCREV ?= "29ab982965b797b1c9b567faba47378578398f4a"
 
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI   = "${REPO};${BRANCHARG}"
diff --git a/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
index 4bb41b7d..28992708 100644
--- a/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
+++ b/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
@@ -3,14 +3,18 @@ DESCRIPTION = "Xilinx Runtime User Space Libraries and headers"
 
 LICENSE = "GPLv2 & Apache-2.0"
 LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSE;md5=fa343562af4b9b922b8d7fe7b0b6d000 \
-                    file://runtime_src/driver/xclng/drm/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
-                    file://runtime_src/driver/xclng/xrt/user_gem/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \
-                    file://runtime_src/driver/xclng/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87"
+                    file://runtime_src/core/edge/drm/zocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
+                    file://runtime_src/core/pcie/driver/linux/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
+                    file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \
+                    file://runtime_src/core/pcie/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 "
 
-SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https;nobranch=1"
+BRANCH ?= "2019.2"
+REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
 
 PV = "2.2.0+git${SRCPV}"
-SRCREV = "da87ac894a037d7e11c0496361458efed4bab438"
+SRCREV = "7e3540d2707443d8c824669ef4272b33ce2f9ba4"
 
 S = "${WORKDIR}/git/src"
 
diff --git a/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb
index b47f45fd..3d1972d4 100644
--- a/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb
+++ b/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb
@@ -4,10 +4,13 @@ DESCRIPTION = "Xilinx Runtime driver module provides memory management and compu
 LICENSE = "GPLv2"
 LIC_FILES_CHKSUM = "file://LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263"
 
-SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https"
+BRANCH ?= "2019.2"
+REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
 
 PV = "2.2.0+git${SRCPV}"
-SRCREV = "da87ac894a037d7e11c0496361458efed4bab438"
+SRCREV = "7e3540d2707443d8c824669ef4272b33ce2f9ba4"
 
 S = "${WORKDIR}/git/src/runtime_src/driver/zynq/drm/zocl"
 
diff --git a/meta-xilinx-contrib/conf/layer.conf b/meta-xilinx-contrib/conf/layer.conf
index 942925eb..93a4c69b 100644
--- a/meta-xilinx-contrib/conf/layer.conf
+++ b/meta-xilinx-contrib/conf/layer.conf
@@ -12,5 +12,6 @@ BBFILE_PRIORITY_xilinx-contrib = "5"
 LAYERDEPENDS_xilinx-contrib = "core"
 LAYERDEPENDS_xilinx-contrib = "xilinx"
 
-LAYERSERIES_COMPAT_xilinx-contrib = "warrior"
+LAYERSERIES_COMPAT_xilinx-contrib = "zeus"
 
+XILINX_RELEASE_VERSION = "v2019.2"
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
deleted file mode 100644
index 660bc218..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
+++ /dev/null
@@ -1,305 +0,0 @@
-From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001
-From: Jason Wu <jason.wu.misc@gmail.com>
-Date: Sun, 10 Apr 2016 13:14:13 +1000
-Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
-
-Add the dglnt_encoder driver that enables DRM support for the VGA and
-HDMI output ports found on many Digilent boards.
-
-Upstream-Status: Pending
-
-Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
-Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
----
- .../bindings/drm/xilinx/dglnt_encoder.txt          |  23 +++
- drivers/gpu/drm/xilinx/Kconfig                     |   6 +
- drivers/gpu/drm/xilinx/Makefile                    |   1 +
- drivers/gpu/drm/xilinx/dglnt_encoder.c             | 217 +++++++++++++++++++++
- 4 files changed, 247 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
- create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
-
-diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
-new file mode 100644
-index 0000000..242b24e
---- /dev/null
-+++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
-@@ -0,0 +1,23 @@
-+Device-Tree bindings for Digilent DRM Encoder Slave
-+
-+This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
-+The VGA or HDMI port must be connected to a Xilinx display pipeline via an
-+axi2vid IP core.
-+
-+Required properties:
-+ - compatible: Should be "digilent,drm-encoder".
-+
-+Optional properties:
-+ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
-+                   connector. This is used to obtain the supported resolutions
-+                   of an attached monitor. If not defined, then a default
-+                   set of resolutions is used and the display will initialize
-+                   to 720p. Note most VGA connectors on Digilent boards do
-+                   not have the DDC bus routed out.
-+
-+Example:
-+
-+	encoder_0: digilent_encoder {
-+		compatible = "digilent,drm-encoder";
-+		dglnt,edid-i2c = <&i2c1>;
-+	};
-diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
-index 57e18a9..d9ecff2 100644
---- a/drivers/gpu/drm/xilinx/Kconfig
-+++ b/drivers/gpu/drm/xilinx/Kconfig
-@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB
- 	help
- 	  DRM driver for Xilinx Display Port Subsystem.
- 
-+config DRM_DIGILENT_ENCODER
-+   tristate "Digilent VGA/HDMI DRM Encoder Driver"
-+   depends on DRM_XILINX
-+   help
-+     DRM slave encoder for Video-out on Digilent boards.
-+
- config DRM_XILINX_DP_SUB_DEBUG_FS
- 	bool "Xilinx DRM DPSUB debugfs"
- 	depends on DEBUG_FS && DRM_XILINX_DP_SUB
-diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
-index 19bc154..c2717e40 100644
---- a/drivers/gpu/drm/xilinx/Makefile
-+++ b/drivers/gpu/drm/xilinx/Makefile
-@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \
- 		xilinx_drm_plane.o
- xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
- 
-+obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
- obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
- obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
- obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
-diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
-new file mode 100644
-index 0000000..cb9fc7d
---- /dev/null
-+++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
-@@ -0,0 +1,217 @@
-+/*
-+ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
-+ *
-+ * Copyright (C) 2015 Digilent
-+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
-+ *
-+ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
-+ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <drm/drmP.h>
-+#include <drm/drm_edid.h>
-+#include <drm/drm_encoder_slave.h>
-+
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <linux/i2c.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define DGLNT_ENC_MAX_FREQ 150000
-+#define DGLNT_ENC_MAX_H 1920
-+#define DGLNT_ENC_MAX_V 1080
-+#define DGLNT_ENC_PREF_H 1280
-+#define DGLNT_ENC_PREF_V 720
-+
-+struct dglnt_encoder {
-+	struct drm_encoder *encoder;
-+	struct i2c_adapter *i2c_bus;
-+	bool i2c_present;
-+};
-+
-+static inline struct dglnt_encoder *to_dglnt_encoder(
-+					struct drm_encoder *encoder)
-+{
-+	return to_encoder_slave(encoder)->slave_priv;
-+}
-+
-+static bool dglnt_mode_fixup(struct drm_encoder *encoder,
-+				const struct drm_display_mode *mode,
-+				struct drm_display_mode *adjusted_mode)
-+{
-+	return true;
-+}
-+
-+static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
-+				struct drm_display_mode *mode,
-+				struct drm_display_mode *adjusted_mode)
-+{
-+}
-+
-+static void
-+dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
-+{
-+}
-+
-+static void dglnt_encoder_save(struct drm_encoder *encoder)
-+{
-+}
-+
-+static void dglnt_encoder_restore(struct drm_encoder *encoder)
-+{
-+}
-+
-+static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
-+				struct drm_display_mode *mode)
-+{
-+	if (mode &&
-+		!(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
-+			DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
-+		(mode->clock <= DGLNT_ENC_MAX_FREQ) &&
-+		(mode->hdisplay <= DGLNT_ENC_MAX_H) &&
-+		(mode->vdisplay <= DGLNT_ENC_MAX_V))
-+		return MODE_OK;
-+	return MODE_BAD;
-+}
-+
-+static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
-+				struct drm_connector *connector)
-+{
-+	struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
-+	struct edid *edid;
-+	int num_modes = 0;
-+
-+	if (dglnt->i2c_present) {
-+		edid = drm_get_edid(connector, dglnt->i2c_bus);
-+		drm_connector_update_edid_property(connector, edid);
-+		if (edid) {
-+			num_modes = drm_add_edid_modes(connector, edid);
-+			kfree(edid);
-+		}
-+	} else {
-+		num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
-+						DGLNT_ENC_MAX_V);
-+		drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
-+					DGLNT_ENC_PREF_V);
-+	}
-+	return num_modes;
-+}
-+
-+static enum drm_connector_status dglnt_encoder_detect(
-+					struct drm_encoder *encoder,
-+					struct drm_connector *connector)
-+{
-+	struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
-+
-+	if (dglnt->i2c_present) {
-+		if (drm_probe_ddc(dglnt->i2c_bus))
-+			return connector_status_connected;
-+		return connector_status_disconnected;
-+	} else
-+		return connector_status_unknown;
-+}
-+
-+static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
-+	.dpms			= dglnt_encoder_dpms,
-+	.save			= dglnt_encoder_save,
-+	.restore		= dglnt_encoder_restore,
-+	.mode_fixup		= dglnt_mode_fixup,
-+	.mode_valid		= dglnt_encoder_mode_valid,
-+	.mode_set		= dglnt_encoder_mode_set,
-+	.detect			= dglnt_encoder_detect,
-+	.get_modes		= dglnt_encoder_get_modes,
-+};
-+
-+static int dglnt_encoder_encoder_init(struct platform_device *pdev,
-+				struct drm_device *dev,
-+				struct drm_encoder_slave *encoder)
-+{
-+	struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
-+	struct device_node *sub_node;
-+
-+	encoder->slave_priv = dglnt;
-+	encoder->slave_funcs = &dglnt_encoder_slave_funcs;
-+
-+	dglnt->encoder = &encoder->base;
-+
-+	/* get i2c adapter for edid */
-+	dglnt->i2c_present = false;
-+	sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
-+	if (sub_node) {
-+		dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
-+		if (!dglnt->i2c_bus)
-+			DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
-+		else
-+			dglnt->i2c_present = true;
-+		of_node_put(sub_node);
-+	}
-+
-+	return 0;
-+}
-+
-+static int dglnt_encoder_probe(struct platform_device *pdev)
-+{
-+	struct dglnt_encoder *dglnt;
-+
-+	dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
-+	if (!dglnt)
-+		return -ENOMEM;
-+
-+	platform_set_drvdata(pdev, dglnt);
-+
-+	return 0;
-+}
-+
-+static int dglnt_encoder_remove(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+
-+static const struct of_device_id dglnt_encoder_of_match[] = {
-+	{ .compatible = "digilent,drm-encoder", },
-+	{ /* end of table */ },
-+};
-+MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
-+
-+static struct drm_platform_encoder_driver dglnt_encoder_driver = {
-+	.platform_driver = {
-+		.probe			= dglnt_encoder_probe,
-+		.remove			= dglnt_encoder_remove,
-+		.driver			= {
-+			.owner		= THIS_MODULE,
-+			.name		= "dglnt-drm-enc",
-+			.of_match_table	= dglnt_encoder_of_match,
-+		},
-+	},
-+
-+	.encoder_init = dglnt_encoder_encoder_init,
-+};
-+
-+static int __init dglnt_encoder_init(void)
-+{
-+	return platform_driver_register(&dglnt_encoder_driver.platform_driver);
-+}
-+
-+static void __exit dglnt_encoder_exit(void)
-+{
-+	platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
-+}
-+
-+module_init(dglnt_encoder_init);
-+module_exit(dglnt_encoder_exit);
-+
-+MODULE_AUTHOR("Digilent, Inc.");
-+MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
-+MODULE_LICENSE("GPL v2");
--- 
-2.7.4
-
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
deleted file mode 100644
index 9b6229db..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
+++ /dev/null
@@ -1,607 +0,0 @@
-From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001
-From: Jason Wu <jason.wu.misc@gmail.com>
-Date: Sun, 10 Apr 2016 13:16:06 +1000
-Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
-
-Add support for the axi_dynclk IP Core available from Digilent. This IP
-core dynamically configures the clock resources inside a Xilinx FPGA to
-generate a clock with a software programmable frequency.
-
-Upstream-Status: Pending
-
-Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
-Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
----
- drivers/clk/Kconfig            |   8 +
- drivers/clk/Makefile           |   1 +
- drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 556 insertions(+)
- create mode 100644 drivers/clk/clk-dglnt-dynclk.c
-
-diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
-index dccb111100..7fe65a702b 100644
---- a/drivers/clk/Kconfig
-+++ b/drivers/clk/Kconfig
-@@ -148,6 +148,14 @@ config CLK_QORIQ
- 	  This adds the clock driver support for Freescale QorIQ platforms
- 	  using common clock framework.
- 
-+config COMMON_CLK_DGLNT_DYNCLK
-+	tristate "Digilent axi_dynclk Driver"
-+	depends on ARCH_ZYNQ || MICROBLAZE
-+	help
-+	---help---
-+	  Support for the Digilent AXI Dynamic Clock core for Xilinx
-+	  FPGAs.
-+
- config COMMON_CLK_XGENE
- 	bool "Clock driver for APM XGene SoC"
- 	default y
-diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
-index 0760449dde..45ce97d053 100644
---- a/drivers/clk/Makefile
-+++ b/drivers/clk/Makefile
-@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
- obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o
- obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o
- obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o
-+obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK)	+= clk-dglnt-dynclk.o
- obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
- obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
- obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o
-diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
-new file mode 100644
-index 0000000000..496ad5fc90
---- /dev/null
-+++ b/drivers/clk/clk-dglnt-dynclk.c
-@@ -0,0 +1,547 @@
-+/*
-+ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
-+ *
-+ * Copyright (C) 2015 Digilent
-+ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
-+ *
-+ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/clk-provider.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/io.h>
-+#include <linux/of.h>
-+#include <linux/module.h>
-+#include <linux/err.h>
-+#include <linux/kernel.h>
-+
-+#define CLK_BIT_WEDGE 13
-+#define CLK_BIT_NOCOUNT 12
-+
-+/* This value is used to signal an error */
-+#define ERR_CLKCOUNTCALC 0xFFFFFFFF
-+#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
-+
-+#define DYNCLK_DIV_1_REGMASK 0x1041
-+/* 25 MHz (125 KHz / 5) */
-+#define DYNCLK_DEFAULT_FREQ 125000
-+
-+#define MMCM_FREQ_VCOMIN 600000
-+#define MMCM_FREQ_VCOMAX 1200000
-+#define MMCM_FREQ_PFDMIN 10000
-+#define MMCM_FREQ_PFDMAX 450000
-+#define MMCM_FREQ_OUTMIN 4000
-+#define MMCM_FREQ_OUTMAX 800000
-+#define MMCM_DIV_MAX 106
-+#define MMCM_FB_MIN 2
-+#define MMCM_FB_MAX 64
-+#define MMCM_CLKDIV_MAX 128
-+#define MMCM_CLKDIV_MIN 1
-+
-+#define OFST_DISPLAY_CTRL 0x0
-+#define OFST_DISPLAY_STATUS 0x4
-+#define OFST_DISPLAY_CLK_L 0x8
-+#define OFST_DISPLAY_FB_L 0x0C
-+#define OFST_DISPLAY_FB_H_CLK_H 0x10
-+#define OFST_DISPLAY_DIV 0x14
-+#define OFST_DISPLAY_LOCK_L 0x18
-+#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
-+
-+static const u64 lock_lookup[64] = {
-+	0b0011000110111110100011111010010000000001,
-+	0b0011000110111110100011111010010000000001,
-+	0b0100001000111110100011111010010000000001,
-+	0b0101101011111110100011111010010000000001,
-+	0b0111001110111110100011111010010000000001,
-+	0b1000110001111110100011111010010000000001,
-+	0b1001110011111110100011111010010000000001,
-+	0b1011010110111110100011111010010000000001,
-+	0b1100111001111110100011111010010000000001,
-+	0b1110011100111110100011111010010000000001,
-+	0b1111111111111000010011111010010000000001,
-+	0b1111111111110011100111111010010000000001,
-+	0b1111111111101110111011111010010000000001,
-+	0b1111111111101011110011111010010000000001,
-+	0b1111111111101000101011111010010000000001,
-+	0b1111111111100111000111111010010000000001,
-+	0b1111111111100011111111111010010000000001,
-+	0b1111111111100010011011111010010000000001,
-+	0b1111111111100000110111111010010000000001,
-+	0b1111111111011111010011111010010000000001,
-+	0b1111111111011101101111111010010000000001,
-+	0b1111111111011100001011111010010000000001,
-+	0b1111111111011010100111111010010000000001,
-+	0b1111111111011001000011111010010000000001,
-+	0b1111111111011001000011111010010000000001,
-+	0b1111111111010111011111111010010000000001,
-+	0b1111111111010101111011111010010000000001,
-+	0b1111111111010101111011111010010000000001,
-+	0b1111111111010100010111111010010000000001,
-+	0b1111111111010100010111111010010000000001,
-+	0b1111111111010010110011111010010000000001,
-+	0b1111111111010010110011111010010000000001,
-+	0b1111111111010010110011111010010000000001,
-+	0b1111111111010001001111111010010000000001,
-+	0b1111111111010001001111111010010000000001,
-+	0b1111111111010001001111111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001,
-+	0b1111111111001111101011111010010000000001
-+};
-+
-+static const u32 filter_lookup_low[64] = {
-+	0b0001011111,
-+	0b0001010111,
-+	0b0001111011,
-+	0b0001011011,
-+	0b0001101011,
-+	0b0001110011,
-+	0b0001110011,
-+	0b0001110011,
-+	0b0001110011,
-+	0b0001001011,
-+	0b0001001011,
-+	0b0001001011,
-+	0b0010110011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001010011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0001100011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010010011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011,
-+	0b0010100011
-+};
-+
-+struct dglnt_dynclk_reg;
-+struct dglnt_dynclk_mode;
-+struct dglnt_dynclk;
-+
-+struct dglnt_dynclk_reg {
-+	u32 clk0L;
-+	u32 clkFBL;
-+	u32 clkFBH_clk0H;
-+	u32 divclk;
-+	u32 lockL;
-+	u32 fltr_lockH;
-+};
-+
-+struct dglnt_dynclk_mode {
-+	u32 freq;
-+	u32 fbmult;
-+	u32 clkdiv;
-+	u32 maindiv;
-+};
-+
-+struct dglnt_dynclk {
-+	void __iomem *base;
-+	struct clk_hw clk_hw;
-+	unsigned long freq;
-+};
-+
-+u32 dglnt_dynclk_divider(u32 divide)
-+{
-+	u32 output = 0;
-+	u32 highTime = 0;
-+	u32 lowTime = 0;
-+
-+	if ((divide < 1) || (divide > 128))
-+		return ERR_CLKDIVIDER;
-+
-+	if (divide == 1)
-+		return DYNCLK_DIV_1_REGMASK;
-+
-+	highTime = divide / 2;
-+	/* if divide is odd */
-+	if (divide & 0x1) {
-+		lowTime = highTime + 1;
-+		output = 1 << CLK_BIT_WEDGE;
-+	} else {
-+		lowTime = highTime;
-+	}
-+
-+	output |= 0x03F & lowTime;
-+	output |= 0xFC0 & (highTime << 6);
-+	return output;
-+}
-+
-+u32 dglnt_dynclk_count_calc(u32 divide)
-+{
-+	u32 output = 0;
-+	u32 divCalc = 0;
-+
-+	divCalc = dglnt_dynclk_divider(divide);
-+	if (divCalc == ERR_CLKDIVIDER)
-+		output = ERR_CLKCOUNTCALC;
-+	else
-+		output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
-+	return output;
-+}
-+
-+
-+int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
-+			  struct dglnt_dynclk_mode *clkParams)
-+{
-+	if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
-+		return -EINVAL;
-+
-+	regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
-+	if (regValues->clk0L == ERR_CLKCOUNTCALC)
-+		return -EINVAL;
-+
-+	regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
-+	if (regValues->clkFBL == ERR_CLKCOUNTCALC)
-+		return -EINVAL;
-+
-+	regValues->clkFBH_clk0H = 0;
-+
-+	regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
-+	if (regValues->divclk == ERR_CLKDIVIDER)
-+		return -EINVAL;
-+
-+	regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
-+				 0xFFFFFFFF);
-+
-+	regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
-+				       32) & 0x000000FF);
-+	regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
-+				   16) & 0x03FF0000);
-+
-+	return 0;
-+}
-+
-+void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
-+			    void __iomem *baseaddr)
-+{
-+	writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
-+	writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
-+	writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
-+	writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
-+	writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
-+	writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
-+}
-+
-+u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
-+			   struct dglnt_dynclk_mode *bestPick)
-+{
-+	u32 bestError = MMCM_FREQ_OUTMAX;
-+	u32 curError;
-+	u32 curClkMult;
-+	u32 curFreq;
-+	u32 divVal;
-+	u32 curFb, curClkDiv;
-+	u32 minFb = 0;
-+	u32 maxFb = 0;
-+	u32 curDiv = 1;
-+	u32 maxDiv;
-+	bool freq_found = false;
-+
-+	bestPick->freq = 0;
-+	if (parentFreq == 0)
-+		return 0;
-+
-+	/* minimum frequency is actually dictated by VCOmin */
-+	if (freq < MMCM_FREQ_OUTMIN)
-+		freq = MMCM_FREQ_OUTMIN;
-+	if (freq > MMCM_FREQ_OUTMAX)
-+		freq = MMCM_FREQ_OUTMAX;
-+
-+	if (parentFreq > MMCM_FREQ_PFDMAX)
-+		curDiv = 2;
-+	maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
-+	if (maxDiv > MMCM_DIV_MAX)
-+		maxDiv = MMCM_DIV_MAX;
-+
-+	while (curDiv <= maxDiv && !freq_found) {
-+		minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
-+		maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
-+		if (maxFb > MMCM_FB_MAX)
-+			maxFb = MMCM_FB_MAX;
-+		if (minFb < MMCM_FB_MIN)
-+			minFb = MMCM_FB_MIN;
-+
-+		divVal = curDiv * freq;
-+		/*
-+		 * This multiplier is used to find the best clkDiv value for
-+		 * each FB value
-+		 */
-+		curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
-+
-+		curFb = minFb;
-+		while (curFb <= maxFb && !freq_found) {
-+			curClkDiv = ((curClkMult * curFb) + 500) / 1000;
-+			if (curClkDiv > MMCM_CLKDIV_MAX)
-+				curClkDiv = MMCM_CLKDIV_MAX;
-+			if (curClkDiv < MMCM_CLKDIV_MIN)
-+				curClkDiv = MMCM_CLKDIV_MIN;
-+			curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
-+			if (curFreq >= freq)
-+				curError = curFreq - freq;
-+			else
-+				curError = freq - curFreq;
-+			if (curError < bestError) {
-+				bestError = curError;
-+				bestPick->clkdiv = curClkDiv;
-+				bestPick->fbmult = curFb;
-+				bestPick->maindiv = curDiv;
-+				bestPick->freq = curFreq;
-+			}
-+			if (!curError)
-+				freq_found = true;
-+			curFb++;
-+		}
-+		curDiv++;
-+	}
-+	return bestPick->freq;
-+}
-+
-+static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
-+{
-+	return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
-+}
-+
-+
-+static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
-+{
-+	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
-+	unsigned int clock_state;
-+
-+	if (dglnt_dynclk->freq) {
-+		writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
-+		do {
-+			clock_state = readl(dglnt_dynclk->base +
-+					    OFST_DISPLAY_STATUS);
-+		} while (!clock_state);
-+	}
-+	return 0;
-+}
-+
-+static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
-+{
-+	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
-+
-+	writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
-+}
-+
-+static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
-+	unsigned long rate, unsigned long parent_rate)
-+{
-+	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
-+	struct dglnt_dynclk_reg clkReg;
-+	struct dglnt_dynclk_mode clkMode;
-+
-+	if (parent_rate == 0 || rate == 0)
-+		return -EINVAL;
-+	if (rate == dglnt_dynclk->freq)
-+		return 0;
-+
-+	/*
-+	 * Convert from Hz to KHz, then multiply by five to account for
-+	 * BUFR division
-+	 */
-+	rate = (rate + 100) / 200;
-+	/* convert from Hz to KHz */
-+	parent_rate = (parent_rate + 500) / 1000;
-+	if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
-+		return -EINVAL;
-+
-+	/*
-+	 * Write to the PLL dynamic configuration registers to configure it
-+	 * with the calculated parameters.
-+	 */
-+	dglnt_dynclk_find_reg(&clkReg, &clkMode);
-+	dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
-+	dglnt_dynclk->freq = clkMode.freq * 200;
-+	dglnt_dynclk_disable(clk_hw);
-+	dglnt_dynclk_enable(clk_hw);
-+
-+	return 0;
-+}
-+
-+static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
-+	unsigned long *parent_rate)
-+{
-+	struct dglnt_dynclk_mode clkMode;
-+
-+	dglnt_dynclk_find_mode(((rate + 100) / 200),
-+		((*parent_rate) + 500) / 1000, &clkMode);
-+
-+	return (clkMode.freq * 200);
-+}
-+
-+static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
-+	unsigned long parent_rate)
-+{
-+	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
-+
-+	return dglnt_dynclk->freq;
-+}
-+
-+
-+static const struct clk_ops dglnt_dynclk_ops = {
-+	.recalc_rate = dglnt_dynclk_recalc_rate,
-+	.round_rate = dglnt_dynclk_round_rate,
-+	.set_rate = dglnt_dynclk_set_rate,
-+	.enable = dglnt_dynclk_enable,
-+	.disable = dglnt_dynclk_disable,
-+};
-+
-+static const struct of_device_id dglnt_dynclk_ids[] = {
-+	{ .compatible = "digilent,axi-dynclk", },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
-+
-+static int dglnt_dynclk_probe(struct platform_device *pdev)
-+{
-+	const struct of_device_id *id;
-+	struct dglnt_dynclk *dglnt_dynclk;
-+	struct clk_init_data init;
-+	const char *parent_name;
-+	const char *clk_name;
-+	struct resource *mem;
-+	struct clk *clk;
-+
-+	if (!pdev->dev.of_node)
-+		return -ENODEV;
-+
-+	id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
-+	if (!id)
-+		return -ENODEV;
-+
-+	dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
-+				    GFP_KERNEL);
-+	if (!dglnt_dynclk)
-+		return -ENOMEM;
-+
-+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
-+	if (IS_ERR(dglnt_dynclk->base))
-+		return PTR_ERR(dglnt_dynclk->base);
-+
-+	parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
-+	if (!parent_name)
-+		return -EINVAL;
-+
-+	clk_name = pdev->dev.of_node->name;
-+	of_property_read_string(pdev->dev.of_node, "clock-output-names",
-+		&clk_name);
-+
-+	init.name = clk_name;
-+	init.ops = &dglnt_dynclk_ops;
-+	init.flags = 0;
-+	init.parent_names = &parent_name;
-+	init.num_parents = 1;
-+
-+	dglnt_dynclk->freq = 0;
-+	dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
-+
-+	dglnt_dynclk->clk_hw.init = &init;
-+	clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
-+	if (IS_ERR(clk))
-+		return PTR_ERR(clk);
-+
-+	return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
-+				   clk);
-+}
-+
-+static int dglnt_dynclk_remove(struct platform_device *pdev)
-+{
-+	of_clk_del_provider(pdev->dev.of_node);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver dglnt_dynclk_driver = {
-+	.driver = {
-+		.name = "dglnt-dynclk",
-+		.owner = THIS_MODULE,
-+		.of_match_table = dglnt_dynclk_ids,
-+	},
-+	.probe = dglnt_dynclk_probe,
-+	.remove = dglnt_dynclk_remove,
-+};
-+module_platform_driver(dglnt_dynclk_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
-+MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
--- 
-2.14.2
-
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
deleted file mode 100644
index a98d84c5..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
-From: Nathan Rossi <nathan@nathanrossi.com>
-Date: Mon, 2 May 2016 23:46:42 +1000
-Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
-
-Fix the issues where the VTC is reset (losing its timing config).
-
-Also fix the issue where the plane destroys its DMA descriptors and
-marks the DMA channels as inactive but never recreates the descriptors
-and never updates the active state when turning DPMS back on.
-
-Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
-Upstream-Status: Pending [This is a workaround]
----
- drivers/gpu/drm/xilinx/xilinx_drm_crtc.c  | 1 -
- drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
-index 631d35b921..93dbd4b58a 100644
---- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
-+++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
-@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
- 	default:
- 		if (crtc->vtc) {
- 			xilinx_vtc_disable(crtc->vtc);
--			xilinx_vtc_reset(crtc->vtc);
- 		}
- 		if (crtc->cresample) {
- 			xilinx_cresample_disable(crtc->cresample);
-diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
-index 6a248b72d4..d2518a4bdf 100644
---- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
-+++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
-@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
- 	for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
- 		struct xilinx_drm_plane_dma *dma = &plane->dma[i];
- 
--		if (dma->chan && dma->is_active) {
-+		if (dma->chan) {
- 			flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
- 			desc = dmaengine_prep_interleaved_dma(dma->chan,
- 							      &dma->xt,
-@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
- 			dmaengine_submit(desc);
- 
- 			dma_async_issue_pending(dma->chan);
-+			dma->is_active = true;
- 		}
- 	}
- }
--- 
-2.14.2
-
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg
deleted file mode 100644
index f71e53ab..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.1/0004-minized-wifi-bluetooth.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# Bluetooth config
-#
-CONFIG_BT=y
-CONFIG_BT_BREDR=y
-CONFIG_BT_HS=y
-CONFIG_BT_LE=y
-CONFIG_BT_BCM=y
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCM=y
-CONFIG_BT_HIDP=y
-CONFIG_CFG80211=y
-CONFIG_CFG80211_DEFAULT_PS=y
-CONFIG_CFG80211_CRDA_SUPPORT=y
-CONFIG_BRCMUTIL=y
-CONFIG_BRCMFMAC=y
-CONFIG_BRCMFMAC_PROTO_BCDC=y
-CONFIG_BRCMFMAC_SDIO=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_SHA256=y
-
-#
-# Regulator config
-#
-CONFIG_REGMAP_IRQ=y
-CONFIG_I2C_XILINX=y
-CONFIG_MFD_DA9062=y
-CONFIG_REGULATOR_DA9062=y
-
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
new file mode 100644
index 00000000..660bc218
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch
@@ -0,0 +1,305 @@
+From 21cc8144efdaa3cd8dbd7279f87b14fa3432fae4 Mon Sep 17 00:00:00 2001
+From: Jason Wu <jason.wu.misc@gmail.com>
+Date: Sun, 10 Apr 2016 13:14:13 +1000
+Subject: [PATCH 1/3] drm: xilinx: Add encoder for Digilent boards
+
+Add the dglnt_encoder driver that enables DRM support for the VGA and
+HDMI output ports found on many Digilent boards.
+
+Upstream-Status: Pending
+
+Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
+Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
+---
+ .../bindings/drm/xilinx/dglnt_encoder.txt          |  23 +++
+ drivers/gpu/drm/xilinx/Kconfig                     |   6 +
+ drivers/gpu/drm/xilinx/Makefile                    |   1 +
+ drivers/gpu/drm/xilinx/dglnt_encoder.c             | 217 +++++++++++++++++++++
+ 4 files changed, 247 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+ create mode 100644 drivers/gpu/drm/xilinx/dglnt_encoder.c
+
+diff --git a/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+new file mode 100644
+index 0000000..242b24e
+--- /dev/null
++++ b/Documentation/devicetree/bindings/drm/xilinx/dglnt_encoder.txt
+@@ -0,0 +1,23 @@
++Device-Tree bindings for Digilent DRM Encoder Slave
++
++This driver provides support for VGA and HDMI outputs on Digilent FPGA boards.
++The VGA or HDMI port must be connected to a Xilinx display pipeline via an
++axi2vid IP core.
++
++Required properties:
++ - compatible: Should be "digilent,drm-encoder".
++
++Optional properties:
++ - dglnt,edid-i2c: The I2C device connected to the DDC bus on the video
++                   connector. This is used to obtain the supported resolutions
++                   of an attached monitor. If not defined, then a default
++                   set of resolutions is used and the display will initialize
++                   to 720p. Note most VGA connectors on Digilent boards do
++                   not have the DDC bus routed out.
++
++Example:
++
++	encoder_0: digilent_encoder {
++		compatible = "digilent,drm-encoder";
++		dglnt,edid-i2c = <&i2c1>;
++	};
+diff --git a/drivers/gpu/drm/xilinx/Kconfig b/drivers/gpu/drm/xilinx/Kconfig
+index 57e18a9..d9ecff2 100644
+--- a/drivers/gpu/drm/xilinx/Kconfig
++++ b/drivers/gpu/drm/xilinx/Kconfig
+@@ -33,6 +33,12 @@ config DRM_XILINX_DP_SUB
+ 	help
+ 	  DRM driver for Xilinx Display Port Subsystem.
+ 
++config DRM_DIGILENT_ENCODER
++   tristate "Digilent VGA/HDMI DRM Encoder Driver"
++   depends on DRM_XILINX
++   help
++     DRM slave encoder for Video-out on Digilent boards.
++
+ config DRM_XILINX_DP_SUB_DEBUG_FS
+ 	bool "Xilinx DRM DPSUB debugfs"
+ 	depends on DEBUG_FS && DRM_XILINX_DP_SUB
+diff --git a/drivers/gpu/drm/xilinx/Makefile b/drivers/gpu/drm/xilinx/Makefile
+index 19bc154..c2717e40 100644
+--- a/drivers/gpu/drm/xilinx/Makefile
++++ b/drivers/gpu/drm/xilinx/Makefile
+@@ -7,6 +7,7 @@ xilinx_drm-y := xilinx_drm_crtc.o xilinx_drm_connector.o xilinx_drm_drv.o \
+ 		xilinx_drm_plane.o
+ xilinx_drm-y += xilinx_cresample.o xilinx_osd.o xilinx_rgb2yuv.o xilinx_vtc.o
+ 
++obj-$(CONFIG_DRM_DIGILENT_ENCODER) += dglnt_encoder.o
+ obj-$(CONFIG_DRM_XILINX) += xilinx_drm.o
+ obj-$(CONFIG_DRM_XILINX_DP) += xilinx_drm_dp.o
+ obj-$(CONFIG_DRM_XILINX_DP_SUB) += xilinx_drm_dp_sub.o
+diff --git a/drivers/gpu/drm/xilinx/dglnt_encoder.c b/drivers/gpu/drm/xilinx/dglnt_encoder.c
+new file mode 100644
+index 0000000..cb9fc7d
+--- /dev/null
++++ b/drivers/gpu/drm/xilinx/dglnt_encoder.c
+@@ -0,0 +1,217 @@
++/*
++ * dglnt_encoder.c - DRM slave encoder for Video-out on Digilent boards
++ *
++ * Copyright (C) 2015 Digilent
++ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
++ *
++ * Based on udl_encoder.c and udl_connector.c, Copyright (C) 2012 Red Hat.
++ * Also based on xilinx_drm_dp.c, Copyright (C) 2014 Xilinx, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_encoder_slave.h>
++
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/i2c.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define DGLNT_ENC_MAX_FREQ 150000
++#define DGLNT_ENC_MAX_H 1920
++#define DGLNT_ENC_MAX_V 1080
++#define DGLNT_ENC_PREF_H 1280
++#define DGLNT_ENC_PREF_V 720
++
++struct dglnt_encoder {
++	struct drm_encoder *encoder;
++	struct i2c_adapter *i2c_bus;
++	bool i2c_present;
++};
++
++static inline struct dglnt_encoder *to_dglnt_encoder(
++					struct drm_encoder *encoder)
++{
++	return to_encoder_slave(encoder)->slave_priv;
++}
++
++static bool dglnt_mode_fixup(struct drm_encoder *encoder,
++				const struct drm_display_mode *mode,
++				struct drm_display_mode *adjusted_mode)
++{
++	return true;
++}
++
++static void dglnt_encoder_mode_set(struct drm_encoder *encoder,
++				struct drm_display_mode *mode,
++				struct drm_display_mode *adjusted_mode)
++{
++}
++
++static void
++dglnt_encoder_dpms(struct drm_encoder *encoder, int mode)
++{
++}
++
++static void dglnt_encoder_save(struct drm_encoder *encoder)
++{
++}
++
++static void dglnt_encoder_restore(struct drm_encoder *encoder)
++{
++}
++
++static int dglnt_encoder_mode_valid(struct drm_encoder *encoder,
++				struct drm_display_mode *mode)
++{
++	if (mode &&
++		!(mode->flags & ((DRM_MODE_FLAG_INTERLACE |
++			DRM_MODE_FLAG_DBLCLK) | DRM_MODE_FLAG_3D_MASK)) &&
++		(mode->clock <= DGLNT_ENC_MAX_FREQ) &&
++		(mode->hdisplay <= DGLNT_ENC_MAX_H) &&
++		(mode->vdisplay <= DGLNT_ENC_MAX_V))
++		return MODE_OK;
++	return MODE_BAD;
++}
++
++static int dglnt_encoder_get_modes(struct drm_encoder *encoder,
++				struct drm_connector *connector)
++{
++	struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
++	struct edid *edid;
++	int num_modes = 0;
++
++	if (dglnt->i2c_present) {
++		edid = drm_get_edid(connector, dglnt->i2c_bus);
++		drm_connector_update_edid_property(connector, edid);
++		if (edid) {
++			num_modes = drm_add_edid_modes(connector, edid);
++			kfree(edid);
++		}
++	} else {
++		num_modes = drm_add_modes_noedid(connector, DGLNT_ENC_MAX_H,
++						DGLNT_ENC_MAX_V);
++		drm_set_preferred_mode(connector, DGLNT_ENC_PREF_H,
++					DGLNT_ENC_PREF_V);
++	}
++	return num_modes;
++}
++
++static enum drm_connector_status dglnt_encoder_detect(
++					struct drm_encoder *encoder,
++					struct drm_connector *connector)
++{
++	struct dglnt_encoder *dglnt = to_dglnt_encoder(encoder);
++
++	if (dglnt->i2c_present) {
++		if (drm_probe_ddc(dglnt->i2c_bus))
++			return connector_status_connected;
++		return connector_status_disconnected;
++	} else
++		return connector_status_unknown;
++}
++
++static struct drm_encoder_slave_funcs dglnt_encoder_slave_funcs = {
++	.dpms			= dglnt_encoder_dpms,
++	.save			= dglnt_encoder_save,
++	.restore		= dglnt_encoder_restore,
++	.mode_fixup		= dglnt_mode_fixup,
++	.mode_valid		= dglnt_encoder_mode_valid,
++	.mode_set		= dglnt_encoder_mode_set,
++	.detect			= dglnt_encoder_detect,
++	.get_modes		= dglnt_encoder_get_modes,
++};
++
++static int dglnt_encoder_encoder_init(struct platform_device *pdev,
++				struct drm_device *dev,
++				struct drm_encoder_slave *encoder)
++{
++	struct dglnt_encoder *dglnt = platform_get_drvdata(pdev);
++	struct device_node *sub_node;
++
++	encoder->slave_priv = dglnt;
++	encoder->slave_funcs = &dglnt_encoder_slave_funcs;
++
++	dglnt->encoder = &encoder->base;
++
++	/* get i2c adapter for edid */
++	dglnt->i2c_present = false;
++	sub_node = of_parse_phandle(pdev->dev.of_node, "dglnt,edid-i2c", 0);
++	if (sub_node) {
++		dglnt->i2c_bus = of_find_i2c_adapter_by_node(sub_node);
++		if (!dglnt->i2c_bus)
++			DRM_INFO("failed to get the edid i2c adapter, using default modes\n");
++		else
++			dglnt->i2c_present = true;
++		of_node_put(sub_node);
++	}
++
++	return 0;
++}
++
++static int dglnt_encoder_probe(struct platform_device *pdev)
++{
++	struct dglnt_encoder *dglnt;
++
++	dglnt = devm_kzalloc(&pdev->dev, sizeof(*dglnt), GFP_KERNEL);
++	if (!dglnt)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, dglnt);
++
++	return 0;
++}
++
++static int dglnt_encoder_remove(struct platform_device *pdev)
++{
++	return 0;
++}
++
++static const struct of_device_id dglnt_encoder_of_match[] = {
++	{ .compatible = "digilent,drm-encoder", },
++	{ /* end of table */ },
++};
++MODULE_DEVICE_TABLE(of, dglnt_encoder_of_match);
++
++static struct drm_platform_encoder_driver dglnt_encoder_driver = {
++	.platform_driver = {
++		.probe			= dglnt_encoder_probe,
++		.remove			= dglnt_encoder_remove,
++		.driver			= {
++			.owner		= THIS_MODULE,
++			.name		= "dglnt-drm-enc",
++			.of_match_table	= dglnt_encoder_of_match,
++		},
++	},
++
++	.encoder_init = dglnt_encoder_encoder_init,
++};
++
++static int __init dglnt_encoder_init(void)
++{
++	return platform_driver_register(&dglnt_encoder_driver.platform_driver);
++}
++
++static void __exit dglnt_encoder_exit(void)
++{
++	platform_driver_unregister(&dglnt_encoder_driver.platform_driver);
++}
++
++module_init(dglnt_encoder_init);
++module_exit(dglnt_encoder_exit);
++
++MODULE_AUTHOR("Digilent, Inc.");
++MODULE_DESCRIPTION("DRM slave encoder for Video-out on Digilent boards");
++MODULE_LICENSE("GPL v2");
+-- 
+2.7.4
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
new file mode 100644
index 00000000..9b6229db
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch
@@ -0,0 +1,607 @@
+From 217e3b6f4393926b8dcad841381527ef3fc808c2 Mon Sep 17 00:00:00 2001
+From: Jason Wu <jason.wu.misc@gmail.com>
+Date: Sun, 10 Apr 2016 13:16:06 +1000
+Subject: [PATCH 2/3] clk: Add driver for axi_dynclk IP Core
+
+Add support for the axi_dynclk IP Core available from Digilent. This IP
+core dynamically configures the clock resources inside a Xilinx FPGA to
+generate a clock with a software programmable frequency.
+
+Upstream-Status: Pending
+
+Signed-off-by: Sam Bobrowicz <sbobrowicz@digilentinc.com>
+Signed-off-by: Jason Wu <jason.wu.misc@gmail.com>
+---
+ drivers/clk/Kconfig            |   8 +
+ drivers/clk/Makefile           |   1 +
+ drivers/clk/clk-dglnt-dynclk.c | 547 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 556 insertions(+)
+ create mode 100644 drivers/clk/clk-dglnt-dynclk.c
+
+diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
+index dccb111100..7fe65a702b 100644
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -148,6 +148,14 @@ config CLK_QORIQ
+ 	  This adds the clock driver support for Freescale QorIQ platforms
+ 	  using common clock framework.
+ 
++config COMMON_CLK_DGLNT_DYNCLK
++	tristate "Digilent axi_dynclk Driver"
++	depends on ARCH_ZYNQ || MICROBLAZE
++	help
++	---help---
++	  Support for the Digilent AXI Dynamic Clock core for Xilinx
++	  FPGAs.
++
+ config COMMON_CLK_XGENE
+ 	bool "Clock driver for APM XGene SoC"
+ 	default y
+diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
+index 0760449dde..45ce97d053 100644
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -24,6 +24,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
+ obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o
+ obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o
+ obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o
++obj-$(CONFIG_COMMON_CLK_DGLNT_DYNCLK)	+= clk-dglnt-dynclk.o
+ obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
+ obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o
+ obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o
+diff --git a/drivers/clk/clk-dglnt-dynclk.c b/drivers/clk/clk-dglnt-dynclk.c
+new file mode 100644
+index 0000000000..496ad5fc90
+--- /dev/null
++++ b/drivers/clk/clk-dglnt-dynclk.c
+@@ -0,0 +1,547 @@
++/*
++ * clk-dglnt-dynclk.c - Digilent AXI Dynamic Clock (axi_dynclk) Driver
++ *
++ * Copyright (C) 2015 Digilent
++ * Author: Sam Bobrowicz <sbobrowicz@digilentinc.com>
++ *
++ * Reused code from clk-axi-clkgen.c, Copyright (C) 2012-2013 Analog Devices Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/clk-provider.h>
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/module.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++
++#define CLK_BIT_WEDGE 13
++#define CLK_BIT_NOCOUNT 12
++
++/* This value is used to signal an error */
++#define ERR_CLKCOUNTCALC 0xFFFFFFFF
++#define ERR_CLKDIVIDER (1 << CLK_BIT_WEDGE | 1 << CLK_BIT_NOCOUNT)
++
++#define DYNCLK_DIV_1_REGMASK 0x1041
++/* 25 MHz (125 KHz / 5) */
++#define DYNCLK_DEFAULT_FREQ 125000
++
++#define MMCM_FREQ_VCOMIN 600000
++#define MMCM_FREQ_VCOMAX 1200000
++#define MMCM_FREQ_PFDMIN 10000
++#define MMCM_FREQ_PFDMAX 450000
++#define MMCM_FREQ_OUTMIN 4000
++#define MMCM_FREQ_OUTMAX 800000
++#define MMCM_DIV_MAX 106
++#define MMCM_FB_MIN 2
++#define MMCM_FB_MAX 64
++#define MMCM_CLKDIV_MAX 128
++#define MMCM_CLKDIV_MIN 1
++
++#define OFST_DISPLAY_CTRL 0x0
++#define OFST_DISPLAY_STATUS 0x4
++#define OFST_DISPLAY_CLK_L 0x8
++#define OFST_DISPLAY_FB_L 0x0C
++#define OFST_DISPLAY_FB_H_CLK_H 0x10
++#define OFST_DISPLAY_DIV 0x14
++#define OFST_DISPLAY_LOCK_L 0x18
++#define OFST_DISPLAY_FLTR_LOCK_H 0x1C
++
++static const u64 lock_lookup[64] = {
++	0b0011000110111110100011111010010000000001,
++	0b0011000110111110100011111010010000000001,
++	0b0100001000111110100011111010010000000001,
++	0b0101101011111110100011111010010000000001,
++	0b0111001110111110100011111010010000000001,
++	0b1000110001111110100011111010010000000001,
++	0b1001110011111110100011111010010000000001,
++	0b1011010110111110100011111010010000000001,
++	0b1100111001111110100011111010010000000001,
++	0b1110011100111110100011111010010000000001,
++	0b1111111111111000010011111010010000000001,
++	0b1111111111110011100111111010010000000001,
++	0b1111111111101110111011111010010000000001,
++	0b1111111111101011110011111010010000000001,
++	0b1111111111101000101011111010010000000001,
++	0b1111111111100111000111111010010000000001,
++	0b1111111111100011111111111010010000000001,
++	0b1111111111100010011011111010010000000001,
++	0b1111111111100000110111111010010000000001,
++	0b1111111111011111010011111010010000000001,
++	0b1111111111011101101111111010010000000001,
++	0b1111111111011100001011111010010000000001,
++	0b1111111111011010100111111010010000000001,
++	0b1111111111011001000011111010010000000001,
++	0b1111111111011001000011111010010000000001,
++	0b1111111111010111011111111010010000000001,
++	0b1111111111010101111011111010010000000001,
++	0b1111111111010101111011111010010000000001,
++	0b1111111111010100010111111010010000000001,
++	0b1111111111010100010111111010010000000001,
++	0b1111111111010010110011111010010000000001,
++	0b1111111111010010110011111010010000000001,
++	0b1111111111010010110011111010010000000001,
++	0b1111111111010001001111111010010000000001,
++	0b1111111111010001001111111010010000000001,
++	0b1111111111010001001111111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001,
++	0b1111111111001111101011111010010000000001
++};
++
++static const u32 filter_lookup_low[64] = {
++	0b0001011111,
++	0b0001010111,
++	0b0001111011,
++	0b0001011011,
++	0b0001101011,
++	0b0001110011,
++	0b0001110011,
++	0b0001110011,
++	0b0001110011,
++	0b0001001011,
++	0b0001001011,
++	0b0001001011,
++	0b0010110011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001010011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0001100011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010010011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011,
++	0b0010100011
++};
++
++struct dglnt_dynclk_reg;
++struct dglnt_dynclk_mode;
++struct dglnt_dynclk;
++
++struct dglnt_dynclk_reg {
++	u32 clk0L;
++	u32 clkFBL;
++	u32 clkFBH_clk0H;
++	u32 divclk;
++	u32 lockL;
++	u32 fltr_lockH;
++};
++
++struct dglnt_dynclk_mode {
++	u32 freq;
++	u32 fbmult;
++	u32 clkdiv;
++	u32 maindiv;
++};
++
++struct dglnt_dynclk {
++	void __iomem *base;
++	struct clk_hw clk_hw;
++	unsigned long freq;
++};
++
++u32 dglnt_dynclk_divider(u32 divide)
++{
++	u32 output = 0;
++	u32 highTime = 0;
++	u32 lowTime = 0;
++
++	if ((divide < 1) || (divide > 128))
++		return ERR_CLKDIVIDER;
++
++	if (divide == 1)
++		return DYNCLK_DIV_1_REGMASK;
++
++	highTime = divide / 2;
++	/* if divide is odd */
++	if (divide & 0x1) {
++		lowTime = highTime + 1;
++		output = 1 << CLK_BIT_WEDGE;
++	} else {
++		lowTime = highTime;
++	}
++
++	output |= 0x03F & lowTime;
++	output |= 0xFC0 & (highTime << 6);
++	return output;
++}
++
++u32 dglnt_dynclk_count_calc(u32 divide)
++{
++	u32 output = 0;
++	u32 divCalc = 0;
++
++	divCalc = dglnt_dynclk_divider(divide);
++	if (divCalc == ERR_CLKDIVIDER)
++		output = ERR_CLKCOUNTCALC;
++	else
++		output = (0xFFF & divCalc) | ((divCalc << 10) & 0x00C00000);
++	return output;
++}
++
++
++int dglnt_dynclk_find_reg(struct dglnt_dynclk_reg *regValues,
++			  struct dglnt_dynclk_mode *clkParams)
++{
++	if ((clkParams->fbmult < 2) || clkParams->fbmult > 64)
++		return -EINVAL;
++
++	regValues->clk0L = dglnt_dynclk_count_calc(clkParams->clkdiv);
++	if (regValues->clk0L == ERR_CLKCOUNTCALC)
++		return -EINVAL;
++
++	regValues->clkFBL = dglnt_dynclk_count_calc(clkParams->fbmult);
++	if (regValues->clkFBL == ERR_CLKCOUNTCALC)
++		return -EINVAL;
++
++	regValues->clkFBH_clk0H = 0;
++
++	regValues->divclk = dglnt_dynclk_divider(clkParams->maindiv);
++	if (regValues->divclk == ERR_CLKDIVIDER)
++		return -EINVAL;
++
++	regValues->lockL = (u32)(lock_lookup[clkParams->fbmult - 1] &
++				 0xFFFFFFFF);
++
++	regValues->fltr_lockH = (u32)((lock_lookup[clkParams->fbmult - 1] >>
++				       32) & 0x000000FF);
++	regValues->fltr_lockH |= ((filter_lookup_low[clkParams->fbmult - 1] <<
++				   16) & 0x03FF0000);
++
++	return 0;
++}
++
++void dglnt_dynclk_write_reg(struct dglnt_dynclk_reg *regValues,
++			    void __iomem *baseaddr)
++{
++	writel(regValues->clk0L, baseaddr + OFST_DISPLAY_CLK_L);
++	writel(regValues->clkFBL, baseaddr + OFST_DISPLAY_FB_L);
++	writel(regValues->clkFBH_clk0H, baseaddr + OFST_DISPLAY_FB_H_CLK_H);
++	writel(regValues->divclk, baseaddr + OFST_DISPLAY_DIV);
++	writel(regValues->lockL, baseaddr + OFST_DISPLAY_LOCK_L);
++	writel(regValues->fltr_lockH, baseaddr + OFST_DISPLAY_FLTR_LOCK_H);
++}
++
++u32 dglnt_dynclk_find_mode(u32 freq, u32 parentFreq,
++			   struct dglnt_dynclk_mode *bestPick)
++{
++	u32 bestError = MMCM_FREQ_OUTMAX;
++	u32 curError;
++	u32 curClkMult;
++	u32 curFreq;
++	u32 divVal;
++	u32 curFb, curClkDiv;
++	u32 minFb = 0;
++	u32 maxFb = 0;
++	u32 curDiv = 1;
++	u32 maxDiv;
++	bool freq_found = false;
++
++	bestPick->freq = 0;
++	if (parentFreq == 0)
++		return 0;
++
++	/* minimum frequency is actually dictated by VCOmin */
++	if (freq < MMCM_FREQ_OUTMIN)
++		freq = MMCM_FREQ_OUTMIN;
++	if (freq > MMCM_FREQ_OUTMAX)
++		freq = MMCM_FREQ_OUTMAX;
++
++	if (parentFreq > MMCM_FREQ_PFDMAX)
++		curDiv = 2;
++	maxDiv = parentFreq / MMCM_FREQ_PFDMIN;
++	if (maxDiv > MMCM_DIV_MAX)
++		maxDiv = MMCM_DIV_MAX;
++
++	while (curDiv <= maxDiv && !freq_found) {
++		minFb = curDiv * DIV_ROUND_UP(MMCM_FREQ_VCOMIN, parentFreq);
++		maxFb = curDiv * (MMCM_FREQ_VCOMAX / parentFreq);
++		if (maxFb > MMCM_FB_MAX)
++			maxFb = MMCM_FB_MAX;
++		if (minFb < MMCM_FB_MIN)
++			minFb = MMCM_FB_MIN;
++
++		divVal = curDiv * freq;
++		/*
++		 * This multiplier is used to find the best clkDiv value for
++		 * each FB value
++		 */
++		curClkMult = ((parentFreq * 1000) + (divVal / 2)) / divVal;
++
++		curFb = minFb;
++		while (curFb <= maxFb && !freq_found) {
++			curClkDiv = ((curClkMult * curFb) + 500) / 1000;
++			if (curClkDiv > MMCM_CLKDIV_MAX)
++				curClkDiv = MMCM_CLKDIV_MAX;
++			if (curClkDiv < MMCM_CLKDIV_MIN)
++				curClkDiv = MMCM_CLKDIV_MIN;
++			curFreq = (((parentFreq * curFb) / curDiv) / curClkDiv);
++			if (curFreq >= freq)
++				curError = curFreq - freq;
++			else
++				curError = freq - curFreq;
++			if (curError < bestError) {
++				bestError = curError;
++				bestPick->clkdiv = curClkDiv;
++				bestPick->fbmult = curFb;
++				bestPick->maindiv = curDiv;
++				bestPick->freq = curFreq;
++			}
++			if (!curError)
++				freq_found = true;
++			curFb++;
++		}
++		curDiv++;
++	}
++	return bestPick->freq;
++}
++
++static struct dglnt_dynclk *clk_hw_to_dglnt_dynclk(struct clk_hw *clk_hw)
++{
++	return container_of(clk_hw, struct dglnt_dynclk, clk_hw);
++}
++
++
++static int dglnt_dynclk_enable(struct clk_hw *clk_hw)
++{
++	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++	unsigned int clock_state;
++
++	if (dglnt_dynclk->freq) {
++		writel(1, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
++		do {
++			clock_state = readl(dglnt_dynclk->base +
++					    OFST_DISPLAY_STATUS);
++		} while (!clock_state);
++	}
++	return 0;
++}
++
++static void dglnt_dynclk_disable(struct clk_hw *clk_hw)
++{
++	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++
++	writel(0, dglnt_dynclk->base + OFST_DISPLAY_CTRL);
++}
++
++static int dglnt_dynclk_set_rate(struct clk_hw *clk_hw,
++	unsigned long rate, unsigned long parent_rate)
++{
++	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++	struct dglnt_dynclk_reg clkReg;
++	struct dglnt_dynclk_mode clkMode;
++
++	if (parent_rate == 0 || rate == 0)
++		return -EINVAL;
++	if (rate == dglnt_dynclk->freq)
++		return 0;
++
++	/*
++	 * Convert from Hz to KHz, then multiply by five to account for
++	 * BUFR division
++	 */
++	rate = (rate + 100) / 200;
++	/* convert from Hz to KHz */
++	parent_rate = (parent_rate + 500) / 1000;
++	if (!dglnt_dynclk_find_mode(rate, parent_rate, &clkMode))
++		return -EINVAL;
++
++	/*
++	 * Write to the PLL dynamic configuration registers to configure it
++	 * with the calculated parameters.
++	 */
++	dglnt_dynclk_find_reg(&clkReg, &clkMode);
++	dglnt_dynclk_write_reg(&clkReg, dglnt_dynclk->base);
++	dglnt_dynclk->freq = clkMode.freq * 200;
++	dglnt_dynclk_disable(clk_hw);
++	dglnt_dynclk_enable(clk_hw);
++
++	return 0;
++}
++
++static long dglnt_dynclk_round_rate(struct clk_hw *hw, unsigned long rate,
++	unsigned long *parent_rate)
++{
++	struct dglnt_dynclk_mode clkMode;
++
++	dglnt_dynclk_find_mode(((rate + 100) / 200),
++		((*parent_rate) + 500) / 1000, &clkMode);
++
++	return (clkMode.freq * 200);
++}
++
++static unsigned long dglnt_dynclk_recalc_rate(struct clk_hw *clk_hw,
++	unsigned long parent_rate)
++{
++	struct dglnt_dynclk *dglnt_dynclk = clk_hw_to_dglnt_dynclk(clk_hw);
++
++	return dglnt_dynclk->freq;
++}
++
++
++static const struct clk_ops dglnt_dynclk_ops = {
++	.recalc_rate = dglnt_dynclk_recalc_rate,
++	.round_rate = dglnt_dynclk_round_rate,
++	.set_rate = dglnt_dynclk_set_rate,
++	.enable = dglnt_dynclk_enable,
++	.disable = dglnt_dynclk_disable,
++};
++
++static const struct of_device_id dglnt_dynclk_ids[] = {
++	{ .compatible = "digilent,axi-dynclk", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, dglnt_dynclk_ids);
++
++static int dglnt_dynclk_probe(struct platform_device *pdev)
++{
++	const struct of_device_id *id;
++	struct dglnt_dynclk *dglnt_dynclk;
++	struct clk_init_data init;
++	const char *parent_name;
++	const char *clk_name;
++	struct resource *mem;
++	struct clk *clk;
++
++	if (!pdev->dev.of_node)
++		return -ENODEV;
++
++	id = of_match_node(dglnt_dynclk_ids, pdev->dev.of_node);
++	if (!id)
++		return -ENODEV;
++
++	dglnt_dynclk = devm_kzalloc(&pdev->dev, sizeof(*dglnt_dynclk),
++				    GFP_KERNEL);
++	if (!dglnt_dynclk)
++		return -ENOMEM;
++
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	dglnt_dynclk->base = devm_ioremap_resource(&pdev->dev, mem);
++	if (IS_ERR(dglnt_dynclk->base))
++		return PTR_ERR(dglnt_dynclk->base);
++
++	parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
++	if (!parent_name)
++		return -EINVAL;
++
++	clk_name = pdev->dev.of_node->name;
++	of_property_read_string(pdev->dev.of_node, "clock-output-names",
++		&clk_name);
++
++	init.name = clk_name;
++	init.ops = &dglnt_dynclk_ops;
++	init.flags = 0;
++	init.parent_names = &parent_name;
++	init.num_parents = 1;
++
++	dglnt_dynclk->freq = 0;
++	dglnt_dynclk_disable(&dglnt_dynclk->clk_hw);
++
++	dglnt_dynclk->clk_hw.init = &init;
++	clk = devm_clk_register(&pdev->dev, &dglnt_dynclk->clk_hw);
++	if (IS_ERR(clk))
++		return PTR_ERR(clk);
++
++	return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
++				   clk);
++}
++
++static int dglnt_dynclk_remove(struct platform_device *pdev)
++{
++	of_clk_del_provider(pdev->dev.of_node);
++
++	return 0;
++}
++
++static struct platform_driver dglnt_dynclk_driver = {
++	.driver = {
++		.name = "dglnt-dynclk",
++		.owner = THIS_MODULE,
++		.of_match_table = dglnt_dynclk_ids,
++	},
++	.probe = dglnt_dynclk_probe,
++	.remove = dglnt_dynclk_remove,
++};
++module_platform_driver(dglnt_dynclk_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Sam Bobrowicz <sbobrowicz@digilentinc.com>");
++MODULE_DESCRIPTION("CCF Driver for Digilent axi_dynclk IP Core");
+-- 
+2.14.2
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
new file mode 100644
index 00000000..a98d84c5
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0003-drm-xilinx-Fix-DPMS-transition-to-on.patch
@@ -0,0 +1,54 @@
+From 1a18e2b514ae9e75145597ac509a87f656c976ba Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan@nathanrossi.com>
+Date: Mon, 2 May 2016 23:46:42 +1000
+Subject: [PATCH 3/3] drm: xilinx: Fix DPMS transition to on
+
+Fix the issues where the VTC is reset (losing its timing config).
+
+Also fix the issue where the plane destroys its DMA descriptors and
+marks the DMA channels as inactive but never recreates the descriptors
+and never updates the active state when turning DPMS back on.
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending [This is a workaround]
+---
+ drivers/gpu/drm/xilinx/xilinx_drm_crtc.c  | 1 -
+ drivers/gpu/drm/xilinx/xilinx_drm_plane.c | 3 ++-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
+index 631d35b921..93dbd4b58a 100644
+--- a/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
++++ b/drivers/gpu/drm/xilinx/xilinx_drm_crtc.c
+@@ -88,7 +88,6 @@ static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
+ 	default:
+ 		if (crtc->vtc) {
+ 			xilinx_vtc_disable(crtc->vtc);
+-			xilinx_vtc_reset(crtc->vtc);
+ 		}
+ 		if (crtc->cresample) {
+ 			xilinx_cresample_disable(crtc->cresample);
+diff --git a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
+index 6a248b72d4..d2518a4bdf 100644
+--- a/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
++++ b/drivers/gpu/drm/xilinx/xilinx_drm_plane.c
+@@ -140,7 +140,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
+ 	for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
+ 		struct xilinx_drm_plane_dma *dma = &plane->dma[i];
+ 
+-		if (dma->chan && dma->is_active) {
++		if (dma->chan) {
+ 			flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+ 			desc = dmaengine_prep_interleaved_dma(dma->chan,
+ 							      &dma->xt,
+@@ -153,6 +153,7 @@ void xilinx_drm_plane_commit(struct drm_plane *base_plane)
+ 			dmaengine_submit(desc);
+ 
+ 			dma_async_issue_pending(dma->chan);
++			dma->is_active = true;
+ 		}
+ 	}
+ }
+-- 
+2.14.2
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg
new file mode 100644
index 00000000..f71e53ab
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx/v2019.2/0004-minized-wifi-bluetooth.cfg
@@ -0,0 +1,33 @@
+#
+# Bluetooth config
+#
+CONFIG_BT=y
+CONFIG_BT_BREDR=y
+CONFIG_BT_HS=y
+CONFIG_BT_LE=y
+CONFIG_BT_BCM=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HIDP=y
+CONFIG_CFG80211=y
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_CRDA_SUPPORT=y
+CONFIG_BRCMUTIL=y
+CONFIG_BRCMFMAC=y
+CONFIG_BRCMFMAC_PROTO_BCDC=y
+CONFIG_BRCMFMAC_SDIO=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
+
+#
+# Regulator config
+#
+CONFIG_REGMAP_IRQ=y
+CONFIG_I2C_XILINX=y
+CONFIG_MFD_DA9062=y
+CONFIG_REGULATOR_DA9062=y
+
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend
deleted file mode 100644
index 535fbb26..00000000
--- a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.1.bbappend
+++ /dev/null
@@ -1,9 +0,0 @@
-FILESEXTRAPATHS_prepend := "${THISDIR}/linux-xlnx:"
-
-SRC_URI_append_zybo-linux-bd-zynq7 = " \
-	file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
-	file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
-	file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
-	"
-
-SRC_URI_append_minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg"
diff --git a/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend
new file mode 100644
index 00000000..535fbb26
--- /dev/null
+++ b/meta-xilinx-contrib/recipes-kernel/linux/linux-xlnx_2019.2.bbappend
@@ -0,0 +1,9 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/linux-xlnx:"
+
+SRC_URI_append_zybo-linux-bd-zynq7 = " \
+	file://0001-drm-xilinx-Add-encoder-for-Digilent-boards.patch \
+	file://0002-clk-Add-driver-for-axi_dynclk-IP-Core.patch \
+	file://0003-drm-xilinx-Fix-DPMS-transition-to-on.patch \
+	"
+
+SRC_URI_append_minized-zynq7 = " file://0004-minized-wifi-bluetooth.cfg"
diff --git a/meta-xilinx-standalone/conf/layer.conf b/meta-xilinx-standalone/conf/layer.conf
index 16bfb74a..db3c2853 100644
--- a/meta-xilinx-standalone/conf/layer.conf
+++ b/meta-xilinx-standalone/conf/layer.conf
@@ -11,4 +11,5 @@ BBFILE_PRIORITY_xilinx-standalone = "5"
 
 LAYERDEPENDS_xilinx-standalone = "core xilinx"
 
-LAYERSERIES_COMPAT_xilinx-standalone = "warrior"
+LAYERSERIES_COMPAT_xilinx-standalone = "zeus"
+XILINX_RELEASE_VERSION = "v2019.2"
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend
deleted file mode 100644
index fc4db884..00000000
--- a/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.0.0.bbappend
+++ /dev/null
@@ -1,10 +0,0 @@
-do_configure_prepend_microblaze() {
-    # hack for microblaze, which needs xilinx.ld to literally do any linking (its hard coded in its LINK_SPEC)
-    export CC="${CC} -L${S}/libgloss/microblaze"
-}
-
-
-# We use libgloss as if it was libxil, to avoid linking issues
-do_install_append_zynqmp-pmu(){
-  cp ${D}/${libdir}/libgloss.a ${D}/${libdir}/libxil.a
-}
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend
new file mode 100644
index 00000000..fc4db884
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-standalone/newlib/libgloss_3.1.0.bbappend
@@ -0,0 +1,10 @@
+do_configure_prepend_microblaze() {
+    # hack for microblaze, which needs xilinx.ld to literally do any linking (its hard coded in its LINK_SPEC)
+    export CC="${CC} -L${S}/libgloss/microblaze"
+}
+
+
+# We use libgloss as if it was libxil, to avoid linking issues
+do_install_append_zynqmp-pmu(){
+  cp ${D}/${libdir}/libgloss.a ${D}/${libdir}/libxil.a
+}
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend
deleted file mode 100644
index e5249ab0..00000000
--- a/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.0.0.bbappend
+++ /dev/null
@@ -1,4 +0,0 @@
-do_configure_prepend_microblaze() {
-    # hack for microblaze, which needs xilinx.ld to literally do any linking (its hard coded in its LINK_SPEC)
-    export CC="${CC} -L${S}/libgloss/microblaze"
-}
diff --git a/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend b/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend
new file mode 100644
index 00000000..e5249ab0
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-standalone/newlib/newlib_3.1.0.bbappend
@@ -0,0 +1,4 @@
+do_configure_prepend_microblaze() {
+    # hack for microblaze, which needs xilinx.ld to literally do any linking (its hard coded in its LINK_SPEC)
+    export CC="${CC} -L${S}/libgloss/microblaze"
+}
diff --git a/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb b/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb
deleted file mode 100644
index 030de054..00000000
--- a/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.1.bb
+++ /dev/null
@@ -1,71 +0,0 @@
-inherit deploy
-
-LICENSE = "Proprietary"
-LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=e9b6d01d45faccfbf05d8caea53f0a35"
-
-XILINX_RELEASE_VERSION = "v2019.1"
-SRCREV = "26c14d9861010a0e3a55c73fb79efdb816eb42ca"
-PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}"
-
-SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1"
-
-COMPATIBLE_HOST = "microblaze.*-elf"
-COMPATIBLE_MACHINE = "^$"
-COMPATIBLE_MACHINE_zynqmp-pmu = "zynqmp-pmu"
-
-
-S = "${WORKDIR}/git/lib/sw_apps/zynqmp_pmufw/src"
-
-# The makefile does not handle parallelization
-PARALLEL_MAKE = ""
-
-do_configure() {
-    # manually do the copy_bsp step first, so as to be able to fix up use of
-    # mb-* commands
-    ${S}/../misc/copy_bsp.sh
-}
-
-COMPILER = "${CC}"
-COMPILER_FLAGS = "-O2 -c"
-EXTRA_COMPILER_FLAGS = "-g -Wall -Wextra -Os -flto -ffat-lto-objects"
-ARCHIVER = "${AR}"
-
-BSP_DIR ?= "${S}/../misc/zynqmp_pmufw_bsp"
-BSP_TARGETS_DIR ?= "${BSP_DIR}/psu_pmu_0/libsrc"
-
-def bsp_make_vars(d):
-    s = ["COMPILER", "CC", "COMPILER_FLAGS", "EXTRA_COMPILER_FLAGS", "ARCHIVER", "AR", "AS"]
-    return " ".join(["\"%s=%s\"" % (v, d.getVar(v)) for v in s])
-
-do_compile() {
-    # the Makefile in ${S}/../misc/Makefile, does not handle CC, AR, AS, etc
-    # properly. So do its job manually. Preparing the includes first, then libs.
-    for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
-        oe_runmake -C $(dirname $i) -s include ${@bsp_make_vars(d)}
-    done
-    for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
-        oe_runmake -C $(dirname $i) -s libs ${@bsp_make_vars(d)}
-    done
-
-    # --build-id=none is required due to linker script not defining a location for it.
-    # Again, recipe-systoot include is necessary
-    oe_runmake CC="${CC}" CC_FLAGS="-MMD -MP -Wl,--build-id=none -I${STAGING_DIR_TARGET}/usr/include"
-}
-
-do_install() {
-    :
-}
-
-PMU_FIRMWARE_BASE_NAME ?= "${BPN}-${PKGE}-${PKGV}-${PKGR}-${MACHINE}-${DATETIME}"
-PMU_FIRMWARE_BASE_NAME[vardepsexclude] = "DATETIME"
-
-do_deploy() {
-    install -Dm 0644 ${B}/executable.elf ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.elf
-    ln -sf ${PMU_FIRMWARE_BASE_NAME}.elf ${DEPLOYDIR}/${BPN}-${MACHINE}.elf
-    ${OBJCOPY} -O binary ${B}/executable.elf ${B}/executable.bin
-    install -m 0644 ${B}/executable.bin ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.bin
-    ln -sf ${PMU_FIRMWARE_BASE_NAME}.bin ${DEPLOYDIR}/${BPN}-${MACHINE}.bin
-}
-
-addtask deploy before do_build after do_install
-
diff --git a/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb b/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb
new file mode 100644
index 00000000..3d0142f8
--- /dev/null
+++ b/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2019.2.bb
@@ -0,0 +1,71 @@
+inherit deploy
+
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=39ab6ab638f4d1836ba994ec6852de94"
+
+XILINX_RELEASE_VERSION = "v2019.2"
+SRCREV = "e8db5fb118229fdc621e0ec7848641a23bf60998"
+PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1"
+
+COMPATIBLE_HOST = "microblaze.*-elf"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE_zynqmp-pmu = "zynqmp-pmu"
+
+
+S = "${WORKDIR}/git/lib/sw_apps/zynqmp_pmufw/src"
+
+# The makefile does not handle parallelization
+PARALLEL_MAKE = ""
+
+do_configure() {
+    # manually do the copy_bsp step first, so as to be able to fix up use of
+    # mb-* commands
+    ${S}/../misc/copy_bsp.sh
+}
+
+COMPILER = "${CC}"
+COMPILER_FLAGS = "-O2 -c"
+EXTRA_COMPILER_FLAGS = "-g -Wall -Wextra -Os -flto -ffat-lto-objects"
+ARCHIVER = "${AR}"
+
+BSP_DIR ?= "${S}/../misc/zynqmp_pmufw_bsp"
+BSP_TARGETS_DIR ?= "${BSP_DIR}/psu_pmu_0/libsrc"
+
+def bsp_make_vars(d):
+    s = ["COMPILER", "CC", "COMPILER_FLAGS", "EXTRA_COMPILER_FLAGS", "ARCHIVER", "AR", "AS"]
+    return " ".join(["\"%s=%s\"" % (v, d.getVar(v)) for v in s])
+
+do_compile() {
+    # the Makefile in ${S}/../misc/Makefile, does not handle CC, AR, AS, etc
+    # properly. So do its job manually. Preparing the includes first, then libs.
+    for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
+        oe_runmake -C $(dirname $i) -s include ${@bsp_make_vars(d)}
+    done
+    for i in $(ls ${BSP_TARGETS_DIR}/*/src/Makefile); do
+        oe_runmake -C $(dirname $i) -s libs ${@bsp_make_vars(d)}
+    done
+
+    # --build-id=none is required due to linker script not defining a location for it.
+    # Again, recipe-systoot include is necessary
+    oe_runmake CC="${CC}" CC_FLAGS="-MMD -MP -Wl,--build-id=none -I${STAGING_DIR_TARGET}/usr/include"
+}
+
+do_install() {
+    :
+}
+
+PMU_FIRMWARE_BASE_NAME ?= "${BPN}-${PKGE}-${PKGV}-${PKGR}-${MACHINE}-${DATETIME}"
+PMU_FIRMWARE_BASE_NAME[vardepsexclude] = "DATETIME"
+
+do_deploy() {
+    install -Dm 0644 ${B}/executable.elf ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.elf
+    ln -sf ${PMU_FIRMWARE_BASE_NAME}.elf ${DEPLOYDIR}/${BPN}-${MACHINE}.elf
+    ${OBJCOPY} -O binary ${B}/executable.elf ${B}/executable.bin
+    install -m 0644 ${B}/executable.bin ${DEPLOYDIR}/${PMU_FIRMWARE_BASE_NAME}.bin
+    ln -sf ${PMU_FIRMWARE_BASE_NAME}.bin ${DEPLOYDIR}/${BPN}-${MACHINE}.bin
+}
+
+addtask deploy before do_build after do_install
+
-- 
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