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authorNathan Rossi <nathan@nathanrossi.com>2017-12-13 16:58:34 -0800
committerManjukumar Matha <manjukumar.harthikote-matha@xilinx.com>2018-01-12 15:47:59 -0800
commit7935ef724cd7359ed97e6ae3d90ebc8f07dd7e1f (patch)
tree7c6faff836ccec34825a97fa7b7c49936e2bc4e2
parentfb15f2e401ed07f774ea89e0c91ecd927bf09235 (diff)
downloadmeta-xilinx-rocko.tar.gz
gcc-source: Add all Xilinx MicroBlaze GCC 7.2 patchesrocko
Add all the Xilinx patches for MicroBlaze, this includes a number of bug fixes, testsuite fixes, feature improvements and additional feature support. Important changes: * v10.0 - CPU support * v10.0 - Bit-field instruction support * v10.0 - 8-stage pipeline aka 'frequency' optimized * Size optimized implementations for shift instructions Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Diffstat
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch6
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch7
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-gcc-config-microblaze-Use-default-ident-output-gener.patch (renamed from meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-gcc-config-microblaze-Use-default-ident-output-gener.patch)7
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch76
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch36
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch118
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch37
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch46
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch68
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch32
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch69
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch44
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch37
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch53
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch156
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch46
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch29
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch38
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch104
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch87
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch33
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch212
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch64
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch78
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch195
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch72
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch42
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch48
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch126
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch250
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch52
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch48
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch83
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch51
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend33
35 files changed, 2394 insertions, 89 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
index 8501bd87..93af6514 100644
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch
@@ -1,7 +1,7 @@
1From cd395cbdaa551924459d6ecf143cb8e4a5771f2f Mon Sep 17 00:00:00 2001 1From 12cd383fbef719cc1a84cc80ff171073409a8557 Mon Sep 17 00:00:00 2001
2From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4> 2From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4>
3Date: Sat, 27 May 2017 18:29:40 +0000 3Date: Sat, 27 May 2017 18:29:40 +0000
4Subject: [PATCH 1/4] Revert: 2016-01-21 Ajit Agarwal 4Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal
5 <ajitkum@xilinx.com> 5 <ajitkum@xilinx.com>
6 6
7 See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html. 7 See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html.
@@ -38,5 +38,5 @@ index 66e4ef5c3d..2c9ece1d6c 100644
38 } 38 }
39 #define GP_REG_FIRST 0 39 #define GP_REG_FIRST 0
40-- 40--
412.11.0 412.14.2
42 42
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
index 9aa5d98a..03ea8b19 100644
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
@@ -1,8 +1,7 @@
1From db7a0ac634ccaa1781d0a0d17dfffd3f1719bb6d Mon Sep 17 00:00:00 2001 1From 2d90c10cf4d95999f68f474305828c7dfc51af18 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com> 2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Thu, 12 Nov 2015 16:09:31 +1000 3Date: Thu, 12 Nov 2015 16:09:31 +1000
4Subject: [PATCH 2/4] microblaze.md: Improve 'adddi3' and 'subdi3' insn 4Subject: [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions
5 definitions
6 5
7Change adddi3 to handle DI immediates as the second operand, this 6Change adddi3 to handle DI immediates as the second operand, this
8requires modification to the output template however reduces the need to 7requires modification to the output template however reduces the need to
@@ -63,5 +62,5 @@ index b3a0011fd7..8a372d7ebb 100644
63 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" 62 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
64 [(set_attr "type" "darith") 63 [(set_attr "type" "darith")
65-- 64--
662.11.0 652.14.2
67 66
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-gcc-config-microblaze-Use-default-ident-output-gener.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-gcc-config-microblaze-Use-default-ident-output-gener.patch
index 3b8a2f5d..9a310ab8 100644
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-gcc-config-microblaze-Use-default-ident-output-gener.patch
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-gcc-config-microblaze-Use-default-ident-output-gener.patch
@@ -1,8 +1,7 @@
1From 308ac81945b2674953797a9db4aee98397f88362 Mon Sep 17 00:00:00 2001 1From 89b0d852718f0ad2b48899880c2bc1e5dc979704 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com> 2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Sat, 27 May 2017 00:00:17 +1000 3Date: Sat, 27 May 2017 00:00:17 +1000
4Subject: [PATCH 4/4] gcc/config/microblaze: Use default ident output 4Subject: [PATCH] gcc/config/microblaze: Use default ident output generation
5 generation
6 5
7Remove the MicroBlaze specific TARGET_ASM_OUTPUT_IDENT definition, and 6Remove the MicroBlaze specific TARGET_ASM_OUTPUT_IDENT definition, and
8use the default. 7use the default.
@@ -76,5 +75,5 @@ index 2c9ece1d6c..ccd77e8b4d 100644
76 /* Default to -G 8 */ 75 /* Default to -G 8 */
77 #ifndef MICROBLAZE_DEFAULT_GVALUE 76 #ifndef MICROBLAZE_DEFAULT_GVALUE
78-- 77--
792.11.0 782.14.2
80 79
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch
deleted file mode 100644
index 9336291b..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch
+++ /dev/null
@@ -1,76 +0,0 @@
1From 6c7a10a9e077d0221cc9a6c5f5a6365815c1dca4 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Mon, 12 Jun 2017 00:28:42 +1000
4Subject: [PATCH 3/4] microblaze/sync.md: Correct behaviour and define
5 side-effects
6
7This change corrects the behaviour with regards to the bool output.
8Previously the definition would set the bool operand to true (non-zero)
9on failure, specifically at the 'cmp' against the expected operand which
10would be set non-zero when the memory != expected value. Instead of
11using the bool operand as the compare result use the clobbered %8
12operand for temporary comparison result and set the bool operand at the
13end of the definition to true (in this case the immediate value of 1).
14Also to ensure that the bool operand is 0 in all other cases the first
15instruction which is intended as a clear of the carry bit is reused to
16set the bool operand to 0 at the same time as clearing the carry bit.
17And finally the jump offsets were updated
18
19Additional to the behaviour change this change defines the side-effects
20of the atomic_compare_and_swap. Specifically the side effects where the
21bool and val operands are modified/set based on the value of the memory
22content. This prevents certain optimization behaviour from incorrectly
23optimizing away code. An example of this is the snippet below, where in
24certain cases the comparison is optimized away entirely.
25
26 mem = 2;
27 if (atomic_compare_and_swap(&mem, ...) == 2)
28 ...
29
30Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
31Upstream-Status: Unsubmitted
32---
33 gcc/config/microblaze/sync.md | 14 ++++++++------
34 1 file changed, 8 insertions(+), 6 deletions(-)
35
36diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
37index 8125bd8d63..605a9a969e 100644
38--- a/gcc/config/microblaze/sync.md
39+++ b/gcc/config/microblaze/sync.md
40@@ -18,9 +18,10 @@
41 ;; <http://www.gnu.org/licenses/>.
42
43 (define_insn "atomic_compare_and_swapsi"
44- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
45- (match_operand:SI 1 "register_operand" "=&d") ;; val output
46- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
47+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
48+ (match_operand:SI 2 "nonimmediate_operand" "+Q")) ;; memory
49+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
50+ (match_dup 2))
51 (match_operand:SI 3 "register_operand" "d") ;; expected value
52 (match_operand:SI 4 "register_operand" "d") ;; desired value
53 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
54@@ -29,15 +30,16 @@
55 (clobber (match_scratch:SI 8 "=&d"))]
56 ""
57 {
58- output_asm_insn ("addc \tr0,r0,r0", operands);
59+ output_asm_insn ("add \t%0,r0,r0", operands);
60 output_asm_insn ("lwx \t%1,%y2,r0", operands);
61 output_asm_insn ("addic\t%8,r0,0", operands);
62 output_asm_insn ("bnei \t%8,.-8", operands);
63- output_asm_insn ("cmp \t%0,%1,%3", operands);
64- output_asm_insn ("bnei \t%0,.+16", operands);
65+ output_asm_insn ("cmp \t%8,%1,%3", operands);
66+ output_asm_insn ("bnei \t%8,.+20", operands);
67 output_asm_insn ("swx \t%4,%y2,r0", operands);
68 output_asm_insn ("addic\t%8,r0,0", operands);
69 output_asm_insn ("bnei \t%8,.-28", operands);
70+ output_asm_insn ("addi \t%0,r0,1", operands);
71 return "";
72 }
73 )
74--
752.11.0
76
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
new file mode 100644
index 00000000..c0a427ea
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch
@@ -0,0 +1,36 @@
1From ab2cb6320138c173b20fee8ce6e8d4afa4696384 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:16 -0700
4Subject: [PATCH] dejagnu static testing on qemu, suppress warnings
5
6For dejagnu static testing on qemu, suppress warnings about multiple
7definitions from the test function and libc in line with method used by
8powerpc. Dynamic linking and using a qemu binary which understands
9sysroot resolves all test failures with builtins
10
11Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
12Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
13Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
14Upstream-Status: Pending
15---
16 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ++++
17 1 file changed, 4 insertions(+)
18
19diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
20index ba16b09c41..ada149912b 100644
21--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
22+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
23@@ -48,6 +48,10 @@ if { [istarget *-*-eabi*]
24 lappend additional_flags "-Wl,--allow-multiple-definition"
25 }
26
27+if [istarget "microblaze*-*-linux*"] {
28+ lappend additional_flags "-Wl,-zmuldefs"
29+}
30+
31 foreach src [lsort [find $srcdir/$subdir *.c]] {
32 if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
33 c-torture-execute [list $src \
34--
352.14.2
36
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
new file mode 100644
index 00000000..b428d121
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch
@@ -0,0 +1,118 @@
1From 7f0a129701ce9809d79ea4618f3293062bd24bbf Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:18 -0700
4Subject: [PATCH] Testsuite - explicitly add -fivopts for tests that depend on
5 it
6
7Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
8Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +-
13 gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +-
14 gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +-
15 gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +-
16 gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +-
17 gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +-
18 gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +-
19 gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
20 8 files changed, 8 insertions(+), 8 deletions(-)
21
22diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
23index 438db88204..ede883eb28 100644
24--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
25+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
26@@ -1,5 +1,5 @@
27 /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
28-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
29+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
30
31 void test (int *b, int *e, int stride)
32 {
33diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
34index eb72581390..02f3ea4a7d 100644
35--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
36+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
37@@ -1,5 +1,5 @@
38 // { dg-do compile }
39-// { dg-options "-O2 -fdump-tree-ivopts-details" }
40+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
41
42 class MinimalVec3
43 {
44diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
45index bda2516735..22c8a5dcff 100644
46--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
47+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
48@@ -1,7 +1,7 @@
49 /* A test for strength reduction and induction variable elimination. */
50
51 /* { dg-do compile } */
52-/* { dg-options "-O1 -fdump-tree-optimized" } */
53+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
54 /* { dg-require-effective-target size32plus } */
55
56 /* Size of this structure should be sufficiently weird so that no memory
57diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
58index f0770abdbb..65d74c8e62 100644
59--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
60+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
61@@ -1,7 +1,7 @@
62 /* A test for strength reduction and induction variable elimination. */
63
64 /* { dg-do compile } */
65-/* { dg-options "-O1 -fdump-tree-optimized" } */
66+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
67 /* { dg-require-effective-target size32plus } */
68
69 /* Size of this structure should be sufficiently weird so that no memory
70diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
71index 5f42857fe1..9bc86ee0d2 100644
72--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
73+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
74@@ -1,7 +1,7 @@
75 /* A test for induction variable merging. */
76
77 /* { dg-do compile } */
78-/* { dg-options "-O1 -fdump-tree-optimized" } */
79+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
80
81 void foo(long);
82
83diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
84index 3c8ee06016..db192a657f 100644
85--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
86+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
87@@ -1,5 +1,5 @@
88 /* { dg-do compile } */
89-/* { dg-options "-O2 -Wunsafe-loop-optimizations" } */
90+/* { dg-options "-O2 -fivopts -Wunsafe-loop-optimizations" } */
91 extern void g(void);
92
93 void
94diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
95index 2c6cfc6f83..648e6e67e8 100644
96--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
97+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
98@@ -1,5 +1,5 @@
99 /* { dg-do compile } */
100-/* { dg-options "-O2 -fdump-tree-ivopts" } */
101+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
102
103 void vnum_test8(int *data)
104 {
105diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
106index e911bfcd52..5d3e7e0801 100644
107--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
108+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
109@@ -1,5 +1,5 @@
110 /* { dg-do compile } */
111-/* { dg-options "-Os -fdump-tree-optimized" } */
112+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
113
114 /* Slightly changed testcase from PR middle-end/40815. */
115 void bar(char*, char*, int);
116--
1172.14.2
118
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
new file mode 100644
index 00000000..6fad8bf7
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch
@@ -0,0 +1,37 @@
1From 8bcdd551f7fe585126ea3173ece976fbc646c34a Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:20 -0700
4Subject: [PATCH] Add MicroBlaze to target-supports for atomic builtin tests
5
6MicroBlaze added to supported targets for atomic builtin tests.
7
8Changelog/testsuite
9
102014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
11
12 * gcc/testsuite/lib/target-supports.exp: Add microblaze to
13 check_effective_target_sync_int_long.
14
15Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
16Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
17Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
18Upstream-Status: Pending
19---
20 gcc/testsuite/lib/target-supports.exp | 1 +
21 1 file changed, 1 insertion(+)
22
23diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
24index 342af270ab..b0f510e596 100644
25--- a/gcc/testsuite/lib/target-supports.exp
26+++ b/gcc/testsuite/lib/target-supports.exp
27@@ -6715,6 +6715,7 @@ proc check_effective_target_sync_int_long { } {
28 && [check_effective_target_arm_acq_rel])
29 || [istarget bfin*-*linux*]
30 || [istarget hppa*-*linux*]
31+ || [istarget microblaze*-*linux*]
32 || [istarget s390*-*-*]
33 || [istarget powerpc*-*-*]
34 || [istarget crisv32-*-*] || [istarget cris-*-*]
35--
362.14.2
37
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
new file mode 100644
index 00000000..069329fc
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
@@ -0,0 +1,46 @@
1From 4622988b62335af6ef17d58bf10940419fd0f99f Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:21 -0700
4Subject: [PATCH] Update MicroBlaze strings test for new scan-assembly output
5 resulting in use of $LC label
6
7ChangeLog/testsuite
8
92014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
10
11 * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
12 to include $LC label.
13
14Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
15Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
16Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
17Upstream-Status: Pending
18---
19 gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
20 1 file changed, 4 insertions(+), 2 deletions(-)
21
22diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
23index 7a63faf79f..0403b7bdca 100644
24--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
25+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
26@@ -1,13 +1,15 @@
27 /* { dg-options "-O3" } */
28
29+/* { dg-final { scan-assembler "\.rodata*" } } */
30+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
31+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
32+
33 #include <string.h>
34
35-/* { dg-final { scan-assembler "\.rodata*" } } */
36 extern void somefunc (char *);
37 int testfunc ()
38 {
39 char string2[80];
40-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */
41 strcpy (string2, "hello");
42 somefunc (string2);
43 }
44--
452.14.2
46
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
new file mode 100644
index 00000000..dbfeb52b
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch
@@ -0,0 +1,68 @@
1From 037809e91bfed9c501ecd5272ff6d3ce96edf76c Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:22 -0700
4Subject: [PATCH] Allow MicroBlaze .weakext pattern in testsuite
5
6Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to
7include optional ext at the end of .weak to match the MicroBlaze weak
8label .weakext
9
10ChangeLog/testsuite
11
122014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
13
14 * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
15 pattern to take optional ext after .weak.
16 * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
17
18Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
19Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
20Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
21Upstream-Status: Pending
22---
23 gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++--
24 gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
25 gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
26 3 files changed, 4 insertions(+), 4 deletions(-)
27
28diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
29index 0316bcb5de..5a39a0811f 100644
30--- a/gcc/testsuite/g++.dg/abi/rtti3.C
31+++ b/gcc/testsuite/g++.dg/abi/rtti3.C
32@@ -3,8 +3,8 @@
33
34 // { dg-require-weak "" }
35 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
36-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
37-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
38+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
39+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
40 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
41 // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
42
43diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
44index f2347f79ec..dcec8a771a 100644
45--- a/gcc/testsuite/g++.dg/abi/thunk3.C
46+++ b/gcc/testsuite/g++.dg/abi/thunk3.C
47@@ -1,5 +1,5 @@
48 // { dg-require-weak "" }
49-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
50+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
51 // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
52
53 struct Base
54diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
55index fa5fbd4327..79cb311cab 100644
56--- a/gcc/testsuite/g++.dg/abi/thunk4.C
57+++ b/gcc/testsuite/g++.dg/abi/thunk4.C
58@@ -1,6 +1,6 @@
59 // { dg-require-weak "" }
60 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } }
61-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
62+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
63 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
64
65 struct Base
66--
672.14.2
68
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
new file mode 100644
index 00000000..6b9dd991
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
@@ -0,0 +1,32 @@
1From 23a04c06c2a689fed151eeb94c45ea9b512036ae Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:23 -0700
4Subject: [PATCH] Add MicroBlaze to check_profiling_available Testsuite
5
6Add MicroBlaze to check_profiling_available Testsuite, add
7microblaze*-*-* target in check_profiling_available inline with other
8archs setting profiling_available_saved to 0
9
10Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
11Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
12Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
13Upstream-Status: Pending
14---
15 gcc/testsuite/lib/target-supports.exp | 1 +
16 1 file changed, 1 insertion(+)
17
18diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
19index b0f510e596..fffb690e49 100644
20--- a/gcc/testsuite/lib/target-supports.exp
21+++ b/gcc/testsuite/lib/target-supports.exp
22@@ -625,6 +625,7 @@ proc check_profiling_available { test_what } {
23 || [istarget m68k-*-elf]
24 || [istarget m68k-*-uclinux*]
25 || [istarget mips*-*-elf*]
26+ || [istarget microblaze*-*-*]
27 || [istarget mmix-*-*]
28 || [istarget mn10300-*-elf*]
29 || [istarget moxie-*-elf*]
30--
312.14.2
32
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
new file mode 100644
index 00000000..c21ca816
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch
@@ -0,0 +1,69 @@
1From c1e8a1419e8f5d18e7135fb4fe3bf21941125008 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:24 -0700
4Subject: [PATCH] Fix atomic side effects.
5
6In atomic_compare_and_swapsi, add side effects to prevent incorrect
7assumptions during optimization. Previously, the outputs were considered
8unused; this generated assembly code with undefined side effects after
9invocation of the atomic.
10
11Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
12Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
13Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
14Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
15Upstream-Status: Pending
16---
17 gcc/config/microblaze/microblaze.md | 3 +++
18 gcc/config/microblaze/sync.md | 21 +++++++++++++--------
19 2 files changed, 16 insertions(+), 8 deletions(-)
20
21diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
22index 8a372d7ebb..59d629b559 100644
23--- a/gcc/config/microblaze/microblaze.md
24+++ b/gcc/config/microblaze/microblaze.md
25@@ -41,6 +41,9 @@
26 (UNSPEC_CMP 104) ;; signed compare
27 (UNSPEC_CMPU 105) ;; unsigned compare
28 (UNSPEC_TLS 106) ;; jump table
29+ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
30+ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
31+ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
32 ])
33
34 (define_c_enum "unspec" [
35diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
36index 8125bd8d63..edf4bdd811 100644
37--- a/gcc/config/microblaze/sync.md
38+++ b/gcc/config/microblaze/sync.md
39@@ -18,14 +18,19 @@
40 ;; <http://www.gnu.org/licenses/>.
41
42 (define_insn "atomic_compare_and_swapsi"
43- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
44- (match_operand:SI 1 "register_operand" "=&d") ;; val output
45- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
46- (match_operand:SI 3 "register_operand" "d") ;; expected value
47- (match_operand:SI 4 "register_operand" "d") ;; desired value
48- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
49- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
50- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
51+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
52+ (unspec_volatile:SI
53+ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
54+ (match_operand:SI 3 "register_operand" "d") ;; expected value
55+ (match_operand:SI 4 "register_operand" "d")] ;; desired value
56+ UNSPECV_CAS_BOOL))
57+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
58+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
59+ (set (match_dup 2)
60+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
61+ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
62+ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
63+ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
64 (clobber (match_scratch:SI 8 "=&d"))]
65 ""
66 {
67--
682.14.2
69
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 00000000..f4bc16e8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,44 @@
1From a5957bdf7acfde0a65eeba90bae11f5619bf96af Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:25 -0700
4Subject: [PATCH] Fix atomic boolean return value.
5
6In atomic_compare_and_swapsi, fix boolean return value. Previously, it
7contained zero if successful and non-zero if unsuccessful.
8
9Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
10Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
11Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
12Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
13Upstream-Status: Pending
14---
15 gcc/config/microblaze/sync.md | 7 ++++---
16 1 file changed, 4 insertions(+), 3 deletions(-)
17
18diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
19index edf4bdd811..aadb414728 100644
20--- a/gcc/config/microblaze/sync.md
21+++ b/gcc/config/microblaze/sync.md
22@@ -34,15 +34,16 @@
23 (clobber (match_scratch:SI 8 "=&d"))]
24 ""
25 {
26- output_asm_insn ("addc \tr0,r0,r0", operands);
27+ output_asm_insn ("add \t%0,r0,r0", operands);
28 output_asm_insn ("lwx \t%1,%y2,r0", operands);
29 output_asm_insn ("addic\t%8,r0,0", operands);
30 output_asm_insn ("bnei \t%8,.-8", operands);
31- output_asm_insn ("cmp \t%0,%1,%3", operands);
32- output_asm_insn ("bnei \t%0,.+16", operands);
33+ output_asm_insn ("cmp \t%8,%1,%3", operands);
34+ output_asm_insn ("bnei \t%8,.+20", operands);
35 output_asm_insn ("swx \t%4,%y2,r0", operands);
36 output_asm_insn ("addic\t%8,r0,0", operands);
37 output_asm_insn ("bnei \t%8,.-28", operands);
38+ output_asm_insn ("addi \t%0,r0,1", operands);
39 return "";
40 }
41 )
42--
432.14.2
44
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
new file mode 100644
index 00000000..464f59e3
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch
@@ -0,0 +1,37 @@
1From 1a9dcdb578452ecd53e0aec65fe6279233218778 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:26 -0700
4Subject: [PATCH] Fix the Microblaze crash with msmall-divides flag
5
6Fix the Microblaze crash with msmall-divides flag Compiler is crashing
7when we use msmall-divides and mxl-barrel-shift flag. This is because
8when use above flags microblaze_expand_divide function will be called
9for division operation. In microblaze_expand_divide function we are
10using sub_reg but MicroBlaze doesn't have subreg register due to this
11compiler was crashing. Changed the logic to avoid sub_reg call
12
13Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
14Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
15Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
16Upstream-Status: Pending
17---
18 gcc/config/microblaze/microblaze.c | 3 +--
19 1 file changed, 1 insertion(+), 2 deletions(-)
20
21diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
22index bba6983b65..15080db539 100644
23--- a/gcc/config/microblaze/microblaze.c
24+++ b/gcc/config/microblaze/microblaze.c
25@@ -3527,8 +3527,7 @@ microblaze_expand_divide (rtx operands[])
26 mem_rtx = gen_rtx_MEM (QImode,
27 gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
28
29- insn = emit_insn (gen_movqi (regqi, mem_rtx));
30- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
31+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
32 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
33 JUMP_LABEL (jump) = div_end_label;
34 LABEL_NUSES (div_end_label) = 1;
35--
362.14.2
37
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
new file mode 100644
index 00000000..6005e216
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch
@@ -0,0 +1,53 @@
1From c32df2ec3d269d19b631a17cea2b6d19bbb98c27 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:27 -0700
4Subject: [PATCH] Add MicroBlaze ashrsi_3_with_size_opt
5
6Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to
7optimize the sra instructions when the -Os optimization is used.
8lshrsi3_with_size_opt is being removed as it has conflicts with unsigned
9int variables
10
11Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
12Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
13Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
14Upstream-Status: Pending
15---
16 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
17 1 file changed, 21 insertions(+)
18
19diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
20index 59d629b559..8c0a97e032 100644
21--- a/gcc/config/microblaze/microblaze.md
22+++ b/gcc/config/microblaze/microblaze.md
23@@ -1505,6 +1505,27 @@
24 (set_attr "length" "4,4")]
25 )
26
27+(define_insn "*ashrsi3_with_size_opt"
28+ [(set (match_operand:SI 0 "register_operand" "=&d")
29+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
30+ (match_operand:SI 2 "immediate_operand" "I")))]
31+ "(INTVAL (operands[2]) > 5 && optimize_size)"
32+ {
33+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
34+
35+ output_asm_insn ("ori\t%3,r0,%2", operands);
36+ if (REGNO (operands[0]) != REGNO (operands[1]))
37+ output_asm_insn ("addk\t%0,%1,r0", operands);
38+
39+ output_asm_insn ("addik\t%3,%3,-1", operands);
40+ output_asm_insn ("bneid\t%3,.-4", operands);
41+ return "sra\t%0,%0";
42+ }
43+ [(set_attr "type" "arith")
44+ (set_attr "mode" "SI")
45+ (set_attr "length" "20")]
46+)
47+
48 (define_insn "*ashrsi_inline"
49 [(set (match_operand:SI 0 "register_operand" "=&d")
50 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
51--
522.14.2
53
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
new file mode 100644
index 00000000..b0195718
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch
@@ -0,0 +1,156 @@
1From a68e94fc57bcf60cb730894e49dde55d081397f5 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:28 -0700
4Subject: [PATCH] Removed MicroBlaze moddi3 routinue
5
6Removed moddi3 routinue Using the default moddi3 function as the
7existing implementation has many bugs
8
9Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
10Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
11Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
12Upstream-Status: Pending
13---
14 libgcc/config/microblaze/moddi3.S | 115 ----------------------------------
15 libgcc/config/microblaze/t-microblaze | 3 +-
16 2 files changed, 1 insertion(+), 117 deletions(-)
17 delete mode 100644 libgcc/config/microblaze/moddi3.S
18
19diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
20deleted file mode 100644
21index bcea079476..0000000000
22--- a/libgcc/config/microblaze/moddi3.S
23+++ /dev/null
24@@ -1,115 +0,0 @@
25-###################################
26-#
27-# Copyright (C) 2009-2017 Free Software Foundation, Inc.
28-#
29-# Contributed by Michael Eager <eager@eagercon.com>.
30-#
31-# This file is free software; you can redistribute it and/or modify it
32-# under the terms of the GNU General Public License as published by the
33-# Free Software Foundation; either version 3, or (at your option) any
34-# later version.
35-#
36-# GCC is distributed in the hope that it will be useful, but WITHOUT
37-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
38-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
39-# License for more details.
40-#
41-# Under Section 7 of GPL version 3, you are granted additional
42-# permissions described in the GCC Runtime Library Exception, version
43-# 3.1, as published by the Free Software Foundation.
44-#
45-# You should have received a copy of the GNU General Public License and
46-# a copy of the GCC Runtime Library Exception along with this program;
47-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
48-# <http://www.gnu.org/licenses/>.
49-#
50-# modsi3.S
51-#
52-# modulo operation for 64 bit integers.
53-#
54-#######################################
55-
56-
57- .globl __moddi3
58- .ent __moddi3
59-__moddi3:
60- .frame r1,0,r15
61-
62-#Change the stack pointer value and Save callee saved regs
63- addik r1,r1,-24
64- swi r25,r1,0
65- swi r26,r1,4
66- swi r27,r1,8 # used for sign
67- swi r28,r1,12 # used for loop count
68- swi r29,r1,16 # Used for div value High
69- swi r30,r1,20 # Used for div value Low
70-
71-#Check for Zero Value in the divisor/dividend
72- OR r9,r5,r6 # Check for the op1 being zero
73- BEQID r9,$LaResult_Is_Zero # Result is zero
74- OR r9,r7,r8 # Check for the dividend being zero
75- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
76- BGEId r5,$La1_Pos
77- XOR r27,r5,r7 # Get the sign of the result
78- RSUBI r6,r6,0 # Make dividend positive
79- RSUBIC r5,r5,0 # Make dividend positive
80-$La1_Pos:
81- BGEI r7,$La2_Pos
82- RSUBI r8,r8,0 # Make Divisor Positive
83- RSUBIC r9,r9,0 # Make Divisor Positive
84-$La2_Pos:
85- ADDIK r4,r0,0 # Clear mod low
86- ADDIK r3,r0,0 # Clear mod high
87- ADDIK r29,r0,0 # clear div high
88- ADDIK r30,r0,0 # clear div low
89- ADDIK r28,r0,64 # Initialize the loop count
90- # First part try to find the first '1' in the r5/r6
91-$LaDIV1:
92- ADD r6,r6,r6
93- ADDC r5,r5,r5 # left shift logical r5
94- BGEID r5,$LaDIV1
95- ADDIK r28,r28,-1
96-$LaDIV2:
97- ADD r6,r6,r6
98- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
99- ADDC r4,r4,r4 # Move that bit into the Mod register
100- ADDC r3,r3,r3 # Move carry into high mod register
101- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
102- bnei r18,$L_High_EQ
103- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
104-$L_High_EQ:
105- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
106- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
107- BLTi r25,$LaMOD_TOO_SMALL
108- OR r3,r0,r25 # move r25 to mod [h]
109- OR r4,r0,r26 # move r26 to mod [l]
110- ADDI r30,r30,1
111- ADDC r29,r29,r0
112-$LaMOD_TOO_SMALL:
113- ADDIK r28,r28,-1
114- BEQi r28,$LaLOOP_END
115- ADD r30,r30,r30 # Shift in the '1' into div [low]
116- ADDC r29,r29,r29 # Move the carry generated into high
117- BRI $LaDIV2 # Div2
118-$LaLOOP_END:
119- BGEI r27,$LaRETURN_HERE
120- rsubi r30,r30,0
121- rsubc r29,r29,r0
122- BRI $LaRETURN_HERE
123-$LaDiv_By_Zero:
124-$LaResult_Is_Zero:
125- or r29,r0,r0 # set result to 0 [High]
126- or r30,r0,r0 # set result to 0 [Low]
127-$LaRETURN_HERE:
128-# Restore values of CSRs and that of r29 and the divisor and the dividend
129-
130- lwi r25,r1,0
131- lwi r26,r1,4
132- lwi r27,r1,8
133- lwi r28,r1,12
134- lwi r29,r1,16
135- lwi r30,r1,20
136- rtsd r15,8
137- addik r1,r1,24
138- .end __moddi3
139-
140diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
141index 96959f0292..8d954a4957 100644
142--- a/libgcc/config/microblaze/t-microblaze
143+++ b/libgcc/config/microblaze/t-microblaze
144@@ -1,8 +1,7 @@
145-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
146+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
147
148 LIB2ADD += \
149 $(srcdir)/config/microblaze/divsi3.S \
150- $(srcdir)/config/microblaze/moddi3.S \
151 $(srcdir)/config/microblaze/modsi3.S \
152 $(srcdir)/config/microblaze/muldi3_hard.S \
153 $(srcdir)/config/microblaze/mulsi3.S \
154--
1552.14.2
156
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
new file mode 100644
index 00000000..e75bebeb
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch
@@ -0,0 +1,46 @@
1From 79ea36649467aea6045a49c7d016f8f9245efb8c Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:29 -0700
4Subject: [PATCH] MicroBlaze fixed missing save of r18 in fast_interrupt
5
6Fixed missing save of r18 in fast_interrupt. Register 18 is used as a
7clobber register, and must be stored when entering a fast_interrupt.
8Before this fix, register 18 was only saved if it was used directly in
9the interrupt function.
10
11However, if the fast_interrupt function called a function that used
12r18, the register would not be saved, and thus be mangled
13upon returning from the interrupt.
14
15Changelog
16
172014-02-27 Klaus Petersen <klauspetersen@gmail.com>
18
19 * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
20 microblaze_must_save_register.
21
22Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
23Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
24Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
25Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
26Upstream-Status: Pending
27---
28 gcc/config/microblaze/microblaze.c | 2 +-
29 1 file changed, 1 insertion(+), 1 deletion(-)
30
31diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
32index 15080db539..558796cad9 100644
33--- a/gcc/config/microblaze/microblaze.c
34+++ b/gcc/config/microblaze/microblaze.c
35@@ -1943,7 +1943,7 @@ microblaze_must_save_register (int regno)
36 {
37 if (df_regs_ever_live_p (regno)
38 || regno == MB_ABI_MSR_SAVE_REG
39- || (interrupt_handler
40+ || ((interrupt_handler || fast_interrupt)
41 && (regno == MB_ABI_ASM_TEMP_REGNUM
42 || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
43 return 1;
44--
452.14.2
46
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
new file mode 100644
index 00000000..f5de718e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch
@@ -0,0 +1,29 @@
1From 6ed57ee8219e5d09a294b329dd7c531a1868dc8a Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:31 -0700
4Subject: [PATCH] MicroBlaze use bralid for profiler calls
5
6Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
7Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
8Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
9Upstream-Status: Pending
10---
11 gcc/config/microblaze/microblaze.h | 2 +-
12 1 file changed, 1 insertion(+), 1 deletion(-)
13
14diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
15index ccd77e8b4d..0dd8b853e2 100644
16--- a/gcc/config/microblaze/microblaze.h
17+++ b/gcc/config/microblaze/microblaze.h
18@@ -519,7 +519,7 @@ typedef struct microblaze_args
19
20 #define FUNCTION_PROFILER(FILE, LABELNO) { \
21 { \
22- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
23+ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \
24 } \
25 }
26
27--
282.14.2
29
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
new file mode 100644
index 00000000..4041e11f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch
@@ -0,0 +1,38 @@
1From 25b161dd222311cca0e6ab46b7f3be444bd4bbe8 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:32 -0700
4Subject: [PATCH] Disable fivopts by default Turn off ivopts by default.
5 Interferes with cse.
6
7Changelog
8
92013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
11 * gcc/common/config/microblaze/microblaze-common.c
12 (microblaze_option_optimization_table): Disable fivopts by default.
13
14Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
15Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
16Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
17Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
18Upstream-Status: Pending
19---
20 gcc/common/config/microblaze/microblaze-common.c | 2 ++
21 1 file changed, 2 insertions(+)
22
23diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
24index 4975663305..8ddc4c3cbe 100644
25--- a/gcc/common/config/microblaze/microblaze-common.c
26+++ b/gcc/common/config/microblaze/microblaze-common.c
27@@ -27,6 +27,8 @@
28 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
29 static const struct default_options microblaze_option_optimization_table[] =
30 {
31+ /* Turn off ivopts by default. It messes up cse. */
32+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
33 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
34 { OPT_LEVELS_NONE, 0, NULL, 0 }
35 };
36--
372.14.2
38
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
new file mode 100644
index 00000000..5239d2bd
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
@@ -0,0 +1,104 @@
1From 02d8afd50a868e827ac8b6b6243c69922cd694ed Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:34 -0700
4Subject: [PATCH] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and
5 TARGET_ASM_DESTRUCTOR macros.
6
7These macros allows users to control the order of initialization
8of objects defined at namespace scope with the init_priority
9attribute by specifying a relative priority, a constant integral
10expression currently bounded between 101 and 65535 inclusive.
11
12Lower numbers indicate a higher priority.
13
14Changelog
15
162013-11-26 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
17
18 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
19 microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
20 TARGET_ASM_DESTRUCTOR.
21
22Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
23Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
24Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
25Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
26Upstream-Status: Pending
27---
28 gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++
29 1 file changed, 53 insertions(+)
30
31diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
32index 558796cad9..c1b0172bcf 100644
33--- a/gcc/config/microblaze/microblaze.c
34+++ b/gcc/config/microblaze/microblaze.c
35@@ -2530,6 +2530,53 @@ print_operand_address (FILE * file, rtx addr)
36 }
37 }
38
39+/* Output an element in the table of global constructors. */
40+void
41+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
42+{
43+ const char *section = ".ctors";
44+ char buf[16];
45+
46+ if (priority != DEFAULT_INIT_PRIORITY)
47+ {
48+ sprintf (buf, ".ctors.%.5u",
49+ /* Invert the numbering so the linker puts us in the proper
50+ order; constructors are run from right to left, and the
51+ linker sorts in increasing order. */
52+ MAX_INIT_PRIORITY - priority);
53+ section = buf;
54+ }
55+
56+ switch_to_section (get_section (section, 0, NULL));
57+ assemble_align (POINTER_SIZE);
58+ fputs ("\t.word\t", asm_out_file);
59+ output_addr_const (asm_out_file, symbol);
60+ fputs ("\n", asm_out_file);
61+}
62+
63+/* Output an element in the table of global destructors. */
64+void
65+microblaze_asm_destructor (rtx symbol, int priority)
66+{
67+ const char *section = ".dtors";
68+ char buf[16];
69+ if (priority != DEFAULT_INIT_PRIORITY)
70+ {
71+ sprintf (buf, ".dtors.%.5u",
72+ /* Invert the numbering so the linker puts us in the proper
73+ order; constructors are run from right to left, and the
74+ linker sorts in increasing order. */
75+ MAX_INIT_PRIORITY - priority);
76+ section = buf;
77+ }
78+
79+ switch_to_section (get_section (section, 0, NULL));
80+ assemble_align (POINTER_SIZE);
81+ fputs ("\t.word\t", asm_out_file);
82+ output_addr_const (asm_out_file, symbol);
83+ fputs ("\n", asm_out_file);
84+}
85+
86 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
87 is used, so that we don't emit an .extern for it in
88 microblaze_asm_file_end. */
89@@ -3775,6 +3822,12 @@ microblaze_machine_dependent_reorg (void)
90 #undef TARGET_ATTRIBUTE_TABLE
91 #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table
92
93+#undef TARGET_ASM_CONSTRUCTOR
94+#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor
95+
96+#undef TARGET_ASM_DESTRUCTOR
97+#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor
98+
99 #undef TARGET_IN_SMALL_DATA_P
100 #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p
101
102--
1032.14.2
104
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
new file mode 100644
index 00000000..049ce3fe
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch
@@ -0,0 +1,87 @@
1From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:35 -0700
4Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not
5 present
6
7Add optimized lshrsi3 When barrel shifter is not present, the immediate
8value is greater than #5 and optimization is -OS, the compiler will
9generate shift operation using loop.
10
11Changelog
12
132013-11-26 David Holsgrove <david.holsgrove@xilinx.com>
14
15 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
16
17ChangeLog/testsuite
18
192014-02-12 David Holsgrove <david.holsgrove@xilinx.com>
20
21 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
22
23Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
24Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
25Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
26Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
27Upstream-Status: Pending
28---
29 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
30 .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++
31 2 files changed, 34 insertions(+)
32 create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
33
34diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
35index 8c0a97e032..abbe97c15f 100644
36--- a/gcc/config/microblaze/microblaze.md
37+++ b/gcc/config/microblaze/microblaze.md
38@@ -1615,6 +1615,27 @@
39 (set_attr "length" "4,4")]
40 )
41
42+(define_insn "*lshrsi3_with_size_opt"
43+ [(set (match_operand:SI 0 "register_operand" "=&d")
44+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
45+ (match_operand:SI 2 "immediate_operand" "I")))]
46+ "(INTVAL (operands[2]) > 5 && optimize_size)"
47+ {
48+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
49+
50+ output_asm_insn ("ori\t%3,r0,%2", operands);
51+ if (REGNO (operands[0]) != REGNO (operands[1]))
52+ output_asm_insn ("addk\t%0,%1,r0", operands);
53+
54+ output_asm_insn ("addik\t%3,%3,-1", operands);
55+ output_asm_insn ("bneid\t%3,.-4", operands);
56+ return "srl\t%0,%0";
57+ }
58+ [(set_attr "type" "multi")
59+ (set_attr "mode" "SI")
60+ (set_attr "length" "20")]
61+)
62+
63 (define_insn "*lshrsi_inline"
64 [(set (match_operand:SI 0 "register_operand" "=&d")
65 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
66diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
67new file mode 100644
68index 0000000000..32a3be7c76
69--- /dev/null
70+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
71@@ -0,0 +1,13 @@
72+/* { dg-options "-Os -mno-xl-barrel-shift" } */
73+
74+void testfunc(void)
75+{
76+ unsigned volatile int z = 8192;
77+ z >>= 8;
78+}
79+/* { dg-final { scan-assembler-not "\bsrli" } } */
80+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
81+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
82+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
83+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
84+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
85--
862.14.2
87
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
new file mode 100644
index 00000000..00e79b93
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch
@@ -0,0 +1,33 @@
1From 1b9bd76840fc1e67770a23c58bf18a24a25eb2b9 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:36 -0700
4Subject: [PATCH] Modified MicroBlaze trap instruction
5
6Modified trap instruction The instruction was wrongly written to brki
7r0,-1 it should be bri r0. Modified with the correct instruction
8
9Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
10Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
11Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
12Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
13Upstream-Status: Pending
14---
15 gcc/config/microblaze/microblaze.md | 2 +-
16 1 file changed, 1 insertion(+), 1 deletion(-)
17
18diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
19index abbe97c15f..a3954a24b6 100644
20--- a/gcc/config/microblaze/microblaze.md
21+++ b/gcc/config/microblaze/microblaze.md
22@@ -2343,7 +2343,7 @@
23 (define_insn "trap"
24 [(trap_if (const_int 1) (const_int 0))]
25 ""
26- "brki\tr0,-1"
27+ "bri\t0"
28 [(set_attr "type" "trap")]
29 )
30
31--
322.14.2
33
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
new file mode 100644
index 00000000..ead929ab
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch
@@ -0,0 +1,212 @@
1From f5416ee7ddc6e4853e57ed15fb2bf630de2c3b12 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:37 -0700
4Subject: [PATCH] Reducing Stack space for arguments Currently in Microblaze
5 target stack space
6
7Reducing Stack space for arguments Currently in Microblaze target stack
8space for arguments in register is being allocated even if there are no
9arguments in the function. This patch will optimize the extra 24 bytes
10that are being allocated.
11
12ChangeLog:
132015-04-17 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 * microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
17 * microblaze.c (REG_PARM_STACK_SPACE): Modify
18
19Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
20Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
21Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
22Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
23Upstream-Status: Pending
24---
25 gcc/config/microblaze/microblaze-protos.h | 1 +
26 gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++-
27 gcc/config/microblaze/microblaze.h | 4 +-
28 3 files changed, 136 insertions(+), 3 deletions(-)
29
30diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
31index b56e052ae4..a1408629cc 100644
32--- a/gcc/config/microblaze/microblaze-protos.h
33+++ b/gcc/config/microblaze/microblaze-protos.h
34@@ -57,6 +57,7 @@ extern int symbol_mentioned_p (rtx);
35 extern int label_mentioned_p (rtx);
36 extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
37 extern void microblaze_eh_return (rtx op0);
38+int microblaze_reg_parm_stack_space(tree fun);
39 #endif /* RTX_CODE */
40
41 /* Declare functions in microblaze-c.c. */
42diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
43index c1b0172bcf..f46dffff0d 100644
44--- a/gcc/config/microblaze/microblaze.c
45+++ b/gcc/config/microblaze/microblaze.c
46@@ -1965,6 +1965,138 @@ microblaze_must_save_register (int regno)
47 return 0;
48 }
49
50+static bool
51+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
52+{
53+ enum machine_mode mode;
54+ int unsignedp;
55+ rtx entry_parm;
56+
57+ /* Catch errors. */
58+ if (type == NULL || type == error_mark_node)
59+ return true;
60+
61+ if (TREE_CODE (type) == POINTER_TYPE)
62+ return true;
63+
64+ /* Handle types with no storage requirement. */
65+ if (TYPE_MODE (type) == VOIDmode)
66+ return false;
67+
68+ /* Handle complex types. */
69+ if (TREE_CODE (type) == COMPLEX_TYPE)
70+ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
71+ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
72+
73+ /* Handle transparent aggregates. */
74+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
75+ && TYPE_TRANSPARENT_AGGR (type))
76+ type = TREE_TYPE (first_field (type));
77+
78+ /* See if this arg was passed by invisible reference. */
79+ if (pass_by_reference (get_cumulative_args (args_so_far),
80+ TYPE_MODE (type), type, true))
81+ type = build_pointer_type (type);
82+
83+ /* Find mode as it is passed by the ABI. */
84+ unsignedp = TYPE_UNSIGNED (type);
85+ mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
86+
87+/* If there is no incoming register, we need a stack. */
88+ entry_parm = microblaze_function_arg (args_so_far, mode, type, true);
89+ if (entry_parm == NULL)
90+ return true;
91+
92+ /* Likewise if we need to pass both in registers and on the stack. */
93+ if (GET_CODE (entry_parm) == PARALLEL
94+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
95+ return true;
96+
97+ /* Also true if we're partially in registers and partially not. */
98+ if (function_arg_partial_bytes (args_so_far, mode, type, true) != 0)
99+ return true;
100+
101+ /* Update info on where next arg arrives in registers. */
102+ microblaze_function_arg_advance (args_so_far, mode, type, true);
103+ return false;
104+ }
105+
106+static bool
107+microblaze_function_parms_need_stack (tree fun, bool incoming)
108+{
109+ tree fntype, result;
110+ CUMULATIVE_ARGS args_so_far_v;
111+ cumulative_args_t args_so_far;
112+ int num_of_args = 0;
113+
114+ /* Must be a libcall, all of which only use reg parms. */
115+ if (!fun)
116+ return true;
117+
118+ fntype = fun;
119+ if (!TYPE_P (fun))
120+ fntype = TREE_TYPE (fun);
121+
122+ /* Varargs functions need the parameter save area. */
123+ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
124+ return true;
125+
126+ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
127+ args_so_far = pack_cumulative_args (&args_so_far_v);
128+
129+ /* When incoming, we will have been passed the function decl.
130+ * It is necessary to use the decl to handle K&R style functions,
131+ * where TYPE_ARG_TYPES may not be available. */
132+ if (incoming)
133+ {
134+ gcc_assert (DECL_P (fun));
135+ result = DECL_RESULT (fun);
136+ }
137+ else
138+ result = TREE_TYPE (fntype);
139+
140+ if (result && aggregate_value_p (result, fntype))
141+ {
142+ if (!TYPE_P (result))
143+ result = build_pointer_type (result);
144+ microblaze_parm_needs_stack (args_so_far, result);
145+ }
146+
147+ if (incoming)
148+ {
149+ tree parm;
150+ for (parm = DECL_ARGUMENTS (fun);
151+ parm && parm != void_list_node;
152+ parm = TREE_CHAIN (parm))
153+ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
154+ return true;
155+ }
156+ else
157+ {
158+ function_args_iterator args_iter;
159+ tree arg_type;
160+
161+ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
162+ {
163+ num_of_args++;
164+ if (microblaze_parm_needs_stack (args_so_far, arg_type))
165+ return true;
166+ }
167+ }
168+
169+ if (num_of_args > 3) return true;
170+
171+ return false;
172+}
173+
174+int microblaze_reg_parm_stack_space(tree fun)
175+{
176+ if (microblaze_function_parms_need_stack (fun,false))
177+ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
178+ else
179+ return 0;
180+}
181+
182 /* Return the bytes needed to compute the frame pointer from the current
183 stack pointer.
184
185@@ -3275,7 +3407,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
186 emit_insn (gen_indirect_jump (temp2));
187
188 /* Run just enough of rest_of_compilation. This sequence was
189- "borrowed" from rs6000.c. */
190+ "borrowed" from microblaze.c. */
191 insn = get_insns ();
192 shorten_branches (insn);
193 final_start_function (insn, file, 1);
194diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
195index 0dd8b853e2..82e7e890be 100644
196--- a/gcc/config/microblaze/microblaze.h
197+++ b/gcc/config/microblaze/microblaze.h
198@@ -467,9 +467,9 @@ extern struct microblaze_frame_info current_frame_info;
199
200 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
201
202-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
203+#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
204
205-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
206+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
207
208 #define STACK_BOUNDARY 32
209
210--
2112.14.2
212
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 00000000..6de17024
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,64 @@
1From cf85f09a0fade1e7827828a3dc9a526c212f3be7 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:39 -0700
4Subject: [PATCH] Inline Expansion of fsqrt builtin
5
6Inline Expansion of fsqrt builtin. The changes are made in the patch for
7the inline expansion of the fsqrt builtin with fqrt instruction. The
8sqrt math function takes double as argument and return double as
9argument. The pattern is selected while expanding the unary op through
10expand_unop which passes DFmode and the DFmode pattern was not there
11returning zero. Thus the sqrt math function is not inlined and expanded.
12The pattern with DFmode argument is added. Also the source and
13destination argument is not same the DF through two different
14consecutive registers with lower 32 bit is the argument passed to sqrt
15and the higher 32 bit is zero. If the source and destinations are
16different the DFmode 64 bits registers is not set properly giving the
17problem in runtime. Such changes are taken care in the implementation of
18the pattern for DFmode for inline expansion of the sqrt.
19
20ChangeLog:
21
222015-06-16 Ajit Agarwal <ajitkum@xilinx.com>
23 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
24
25 * config/microblaze/microblaze.md (sqrtdf2): New
26 pattern.
27
28Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
29Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
30Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
31Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
32Upstream-Status: Pending
33---
34 gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
35 1 file changed, 14 insertions(+)
36
37diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
38index a3954a24b6..13f8803428 100644
39--- a/gcc/config/microblaze/microblaze.md
40+++ b/gcc/config/microblaze/microblaze.md
41@@ -449,6 +449,20 @@
42 (set_attr "mode" "SF")
43 (set_attr "length" "4")])
44
45+(define_insn "sqrtdf2"
46+ [(set (match_operand:DF 0 "register_operand" "=d")
47+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
48+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
49+ {
50+ if (REGNO (operands[0]) == REGNO (operands[1]))
51+ return "fsqrt\t%0,%1";
52+ else
53+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
54+ }
55+ [(set_attr "type" "fsqrt")
56+ (set_attr "mode" "SF")
57+ (set_attr "length" "4")])
58+
59 (define_insn "fix_truncsfsi2"
60 [(set (match_operand:SI 0 "register_operand" "=d")
61 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
62--
632.14.2
64
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
new file mode 100644
index 00000000..d8eb7695
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,78 @@
1From f269f552e1abf182dc3749e0f29b1529fc82644a Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:42 -0700
4Subject: [PATCH] Update MicroBlaze ashlsi3 & movsf patterns
5
6This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in
7print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and
8movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating
964-bit value which our instruction doesn't support so using gen_int_mode
10function
11
12ChangeLog:
13
142016-01-07 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
15 Ajit Agarwal <ajitkum@xilinx.com>
16
17 * microblaze.md (ashlsi3_with_mul_nodelay,
18 ashlsi3_with_mul_delay,
19 movsf_internal):
20 Updated the patterns to use gen_int_mode function
21 * microblaze.c (print_operand):
22 updated the 'F' case to use "unsinged int" instead
23 of HOST_WIDE_INT_PRINT_HEX
24
25Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
26Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
27Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
28Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
29Upstream-Status: Pending
30---
31 gcc/config/microblaze/microblaze.c | 2 +-
32 gcc/config/microblaze/microblaze.md | 10 ++++++++--
33 2 files changed, 9 insertions(+), 3 deletions(-)
34
35diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
36index f46dffff0d..663b20a022 100644
37--- a/gcc/config/microblaze/microblaze.c
38+++ b/gcc/config/microblaze/microblaze.c
39@@ -2507,7 +2507,7 @@ print_operand (FILE * file, rtx op, int letter)
40 unsigned long value_long;
41 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
42 value_long);
43- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
44+ fprintf (file, "0x%08x", (unsigned int) value_long);
45 }
46 else
47 {
48diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
49index 13f8803428..b9c62b6d0f 100644
50--- a/gcc/config/microblaze/microblaze.md
51+++ b/gcc/config/microblaze/microblaze.md
52@@ -1366,7 +1366,10 @@
53 (match_operand:SI 2 "immediate_operand" "I")))]
54 "!TARGET_SOFT_MUL
55 && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
56- "muli\t%0,%1,%m2"
57+ {
58+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
59+ return "muli\t%0,%1,%2";
60+ }
61 ;; This MUL will not generate an imm. Can go into a delay slot.
62 [(set_attr "type" "arith")
63 (set_attr "mode" "SI")
64@@ -1378,7 +1381,10 @@
65 (ashift:SI (match_operand:SI 1 "register_operand" "d")
66 (match_operand:SI 2 "immediate_operand" "I")))]
67 "!TARGET_SOFT_MUL"
68- "muli\t%0,%1,%m2"
69+ {
70+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
71+ return "muli\t%0,%1,%2";
72+ }
73 ;; This MUL will generate an IMM. Cannot go into a delay slot
74 [(set_attr "type" "no_delay_arith")
75 (set_attr "mode" "SI")
76--
772.14.2
78
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 00000000..6faa6251
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,195 @@
1From 17353cc4ba521f5ad928a1ede61cf03110e366ae Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:43 -0700
4Subject: [PATCH] 8-stage pipeline for microblaze
5
6This patch adds the support for the 8-stage pipeline. The new 8-stage
7pipeline reduces the latencies of float & integer division drastically
8
9ChangeLog:
10
112016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
12
13 * microblaze.md (define_automaton mbpipe_8): New
14 * microblaze.c (microblaze_option_override): Update
15 Updated the logic to generate only when MB version is 10.0
16 * microblaze.h (pipeline_type): Update
17 Update the enum with MICROBLAZE_PIPE_8
18 * microblaze.opt (mxl-frequency): New
19 New flag added for 8-stage pipeline
20
21Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
22Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
23Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
24Upstream-Status: Pending
25---
26 gcc/config/microblaze/microblaze.c | 13 ++++++
27 gcc/config/microblaze/microblaze.h | 3 +-
28 gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++++++++++-
29 gcc/config/microblaze/microblaze.opt | 4 ++
30 4 files changed, 96 insertions(+), 3 deletions(-)
31
32diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
33index 663b20a022..e7697bf30d 100644
34--- a/gcc/config/microblaze/microblaze.c
35+++ b/gcc/config/microblaze/microblaze.c
36@@ -1773,6 +1773,19 @@ microblaze_option_override (void)
37 warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a");
38 TARGET_REORDER = 0;
39 }
40+ ver = ver_int - microblaze_version_to_int("v10.0");
41+ if (ver < 0)
42+ {
43+ if (TARGET_AREA_OPTIMIZED_2)
44+ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
45+ }
46+ else
47+ {
48+ if (TARGET_AREA_OPTIMIZED_2)
49+ microblaze_pipe = MICROBLAZE_PIPE_8;
50+ if (TARGET_BARREL_SHIFT)
51+ microblaze_has_bitfield = 1;
52+ }
53
54 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
55 error ("-mxl-multiply-high requires -mno-xl-soft-mul");
56diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
57index 82e7e890be..3f48e48f10 100644
58--- a/gcc/config/microblaze/microblaze.h
59+++ b/gcc/config/microblaze/microblaze.h
60@@ -27,7 +27,8 @@
61 enum pipeline_type
62 {
63 MICROBLAZE_PIPE_3 = 0,
64- MICROBLAZE_PIPE_5 = 1
65+ MICROBLAZE_PIPE_5 = 1,
66+ MICROBLAZE_PIPE_8 = 2
67 };
68
69 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
70diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
71index b9c62b6d0f..61d6412dac 100644
72--- a/gcc/config/microblaze/microblaze.md
73+++ b/gcc/config/microblaze/microblaze.md
74@@ -35,6 +35,7 @@
75 (R_GOT 20) ;; GOT ptr reg
76 (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline
77 (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline
78+ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline
79 (UNSPEC_SET_GOT 101) ;;
80 (UNSPEC_GOTOFF 102) ;; GOT offset
81 (UNSPEC_PLT 103) ;; jump table
82@@ -80,7 +81,7 @@
83 ;; bshift Shift operations
84
85 (define_attr "type"
86- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
87+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
88 (const_string "unknown"))
89
90 ;; Main data type used by the insn
91@@ -222,6 +223,80 @@
92 ;;-----------------------------------------------------------------
93
94
95+
96+;;----------------------------------------------------------------
97+;; Microblaze 8-stage pipeline description (v10.0 and later)
98+;;----------------------------------------------------------------
99+
100+(define_automaton "mbpipe_8")
101+(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
102+
103+(define_insn_reservation "mb8-integer" 1
104+ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
105+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
106+ "mb8_issue,mb8_iu,mb8_wb")
107+
108+(define_insn_reservation "mb8-special-move" 2
109+ (and (eq_attr "type" "move")
110+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
111+ "mb8_issue,mb8_iu*2,mb8_wb")
112+
113+(define_insn_reservation "mb8-mem-load" 3
114+ (and (eq_attr "type" "load,no_delay_load")
115+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
116+ "mb8_issue,mb8_iu,mb8_wb")
117+
118+(define_insn_reservation "mb8-mem-store" 1
119+ (and (eq_attr "type" "store,no_delay_store")
120+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
121+ "mb8_issue,mb8_iu,mb8_wb")
122+
123+(define_insn_reservation "mb8-mul" 3
124+ (and (eq_attr "type" "imul,no_delay_imul")
125+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
126+ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
127+
128+(define_insn_reservation "mb8-div" 30
129+ (and (eq_attr "type" "idiv")
130+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
131+ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
132+
133+(define_insn_reservation "mb8-bs" 2
134+ (and (eq_attr "type" "bshift")
135+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
136+ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
137+
138+(define_insn_reservation "mb8-fpu-add-sub-mul" 1
139+ (and (eq_attr "type" "fadd,frsub,fmul")
140+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
141+ "mb8_issue,mb8_fpu,mb8_wb")
142+
143+(define_insn_reservation "mb8-fpu-fcmp" 3
144+ (and (eq_attr "type" "fcmp")
145+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
146+ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
147+
148+(define_insn_reservation "mb8-fpu-div" 24
149+ (and (eq_attr "type" "fdiv")
150+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
151+ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
152+
153+(define_insn_reservation "mb8-fpu-sqrt" 23
154+ (and (eq_attr "type" "fsqrt")
155+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
156+ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
157+
158+(define_insn_reservation "mb8-fpu-fcvt" 1
159+ (and (eq_attr "type" "fcvt")
160+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
161+ "mb8_issue,mb8_fpu,mb8_wb")
162+
163+(define_insn_reservation "mb8-fpu-fint" 2
164+ (and (eq_attr "type" "fint")
165+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
166+ "mb8_issue,mb8_fpu,mb8_wb")
167+
168+
169 ;;----------------------------------------------------------------
170 ;; Microblaze 5-stage pipeline description (v5.00.a and later)
171 ;;----------------------------------------------------------------
172@@ -468,7 +543,7 @@
173 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
174 "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
175 "fint\t%0,%1"
176- [(set_attr "type" "fcvt")
177+ [(set_attr "type" "fint")
178 (set_attr "mode" "SF")
179 (set_attr "length" "4")])
180
181diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
182index 8847c3daf8..85a9929d74 100644
183--- a/gcc/config/microblaze/microblaze.opt
184+++ b/gcc/config/microblaze/microblaze.opt
185@@ -129,3 +129,7 @@ Use hardware prefetch instruction
186
187 mxl-mode-xilkernel
188 Target
189+
190+mxl-frequency
191+Target Mask(AREA_OPTIMIZED_2)
192+Use 8 stage pipeline (frequency optimization)
193--
1942.14.2
195
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
new file mode 100644
index 00000000..ff8e6107
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch
@@ -0,0 +1,72 @@
1From fabd23a354496701b4a9ebf6931485b0d61c7bbe Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:45 -0700
4Subject: [PATCH] MicroBlaze correct the const high double immediate value
5
6With this patch the loading of the DI mode immediate values will be
7using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
8functions, as CONST_DOUBLE_HIGH was returning the sign extension value
9even of the unsigned long long constants also
10
11ChangeLog:
12
132016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 * microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
17 REAL_VALUE_TO_TARGET_DOUBLE
18 * long.c (new): Added new testcase
19
20Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
21Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
22Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
23Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
24Upstream-Status: Pending
25---
26 gcc/config/microblaze/microblaze.c | 6 ++++--
27 gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
28 2 files changed, 14 insertions(+), 2 deletions(-)
29 create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
30
31diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
32index e7697bf30d..96bf6e1cab 100644
33--- a/gcc/config/microblaze/microblaze.c
34+++ b/gcc/config/microblaze/microblaze.c
35@@ -2493,14 +2493,16 @@ print_operand (FILE * file, rtx op, int letter)
36 else if (letter == 'h' || letter == 'j')
37 {
38 long val[2];
39+ long l[2];
40 if (code == CONST_DOUBLE)
41 {
42 if (GET_MODE (op) == DFmode)
43 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
44 else
45 {
46- val[0] = CONST_DOUBLE_HIGH (op);
47- val[1] = CONST_DOUBLE_LOW (op);
48+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
49+ val[1] = l[WORDS_BIG_ENDIAN == 0];
50+ val[0] = l[WORDS_BIG_ENDIAN != 0];
51 }
52 }
53 else if (code == CONST_INT)
54diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
55new file mode 100644
56index 0000000000..4d4518619d
57--- /dev/null
58+++ b/gcc/testsuite/gcc.target/microblaze/long.c
59@@ -0,0 +1,10 @@
60+/* { dg-options "-O0" } */
61+#define BASEADDR 0xF0000000ULL
62+int main ()
63+{
64+ unsigned long long start;
65+ start = (unsigned long long) BASEADDR;
66+ return 0;
67+}
68+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
69+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
70--
712.14.2
72
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
new file mode 100644
index 00000000..7ea28ee8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch
@@ -0,0 +1,42 @@
1From 2149d85f1f7375dd97bf961b2bdb693d6d931c13 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:46 -0700
4Subject: [PATCH] Fix internal compiler error with msmall-divides
5
6This patch will fix the internal error microblaze_expand_divide function
7which comes because of rtx PLUS where the mem_rtx is of type SI and the
8operand is of type QImode. This patch modifies the mem_rtx as QImode and
9Plus as QImode to fix the error.
10
11ChangeLog:
12
132016-02-23 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
14 Ajit Agarwal <ajitkum@xilinx.com>
15
16 * microblaze.c (microblaze_expand_divide): Update
17
18Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
19Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
20Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
21Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
22Upstream-Status: Pending
23---
24 gcc/config/microblaze/microblaze.c | 2 +-
25 1 file changed, 1 insertion(+), 1 deletion(-)
26
27diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
28index 96bf6e1cab..a41121264e 100644
29--- a/gcc/config/microblaze/microblaze.c
30+++ b/gcc/config/microblaze/microblaze.c
31@@ -3719,7 +3719,7 @@ microblaze_expand_divide (rtx operands[])
32 emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
33 emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
34 mem_rtx = gen_rtx_MEM (QImode,
35- gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
36+ gen_rtx_PLUS (QImode, regt1, div_table_rtx));
37
38 insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
39 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
40--
412.14.2
42
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
new file mode 100644
index 00000000..97422aea
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
@@ -0,0 +1,48 @@
1From 34049c9fcaa256befad032cbcd8aa74beecf13dc Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:47 -0700
4Subject: [PATCH] Fix the calculation of high word in a long long 64-bit
5
6This patch will change the calculation of high word in a long long 64-bit.
7Earlier to this patch the high word of long long word (0xF0000000ULL) is
8coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
9should be 0x00000000 and the low word should be 0xF0000000. This patch
10removes the condition of checking high word = 0 & low word < 0.
11This check is not required for the correctness of calculating 32-bit high
12and low words in a 64-bit long long.
13
14ChangeLog:
15
162016-03-01 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
17 Ajit Agarwal <ajitkum@xilinx.com>
18
19 * config/microblaze/microblaze.c (print_operand): Remove the
20 condition of checking high word = 0 & low word < 0.
21 * testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
22
23Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
24Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
25Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
26Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
27Upstream-Status: Pending
28---
29 gcc/config/microblaze/microblaze.c | 3 ---
30 1 file changed, 3 deletions(-)
31
32diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
33index a41121264e..2ed64971fb 100644
34--- a/gcc/config/microblaze/microblaze.c
35+++ b/gcc/config/microblaze/microblaze.c
36@@ -2509,9 +2509,6 @@ print_operand (FILE * file, rtx op, int letter)
37 {
38 val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
39 val[1] = INTVAL (op) & 0x00000000ffffffffLL;
40- if (val[0] == 0 && val[1] < 0)
41- val[0] = -1;
42-
43 }
44 fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
45 }
46--
472.14.2
48
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
new file mode 100644
index 00000000..02940e2f
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch
@@ -0,0 +1,126 @@
1From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:48 -0700
4Subject: [PATCH] Add new bit-field instructions
5
6This patches adds new bsefi and bsifi instructions. BSEFI- The
7instruction shall extract a bit field from a register and place it
8right-adjusted in the destination register. The other bits in the
9destination register shall be set to zero BSIFI- The instruction shall
10insert a right-adjusted bit field from a register at another position in
11the destination register. The rest of the bits in the destination
12register shall be unchanged
13
14ChangeLog:
15
162016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
17
18 * microblaze.md (Update): Added new patterns
19
20Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
21Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
22Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
23Upstream-Status: Pending
24---
25 gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++
26 1 file changed, 73 insertions(+)
27
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index 61d6412dac..7a00629922 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -980,6 +980,8 @@
33 (set_attr "mode" "DI")
34 (set_attr "length" "20,20,20")])
35
36+
37+
38 ;;----------------------------------------------------------------
39 ;; Data movement
40 ;;----------------------------------------------------------------
41@@ -1774,6 +1776,7 @@
42 (set_attr "length" "28")]
43 )
44
45+
46 ;;----------------------------------------------------------------
47 ;; Setting a register from an integer comparison.
48 ;;----------------------------------------------------------------
49@@ -2473,4 +2476,74 @@
50 DONE;
51 }")
52
53+(define_expand "extvsi"
54+ [(set (match_operand:SI 0 "register_operand" "r")
55+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
56+ (match_operand:SI 2 "immediate_operand" "I")
57+ (match_operand:SI 3 "immediate_operand" "I")))]
58+"TARGET_HAS_BITFIELD"
59+"
60+{
61+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
62+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
63+
64+ if ((len == 0) || (pos + len > 32) )
65+ FAIL;
66+
67+ ;;if (!register_operand (operands[1], VOIDmode))
68+ ;; FAIL;
69+ if (operands[0] == operands[1])
70+ FAIL;
71+ if (GET_CODE (operands[1]) == ASHIFT)
72+ FAIL;
73+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
74+ emit_insn (gen_extv_32 (operands[0], operands[1],
75+ operands[2], operands[3]));
76+ DONE;
77+}")
78+
79+(define_insn "extv_32"
80+ [(set (match_operand:SI 0 "register_operand" "=r")
81+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
82+ (match_operand:SI 2 "immediate_operand" "I")
83+ (match_operand:SI 3 "immediate_operand" "I")))]
84+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
85+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
86+ "bsefi %0,%1,%2,%3"
87+ [(set_attr "type" "bshift")
88+ (set_attr "length" "4")])
89+
90+(define_expand "insvsi"
91+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
92+ (match_operand:SI 1 "immediate_operand" "I")
93+ (match_operand:SI 2 "immediate_operand" "I"))
94+ (match_operand:SI 3 "register_operand" "r"))]
95+ "TARGET_HAS_BITFIELD"
96+ "
97+{
98+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
99+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
100+
101+ if (len <= 0 || pos + len > 32)
102+ FAIL;
103+
104+ ;;if (!register_operand (operands[0], VOIDmode))
105+ ;; FAIL;
106+
107+ emit_insn (gen_insv_32 (operands[0], operands[1],
108+ operands[2], operands[3]));
109+ DONE;
110+}")
111+
112+(define_insn "insv_32"
113+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
114+ (match_operand:SI 1 "immediate_operand" "I")
115+ (match_operand:SI 2 "immediate_operand" "I"))
116+ (match_operand:SI 3 "register_operand" "r"))]
117+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
118+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
119+ "bsifi %0, %3, %1, %2"
120+ [(set_attr "type" "bshift")
121+ (set_attr "length" "4")])
122+
123 (include "sync.md")
124--
1252.14.2
126
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 00000000..c3e4bc9e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,250 @@
1From 3eada9d81437d378ef24f11a8bd046fee5b3505a Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:49 -0700
4Subject: [PATCH] Fix bug in MB version calculation
5
6This patch fixes the bug in microblaze_version_to_int function. Earlier
7the conversion of vXX.YY.Z to int has a bug which is fixed now.
8
9Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
10Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
11Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
12Upstream-Status: Pending
13---
14 gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++-------------------
15 1 file changed, 70 insertions(+), 77 deletions(-)
16
17diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
18index 2ed64971fb..55dba83882 100644
19--- a/gcc/config/microblaze/microblaze.c
20+++ b/gcc/config/microblaze/microblaze.c
21@@ -239,6 +239,63 @@ section *sdata2_section;
22 #define TARGET_HAVE_TLS true
23 #endif
24
25+/* Convert a version number of the form "vX.YY.Z" to an integer encoding
26+ for easier range comparison. */
27+static int
28+microblaze_version_to_int (const char *version)
29+{
30+ const char *p, *v;
31+ const char *tmpl = "vXX.YY.Z";
32+ int iver1 =0, iver2 =0, iver3 =0;
33+
34+ p = version;
35+ v = tmpl;
36+
37+ while (*p)
38+ {
39+ if (*v == 'X')
40+ { /* Looking for major */
41+ if (*p == '.')
42+ {
43+ *v++;
44+ }
45+ else
46+ {
47+ if (!(*p >= '0' && *p <= '9'))
48+ return -1;
49+ iver1 += (int) (*p - '0');
50+ iver1 *= 1000;
51+ }
52+ }
53+ else if (*v == 'Y')
54+ { /* Looking for minor */
55+ if (!(*p >= '0' && *p <= '9'))
56+ return -1;
57+ iver2 += (int) (*p - '0');
58+ iver2 *= 10;
59+ }
60+ else if (*v == 'Z')
61+ { /* Looking for compat */
62+ if (!(*p >= 'a' && *p <= 'z'))
63+ return -1;
64+ iver3 = ((int) (*p)) - 96;
65+ }
66+ else
67+ {
68+ if (*p != *v)
69+ return -1;
70+ }
71+
72+ v++;
73+ p++;
74+ }
75+
76+ if (*p)
77+ return -1;
78+
79+ return iver1 + iver2 + iver3;
80+}
81+
82 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
83 static bool
84 microblaze_const_double_ok (rtx op, machine_mode mode)
85@@ -1267,8 +1324,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
86 {
87 if (TARGET_BARREL_SHIFT)
88 {
89- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
90- >= 0)
91+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
92 *total = COSTS_N_INSNS (1);
93 else
94 *total = COSTS_N_INSNS (2);
95@@ -1329,8 +1385,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
96 }
97 else if (!TARGET_SOFT_MUL)
98 {
99- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
100- >= 0)
101+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
102 *total = COSTS_N_INSNS (1);
103 else
104 *total = COSTS_N_INSNS (3);
105@@ -1610,72 +1665,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
106 return 0;
107 }
108
109-/* Convert a version number of the form "vX.YY.Z" to an integer encoding
110- for easier range comparison. */
111-static int
112-microblaze_version_to_int (const char *version)
113-{
114- const char *p, *v;
115- const char *tmpl = "vXX.YY.Z";
116- int iver = 0;
117-
118- p = version;
119- v = tmpl;
120-
121- while (*p)
122- {
123- if (*v == 'X')
124- { /* Looking for major */
125- if (*p == '.')
126- {
127- v++;
128- }
129- else
130- {
131- if (!(*p >= '0' && *p <= '9'))
132- return -1;
133- iver += (int) (*p - '0');
134- iver *= 10;
135- }
136- }
137- else if (*v == 'Y')
138- { /* Looking for minor */
139- if (!(*p >= '0' && *p <= '9'))
140- return -1;
141- iver += (int) (*p - '0');
142- iver *= 10;
143- }
144- else if (*v == 'Z')
145- { /* Looking for compat */
146- if (!(*p >= 'a' && *p <= 'z'))
147- return -1;
148- iver *= 10;
149- iver += (int) (*p - 'a');
150- }
151- else
152- {
153- if (*p != *v)
154- return -1;
155- }
156-
157- v++;
158- p++;
159- }
160-
161- if (*p)
162- return -1;
163-
164- return iver;
165-}
166-
167-
168 static void
169 microblaze_option_override (void)
170 {
171 register int i, start;
172 register int regno;
173 register machine_mode mode;
174- int ver;
175+ int ver,ver_int;
176
177 microblaze_section_threshold = (global_options_set.x_g_switch_value
178 ? g_switch_value
179@@ -1696,13 +1692,13 @@ microblaze_option_override (void)
180 /* Check the MicroBlaze CPU version for any special action to be done. */
181 if (microblaze_select_cpu == NULL)
182 microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
183- ver = microblaze_version_to_int (microblaze_select_cpu);
184- if (ver == -1)
185+ ver_int = microblaze_version_to_int (microblaze_select_cpu);
186+ if (ver_int == -1)
187 {
188 error ("%qs is an invalid argument to -mcpu=", microblaze_select_cpu);
189 }
190
191- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
192+ ver = ver_int - microblaze_version_to_int("v3.00.a");
193 if (ver < 0)
194 {
195 /* No hardware exceptions in earlier versions. So no worries. */
196@@ -1713,8 +1709,7 @@ microblaze_option_override (void)
197 microblaze_pipe = MICROBLAZE_PIPE_3;
198 }
199 else if (ver == 0
200- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
201- == 0))
202+ || (ver_int == microblaze_version_to_int("v4.00.b")))
203 {
204 #if 0
205 microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
206@@ -1731,11 +1726,9 @@ microblaze_option_override (void)
207 #endif
208 microblaze_no_unsafe_delay = 0;
209 microblaze_pipe = MICROBLAZE_PIPE_5;
210- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
211- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
212- "v5.00.b") == 0
213- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
214- "v5.00.c") == 0)
215+ if ((ver_int == microblaze_version_to_int("v5.00.a"))
216+ || (ver_int == microblaze_version_to_int("v5.00.b"))
217+ || (ver_int == microblaze_version_to_int("v5.00.c")))
218 {
219 /* Pattern compares are to be turned on by default only when
220 compiling for MB v5.00.'z'. */
221@@ -1743,7 +1736,7 @@ microblaze_option_override (void)
222 }
223 }
224
225- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
226+ ver = ver_int - microblaze_version_to_int("v6.00.a");
227 if (ver < 0)
228 {
229 if (TARGET_MULTIPLY_HIGH)
230@@ -1751,7 +1744,7 @@ microblaze_option_override (void)
231 "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater");
232 }
233
234- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
235+ ver = ver_int - microblaze_version_to_int("v8.10.a");
236 microblaze_has_clz = 1;
237 if (ver < 0)
238 {
239@@ -1760,7 +1753,7 @@ microblaze_option_override (void)
240 }
241
242 /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */
243- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
244+ ver = ver_int - microblaze_version_to_int("v8.30.a");
245 if (ver < 0)
246 {
247 if (TARGET_REORDER == 1)
248--
2492.14.2
250
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
new file mode 100644
index 00000000..1d877be6
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch
@@ -0,0 +1,52 @@
1From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:50 -0700
4Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction.
5
6Bit field instruction should be generated only if mcpu >10.0
7
8Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com>
9Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
10Upstream-Status: Pending
11---
12 gcc/config/microblaze/microblaze.c | 3 +++
13 gcc/config/microblaze/microblaze.h | 2 ++
14 2 files changed, 5 insertions(+)
15
16diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
17index 55dba83882..4f6d399bba 100644
18--- a/gcc/config/microblaze/microblaze.c
19+++ b/gcc/config/microblaze/microblaze.c
20@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay;
21 /* Set to one if the targeted core has the CLZ insn. */
22 int microblaze_has_clz = 0;
23
24+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
25+int microblaze_has_bitfield = 0;
26+
27 /* Which CPU pipeline do we use. We haven't really standardized on a CPU
28 version having only a particular type of pipeline. There can still be
29 options on the CPU to scale pipeline features up or down. :(
30diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
31index 3f48e48f10..712525f856 100644
32--- a/gcc/config/microblaze/microblaze.h
33+++ b/gcc/config/microblaze/microblaze.h
34@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
35
36 extern int microblaze_no_unsafe_delay;
37 extern int microblaze_has_clz;
38+extern int microblaze_has_bitfield;
39 extern enum pipeline_type microblaze_pipe;
40
41 #define OBJECT_FORMAT_ELF
42@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
43
44 /* Do we have CLZ? */
45 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
46+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
47
48 /* The default is to support PIC. */
49 #define TARGET_SUPPORTS_PIC 1
50--
512.14.2
52
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
new file mode 100644
index 00000000..3786a71a
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch
@@ -0,0 +1,48 @@
1From fdb99f97b41f7cd06b81e668b88463d0fc2cbe87 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:54 -0700
4Subject: [PATCH] Fixing the issue with MicroBlaze builtin_alloc
5
6Fixing the issue with the builtin_alloc. Register r18 was not properly
7handling the stack pattern which was resolved by using free available
8register
9
10Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
11Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
12Upstream-Status: Pending
13---
14 gcc/config/microblaze/microblaze.md | 8 ++++----
15 1 file changed, 4 insertions(+), 4 deletions(-)
16
17diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
18index 7a00629922..68c3b22bd4 100644
19--- a/gcc/config/microblaze/microblaze.md
20+++ b/gcc/config/microblaze/microblaze.md
21@@ -2076,10 +2076,10 @@
22 ""
23 {
24 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
25- rtx rtmp = gen_rtx_REG (SImode, R_TMP);
26+ rtx reg = gen_reg_rtx (Pmode);
27 rtx neg_op0;
28
29- emit_move_insn (rtmp, retaddr);
30+ emit_move_insn (reg, retaddr);
31 if (GET_CODE (operands[1]) != CONST_INT)
32 {
33 neg_op0 = gen_reg_rtx (Pmode);
34@@ -2088,9 +2088,9 @@
35 neg_op0 = GEN_INT (- INTVAL (operands[1]));
36
37 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
38- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
39+ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
40 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
41- emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
42+ emit_insn (gen_rtx_CLOBBER (SImode, reg));
43 DONE;
44 }
45 )
46--
472.14.2
48
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
new file mode 100644
index 00000000..29bc752e
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch
@@ -0,0 +1,83 @@
1From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
3Date: Sat, 26 Aug 2017 19:21:56 -0700
4Subject: [PATCH] MicroBlaze remove bitfield instructions macros
5
6Remove the conditions in the bit field expand macros to generate the
7instructions in structure bit-field usecases
8
9ChangeLog:
10
112018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
12
13 * gcc/config/microblaze/microblaze.md:
14 remove the expand constraints
15
16Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
17Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
18Upstream-Status: Pending
19---
20 gcc/config/microblaze/microblaze.md | 40 +++++--------------------------------
21 1 file changed, 5 insertions(+), 35 deletions(-)
22
23diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
24index 68c3b22bd4..ef53c3069e 100644
25--- a/gcc/config/microblaze/microblaze.md
26+++ b/gcc/config/microblaze/microblaze.md
27@@ -2482,25 +2482,8 @@
28 (match_operand:SI 2 "immediate_operand" "I")
29 (match_operand:SI 3 "immediate_operand" "I")))]
30 "TARGET_HAS_BITFIELD"
31-"
32-{
33- unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
34- unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
35-
36- if ((len == 0) || (pos + len > 32) )
37- FAIL;
38-
39- ;;if (!register_operand (operands[1], VOIDmode))
40- ;; FAIL;
41- if (operands[0] == operands[1])
42- FAIL;
43- if (GET_CODE (operands[1]) == ASHIFT)
44- FAIL;
45-;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
46- emit_insn (gen_extv_32 (operands[0], operands[1],
47- operands[2], operands[3]));
48- DONE;
49-}")
50+""
51+)
52
53 (define_insn "extv_32"
54 [(set (match_operand:SI 0 "register_operand" "=r")
55@@ -2518,22 +2501,9 @@
56 (match_operand:SI 1 "immediate_operand" "I")
57 (match_operand:SI 2 "immediate_operand" "I"))
58 (match_operand:SI 3 "register_operand" "r"))]
59- "TARGET_HAS_BITFIELD"
60- "
61-{
62- unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
63- unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
64-
65- if (len <= 0 || pos + len > 32)
66- FAIL;
67-
68- ;;if (!register_operand (operands[0], VOIDmode))
69- ;; FAIL;
70-
71- emit_insn (gen_insv_32 (operands[0], operands[1],
72- operands[2], operands[3]));
73- DONE;
74-}")
75+"TARGET_HAS_BITFIELD"
76+""
77+)
78
79 (define_insn "insv_32"
80 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
81--
822.14.2
83
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
new file mode 100644
index 00000000..eaae5667
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch
@@ -0,0 +1,51 @@
1From e2a7a582945d24ede55393462a3360f377f45478 Mon Sep 17 00:00:00 2001
2From: Nathan Rossi <nathan@nathanrossi.com>
3Date: Sun, 5 Nov 2017 23:03:54 +1000
4Subject: [PATCH] MicroBlaze fix signed bit fields with bit field instructions
5
6The 'extv' definition is expected to sign extended the result based on
7the width of the bit field.
8
9 https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html#index-extvm-instruction-pattern
10
11The MicroBlaze 'bsefi' instruction does not sign extended, it zero
12extends. There is no option for the instruction to sign extended the
13result and no simple instruction or expression to implement a variant
14length sign extend (only sext8/sext16 instructions exist).
15
16As such these definitions needs to be changed to the zero extended
17variant of 'extv' which is 'extzv'. This change updates the existing
18definitions to allow for signed bit fields to function correctly and be
19sign extended.
20
21Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
22Upstream-Status: Pending
23---
24 gcc/config/microblaze/microblaze.md | 4 ++--
25 1 file changed, 2 insertions(+), 2 deletions(-)
26
27diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
28index ef53c3069e..b52be42d6e 100644
29--- a/gcc/config/microblaze/microblaze.md
30+++ b/gcc/config/microblaze/microblaze.md
31@@ -2476,7 +2476,7 @@
32 DONE;
33 }")
34
35-(define_expand "extvsi"
36+(define_expand "extzvsi"
37 [(set (match_operand:SI 0 "register_operand" "r")
38 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
39 (match_operand:SI 2 "immediate_operand" "I")
40@@ -2485,7 +2485,7 @@
41 ""
42 )
43
44-(define_insn "extv_32"
45+(define_insn "extzv_32"
46 [(set (match_operand:SI 0 "register_operand" "=r")
47 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
48 (match_operand:SI 2 "immediate_operand" "I")
49--
502.14.2
51
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
index 5b695638..d6b69001 100644
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
+++ b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend
@@ -3,7 +3,36 @@ FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-7:"
3SRC_URI_append_microblaze = " \ 3SRC_URI_append_microblaze = " \
4 file://0001-Revert.patch \ 4 file://0001-Revert.patch \
5 file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \ 5 file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \
6 file://0003-microblaze-sync.md-Correct-behaviour-and-define-side.patch \ 6 file://0003-gcc-config-microblaze-Use-default-ident-output-gener.patch \
7 file://0004-gcc-config-microblaze-Use-default-ident-output-gener.patch \ 7 file://0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch \
8 file://0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch \
9 file://0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch \
10 file://0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \
11 file://0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch \
12 file://0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \
13 file://0010-Fix-atomic-side-effects.patch \
14 file://0011-Fix-atomic-boolean-return-value.patch \
15 file://0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch \
16 file://0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch \
17 file://0014-Removed-MicroBlaze-moddi3-routinue.patch \
18 file://0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch \
19 file://0016-MicroBlaze-use-bralid-for-profiler-calls.patch \
20 file://0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch \
21 file://0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \
22 file://0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch \
23 file://0020-Modified-MicroBlaze-trap-instruction.patch \
24 file://0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch \
25 file://0022-Inline-Expansion-of-fsqrt-builtin.patch \
26 file://0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch \
27 file://0024-8-stage-pipeline-for-microblaze.patch \
28 file://0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch \
29 file://0026-Fix-internal-compiler-error-with-msmall-divides.patch \
30 file://0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \
31 file://0028-Add-new-bit-field-instructions.patch \
32 file://0029-Fix-bug-in-MB-version-calculation.patch \
33 file://0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch \
34 file://0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch \
35 file://0032-MicroBlaze-remove-bitfield-instructions-macros.patch \
36 file://0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch \
8 " 37 "
9 38
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-03 06:38:04 +0000