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-rw-r--r--extras/recipes-kernel/linux/linux-omap/usrp/0003-usrp-embedded-Add-driver-for-USRP-Embedded-FPGA-inte.patch1889
1 files changed, 1889 insertions, 0 deletions
diff --git a/extras/recipes-kernel/linux/linux-omap/usrp/0003-usrp-embedded-Add-driver-for-USRP-Embedded-FPGA-inte.patch b/extras/recipes-kernel/linux/linux-omap/usrp/0003-usrp-embedded-Add-driver-for-USRP-Embedded-FPGA-inte.patch
new file mode 100644
index 00000000..400807d1
--- /dev/null
+++ b/extras/recipes-kernel/linux/linux-omap/usrp/0003-usrp-embedded-Add-driver-for-USRP-Embedded-FPGA-inte.patch
@@ -0,0 +1,1889 @@
1From 56a2e5e0ace395e94f176a90a12d3cfcd8b7f68f Mon Sep 17 00:00:00 2001
2From: Philip Balister <balister@moose.(none)>
3Date: Wed, 13 Jan 2010 14:35:39 -0500
4Subject: [PATCH 3/3] usrp-embedded : Add driver for USRP Embedded FPGA interface.
5
6---
7 arch/arm/mach-omap2/board-overo.c | 176 +++++-
8 drivers/misc/Kconfig | 9 +
9 drivers/misc/Makefile | 1 +
10 drivers/misc/usrp_e.c | 1481 +++++++++++++++++++++++++++++++++++++
11 include/linux/usrp_e.h | 87 +++
12 5 files changed, 1750 insertions(+), 4 deletions(-)
13 create mode 100644 drivers/misc/usrp_e.c
14 create mode 100644 include/linux/usrp_e.h
15
16diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
17index 8a44c17..8686015 100644
18--- a/arch/arm/mach-omap2/board-overo.c
19+++ b/arch/arm/mach-omap2/board-overo.c
20@@ -35,6 +35,8 @@
21 #include <linux/mtd/partitions.h>
22 #include <linux/mmc/host.h>
23
24+#include <linux/spi/spi.h>
25+
26 #include <asm/mach-types.h>
27 #include <asm/mach/arch.h>
28 #include <asm/mach/flash.h>
29@@ -63,6 +65,8 @@
30 #define OVERO_GPIO_USBH_NRESET 183
31
32 #define NAND_BLOCK_SIZE SZ_128K
33+#define GPMC_CS0_BASE 0x60
34+#define GPMC_CS_SIZE 0x30
35
36 #define OVERO_SMSC911X_CS 5
37 #define OVERO_SMSC911X_GPIO 176
38@@ -164,7 +168,9 @@ static struct platform_device overo_smsc911x2_device = {
39
40 static struct platform_device *smsc911x_devices[] = {
41 &overo_smsc911x_device,
42+#if 0
43 &overo_smsc911x2_device,
44+#endif
45 };
46
47 static inline void __init overo_init_smsc911x(void)
48@@ -194,6 +200,7 @@ static inline void __init overo_init_smsc911x(void)
49
50 /* set up second smsc911x chip */
51
52+#if 0
53 if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
54 printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
55 return;
56@@ -213,6 +220,7 @@ static inline void __init overo_init_smsc911x(void)
57 overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
58 overo_smsc911x2_resources[1].end = 0;
59
60+#endif
61 platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
62 }
63
64@@ -353,6 +361,16 @@ static struct regulator_consumer_supply overo_vdda_dac_supply =
65 static struct regulator_consumer_supply overo_vdds_dsi_supply =
66 REGULATOR_SUPPLY("vdds_dsi", "omapdss");
67
68+static struct spi_board_info overo_mcspi_board_info[] = {
69+ {
70+ .modalias = "spidev",
71+ .max_speed_hz = 12000000, // 12 MHz
72+ .bus_num = 1,
73+ .chip_select = 0,
74+ .mode = SPI_MODE_1,
75+ },
76+};
77+
78 static struct mtd_partition overo_nand_partitions[] = {
79 {
80 .name = "xloader",
81@@ -432,8 +450,8 @@ static struct omap2_hsmmc_info mmc[] = {
82 .mmc = 2,
83 .caps = MMC_CAP_4_BIT_DATA,
84 .gpio_cd = -EINVAL,
85- .gpio_wp = -EINVAL,
86- .transceiver = true,
87+ .transceiver = true,
88+ .gpio_wp = 150,
89 .ocr_mask = 0x00100000, /* 3.3V */
90 },
91 {} /* Terminator */
92@@ -612,6 +630,8 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
93 static struct omap_board_mux board_mux[] __initdata = {
94 { .reg_offset = OMAP_MUX_TERMINATOR },
95 };
96+#else
97+#define board_mux NULL
98 #endif
99
100 static struct omap_musb_board_data musb_board_data = {
101@@ -626,6 +646,148 @@ static struct omap_musb_board_data musb_board_data = {
102 .power = 100,
103 };
104
105+static void __init usrp1_e_init(void)
106+{
107+ unsigned int tmp;
108+
109+ printk("Setup up gpmc timing.\n");
110+
111+// Set up CS4, data read/write
112+
113+#if 1
114+ // Signal control parameters per chip select
115+ tmp = gpmc_cs_read_reg(4, GPMC_CS_CONFIG1);
116+// tmp |= (GPMC_CONFIG1_MUXADDDATA);
117+// tmp |= (GPMC_CONFIG1_WRITETYPE_SYNC);
118+// tmp |= (GPMC_CONFIG1_READTYPE_SYNC);
119+ tmp |= (GPMC_CONFIG1_FCLK_DIV(0));
120+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG1, tmp);
121+ printk("GPMC_CONFIG1 reg: %x\n", tmp);
122+#endif
123+
124+#if 1
125+ // CS signal timing parameter configuration
126+ tmp = 0;
127+ tmp |= GPMC_CONFIG2_CSONTIME(1); /* 1 */
128+ tmp |= GPMC_CONFIG2_CSWROFFTIME(16); /* 16 */
129+ tmp |= GPMC_CONFIG2_CSRDOFFTIME(16); /* 16 */
130+ printk("GPMC_CONFIG2 reg: %x\n", tmp);
131+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG2, tmp);
132+#endif
133+
134+#if 0
135+ // nADV signal timing parameter configuration
136+ tmp = 0;
137+ tmp |= GPMC_CONFIG3_ADVONTIME(1);
138+ tmp |= GPMC_CONFIG3_ADVRDOFFTIME(2);
139+ tmp |= GPMC_CONFIG3_ADVWROFFTIME(2);
140+ printk("GPMC_CONFIG3 reg: %x\n", tmp);
141+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG3, tmp);
142+#endif
143+
144+#if 1
145+ // nWE and nOE signals timing parameter configuration
146+ tmp = 0;
147+ tmp |= GPMC_CONFIG4_WEONTIME(3); /* 3 */
148+ tmp |= GPMC_CONFIG4_WEOFFTIME(16); /* 16 */
149+ tmp |= GPMC_CONFIG4_OEONTIME(3); /* 3 */
150+ tmp |= GPMC_CONFIG4_OEOFFTIME(16); /* 16 */
151+ printk("GPMC_CONFIG4 reg: %x\n", tmp);
152+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG4, tmp);
153+#endif
154+
155+#if 1
156+ // RdAccess time and Cycle time timing parameters configuration
157+ tmp = 0;
158+ tmp |= GPMC_CONFIG5_PAGEBURSTACCESSTIME(1);
159+ tmp |= GPMC_CONFIG5_RDACCESSTIME(15); /* 15 */
160+ tmp |= GPMC_CONFIG5_WRCYCLETIME(17); /* 17 */
161+ tmp |= GPMC_CONFIG5_RDCYCLETIME(17); /* 17 */
162+ printk("GPMC_CONFIG5 reg: %x\n", tmp);
163+
164+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG5, tmp);
165+#endif
166+
167+#if 1
168+ // WrAccessTime WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround params
169+ tmp = (1<<31);
170+ tmp |= GPMC_CONFIG6_WRACCESSTIME(15); /* 15 */
171+ tmp |= GPMC_CONFIG6_WRDATAONADMUXBUS(3);
172+ tmp |= GPMC_CONFIG6_CYCLE2CYCLEDELAY(0);
173+ tmp |= GPMC_CONFIG6_BUSTURNAROUND(0);
174+ printk("GPMC_CONFIG6 reg: %x\n", tmp);
175+ gpmc_cs_write_reg(4, GPMC_CS_CONFIG6, tmp);
176+#endif
177+
178+// Configure timing for CS6, wishbone access
179+
180+#if 1
181+ // Signal control parameters per chip select
182+ tmp = gpmc_cs_read_reg(6, GPMC_CS_CONFIG1);
183+// tmp |= (GPMC_CONFIG1_MUXADDDATA);
184+ tmp |= (GPMC_CONFIG1_WRITETYPE_SYNC);
185+ tmp |= (GPMC_CONFIG1_READTYPE_SYNC);
186+ tmp |= (GPMC_CONFIG1_FCLK_DIV(0));
187+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG1, tmp);
188+ printk("GPMC_CONFIG1 reg: %x\n", tmp);
189+#endif
190+
191+#if 1
192+ // CS signal timing parameter configuration
193+ tmp = 0;
194+ tmp |= GPMC_CONFIG2_CSONTIME(1);
195+ tmp |= GPMC_CONFIG2_CSWROFFTIME(17);
196+ tmp |= GPMC_CONFIG2_CSRDOFFTIME(17);
197+ printk("GPMC_CONFIG2 reg: %x\n", tmp);
198+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG2, tmp);
199+#endif
200+
201+#if 0
202+ // nADV signal timing parameter configuration
203+ tmp = 0;
204+ tmp |= GPMC_CONFIG3_ADVONTIME(1);
205+ tmp |= GPMC_CONFIG3_ADVRDOFFTIME(2);
206+ tmp |= GPMC_CONFIG3_ADVWROFFTIME(2);
207+ printk("GPMC_CONFIG3 reg: %x\n", tmp);
208+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG3, tmp);
209+#endif
210+
211+#if 0
212+ // nWE and nOE signals timing parameter configuration
213+ tmp = 0;
214+ tmp |= GPMC_CONFIG4_WEONTIME(3);
215+ tmp |= GPMC_CONFIG4_WEOFFTIME(4);
216+ tmp |= GPMC_CONFIG4_OEONTIME(3);
217+ tmp |= GPMC_CONFIG4_OEOFFTIME(4);
218+ printk("GPMC_CONFIG4 reg: %x\n", tmp);
219+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG4, tmp);
220+#endif
221+
222+#if 0
223+ // RdAccess time and Cycle time timing paraters configuration
224+ tmp = 0;
225+ tmp |= GPMC_CONFIG5_PAGEBURSTACCESSTIME(1);
226+ tmp |= GPMC_CONFIG5_RDACCESSTIME(4);
227+ tmp |= GPMC_CONFIG5_WRCYCLETIME(5);
228+ tmp |= GPMC_CONFIG5_RDCYCLETIME(5);
229+ printk("GPMC_CONFIG5 reg: %x\n", tmp);
230+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG5, tmp);
231+#endif
232+
233+#if 1
234+ // WrAccessTime WrDataOnADmuxBus, Cycle2Cycle, and BusTurnAround params
235+ tmp = 0;
236+ tmp |= GPMC_CONFIG6_WRACCESSTIME(15);
237+ tmp |= GPMC_CONFIG6_WRDATAONADMUXBUS(3);
238+ tmp |= GPMC_CONFIG6_CYCLE2CYCLEDELAY(3);
239+ tmp |= GPMC_CONFIG6_CYCLE2CYCLESAMECSEN;
240+ tmp |= GPMC_CONFIG6_BUSTURNAROUND(0);
241+ printk("GPMC_CONFIG6 reg: %x\n", tmp);
242+ gpmc_cs_write_reg(6, GPMC_CS_CONFIG6, tmp);
243+#endif
244+
245+}
246+
247 static void __init overo_init(void)
248 {
249 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
250@@ -637,8 +799,14 @@ static void __init overo_init(void)
251 usb_ehci_init(&ehci_pdata);
252 overo_spi_init();
253 overo_init_smsc911x();
254+#if 0
255 overo_display_init();
256-
257+#endif
258+ usrp1_e_init();
259+#if 1
260+ spi_register_board_info(overo_mcspi_board_info,
261+ ARRAY_SIZE(overo_mcspi_board_info));
262+#endif
263 /* Ensure SDRC pins are mux'd for self-refresh */
264 omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
265 omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
266@@ -680,7 +848,7 @@ static void __init overo_init(void)
267 "OVERO_GPIO_USBH_CPEN\n");
268 }
269
270-MACHINE_START(OVERO, "Gumstsix Overo")
271+MACHINE_START(OVERO, "Gumstix Overo")
272 .boot_params = 0x80000100,
273 .map_io = omap3_map_io,
274 .reserve = omap_reserve,
275diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
276index 4d073f1..8bd6dfb 100644
277--- a/drivers/misc/Kconfig
278+++ b/drivers/misc/Kconfig
279@@ -452,6 +452,15 @@ config PCH_PHUB
280 To compile this driver as a module, choose M here: the module will
281 be called pch_phub.
282
283+config USRP_E
284+ tristate "USRP-E FPGA interface driver"
285+ default n
286+ help
287+ This driver is for the Ettus Research USRP Embedded Software
288+ Defined Radio platform.
289+
290+ If you do not plan to run this kernel on that hardware choose N.
291+
292 source "drivers/misc/c2port/Kconfig"
293 source "drivers/misc/eeprom/Kconfig"
294 source "drivers/misc/cb710/Kconfig"
295diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
296index 98009cc..f43483e 100644
297--- a/drivers/misc/Makefile
298+++ b/drivers/misc/Makefile
299@@ -35,6 +35,7 @@ obj-$(CONFIG_TI_DAC7512) += ti_dac7512.o
300 obj-$(CONFIG_C2PORT) += c2port/
301 obj-$(CONFIG_IWMC3200TOP) += iwmc3200top/
302 obj-$(CONFIG_HMC6352) += hmc6352.o
303+obj-$(CONFIG_USRP_E) += usrp_e.o
304 obj-y += eeprom/
305 obj-y += cb710/
306 obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o
307diff --git a/drivers/misc/usrp_e.c b/drivers/misc/usrp_e.c
308new file mode 100644
309index 0000000..2923b14
310--- /dev/null
311+++ b/drivers/misc/usrp_e.c
312@@ -0,0 +1,1481 @@
313+/*
314+ * -*- linux-c -*-
315+ * Interface for USRP Embedded from Ettus Research, LLC.
316+ * This driver uses the GPMC interface on the OMAP3 to pass data
317+ * to/from a Spartan 3 FPGA.
318+ *
319+ * Copyright (C) Ettus Research, LLC
320+ *
321+ * Written by Philip Balister <philip@opensdr.com>
322+ *
323+ * This program is free software; you can redistribute it and/or modify
324+ * it under the terms of the GNU General Public License version 2 as
325+ * published by the Free Software Foundation.
326+ */
327+
328+#include "linux/fs.h"
329+#include "linux/module.h"
330+#include "linux/cdev.h"
331+#include "linux/device.h"
332+#include "linux/spinlock.h"
333+#include "linux/errno.h"
334+#include "linux/irq.h"
335+#include "linux/interrupt.h"
336+#include "linux/wait.h"
337+#include "linux/sched.h"
338+#include "linux/dma-mapping.h"
339+#include "linux/semaphore.h"
340+#include "linux/kthread.h"
341+#include "linux/poll.h"
342+#include "linux/slab.h"
343+
344+#include "plat/gpmc.h"
345+#include "plat/gpio.h"
346+#include "plat/dma.h"
347+
348+#include "asm/uaccess.h"
349+#include "asm/io.h"
350+#include "asm/atomic.h"
351+
352+#include "linux/usrp_e.h"
353+
354+#define TX_SPACE_AVAILABLE_GPIO 144
355+#define RX_DATA_READY_GPIO 146
356+
357+static atomic_t use_count = ATOMIC_INIT(0);
358+static atomic_t mapped = ATOMIC_INIT(0);
359+static int shutting_down;
360+
361+struct spi_regs_wb;
362+struct i2c_regs_wb;
363+
364+struct usrp_e_dev {
365+ struct cdev cdev;
366+ unsigned long mem_base;
367+ unsigned long control_mem_base;
368+ u32 *ioaddr;
369+ u8 *ctl_addr;
370+ struct spi_regs_wb *ctl_spi;
371+ struct i2c_regs_wb *ctl_i2c;
372+ spinlock_t fpga_lock;
373+
374+ atomic_t n_overruns;
375+ atomic_t n_underruns;
376+
377+} *usrp_e_devp;
378+
379+struct dma_data {
380+ int ch;
381+ struct omap_dma_channel_params params;
382+
383+ unsigned long virt_from;
384+ unsigned long virt_to;
385+ unsigned long phys_from;
386+ unsigned long phys_to;
387+};
388+
389+#define MISC_REGS_BASE 0x0
390+
391+#define UE_REG_MISC_LED (MISC_REGS_BASE + 0)
392+
393+#define UE_REG_MISC_RX_LEN (MISC_REGS_BASE + 10)
394+#define UE_REG_MISC_TX_LEN (MISC_REGS_BASE + 12)
395+
396+#define UE_REG_SLAVE(n) ((n)<<7)
397+#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n)))
398+
399+#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25)
400+#define UE_SR_CLEAR_FIFO UE_REG_SR_ADDR(6)
401+
402+#define CTL_SPI_BASE 0x100
403+
404+struct spi_regs_wb {
405+ u32 txrx0;
406+ u32 txrx1;
407+ u32 txrx2;
408+ u32 txrx3;
409+ u32 ctrl;
410+ u32 div;
411+ u32 ss;
412+};
413+
414+/* Defines for spi ctrl register */
415+#define UE_SPI_CTRL_ASS (BIT(13))
416+#define UE_SPI_CTRL_IE (BIT(12))
417+#define UE_SPI_CTRL_LSB (BIT(11))
418+/* defines for TXNEG and RXNEG in usrp_e.h so user can pass them to driver. */
419+#define UE_SPI_CTRL_GO_BSY (BIT(8))
420+#define UE_SPI_CTRL_CHAR_LEN_MASK 0x7f
421+
422+
423+#define CTL_I2C_BASE 0x180
424+#if 1
425+struct i2c_regs_wb {
426+ u8 prescalar_lo;
427+ u8 dummy;
428+ u8 dummy1;
429+ u8 dummy2;
430+ u8 prescalar_hi;
431+ u8 dummy3;
432+ u8 dummy4;
433+ u8 dummy5;
434+ u8 ctrl;
435+ u8 dummy6;
436+ u8 dummy7;
437+ u8 dummy8;
438+ u8 data;
439+ u8 dummy9;
440+ u8 dummy10;
441+ u8 dummy11;
442+ u8 cmd_status;
443+};
444+#else
445+struct i2c_regs_wb {
446+ u16 prescalar_lo;
447+ u16 dummy2;
448+ u16 prescalar_hi;
449+ u16 dummy3;
450+ u16 ctrl;
451+ u16 dummy6;
452+ u16 data;
453+ u16 dummy9;
454+ u16 cmd_status;
455+};
456+#endif
457+
458+#define I2C_CTRL_EN (BIT(7)) /* core enable */
459+#define I2C_CTRL_IE (BIT(6)) /* interrupt enable */
460+
461+/* STA, STO, RD, WR, and IACK bits are cleared automatically */
462+
463+#define I2C_CMD_START (BIT(7))
464+#define I2C_CMD_STOP (BIT(6))
465+#define I2C_CMD_RD (BIT(5))
466+#define I2C_CMD_WR (BIT(4))
467+#define I2C_CMD_NACK (BIT(3))
468+#define I2C_CMD_RSVD_2 (BIT(2))
469+#define I2C_CMD_RSVD_1 (BIT(1))
470+#define I2C_CMD_IACK (BIT(0))
471+
472+#define I2C_ST_RXACK (BIT(7))
473+#define I2C_ST_BUSY (BIT(6))
474+#define I2C_ST_AL (BIT(5))
475+#define I2C_RSVD_4 (BIT(4))
476+#define I2C_RSVD_3 (BIT(3))
477+#define I2C_RSVD_2 (BIT(2))
478+#define I2C_ST_TIP (BIT(1))
479+#define I2C_ST_IP (BIT(0))
480+
481+#define MAX_WB_DIV 4
482+#define MASTER_CLK_RATE 64000000
483+#define PRESCALAR(wb_div) (((MASTER_CLK_RATE/(wb_div)) / (5 * 100000)) - 1)
484+
485+static __u16 prescalar_values[MAX_WB_DIV+1] = {
486+ 0xffff,
487+ PRESCALAR(1),
488+ PRESCALAR(2),
489+ PRESCALAR(3),
490+ PRESCALAR(4),
491+};
492+
493+static struct dma_data *rx_dma;
494+static struct dma_data *tx_dma;
495+
496+struct ring_buffer_entry {
497+ unsigned long dma_addr;
498+ __u8 *frame_addr;
499+};
500+
501+struct ring_buffer {
502+ struct ring_buffer_info (*rbi)[];
503+ struct ring_buffer_entry (*rbe)[];
504+ int num_pages;
505+ unsigned long (*pages)[];
506+};
507+
508+static struct ring_buffer tx_rb;
509+static struct ring_buffer rx_rb;
510+
511+static struct usrp_e_ring_buffer_size_t rb_size;
512+
513+#define NUM_PAGES_RX_FLAGS 1
514+#define NUM_RX_FRAMES 100
515+#define NUM_PAGES_TX_FLAGS 1
516+#define NUM_TX_FRAMES 100
517+
518+static int tx_rb_write;
519+static int tx_rb_read;
520+static int rx_rb_write;
521+static int rx_rb_read;
522+
523+static int alloc_ring_buffer(struct ring_buffer *rb,
524+ unsigned int num_bufs, enum dma_data_direction direction);
525+static void delete_ring_buffer(struct ring_buffer *rb,
526+ unsigned int num_bufs, enum dma_data_direction direction);
527+static int alloc_ring_buffers(void);
528+static void init_ring_buffer(struct ring_buffer *rb, int num_bufs,
529+ int init_flags, enum dma_data_direction direction);
530+
531+static dev_t usrp_e_dev_number;
532+static struct class *usrp_e_class;
533+
534+#define DEVICE_NAME "usrp_e"
535+
536+static const struct file_operations usrp_e_fops;
537+
538+static irqreturn_t space_available_irqhandler(int irq, void *dev_id);
539+static irqreturn_t data_ready_irqhandler(int irq, void *dev_id);
540+static void usrp_rx_dma_irq(int ch, u16 stat, void *data);
541+static void usrp_tx_dma_irq(int ch, u16 stat, void *data);
542+
543+static DECLARE_WAIT_QUEUE_HEAD(data_received_queue);
544+static DECLARE_WAIT_QUEUE_HEAD(space_available_queue);
545+static DECLARE_WAIT_QUEUE_HEAD(received_data_from_user);
546+static DECLARE_WAIT_QUEUE_HEAD(tx_rb_space_available);
547+
548+static int tx_dma_waiting_for_data;
549+static int waiting_for_space_in_tx_rb;
550+
551+#define DEBUG_RX 1
552+
553+static DEFINE_SEMAPHORE(dma_lock);
554+
555+static void usrp_e_spi_init(void);
556+static void usrp_e_i2c_init(void);
557+
558+static int init_dma_controller(void);
559+static void release_dma_controller(void);
560+static int get_frame_from_fpga_start(void);
561+static int get_frame_from_fpga_finish(void);
562+static int send_frame_to_fpga_start(void);
563+static int send_frame_to_fpga_finish(void);
564+
565+static int rx_dma_active;
566+static int tx_dma_active;
567+
568+static int __init
569+usrp_e_init(void)
570+{
571+ int ret;
572+ struct usrp_e_dev *p;
573+
574+ printk(KERN_DEBUG "usrp_e entering driver initialization\n");
575+
576+ if (alloc_chrdev_region(&usrp_e_dev_number, 0, 1, DEVICE_NAME) < 0) {
577+ printk(KERN_DEBUG "Can't register device\n");
578+ return -1;
579+ }
580+
581+ usrp_e_class = class_create(THIS_MODULE, DEVICE_NAME);
582+
583+ usrp_e_devp = kzalloc(sizeof(struct usrp_e_dev), GFP_KERNEL);
584+ if (!usrp_e_devp) {
585+ printk(KERN_ERR "Bad kmalloc\n");
586+ return -ENOMEM;
587+ }
588+
589+ p = usrp_e_devp; /* Shorten var name so I stay sane. */
590+
591+ printk(KERN_DEBUG "usrp_e data struct malloc'd.\n");
592+
593+ atomic_set(&p->n_underruns, 0);
594+ atomic_set(&p->n_overruns, 0);
595+
596+ printk(KERN_DEBUG "usrp_e Data initialized..\n");
597+
598+ cdev_init(&p->cdev, &usrp_e_fops);
599+ p->cdev.owner = THIS_MODULE;
600+
601+ ret = cdev_add(&p->cdev, MKDEV(MAJOR(usrp_e_dev_number), 0), 1);
602+ if (ret) {
603+ printk(KERN_ERR "Bad cdev\n");
604+ return ret;
605+ }
606+
607+ printk(KERN_DEBUG "usrp_e major number : %d\n",
608+ MAJOR(usrp_e_dev_number));
609+ device_create(usrp_e_class, NULL, MKDEV(MAJOR(usrp_e_dev_number), 0),
610+ NULL, "usrp_e%d", 0);
611+
612+ printk(KERN_DEBUG "Getting Chip Select\n");
613+
614+ if (gpmc_cs_request(4, SZ_2K, &p->mem_base) < 0) {
615+ printk(KERN_ERR "Failed request for GPMC mem for usrp_e\n");
616+ return -1;
617+ }
618+ printk(KERN_DEBUG "Got CS4, address = %lx\n", p->mem_base);
619+
620+ if (!request_mem_region(p->mem_base, SZ_2K, "usrp_e")) {
621+ printk(KERN_ERR "Request_mem_region failed.\n");
622+ gpmc_cs_free(4);
623+ return -1;
624+ }
625+
626+ p->ioaddr = ioremap(p->mem_base, SZ_2K);
627+ spin_lock_init(&p->fpga_lock);
628+
629+ if (gpmc_cs_request(6, SZ_2K, &p->control_mem_base) < 0) {
630+ printk(KERN_ERR "Failed request for GPMC control mem for usrp_e\n");
631+ return -1;
632+ }
633+ printk(KERN_DEBUG "Got CS6, address = %lx\n", p->control_mem_base);
634+
635+ if (!request_mem_region(p->control_mem_base, SZ_2K, "usrp_e_c")) {
636+ printk(KERN_ERR "Request_mem_region failed.\n");
637+ gpmc_cs_free(6);
638+ return -1;
639+ }
640+
641+ p->ctl_addr = ioremap_nocache(p->control_mem_base, SZ_2K);
642+
643+ /* Initialize wishbone SPI and I2C interfaces */
644+
645+ usrp_e_spi_init();
646+ usrp_e_i2c_init();
647+
648+ /* Configure GPIO's */
649+
650+ if (!(((gpio_request(TX_SPACE_AVAILABLE_GPIO,
651+ "TX_SPACE_AVAILABLE_GPIO") == 0) &&
652+ (gpio_direction_input(TX_SPACE_AVAILABLE_GPIO) == 0)))) {
653+ printk(KERN_ERR "Could not claim GPIO for TX_SPACE_AVAILABLE_GPIO\n");
654+ return -1;
655+ }
656+
657+ if (!(((gpio_request(RX_DATA_READY_GPIO, "RX_DATA_READY_GPIO") == 0) &&
658+ (gpio_direction_input(RX_DATA_READY_GPIO) == 0)))) {
659+ printk(KERN_ERR "Could not claim GPIO for RX_DATA_READY_GPIO\n");
660+ return -1;
661+ }
662+
663+ /* Debug gpios */
664+ if (!(((gpio_request(14, "Debug0") == 0) &&
665+ (gpio_direction_output(14, 0) == 0)))) {
666+ printk(KERN_ERR "Could not claim GPIO for Debug0\n");
667+ return -1;
668+ }
669+
670+ if (!(((gpio_request(21, "Debug1") == 0) &&
671+ (gpio_direction_output(21, 0) == 0)))) {
672+ printk(KERN_ERR "Could not claim GPIO for Debug1\n");
673+ return -1;
674+ }
675+
676+ if (!(((gpio_request(22, "Debug2") == 0) &&
677+ (gpio_direction_output(22, 0) == 0)))) {
678+ printk(KERN_ERR "Could not claim GPIO for Debug2\n");
679+ return -1;
680+ }
681+
682+ if (!(((gpio_request(23, "Debug3") == 0) &&
683+ (gpio_direction_output(23, 0) == 0)))) {
684+ printk(KERN_ERR "Could not claim GPIO for Debug3\n");
685+ return -1;
686+ }
687+
688+
689+ rb_size.num_pages_rx_flags = NUM_PAGES_RX_FLAGS;
690+ rb_size.num_rx_frames = NUM_RX_FRAMES;
691+ rb_size.num_pages_tx_flags = NUM_PAGES_TX_FLAGS;
692+ rb_size.num_tx_frames = NUM_TX_FRAMES;
693+
694+ ret = alloc_ring_buffers();
695+ if (ret < 0)
696+ return ret;
697+
698+ /* Initialize various DMA related flags */
699+ rx_dma_active = 0;
700+ tx_dma_active = 0;
701+ shutting_down = 0;
702+
703+ printk(KERN_DEBUG "usrp_e Driver Initialized.\n");
704+
705+ return 0;
706+}
707+
708+static void __exit
709+usrp_e_cleanup(void)
710+{
711+ struct usrp_e_dev *p = usrp_e_devp;
712+
713+ unregister_chrdev_region(usrp_e_dev_number, 1);
714+
715+ release_mem_region(p->mem_base, SZ_2K);
716+ release_mem_region(p->control_mem_base, SZ_2K);
717+
718+ device_destroy(usrp_e_class, MKDEV(MAJOR(usrp_e_dev_number), 0));
719+ cdev_del(&p->cdev);
720+
721+ class_destroy(usrp_e_class);
722+
723+ iounmap(p->ioaddr);
724+ iounmap(p->ctl_addr);
725+
726+ gpmc_cs_free(4);
727+ gpmc_cs_free(6);
728+
729+ printk(KERN_DEBUG "Freeing gpios\n");
730+
731+ gpio_free(TX_SPACE_AVAILABLE_GPIO);
732+ gpio_free(RX_DATA_READY_GPIO);
733+
734+ /* debug */
735+ gpio_free(14);
736+ gpio_free(21);
737+ gpio_free(22);
738+ gpio_free(23);
739+
740+ delete_ring_buffer(&tx_rb, rb_size.num_tx_frames, DMA_TO_DEVICE);
741+ delete_ring_buffer(&rx_rb, rb_size.num_rx_frames, DMA_FROM_DEVICE);
742+
743+ kfree(p);
744+
745+ printk(KERN_DEBUG "Leaving cleanup\n");
746+}
747+
748+static int
749+usrp_e_open(struct inode *inode, struct file *file)
750+{
751+ struct usrp_e_dev *p = usrp_e_devp;
752+ int ret;
753+
754+ printk(KERN_DEBUG "usrp_e open called, use_count = %d\n",
755+ atomic_read(&use_count));
756+ if (atomic_add_return(1, &use_count) != 1) {
757+ printk(KERN_ERR "use_count = %d\n", atomic_read(&use_count));
758+ atomic_dec(&use_count);
759+ return -EBUSY;
760+ }
761+
762+ /* Clear rx and tx fifos in the fpga */
763+ writel(1, p->ctl_addr + UE_SR_CLEAR_FIFO);
764+ writel(2, p->ctl_addr + UE_SR_CLEAR_FIFO);
765+
766+#if 0
767+ usrp_e_devp = container_of(inode->i_cdev, struct usrp_e_dev, cdev);
768+
769+ file->private_data = usrp_e_devp;
770+#endif
771+
772+ ret = init_dma_controller();
773+ if (ret < 0)
774+ return ret;
775+
776+ tx_rb_write = 0;
777+ tx_rb_read = 0;
778+
779+ rx_rb_write = 0;
780+ rx_rb_read = 0;
781+
782+ tx_dma_active = 0;
783+ rx_dma_active = 0;
784+ shutting_down = 0;
785+
786+ init_ring_buffer(&rx_rb, rb_size.num_rx_frames, RB_KERNEL, DMA_FROM_DEVICE);
787+ init_ring_buffer(&tx_rb, rb_size.num_tx_frames, RB_KERNEL, DMA_TO_DEVICE);
788+
789+ /* Configure interrupts for GPIO pins */
790+
791+ ret = request_irq(gpio_to_irq(TX_SPACE_AVAILABLE_GPIO),
792+ space_available_irqhandler,
793+ IRQF_TRIGGER_RISING, "usrp_e_space_available", NULL);
794+
795+ ret = request_irq(gpio_to_irq(RX_DATA_READY_GPIO),
796+ data_ready_irqhandler,
797+ IRQF_TRIGGER_RISING, "usrp_e_data_ready", NULL);
798+
799+ printk(KERN_DEBUG "usrp: leaving open\n");
800+ return 0;
801+}
802+
803+static int
804+usrp_e_release(struct inode *inode, struct file *file)
805+{
806+ struct usrp_e_dev *usrp_e_devp = file->private_data;
807+
808+ printk(KERN_DEBUG "usrp_e release called\n");
809+
810+ if (atomic_read(&use_count) != 1) {
811+ printk(KERN_ERR "Attempt to close usrp_e driver that is not open");
812+ return -ENOENT;
813+ }
814+
815+ printk(KERN_DEBUG "Waiting for DMA to become inactive\n");
816+ shutting_down = 0;
817+ while (tx_dma_active || rx_dma_active)
818+ cpu_relax();
819+
820+ /* Freeing gpio irq's */
821+ printk(KERN_DEBUG "Freeing gpio irq's\n");
822+
823+ free_irq(gpio_to_irq(TX_SPACE_AVAILABLE_GPIO), NULL);
824+ free_irq(gpio_to_irq(RX_DATA_READY_GPIO), NULL);
825+
826+ printk(KERN_DEBUG "Freeing DMA channels\n");
827+
828+ release_dma_controller();
829+
830+ usrp_e_devp = 0;
831+
832+ atomic_dec(&use_count);
833+
834+ return 0;
835+}
836+
837+static ssize_t
838+usrp_e_read(struct file *file, char *buf, size_t count, loff_t *ppos)
839+{
840+ size_t ret;
841+ int rx_pkt_len;
842+
843+ if (count > SZ_2K)
844+ return -EMSGSIZE;
845+
846+ if (!((*rx_rb.rbi)[rx_rb_read].flags & RB_USER)) {
847+ if (wait_event_interruptible(data_received_queue,
848+ (((*rx_rb.rbi)[rx_rb_read].flags & RB_USER))))
849+ return -EINTR;
850+ }
851+
852+ rx_pkt_len = (*rx_rb.rbi)[rx_rb_read].len;
853+ ret = copy_to_user(buf, (*rx_rb.rbe)[rx_rb_read].frame_addr, rx_pkt_len);
854+
855+ (*rx_rb.rbi)[rx_rb_read].flags = RB_KERNEL;
856+
857+ rx_rb_read++;
858+ if (rx_rb_read == rb_size.num_rx_frames)
859+ rx_rb_read = 0;
860+
861+ get_frame_from_fpga_start();
862+
863+ return ((ret == 0) ? rx_pkt_len : -ret);
864+}
865+
866+static ssize_t
867+usrp_e_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
868+{
869+ size_t ret;
870+
871+#if 0
872+// printk("In write.\n");
873+
874+ /* Trigger a DMA transfer. Used to start transmit after writing */
875+ /* data into the transmit ring buffer from user space */
876+ if (count < 0) {
877+ send_frame_to_fpga_start();
878+ return 0;
879+ }
880+
881+ if (count > SZ_2K)
882+ return -EMSGSIZE;
883+
884+// printk("Write flags: %d\n", (*tx_rb.rbe)[tx_rb_write].flags);
885+ if (!((*tx_rb.rbi)[tx_rb_write].flags & RB_KERNEL)) {
886+ waiting_for_space_in_tx_rb = 1;
887+// printk("Sleeping\n");
888+ if (wait_event_interruptible(tx_rb_space_available,
889+ ((*tx_rb.rbi)[tx_rb_write].flags & RB_KERNEL)))
890+ return -EINTR;
891+// printk("Waking\n");
892+ }
893+
894+ ret = copy_from_user((*tx_rb.rbe)[tx_rb_write].frame_addr, buf, count);
895+ if (ret)
896+ return -ret;
897+
898+ (*tx_rb.rbi)[tx_rb_write].len = count;
899+ (*tx_rb.rbi)[tx_rb_write].flags = RB_USER;
900+
901+ tx_rb_write++;
902+ if (tx_rb_write == rb_size.num_tx_frames)
903+ tx_rb_write = 0;
904+
905+// printk("Calling send_to_fpga_start from write\n");
906+#endif
907+ send_frame_to_fpga_start();
908+
909+ return count;
910+}
911+
912+static loff_t
913+usrp_e_llseek(struct file *file, loff_t offest, int orig)
914+{
915+ printk(KERN_DEBUG "usrp_e llseek called\n");
916+
917+ return 0;
918+}
919+
920+static int usrp_e_ctl16(unsigned long arg, int direction)
921+{
922+ struct usrp_e_ctl16 __user *argp = (struct usrp_e_ctl16 __user *) arg;
923+ int i;
924+ struct usrp_e_ctl16 ctl;
925+
926+ if (copy_from_user(&ctl, argp, sizeof(struct usrp_e_ctl16)))
927+ return -EFAULT;
928+
929+ if (ctl.count > 10)
930+ return -EINVAL;
931+
932+ if (direction == 0) {
933+ for (i = 0; i < ctl.count; i++)
934+ writew(ctl.buf[i], &usrp_e_devp->ctl_addr \
935+ [i + ctl.offset]);
936+ } else if (direction == 1) {
937+ for (i = 0; i < ctl.count; i++)
938+ ctl.buf[i] = readw(&usrp_e_devp->ctl_addr \
939+ [i + ctl.offset]);
940+
941+ if (copy_to_user(argp, &ctl, sizeof(struct usrp_e_ctl16)))
942+ return -EFAULT;
943+ } else
944+ return -EFAULT;
945+
946+ return 0;
947+}
948+
949+static int usrp_e_ctl32(unsigned long arg, int direction)
950+{
951+ struct usrp_e_ctl32 __user *argp = (struct usrp_e_ctl32 __user *) arg;
952+ int i;
953+ struct usrp_e_ctl32 ctl;
954+
955+ if (copy_from_user(&ctl, argp, sizeof(struct usrp_e_ctl32)))
956+ return -EFAULT;
957+
958+ if (ctl.count > 20)
959+ return -EINVAL;
960+
961+ if (direction == 0) {
962+ for (i = 0; i < ctl.count; i++)
963+ writel(ctl.buf[i], &usrp_e_devp->ctl_addr \
964+ [i + ctl.offset]);
965+ } else if (direction == 1) {
966+ for (i = 0; i < ctl.count; i++)
967+ ctl.buf[i] = readl(&usrp_e_devp->ctl_addr \
968+ [i + ctl.offset]);
969+
970+ if (copy_to_user(argp, &ctl, sizeof(struct usrp_e_ctl16)))
971+ return -EFAULT;
972+
973+ } else
974+ return -EFAULT;
975+
976+ return 0;
977+}
978+
979+static int usrp_e_get_rb_info(unsigned long arg)
980+{
981+ struct usrp_e_ring_buffer_size_t __user *argp = (struct usrp_e_ring_buffer_size_t __user *) arg;
982+ int i;
983+
984+ if (copy_to_user(argp, &rb_size, sizeof(rb_size)))
985+ return -EFAULT;
986+
987+ return 0;
988+}
989+
990+static void usrp_e_spi_init()
991+{
992+ struct usrp_e_dev *p = usrp_e_devp;
993+
994+ p->ctl_spi = (struct spi_regs_wb *)(p->ctl_addr + CTL_SPI_BASE);
995+ p->ctl_spi->div = 64; /* 1 = Div by 4 (12.5 MHz) */
996+}
997+
998+static int usrp_e_spi_wait(void)
999+{
1000+ struct usrp_e_dev *p = usrp_e_devp;
1001+
1002+ while (p->ctl_spi->ctrl & UE_SPI_CTRL_GO_BSY) {
1003+ if (signal_pending(current)) {
1004+ printk(KERN_DEBUG "Signal received.\n");
1005+ set_current_state(TASK_RUNNING);
1006+ return -EINTR;
1007+ }
1008+ schedule();
1009+ }
1010+
1011+ return 0;
1012+}
1013+
1014+static int usrp_e_spi(unsigned long __user arg)
1015+{
1016+ struct usrp_e_dev *p = usrp_e_devp;
1017+ struct usrp_e_spi __user *argp = (struct usrp_e_spi __user *) arg;
1018+ struct usrp_e_spi spi_cmd;
1019+ int ctrl, ret;
1020+
1021+ if (copy_from_user(&spi_cmd, argp, sizeof(struct usrp_e_spi)))
1022+ return -EFAULT;
1023+
1024+ spi_cmd.flags &= (UE_SPI_CTRL_TXNEG | UE_SPI_CTRL_RXNEG);
1025+ ctrl = UE_SPI_CTRL_ASS | (UE_SPI_CTRL_CHAR_LEN_MASK & spi_cmd.length) \
1026+ | spi_cmd.flags;
1027+
1028+ ret = usrp_e_spi_wait();
1029+ if (ret < 0)
1030+ return ret;
1031+
1032+ p->ctl_spi->ss = spi_cmd.slave & 0xff;
1033+
1034+ p->ctl_spi->txrx0 = spi_cmd.data;
1035+
1036+ p->ctl_spi->ctrl = ctrl;
1037+ p->ctl_spi->ctrl = ctrl | UE_SPI_CTRL_GO_BSY;
1038+
1039+ if (spi_cmd.readback) {
1040+ usrp_e_spi_wait();
1041+ if (copy_to_user(&argp->data, &p->ctl_spi->txrx0,
1042+ sizeof(__u32)))
1043+ return -EFAULT;
1044+ else
1045+ return 0;
1046+ } else
1047+ return 0;
1048+
1049+}
1050+
1051+static void usrp_e_i2c_init()
1052+{
1053+ struct usrp_e_dev *p = usrp_e_devp;
1054+ int wb_div;
1055+
1056+ p->ctl_i2c = (struct i2c_regs_wb *)(p->ctl_addr + CTL_I2C_BASE);
1057+
1058+ writeb(0, &p->ctl_i2c->ctrl); /* disable core */
1059+
1060+ /* Assume wb_div is 4, deal with this later */
1061+ wb_div = 4;
1062+ if (wb_div > MAX_WB_DIV)
1063+ wb_div = MAX_WB_DIV;
1064+
1065+ writeb((prescalar_values[wb_div] & 0xff), &p->ctl_i2c->prescalar_lo);
1066+ writeb(((prescalar_values[wb_div] >> 8) & 0xff),
1067+ &p->ctl_i2c->prescalar_hi);
1068+ writeb(I2C_CTRL_EN, &p->ctl_i2c->ctrl); /* enable core */
1069+}
1070+
1071+static int usrp_e_i2c_wait(__u32 mask, int chk_ack)
1072+{
1073+ struct usrp_e_dev *p = usrp_e_devp;
1074+
1075+ while (readb(&p->ctl_i2c->cmd_status) & mask) {
1076+ if (signal_pending(current)) {
1077+ printk(KERN_DEBUG "Signal received.\n");
1078+ set_current_state(TASK_RUNNING);
1079+ return -EINTR;
1080+ }
1081+ schedule();
1082+ }
1083+
1084+ if (chk_ack) {
1085+ if ((readb(&p->ctl_i2c->cmd_status) & I2C_ST_RXACK) == 0)
1086+ return 1;
1087+ else
1088+ return 0;
1089+ }
1090+
1091+ return 0;
1092+}
1093+
1094+static int usrp_e_i2c(unsigned long arg, int direction)
1095+{
1096+ struct usrp_e_dev *p = usrp_e_devp;
1097+ struct usrp_e_i2c __user *argp = (struct usrp_e_i2c __user *) arg;
1098+ struct usrp_e_i2c tmp;
1099+ struct usrp_e_i2c *i2c_msg;
1100+ int ret, len, i;
1101+
1102+ if (copy_from_user(&tmp, argp, sizeof(struct usrp_e_i2c)))
1103+ return -EFAULT;
1104+
1105+ i2c_msg = kmalloc(sizeof(struct usrp_e_i2c) + tmp.len, GFP_KERNEL);
1106+ if (!i2c_msg)
1107+ return -ENOMEM;
1108+
1109+ if (copy_from_user(i2c_msg, argp,
1110+ (sizeof(struct usrp_e_i2c) + tmp.len)))
1111+ return -EFAULT;
1112+
1113+ if (direction) {
1114+ /* read */
1115+ if (i2c_msg->len == 0)
1116+ return 1;
1117+
1118+ usrp_e_i2c_wait(I2C_ST_BUSY, 0);
1119+
1120+ writeb(((i2c_msg->addr << 1) | 1), &p->ctl_i2c->data);
1121+ writeb((I2C_CMD_WR | I2C_CMD_START), &p->ctl_i2c->cmd_status);
1122+ ret = usrp_e_i2c_wait(I2C_ST_TIP, 1);
1123+ if (ret < 0) {
1124+ return ret;
1125+ } else if (ret == 0) {
1126+ writeb(I2C_CMD_STOP, &p->ctl_i2c->cmd_status);
1127+ return 2;
1128+ }
1129+
1130+ for (len = i2c_msg->len, i = 0; len > 0; i++, len--) {
1131+ writeb((I2C_CMD_RD | ((len == 1) ?
1132+ (I2C_CMD_NACK | I2C_CMD_STOP) : 0)),
1133+ &p->ctl_i2c->cmd_status);
1134+ usrp_e_i2c_wait(I2C_ST_TIP, 0);
1135+ i2c_msg->data[i] = readb(&p->ctl_i2c->data);
1136+ }
1137+ if (copy_to_user(argp, i2c_msg, (sizeof(struct usrp_e_i2c) +
1138+ tmp.len)))
1139+ return -EFAULT;
1140+ } else {
1141+ /* write */
1142+ usrp_e_i2c_wait(I2C_ST_BUSY, 0);
1143+ writeb(((i2c_msg->addr << 1) | 0), &p->ctl_i2c->data);
1144+ writeb((I2C_CMD_WR | I2C_CMD_START |
1145+ (i2c_msg->len == 0 ? I2C_CMD_STOP : 0)),
1146+ &p->ctl_i2c->cmd_status);
1147+ ret = usrp_e_i2c_wait(I2C_ST_TIP, 1);
1148+ if (ret < 0) {
1149+ return ret;
1150+ } else if (ret == 0) {
1151+ writeb(I2C_CMD_STOP, &p->ctl_i2c->cmd_status);
1152+ return 2;
1153+ }
1154+ for (len = i2c_msg->len, i = 0; len > 0; i++, len--) {
1155+ writeb(i2c_msg->data[i], &p->ctl_i2c->data);
1156+ writeb((I2C_CMD_WR | (len == 1 ? I2C_CMD_STOP : 0)),
1157+ &p->ctl_i2c->cmd_status);
1158+ ret = usrp_e_i2c_wait(I2C_ST_TIP, 1);
1159+ if (ret < 0) {
1160+ return ret;
1161+ } else if (ret == 0) {
1162+ writeb(I2C_CMD_STOP, &p->ctl_i2c->cmd_status);
1163+ return 2;
1164+ }
1165+ }
1166+
1167+ }
1168+
1169+
1170+ return 1;
1171+}
1172+
1173+static int usrp_e_ioctl(struct file *file,
1174+ unsigned int cmd, unsigned long arg)
1175+{
1176+
1177+ switch (cmd) {
1178+ case USRP_E_WRITE_CTL16:
1179+ return usrp_e_ctl16(arg, 0);
1180+
1181+ case USRP_E_READ_CTL16:
1182+ return usrp_e_ctl16(arg, 1);
1183+
1184+ case USRP_E_WRITE_CTL32:
1185+ return usrp_e_ctl32(arg, 0);
1186+
1187+ case USRP_E_READ_CTL32:
1188+ return usrp_e_ctl32(arg, 1);
1189+
1190+ case USRP_E_SPI:
1191+ return usrp_e_spi(arg);
1192+
1193+ case USRP_E_I2C_WRITE:
1194+ return usrp_e_i2c(arg, 0);
1195+
1196+ case USRP_E_I2C_READ:
1197+ return usrp_e_i2c(arg, 1);
1198+
1199+ case USRP_E_GET_RB_INFO:
1200+ return usrp_e_get_rb_info(arg);
1201+
1202+ default:
1203+ return -ENOTTY;
1204+ }
1205+
1206+ return 0;
1207+}
1208+
1209+static unsigned int usrp_e_poll(struct file *filp, poll_table *wait)
1210+{
1211+ unsigned int mask = 0;
1212+
1213+ poll_wait(filp, &data_received_queue, wait);
1214+ poll_wait(filp, &tx_rb_space_available, wait);
1215+
1216+ // Make sure write is active before sleeping
1217+ send_frame_to_fpga_start();
1218+
1219+ /* Make sure to read in case the rx ring buffer is full */
1220+ get_frame_from_fpga_start();
1221+
1222+ // This likely needs some locking. The pointer is incremented
1223+ // before the flag state is updated.
1224+
1225+ if (rx_rb_write == 0) {
1226+ if ((*rx_rb.rbi)[rb_size.num_rx_frames - 1].flags & RB_USER)
1227+ mask |= POLLIN | POLLRDNORM;
1228+ } else {
1229+ if ((*rx_rb.rbi)[rx_rb_write - 1].flags & RB_USER)
1230+ mask |= POLLIN | POLLRDNORM;
1231+ }
1232+
1233+ if (tx_rb_read == 0) {
1234+ if ((*tx_rb.rbi)[rb_size.num_tx_frames - 1].flags & RB_KERNEL)
1235+ mask |= POLLOUT | POLLWRNORM;
1236+ } else {
1237+ if ((*tx_rb.rbi)[tx_rb_read - 1].flags & RB_KERNEL)
1238+ mask |= POLLOUT | POLLWRNORM;
1239+ }
1240+
1241+ return mask;
1242+
1243+}
1244+
1245+/* The mmap code is based on code in af_packet.c */
1246+
1247+static void usrp_e_mm_open(struct vm_area_struct *vma)
1248+{
1249+
1250+ atomic_inc(&mapped);
1251+}
1252+
1253+static void usrp_e_mm_close(struct vm_area_struct *vma)
1254+{
1255+
1256+ atomic_dec(&mapped);
1257+}
1258+
1259+static const struct vm_operations_struct usrp_e_mmap_ops = {
1260+ .open = usrp_e_mm_open,
1261+ .close = usrp_e_mm_close,
1262+};
1263+
1264+static int usrp_e_mmap(struct file *filp, struct vm_area_struct *vma)
1265+{
1266+ unsigned long size, expected_size;
1267+ unsigned int i;
1268+ unsigned long start;
1269+ int err;
1270+ struct page *page;
1271+
1272+ printk("In mmap\n");
1273+
1274+ if (vma->vm_pgoff)
1275+ return -EINVAL;
1276+
1277+ /* Verify the user will map the entire tx and rx ring buffer space */
1278+ expected_size = (rb_size.num_rx_frames + rb_size.num_tx_frames) * (PAGE_SIZE >> 1)
1279+ + (rb_size.num_pages_rx_flags + rb_size.num_pages_tx_flags) * PAGE_SIZE;
1280+
1281+ size = vma->vm_end - vma->vm_start;
1282+ printk(KERN_DEBUG "Size = %d, expected sixe = %d\n", size, expected_size);
1283+
1284+ if (size != expected_size)
1285+ return -EINVAL;
1286+
1287+ start = vma->vm_start;
1288+
1289+ page = virt_to_page(rx_rb.rbi);
1290+ err = vm_insert_page(vma, start, page);
1291+ if (err)
1292+ return -EINVAL;
1293+
1294+ start += PAGE_SIZE;
1295+
1296+ for (i = 0; i < rx_rb.num_pages; ++i) {
1297+ struct page *page = virt_to_page((*rx_rb.pages)[i]);
1298+ err = vm_insert_page(vma, start, page);
1299+ if (err)
1300+ return -EINVAL;
1301+
1302+ start += PAGE_SIZE;
1303+ }
1304+
1305+ page = virt_to_page(tx_rb.rbi);
1306+ err = vm_insert_page(vma, start, page);
1307+ if (err)
1308+ return -EINVAL;
1309+
1310+ start += PAGE_SIZE;
1311+
1312+ for (i = 0; i < tx_rb.num_pages; ++i) {
1313+ struct page *page = virt_to_page((*tx_rb.pages)[i]);
1314+
1315+ err = vm_insert_page(vma, start, page);
1316+ if (err)
1317+ return err;
1318+
1319+ start += PAGE_SIZE;
1320+ }
1321+
1322+ vma->vm_ops = &usrp_e_mmap_ops;
1323+
1324+ return 0;
1325+}
1326+
1327+static const struct file_operations usrp_e_fops = {
1328+ .owner = THIS_MODULE,
1329+ .open = usrp_e_open,
1330+ .release = usrp_e_release,
1331+ .read = usrp_e_read,
1332+ .write = usrp_e_write,
1333+ .llseek = usrp_e_llseek,
1334+ .unlocked_ioctl = usrp_e_ioctl,
1335+ .poll = usrp_e_poll,
1336+ .mmap = usrp_e_mmap,
1337+};
1338+
1339+MODULE_VERSION("0.1");
1340+MODULE_ALIAS(DEVICE_NAME);
1341+MODULE_DESCRIPTION(DEVICE_NAME);
1342+MODULE_AUTHOR("Philip Balister <philip@opensdr.com>");
1343+MODULE_LICENSE("GPL v2");
1344+
1345+module_init(usrp_e_init);
1346+module_exit(usrp_e_cleanup);
1347+
1348+static irqreturn_t space_available_irqhandler(int irq, void *dev_id)
1349+{
1350+ int serviced = IRQ_NONE;
1351+
1352+#ifdef DEBUG_TX
1353+ gpio_set_value(22, 1);
1354+#endif
1355+
1356+// printk("Calling send_to_fpga_start from space_available irq\n");
1357+ send_frame_to_fpga_start();
1358+
1359+ serviced = IRQ_HANDLED;
1360+
1361+#ifdef DEBUG_TX
1362+ gpio_set_value(22, 0);
1363+#endif
1364+
1365+ return serviced;
1366+}
1367+
1368+static void usrp_rx_dma_irq(int ch, u16 stat, void *data)
1369+{
1370+
1371+#ifdef DEBUG_RX
1372+ gpio_set_value(23, 1);
1373+#endif
1374+
1375+ rx_dma_active = 0;
1376+
1377+ get_frame_from_fpga_finish();
1378+
1379+#ifdef DEBUG_RX
1380+ gpio_set_value(23, 0);
1381+#endif
1382+}
1383+
1384+static void usrp_tx_dma_irq(int ch, u16 stat, void *data)
1385+{
1386+
1387+#ifdef DEBUG_TX
1388+ gpio_set_value(23, 1);
1389+#endif
1390+ tx_dma_active = 0;
1391+
1392+ send_frame_to_fpga_finish();
1393+
1394+#ifdef DEBUG_TX
1395+ gpio_set_value(23, 0);
1396+#endif
1397+
1398+/* Save
1399+ gpio_set_value(21, 1);
1400+ gpio_set_value(21, 0);
1401+*/
1402+
1403+}
1404+
1405+static irqreturn_t data_ready_irqhandler(int irq, void *dev_id)
1406+{
1407+ int serviced = IRQ_NONE;
1408+
1409+#ifdef DEBUG_RX
1410+ gpio_set_value(22, 1);
1411+#endif
1412+
1413+ get_frame_from_fpga_start();
1414+
1415+ serviced = IRQ_HANDLED;
1416+
1417+#ifdef DEBUG_RX
1418+ gpio_set_value(22, 0);
1419+#endif
1420+ return serviced;
1421+}
1422+
1423+static int init_dma_controller()
1424+{
1425+ struct usrp_e_dev *p = usrp_e_devp;
1426+
1427+ rx_dma = kzalloc(sizeof(struct dma_data), GFP_KERNEL);
1428+ if (!rx_dma) {
1429+ printk(KERN_ERR "Failed to allocate memory for rx_dma struct.");
1430+ return -ENOMEM;
1431+ }
1432+
1433+ if (omap_request_dma(OMAP_DMA_NO_DEVICE, "usrp-e-rx",
1434+ usrp_rx_dma_irq, (void *) rx_dma, &rx_dma->ch)) {
1435+ printk(KERN_ERR "Could not get rx DMA channel for usrp_e\n");
1436+ return -ENOMEM;
1437+ }
1438+ printk(KERN_DEBUG "rx_dma->ch %d\n", rx_dma->ch);
1439+
1440+ rx_dma->phys_from = p->mem_base;
1441+
1442+ memset(&rx_dma->params, 0, sizeof(rx_dma->params));
1443+ rx_dma->params.data_type = OMAP_DMA_DATA_TYPE_S16;
1444+
1445+ rx_dma->params.src_amode = OMAP_DMA_AMODE_CONSTANT;
1446+ rx_dma->params.dst_amode = OMAP_DMA_AMODE_POST_INC;
1447+
1448+ rx_dma->params.src_start = p->mem_base;
1449+ rx_dma->params.dst_start = rx_dma->phys_to;
1450+
1451+ rx_dma->params.src_ei = 1;
1452+ rx_dma->params.src_fi = 1;
1453+ rx_dma->params.dst_ei = 1;
1454+ rx_dma->params.dst_fi = 1;
1455+
1456+ rx_dma->params.elem_count = 1024;
1457+ rx_dma->params.frame_count = 1;
1458+
1459+ rx_dma->params.read_prio = DMA_CH_PRIO_HIGH;
1460+ rx_dma->params.write_prio = DMA_CH_PRIO_LOW;
1461+
1462+ omap_set_dma_params(rx_dma->ch, &rx_dma->params);
1463+
1464+// Play with these with a real application
1465+//G omap_set_dma_src_burst_mode(rx_dma->ch, OMAP_DMA_DATA_BURST_16);
1466+// omap_set_dma_dest_burst_mode(rx_dma->ch, OMAP_DMA_DATA_BURST_16);
1467+
1468+#if 0 // Need to find implentations of the endian calls
1469+ omap_set_dma_src_endian_type(rx_dma->ch, OMAP_DMA_BIG_ENDIAN);
1470+ omap_set_dma_dst_endian_type(rx_dma->ch, OMAP_DMA_LITTLE_ENDIAN);
1471+#endif
1472+
1473+ tx_dma = kzalloc(sizeof(struct dma_data), GFP_KERNEL);
1474+ if (!tx_dma) {
1475+ printk(KERN_ERR "Failed to allocate memory for tx_dma struct.");
1476+ return -ENOMEM;
1477+ }
1478+
1479+ if (omap_request_dma(OMAP_DMA_NO_DEVICE, "usrp-e-tx",
1480+ usrp_tx_dma_irq, (void *) tx_dma, &tx_dma->ch)) {
1481+ printk(KERN_ERR "Could not get tx DMA channel for usrp_e\n");
1482+ return -ENOMEM;
1483+ }
1484+
1485+ printk(KERN_DEBUG "tx_dma->ch %d\n", tx_dma->ch);
1486+
1487+ tx_dma->phys_from = p->mem_base;
1488+
1489+ memset(&tx_dma->params, 0, sizeof(tx_dma->params));
1490+ tx_dma->params.data_type = OMAP_DMA_DATA_TYPE_S16;
1491+
1492+ tx_dma->params.src_amode = OMAP_DMA_AMODE_POST_INC;
1493+ tx_dma->params.dst_amode = OMAP_DMA_AMODE_CONSTANT;
1494+
1495+ tx_dma->params.src_start = tx_dma->phys_from;
1496+ tx_dma->params.dst_start = p->mem_base;
1497+
1498+ tx_dma->params.src_ei = 1;
1499+ tx_dma->params.src_fi = 1;
1500+ tx_dma->params.dst_ei = 1;
1501+ tx_dma->params.dst_fi = 1;
1502+
1503+ tx_dma->params.elem_count = 1024;
1504+ tx_dma->params.frame_count = 1;
1505+
1506+ tx_dma->params.read_prio = DMA_CH_PRIO_LOW;
1507+ tx_dma->params.write_prio = DMA_CH_PRIO_HIGH;
1508+
1509+ omap_set_dma_params(tx_dma->ch, &tx_dma->params);
1510+
1511+// Play with these with a real application
1512+//G omap_set_dma_src_burst_mode(tx_dma->ch, OMAP_DMA_DATA_BURST_16);
1513+// omap_set_dma_dest_burst_mode(tx_dma->ch, OMAP_DMA_DATA_BURST_16);
1514+
1515+ return 0;
1516+}
1517+
1518+static void release_dma_controller()
1519+{
1520+
1521+ omap_free_dma(rx_dma->ch);
1522+ omap_free_dma(tx_dma->ch);
1523+
1524+ kfree(rx_dma);
1525+ kfree(tx_dma);
1526+}
1527+
1528+static int get_frame_from_fpga_start()
1529+{
1530+ struct usrp_e_dev *p = usrp_e_devp;
1531+ struct ring_buffer_info *rbi = &(*rx_rb.rbi)[rx_rb_write];
1532+ struct ring_buffer_entry *rbe = &(*rx_rb.rbe)[rx_rb_write];
1533+ u16 elements_to_read;
1534+
1535+ /* Check for space available in the ring buffer */
1536+ /* If no space, drop data. A read call will restart dma transfers. */
1537+ if (((*rx_rb.rbi)[rx_rb_write].flags & RB_KERNEL) && (gpio_get_value(RX_DATA_READY_GPIO)) && !rx_dma_active && !shutting_down) {
1538+
1539+ rx_dma_active = 1;
1540+#ifdef DEBUG_RX
1541+ gpio_set_value(14, 1);
1542+#endif
1543+
1544+ elements_to_read = readw(p->ctl_addr + UE_REG_MISC_RX_LEN);
1545+
1546+ rbi->flags = RB_DMA_ACTIVE;
1547+
1548+ rbi->len = elements_to_read << 1;
1549+
1550+ omap_set_dma_dest_addr_size(rx_dma->ch, rbe->dma_addr,
1551+ elements_to_read);
1552+
1553+ dma_sync_single_for_device(NULL, rbe->dma_addr, SZ_2K, DMA_FROM_DEVICE);
1554+
1555+ omap_start_dma(rx_dma->ch);
1556+ }
1557+
1558+ return 0;
1559+}
1560+
1561+
1562+static int get_frame_from_fpga_finish()
1563+{
1564+ dma_sync_single_for_cpu(NULL, (*rx_rb.rbe)[rx_rb_write].dma_addr, SZ_2K, DMA_FROM_DEVICE);
1565+
1566+ (*rx_rb.rbi)[rx_rb_write].flags = RB_USER;
1567+ rx_rb_write++;
1568+ if (rx_rb_write == rb_size.num_rx_frames)
1569+ rx_rb_write = 0;
1570+
1571+ wake_up_interruptible(&data_received_queue);
1572+
1573+ rx_dma_active = 0;
1574+
1575+ get_frame_from_fpga_start();
1576+
1577+#ifdef DEBUG_RX
1578+ gpio_set_value(14, 0);
1579+#endif
1580+
1581+ return 0;
1582+}
1583+
1584+static int send_frame_to_fpga_start()
1585+{
1586+ struct usrp_e_dev *p = usrp_e_devp;
1587+ struct ring_buffer_info *rbi = &(*tx_rb.rbi)[tx_rb_read];
1588+ struct ring_buffer_entry *rbe = &(*tx_rb.rbe)[tx_rb_read];
1589+ u16 elements_to_write;
1590+
1591+// printk("In send_frame_to_fpga_start.\n");
1592+
1593+ /* Check if there is data to write to the FPGA, if so send it */
1594+ /* Otherwise, do nothing. Process is restarted by calls to write */
1595+ if (((*tx_rb.rbi)[tx_rb_read].flags & RB_USER) && !tx_dma_active && (gpio_get_value(TX_SPACE_AVAILABLE_GPIO)) && !shutting_down) {
1596+// printk("In send_frame_to_fpga_start, past if.\n");
1597+ tx_dma_active = 1;
1598+#ifdef DEBUG_TX
1599+ gpio_set_value(14, 1);
1600+#endif
1601+
1602+ elements_to_write = ((rbi->len) >> 1);
1603+
1604+ writew(elements_to_write, p->ctl_addr + UE_REG_MISC_TX_LEN);
1605+
1606+ rbi->flags = RB_DMA_ACTIVE;
1607+
1608+ omap_set_dma_src_addr_size(tx_dma->ch, rbe->dma_addr,
1609+ elements_to_write);
1610+
1611+ dma_sync_single_for_device(NULL, rbe->dma_addr, SZ_2K, DMA_TO_DEVICE);
1612+
1613+ omap_start_dma(tx_dma->ch);
1614+ }
1615+
1616+ return 0;
1617+}
1618+
1619+static int send_frame_to_fpga_finish()
1620+{
1621+
1622+ dma_sync_single_for_cpu(NULL, (*tx_rb.rbe)[tx_rb_read].dma_addr, SZ_2K, DMA_TO_DEVICE);
1623+
1624+ (*tx_rb.rbi)[tx_rb_read].flags = RB_KERNEL;
1625+
1626+ tx_rb_read++;
1627+ if (tx_rb_read == rb_size.num_tx_frames)
1628+ tx_rb_read = 0;
1629+
1630+ wake_up_interruptible(&tx_rb_space_available);
1631+
1632+ tx_dma_active = 0;
1633+
1634+ send_frame_to_fpga_start();
1635+
1636+#ifdef DEBUG_TX
1637+ gpio_set_value(14, 0);
1638+#endif
1639+
1640+ return 0;
1641+}
1642+
1643+static int alloc_ring_buffer(struct ring_buffer *rb,
1644+ unsigned int num_bufs, enum dma_data_direction direction)
1645+{
1646+ int i;
1647+
1648+ rb->rbi = __get_free_page(GFP_KERNEL | __GFP_COMP | __GFP_ZERO | __GFP_NOWARN);
1649+
1650+ rb->rbe = kzalloc(sizeof(struct ring_buffer_entry) * num_bufs, GFP_KERNEL);
1651+ if (!rb) {
1652+ printk(KERN_ERR "Failed to allocate memory for rb entries\n");
1653+ return -ENOMEM;
1654+ }
1655+
1656+ rb->num_pages = (num_bufs & 1) ? ((num_bufs + 1) / 2) : (num_bufs / 2);
1657+
1658+ rb->pages = kzalloc(sizeof(unsigned long) * rb->num_pages, GFP_KERNEL);
1659+ if (!(rb->pages)) {
1660+ printk(KERN_ERR "Failed to allocate memory for rb page entries\n");
1661+ return -ENOMEM;
1662+ }
1663+
1664+ for (i = 0; i < rb->num_pages; i++) {
1665+ (*rb->pages)[i] = __get_free_page(GFP_KERNEL | __GFP_DMA | __GFP_COMP | __GFP_ZERO | __GFP_NOWARN);
1666+
1667+ (*(rb->rbe))[i*2].frame_addr =
1668+ (*(rb->pages))[i];
1669+ (*(rb->rbe))[i*2 + 1].frame_addr =
1670+ ((*(rb->pages))[i] + SZ_2K);
1671+ if (!(*(rb->rbe))[i*2].frame_addr || !(*(rb->rbe))[i*2 + 1].frame_addr) {
1672+ printk(KERN_ERR "Failed to allocate memory dma buf\n");
1673+ return -ENOMEM;
1674+ }
1675+
1676+ (*(rb->rbe))[i*2].dma_addr = dma_map_single(NULL, (*(rb->rbe))[i*2].frame_addr, SZ_2K, direction);
1677+ (*(rb->rbe))[i*2 + 1].dma_addr = dma_map_single(NULL, (*(rb->rbe))[i*2 + 1].frame_addr, SZ_2K, direction);
1678+ if (!(*(rb->rbe))[i*2].dma_addr || !(*(rb->rbe))[i*2 + 1].dma_addr) {
1679+ printk(KERN_ERR "Failed to get physical address for dma buf\n");
1680+ return -ENOMEM;
1681+ }
1682+ }
1683+
1684+ return 0;
1685+}
1686+
1687+static void delete_ring_buffer(struct ring_buffer *rb,
1688+ unsigned int num_bufs, enum dma_data_direction direction)
1689+{
1690+ unsigned int i;
1691+ unsigned int num_pages;
1692+
1693+ printk(KERN_DEBUG "Entering delete_ring_buffer\n");
1694+
1695+ num_pages = (num_bufs & 1) ? ((num_bufs + 1) / 2) : (num_bufs / 2);
1696+
1697+ for (i = 0; i < num_pages; i++) {
1698+ dma_unmap_single(NULL, (*rb->rbe)[i*2].dma_addr, SZ_2K, direction);
1699+ dma_unmap_single(NULL, (*rb->rbe)[i*2 + 1].dma_addr, SZ_2K, direction);
1700+ free_page((*rb->pages)[i]);
1701+ }
1702+
1703+ free_page(rb->rbi);
1704+
1705+ kfree(rb->pages);
1706+ kfree(rb->rbe);
1707+
1708+ printk(KERN_DEBUG "Leaving delete_ring_buffer\n");
1709+}
1710+
1711+static int alloc_ring_buffers()
1712+{
1713+
1714+ if (alloc_ring_buffer(&tx_rb, rb_size.num_rx_frames, DMA_TO_DEVICE) < 0)
1715+ return -ENOMEM;
1716+ if (alloc_ring_buffer(&rx_rb, rb_size.num_tx_frames, DMA_FROM_DEVICE) < 0)
1717+ return -ENOMEM;
1718+
1719+ return 0;
1720+}
1721+
1722+static void init_ring_buffer(struct ring_buffer *rb, int num_bufs,
1723+ int initial_flags, enum dma_data_direction direction)
1724+{
1725+ int i;
1726+
1727+ for (i = 0; i < num_bufs; i++) {
1728+ dma_sync_single_for_device(NULL, (*rb->rbe)[i].dma_addr,
1729+ SZ_2K, direction);
1730+ dma_sync_single_for_cpu(NULL, (*rb->rbe)[i].dma_addr,
1731+ SZ_2K, direction);
1732+ (*rb->rbi)[i].flags = initial_flags;
1733+ }
1734+
1735+}
1736+
1737+#if 0
1738+static int tx_dma_func(void *data)
1739+{
1740+ int ret;
1741+ struct sched_param s = { .sched_priority = 1};
1742+
1743+ printk(KERN_DEBUG "In tx_dma_func\n");
1744+
1745+ allow_signal(SIGSTOP);
1746+
1747+ sched_setscheduler(current, SCHED_FIFO, &s);
1748+
1749+ while (!kthread_should_stop() && !closing_driver) {
1750+
1751+ if (!((*tx_rb.rbe)[tx_rb_read].flags & RB_USER)) {
1752+ tx_dma_waiting_for_data = 1;
1753+ ret = wait_event_interruptible(received_data_from_user,
1754+ (*tx_rb.rbe)[tx_rb_read].flags & RB_USER);
1755+ if (ret) {
1756+ printk(KERN_DEBUG
1757+ "tx_dma_func received signal %d\n",
1758+ ret);
1759+ if (closing_driver)
1760+ break;
1761+
1762+ }
1763+ tx_dma_waiting_for_data = 0;
1764+ }
1765+
1766+ if (wait_event_interruptible(space_available_queue,
1767+ gpio_get_value(TX_SPACE_AVAILABLE_GPIO))) {
1768+ printk(KERN_DEBUG "tx_dma received signal waiting for space.\n");
1769+ if (closing_driver)
1770+ break;
1771+ }
1772+
1773+ if (send_frame_to_fpga(&(*tx_rb.rbe)[tx_rb_read]) != 0) {
1774+ printk(KERN_DEBUG "send_frame received signal.\n");
1775+ if (closing_driver)
1776+ break;
1777+ }
1778+
1779+ (*tx_rb.rbe)[tx_rb_read].flags = RB_KERNEL;
1780+
1781+ tx_rb_read++;
1782+ if (tx_rb_read == RB_SIZE)
1783+ tx_rb_read = 0;
1784+
1785+#if 0
1786+ if (waiting_for_space_in_tx_rb)
1787+#endif
1788+ wake_up_interruptible(&tx_rb_space_queue);
1789+
1790+ }
1791+ return 0;
1792+}
1793+#endif
1794diff --git a/include/linux/usrp_e.h b/include/linux/usrp_e.h
1795new file mode 100644
1796index 0000000..e52f709
1797--- /dev/null
1798+++ b/include/linux/usrp_e.h
1799@@ -0,0 +1,87 @@
1800+
1801+/*
1802+ * Copyright (C) 2010 Ettus Research, LLC
1803+ *
1804+ * Written by Philip Balister <philip@opensdr.com>
1805+ *
1806+ * This program is free software; you can redistribute it and/or modify
1807+ * it under the terms of the GNU General Public License as published by
1808+ * the Free Software Foundation; either version 2 of the License, or
1809+ * (at your option) any later version.
1810+ */
1811+
1812+#ifndef __USRP_E_H
1813+#define __USRP_E_H
1814+
1815+#include <linux/types.h>
1816+#include <linux/ioctl.h>
1817+
1818+struct usrp_e_ctl16 {
1819+ __u32 offset;
1820+ __u32 count;
1821+ __u16 buf[20];
1822+};
1823+
1824+struct usrp_e_ctl32 {
1825+ __u32 offset;
1826+ __u32 count;
1827+ __u32 buf[10];
1828+};
1829+
1830+/* SPI interface */
1831+
1832+#define UE_SPI_TXONLY 0
1833+#define UE_SPI_TXRX 1
1834+
1835+/* Defines for spi ctrl register */
1836+#define UE_SPI_CTRL_TXNEG (BIT(10))
1837+#define UE_SPI_CTRL_RXNEG (BIT(9))
1838+
1839+#define UE_SPI_PUSH_RISE 0
1840+#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG
1841+#define UE_SPI_LATCH_RISE 0
1842+#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG
1843+
1844+struct usrp_e_spi {
1845+ __u8 readback;
1846+ __u32 slave;
1847+ __u32 data;
1848+ __u32 length;
1849+ __u32 flags;
1850+};
1851+
1852+struct usrp_e_i2c {
1853+ __u8 addr;
1854+ __u32 len;
1855+ __u8 data[];
1856+};
1857+
1858+#define USRP_E_IOC_MAGIC 'u'
1859+#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16)
1860+#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16)
1861+#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32)
1862+#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32)
1863+#define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi)
1864+#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c)
1865+#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c)
1866+#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t)
1867+
1868+/* Flag defines */
1869+#define RB_USER (BIT(0))
1870+#define RB_KERNEL (BIT(1))
1871+#define RB_OVERRUN (BIT(2))
1872+#define RB_DMA_ACTIVE (BIT(3))
1873+
1874+struct ring_buffer_info {
1875+ int flags;
1876+ int len;
1877+};
1878+
1879+struct usrp_e_ring_buffer_size_t {
1880+ int num_pages_rx_flags;
1881+ int num_rx_frames;
1882+ int num_pages_tx_flags;
1883+ int num_tx_frames;
1884+};
1885+
1886+#endif
1887--
18881.6.6.1
1889
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-28 10:09:37 +0000