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Diffstat (limited to 'extras/recipes-kernel/linux/linux-omap/media/0036-v4l-Add-remaining-RAW10-patterns-w-DPCM-pixel-code-v.patch')
-rw-r--r--extras/recipes-kernel/linux/linux-omap/media/0036-v4l-Add-remaining-RAW10-patterns-w-DPCM-pixel-code-v.patch48
1 files changed, 48 insertions, 0 deletions
diff --git a/extras/recipes-kernel/linux/linux-omap/media/0036-v4l-Add-remaining-RAW10-patterns-w-DPCM-pixel-code-v.patch b/extras/recipes-kernel/linux/linux-omap/media/0036-v4l-Add-remaining-RAW10-patterns-w-DPCM-pixel-code-v.patch
new file mode 100644
index 00000000..ec6c332f
--- /dev/null
+++ b/extras/recipes-kernel/linux/linux-omap/media/0036-v4l-Add-remaining-RAW10-patterns-w-DPCM-pixel-code-v.patch
@@ -0,0 +1,48 @@
1From a63be84f54298581d51efb8a4745747ca17a9d0d Mon Sep 17 00:00:00 2001
2From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
3Date: Fri, 3 Sep 2010 10:47:25 +0200
4Subject: [PATCH 36/43] v4l: Add remaining RAW10 patterns w DPCM pixel code variants
5
6This adds following formats:
7- V4L2_MBUS_FMT_SRGGB10_1X10
8- V4L2_MBUS_FMT_SGBRG10_1X10
9- V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8
10- V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8
11- V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8
12
13Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
14Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
15---
16 include/linux/v4l2-mediabus.h | 7 ++++++-
17 1 files changed, 6 insertions(+), 1 deletions(-)
18
19diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h
20index c4caca3..5c64924 100644
21--- a/include/linux/v4l2-mediabus.h
22+++ b/include/linux/v4l2-mediabus.h
23@@ -67,16 +67,21 @@ enum v4l2_mbus_pixelcode {
24 V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
25 V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
26
27- /* Bayer - next is 0x300b */
28+ /* Bayer - next is 0x3010 */
29 V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
30 V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
31+ V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b,
32+ V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c,
33 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009,
34+ V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8 = 0x300d,
35 V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003,
36 V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004,
37 V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005,
38 V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006,
39 V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007,
40+ V4L2_MBUS_FMT_SGBRG10_1X10 = 0x300e,
41 V4L2_MBUS_FMT_SGRBG10_1X10 = 0x300a,
42+ V4L2_MBUS_FMT_SRGGB10_1X10 = 0x300f,
43 V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008,
44 };
45
46--
471.6.6.1
48