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-rw-r--r--extras/recipes-kernel/linux/linux-omap-2.6.39/camera/0001-Add-driver-for-Aptina-Micron-mt9p031-sensor.patch859
1 files changed, 859 insertions, 0 deletions
diff --git a/extras/recipes-kernel/linux/linux-omap-2.6.39/camera/0001-Add-driver-for-Aptina-Micron-mt9p031-sensor.patch b/extras/recipes-kernel/linux/linux-omap-2.6.39/camera/0001-Add-driver-for-Aptina-Micron-mt9p031-sensor.patch
new file mode 100644
index 00000000..cf9e116d
--- /dev/null
+++ b/extras/recipes-kernel/linux/linux-omap-2.6.39/camera/0001-Add-driver-for-Aptina-Micron-mt9p031-sensor.patch
@@ -0,0 +1,859 @@
1From e630a914bf14bf190feaf4a2cc57f6b27c4024e1 Mon Sep 17 00:00:00 2001
2From: Javier Martin <javier.martin@vista-silicon.com>
3Date: Wed, 1 Jun 2011 17:36:48 +0200
4Subject: [PATCH 1/3] Add driver for Aptina (Micron) mt9p031 sensor.
5
6Clock frequency of 57MHz used in previous version was wrong since
7when VDD_IO is 1.8V it can only support 48MHz.
8
9Two new platform flags have been added:
10
11- vdd_io: indicates whether the chip is powered with 1.8 or 2.8 VDD_IO.
12So that it can use the maximum allowed frequency.
13- version: monochrome and color versions of the chip have exactly
14the same ID, so the only way to select one of them is through
15platform data.
16
17Internal PLL is now used to generate PIXCLK depending on VDD_IO.
18
19Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
20---
21 drivers/media/video/Kconfig | 7 +
22 drivers/media/video/Makefile | 1 +
23 drivers/media/video/mt9p031.c | 763 +++++++++++++++++++++++++++++++++++++++++
24 include/media/mt9p031.h | 23 ++
25 4 files changed, 794 insertions(+), 0 deletions(-)
26 create mode 100644 drivers/media/video/mt9p031.c
27 create mode 100644 include/media/mt9p031.h
28
29diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
30index 00f51dd..cb87e35 100644
31--- a/drivers/media/video/Kconfig
32+++ b/drivers/media/video/Kconfig
33@@ -329,6 +329,13 @@ config VIDEO_OV7670
34 OV7670 VGA camera. It currently only works with the M88ALP01
35 controller.
36
37+config VIDEO_MT9P031
38+ tristate "Aptina MT9P031 support"
39+ depends on I2C && VIDEO_V4L2
40+ ---help---
41+ This is a Video4Linux2 sensor-level driver for the Aptina
42+ (Micron) mt9p031 5 Mpixel camera.
43+
44 config VIDEO_MT9V011
45 tristate "Micron mt9v011 sensor support"
46 depends on I2C && VIDEO_V4L2
47diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
48index ace5d8b..912b29b 100644
49--- a/drivers/media/video/Makefile
50+++ b/drivers/media/video/Makefile
51@@ -65,6 +65,7 @@ obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
52 obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
53 obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
54 obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
55+obj-$(CONFIG_VIDEO_MT9P031) += mt9p031.o
56 obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o
57 obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
58 obj-$(CONFIG_VIDEO_NOON010PC30) += noon010pc30.o
59diff --git a/drivers/media/video/mt9p031.c b/drivers/media/video/mt9p031.c
60new file mode 100644
61index 0000000..cd830b1
62--- /dev/null
63+++ b/drivers/media/video/mt9p031.c
64@@ -0,0 +1,763 @@
65+/*
66+ * Driver for MT9P031 CMOS Image Sensor from Aptina
67+ *
68+ * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com>
69+ *
70+ * Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
71+ *
72+ * Based on the MT9V032 driver and Bastian Hecht's code.
73+ *
74+ * This program is free software; you can redistribute it and/or modify
75+ * it under the terms of the GNU General Public License version 2 as
76+ * published by the Free Software Foundation.
77+ */
78+
79+#include <linux/delay.h>
80+#include <linux/device.h>
81+#include <linux/i2c.h>
82+#include <linux/log2.h>
83+#include <linux/pm.h>
84+#include <linux/slab.h>
85+#include <media/v4l2-subdev.h>
86+#include <linux/videodev2.h>
87+
88+#include <media/mt9p031.h>
89+#include <media/v4l2-chip-ident.h>
90+#include <media/v4l2-subdev.h>
91+#include <media/v4l2-device.h>
92+
93+#define MT9P031_EXTCLK_FREQ 20000000
94+
95+#define MT9P031_CHIP_VERSION 0x00
96+#define MT9P031_CHIP_VERSION_VALUE 0x1801
97+#define MT9P031_ROW_START 0x01
98+#define MT9P031_ROW_START_MIN 1
99+#define MT9P031_ROW_START_MAX 2004
100+#define MT9P031_ROW_START_DEF 54
101+#define MT9P031_COLUMN_START 0x02
102+#define MT9P031_COLUMN_START_MIN 1
103+#define MT9P031_COLUMN_START_MAX 2750
104+#define MT9P031_COLUMN_START_DEF 16
105+#define MT9P031_WINDOW_HEIGHT 0x03
106+#define MT9P031_WINDOW_HEIGHT_MIN 2
107+#define MT9P031_WINDOW_HEIGHT_MAX 2003
108+#define MT9P031_WINDOW_HEIGHT_DEF 2003
109+#define MT9P031_WINDOW_WIDTH 0x04
110+#define MT9P031_WINDOW_WIDTH_MIN 18
111+#define MT9P031_WINDOW_WIDTH_MAX 2751
112+#define MT9P031_WINDOW_WIDTH_DEF 2751
113+#define MT9P031_H_BLANKING 0x05
114+#define MT9P031_H_BLANKING_VALUE 0
115+#define MT9P031_V_BLANKING 0x06
116+#define MT9P031_V_BLANKING_VALUE 25
117+#define MT9P031_OUTPUT_CONTROL 0x07
118+#define MT9P031_OUTPUT_CONTROL_CEN 2
119+#define MT9P031_OUTPUT_CONTROL_SYN 1
120+#define MT9P031_SHUTTER_WIDTH_UPPER 0x08
121+#define MT9P031_SHUTTER_WIDTH 0x09
122+#define MT9P031_PLL_CONTROL 0x10
123+#define MT9P031_PLL_CONTROL_PWROFF 0x0050
124+#define MT9P031_PLL_CONTROL_PWRON 0x0051
125+#define MT9P031_PLL_CONTROL_USEPLL 0x0052
126+#define MT9P031_PLL_CONFIG_1 0x11
127+#define MT9P031_PLL_CONFIG_1_M_48MHZ 0x5000
128+#define MT9P031_PLL_CONFIG_1_N_48MHZ 0x05
129+#define MT9P031_PLL_CONFIG_1_M_96MHZ 0x3600
130+#define MT9P031_PLL_CONFIG_1_N_96MHZ 0x05
131+#define MT9P031_PLL_CONFIG_2 0x12
132+#define MT9P031_PLL_CONFIG_2_P1_48MHZ 5
133+#define MT9P031_PLL_CONFIG_2_P1_96MHZ 2
134+#define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
135+#define MT9P031_FRAME_RESTART 0x0b
136+#define MT9P031_SHUTTER_DELAY 0x0c
137+#define MT9P031_RST 0x0d
138+#define MT9P031_RST_ENABLE 1
139+#define MT9P031_RST_DISABLE 0
140+#define MT9P031_READ_MODE_1 0x1e
141+#define MT9P031_READ_MODE_2 0x20
142+#define MT9P031_READ_MODE_2_ROW_MIR 0x8000
143+#define MT9P031_READ_MODE_2_COL_MIR 0x4000
144+#define MT9P031_ROW_ADDRESS_MODE 0x22
145+#define MT9P031_COLUMN_ADDRESS_MODE 0x23
146+#define MT9P031_GLOBAL_GAIN 0x35
147+
148+struct mt9p031 {
149+ struct v4l2_subdev subdev;
150+ struct media_pad pad;
151+ struct v4l2_rect rect; /* Sensor window */
152+ struct v4l2_mbus_framefmt format;
153+ struct mt9p031_platform_data *pdata;
154+ struct mutex power_lock; /* lock to protect power_count */
155+ int power_count;
156+ u16 xskip;
157+ u16 yskip;
158+ /* cache register values */
159+ u16 output_control;
160+};
161+
162+static struct mt9p031 *to_mt9p031(const struct i2c_client *client)
163+{
164+ return container_of(i2c_get_clientdata(client), struct mt9p031, subdev);
165+}
166+
167+static int reg_read(struct i2c_client *client, const u8 reg)
168+{
169+ s32 data = i2c_smbus_read_word_data(client, reg);
170+ return data < 0 ? data : swab16(data);
171+}
172+
173+static int reg_write(struct i2c_client *client, const u8 reg,
174+ const u16 data)
175+{
176+ return i2c_smbus_write_word_data(client, reg, swab16(data));
177+}
178+
179+static int mt9p031_set_output_control(struct mt9p031 *mt9p031, u16 clear,
180+ u16 set)
181+{
182+ struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
183+ u16 value = (mt9p031->output_control & ~clear) | set;
184+ int ret;
185+
186+ ret = reg_write(client, MT9P031_OUTPUT_CONTROL, value);
187+ if (ret < 0)
188+ return ret;
189+ mt9p031->output_control = value;
190+ return 0;
191+}
192+
193+static int mt9p031_reset(struct i2c_client *client)
194+{
195+ struct mt9p031 *mt9p031 = to_mt9p031(client);
196+ int ret;
197+
198+ /* Disable chip output, synchronous option update */
199+ ret = reg_write(client, MT9P031_RST, MT9P031_RST_ENABLE);
200+ if (ret < 0)
201+ return ret;
202+ ret = reg_write(client, MT9P031_RST, MT9P031_RST_DISABLE);
203+ if (ret < 0)
204+ return ret;
205+ return mt9p031_set_output_control(mt9p031,
206+ MT9P031_OUTPUT_CONTROL_CEN, 0);
207+}
208+
209+static int mt9p031_power_on(struct mt9p031 *mt9p031)
210+{
211+ struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
212+ int ret;
213+
214+ /* Ensure RESET_BAR is low */
215+ if (mt9p031->pdata->reset) {
216+ mt9p031->pdata->reset(&mt9p031->subdev, 1);
217+ msleep(1);
218+ }
219+ /* Emable clock */
220+ if (mt9p031->pdata->set_xclk)
221+ mt9p031->pdata->set_xclk(&mt9p031->subdev, MT9P031_EXTCLK_FREQ);
222+ /* Now RESET_BAR must be high */
223+ if (mt9p031->pdata->reset) {
224+ mt9p031->pdata->reset(&mt9p031->subdev, 0);
225+ msleep(1);
226+ }
227+ /* soft reset */
228+ ret = mt9p031_reset(client);
229+ if (ret < 0) {
230+ dev_err(&client->dev, "Failed to reset the camera\n");
231+ return ret;
232+ }
233+ return 0;
234+}
235+
236+static void mt9p031_power_off(struct mt9p031 *mt9p031)
237+{
238+ if (mt9p031->pdata->reset) {
239+ mt9p031->pdata->reset(&mt9p031->subdev, 1);
240+ msleep(1);
241+ }
242+ if (mt9p031->pdata->set_xclk)
243+ mt9p031->pdata->set_xclk(&mt9p031->subdev, 0);
244+}
245+
246+static int mt9p031_enum_mbus_code(struct v4l2_subdev *sd,
247+ struct v4l2_subdev_fh *fh,
248+ struct v4l2_subdev_mbus_code_enum *code)
249+{
250+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
251+
252+ if (code->pad || code->index)
253+ return -EINVAL;
254+
255+ code->code = mt9p031->format.code;
256+ return 0;
257+}
258+
259+static struct v4l2_mbus_framefmt *mt9p031_get_pad_format(
260+ struct mt9p031 *mt9p031,
261+ struct v4l2_subdev_fh *fh,
262+ unsigned int pad, u32 which)
263+{
264+ switch (which) {
265+ case V4L2_SUBDEV_FORMAT_TRY:
266+ return v4l2_subdev_get_try_format(fh, pad);
267+ case V4L2_SUBDEV_FORMAT_ACTIVE:
268+ return &mt9p031->format;
269+ default:
270+ return NULL;
271+ }
272+}
273+
274+static struct v4l2_rect *mt9p031_get_pad_crop(struct mt9p031 *mt9p031,
275+ struct v4l2_subdev_fh *fh, unsigned int pad, u32 which)
276+{
277+ switch (which) {
278+ case V4L2_SUBDEV_FORMAT_TRY:
279+ return v4l2_subdev_get_try_crop(fh, pad);
280+ case V4L2_SUBDEV_FORMAT_ACTIVE:
281+ return &mt9p031->rect;
282+ default:
283+ return NULL;
284+ }
285+}
286+
287+static int mt9p031_get_crop(struct v4l2_subdev *sd,
288+ struct v4l2_subdev_fh *fh,
289+ struct v4l2_subdev_crop *crop)
290+{
291+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
292+ struct v4l2_rect *rect = mt9p031_get_pad_crop(mt9p031, fh, crop->pad,
293+ crop->which);
294+ if (!rect)
295+ return -EINVAL;
296+
297+ crop->rect = *rect;
298+
299+ return 0;
300+}
301+
302+static u16 mt9p031_skip_for_crop(s32 source, s32 *target, s32 max_skip)
303+{
304+ unsigned int skip;
305+
306+ if (source - source / 4 < *target) {
307+ *target = source;
308+ return 1;
309+ }
310+
311+ skip = DIV_ROUND_CLOSEST(source, *target);
312+ if (skip > max_skip)
313+ skip = max_skip;
314+ *target = 2 * DIV_ROUND_UP(source, 2 * skip);
315+
316+ return skip;
317+}
318+
319+static int mt9p031_set_params(struct i2c_client *client,
320+ struct v4l2_rect *rect, u16 xskip, u16 yskip)
321+{
322+ struct mt9p031 *mt9p031 = to_mt9p031(client);
323+ int ret;
324+ u16 xbin, ybin;
325+ const u16 hblank = MT9P031_H_BLANKING_VALUE,
326+ vblank = MT9P031_V_BLANKING_VALUE;
327+ __s32 left;
328+
329+ /*
330+ * TODO: Attention! When implementing horizontal flipping, adjust
331+ * alignment according to R2 "Column Start" description in the datasheet
332+ */
333+ if (xskip & 1) {
334+ xbin = 1;
335+ left = rect->left & (~3);
336+ } else if (xskip & 2) {
337+ xbin = 2;
338+ left = rect->left & (~7);
339+ } else {
340+ xbin = 4;
341+ left = rect->left & (~15);
342+ }
343+ ybin = min(yskip, (u16)4);
344+
345+ /* Disable register update, reconfigure atomically */
346+ ret = mt9p031_set_output_control(mt9p031, 0,
347+ MT9P031_OUTPUT_CONTROL_SYN);
348+ if (ret < 0)
349+ return ret;
350+
351+ dev_dbg(&client->dev, "skip %u:%u, rect %ux%u@%u:%u\n",
352+ xskip, yskip, rect->width, rect->height, rect->left, rect->top);
353+
354+ /* Blanking and start values - default... */
355+ ret = reg_write(client, MT9P031_H_BLANKING, hblank);
356+ if (ret < 0)
357+ return ret;
358+ ret = reg_write(client, MT9P031_V_BLANKING, vblank);
359+ if (ret < 0)
360+ return ret;
361+
362+ ret = reg_write(client, MT9P031_COLUMN_ADDRESS_MODE,
363+ ((xbin - 1) << 4) | (xskip - 1));
364+ if (ret < 0)
365+ return ret;
366+ ret = reg_write(client, MT9P031_ROW_ADDRESS_MODE,
367+ ((ybin - 1) << 4) | (yskip - 1));
368+ if (ret < 0)
369+ return ret;
370+
371+ dev_dbg(&client->dev, "new physical left %u, top %u\n",
372+ rect->left, rect->top);
373+
374+ ret = reg_write(client, MT9P031_COLUMN_START,
375+ rect->left);
376+ if (ret < 0)
377+ return ret;
378+ ret = reg_write(client, MT9P031_ROW_START,
379+ rect->top);
380+ if (ret < 0)
381+ return ret;
382+
383+ ret = reg_write(client, MT9P031_WINDOW_WIDTH,
384+ rect->width - 1);
385+ if (ret < 0)
386+ return ret;
387+ ret = reg_write(client, MT9P031_WINDOW_HEIGHT,
388+ rect->height - 1);
389+ if (ret < 0)
390+ return ret;
391+
392+ /* Re-enable register update, commit all changes */
393+ ret = mt9p031_set_output_control(mt9p031,
394+ MT9P031_OUTPUT_CONTROL_SYN, 0);
395+ if (ret < 0)
396+ return ret;
397+
398+ mt9p031->xskip = xskip;
399+ mt9p031->yskip = yskip;
400+ return ret;
401+}
402+
403+static int mt9p031_set_crop(struct v4l2_subdev *sd,
404+ struct v4l2_subdev_fh *fh,
405+ struct v4l2_subdev_crop *crop)
406+{
407+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
408+ struct v4l2_mbus_framefmt *f;
409+ struct v4l2_rect *c;
410+ struct v4l2_rect rect;
411+ u16 xskip, yskip;
412+ s32 width, height;
413+
414+ dev_dbg(mt9p031->subdev.v4l2_dev->dev, "%s(%ux%u@%u:%u : %u)\n",
415+ __func__, crop->rect.width, crop->rect.height,
416+ crop->rect.left, crop->rect.top, crop->which);
417+
418+ /*
419+ * Clamp the crop rectangle boundaries and align them to a multiple of 2
420+ * pixels.
421+ */
422+ rect.width = ALIGN(clamp(crop->rect.width,
423+ MT9P031_WINDOW_WIDTH_MIN,
424+ MT9P031_WINDOW_WIDTH_MAX), 2);
425+ rect.height = ALIGN(clamp(crop->rect.height,
426+ MT9P031_WINDOW_HEIGHT_MIN,
427+ MT9P031_WINDOW_HEIGHT_MAX), 2);
428+ rect.left = ALIGN(clamp(crop->rect.left,
429+ MT9P031_COLUMN_START_MIN,
430+ MT9P031_COLUMN_START_MAX), 2);
431+ rect.top = ALIGN(clamp(crop->rect.top,
432+ MT9P031_ROW_START_MIN,
433+ MT9P031_ROW_START_MAX), 2);
434+
435+ c = mt9p031_get_pad_crop(mt9p031, fh, crop->pad, crop->which);
436+
437+ if (rect.width != c->width || rect.height != c->height) {
438+ /*
439+ * Reset the output image size if the crop rectangle size has
440+ * been modified.
441+ */
442+ f = mt9p031_get_pad_format(mt9p031, fh, crop->pad,
443+ crop->which);
444+ width = f->width;
445+ height = f->height;
446+
447+ xskip = mt9p031_skip_for_crop(rect.width, &width, 7);
448+ yskip = mt9p031_skip_for_crop(rect.height, &height, 8);
449+ } else {
450+ xskip = mt9p031->xskip;
451+ yskip = mt9p031->yskip;
452+ f = NULL;
453+ }
454+ if (f) {
455+ f->width = width;
456+ f->height = height;
457+ }
458+
459+ *c = rect;
460+ crop->rect = rect;
461+
462+ mt9p031->xskip = xskip;
463+ mt9p031->yskip = yskip;
464+ mt9p031->rect = *c;
465+ return 0;
466+}
467+
468+static int mt9p031_get_format(struct v4l2_subdev *sd,
469+ struct v4l2_subdev_fh *fh,
470+ struct v4l2_subdev_format *fmt)
471+{
472+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
473+
474+ fmt->format =
475+ *mt9p031_get_pad_format(mt9p031, fh, fmt->pad, fmt->which);
476+ return 0;
477+}
478+
479+static u16 mt9p031_skip_for_scale(s32 *source, s32 target,
480+ s32 max_skip, s32 max)
481+{
482+ unsigned int skip;
483+
484+ if (*source - *source / 4 < target) {
485+ *source = target;
486+ return 1;
487+ }
488+
489+ skip = min(max, *source + target / 2) / target;
490+ if (skip > max_skip)
491+ skip = max_skip;
492+ *source = target * skip;
493+
494+ return skip;
495+}
496+
497+static int mt9p031_set_format(struct v4l2_subdev *sd,
498+ struct v4l2_subdev_fh *fh,
499+ struct v4l2_subdev_format *format)
500+{
501+ struct v4l2_mbus_framefmt *__format;
502+ struct v4l2_rect *__crop, rect;
503+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
504+ unsigned int width;
505+ unsigned int height;
506+ u16 xskip, yskip;
507+
508+ __crop = mt9p031_get_pad_crop(mt9p031, fh, format->pad, format->which);
509+
510+ width = clamp_t(int, ALIGN(format->format.width, 2), 2,
511+ MT9P031_WINDOW_WIDTH_MAX);
512+ height = clamp_t(int, ALIGN(format->format.height, 2), 2,
513+ MT9P031_WINDOW_HEIGHT_MAX);
514+
515+ rect.width = __crop->width;
516+ rect.height = __crop->height;
517+
518+ xskip = mt9p031_skip_for_scale(&rect.width, width, 7,
519+ MT9P031_WINDOW_WIDTH_MAX);
520+ if (rect.width + __crop->left > MT9P031_WINDOW_WIDTH_MAX)
521+ rect.left = (MT9P031_WINDOW_WIDTH_MAX - rect.width) / 2;
522+ else
523+ rect.left = __crop->left;
524+ yskip = mt9p031_skip_for_scale(&rect.height, height, 8,
525+ MT9P031_WINDOW_HEIGHT_MAX);
526+ if (rect.height + __crop->top > MT9P031_WINDOW_HEIGHT_MAX)
527+ rect.top = (MT9P031_WINDOW_HEIGHT_MAX - rect.height) / 2;
528+ else
529+ rect.top = __crop->top;
530+
531+ dev_dbg(mt9p031->subdev.v4l2_dev->dev, "%s(%ux%u : %u)\n", __func__,
532+ width, height, format->which);
533+ if (__crop)
534+ *__crop = rect;
535+
536+ __format = mt9p031_get_pad_format(mt9p031, fh, format->pad,
537+ format->which);
538+ __format->width = width;
539+ __format->height = height;
540+ format->format = *__format;
541+
542+ mt9p031->xskip = xskip;
543+ mt9p031->yskip = yskip;
544+ mt9p031->rect = *__crop;
545+ return 0;
546+}
547+
548+static int mt9p031_pll_enable(struct i2c_client *client)
549+{
550+ struct mt9p031 *mt9p031 = to_mt9p031(client);
551+ int ret;
552+
553+ ret = reg_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWRON);
554+ if (ret < 0)
555+ return ret;
556+
557+ /* Always set the maximum frequency allowed by VDD_IO */
558+ if (mt9p031->pdata->vdd_io == MT9P031_VDD_IO_2V8) {
559+ ret = reg_write(client, MT9P031_PLL_CONFIG_1,
560+ MT9P031_PLL_CONFIG_1_M_96MHZ |
561+ MT9P031_PLL_CONFIG_1_N_96MHZ);
562+ if (ret < 0)
563+ return ret;
564+ ret = reg_write(client, MT9P031_PLL_CONFIG_2,
565+ MT9P031_PLL_CONFIG_2_P1_96MHZ);
566+ if (ret < 0)
567+ return ret;
568+ } else {
569+ ret = reg_write(client, MT9P031_PLL_CONFIG_1,
570+ MT9P031_PLL_CONFIG_1_M_48MHZ |
571+ MT9P031_PLL_CONFIG_1_N_48MHZ);
572+ if (ret < 0)
573+ return ret;
574+ ret = reg_write(client, MT9P031_PLL_CONFIG_2,
575+ MT9P031_PLL_CONFIG_2_P1_48MHZ);
576+ if (ret < 0)
577+ return ret;
578+ }
579+ mdelay(1);
580+ ret = reg_write(client, MT9P031_PLL_CONTROL,
581+ MT9P031_PLL_CONTROL_PWRON |
582+ MT9P031_PLL_CONTROL_USEPLL);
583+ mdelay(1);
584+ return ret;
585+}
586+
587+static inline int mt9p031_pll_disable(struct i2c_client *client)
588+{
589+ return reg_write(client, MT9P031_PLL_CONTROL,
590+ MT9P031_PLL_CONTROL_PWROFF);
591+}
592+
593+static int mt9p031_s_stream(struct v4l2_subdev *sd, int enable)
594+{
595+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
596+ struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
597+ struct v4l2_rect rect = mt9p031->rect;
598+ u16 xskip = mt9p031->xskip;
599+ u16 yskip = mt9p031->yskip;
600+ int ret;
601+
602+ if (enable) {
603+ ret = mt9p031_set_params(client, &rect, xskip, yskip);
604+ if (ret < 0)
605+ return ret;
606+ /* Switch to master "normal" mode */
607+ ret = mt9p031_set_output_control(mt9p031, 0,
608+ MT9P031_OUTPUT_CONTROL_CEN);
609+ if (ret < 0)
610+ return ret;
611+ ret = mt9p031_pll_enable(client);
612+ } else {
613+ /* Stop sensor readout */
614+ ret = mt9p031_set_output_control(mt9p031,
615+ MT9P031_OUTPUT_CONTROL_CEN, 0);
616+ if (ret < 0)
617+ return ret;
618+ ret = mt9p031_pll_disable(client);
619+ }
620+ return ret;
621+}
622+
623+static int mt9p031_video_probe(struct i2c_client *client)
624+{
625+ s32 data;
626+
627+ /* Read out the chip version register */
628+ data = reg_read(client, MT9P031_CHIP_VERSION);
629+ if (data != MT9P031_CHIP_VERSION_VALUE) {
630+ dev_err(&client->dev,
631+ "No MT9P031 chip detected, register read %x\n", data);
632+ return -ENODEV;
633+ }
634+
635+ dev_info(&client->dev, "Detected a MT9P031 chip ID %x\n", data);
636+
637+ return 0;
638+}
639+
640+static int mt9p031_set_power(struct v4l2_subdev *sd, int on)
641+{
642+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
643+ int ret = 0;
644+
645+ mutex_lock(&mt9p031->power_lock);
646+
647+ /*
648+ * If the power count is modified from 0 to != 0 or from != 0 to 0,
649+ * update the power state.
650+ */
651+ if (mt9p031->power_count == !on) {
652+ if (on) {
653+ ret = mt9p031_power_on(mt9p031);
654+ if (ret) {
655+ dev_err(mt9p031->subdev.v4l2_dev->dev,
656+ "Failed to power on: %d\n", ret);
657+ goto out;
658+ }
659+ } else {
660+ mt9p031_power_off(mt9p031);
661+ }
662+ }
663+
664+ /* Update the power count. */
665+ mt9p031->power_count += on ? 1 : -1;
666+ WARN_ON(mt9p031->power_count < 0);
667+
668+out:
669+ mutex_unlock(&mt9p031->power_lock);
670+ return ret;
671+}
672+
673+static int mt9p031_registered(struct v4l2_subdev *sd)
674+{
675+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
676+ struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
677+ int ret;
678+
679+ ret = mt9p031_set_power(&mt9p031->subdev, 1);
680+ if (ret) {
681+ dev_err(&client->dev,
682+ "Failed to power on device: %d\n", ret);
683+ return ret;
684+ }
685+
686+ ret = mt9p031_video_probe(client);
687+
688+ mt9p031_set_power(&mt9p031->subdev, 0);
689+
690+ return ret;
691+}
692+
693+static int mt9p031_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
694+{
695+ struct mt9p031 *mt9p031;
696+ mt9p031 = container_of(sd, struct mt9p031, subdev);
697+
698+ mt9p031->rect.width = MT9P031_WINDOW_WIDTH_DEF;
699+ mt9p031->rect.height = MT9P031_WINDOW_HEIGHT_DEF;
700+ mt9p031->rect.left = MT9P031_COLUMN_START_DEF;
701+ mt9p031->rect.top = MT9P031_ROW_START_DEF;
702+
703+ if (mt9p031->pdata->version == MT9P031_MONOCHROME_VERSION)
704+ mt9p031->format.code = V4L2_MBUS_FMT_Y12_1X12;
705+ else
706+ mt9p031->format.code = V4L2_MBUS_FMT_SGRBG12_1X12;
707+
708+ mt9p031->format.width = MT9P031_WINDOW_WIDTH_DEF;
709+ mt9p031->format.height = MT9P031_WINDOW_HEIGHT_DEF;
710+ mt9p031->format.field = V4L2_FIELD_NONE;
711+ mt9p031->format.colorspace = V4L2_COLORSPACE_SRGB;
712+
713+ mt9p031->xskip = 1;
714+ mt9p031->yskip = 1;
715+ return mt9p031_set_power(sd, 1);
716+}
717+
718+static int mt9p031_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
719+{
720+ return mt9p031_set_power(sd, 0);
721+}
722+
723+static struct v4l2_subdev_core_ops mt9p031_subdev_core_ops = {
724+ .s_power = mt9p031_set_power,
725+};
726+
727+static struct v4l2_subdev_video_ops mt9p031_subdev_video_ops = {
728+ .s_stream = mt9p031_s_stream,
729+};
730+
731+static struct v4l2_subdev_pad_ops mt9p031_subdev_pad_ops = {
732+ .enum_mbus_code = mt9p031_enum_mbus_code,
733+ .get_fmt = mt9p031_get_format,
734+ .set_fmt = mt9p031_set_format,
735+ .get_crop = mt9p031_get_crop,
736+ .set_crop = mt9p031_set_crop,
737+};
738+
739+static struct v4l2_subdev_ops mt9p031_subdev_ops = {
740+ .core = &mt9p031_subdev_core_ops,
741+ .video = &mt9p031_subdev_video_ops,
742+ .pad = &mt9p031_subdev_pad_ops,
743+};
744+
745+static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
746+ .registered = mt9p031_registered,
747+ .open = mt9p031_open,
748+ .close = mt9p031_close,
749+};
750+
751+static int mt9p031_probe(struct i2c_client *client,
752+ const struct i2c_device_id *did)
753+{
754+ int ret;
755+ struct mt9p031 *mt9p031;
756+ struct mt9p031_platform_data *pdata = client->dev.platform_data;
757+ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
758+
759+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
760+ dev_warn(&adapter->dev,
761+ "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
762+ return -EIO;
763+ }
764+
765+ mt9p031 = kzalloc(sizeof(struct mt9p031), GFP_KERNEL);
766+ if (!mt9p031)
767+ return -ENOMEM;
768+
769+ mutex_init(&mt9p031->power_lock);
770+ v4l2_i2c_subdev_init(&mt9p031->subdev, client, &mt9p031_subdev_ops);
771+ mt9p031->subdev.internal_ops = &mt9p031_subdev_internal_ops;
772+
773+ mt9p031->pdata = pdata;
774+
775+ mt9p031->pad.flags = MEDIA_PAD_FL_SOURCE;
776+ ret = media_entity_init(&mt9p031->subdev.entity, 1, &mt9p031->pad, 0);
777+ if (ret)
778+ return ret;
779+
780+ mt9p031->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
781+
782+ return 0;
783+}
784+
785+static int mt9p031_remove(struct i2c_client *client)
786+{
787+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
788+ struct mt9p031 *mt9p031 = container_of(sd, struct mt9p031, subdev);
789+
790+ v4l2_device_unregister_subdev(sd);
791+ media_entity_cleanup(&sd->entity);
792+ kfree(mt9p031);
793+
794+ return 0;
795+}
796+
797+static const struct i2c_device_id mt9p031_id[] = {
798+ { "mt9p031", 0 },
799+ { }
800+};
801+MODULE_DEVICE_TABLE(i2c, mt9p031_id);
802+
803+static struct i2c_driver mt9p031_i2c_driver = {
804+ .driver = {
805+ .name = "mt9p031",
806+ },
807+ .probe = mt9p031_probe,
808+ .remove = mt9p031_remove,
809+ .id_table = mt9p031_id,
810+};
811+
812+static int __init mt9p031_mod_init(void)
813+{
814+ return i2c_add_driver(&mt9p031_i2c_driver);
815+}
816+
817+static void __exit mt9p031_mod_exit(void)
818+{
819+ i2c_del_driver(&mt9p031_i2c_driver);
820+}
821+
822+module_init(mt9p031_mod_init);
823+module_exit(mt9p031_mod_exit);
824+
825+MODULE_DESCRIPTION("Aptina MT9P031 Camera driver");
826+MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
827+MODULE_LICENSE("GPL v2");
828diff --git a/include/media/mt9p031.h b/include/media/mt9p031.h
829new file mode 100644
830index 0000000..27b4c75
831--- /dev/null
832+++ b/include/media/mt9p031.h
833@@ -0,0 +1,23 @@
834+#ifndef MT9P031_H
835+#define MT9P031_H
836+
837+struct v4l2_subdev;
838+
839+enum {
840+ MT9P031_COLOR_VERSION = 0,
841+ MT9P031_MONOCHROME_VERSION = 1,
842+};
843+
844+enum {
845+ MT9P031_VDD_IO_1V8 = 0,
846+ MT9P031_VDD_IO_2V8 = 1,
847+};
848+
849+struct mt9p031_platform_data {
850+ int (*set_xclk)(struct v4l2_subdev *subdev, int hz);
851+ int (*reset)(struct v4l2_subdev *subdev, int active);
852+ int vdd_io; /* MT9P031_VDD_IO_1V8 or MT9P031_VDD_IO_2V8 */
853+ int version; /* MT9P031_COLOR_VERSION or MT9P031_MONOCHROME_VERSION */
854+};
855+
856+#endif
857--
8581.6.6.1
859
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2024-05-28 22:18:45 +0000